* [PATCH 0/6] STM32F4 Add RTC & QSPI clocks
From: gabriel.fernandez at st.com @ 2016-09-30 14:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch-set introduce RTC and QSPI clocks for STM32F4 socs
RTC clock has 3 parents clock oscillators (lsi/lse/hse_rtc)
example to use rtc clock:
rtc: rtc at 40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
...
clocks = <&rcc 1 CLK_RTC>;
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
...
};
Gabriel Fernandez (6):
clk: stm32f4: Add LSI & LSE clocks
ARM: dts: stm32f429: add LSI and LSE clocks
arm: stmf32: Enable SYSCON
clk: stm32f4: Add RTC clock
clk: stm32f469: Add QSPI clock
ARM: dts: stm32f429: Add QSPI clock
.../devicetree/bindings/clock/st,stm32-rcc.txt | 4 +-
arch/arm/boot/dts/stm32f429.dtsi | 18 +
arch/arm/boot/dts/stm32f469-disco.dts | 4 +
arch/arm/configs/stm32_defconfig | 1 +
drivers/clk/clk-stm32f4.c | 450 ++++++++++++++++++++-
5 files changed, 455 insertions(+), 22 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH 1/6] clk: stm32f4: Add LSI & LSE clocks
From: gabriel.fernandez at st.com @ 2016-09-30 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475245509-6487-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch introduces the support of the LSI & LSE clocks.
The clock drivers needs to disable the power domain write protection
using syscon/regmap to enable these clocks.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 146 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 142 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 02d6810..f57e73c 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -19,10 +19,14 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
#define STM32F4_RCC_PLLCFGR 0x04
#define STM32F4_RCC_CFGR 0x08
@@ -31,6 +35,8 @@
#define STM32F4_RCC_AHB3ENR 0x38
#define STM32F4_RCC_APB1ENR 0x40
#define STM32F4_RCC_APB2ENR 0x44
+#define STM32F4_RCC_BDCR 0x70
+#define STM32F4_RCC_CSR 0x74
struct stm32f4_gate_data {
u8 offset;
@@ -39,6 +45,14 @@ struct stm32f4_gate_data {
const char *parent_name;
unsigned long flags;
};
+struct stm32f4_rgate_data {
+ u8 offset;
+ u8 bit_idx;
+ u8 bit_rdy_idx;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+};
static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
{ STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
@@ -120,13 +134,13 @@ static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
};
+enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, END_PRIMARY_CLK };
/*
* MAX_CLKS is the maximum value in the enumeration below plus the combined
* hweight of stm32f42xx_gate_map (plus one).
*/
-#define MAX_CLKS 74
+#define MAX_CLKS (71 + END_PRIMARY_CLK + 1)
-enum { SYSTICK, FCLK };
/*
* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
@@ -259,7 +273,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
u64 table[ARRAY_SIZE(stm32f42xx_gate_map)];
if (primary == 1) {
- if (WARN_ON(secondary > FCLK))
+ if (WARN_ON(secondary >= END_PRIMARY_CLK))
return -EINVAL;
return secondary;
}
@@ -276,7 +290,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
table[BIT_ULL_WORD(secondary)] &=
GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
- return FCLK + hweight64(table[0]) +
+ return END_PRIMARY_CLK - 1 + hweight64(table[0]) +
(BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
(BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
}
@@ -292,8 +306,110 @@ stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
return clks[i];
}
+static struct regmap *pdrm;
+
+static inline void disable_power_domain_write_protection(void)
+{
+ regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
+}
+
+static inline void enable_power_domain_write_protection(void)
+{
+ regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
+}
+
+struct stm32_rgate {
+ struct clk_hw hw;
+ struct clk_gate gate;
+ u8 bit_rdy_idx;
+};
+
+#define RTC_TIMEOUT 1000000
+
+#define to_rgclk(_hw) container_of(_hw, struct stm32_rgate, hw)
+
+static int rgclk_enable(struct clk_hw *hw)
+{
+ struct stm32_rgate *rgate = to_rgclk(hw);
+ struct clk_hw *gate_hw = &rgate->gate.hw;
+ struct clk_gate *gate = to_clk_gate(gate_hw);
+ u32 reg;
+ int ret;
+
+ __clk_hw_set_clk(gate_hw, hw);
+
+ disable_power_domain_write_protection();
+
+ clk_gate_ops.enable(gate_hw);
+
+ ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg,
+ reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT);
+
+ enable_power_domain_write_protection();
+
+ return ret;
+}
+
+static void rgclk_disable(struct clk_hw *hw)
+{
+ clk_gate_ops.disable(hw);
+}
+
+static int rgclk_is_enabled(struct clk_hw *hw)
+{
+ return clk_gate_ops.is_enabled(hw);
+}
+
+
+static const struct clk_ops rgclk_ops = {
+ .enable = rgclk_enable,
+ .disable = rgclk_disable,
+ .is_enabled = rgclk_is_enabled,
+};
+
+static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ struct stm32_rgate *rgate;
+ struct clk_init_data init = { NULL };
+ struct clk_hw *hw;
+ int ret;
+
+ rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
+ if (!rgate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &rgclk_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ rgate->hw.init = &init;
+ rgate->bit_rdy_idx = bit_rdy_idx;
+
+ rgate->gate.lock = lock;
+ rgate->gate.reg = reg;
+ rgate->gate.bit_idx = bit_idx;
+
+ hw = &rgate->hw;
+ ret = clk_hw_register(dev, hw);
+ if (ret) {
+ kfree(rgate);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
+
static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
+const char *rtc_parents[4] = {
+ "no-clock", "lse", "lsi", "hse-rtc"
+};
+
static const struct clk_div_table ahb_div_table[] = {
{ 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
{ 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
@@ -319,6 +435,12 @@ static void __init stm32f4_rcc_init(struct device_node *np)
return;
}
+ pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+ if (IS_ERR(pdrm)) {
+ pr_err("%s: Unable to get syscfg\n", __func__);
+ goto fail;
+ }
+
hse_clk = of_clk_get_parent_name(np, 0);
clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
@@ -371,6 +493,22 @@ static void __init stm32f4_rcc_init(struct device_node *np)
}
}
+ clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
+ base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock);
+
+ if (IS_ERR(clks[CLK_LSI])) {
+ pr_err("Unable to register lsi clock\n");
+ goto fail;
+ }
+
+ clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
+ base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock);
+
+ if (IS_ERR(clks[CLK_LSE])) {
+ pr_err("Unable to register lse clock\n");
+ goto fail;
+ }
+
of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
return;
fail:
--
1.9.1
^ permalink raw reply related
* [PATCH 2/6] ARM: dts: stm32f429: add LSI and LSE clocks
From: gabriel.fernandez at st.com @ 2016-09-30 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475245509-6487-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch adds lsi / lse oscillators. These clocks can be use by
RTC clocks.
The clock drivers needs to disable the power domain write protection using
syscon / regmap to enable these clocks.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..0979fb6 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -55,6 +55,18 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
+
+ clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
};
soc {
@@ -176,6 +188,11 @@
reg = <0x40013800 0x400>;
};
+ pwrcfg: power-config at 40007000 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
@@ -330,6 +347,7 @@
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
+ st,syscfg = <&pwrcfg>;
};
dma1: dma-controller at 40026000 {
--
1.9.1
^ permalink raw reply related
* [PATCH 3/6] arm: stmf32: Enable SYSCON
From: gabriel.fernandez at st.com @ 2016-09-30 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475245509-6487-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
The clock drivers needs to disable the power domain write protection
using syscon/regmap to enable RTC clock.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 08786d8..f3b1ea5 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -49,6 +49,7 @@ CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
+CONFIG_MFD_SYSCON=y
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
--
1.9.1
^ permalink raw reply related
* [PATCH 4/6] clk: stm32f4: Add RTC clock
From: gabriel.fernandez at st.com @ 2016-09-30 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475245509-6487-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch introduces the support of the RTC clock.
RTC clock can have 3 sources: lsi, lse and hse_rtc.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 135 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 134 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index f57e73c..6e26d39 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -134,7 +134,7 @@ static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
};
-enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, END_PRIMARY_CLK };
+enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC, END_PRIMARY_CLK };
/*
* MAX_CLKS is the maximum value in the enumeration below plus the combined
* hweight of stm32f42xx_gate_map (plus one).
@@ -318,6 +318,15 @@ static inline void enable_power_domain_write_protection(void)
regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
}
+static inline void sofware_reset_backup_domain(void)
+{
+ unsigned long val;
+
+ val = readl(base + STM32F4_RCC_BDCR);
+ writel(val |= (1 << 16), base + STM32F4_RCC_BDCR);
+ writel(val & ~(1 << 16), base + STM32F4_RCC_BDCR);
+}
+
struct stm32_rgate {
struct clk_hw hw;
struct clk_gate gate;
@@ -404,6 +413,113 @@ static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
return hw;
}
+static int cclk_gate_enable(struct clk_hw *hw)
+{
+ int ret;
+
+ disable_power_domain_write_protection();
+
+ ret = clk_gate_ops.enable(hw);
+
+ enable_power_domain_write_protection();
+
+ return ret;
+}
+
+static void cclk_gate_disable(struct clk_hw *hw)
+{
+ disable_power_domain_write_protection();
+
+ clk_gate_ops.disable(hw);
+
+ enable_power_domain_write_protection();
+}
+
+static int cclk_gate_is_enabled(struct clk_hw *hw)
+{
+ return clk_gate_ops.is_enabled(hw);
+}
+
+static const struct clk_ops cclk_gate_ops = {
+ .enable = cclk_gate_enable,
+ .disable = cclk_gate_disable,
+ .is_enabled = cclk_gate_is_enabled,
+};
+
+static u8 cclk_mux_get_parent(struct clk_hw *hw)
+{
+ return clk_mux_ops.get_parent(hw);
+}
+
+
+static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ int ret;
+
+ disable_power_domain_write_protection();
+
+ sofware_reset_backup_domain();
+
+ ret = clk_mux_ops.set_parent(hw, index);
+
+ enable_power_domain_write_protection();
+
+ return ret;
+}
+
+
+static const struct clk_ops cclk_mux_ops = {
+ .get_parent = cclk_mux_get_parent,
+ .set_parent = cclk_mux_set_parent,
+};
+
+static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
+ const char * const *parent_names, int num_parents,
+ void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
+ spinlock_t *lock)
+{
+ struct clk_hw *hw;
+ struct clk_gate *gate;
+ struct clk_mux *mux;
+
+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+ if (!gate) {
+ hw = ERR_PTR(-EINVAL);
+ goto fail;
+ }
+
+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
+ if (!mux) {
+ kfree(gate);
+ hw = ERR_PTR(-EINVAL);
+ goto fail;
+ }
+
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->flags = 0;
+ gate->lock = lock;
+
+ mux->reg = reg;
+ mux->shift = shift;
+ mux->mask = 3;
+ mux->flags = 0;
+
+ hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
+ &mux->hw, &cclk_mux_ops,
+ NULL, NULL,
+ &gate->hw, &cclk_gate_ops,
+ flags);
+
+ if (IS_ERR(hw)) {
+ kfree(gate);
+ kfree(mux);
+ }
+
+fail:
+ return hw;
+}
+
static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
const char *rtc_parents[4] = {
@@ -509,6 +625,23 @@ static void __init stm32f4_rcc_init(struct device_node *np)
goto fail;
}
+ clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
+ 0, base + STM32F4_RCC_CFGR, 16, 5, 0,
+ &stm32f4_clk_lock);
+
+ if (IS_ERR(clks[CLK_HSE_RTC])) {
+ pr_err("Unable to register hse-rtc clock\n");
+ goto fail;
+ }
+
+ clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
+ base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
+
+ if (IS_ERR(clks[CLK_RTC])) {
+ pr_err("Unable to register rtc clock\n");
+ goto fail;
+ }
+
of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
return;
fail:
--
1.9.1
^ permalink raw reply related
* [PATCH 5/6] clk: stm32f469: Add QSPI clock
From: gabriel.fernandez at st.com @ 2016-09-30 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475245509-6487-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch adds the QSPI clock for stm32f469 discovery board.
The gate mapping is a little bit different from stm32f429 soc.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
.../devicetree/bindings/clock/st,stm32-rcc.txt | 4 +-
drivers/clk/clk-stm32f4.c | 173 ++++++++++++++++++---
2 files changed, 158 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
index fee3205..eace3de 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
@@ -8,7 +8,9 @@ Please also refer to clock-bindings.txt in this directory for common clock
controller binding usage.
Required properties:
-- compatible: Should be "st,stm32f42xx-rcc"
+- compatible: Should be:
+ "st,stm32f42xx-rcc"
+ "st,stm32f46xx-rcc"
- reg: should be register base and length as documented in the
datasheet
- #clock-cells: 2, device nodes should specify the clock in their "clocks"
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 6e26d39..bc75d83 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -54,7 +54,7 @@ struct stm32f4_rgate_data {
unsigned long flags;
};
-static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
+static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
{ STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
{ STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
{ STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
@@ -134,23 +134,109 @@ static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
};
+static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
+ { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
+
+ { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
+ { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
+ { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
+ { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
+ { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
+
+ { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
+ CLK_IGNORE_UNUSED },
+ { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
+ CLK_IGNORE_UNUSED },
+
+ { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
+
+ { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
+ { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
+};
+
enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC, END_PRIMARY_CLK };
-/*
- * MAX_CLKS is the maximum value in the enumeration below plus the combined
- * hweight of stm32f42xx_gate_map (plus one).
- */
-#define MAX_CLKS (71 + END_PRIMARY_CLK + 1)
/*
* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
* have gate bits associated with them. Its combined hweight is 71.
*/
-static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ffull,
- 0x0000000000000001ull,
- 0x04777f33f6fec9ffull };
+#define MAX_GATE_MAP 3
+
+static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
+ 0x0000000000000001ull,
+ 0x04777f33f6fec9ffull };
+
+static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
+ 0x0000000000000003ull,
+ 0x0c777f33f6fec9ffull };
+
+const u64 *stm32f4_gate_map;
+
+static struct clk_hw **clks;
-static struct clk_hw *clks[MAX_CLKS];
static DEFINE_SPINLOCK(stm32f4_clk_lock);
static void __iomem *base;
@@ -270,7 +356,7 @@ static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk)
*/
static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
{
- u64 table[ARRAY_SIZE(stm32f42xx_gate_map)];
+ u64 table[MAX_GATE_MAP];
if (primary == 1) {
if (WARN_ON(secondary >= END_PRIMARY_CLK))
@@ -278,7 +364,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
return secondary;
}
- memcpy(table, stm32f42xx_gate_map, sizeof(table));
+ memcpy(table, stm32f4_gate_map, sizeof(table));
/* only bits set in table can be used as indices */
if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
@@ -540,10 +626,42 @@ static const struct clk_div_table apb_div_table[] = {
{ 0 },
};
+struct stm32f4_clk_data {
+ const struct stm32f4_gate_data *gates_data;
+ const u64 *gates_map;
+ int gates_num;
+};
+
+static const struct stm32f4_clk_data stm32f429_clk_data = {
+ .gates_data = stm32f429_gates,
+ .gates_map = stm32f42xx_gate_map,
+ .gates_num = ARRAY_SIZE(stm32f429_gates),
+};
+
+static const struct stm32f4_clk_data stm32f469_clk_data = {
+ .gates_data = stm32f469_gates,
+ .gates_map = stm32f46xx_gate_map,
+ .gates_num = ARRAY_SIZE(stm32f469_gates),
+};
+
+static const struct of_device_id stm32f4_of_match[] = {
+ {
+ .compatible = "st,stm32f42xx-rcc",
+ .data = &stm32f429_clk_data
+ },
+ {
+ .compatible = "st,stm32f46xx-rcc",
+ .data = &stm32f469_clk_data
+ },
+ {}
+};
+
static void __init stm32f4_rcc_init(struct device_node *np)
{
const char *hse_clk;
int n;
+ const struct of_device_id *match;
+ const struct stm32f4_clk_data *data;
base = of_iomap(np, 0);
if (!base) {
@@ -557,6 +675,19 @@ static void __init stm32f4_rcc_init(struct device_node *np)
goto fail;
}
+ match = of_match_node(stm32f4_of_match, np);
+ if (WARN_ON(!match))
+ return;
+
+ data = match->data;
+
+ clks = kmalloc_array(data->gates_num + END_PRIMARY_CLK,
+ sizeof(struct clk_hw *), GFP_KERNEL);
+ if (!clks)
+ goto fail;
+
+ stm32f4_gate_map = data->gates_map;
+
hse_clk = of_clk_get_parent_name(np, 0);
clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
@@ -589,11 +720,15 @@ static void __init stm32f4_rcc_init(struct device_node *np)
clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
0, 1, 1);
- for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) {
- const struct stm32f4_gate_data *gd = &stm32f4_gates[n];
- unsigned int secondary =
- 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx;
- int idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
+ for (n = 0; n < data->gates_num; n++) {
+ const struct stm32f4_gate_data *gd;
+ unsigned int secondary;
+ int idx;
+
+ gd = (struct stm32f4_gate_data *) &data->gates_data[n];
+ secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
+ gd->bit_idx;
+ idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
if (idx < 0)
goto fail;
@@ -645,6 +780,8 @@ static void __init stm32f4_rcc_init(struct device_node *np)
of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
return;
fail:
+ kfree(clks);
iounmap(base);
}
-CLK_OF_DECLARE(stm32f4_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
+CLK_OF_DECLARE(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
+CLK_OF_DECLARE(stm32f46xx_rcc, "st,stm32f46xx-rcc", stm32f4_rcc_init);
--
1.9.1
^ permalink raw reply related
* [PATCH 6/6] ARM: dts: stm32f429: Add QSPI clock
From: gabriel.fernandez at st.com @ 2016-09-30 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475245509-6487-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch adds the QSPI clock for stm32f469 discovery board.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
arch/arm/boot/dts/stm32f469-disco.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index cb55ac8..80aecc0 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -66,6 +66,10 @@
};
};
+&rcc {
+ compatible = "st,stm32f46xx-rcc", "st,stm32-rcc";
+};
+
&clk_hse {
clock-frequency = <8000000>;
};
--
1.9.1
^ permalink raw reply related
* [PATCH] drm/sun4i: Check that the plane coordinates are not negative
From: Maxime Ripard @ 2016-09-30 14:33 UTC (permalink / raw)
To: linux-arm-kernel
Our planes cannot be set at negative coordinates. Make sure we reject such
configuration.
Reported-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/gpu/drm/sun4i/sun4i_layer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c
index f0035bf5efea..f5463c4c2cde 100644
--- a/drivers/gpu/drm/sun4i/sun4i_layer.c
+++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
@@ -29,6 +29,9 @@ struct sun4i_plane_desc {
static int sun4i_backend_layer_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
+ if ((state->crtc_x < 0) || (state->crtc_y < 0))
+ return -EINVAL;
+
return 0;
}
--
2.9.3
^ permalink raw reply related
* No subject
From: Maxime Ripard @ 2016-09-30 14:37 UTC (permalink / raw)
To: linux-arm-kernel
Subject: [PATCH v5 0/5] drm: Add Support for Passive RGB to VGA bridges
Hi,
This serie is about adding support for the RGB to VGA bridge found in
the A13-Olinuxino and the CHIP VGA adapter.
Both these boards rely on an entirely passive bridge made out of
resitor ladders that do not require any initialisation. The only thing
needed is to get the timings from the screen if available (and if not,
fall back on XGA standards), set up the display pipeline to output on
the RGB bus with the proper timings, and you're done.
This serie also fixes a bunch of bugs uncovered when trying to
increase the resolution, and hence the pixel clock, of our
pipeline. It also fixes a few bugs in the DRM driver itself that went
unnoticed before.
Let me know what you think,
Maxime
Changes from v4:
- Removed unused functions
Changes from v3:
- Depends on OF in Kconfig
- Fixed typos in the driver comments
- Removed the mention of a "passive" bridge in the bindings doc
- Made the strcuture const
- Removed the nops and best_encoders implementations
- Removed the call to drm_bridge_enable in the sun4i driver
Changes from v2:
- Changed the compatible as suggested
- Rebased on top 4.8
Changes from v1:
- Switch to using a vga-connector
- Use drm_encoder bridge pointer instead of doing our own
- Report the connector status as unknown instead of connected by
default, and as connected only if we can retrieve the EDID.
- Switch to of_i2c_get_adapter by node, and put the reference when done
- Rebased on linux-next
Maxime Ripard (5):
drm/sun4i: rgb: Remove the bridge enable/disable functions
drm/bridge: Add RGB to VGA bridge support
ARM: sun5i: a13-olinuxino: Enable VGA bridge
ARM: multi_v7: enable VGA bridge
ARM: sunxi: Enable VGA bridge
.../bindings/display/bridge/rgb-to-vga-bridge.txt | 48 +++++
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 54 +++++
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/sunxi_defconfig | 1 +
drivers/gpu/drm/bridge/Kconfig | 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/rgb-to-vga.c | 229 +++++++++++++++++++++
drivers/gpu/drm/sun4i/sun4i_rgb.c | 6 -
8 files changed, 341 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/rgb-to-vga-bridge.txt
create mode 100644 drivers/gpu/drm/bridge/rgb-to-vga.c
--
2.9.3
^ permalink raw reply
* [PATCH v5 1/5] drm/sun4i: rgb: Remove the bridge enable/disable functions
From: Maxime Ripard @ 2016-09-30 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930143709.1388-1-maxime.ripard@free-electrons.com>
The atomic helpers already call the drm_bridge_enable on our behalf,
there's no need to do it a second time.
Reported-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index 4e4bea6f395c..d198ad7e5323 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -155,9 +155,6 @@ static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
if (!IS_ERR(tcon->panel))
drm_panel_prepare(tcon->panel);
- /* encoder->bridge can be NULL; drm_bridge_enable checks for it */
- drm_bridge_enable(encoder->bridge);
-
sun4i_tcon_channel_enable(tcon, 0);
if (!IS_ERR(tcon->panel))
@@ -177,9 +174,6 @@ static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
sun4i_tcon_channel_disable(tcon, 0);
- /* encoder->bridge can be NULL; drm_bridge_disable checks for it */
- drm_bridge_disable(encoder->bridge);
-
if (!IS_ERR(tcon->panel))
drm_panel_unprepare(tcon->panel);
}
--
2.9.3
^ permalink raw reply related
* [PATCH v5 2/5] drm/bridge: Add RGB to VGA bridge support
From: Maxime Ripard @ 2016-09-30 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930143709.1388-1-maxime.ripard@free-electrons.com>
Some boards have an entirely passive RGB to VGA bridge, based on either
DACs or resistor ladders.
Those might or might not have an i2c bus routed to the VGA connector in
order to access the screen EDIDs.
Add a bridge that doesn't do anything but expose the modes available on the
screen, either based on the EDIDs if available, or based on the XGA
standards.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
.../bindings/display/bridge/rgb-to-vga-bridge.txt | 48 +++++
drivers/gpu/drm/bridge/Kconfig | 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/rgb-to-vga.c | 229 +++++++++++++++++++++
4 files changed, 285 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/rgb-to-vga-bridge.txt
create mode 100644 drivers/gpu/drm/bridge/rgb-to-vga.c
diff --git a/Documentation/devicetree/bindings/display/bridge/rgb-to-vga-bridge.txt b/Documentation/devicetree/bindings/display/bridge/rgb-to-vga-bridge.txt
new file mode 100644
index 000000000000..a8375bc1f9cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/rgb-to-vga-bridge.txt
@@ -0,0 +1,48 @@
+Dumb RGB to VGA bridge
+----------------------
+
+This binding is aimed for dumb RGB to VGA bridges that do not require
+any configuration.
+
+Required properties:
+
+- compatible: Must be "rgb-to-vga-bridge"
+
+Required nodes:
+
+This device has two video ports. Their connections are modeled using the OF
+graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for RGB input
+- Video port 1 for VGA output
+
+
+Example
+-------
+
+bridge {
+ compatible = "rgb-to-vga-bridge";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&tcon0_out_vga>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+};
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index b590e678052d..d690398c541c 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -17,6 +17,13 @@ config DRM_ANALOGIX_ANX78XX
the HDMI output of an application processor to MyDP
or DisplayPort.
+config DRM_RGB_TO_VGA
+ tristate "Dumb RGB to VGA Bridge support"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Support for passive RGB to VGA bridges
+
config DRM_DW_HDMI
tristate
select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index efdb07e878f5..3bb8cbe09fe9 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,6 +1,7 @@
ccflags-y := -Iinclude/drm
obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
+obj-$(CONFIG_DRM_RGB_TO_VGA) += rgb-to-vga.o
obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
diff --git a/drivers/gpu/drm/bridge/rgb-to-vga.c b/drivers/gpu/drm/bridge/rgb-to-vga.c
new file mode 100644
index 000000000000..5ff4d4f3598f
--- /dev/null
+++ b/drivers/gpu/drm/bridge/rgb-to-vga.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2015-2016 Free Electrons
+ * Copyright (C) 2015-2016 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/of_graph.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+
+struct dumb_vga {
+ struct drm_bridge bridge;
+ struct drm_connector connector;
+
+ struct i2c_adapter *ddc;
+};
+
+static inline struct dumb_vga *
+drm_bridge_to_dumb_vga(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct dumb_vga, bridge);
+}
+
+static inline struct dumb_vga *
+drm_connector_to_dumb_vga(struct drm_connector *connector)
+{
+ return container_of(connector, struct dumb_vga, connector);
+}
+
+static int dumb_vga_get_modes(struct drm_connector *connector)
+{
+ struct dumb_vga *vga = drm_connector_to_dumb_vga(connector);
+ struct edid *edid;
+ int ret;
+
+ if (IS_ERR(vga->ddc))
+ goto fallback;
+
+ edid = drm_get_edid(connector, vga->ddc);
+ if (!edid) {
+ DRM_INFO("EDID readout failed, falling back to standard modes\n");
+ goto fallback;
+ }
+
+ drm_mode_connector_update_edid_property(connector, edid);
+ return drm_add_edid_modes(connector, edid);
+
+fallback:
+ /*
+ * In case we cannot retrieve the EDIDs (broken or missing i2c
+ * bus), fallback on the XGA standards
+ */
+ ret = drm_add_modes_noedid(connector, 1920, 1200);
+
+ /* And prefer a mode pretty much anyone can handle */
+ drm_set_preferred_mode(connector, 1024, 768);
+
+ return ret;
+}
+
+static const struct drm_connector_helper_funcs dumb_vga_con_helper_funcs = {
+ .get_modes = dumb_vga_get_modes,
+};
+
+static enum drm_connector_status
+dumb_vga_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct dumb_vga *vga = drm_connector_to_dumb_vga(connector);
+
+ /*
+ * Even if we have an I2C bus, we can't assume that the cable
+ * is disconnected if drm_probe_ddc fails. Some cables don't
+ * wire the DDC pins, or the I2C bus might not be working at
+ * all.
+ */
+ if (!IS_ERR(vga->ddc) && drm_probe_ddc(vga->ddc))
+ return connector_status_connected;
+
+ return connector_status_unknown;
+}
+
+static void
+dumb_vga_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs dumb_vga_con_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .detect = dumb_vga_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = dumb_vga_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int dumb_vga_attach(struct drm_bridge *bridge)
+{
+ struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
+ int ret;
+
+ if (!bridge->encoder) {
+ DRM_ERROR("Missing encoder\n");
+ return -ENODEV;
+ }
+
+ drm_connector_helper_add(&vga->connector,
+ &dumb_vga_con_helper_funcs);
+ ret = drm_connector_init(bridge->dev, &vga->connector,
+ &dumb_vga_con_funcs, DRM_MODE_CONNECTOR_VGA);
+ if (ret) {
+ DRM_ERROR("Failed to initialize connector\n");
+ return ret;
+ }
+
+ drm_mode_connector_attach_encoder(&vga->connector,
+ bridge->encoder);
+
+ return 0;
+}
+
+static const struct drm_bridge_funcs dumb_vga_bridge_funcs = {
+ .attach = dumb_vga_attach,
+};
+
+static struct i2c_adapter *dumb_vga_retrieve_ddc(struct device *dev)
+{
+ struct device_node *end_node, *phandle, *remote;
+ struct i2c_adapter *ddc;
+
+ end_node = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
+ if (!end_node) {
+ dev_err(dev, "Missing connector endpoint\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ remote = of_graph_get_remote_port_parent(end_node);
+ of_node_put(end_node);
+ if (!remote) {
+ dev_err(dev, "Enable to parse remote node\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0);
+ of_node_put(remote);
+ if (!phandle)
+ return ERR_PTR(-ENODEV);
+
+ ddc = of_get_i2c_adapter_by_node(phandle);
+ of_node_put(phandle);
+ if (!ddc)
+ return ERR_PTR(-EPROBE_DEFER);
+
+ return ddc;
+}
+
+static int dumb_vga_probe(struct platform_device *pdev)
+{
+ struct dumb_vga *vga;
+ int ret;
+
+ vga = devm_kzalloc(&pdev->dev, sizeof(*vga), GFP_KERNEL);
+ if (!vga)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, vga);
+
+ vga->ddc = dumb_vga_retrieve_ddc(&pdev->dev);
+ if (IS_ERR(vga->ddc)) {
+ if (PTR_ERR(vga->ddc) == -ENODEV) {
+ dev_info(&pdev->dev,
+ "No i2c bus specified... Disabling EDID readout\n");
+ } else {
+ dev_err(&pdev->dev, "Couldn't retrieve i2c bus\n");
+ return PTR_ERR(vga->ddc);
+ }
+ }
+
+ vga->bridge.funcs = &dumb_vga_bridge_funcs;
+ vga->bridge.of_node = pdev->dev.of_node;
+
+ ret = drm_bridge_add(&vga->bridge);
+ if (ret && !IS_ERR(vga->ddc))
+ i2c_put_adapter(vga->ddc);
+
+ return ret;
+}
+
+static int dumb_vga_remove(struct platform_device *pdev)
+{
+ struct dumb_vga *vga = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&vga->bridge);
+
+ if (!IS_ERR(vga->ddc))
+ i2c_put_adapter(vga->ddc);
+
+ return 0;
+}
+
+static const struct of_device_id dumb_vga_match[] = {
+ { .compatible = "rgb-to-vga-bridge" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, dumb_vga_match);
+
+struct platform_driver dumb_vga_driver = {
+ .probe = dumb_vga_probe,
+ .remove = dumb_vga_remove,
+ .driver = {
+ .name = "rgb-to-vga-bridge",
+ .of_match_table = dumb_vga_match,
+ },
+};
+module_platform_driver(dumb_vga_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
+MODULE_DESCRIPTION("Dumb RGB to VGA bridge driver");
+MODULE_LICENSE("GPL");
--
2.9.3
^ permalink raw reply related
* [PATCH v5 3/5] ARM: sun5i: a13-olinuxino: Enable VGA bridge
From: Maxime Ripard @ 2016-09-30 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930143709.1388-1-maxime.ripard@free-electrons.com>
Now that we have support for the VGA bridges using our DRM driver, enable
the display engine for the Olimex A13-Olinuxino.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 54 +++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index b3c234c65ea1..01ce7ea9032d 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -72,6 +72,47 @@
default-state = "on";
};
};
+
+ bridge {
+ compatible = "rgb-to-vga-bridge";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&tcon0_out_vga>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+};
+
+&be0 {
+ status = "okay";
};
&ehci0 {
@@ -211,6 +252,19 @@
status = "okay";
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_vga: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vga_bridge_in>;
+ };
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
--
2.9.3
^ permalink raw reply related
* [PATCH v5 4/5] ARM: multi_v7: enable VGA bridge
From: Maxime Ripard @ 2016-09-30 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930143709.1388-1-maxime.ripard@free-electrons.com>
Enable the RGB to VGA bridge driver in the defconfig
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2c8665cd9dc5..22ef41afc658 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -567,6 +567,7 @@ CONFIG_DRM=y
CONFIG_DRM_I2C_ADV7511=m
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
+CONFIG_DRM_RGB_TO_VGA=m
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
CONFIG_DRM_NOUVEAU=m
--
2.9.3
^ permalink raw reply related
* [PATCH v5 5/5] ARM: sunxi: Enable VGA bridge
From: Maxime Ripard @ 2016-09-30 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930143709.1388-1-maxime.ripard@free-electrons.com>
Enable the VGA bridge used on the A13-Olinuxino in the sunxi defconfig
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 714da336ec86..d830e258db59 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -98,6 +98,7 @@ CONFIG_MEDIA_RC_SUPPORT=y
CONFIG_RC_DEVICES=y
CONFIG_IR_SUNXI=y
CONFIG_DRM=y
+CONFIG_DRM_RGB_TO_VGA=y
CONFIG_DRM_SUN4I=y
CONFIG_FB=y
CONFIG_FB_SIMPLE=y
--
2.9.3
^ permalink raw reply related
* [PATCH 0/3] Support userspace irqchip with arch timers
From: Alexander Graf @ 2016-09-30 14:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160927190806.22988-1-christoffer.dall@linaro.org>
On 27.09.16 21:08, Christoffer Dall wrote:
> Hi Alex,
>
> Marc and I have been looking at this during Linaro connect and have
> slightly reworked your patch into this small series.
>
> It would be good if you could have a look at it and test it out.
>
> I've tested it with your QEMU, and it works for UP, but secondary CPUs
> fail to come up, and it looks like the kernel never gets an IPI for
> those CPUs from userspace. Any chance you're willing to take a look at
> that?
I still need to see whether I can come up with a prettier solution, but
for now this works:
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index f1ad805..8b9a084 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -2393,7 +2393,11 @@ static int kvm_get_mp_state(X86CPU *cpu)
return ret;
}
env->mp_state = mp_state.mp_state;
+#ifdef CONFIG_ARM
+ if (kvm_enabled()) {
+#else
if (kvm_irqchip_in_kernel()) {
+#endif
cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
}
return 0;
Alex
^ permalink raw reply related
* [PATCH 6/6] ARM: da850: adjust memory settings for tilcdc
From: Bartosz Golaszewski @ 2016-09-30 15:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4e089d20-d00f-ff54-7c54-85aa061e23c2@ti.com>
2016-09-30 14:59 GMT+02:00 Peter Ujfalusi <peter.ujfalusi@ti.com>:
> On 09/29/16 19:31, Bartosz Golaszewski wrote:
>> Default memory settings of da850 do not meet the throughput/latency
>> requirements of tilcdc. This results in the image displayed being
>> incorrect and the following warning being displayed by the LCDC
>> drm driver:
>>
>> tilcdc da8xx_lcdc.0: tilcdc_crtc_irq(0x00000020): FIFO underfow
>>
>> Reconfigure the LCDC priority to the highest. This is a workaround
>> for the da850-lcdk board which has the LCD controller enabled in
>> the device tree, but a long-term, system-wide fix is needed for
>> all davinci boards.
>>
>> This patch has been modified for mainline linux. It comes from a
>> downstream TI release for da850[1].
>>
>> Original author: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
>>
[snip]
>
> Is this safe to do for all da850 boards (to change PR_OLD_COUNT from 0xff to
> 0x20)? Most probably it is, but this setting has nothing to do with LCDC.
>
> The whole priority configuration has nothing to do with the LCDC, it is a
> system level priority.
>
> Now you have lowered the eDMA3_0-TPTC0/1 priority. Audio is serviced by
> eDMA3_0-TPTC1. So are we going to see issues in audio if LCDC is taking the
> highest priority?
>
Just ran a quick test with speaker-test -c2 -twav. Besides the fact
that the left and right channels are inverted (I'm looking into that),
I didn't notice any problems. Even at 1024x768 resolution, playing
audio at the same time seems to work fine.
Best regards,
Bartosz Golaszewski
^ permalink raw reply
* [PATCH 0/3] Support userspace irqchip with arch timers
From: Alexander Graf @ 2016-09-30 15:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <de375a6e-095c-a17a-0db7-876a5619df42@suse.de>
On 30.09.16 16:54, Alexander Graf wrote:
>
>
> On 27.09.16 21:08, Christoffer Dall wrote:
>> Hi Alex,
>>
>> Marc and I have been looking at this during Linaro connect and have
>> slightly reworked your patch into this small series.
>>
>> It would be good if you could have a look at it and test it out.
>>
>> I've tested it with your QEMU, and it works for UP, but secondary CPUs
>> fail to come up, and it looks like the kernel never gets an IPI for
>> those CPUs from userspace. Any chance you're willing to take a look at
>> that?
>
> I still need to see whether I can come up with a prettier solution, but
> for now this works:
>
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
Eh, no, not in i386 code :). But the problem seems to be a missing
mpstate sync.
Alex
^ permalink raw reply
* [PATCH 0/3] Support userspace irqchip with arch timers
From: Christoffer Dall @ 2016-09-30 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3e85d538-2539-f190-0d17-a2ecfe7b48ce@suse.de>
On Fri, Sep 30, 2016 at 05:38:11PM +0200, Alexander Graf wrote:
>
>
> On 30.09.16 16:54, Alexander Graf wrote:
> >
> >
> > On 27.09.16 21:08, Christoffer Dall wrote:
> >> Hi Alex,
> >>
> >> Marc and I have been looking at this during Linaro connect and have
> >> slightly reworked your patch into this small series.
> >>
> >> It would be good if you could have a look at it and test it out.
> >>
> >> I've tested it with your QEMU, and it works for UP, but secondary CPUs
> >> fail to come up, and it looks like the kernel never gets an IPI for
> >> those CPUs from userspace. Any chance you're willing to take a look at
> >> that?
> >
> > I still need to see whether I can come up with a prettier solution, but
> > for now this works:
> >
> > diff --git a/target-i386/kvm.c b/target-i386/kvm.c
>
> Eh, no, not in i386 code :). But the problem seems to be a missing
> mpstate sync.
>
Yeah, that looked really dodgy. Have you tested it? :)
-Christoffer
^ permalink raw reply
* [PATCH v5 01/14] drivers: iommu: add FWNODE_IOMMU fwnode type
From: Rafael J. Wysocki @ 2016-09-30 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930090702.GA7725@red-moon>
On Fri, Sep 30, 2016 at 11:07 AM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> On Thu, Sep 29, 2016 at 10:59:40PM +0200, Rafael J. Wysocki wrote:
>> On Thursday, September 29, 2016 03:15:20 PM Lorenzo Pieralisi wrote:
>> > Hi Rafael,
>> >
>> > On Fri, Sep 09, 2016 at 03:23:30PM +0100, Lorenzo Pieralisi wrote:
>> > > On systems booting with a device tree, every struct device is
>> > > associated with a struct device_node, that represents its DT
>> > > representation. The device node can be used in generic kernel
>> > > contexts (eg IRQ translation, IOMMU streamid mapping), to
>> > > retrieve the properties associated with the device and carry
>> > > out kernel operation accordingly. Owing to the 1:1 relationship
>> > > between the device and its device_node, the device_node can also
>> > > be used as a look-up token for the device (eg looking up a device
>> > > through its device_node), to retrieve the device in kernel paths
>> > > where the device_node is available.
>> > >
>> > > On systems booting with ACPI, the same abstraction provided by
>> > > the device_node is required to provide look-up functionality.
>> > >
>> > > Therefore, mirroring the approach implemented in the IRQ domain
>> > > kernel layer, this patch adds an additional fwnode type FWNODE_IOMMU.
>> > >
>> > > This patch also implements a glue kernel layer that allows to
>> > > allocate/free FWNODE_IOMMU fwnode_handle structures and associate
>> > > them with IOMMU devices.
>> > >
>> > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> > > Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
>> > > Cc: Joerg Roedel <joro@8bytes.org>
>> > > Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
>> > > ---
>> > > include/linux/fwnode.h | 1 +
>> > > include/linux/iommu.h | 25 +++++++++++++++++++++++++
>> > > 2 files changed, 26 insertions(+)
>> > >
>> > > diff --git a/include/linux/fwnode.h b/include/linux/fwnode.h
>> > > index 8516717..6e10050 100644
>> > > --- a/include/linux/fwnode.h
>> > > +++ b/include/linux/fwnode.h
>> > > @@ -19,6 +19,7 @@ enum fwnode_type {
>> > > FWNODE_ACPI_DATA,
>> > > FWNODE_PDATA,
>> > > FWNODE_IRQCHIP,
>> > > + FWNODE_IOMMU,
>> >
>> > This patch provides groundwork for this series and it is key for
>> > the rest of it, basically the point here is that we need a fwnode
>> > to differentiate platform devices created out of static ACPI tables
>> > entries (ie IORT), that represent IOMMU components.
>> >
>> > The corresponding device is not an ACPI device (I could fabricate one as
>> > it is done for other static tables entries eg FADT power button, but I
>> > do not necessarily see the reason for doing that given that all we need
>> > the fwnode for is a token identifier), so FWNODE_ACPI does not apply
>> > here.
>> >
>> > Please let me know if it is reasonable how I sorted this out (it
>> > is basically identical to IRQCHIP, just another enum entry), the
>> > remainder of the code depends on this.
>>
>> I'm not familiar with the use case, so I don't see anything unreasonable
>> in it.
>
> The use case is pretty simple: on ARM SMMU devices are platform devices.
> When booting with DT they are identified through an of_node and related
> FWNODE_OF type. When booting with ACPI, the ARM SMMU platform devices,
> to be equivalent to DT booting path, should be created out of static
> IORT table entries (that's how we describe SMMUs); we need to create
> a fwnode "token" to associate with those platform devices and that's
> not a FWNODE_ACPI (that is for an ACPI device firmware object, here we
> really do not need one), so this patch.
>
>> If you're asking about whether or not I mind adding more fwnode types in
>> principle, then no, I don't. :-)
>
> Yes, that's what I was asking, the only point that bugs me is that for
> both FWNODE_IRQCHIP and FWNODE_IOMMU the fwnode is just a "token" (ie a
> valid pointer) used for look-up and the type in the fwnode_handle is
> mostly there for error checking, I was wondering if we could create a
> specific fwnode_type for this specific usage (eg FWNODE_TAG and then add
> a type to it as part of its container struct) instead of adding an enum
> value per subsystem - it seems there are other fwnode types in the
> pipeline :), so I am asking:
>
> lkml.kernel.org/r/3D1468514043-21081-3-git-send-email-minyard at acm.org
OK, I see your concern now, so thanks for presenting it so clearly.
While I don't see anything wrong with having per-subsystem fwnode
types in principle, I agree that if the only purpose of them is to
mean "this comes from ACPI, but from a static table, not from the
namespace", it would be better to have a single fwnode type for that,
like FWNODE_ACPI_STATIC or similar.
Thanks,
Rafael
^ permalink raw reply
* [PATCH] ARM64: dts: meson-gxbb-odroidc2: Enable USB Nodes
From: Kevin Hilman @ 2016-09-30 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475227059-17462-1-git-send-email-brian.kim@hardkernel.com>
Brian Kim <brian.kim@hardkernel.com> writes:
> Enable both gxbb USB controller and add a 5V regulator for the OTG port
> VBUS
>
> Signed-off-by: Brian Kim <brian.kim@hardkernel.com>
Thanks for the patch.
In the future, please state what branch the patch should apply to when
not using mainline. Because of the sd_emmc nodes in your patch, I could
tell that it was based on my integ branch so was able to figure it out,
but it's very helpful to maintainers if you state the branch and/or any
dependencies explicity.
> ---
> .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 29 ++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> index 8d89edc..997c671 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> @@ -64,6 +64,18 @@
> reg = <0x0 0x0 0x0 0x80000000>;
> };
>
> + usb_pwr: regulator-usb-pwrs {
minor nit: since this is specific to the OTG part, can you call this
usb_otg_pwr? ...
> + compatible = "regulator-fixed";
> +
> + regulator-name = "USB_PWR";
... and rename this also?
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +
> + gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
Thanks
Kevin
^ permalink raw reply
* [PATCH] pwm: imx: Port "pwm: imx: support output polarity inversion" to Linux v4.7
From: Stefan Agner @ 2016-09-30 15:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930084958.2f3f6e3a@jawa>
On 2016-09-29 23:49, Lukasz Majewski wrote:
> Dear all,
>
>> Dear Lothar, Stefan,
>>
>> > This patch ports "pwm: imx: support output polarity inversion" patch
>> > set written by Lothar Wassmann (v6 from 10.2014).
>> >
>>
>> I've read the e-mail from Stefan regarding missing support for pwm-imx
>> polarity inversion feature.
>>
>> I also would like to see it in ML. Hence, my patch. Lothar, please
>> feel free to squash it to your patches when you (I hope :-) ) will
>> prepare v7 of this feature.
>>
>> I hope that this would help.
>
> Was there any decision about those patches?
Bhuvan here at Toradex is preparing an updated patchset...
>
> Would they be included to main line anytime soon?
I don't think that there were fundamental issues with the patchset, so I
hope they make it once upon a time...
--
Stefan
>
> Best regards,
> ?ukasz Majewski
>
>>
>> Best regards,
>> ?ukasz Majewski
>>
>> > It is used to control backlight of panels via inverted PWM signal.
>> >
>> > The "inversion" of PWM output is not an issue at such devices, since
>> > separate GPIO pin is responsible for enabling and disabling the
>> > panel's backlight.
>> >
>> > This patch should be put on top of:
>> >
>> > https://patchwork.kernel.org/patch/5065841/
>> > https://patchwork.kernel.org/patch/5065821/
>> > https://patchwork.kernel.org/patch/5065811/
>> >
>> >
>> > Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
>> > ---
>> > drivers/pwm/pwm-imx.c | 20 ++++++++++++++------
>> > 1 file changed, 14 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
>> > index 471a99e..c37d223 100644
>> > --- a/drivers/pwm/pwm-imx.c
>> > +++ b/drivers/pwm/pwm-imx.c
>> > @@ -181,7 +181,7 @@ static int imx_pwm_config_v2(struct pwm_chip
>> > *chip, if (enable)
>> > cr |= MX3_PWMCR_EN;
>> >
>> > - if (pwm->polarity == PWM_POLARITY_INVERSED)
>> > + if (pwm->args.polarity == PWM_POLARITY_INVERSED)
>> > cr |= MX3_PWMCR_POUTC;
>> >
>> > writel(cr, imx->mmio_base + MX3_PWMCR);
>> > @@ -201,11 +201,6 @@ static void imx_pwm_set_enable_v2(struct
>> > pwm_chip *chip, bool enable) else
>> > val &= ~MX3_PWMCR_EN;
>> >
>> > - if (chip->pwms[0].polarity == PWM_POLARITY_INVERSED)
>> > - val |= MX3_PWMCR_POUTC;
>> > - else
>> > - val &= ~MX3_PWMCR_POUTC;
>> > -
>> > writel(val, imx->mmio_base + MX3_PWMCR);
>> > }
>> >
>> > @@ -253,6 +248,19 @@ static int imx_pwm_set_polarity(struct pwm_chip
>> > *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
>> > {
>> > struct imx_chip *imx = to_imx_chip(chip);
>> > + u32 val;
>> > +
>> > + if (polarity == pwm->args.polarity)
>> > + return 0;
>> > +
>> > + val = readl(imx->mmio_base + MX3_PWMCR);
>> > +
>> > + if (polarity == PWM_POLARITY_INVERSED)
>> > + val |= MX3_PWMCR_POUTC;
>> > + else
>> > + val &= ~MX3_PWMCR_POUTC;
>> > +
>> > + writel(val, imx->mmio_base + MX3_PWMCR);
>> >
>> > dev_dbg(imx->chip.dev, "%s: polarity set to %s\n",
>> > __func__, polarity == PWM_POLARITY_INVERSED ? "inverted" :
>> > "normal");
>>
^ permalink raw reply
* [PATCH 0/3] Support userspace irqchip with arch timers
From: Alexander Graf @ 2016-09-30 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930154335.GB7996@cbox>
On 30.09.16 17:43, Christoffer Dall wrote:
> On Fri, Sep 30, 2016 at 05:38:11PM +0200, Alexander Graf wrote:
>>
>>
>> On 30.09.16 16:54, Alexander Graf wrote:
>>>
>>>
>>> On 27.09.16 21:08, Christoffer Dall wrote:
>>>> Hi Alex,
>>>>
>>>> Marc and I have been looking at this during Linaro connect and have
>>>> slightly reworked your patch into this small series.
>>>>
>>>> It would be good if you could have a look at it and test it out.
>>>>
>>>> I've tested it with your QEMU, and it works for UP, but secondary CPUs
>>>> fail to come up, and it looks like the kernel never gets an IPI for
>>>> those CPUs from userspace. Any chance you're willing to take a look at
>>>> that?
>>>
>>> I still need to see whether I can come up with a prettier solution, but
>>> for now this works:
>>>
>>> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
>>
>> Eh, no, not in i386 code :). But the problem seems to be a missing
>> mpstate sync.
>>
> Yeah, that looked really dodgy. Have you tested it? :)
I have, but I ran the wrong command line and by accident used -M
...,kernel-irqchip=on :)
Alex
^ permalink raw reply
* [PATCH 3/3] arm64: dump: Add checking for writable and exectuable pages
From: Mark Rutland @ 2016-09-30 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160929213257.30505-4-labbott@redhat.com>
On Thu, Sep 29, 2016 at 02:32:57PM -0700, Laura Abbott wrote:
> @@ -219,6 +223,15 @@ static void note_page(struct pg_state *st, unsigned long addr, unsigned level,
> unsigned long delta;
>
> if (st->current_prot) {
> + if (st->check_wx &&
> + ((st->current_prot & PTE_RDONLY) != PTE_RDONLY) &&
> + ((st->current_prot & PTE_PXN) != PTE_PXN)) {
> + WARN_ONCE(1, "arm64/mm: Found insecure W+X mapping at address %p/%pS\n",
> + (void *)st->start_address,
> + (void *)st->start_address);
> + st->wx_pages += (addr - st->start_address) / PAGE_SIZE;
> + }
> +
Would it be worth verifying that all kernel mappings are UXN, too?
ARMv8 allows execute-only mappings, and a !UXN mapping could result in an info
leak (e.g. pointers in MOVZ+MOVK sequences), or potential asynchronous issues
(e.g. user instruction fetches accessing read-destructive device registers).
All kernel mappings *should* be UXN.
Thanks,
Mark.
^ permalink raw reply
* [PATCH] drm/sun4i: Check that the plane coordinates are not negative
From: Boris Brezillon @ 2016-09-30 16:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930143320.26241-1-maxime.ripard@free-electrons.com>
On Fri, 30 Sep 2016 16:33:20 +0200
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> Our planes cannot be set at negative coordinates. Make sure we reject such
> configuration.
>
> Reported-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/gpu/drm/sun4i/sun4i_layer.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c
> index f0035bf5efea..f5463c4c2cde 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_layer.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
> @@ -29,6 +29,9 @@ struct sun4i_plane_desc {
> static int sun4i_backend_layer_atomic_check(struct drm_plane *plane,
> struct drm_plane_state *state)
> {
> + if ((state->crtc_x < 0) || (state->crtc_y < 0))
> + return -EINVAL;
> +
Hm, I think it's a perfectly valid use case from the DRM framework and
DRM user PoV: you may want to place your plane at a negative CRTC
offset (which means part of the plane will be hidden).
Maybe I'm wrong, but it seems you can support that by adapting the
start address of your framebuffer pointer and the layer size.
Have you tried doing something like that?
--->8---
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 3ab560450a82..6b68804f3035 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -110,15 +110,30 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
{
struct drm_plane_state *state = plane->state;
struct drm_framebuffer *fb = state->fb;
+ int crtc_w, crtc_h, crtc_x, crtc_y;
DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
+ crtc_x = state->crtc_x;
+ crtc_y = state->crtc_y;
+ crtc_w = state->crtc_w;
+ crtc_h = state->crtc_h;
+
+ if (crtc_x < 0) {
+ crtc_w += crtx_x;
+ crtc_x = 0;
+ }
+
+ if (crtc_y < 0) {
+ crtc_h += crtx_y;
+ crtc_y = 0;
+ }
+
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
state->crtc_w, state->crtc_h);
regmap_write(backend->regs, SUN4I_BACKEND_DISSIZE_REG,
- SUN4I_BACKEND_DISSIZE(state->crtc_w,
- state->crtc_h));
+ SUN4I_BACKEND_DISSIZE(crtc_w, crtc_h));
}
/* Set the line width */
@@ -130,15 +145,13 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
state->crtc_w, state->crtc_h);
regmap_write(backend->regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
- SUN4I_BACKEND_LAYSIZE(state->crtc_w,
- state->crtc_h));
+ SUN4I_BACKEND_LAYSIZE(crtc_w, crtc_h));
/* Set base coordinates */
DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
state->crtc_x, state->crtc_y);
regmap_write(backend->regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
- SUN4I_BACKEND_LAYCOOR(state->crtc_x,
- state->crtc_y));
+ SUN4I_BACKEND_LAYCOOR(crtc_x, crtc_y));
return 0;
}
@@ -198,6 +211,12 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
paddr += (state->src_x >> 16) * bpp;
paddr += (state->src_y >> 16) * fb->pitches[0];
+ if (state->crtc_x < 0)
+ paddr -= bpp * state->crtc_x;
+
+ if (state->crtc_y < 0)
+ paddr -= fb->pitches[0] * state->crtc_y;
+
DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
/* Write the 32 lower bits of the address (in bits) */
^ permalink raw reply related
* [GIT PULL] arm64: updates for 4.9
From: Will Deacon @ 2016-09-30 16:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
Please pull the following arm64 updates for 4.9. I'm sending this before
the merge window actually opens, since I'm off fishing next week and
won't have internet access. Catalin will be in the office in case anything
goes wrong.
As for the changes themselves, there is a summary in the tag but it's
a bit all over the place this time with no "killer feature" to speak of.
Support for mismatched cache line sizes should help people seeing whacky
JIT failures on some SoCs, and the big.LITTLE perf updates have been a
long time coming, but a lot of the changes here are cleanups.
We stray outside arch/arm64 in a few areas: the arch/arm/ arch_timer
workaround is acked by Russell, the DT/OF bits are acked by Rob, the
arch_timer clocksource changes acked by Marc, CPU hotplug by tglx and
jump_label by Peter (all CC'd).
There are a couple of minor conflicts with mainline, due to fixes that
were merged after -rc3. I've included the resolution below, but it's
pretty straighforward.
Cheers,
Will
P.S. I've renewed my gpg key, so you may need to refetch it to see the
updated expiry date.
--->8
diff --cc arch/arm64/kernel/head.S
index 3e7b050e99dc,427f6d3f084c..000000000000
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
diff --cc drivers/perf/arm_pmu.c
index f5e1008a223d,77ac1ccb39ed..000000000000
--- a/drivers/perf/arm_pmu.c
+++ b/drivers/perf/arm_pmu.c
@@@ -970,8 -990,7 +991,8 @@@ static int of_pmu_irq_cfg(struct arm_pm
if (cpumask_weight(&pmu->supported_cpus) == 0) {
int irq = platform_get_irq(pdev, 0);
- if (irq >= 0 && irq_is_percpu(irq)) {
+ if (irq > 0 && irq_is_percpu(irq)) {
+ /* If using PPIs, check the affinity of the partition */
int ret;
ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
--->8
The following changes since commit fa8410b355251fd30341662a40ac6b22d3e38468:
Linux 4.8-rc3 (2016-08-21 16:14:10 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git tags/arm64-upstream
for you to fetch changes up to db68f3e7594aca77632d56c449bd36c6c931d59a:
arm64: tlbflush.h: add __tlbi() macro (2016-09-28 10:44:05 +0100)
----------------------------------------------------------------
arm64 updates for 4.9:
- Support for execute-only page permissions
- Support for hibernate and DEBUG_PAGEALLOC
- Support for heterogeneous systems with mismatches cache line sizes
- Errata workarounds (A53 843419 update and QorIQ A-008585 timer bug)
- arm64 PMU perf updates, including cpumasks for heterogeneous systems
- Set UTS_MACHINE for building rpm packages
- Yet another head.S tidy-up
- Some cleanups and refactoring, particularly in the NUMA code
- Lots of random, non-critical fixes across the board
----------------------------------------------------------------
AKASHI Takahiro (1):
arm64: mark reserved memblock regions explicitly in iomem
Ard Biesheuvel (12):
arm64: head.S: get rid of x25 and x26 with 'global' scope
arm64: cpufeature: constify arm64_ftr_bits structures
arm64: cpufeature: constify arm64_ftr_regs array
arm64: cpufeature: expose arm64_ftr_reg struct for CTR_EL0
arm64: kernel: fix style issues in sleep.S
arm64: kernel: use ordinary return/argument register for el2_setup()
arm64: head.S: move KASLR processing out of __enable_mmu()
arm64: kernel: use x30 for __enable_mmu return address
arm64: kernel: drop use of x24 from primary boot path
arm64: head.S: use ordinary stack frame for __primary_switched()
arm64: head.S: document the use of callee saved registers
arm64: kernel: re-export _cpu_resume() from sleep.S
Catalin Marinas (3):
arm64: Introduce execute-only page access permissions
jump_labels: Allow array initialisers
arm64: Use static keys for CPU features
Chris Metcalf (1):
arm64: factor work_pending state machine to C
David A. Long (1):
arm64: Improve kprobes test for atomic sequence
James Morse (7):
arm64: Create sections.h
arm64: vmlinux.ld: Add mmuoff data sections and move mmuoff text into idmap
arm64: hibernate: Support DEBUG_PAGEALLOC
cpu/hotplug: Allow suspend/resume CPU to be specified
arm64: hibernate: Resume when hibernate image created on non-boot CPU
Revert "arm64: hibernate: Refuse to hibernate if the boot cpu is offline"
arm64: Drop generic xlate_dev_mem_{k,}ptr()
Jeremy Linton (2):
arm64: pmu: Probe default hw/cache counters
arm64: pmu: Hoist pmu platform device name
Jisheng Zhang (3):
arm64: vdso: add __init section marker to alloc_vectors_page
arm64: vdso: constify vm_special_mapping used for aarch32 vectors page
arm64: apply __ro_after_init to some objects
Kefeng Wang (8):
arm64: perf: Use the builtin_platform_driver
arm64: cleanup unused UDBG_* define
arm64: mm: drop fixup_init() and mm.h
of_numa: Use of_get_next_parent to simplify code
of_numa: Use pr_fmt()
arm64: numa: Use pr_fmt()
arm64: Kconfig: select OF/ACPI_NUMA under NUMA config
arm64: Kconfig: remove SMP dependence for NUMA
Kim Phillips (1):
arm64: don't select PERF_USE_VMALLOC by default
Kwangwoo Lee (1):
arm64: mm: convert __dma_* routines to use start, size
Laura Abbott (1):
arm64: Correctly bounds check virt_addr_valid
Marc Zyngier (1):
drivers/perf: arm_pmu: Always consider IRQ0 as an error
Mark Rutland (19):
arm64: hibernate: reduce TLB maintenance scope
arm64: remove traces of perf_ops_bp
arm64: always enable DEBUG_RODATA and remove the Kconfig option
arm64: sysreg: allow write_sysreg to use XZR
arm64: arch_timer: simplify accessors
arm64: dcc: simplify accessors
arm64/kvm: use {read,write}_sysreg()
arm64: simplify sysreg manipulation
arm64: simplify contextidr_thread_switch
drivers/perf: arm_pmu: add common attr group fields
arm64: perf: move to common attr_group fields
arm: perf: move to common attr_group fields
drivers/perf: arm_pmu: only use common attr_groups
drivers/perf: arm_pmu: expose a cpumask in sysfs
arm64: alternative: add auto-nop infrastructure
arm64: use alternative auto-nop
arm64/kvm: use alternative auto-nop
arm64: fix dump_backtrace/unwind_frame with NULL tsk
arm64: tlbflush.h: add __tlbi() macro
Mark Salter (1):
arm64: pmu: add fallback probe table
Masahiro Yamada (1):
arm64: remove redundant "select HAVE_CLK"
Michal Marek (1):
arm64: Set UTS_MACHINE in the Makefile
Paul Gortmaker (1):
arm64: migrate exception table users off module.h and onto extable.h
Pratyush Anand (2):
arm64: kprobe: Always clear pstate.D in breakpoint exception handler
arm64: ftrace: add save_stack_trace_regs()
Robin Murphy (2):
arm64/io: Allow I/O writes to use {W,X}ZR
arm64: Remove shadowed asm-generic headers
Scott Wood (3):
arm64: arch_timer: Add device tree binding for A-008585 erratum
arm64: arch_timer: Work around QorIQ Erratum A-008585
arm/arm64: arch_timer: Use archdata to indicate vdso suitability
Suzuki K Poulose (9):
arm64: Set the safe value for L1 icache policy
arm64: Use consistent naming for errata handling
arm64: Rearrange CPU errata workaround checks
arm64: alternative: Disallow patching instructions using literals
arm64: insn: Add helpers for adrp offsets
arm64: alternative: Add support for patching adrp instructions
arm64: Introduce raw_{d,i}cache_line_size
arm64: Refactor sysinstr exception handling
arm64: Work around systems with mismatched cache line sizes
Vladimir Murzin (1):
arm64: kernel: do not need to reset UAO on exception entry
Will Deacon (9):
arm64: errata: Pass --fix-cortex-a53-843419 to ld if workaround enabled
arm64: debug: avoid resetting stepping state machine when TIF_SINGLESTEP
arm64: hw_breakpoint: convert CPU hotplug notifier to new infrastructure
arm64: debug: convert OS lock CPU hotplug notifier to new infrastructure
arm64: debug: report TRAP_TRACE instead of TRAP_HWBRPT for singlestep
arm64: sysreg: replace open-coded mrs_s/msr_s with {read,write}_sysreg_s
arm64: barriers: introduce nops and __nops macros for NOP sequences
arm64: lse: convert lse alternatives NOP padding to use __nops
MAINTAINERS: Update ARM PMU PROFILING AND DEBUGGING entry
Zhen Lei (8):
of/numa: remove a duplicated pr_debug information
of/numa: fix a memory@ node can only contains one memory block
of/numa: add nid check for memory block
of/numa: remove a duplicated warning
arm64/numa: avoid inconsistent information to be printed
arm64/numa: support HAVE_SETUP_PER_CPU_AREA
arm64/numa: remove some useless code
arm64/numa: remove the limitation that cpu0 must bind to node0
zijun_hu (1):
arm64: remove duplicate macro __KERNEL__ check
Documentation/arm64/silicon-errata.txt | 2 +
.../devicetree/bindings/arm/arch_timer.txt | 6 +
Documentation/kernel-parameters.txt | 9 +
Documentation/static-keys.txt | 9 +
MAINTAINERS | 6 +-
arch/arm/Kconfig | 1 +
arch/arm/include/asm/clocksource.h | 8 +
arch/arm/kernel/perf_event_v7.c | 47 +++--
arch/arm/kernel/vdso.c | 2 +-
arch/arm64/Kconfig | 33 ++--
arch/arm64/Kconfig.debug | 10 --
arch/arm64/Kconfig.platforms | 1 -
arch/arm64/Makefile | 10 ++
arch/arm64/include/asm/Kbuild | 5 -
arch/arm64/include/asm/acpi.h | 8 +-
arch/arm64/include/asm/alternative.h | 70 ++++++--
arch/arm64/include/asm/arch_timer.h | 82 ++++++---
arch/arm64/include/asm/assembler.h | 53 +++++-
arch/arm64/include/asm/atomic_lse.h | 64 +++----
arch/arm64/include/asm/barrier.h | 3 +
arch/arm64/include/asm/cacheflush.h | 3 +-
arch/arm64/include/asm/clocksource.h | 8 +
arch/arm64/include/asm/cmpxchg.h | 4 +-
arch/arm64/include/asm/cpufeature.h | 42 +++--
arch/arm64/include/asm/cputype.h | 6 +-
arch/arm64/include/asm/dcc.h | 14 +-
arch/arm64/include/asm/esr.h | 84 ++++++++-
arch/arm64/include/asm/hw_breakpoint.h | 15 +-
arch/arm64/include/asm/insn.h | 11 +-
arch/arm64/include/asm/io.h | 19 +-
arch/arm64/include/asm/kvm_mmu.h | 10 +-
arch/arm64/include/asm/memory.h | 8 +-
arch/arm64/include/asm/mmu_context.h | 36 ++--
arch/arm64/include/asm/pgtable-hwdef.h | 1 +
arch/arm64/include/asm/pgtable-prot.h | 5 +-
arch/arm64/include/asm/pgtable.h | 20 ++-
arch/arm64/include/asm/processor.h | 2 -
arch/arm64/include/asm/sections.h | 30 ++++
arch/arm64/include/asm/spinlock.h | 27 ++-
arch/arm64/include/asm/suspend.h | 3 +
arch/arm64/include/asm/sysreg.h | 44 +++--
arch/arm64/include/asm/system_misc.h | 6 -
arch/arm64/include/asm/thread_info.h | 3 +
arch/arm64/include/asm/tlbflush.h | 34 +++-
arch/arm64/include/asm/traps.h | 6 +-
arch/arm64/include/asm/virt.h | 15 +-
arch/arm64/kernel/Makefile | 2 +
arch/arm64/kernel/acpi_numa.c | 4 +-
arch/arm64/kernel/alternative.c | 28 ++-
arch/arm64/kernel/asm-offsets.c | 2 +
arch/arm64/kernel/cacheinfo.c | 8 +-
arch/arm64/kernel/cpu_errata.c | 26 ++-
arch/arm64/kernel/cpu_ops.c | 3 +-
arch/arm64/kernel/cpufeature.c | 137 +++++++-------
arch/arm64/kernel/cpuinfo.c | 2 -
arch/arm64/kernel/debug-monitors.c | 48 ++---
arch/arm64/kernel/entry.S | 24 +--
arch/arm64/kernel/head.S | 197 ++++++++++++---------
arch/arm64/kernel/hibernate-asm.S | 6 +-
arch/arm64/kernel/hibernate.c | 118 ++++++++----
arch/arm64/kernel/hw_breakpoint.c | 48 ++---
arch/arm64/kernel/insn.c | 15 +-
arch/arm64/kernel/kaslr.c | 3 +-
arch/arm64/kernel/perf_event.c | 100 ++++++++---
arch/arm64/kernel/probes/decode-insn.c | 48 +++--
arch/arm64/kernel/probes/kprobes.c | 36 ++--
arch/arm64/kernel/process.c | 14 +-
arch/arm64/kernel/relocate_kernel.S | 2 +-
arch/arm64/kernel/setup.c | 11 +-
arch/arm64/kernel/signal.c | 36 ++--
arch/arm64/kernel/sleep.S | 29 ++-
arch/arm64/kernel/smp.c | 14 +-
arch/arm64/kernel/smp_spin_table.c | 3 +-
arch/arm64/kernel/stacktrace.c | 26 ++-
arch/arm64/kernel/suspend.c | 10 +-
arch/arm64/kernel/sys_compat.c | 2 +-
arch/arm64/kernel/traps.c | 97 ++++++----
arch/arm64/kernel/vdso.c | 36 ++--
arch/arm64/kernel/vmlinux.lds.S | 19 ++
arch/arm64/kvm/hyp.S | 6 +-
arch/arm64/kvm/sys_regs.c | 31 ++--
arch/arm64/kvm/sys_regs_generic_v8.c | 6 +-
arch/arm64/lib/copy_page.S | 13 +-
arch/arm64/mm/cache.S | 82 ++++-----
arch/arm64/mm/dma-mapping.c | 9 +-
arch/arm64/mm/extable.c | 2 +-
arch/arm64/mm/fault.c | 7 +-
arch/arm64/mm/flush.c | 2 -
arch/arm64/mm/init.c | 15 +-
arch/arm64/mm/mm.h | 2 -
arch/arm64/mm/mmu.c | 15 +-
arch/arm64/mm/numa.c | 115 ++++++++----
arch/arm64/mm/pageattr.c | 41 ++++-
arch/arm64/mm/pgd.c | 2 -
arch/arm64/mm/proc.S | 13 +-
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/arm_arch_timer.c | 113 +++++++++++-
drivers/of/of_numa.c | 66 +++----
drivers/perf/arm_pmu.c | 35 +++-
include/linux/cpu.h | 6 +-
include/linux/cpuhotplug.h | 2 +
include/linux/jump_label.h | 12 ++
include/linux/perf/arm_pmu.h | 13 +-
kernel/cpu.c | 9 +-
mm/mmap.c | 5 +
105 files changed, 1699 insertions(+), 972 deletions(-)
create mode 100644 arch/arm/include/asm/clocksource.h
create mode 100644 arch/arm64/include/asm/clocksource.h
create mode 100644 arch/arm64/include/asm/sections.h
delete mode 100644 arch/arm64/mm/mm.h
^ permalink raw reply
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