* Coresight ETF trace dump failed in Juno r1 with 4.8-rc8
From: Suzuki K Poulose @ 2016-10-04 14:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGhh56H7a9oEYxzEA4gGvBey=COMqwgisd4tzewU8DLGcGrsww@mail.gmail.com>
On 04/10/16 06:37, Venkatesh Vivekanandan wrote:
> On Mon, Oct 3, 2016 at 6:44 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
>> Hi Venkatesh,
>>
>> On 03/10/16 12:36, Venkatesh Vivekanandan wrote:
>>>
>>> Hi All,
>>>
>>> I am trying to collect ETF trace from Juno R1 and could see "cpu
>>> stall" while dumping the trace. Attached is the log of sequence
>>> followed. Was trying to collect the trace data from hardware and see
>>> if it is any valid data. Am I missing anything here?.
>>>
>>
>> There are few fixes from me and Suzuki queued for v4.9.
>> Can you check if this issue persists even on linux-next ?
>
> Issue is the same in linux-next as well. Please find the attached log.
>
> linaro-test [rc=0]# dd if=/dev/20010000.etf of=/cstrace.bin bs=1
> [ 120.009698] INFO: rcu_preempt detected stalls on CPUs/tasks:
> [ 120.015307] 2-...: (1 GPs behind) idle=f11/140000000000000/0
> softirq=224/224 fqs=1903
> [ 120.023226] (detected by 1, t=5255 jiffies, g=-1, c=-2, q=19)
> [ 120.029001] Task dump for CPU 2:
> [ 120.032190] dd R running task 0 1270 1267 0x00000002
> [ 120.039172] Call trace:
> [ 120.041594] [<ffff000008085534>] __switch_to+0xc8/0xd4
> [ 120.046675] [<0000000000020000>] 0x20000
>
> Steps followed,
> # git clone git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
> linux-next
> # cd linux-next
> # make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- defconfig
> # make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- menuconfig <---
> enable coresight
> # make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 Image
> # make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- dtbs
> # arch/arm64/boot/Image <--- copied this kernel
> # arch/arm64/boot/dts/arm/juno-r1.dtb <--- copied this dtb
>
> Top commit in linux-next is,
>
> commit c7d3b912180a9bb0733e5cfab84e5a7493dd3599
> Author: Stephen Rothwell <sfr@canb.auug.org.au>
> Date: Tue Oct 4 14:52:03 2016 +1100
>
> Add linux-next specific files for 20161004
Can't reproduce it here either.
root at localhost:/sys/bus/coresight/devices# echo 1 > 20010000.etf/enable_sink
root at localhost:/sys/bus/coresight/devices# echo 1 > 22140000.etm/enable_source
root at localhost:/sys/bus/coresight/devices# dd if=/dev/20010000.etf bs=1 of=/root/etr.bin
65536+0 records in
65536+0 records out
65536 bytes (66 kB) copied, 0.227546 s, 288 kB/s
root at localhost:/sys/bus/coresight/devices# dd if=/dev/20010000.etf bs=1 of=/root/etr.bin
65536+0 records in
65536+0 records out
65536 bytes (66 kB) copied, 0.233527 s, 281 kB/s
root at localhost:/sys/bus/coresight/devices# echo 0 > 20010000.etf/enable_sink
root at localhost:/sys/bus/coresight/devices# dd if=/dev/20010000.etf bs=1 of=/root/etr.bin
65536+0 records in
65536+0 records out
65536 bytes (66 kB) copied, 0.474943 s, 138 kB/s
FWIW, here is my firmware version :
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v1.1(release):e04723e21362
NOTICE: BL1: Built : 15:39:56, Sep 1 2015
NOTICE: BL1: Booting BL2
NOTICE: BL2: v1.1(release):e04723e21362
NOTICE: BL2: Built : 15:42:30, Sep 1 2015
NOTICE: BL1: Booting BL3-1
NOTICE: BL3-1: v1.1(release):604d5da6f2aa
NOTICE: BL3-1: Built : 14:50:36, Sep 10 2015
UEFI firmware (version ea31f8e built at 16:35:17 on Aug 5 2015)
Cheers
Suzuki
^ permalink raw reply
* [PATCH 3/3] Revert "ACPI,PCI,IRQ: remove SCI penalize function"
From: Thomas Gleixner @ 2016-10-04 14:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <babdb433-2be5-2c04-cbdd-c2af443447cb@codeaurora.org>
On Tue, 4 Oct 2016, Sinan Kaya wrote:
> On 10/4/2016 3:23 AM, Thomas Gleixner wrote:
> > On Sat, 1 Oct 2016, Sinan Kaya wrote:
> >
> >> This reverts commit 9e5ed6d1fb87 ("ACPI,PCI,IRQ: remove SCI penalize
> >> function"). SCI penalty API was replaced by the runtime penalty calculation
> >> based on the value of acpi_gbl_FADT.sci_interrupt.
> >
> > This does more than only reverting said commit ....
>
> The SCI function was removed in two steps (first refactor and then remove).
> I was trying to do the revert at one step. I can divide into two if it makes
> it better
No one step is fine. But this wants to be documented in the changelog.
> >> acpi_gbl_FADT.sci_interrupt type does not get updated at the right time
> >> for some platforms and results in incorrect penalty assignment for PCI
> >> IRQs as irq_get_trigger_type returns the wrong type.
> >
> > And the obvious question is: Why does irq_get_trigger_type() return the
> > wrong type?
>
> Here is some history:
>
> I now remember that Bjorn indicated the race condition possibility in this thread
> here.
>
> https://lkml.org/lkml/2016/3/8/640
> My understanding is that register_gsi function delivers the IRQ found in
> the ACPI table to the interrupt controller driver. Penalties are
> calculated before a link object is enabled to find out which interrupt
> has the least number of users. By the time penalties are calculated, the
> IRQ is not registered yet and it returns the wrong type.
Ok.
> >
> > What's the root cause of this problem? Your changelog does not tell
> > anything.
>
> If you are OK with the above description, I can add this to the commit message.
Yes please.
Thanks,
tglx
^ permalink raw reply
* [PATCH v3 2/2] crypto: marvell - Don't break chain for computable last ahash requests
From: Boris Brezillon @ 2016-10-04 14:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004125720.3347-3-romain.perier@free-electrons.com>
On Tue, 4 Oct 2016 14:57:20 +0200
Romain Perier <romain.perier@free-electrons.com> wrote:
> Currently, the driver breaks chain for all kind of hash requests in order to
> don't override intermediate states of partial ahash updates. However, some final
> ahash requests can be directly processed by the engine, and so without
> intermediate state. This is typically the case for most for the HMAC requests
> processed via IPSec.
>
> This commits adds a TDMA descriptor to copy context for these of requests
> into the "op" dma pool, then it allow to chain these requests at the DMA level.
> The 'complete' operation is also updated to retrieve the MAC digest from the
> right location.
>
> Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
> ---
>
> Changes in v3:
> - Copy the whole context back to RAM and not just the digest. Also
> fixed a rebase issue ^^ (whoops)
>
> Changes in v2:
> - Replaced BUG_ON by an error
> - Add a variable "break_chain", with "type" to break the chain
>
> with ahash requests. It improves code readability.
> drivers/crypto/marvell/hash.c | 79 +++++++++++++++++++++++++++++++++++--------
> 1 file changed, 64 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/crypto/marvell/hash.c b/drivers/crypto/marvell/hash.c
> index 9f28468..b36f196 100644
> --- a/drivers/crypto/marvell/hash.c
> +++ b/drivers/crypto/marvell/hash.c
> @@ -312,24 +312,53 @@ static void mv_cesa_ahash_complete(struct crypto_async_request *req)
> int i;
>
> digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
> - for (i = 0; i < digsize / 4; i++)
> - creq->state[i] = readl_relaxed(engine->regs + CESA_IVDIG(i));
>
> - if (creq->last_req) {
> + if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ &&
> + !(creq->base.chain.last->flags & CESA_TDMA_BREAK_CHAIN)) {
> + struct mv_cesa_tdma_desc *tdma = NULL;
> + __le32 *data = NULL;
> +
> + for (tdma = creq->base.chain.first; tdma; tdma = tdma->next) {
> + u32 type = tdma->flags & CESA_TDMA_TYPE_MSK;
> + if (type == CESA_TDMA_RESULT)
> + break;
> + }
You should be able to drop the DUMMY desc at the end of the chain and
replace it by the RESULT desc. This way, you won't have to iterate over
the chain to find the TDMA_RESULT element: it should always be the last
desc in the chain.
> +
> + if (!tdma) {
> + dev_err(cesa_dev->dev, "Failed to retrieve tdma "
> + "descriptor for outer data\n");
> + return;
> + }
> +
> /*
> - * Hardware's MD5 digest is in little endian format, but
> - * SHA in big endian format
> + * Result is already in the correct endianess when the SA is
> + * used
> */
> - if (creq->algo_le) {
> - __le32 *result = (void *)ahashreq->result;
> + data = tdma->op->ctx.hash.hash;
> + for (i = 0; i < digsize / 4; i++)
> + creq->state[i] = cpu_to_le32(data[i]);
>
> - for (i = 0; i < digsize / 4; i++)
> - result[i] = cpu_to_le32(creq->state[i]);
> - } else {
> - __be32 *result = (void *)ahashreq->result;
> + memcpy(ahashreq->result, data, digsize);
> + } else {
> + for (i = 0; i < digsize / 4; i++)
> + creq->state[i] = readl_relaxed(engine->regs +
> + CESA_IVDIG(i));
> + if (creq->last_req) {
> + /*
> + * Hardware's MD5 digest is in little endian format, but
> + * SHA in big endian format
> + */
> + if (creq->algo_le) {
> + __le32 *result = (void *)ahashreq->result;
> +
> + for (i = 0; i < digsize / 4; i++)
> + result[i] = cpu_to_le32(creq->state[i]);
> + } else {
> + __be32 *result = (void *)ahashreq->result;
>
> - for (i = 0; i < digsize / 4; i++)
> - result[i] = cpu_to_be32(creq->state[i]);
> + for (i = 0; i < digsize / 4; i++)
> + result[i] = cpu_to_be32(creq->state[i]);
> + }
> }
> }
>
> @@ -504,6 +533,12 @@ mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
> CESA_SA_DESC_CFG_LAST_FRAG,
> CESA_SA_DESC_CFG_FRAG_MSK);
>
> + ret = mv_cesa_dma_add_result_op(chain,
> + CESA_SA_CFG_SRAM_OFFSET,
> + CESA_SA_DATA_SRAM_OFFSET,
> + CESA_TDMA_SRC_IN_SRAM, flags);
> + if (ret)
> + return ERR_PTR(-ENOMEM);
> return op;
> }
>
> @@ -564,6 +599,8 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
> struct mv_cesa_op_ctx *op = NULL;
> unsigned int frag_len;
> int ret;
> + u32 type;
> + bool break_chain = true;
>
> basereq->chain.first = NULL;
> basereq->chain.last = NULL;
> @@ -635,6 +672,16 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
> goto err_free_tdma;
> }
>
> + /*
> + * If results are copied via DMA, this means that this
> + * request can be directly processed by the engine,
> + * without partial updates. So we can chain it at the
> + * DMA level with other requests.
> + */
> + type = basereq->chain.last->flags & CESA_TDMA_TYPE_MSK;
> + if (type == CESA_TDMA_RESULT)
> + break_chain = false;
> +
> if (op) {
> /* Add dummy desc to wait for crypto operation end */
> ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags);
> @@ -648,8 +695,10 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
> else
> creq->cache_ptr = 0;
>
> - basereq->chain.last->flags |= (CESA_TDMA_END_OF_REQ |
> - CESA_TDMA_BREAK_CHAIN);
> + basereq->chain.last->flags |= CESA_TDMA_END_OF_REQ;
> +
> + if (break_chain)
> + basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN;
Not sure this break_chain variable is really needed. you can directly
test the type of the last element in the TDMA chain here and if it's
!= CESA_TDMA_RESULT, pass the CESA_TDMA_BREAK_CHAIN flag.
>
> return 0;
>
^ permalink raw reply
* [PATCH 3/3] Revert "ACPI,PCI,IRQ: remove SCI penalize function"
From: Sinan Kaya @ 2016-10-04 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1610040919110.5278@nanos>
On 10/4/2016 3:23 AM, Thomas Gleixner wrote:
> On Sat, 1 Oct 2016, Sinan Kaya wrote:
>
>> This reverts commit 9e5ed6d1fb87 ("ACPI,PCI,IRQ: remove SCI penalize
>> function"). SCI penalty API was replaced by the runtime penalty calculation
>> based on the value of acpi_gbl_FADT.sci_interrupt.
>
> This does more than only reverting said commit ....
The SCI function was removed in two steps (first refactor and then remove).
I was trying to do the revert at one step. I can divide into two if it makes
it better.
>
>> acpi_gbl_FADT.sci_interrupt type does not get updated at the right time
>> for some platforms and results in incorrect penalty assignment for PCI
>> IRQs as irq_get_trigger_type returns the wrong type.
>
> And the obvious question is: Why does irq_get_trigger_type() return the
> wrong type?
Here is some history:
I now remember that Bjorn indicated the race condition possibility in this thread
here.
https://lkml.org/lkml/2016/3/8/640
My understanding is that register_gsi function delivers the IRQ found in the ACPI table
to the interrupt controller driver.
Penalties are calculated before a link object is enabled to find out which interrupt
has the least number of users. By the time penalties are calculated, the IRQ is not
registered yet and it returns the wrong type.
>
> What's the root cause of this problem? Your changelog does not tell
> anything.
If you are OK with the above description, I can add this to the commit message.
>
> Thanks,
>
> tglx
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH] arm: Added support for getcpu() vDSO using TPIDRURW
From: Fredrik Markstrom @ 2016-10-04 13:49 UTC (permalink / raw)
To: linux-arm-kernel
This makes getcpu() ~1000 times faster, this is very useful when
implementing per-cpu buffers in userspace (to avoid cache line
bouncing). As an example lttng ust becomes ~30% faster.
The patch will break applications using TPIDRURW (which is context switched
since commit 4780adeefd042482f624f5e0d577bf9cdcbb760 ("ARM: 7735/2:
Preserve the user r/w register TPIDRURW on context switch and fork")) and
is therefore made configurable.
Signed-off-by: Fredrik Markstrom <fredrik.markstrom@gmail.com>
---
arch/arm/include/asm/tls.h | 8 +++++++-
arch/arm/kernel/entry-armv.S | 1 -
arch/arm/mm/Kconfig | 10 ++++++++++
arch/arm/vdso/Makefile | 3 +++
arch/arm/vdso/vdso.lds.S | 3 +++
5 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 5f833f7..170fd76 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -10,10 +10,15 @@
.endm
.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+#ifdef CONFIG_VDSO_GETCPU
+ ldr \tpuser, [r2, #TI_CPU]
+#else
mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
+ ldr \tpuser, [r2, #TI_TP_VALUE + 4]
+ str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
+#endif
mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
- str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
.endm
.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
@@ -22,6 +27,7 @@
mov \tmp2, #0xffff0fff
tst \tmp1, #HWCAP_TLS @ hardware TLS available?
streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
+ ldrne \tpuser, [r2, #TI_TP_VALUE + 4] @ load the saved user r/w reg
mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 9f157e7..4e1369a 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -787,7 +787,6 @@ ENTRY(__switch_to)
THUMB( str sp, [ip], #4 )
THUMB( str lr, [ip], #4 )
ldr r4, [r2, #TI_TP_VALUE]
- ldr r5, [r2, #TI_TP_VALUE + 4]
#ifdef CONFIG_CPU_USE_DOMAINS
mrc p15, 0, r6, c3, c0, 0 @ Get domain register
str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c1799dd..f18334a 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -854,6 +854,16 @@ config VDSO
You must have glibc 2.22 or later for programs to seamlessly
take advantage of this.
+config VDSO_GETCPU
+ bool "Enable VDSO for getcpu"
+ depends on VDSO && (CPU_V6K || CPU_V7 || CPU_V7M)
+ help
+ Say Y to make getcpu a VDSO (fast) call. This is useful if you
+ want to implement per cpu buffers to avoid cache line bouncing
+ in user mode.
+ This mechanism uses the TPIDRURW register so enabling it will break
+ applications using this register for it's own purpose.
+
config DMA_CACHE_RWFO
bool "Enable read/write for ownership DMA cache maintenance"
depends on CPU_V6K && SMP
diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile
index 59a8fa7..9f1ec51 100644
--- a/arch/arm/vdso/Makefile
+++ b/arch/arm/vdso/Makefile
@@ -1,6 +1,9 @@
hostprogs-y := vdsomunge
obj-vdso := vgettimeofday.o datapage.o
+#ifeq ($(CONFIG_VDSO_GETCPU),y)
+obj-vdso += vgetcpu.o
+#endif
# Build rules
targets := $(obj-vdso) vdso.so vdso.so.dbg vdso.so.raw vdso.lds
diff --git a/arch/arm/vdso/vdso.lds.S b/arch/arm/vdso/vdso.lds.S
index 89ca89f..1af39fb 100644
--- a/arch/arm/vdso/vdso.lds.S
+++ b/arch/arm/vdso/vdso.lds.S
@@ -82,6 +82,9 @@ VERSION
global:
__vdso_clock_gettime;
__vdso_gettimeofday;
+#ifdef CONFIG_VDSO_GETCPU
+ __vdso_getcpu;
+#endif
local: *;
};
}
--
2.7.2
^ permalink raw reply related
* [PATCH 01/14] dma: sun6i-dma: Add burst case of 4
From: Jean-Francois Moine @ 2016-10-04 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004141221.55327f1b@free-electrons.com>
On Tue, 4 Oct 2016 14:12:21 +0200
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote:
> > > Add the case of a burst of 4 which is handled by the SoC.
> > >
> > > Signed-off-by: Myl?ne Josserand <mylene.josserand@free-electrons.com>
> > > ---
> > > drivers/dma/sun6i-dma.c | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> > > index 8346199..0485204 100644
> > > --- a/drivers/dma/sun6i-dma.c
> > > +++ b/drivers/dma/sun6i-dma.c
> > > @@ -240,6 +240,8 @@ static inline s8 convert_burst(u32 maxburst)
> > > switch (maxburst) {
> > > case 1:
> > > return 0;
> > > + case 4:
> > > + return 1;
> > > case 8:
> > > return 2;
> > > default:
> > > --
> > > 2.9.3
> >
> > This patch has already been rejected by Maxime in the threads
> > http://www.spinics.net/lists/dmaengine/msg08610.html
> > and
> > http://www.spinics.net/lists/dmaengine/msg08719.html
> >
> > I hope you will find the way he wants for this maxburst to be added.
>
> I was about to reply to Mylene's e-mail, suggesting that she should add
> a comment in the code (and maybe in the commit log) to explain why this
> addition is needed, and also that even though the schematics say that
> value "1" (max burst size of 4 bytes) is reserved, it is in fact
> incorrect. The Allwinner BSP code is really using this value, and it's
> the value that makes audio work, so we believe the datasheet is simply
> incorrect.
>
> We already discussed it with Maxime, so I believe he should agree this
> time. But I would suggest to have such details explained in the commit
> log and in a comment in the code.
Strange. Looking at the datasheets of the A23, A31, A33, A83T and H3
(these are the SoCs using the DMA sun6i), only the H3 can have 4 as the
burst size (the doc is unclear for the A31).
Well, I was submitting for the H3, Myl?ne is submitting for the A33.
So, what about the A23, A31 and A83T?
--
Ken ar c'henta? | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
^ permalink raw reply
* [PATCH v2 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC
From: Krzysztof Kozlowski @ 2016-10-04 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdV3WdS75QXsJgEXirqV-d=RJa-LTq4OdvS6fgQWS+DO-A@mail.gmail.com>
On Tue, Oct 04, 2016 at 03:37:35PM +0200, Geert Uytterhoeven wrote:
> On Wed, Aug 24, 2016 at 3:49 PM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>
> > + cluster_a53_opp_table: opp_table0 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp at 400000000 {
> > + opp-hz = /bits/ 64 <400000000>;
> > + opp-microvolt = <900000>;
> > + };
>
> With W=1:
>
> Warning (unit_address_vs_reg): Node /opp_table0/opp at 400000000 has a
> unit name, but no reg property
AFAIR, there should be an exception for this... [1] But maybe it was not
added after all?
Best regards,
Krzysztof
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-April/419738.html
^ permalink raw reply
* [PATCH 3/3] dt-bindings: oxnas: Update Pinctrl and GPIO for OX820 Support
From: Neil Armstrong @ 2016-10-04 13:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004134148.23028-1-narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/gpio/gpio_oxnas.txt | 2 +-
Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
index 928ed4f..9665147 100644
--- a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
@@ -3,7 +3,7 @@
Please refer to gpio.txt for generic information regarding GPIO bindings.
Required properties:
- - compatible: "oxsemi,ox810se-gpio"
+ - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
- reg: Base address and length for the device.
- interrupts: The port interrupt shared by all pins.
- gpio-controller: Marks the port as GPIO controller.
diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
index d607432..09e81a9 100644
--- a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
@@ -9,7 +9,7 @@ used for a specific device or function. This node represents configurations of
pins, optional function, and optional mux related configuration.
Required properties for pin controller node:
- - compatible: "oxsemi,ox810se-pinctrl"
+ - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
- oxsemi,sys-ctrl: a phandle to the system controller syscon node
Required properties for pin configuration sub-nodes:
--
2.7.0
^ permalink raw reply related
* [PATCH 2/3] pinctrl: oxnas: Add support for OX820
From: Neil Armstrong @ 2016-10-04 13:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004134148.23028-1-narmstrong@baylibre.com>
Add support for the Oxford Semiconductor OX820 which is similar as OX810 but
has 50 pins and two registers banks to setup alternate functions.
Add specific pins, groups and functions structures.
Add DT match data to select corresponding support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/pinctrl/pinctrl-oxnas.c | 433 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 433 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c
index 218ad48..494ec9a 100644
--- a/drivers/pinctrl/pinctrl-oxnas.c
+++ b/drivers/pinctrl/pinctrl-oxnas.c
@@ -47,6 +47,15 @@
#define PINMUX_810_PULLUP_CTRL0 0xac
#define PINMUX_810_PULLUP_CTRL1 0xb0
+/* OX820 Regmap Offsets */
+#define PINMUX_820_BANK_OFFSET 0x100000
+#define PINMUX_820_SECONDARY_SEL 0x14
+#define PINMUX_820_TERTIARY_SEL 0x8c
+#define PINMUX_820_QUATERNARY_SEL 0x94
+#define PINMUX_820_DEBUG_SEL 0x9c
+#define PINMUX_820_ALTERNATIVE_SEL 0xa4
+#define PINMUX_820_PULLUP_CTRL 0xac
+
/* GPIO Registers */
#define INPUT_VALUE 0x00
#define OUTPUT_EN 0x04
@@ -138,6 +147,59 @@ static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
PINCTRL_PIN(34, "gpio34"),
};
+static const struct pinctrl_pin_desc oxnas_ox820_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+ PINCTRL_PIN(15, "gpio15"),
+ PINCTRL_PIN(16, "gpio16"),
+ PINCTRL_PIN(17, "gpio17"),
+ PINCTRL_PIN(18, "gpio18"),
+ PINCTRL_PIN(19, "gpio19"),
+ PINCTRL_PIN(20, "gpio20"),
+ PINCTRL_PIN(21, "gpio21"),
+ PINCTRL_PIN(22, "gpio22"),
+ PINCTRL_PIN(23, "gpio23"),
+ PINCTRL_PIN(24, "gpio24"),
+ PINCTRL_PIN(25, "gpio25"),
+ PINCTRL_PIN(26, "gpio26"),
+ PINCTRL_PIN(27, "gpio27"),
+ PINCTRL_PIN(28, "gpio28"),
+ PINCTRL_PIN(29, "gpio29"),
+ PINCTRL_PIN(30, "gpio30"),
+ PINCTRL_PIN(31, "gpio31"),
+ PINCTRL_PIN(32, "gpio32"),
+ PINCTRL_PIN(33, "gpio33"),
+ PINCTRL_PIN(34, "gpio34"),
+ PINCTRL_PIN(35, "gpio35"),
+ PINCTRL_PIN(36, "gpio36"),
+ PINCTRL_PIN(37, "gpio37"),
+ PINCTRL_PIN(38, "gpio38"),
+ PINCTRL_PIN(39, "gpio39"),
+ PINCTRL_PIN(40, "gpio40"),
+ PINCTRL_PIN(41, "gpio41"),
+ PINCTRL_PIN(42, "gpio42"),
+ PINCTRL_PIN(43, "gpio43"),
+ PINCTRL_PIN(44, "gpio44"),
+ PINCTRL_PIN(45, "gpio45"),
+ PINCTRL_PIN(46, "gpio46"),
+ PINCTRL_PIN(47, "gpio47"),
+ PINCTRL_PIN(48, "gpio48"),
+ PINCTRL_PIN(49, "gpio49"),
+};
+
static const char * const oxnas_ox810se_fct0_group[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6", "gpio7",
@@ -161,6 +223,40 @@ static const char * const oxnas_ox810se_fct3_group[] = {
"gpio34"
};
+static const char * const oxnas_ox820_fct0_group[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15",
+ "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27",
+ "gpio28", "gpio29", "gpio30", "gpio31",
+ "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42", "gpio43",
+ "gpio44", "gpio45", "gpio46", "gpio47",
+ "gpio48", "gpio49"
+};
+
+static const char * const oxnas_ox820_fct1_group[] = {
+ "gpio3", "gpio4",
+ "gpio12", "gpio13", "gpio14", "gpio15",
+ "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24"
+};
+
+static const char * const oxnas_ox820_fct4_group[] = {
+ "gpio5", "gpio6", "gpio7", "gpio8",
+ "gpio24", "gpio25", "gpio26", "gpio27",
+ "gpio40", "gpio41", "gpio42", "gpio43"
+};
+
+static const char * const oxnas_ox820_fct5_group[] = {
+ "gpio28", "gpio29", "gpio30", "gpio31"
+};
+
#define FUNCTION(_name, _gr) \
{ \
.name = #_name, \
@@ -173,6 +269,13 @@ static const struct oxnas_function oxnas_ox810se_functions[] = {
FUNCTION(fct3, ox810se_fct3),
};
+static const struct oxnas_function oxnas_ox820_functions[] = {
+ FUNCTION(gpio, ox820_fct0),
+ FUNCTION(fct1, ox820_fct1),
+ FUNCTION(fct4, ox820_fct4),
+ FUNCTION(fct5, ox820_fct5),
+};
+
#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \
{ \
.name = #_name, \
@@ -285,6 +388,140 @@ static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
OXNAS_PINCTRL_FUNCTION(fct3, 3)),
};
+static const struct oxnas_pin_group oxnas_ox820_groups[] = {
+ OXNAS_PINCTRL_GROUP(0, gpio0,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(1, gpio1,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(2, gpio2,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(3, gpio3,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(4, gpio4,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(5, gpio5,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(6, gpio6,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(7, gpio7,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(8, gpio8,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(9, gpio9,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(10, gpio10,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(11, gpio11,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(12, gpio12,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(13, gpio13,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(14, gpio14,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(15, gpio15,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(16, gpio16,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(17, gpio17,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(18, gpio18,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(19, gpio19,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(20, gpio20,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(21, gpio21,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(22, gpio22,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(23, gpio23,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1)),
+ OXNAS_PINCTRL_GROUP(24, gpio24,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct1, 1),
+ OXNAS_PINCTRL_FUNCTION(fct4, 5)),
+ OXNAS_PINCTRL_GROUP(25, gpio25,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(26, gpio26,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(27, gpio27,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(28, gpio28,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct5, 5)),
+ OXNAS_PINCTRL_GROUP(29, gpio29,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct5, 5)),
+ OXNAS_PINCTRL_GROUP(30, gpio30,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct5, 5)),
+ OXNAS_PINCTRL_GROUP(31, gpio31,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct5, 5)),
+ OXNAS_PINCTRL_GROUP(32, gpio32,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(33, gpio33,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(34, gpio34,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(35, gpio35,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(36, gpio36,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(37, gpio37,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(38, gpio38,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(39, gpio39,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(40, gpio40,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(41, gpio41,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(42, gpio42,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(43, gpio43,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct4, 4)),
+ OXNAS_PINCTRL_GROUP(44, gpio44,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(45, gpio45,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(46, gpio46,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(47, gpio47,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(48, gpio48,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(49, gpio49,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+};
+
static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
unsigned int pin)
{
@@ -405,6 +642,61 @@ static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
return -EINVAL;
}
+static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev,
+ unsigned int func, unsigned int group)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct oxnas_pin_group *pg = &pctl->groups[group];
+ const struct oxnas_function *pf = &pctl->functions[func];
+ const char *fname = pf->name;
+ struct oxnas_desc_function *functions = pg->functions;
+ unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);
+ u32 mask = BIT(pg->pin);
+
+ while (functions->name) {
+ if (!strcmp(functions->name, fname)) {
+ dev_dbg(pctl->dev,
+ "setting function %s bank %d pin %d fct %d mask %x\n",
+ fname, pg->bank, pg->pin,
+ functions->fct, mask);
+
+ regmap_write_bits(pctl->regmap,
+ offset + PINMUX_820_SECONDARY_SEL,
+ mask,
+ (functions->fct == 1 ?
+ mask : 0));
+ regmap_write_bits(pctl->regmap,
+ offset + PINMUX_820_TERTIARY_SEL,
+ mask,
+ (functions->fct == 2 ?
+ mask : 0));
+ regmap_write_bits(pctl->regmap,
+ offset + PINMUX_820_QUATERNARY_SEL,
+ mask,
+ (functions->fct == 3 ?
+ mask : 0));
+ regmap_write_bits(pctl->regmap,
+ offset + PINMUX_820_DEBUG_SEL,
+ mask,
+ (functions->fct == 4 ?
+ mask : 0));
+ regmap_write_bits(pctl->regmap,
+ offset + PINMUX_820_ALTERNATIVE_SEL,
+ mask,
+ (functions->fct == 5 ?
+ mask : 0));
+
+ return 0;
+ }
+
+ functions++;
+ }
+
+ dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
+
+ return -EINVAL;
+}
+
static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
@@ -435,6 +727,37 @@ static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
return 0;
}
+static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
+ unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
+ u32 mask = BIT(offset - bank->gpio_chip.base);
+
+ dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
+ offset, bank->gpio_chip.base, bank->id, mask);
+
+ regmap_write_bits(pctl->regmap,
+ bank_offset + PINMUX_820_SECONDARY_SEL,
+ mask, 0);
+ regmap_write_bits(pctl->regmap,
+ bank_offset + PINMUX_820_TERTIARY_SEL,
+ mask, 0);
+ regmap_write_bits(pctl->regmap,
+ bank_offset + PINMUX_820_QUATERNARY_SEL,
+ mask, 0);
+ regmap_write_bits(pctl->regmap,
+ bank_offset + PINMUX_820_DEBUG_SEL,
+ mask, 0);
+ regmap_write_bits(pctl->regmap,
+ bank_offset + PINMUX_820_ALTERNATIVE_SEL,
+ mask, 0);
+
+ return 0;
+}
+
static int oxnas_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
@@ -510,6 +833,15 @@ static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
.gpio_set_direction = oxnas_gpio_set_direction,
};
+static const struct pinmux_ops oxnas_ox820_pinmux_ops = {
+ .get_functions_count = oxnas_pinmux_get_functions_count,
+ .get_function_name = oxnas_pinmux_get_function_name,
+ .get_function_groups = oxnas_pinmux_get_function_groups,
+ .set_mux = oxnas_ox820_pinmux_enable,
+ .gpio_request_enable = oxnas_ox820_gpio_request_enable,
+ .gpio_set_direction = oxnas_gpio_set_direction,
+};
+
static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
@@ -541,6 +873,36 @@ static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
+static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
+ unsigned int param = pinconf_to_config_param(*config);
+ unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
+ u32 mask = BIT(pin - bank->gpio_chip.base);
+ int ret;
+ u32 arg;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = regmap_read(pctl->regmap,
+ bank_offset + PINMUX_820_PULLUP_CTRL,
+ &arg);
+ if (ret)
+ return ret;
+
+ arg = !!(arg & mask);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
@@ -579,12 +941,55 @@ static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
+static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
+ unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
+ unsigned int param;
+ u32 arg;
+ unsigned int i;
+ u32 offset = pin - bank->gpio_chip.base;
+ u32 mask = BIT(offset);
+
+ dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
+ pin, bank->gpio_chip.base, mask);
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ dev_dbg(pctl->dev, " pullup\n");
+ regmap_write_bits(pctl->regmap,
+ bank_offset + PINMUX_820_PULLUP_CTRL,
+ mask, mask);
+ break;
+ default:
+ dev_err(pctl->dev, "Property %u not supported\n",
+ param);
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
.pin_config_get = oxnas_ox810se_pinconf_get,
.pin_config_set = oxnas_ox810se_pinconf_set,
.is_generic = true,
};
+static const struct pinconf_ops oxnas_ox820_pinconf_ops = {
+ .pin_config_get = oxnas_ox820_pinconf_get,
+ .pin_config_set = oxnas_ox820_pinconf_set,
+ .is_generic = true,
+};
+
static void oxnas_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
@@ -714,15 +1119,42 @@ static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
.owner = THIS_MODULE,
};
+static struct oxnas_pinctrl ox820_pinctrl = {
+ .functions = oxnas_ox820_functions,
+ .nfunctions = ARRAY_SIZE(oxnas_ox820_functions),
+ .groups = oxnas_ox820_groups,
+ .ngroups = ARRAY_SIZE(oxnas_ox820_groups),
+ .gpio_banks = oxnas_gpio_banks,
+ .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
+};
+
+static struct pinctrl_desc oxnas_ox820_pinctrl_desc = {
+ .name = "oxnas-pinctrl",
+ .pins = oxnas_ox820_pins,
+ .npins = ARRAY_SIZE(oxnas_ox820_pins),
+ .pctlops = &oxnas_pinctrl_ops,
+ .pmxops = &oxnas_ox820_pinmux_ops,
+ .confops = &oxnas_ox820_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
.desc = &oxnas_ox810se_pinctrl_desc,
.pctl = &ox810se_pinctrl,
};
+static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = {
+ .desc = &oxnas_ox820_pinctrl_desc,
+ .pctl = &ox820_pinctrl,
+};
+
static const struct of_device_id oxnas_pinctrl_of_match[] = {
{ .compatible = "oxsemi,ox810se-pinctrl",
.data = &oxnas_ox810se_pinctrl_data
},
+ { .compatible = "oxsemi,ox820-pinctrl",
+ .data = &oxnas_ox820_pinctrl_data,
+ },
{ },
};
@@ -847,6 +1279,7 @@ static struct platform_driver oxnas_pinctrl_driver = {
static const struct of_device_id oxnas_gpio_of_match[] = {
{ .compatible = "oxsemi,ox810se-gpio", },
+ { .compatible = "oxsemi,ox820-gpio", },
{ },
};
--
2.7.0
^ permalink raw reply related
* [PATCH 1/3] pinctrl: oxnas: Move OX810SE specific function and structure as separate
From: Neil Armstrong @ 2016-10-04 13:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004134148.23028-1-narmstrong@baylibre.com>
Add refactoring to move ox810se specific functions into specific ops structures
an add support for the dt match data to get soc specific structures.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/pinctrl/pinctrl-oxnas.c | 176 +++++++++++++++++++++++-----------------
1 file changed, 101 insertions(+), 75 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c
index 917a7d2..218ad48 100644
--- a/drivers/pinctrl/pinctrl-oxnas.c
+++ b/drivers/pinctrl/pinctrl-oxnas.c
@@ -37,15 +37,15 @@
#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
-/* Regmap Offsets */
-#define PINMUX_PRIMARY_SEL0 0x0c
-#define PINMUX_SECONDARY_SEL0 0x14
-#define PINMUX_TERTIARY_SEL0 0x8c
-#define PINMUX_PRIMARY_SEL1 0x10
-#define PINMUX_SECONDARY_SEL1 0x18
-#define PINMUX_TERTIARY_SEL1 0x90
-#define PINMUX_PULLUP_CTRL0 0xac
-#define PINMUX_PULLUP_CTRL1 0xb0
+/* OX810 Regmap Offsets */
+#define PINMUX_810_PRIMARY_SEL0 0x0c
+#define PINMUX_810_SECONDARY_SEL0 0x14
+#define PINMUX_810_TERTIARY_SEL0 0x8c
+#define PINMUX_810_PRIMARY_SEL1 0x10
+#define PINMUX_810_SECONDARY_SEL1 0x18
+#define PINMUX_810_TERTIARY_SEL1 0x90
+#define PINMUX_810_PULLUP_CTRL0 0xac
+#define PINMUX_810_PULLUP_CTRL1 0xb0
/* GPIO Registers */
#define INPUT_VALUE 0x00
@@ -87,8 +87,6 @@ struct oxnas_pinctrl {
struct regmap *regmap;
struct device *dev;
struct pinctrl_dev *pctldev;
- const struct pinctrl_pin_desc *pins;
- unsigned int npins;
const struct oxnas_function *functions;
unsigned int nfunctions;
const struct oxnas_pin_group *groups;
@@ -97,7 +95,12 @@ struct oxnas_pinctrl {
unsigned int nbanks;
};
-static const struct pinctrl_pin_desc oxnas_pins[] = {
+struct oxnas_pinctrl_data {
+ struct pinctrl_desc *desc;
+ struct oxnas_pinctrl *pctl;
+};
+
+static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
@@ -135,7 +138,7 @@ static const struct pinctrl_pin_desc oxnas_pins[] = {
PINCTRL_PIN(34, "gpio34"),
};
-static const char * const oxnas_fct0_group[] = {
+static const char * const oxnas_ox810se_fct0_group[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11",
@@ -147,7 +150,7 @@ static const char * const oxnas_fct0_group[] = {
"gpio32", "gpio33", "gpio34"
};
-static const char * const oxnas_fct3_group[] = {
+static const char * const oxnas_ox810se_fct3_group[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9",
@@ -165,9 +168,9 @@ static const char * const oxnas_fct3_group[] = {
.ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \
}
-static const struct oxnas_function oxnas_functions[] = {
- FUNCTION(gpio, fct0),
- FUNCTION(fct3, fct3),
+static const struct oxnas_function oxnas_ox810se_functions[] = {
+ FUNCTION(gpio, ox810se_fct0),
+ FUNCTION(fct3, ox810se_fct3),
};
#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \
@@ -185,7 +188,7 @@ static const struct oxnas_function oxnas_functions[] = {
.fct = _fct, \
}
-static const struct oxnas_pin_group oxnas_groups[] = {
+static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
OXNAS_PINCTRL_GROUP(0, gpio0,
OXNAS_PINCTRL_FUNCTION(gpio, 0),
OXNAS_PINCTRL_FUNCTION(fct3, 3)),
@@ -352,8 +355,8 @@ static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
return 0;
}
-static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev,
- unsigned int func, unsigned int group)
+static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
+ unsigned int func, unsigned int group)
{
struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct oxnas_pin_group *pg = &pctl->groups[group];
@@ -371,22 +374,22 @@ static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev,
regmap_write_bits(pctl->regmap,
(pg->bank ?
- PINMUX_PRIMARY_SEL1 :
- PINMUX_PRIMARY_SEL0),
+ PINMUX_810_PRIMARY_SEL1 :
+ PINMUX_810_PRIMARY_SEL0),
mask,
(functions->fct == 1 ?
mask : 0));
regmap_write_bits(pctl->regmap,
(pg->bank ?
- PINMUX_SECONDARY_SEL1 :
- PINMUX_SECONDARY_SEL0),
+ PINMUX_810_SECONDARY_SEL1 :
+ PINMUX_810_SECONDARY_SEL0),
mask,
(functions->fct == 2 ?
mask : 0));
regmap_write_bits(pctl->regmap,
(pg->bank ?
- PINMUX_TERTIARY_SEL1 :
- PINMUX_TERTIARY_SEL0),
+ PINMUX_810_TERTIARY_SEL1 :
+ PINMUX_810_TERTIARY_SEL0),
mask,
(functions->fct == 3 ?
mask : 0));
@@ -402,9 +405,9 @@ static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev,
return -EINVAL;
}
-static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int offset)
+static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
{
struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
@@ -415,18 +418,18 @@ static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
regmap_write_bits(pctl->regmap,
(bank->id ?
- PINMUX_PRIMARY_SEL1 :
- PINMUX_PRIMARY_SEL0),
+ PINMUX_810_PRIMARY_SEL1 :
+ PINMUX_810_PRIMARY_SEL0),
mask, 0);
regmap_write_bits(pctl->regmap,
(bank->id ?
- PINMUX_SECONDARY_SEL1 :
- PINMUX_SECONDARY_SEL0),
+ PINMUX_810_SECONDARY_SEL1 :
+ PINMUX_810_SECONDARY_SEL0),
mask, 0);
regmap_write_bits(pctl->regmap,
(bank->id ?
- PINMUX_TERTIARY_SEL1 :
- PINMUX_TERTIARY_SEL0),
+ PINMUX_810_TERTIARY_SEL1 :
+ PINMUX_810_TERTIARY_SEL0),
mask, 0);
return 0;
@@ -498,17 +501,17 @@ static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
return 0;
}
-static const struct pinmux_ops oxnas_pinmux_ops = {
+static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
.get_functions_count = oxnas_pinmux_get_functions_count,
.get_function_name = oxnas_pinmux_get_function_name,
.get_function_groups = oxnas_pinmux_get_function_groups,
- .set_mux = oxnas_pinmux_enable,
- .gpio_request_enable = oxnas_gpio_request_enable,
+ .set_mux = oxnas_ox810se_pinmux_enable,
+ .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
.gpio_set_direction = oxnas_gpio_set_direction,
};
-static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *config)
+static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
{
struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
@@ -521,8 +524,8 @@ static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
case PIN_CONFIG_BIAS_PULL_UP:
ret = regmap_read(pctl->regmap,
(bank->id ?
- PINMUX_PULLUP_CTRL1 :
- PINMUX_PULLUP_CTRL0),
+ PINMUX_810_PULLUP_CTRL1 :
+ PINMUX_810_PULLUP_CTRL0),
&arg);
if (ret)
return ret;
@@ -538,8 +541,9 @@ static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
return 0;
}
-static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *configs, unsigned int num_configs)
+static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *configs,
+ unsigned int num_configs)
{
struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
@@ -561,8 +565,8 @@ static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
dev_dbg(pctl->dev, " pullup\n");
regmap_write_bits(pctl->regmap,
(bank->id ?
- PINMUX_PULLUP_CTRL1 :
- PINMUX_PULLUP_CTRL0),
+ PINMUX_810_PULLUP_CTRL1 :
+ PINMUX_810_PULLUP_CTRL0),
mask, mask);
break;
default:
@@ -575,20 +579,12 @@ static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
return 0;
}
-static const struct pinconf_ops oxnas_pinconf_ops = {
- .pin_config_get = oxnas_pinconf_get,
- .pin_config_set = oxnas_pinconf_set,
+static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
+ .pin_config_get = oxnas_ox810se_pinconf_get,
+ .pin_config_set = oxnas_ox810se_pinconf_set,
.is_generic = true,
};
-static struct pinctrl_desc oxnas_pinctrl_desc = {
- .name = "oxnas-pinctrl",
- .pctlops = &oxnas_pinctrl_ops,
- .pmxops = &oxnas_pinmux_ops,
- .confops = &oxnas_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
static void oxnas_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
@@ -699,10 +695,51 @@ static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
GPIO_BANK(1),
};
+static struct oxnas_pinctrl ox810se_pinctrl = {
+ .functions = oxnas_ox810se_functions,
+ .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
+ .groups = oxnas_ox810se_groups,
+ .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
+ .gpio_banks = oxnas_gpio_banks,
+ .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
+};
+
+static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
+ .name = "oxnas-pinctrl",
+ .pins = oxnas_ox810se_pins,
+ .npins = ARRAY_SIZE(oxnas_ox810se_pins),
+ .pctlops = &oxnas_pinctrl_ops,
+ .pmxops = &oxnas_ox810se_pinmux_ops,
+ .confops = &oxnas_ox810se_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
+ .desc = &oxnas_ox810se_pinctrl_desc,
+ .pctl = &ox810se_pinctrl,
+};
+
+static const struct of_device_id oxnas_pinctrl_of_match[] = {
+ { .compatible = "oxsemi,ox810se-pinctrl",
+ .data = &oxnas_ox810se_pinctrl_data
+ },
+ { },
+};
+
static int oxnas_pinctrl_probe(struct platform_device *pdev)
{
+ const struct of_device_id *id;
+ const struct oxnas_pinctrl_data *data;
struct oxnas_pinctrl *pctl;
+ id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
+ if (!id)
+ return -ENODEV;
+
+ data = id->data;
+ if (!data || !data->pctl || !data->desc)
+ return -EINVAL;
+
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
@@ -716,20 +753,14 @@ static int oxnas_pinctrl_probe(struct platform_device *pdev)
return -ENODEV;
}
- pctl->pins = oxnas_pins;
- pctl->npins = ARRAY_SIZE(oxnas_pins);
- pctl->functions = oxnas_functions;
- pctl->nfunctions = ARRAY_SIZE(oxnas_functions);
- pctl->groups = oxnas_groups;
- pctl->ngroups = ARRAY_SIZE(oxnas_groups);
- pctl->gpio_banks = oxnas_gpio_banks;
- pctl->nbanks = ARRAY_SIZE(oxnas_gpio_banks);
+ pctl->functions = data->pctl->functions;
+ pctl->nfunctions = data->pctl->nfunctions;
+ pctl->groups = data->pctl->groups;
+ pctl->ngroups = data->pctl->ngroups;
+ pctl->gpio_banks = data->pctl->gpio_banks;
+ pctl->nbanks = data->pctl->nbanks;
- oxnas_pinctrl_desc.pins = pctl->pins;
- oxnas_pinctrl_desc.npins = pctl->npins;
-
- pctl->pctldev = pinctrl_register(&oxnas_pinctrl_desc,
- &pdev->dev, pctl);
+ pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
if (IS_ERR(pctl->pctldev)) {
dev_err(&pdev->dev, "Failed to register pinctrl device\n");
return PTR_ERR(pctl->pctldev);
@@ -805,11 +836,6 @@ static int oxnas_gpio_probe(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id oxnas_pinctrl_of_match[] = {
- { .compatible = "oxsemi,ox810se-pinctrl", },
- { },
-};
-
static struct platform_driver oxnas_pinctrl_driver = {
.driver = {
.name = "oxnas-pinctrl",
--
2.7.0
^ permalink raw reply related
* [PATCH 0/3] pinctrl: oxnas: Add Support for OX820
From: Neil Armstrong @ 2016-10-04 13:41 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds support for the Oxford Semiconductor OX820 SoC Pinctrl
registers along he OX810 Pinctrl support.
The GPIO control registers are common enough to leave the code untouched.
Neil Armstrong (3):
pinctrl: oxnas: Move OX810SE specific function and structure as
separate
pinctrl: oxnas: Add support for OX820
dt-bindings: oxnas: Update Pinctrl and GPIO for OX820 Support
.../devicetree/bindings/gpio/gpio_oxnas.txt | 2 +-
.../devicetree/bindings/pinctrl/oxnas,pinctrl.txt | 2 +-
drivers/pinctrl/pinctrl-oxnas.c | 605 ++++++++++++++++++---
3 files changed, 534 insertions(+), 75 deletions(-)
--
2.7.0
^ permalink raw reply
* [PATCH v2 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC
From: Geert Uytterhoeven @ 2016-10-04 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1472046551-703-6-git-send-email-cw00.choi@samsung.com>
On Wed, Aug 24, 2016 at 3:49 PM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> + cluster_a53_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp at 400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-microvolt = <900000>;
> + };
With W=1:
Warning (unit_address_vs_reg): Node /opp_table0/opp at 400000000 has a
unit name, but no reg property
...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] ARM: dts: r8a7794: Fix W=1 dtc warnings
From: Geert Uytterhoeven @ 2016-10-04 13:31 UTC (permalink / raw)
To: linux-arm-kernel
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,dvc/dvc at 0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,dvc/dvc at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,mix/mix at 0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,mix/mix at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ctu/ctu at 7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,src/src at 0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,src/src at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,src/src at 2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,src/src at 3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,src/src at 4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,src/src at 5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,src/src at 6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound at ec500000/rcar_sound,ssi/ssi at 9 has a unit name, but no reg property
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7794.dtsi | 58 +++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index f53c75b2b0d33de2..7bfa57f357d4ad2a 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1502,62 +1502,62 @@
status = "disabled";
rcar_sound,dvc {
- dvc0: dvc at 0 {
+ dvc0: dvc-0 {
dmas = <&audma0 0xbc>;
dma-names = "tx";
};
- dvc1: dvc at 1 {
+ dvc1: dvc-1 {
dmas = <&audma0 0xbe>;
dma-names = "tx";
};
};
rcar_sound,mix {
- mix0: mix at 0 { };
- mix1: mix at 1 { };
+ mix0: mix-0 { };
+ mix1: mix-1 { };
};
rcar_sound,ctu {
- ctu00: ctu at 0 { };
- ctu01: ctu at 1 { };
- ctu02: ctu at 2 { };
- ctu03: ctu at 3 { };
- ctu10: ctu at 4 { };
- ctu11: ctu at 5 { };
- ctu12: ctu at 6 { };
- ctu13: ctu at 7 { };
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
};
rcar_sound,src {
- src at 0 {
+ src-0 {
status = "disabled";
};
- src1: src at 1 {
+ src1: src-1 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x87>, <&audma0 0x9c>;
dma-names = "rx", "tx";
};
- src2: src at 2 {
+ src2: src-2 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x89>, <&audma0 0x9e>;
dma-names = "rx", "tx";
};
- src3: src at 3 {
+ src3: src-3 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8b>, <&audma0 0xa0>;
dma-names = "rx", "tx";
};
- src4: src at 4 {
+ src4: src-4 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8d>, <&audma0 0xb0>;
dma-names = "rx", "tx";
};
- src5: src at 5 {
+ src5: src-5 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma0 0xb2>;
dma-names = "rx", "tx";
};
- src6: src at 6 {
+ src6: src-6 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma0 0xb4>;
dma-names = "rx", "tx";
@@ -1565,61 +1565,61 @@
};
rcar_sound,ssi {
- ssi0: ssi at 0 {
+ ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma0 0x02>,
<&audma0 0x15>, <&audma0 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi1: ssi at 1 {
+ ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma0 0x04>,
<&audma0 0x49>, <&audma0 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi2: ssi at 2 {
+ ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma0 0x06>,
<&audma0 0x63>, <&audma0 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi3: ssi at 3 {
+ ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma0 0x08>,
<&audma0 0x6f>, <&audma0 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi4: ssi at 4 {
+ ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma0 0x0a>,
<&audma0 0x71>, <&audma0 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi5: ssi at 5 {
+ ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma0 0x0c>,
<&audma0 0x73>, <&audma0 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi6: ssi at 6 {
+ ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma0 0x0e>,
<&audma0 0x75>, <&audma0 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi7: ssi at 7 {
+ ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma0 0x10>,
<&audma0 0x79>, <&audma0 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi8: ssi at 8 {
+ ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma0 0x12>,
<&audma0 0x7b>, <&audma0 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi9: ssi at 9 {
+ ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma0 0x14>,
<&audma0 0x7d>, <&audma0 0x7e>;
--
1.9.1
^ permalink raw reply related
* [PATCH v26 0/7] arm64: add kdump support
From: Manish Jaggi @ 2016-10-04 13:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57F38A30.2050200@arm.com>
On 10/04/2016 04:23 PM, James Morse wrote:
> Hi Manish,
>
> On 04/10/16 11:05, Manish Jaggi wrote:
>> On 10/04/2016 03:16 PM, James Morse wrote:
>>> On 03/10/16 13:41, Manish Jaggi wrote:
>>>> On 10/03/2016 04:34 PM, AKASHI Takahiro wrote:
>>>>> On Mon, Oct 03, 2016 at 01:24:34PM +0530, Manish Jaggi wrote:
>>>>>> First kernel is booted with mem=2G crashkernel=1G command line option.
>>>>>> While the system has 64G memory.
>>>
>>>>> Are you saying that "mem=..." doesn't have any effect?
>>>> What I am saying it that If the first kernel is booted using mem= option and crashkernel= option
>>>> the memory for second kernel has to be withing the crashkernel size.
>>>> As per /proc/iomem System RAM the information is correct, but the /proc/meminfo is showing total memory
>>>> much more than the first kernel had in first place.
>>>
>>> So your second crashkernel has 63G of memory? Unless you provide the same 'mem='
>>> to the kdump kernel, this is the expected behaviour. The
>>> DT:/reserved-memory/crash_dump describes the memory not to use.
>>>
>>> On your first boot with 'mem=2G' memblock_mem_limit_remove_map() called from
>>> arm64_memblock_init() removed the top 62G of memory. Neither the first kernel
>>> nor kexec-tools know about the top 62G.
>>> When you run kexec-tools, it describes what it sees in /proc/iomem in the
>>> DT:/reserved-memory/crash_dump, which is just the remaining 1G of memory.
>>>
>>> When we crash and reboot, the crash kernel discovers all 64G of memory from the
>>> EFI memory map.
>
>> So the iomem and meminfo should be same or different for the second kernel?
>> Also i assumed that crashkernel=1G should restrict the second kernels to 1G.
>
> Not with v26 of this series. What should it do with the 62G of memory that was
> removed by booting with 'mem=2G'? It isn't part of the crashkernel reserved
> area, and it isn't part of the vmcore described in elfcorehdr either...
>
>
>> This is my understanding from the description. It should not require a second mem= option
>
>>> kexec-tools described the 1G of memory that the first kernel was using in the
>>> DT:/reserved-memory/crash_dump node, so early_init_fdt_scan_reserved_mem()
>>> reserves the 1G of memory the first kernel used. This leaves us with 63G of memory.
>>>
>>> This may change with the next version of kdump if it switches back to using
>>> DT:/chosen/linux,usable-memory-range.
>>> If you need v26 to avoid the top 62G of memory, you need to provide the same
>>> 'mem=' to the first and second kernel.
>
>> If I provide for second kernel, I dont see any prints after Bye.
>> Have you tired this anytime?
>
> Yes, on juno-r1 passing 'mem=2G' to both the first and second kernel causes only
> the first 2G of memory to be used with this pattern:
> first kernel: [1G used for linux] [1G reserved for Crash kernel] [6G memory
> hidden]
> kdump kernel: [1G vmcore] [1G used for linux] [6G memory hidden]
>
>
Oh, ok!
I was giving mem=1G to crashkernel to test. with mem=2G it works.
>>>>>> 1.2 Live crash dump fails with error
>>>
>>> ... do we expect this to work? I don't think it has anything to do with this
>>> series...
>>>
>> Why it should not?
>> I saved the vmcore file while in second kernel. Since crash without vmcore file didnt run,
>> Tried with vmcore file and it worked. Its just that if you want to boot a second kernel
>> with read only file system without network live crash dump analysis is handy.
>
> Ah, you want to run /usr/bin/crash with the kdump boot of linux. You still need
> to tell it where to find the memory image: "crash /path/to/vmlinux /proc/vmcore"
> should do the trick.
>
We should fix the documentation of kdump them.
Since it is not supported, it should be removed.
>
> Thanks,
>
> James
>
^ permalink raw reply
* [PATCH 2/2] ARM: shmobile: r8a7793/gose: Add board part number to DT bindings
From: Geert Uytterhoeven @ 2016-10-04 13:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475587248-13670-1-git-send-email-geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 6c3ffc2ebeaa346a..18a20a7689c52342 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -47,7 +47,7 @@ Boards:
compatible = "renesas,bockw", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- - Gose
+ - Gose (RTP0RC7793SEB00010S)
compatible = "renesas,gose", "renesas,r8a7793"
- H3ULCB (RTP0RC7795SKB00010S)
compatible = "renesas,h3ulcb", "renesas,r8a7795";
--
1.9.1
^ permalink raw reply related
* [PATCH 1/2] ARM: shmobile: r8a7794/alt: Add board part number to DT bindings
From: Geert Uytterhoeven @ 2016-10-04 13:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475587248-13670-1-git-send-email-geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 19f0a9e4302b508c..6c3ffc2ebeaa346a 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -35,7 +35,7 @@ SoCs:
Boards:
- - Alt
+ - Alt (RTP0RC7794SEB00010S)
compatible = "renesas,alt", "renesas,r8a7794"
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
--
1.9.1
^ permalink raw reply related
* [PATCH 0/2] ARM: shmobile: alt/gose: Add board part number to DT bindings
From: Geert Uytterhoeven @ 2016-10-04 13:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon, Magnus,
This series at the missing board part numbers for r8a7794/alt and
r8a7793/gose to the DT binding documentation, like is done for the other
boards.
Thanks for applying!
Geert Uytterhoeven (2):
ARM: shmobile: r8a7794/alt: Add board part number to DT bindings
ARM: shmobile: r8a7793/gose: Add board part number to DT bindings
Documentation/devicetree/bindings/arm/shmobile.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v3 1/2] crypto: marvell - Use an unique pool to copy results of requests
From: Boris Brezillon @ 2016-10-04 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004125720.3347-2-romain.perier@free-electrons.com>
On Tue, 4 Oct 2016 14:57:19 +0200
Romain Perier <romain.perier@free-electrons.com> wrote:
> So far, we used a dedicated dma pool to copy the result of outer IV for
> cipher requests. Instead of using a dma pool per outer data, we prefer
> use the op dma pool that contains all part of the request from the SRAM.
> Then, the outer data that is likely to be used by the 'complete'
> operation, is copied later. In this way, any type of result can be
> retrieved by DMA for cipher or ahash requests.
>
> Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
> ---
>
> Changes in v3:
> - Don't allocate a new op ctx for the last tdma descriptor. Instead
> we point to the last op ctx in the tdma chain, and copy the context
> of the current request to this location.
>
> Changes in v2:
> - Use the dma pool "op" to retrieve outer data intead of introducing
> a new one.
>
> drivers/crypto/marvell/cesa.c | 4 ----
> drivers/crypto/marvell/cesa.h | 5 ++---
> drivers/crypto/marvell/cipher.c | 8 +++++---
> drivers/crypto/marvell/tdma.c | 28 ++++++++++++++--------------
> 4 files changed, 21 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
> index 37dadb2..6e7a5c7 100644
> --- a/drivers/crypto/marvell/cesa.c
> +++ b/drivers/crypto/marvell/cesa.c
> @@ -375,10 +375,6 @@ static int mv_cesa_dev_dma_init(struct mv_cesa_dev *cesa)
> if (!dma->padding_pool)
> return -ENOMEM;
>
> - dma->iv_pool = dmam_pool_create("cesa_iv", dev, 16, 1, 0);
> - if (!dma->iv_pool)
> - return -ENOMEM;
> -
> cesa->dma = dma;
>
> return 0;
> diff --git a/drivers/crypto/marvell/cesa.h b/drivers/crypto/marvell/cesa.h
> index e423d33..a768da7 100644
> --- a/drivers/crypto/marvell/cesa.h
> +++ b/drivers/crypto/marvell/cesa.h
> @@ -277,7 +277,7 @@ struct mv_cesa_op_ctx {
> #define CESA_TDMA_DUMMY 0
> #define CESA_TDMA_DATA 1
> #define CESA_TDMA_OP 2
> -#define CESA_TDMA_IV 3
> +#define CESA_TDMA_RESULT 3
>
> /**
> * struct mv_cesa_tdma_desc - TDMA descriptor
> @@ -393,7 +393,6 @@ struct mv_cesa_dev_dma {
> struct dma_pool *op_pool;
> struct dma_pool *cache_pool;
> struct dma_pool *padding_pool;
> - struct dma_pool *iv_pool;
> };
>
> /**
> @@ -839,7 +838,7 @@ mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
> memset(chain, 0, sizeof(*chain));
> }
>
> -int mv_cesa_dma_add_iv_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
> +int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
> u32 size, u32 flags, gfp_t gfp_flags);
>
> struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
> diff --git a/drivers/crypto/marvell/cipher.c b/drivers/crypto/marvell/cipher.c
> index d19dc96..098871a 100644
> --- a/drivers/crypto/marvell/cipher.c
> +++ b/drivers/crypto/marvell/cipher.c
> @@ -212,7 +212,8 @@ mv_cesa_ablkcipher_complete(struct crypto_async_request *req)
> struct mv_cesa_req *basereq;
>
> basereq = &creq->base;
> - memcpy(ablkreq->info, basereq->chain.last->data, ivsize);
> + memcpy(ablkreq->info, basereq->chain.last->op->ctx.blkcipher.iv,
> + ivsize);
> } else {
> memcpy_fromio(ablkreq->info,
> engine->sram + CESA_SA_CRYPT_IV_SRAM_OFFSET,
> @@ -373,8 +374,9 @@ static int mv_cesa_ablkcipher_dma_req_init(struct ablkcipher_request *req,
>
> /* Add output data for IV */
> ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
> - ret = mv_cesa_dma_add_iv_op(&basereq->chain, CESA_SA_CRYPT_IV_SRAM_OFFSET,
> - ivsize, CESA_TDMA_SRC_IN_SRAM, flags);
> + ret = mv_cesa_dma_add_result_op(&basereq->chain, CESA_SA_CFG_SRAM_OFFSET,
> + CESA_SA_DATA_SRAM_OFFSET,
> + CESA_TDMA_SRC_IN_SRAM, flags);
>
> if (ret)
> goto err_free_tdma;
> diff --git a/drivers/crypto/marvell/tdma.c b/drivers/crypto/marvell/tdma.c
> index 9fd7a5f..991dc3f 100644
> --- a/drivers/crypto/marvell/tdma.c
> +++ b/drivers/crypto/marvell/tdma.c
> @@ -69,9 +69,6 @@ void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq)
> if (type == CESA_TDMA_OP)
> dma_pool_free(cesa_dev->dma->op_pool, tdma->op,
> le32_to_cpu(tdma->src));
> - else if (type == CESA_TDMA_IV)
> - dma_pool_free(cesa_dev->dma->iv_pool, tdma->data,
> - le32_to_cpu(tdma->dst));
>
> tdma = tdma->next;
> dma_pool_free(cesa_dev->dma->tdma_desc_pool, old_tdma,
> @@ -209,29 +206,32 @@ mv_cesa_dma_add_desc(struct mv_cesa_tdma_chain *chain, gfp_t flags)
> return new_tdma;
> }
>
> -int mv_cesa_dma_add_iv_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
> +int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
> u32 size, u32 flags, gfp_t gfp_flags)
> {
> -
> - struct mv_cesa_tdma_desc *tdma;
> - u8 *iv;
> - dma_addr_t dma_handle;
> + struct mv_cesa_tdma_desc *tdma, *op_desc;
>
> tdma = mv_cesa_dma_add_desc(chain, gfp_flags);
> if (IS_ERR(tdma))
> return PTR_ERR(tdma);
>
> - iv = dma_pool_alloc(cesa_dev->dma->iv_pool, gfp_flags, &dma_handle);
> - if (!iv)
> - return -ENOMEM;
Can you add a comment explaining what you're doing here?
/* We re-use an existing op_desc object to retrieve the context
* and result instead of allocating a new one.
* There is at least one object of this type in a CESA crypto
* req, just pick the first one in the chain.
*/
Once this is addressed, you can add my
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> + for (op_desc = chain->first; op_desc; op_desc = op_desc->next) {
> + u32 type = op_desc->flags & CESA_TDMA_TYPE_MSK;
> +
> + if (type == CESA_TDMA_OP)
> + break;
> + }
> +
> + if (!op_desc)
> + return -EIO;
>
> tdma->byte_cnt = cpu_to_le32(size | BIT(31));
> tdma->src = src;
> - tdma->dst = cpu_to_le32(dma_handle);
> - tdma->data = iv;
> + tdma->dst = op_desc->src;
> + tdma->op = op_desc->op;
>
> flags &= (CESA_TDMA_DST_IN_SRAM | CESA_TDMA_SRC_IN_SRAM);
> - tdma->flags = flags | CESA_TDMA_IV;
> + tdma->flags = flags | CESA_TDMA_RESULT;
> return 0;
> }
>
^ permalink raw reply
* [PATCH 06/14] ASoC: Add sun8i digital audio codec
From: Thomas Petazzoni @ 2016-10-04 13:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004130727.srmaielkvd2z5k3s@sirena.org.uk>
Hello,
On Tue, 4 Oct 2016 15:07:27 +0200, Mark Brown wrote:
> > /*
> > * ...
> > */
>
> I don't care, IIRC that's something from CodingStyle which checkpatch
> moans about.
Correct. The
/* ..
* ..
*/
style is mandatory for net/ and crypto code, but not in the rest of the
kernel.
> > I'm probably missing something, but in the sun4i-codec.c driver, those
> > fields are initialized directly in the snd_soc_codec_driver structure,
> > not in the .component_driver sub-structure.
>
> We're in the process of pushing everything out to component level, this
> update should be made in the old code if it's not happened already.
OK.
> > > + if (clk_prepare_enable(scodec->clk_module))
> > > + pr_err("err:open failed;\n");
>
> > Grr, pr_err, not good. Plus you want to return with an error from the
> > probe() function.
>
> Also when printing an error message use dev_err().
That's why I said "Grr, pr_err, not good" :)
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 4/4] ARM: dts: dra72-evm-revc: fix correct phy delay
From: Andrew Lunn @ 2016-10-04 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004125607.10569-5-mugunthanvnm@ti.com>
On Tue, Oct 04, 2016 at 06:26:07PM +0530, Mugunthan V N wrote:
> The current delay settings of the phy are not the optimal value,
> fix it with correct values.
This should be a separate patch, since it has nothing to do with impedance.
Andrew
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
> arch/arm/boot/dts/dra72-evm-revc.dts | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
> index d626cd7..8472a8c 100644
> --- a/arch/arm/boot/dts/dra72-evm-revc.dts
> +++ b/arch/arm/boot/dts/dra72-evm-revc.dts
> @@ -59,16 +59,16 @@
> &davinci_mdio {
> dp83867_0: ethernet-phy at 2 {
> reg = <2>;
> - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> - ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
> ti,min-output-imepdance;
> };
>
> dp83867_1: ethernet-phy at 3 {
> reg = <3>;
> - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> - ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
> ti,min-output-imepdance;
> };
> --
> 2.10.0.372.g6fe1b14
>
^ permalink raw reply
* [PATCH v2 3/4] ARM: dts: dra72-evm-revc: fix correct phy delay and impedance settings
From: Andrew Lunn @ 2016-10-04 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004125607.10569-4-mugunthanvnm@ti.com>
On Tue, Oct 04, 2016 at 06:26:06PM +0530, Mugunthan V N wrote:
> The default impedance settings of the phy is not the optimal
> value, due to this the second ethernet is not working. Fix it
> with correct values which makes the second ethernet port to work.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
> arch/arm/boot/dts/dra72-evm-revc.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
> index f9cfd3b..d626cd7 100644
> --- a/arch/arm/boot/dts/dra72-evm-revc.dts
> +++ b/arch/arm/boot/dts/dra72-evm-revc.dts
> @@ -62,6 +62,7 @@
> ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
> + ti,min-output-imepdance;
And there is my answer :-(
Andrew
^ permalink raw reply
* [PATCH v2 3/4] ARM: dts: dra72-evm-revc: fix correct phy delay and impedance settings
From: Lokesh Vutla @ 2016-10-04 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004125607.10569-4-mugunthanvnm@ti.com>
On Tuesday 04 October 2016 06:26 PM, Mugunthan V N wrote:
> The default impedance settings of the phy is not the optimal
> value, due to this the second ethernet is not working. Fix it
> with correct values which makes the second ethernet port to work.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
> arch/arm/boot/dts/dra72-evm-revc.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
> index f9cfd3b..d626cd7 100644
> --- a/arch/arm/boot/dts/dra72-evm-revc.dts
> +++ b/arch/arm/boot/dts/dra72-evm-revc.dts
> @@ -62,6 +62,7 @@
> ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
> + ti,min-output-imepdance;
s/imepdance/impedance
> };
>
> dp83867_1: ethernet-phy at 3 {
> @@ -69,5 +70,6 @@
> ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
> + ti,min-output-imepdance;
same here.
Thanks and regards,
Lokesh
> };
> };
>
^ permalink raw reply
* [PATCH v2 2/4] net: phy: dp83867: add support for MAC impedance configuration
From: Andrew Lunn @ 2016-10-04 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004125607.10569-3-mugunthanvnm@ti.com>
> + if (of_property_read_bool(of_node, "ti,max-output-imepdance"))
> + dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
> + else if (of_property_read_bool(of_node, "ti,min-output-imepdance"))
Did you really test this? Or did you make the same typos in your device
tree file?
Andrew
^ permalink raw reply
* [PATCH v2 2/4] net: phy: dp83867: add support for MAC impedance configuration
From: Lokesh Vutla @ 2016-10-04 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004125607.10569-3-mugunthanvnm@ti.com>
On Tuesday 04 October 2016 06:26 PM, Mugunthan V N wrote:
> Add support for programmable MAC impedance configuration
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
> drivers/net/phy/dp83867.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index 91177a4..795ae17 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -33,6 +33,7 @@
> /* Extended Registers */
> #define DP83867_RGMIICTL 0x0032
> #define DP83867_RGMIIDCTL 0x0086
> +#define DP83867_IO_MUX_CFG 0x0170
>
> #define DP83867_SW_RESET BIT(15)
> #define DP83867_SW_RESTART BIT(14)
> @@ -62,10 +63,17 @@
> /* RGMIIDCTL bits */
> #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
>
> +/* IO_MUX_CFG bits */
> +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
> +
> +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
> +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
> +
> struct dp83867_private {
> int rx_id_delay;
> int tx_id_delay;
> int fifo_depth;
> + int io_impedance;
> };
>
> static int dp83867_ack_interrupt(struct phy_device *phydev)
> @@ -111,6 +119,14 @@ static int dp83867_of_init(struct phy_device *phydev)
> if (!of_node)
> return -ENODEV;
>
> + dp83867->io_impedance = -EINVAL;
> +
> + /* Optional configuration */
> + if (of_property_read_bool(of_node, "ti,max-output-imepdance"))
s/imepdance/impedance
> + dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
> + else if (of_property_read_bool(of_node, "ti,min-output-imepdance"))
s/imepdance/impedance
Thanks and regards,
Lokesh
> + dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
> +
> ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
> &dp83867->rx_id_delay);
> if (ret)
> @@ -184,6 +200,18 @@ static int dp83867_config_init(struct phy_device *phydev)
>
> phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
> DP83867_DEVADDR, delay);
> +
> + if (dp83867->io_impedance >= 0) {
> + val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
> + DP83867_DEVADDR);
> +
> + val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
> + val |= dp83867->io_impedance &
> + DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
> +
> + phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
> + DP83867_DEVADDR, val);
> + }
> }
>
> return 0;
>
^ permalink raw reply
* [PATCH 06/14] ASoC: Add sun8i digital audio codec
From: Mark Brown @ 2016-10-04 13:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004144008.0d07d18c@free-electrons.com>
On Tue, Oct 04, 2016 at 02:40:08PM +0200, Thomas Petazzoni wrote:
> > +/* CODEC_OFFSET represents the offset of the codec registers
> > + * and not all the DAI registers
> > + */
> This is not the proper comment style I believe for audio code, it
> should be:
> /*
> * ...
> */
I don't care, IIRC that's something from CodingStyle which checkpatch
moans about.
> > + /* pcm operations */
> > + .ops = &sun8i_codec_dai_ops,
> > +};
> > +EXPORT_SYMBOL(sun8i_codec_dai);
> This EXPORT_SYMBOL looks wrong. First because it doesn't seem to be
> used outside of this module. And second because using EXPORT_SYMBOL on
> a function defined as static doesn't make much sense, as the "static"
> qualifier limits the visibility of the symbol to the current
> compilation unit.
Also all the ASoC code is _GPL so a non-GPL export is an issue.
> > + .component_driver = {
> > + .dapm_widgets = sun8i_codec_dapm_widgets,
> > + .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets),
> > + .dapm_routes = sun8i_codec_dapm_routes,
> > + .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes),
> I'm probably missing something, but in the sun4i-codec.c driver, those
> fields are initialized directly in the snd_soc_codec_driver structure,
> not in the .component_driver sub-structure.
We're in the process of pushing everything out to component level, this
update should be made in the old code if it's not happened already.
> > + if (clk_prepare_enable(scodec->clk_module))
> > + pr_err("err:open failed;\n");
> Grr, pr_err, not good. Plus you want to return with an error from the
> probe() function.
Also when printing an error message use dev_err().
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