* [PATCH] ARM: dts: fix naming of pinctrl node
From: Ray Jui @ 2016-10-08 21:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475958866-15942-1-git-send-email-scott.branden@broadcom.com>
On 10/8/2016 1:34 PM, Scott Branden wrote:
> Remove 0x from pinctrl node to match device tree naming convention.
>
> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
> ---
> arch/arm/boot/dts/bcm-cygnus.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
> index fabc9f3..539c58f 100644
> --- a/arch/arm/boot/dts/bcm-cygnus.dtsi
> +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
> @@ -108,7 +108,7 @@
> };
> };
>
> - pinctrl: pinctrl at 0x0301d0c8 {
> + pinctrl: pinctrl at 0301d0c8 {
> compatible = "brcm,cygnus-pinmux";
> reg = <0x0301d0c8 0x30>,
> <0x0301d24c 0x2c>;
>
Looks good to me!
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
^ permalink raw reply
* [PATCH v3 03/11] ARM: shmobile: r8a7743: basic SoC support
From: Laurent Pinchart @ 2016-10-08 21:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161008023149.GB14617@verge.net.au>
Hi Simon,
On Saturday 08 Oct 2016 11:31:50 Simon Horman wrote:
> On Fri, Oct 07, 2016 at 11:33:33AM +0300, Laurent Pinchart wrote:
> > On Friday 07 Oct 2016 12:15:37 Simon Horman wrote:
> >> On Thu, Oct 06, 2016 at 12:37:08AM +0300, Sergei Shtylyov wrote:
> >>> Add minimal support for the RZ/G1M (R8A7743) SoC.
> >>>
> >>> Based on the original (and large) patch by Dmitry Shifrin
> >>> <dmitry.shifrin@cogentembedded.com>.
> >>>
> >>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >>
> >> Thanks, I have queued this up.
> >
> > I'd like to see this patch rebased on top of "[PATCH] ARM: shmobile:
> > Consolidate R8A779[234] machine definitions".
>
> I'm happy to drop this patch if that is the desired outcome of
> the discussion in this sub-thread.
It's at least my desired outcome ;-)
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH 3/3] bindings: add compatible "fsl, ls1043-ucc-hdlc" to bindings
From: Rob Herring @ 2016-10-08 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475034038-7217-3-git-send-email-qiang.zhao@nxp.com>
On Wed, Sep 28, 2016 at 11:40:38AM +0800, Zhao Qiang wrote:
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> ---
> Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt
> index 03c7416..325e3e2 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt
> @@ -45,7 +45,7 @@ Example:
> * HDLC
>
> Currently defined compatibles:
> -- fsl,ucc-hdlc
> +- "fsl,ucc-hdlc", "fsl,ls1043-ucc-hdlc"
What's the relationship of these 2 compatibles? Both should be specified
for LS1043 or ...? The former only applies to certain SoCs? Rework this
text to answer these questions.
Rob
^ permalink raw reply
* Re: [PATCH v5] drm/fsl-dcu: Implement gamma_lut atomic crtc properties
From: Rob Herring @ 2016-10-08 22:26 UTC (permalink / raw)
To: Meng Yi, linux-arm-kernel; +Cc: stefan
In-Reply-To: <1475051069-24452-1-git-send-email-meng.yi@nxp.com>
On Wed, Sep 28, 2016 at 04:24:29PM +0800, Meng Yi wrote:
> Gamma correction is optional and can be used to adjust the color
> output values to match the gamut of a particular TFT LCD panel
>
> Split the DCU regs into "regs", "palette", "gamma" and "cursor".
> Create a second regmap for gamma memory space using little endian.
> The registers after the first address space are not accessed yet,
> hence new device trees would even work with old kernels. Just new
> kernel need the new format so we can access the separate gamma
> reg space.
>
> Suggested-by: Stefan Agner <stefan@agner.ch>
> Signed-off-by: Meng Yi <meng.yi@nxp.com>
> ---
> Changes since V1:
> -created a second regmap for gamma
> -updated the DCU DT binding
> -removed Kconfig for gamma and enable gamma when valid data filled.
> -extended and simplified comment lines.
> ---
> .../devicetree/bindings/display/fsl,dcu.txt | 12 +++++++-
Acked-by: Rob Herring <robh@kernel.org>
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 33 ++++++++++++++++++++
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 35 +++++++++++++++++++++-
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 7 +++++
> 4 files changed, 85 insertions(+), 2 deletions(-)
^ permalink raw reply
* Re: [PATCH] usb: xhci: add support for performing fake doorbell
From: Rob Herring @ 2016-10-08 22:32 UTC (permalink / raw)
To: Rafał Miłecki, linux-arm-kernel
Cc: Greg Kroah-Hartman, Hauke Mehrtens, Rafał Miłecki,
Mark Rutland, Mathias Nyman, open list:USB SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20161001215817.25384-1-zajec5@gmail.com>
On Sat, Oct 01, 2016 at 11:58:10PM +0200, Rafa?? Mi??ecki wrote:
> From: Rafa?? Mi??ecki <rafal@milecki.pl>
>
> Broadcom's Northstar XHCI controllers seem to need a special start
> procedure to work correctly. There isn't any official documentation on
> this, the problem is that controller doesn't detect any connected
> devices with default setup. Moreover connecting USB device to controller
> that doesn't run properly can cause SoC's watchdog issues.
>
> A workaround that was successfully tested on multiple devices is to
> perform a fake doorbell. This patch adds code for doing that and a DT
> binding enabling it.
>
> Signed-off-by: Rafa?? Mi??ecki <rafal@milecki.pl>
> ---
> Documentation/devicetree/bindings/usb/usb-xhci.txt | 2 +
> drivers/usb/host/xhci-plat.c | 6 +++
> drivers/usb/host/xhci.c | 63 ++++++++++++++++++++--
> drivers/usb/host/xhci.h | 1 +
> 4 files changed, 69 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> index 966885c..ce01b7f 100644
> --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
> +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> @@ -26,6 +26,8 @@ Required properties:
> Optional properties:
> - clocks: reference to a clock
> - usb3-lpm-capable: determines if platform is USB3 LPM capable
> + - usb3-fake-doorbell: determines if controller requires a fake doorbell when
> + starting it
You should use Northstar XHCI compatible string to enable this. Then the
DT doesn't need updating.
Rob
^ permalink raw reply
* Re: [RFC V2 PATCH 04/12] dt-bindings: qcom: Add msm8992 bindings
From: Rob Herring @ 2016-10-08 22:41 UTC (permalink / raw)
To: Jeremy McNicoll, linux-arm-kernel; +Cc: andy.gross
In-Reply-To: <1475375919-618-5-git-send-email-jmcnicol@redhat.com>
On Sat, Oct 01, 2016 at 07:38:31PM -0700, Jeremy McNicoll wrote:
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
> index 3e24518..fc5d5ee 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.txt
> +++ b/Documentation/devicetree/bindings/arm/qcom.txt
> @@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings:
> msm8916
> msm8974
> msm8996
> + msm8992
What about 8994 and 8994v2?
>
> The 'board' element must be one of the following strings:
>
> --
> 2.6.1
>
^ permalink raw reply
* Re: [PATCH v7 1/3] Documentation: dt: net: add ath9k wireless device binding
From: Rob Herring @ 2016-10-08 22:50 UTC (permalink / raw)
To: Martin Blumenstingl, linux-arm-kernel; +Cc: ath9k-devel
In-Reply-To: <20161002214743.2263-2-martin.blumenstingl@googlemail.com>
On Sun, Oct 02, 2016 at 11:47:41PM +0200, Martin Blumenstingl wrote:
> Add documentation how devicetree can be used to configure ath9k based
> devices.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> .../devicetree/bindings/net/wireless/qca,ath9k.txt | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt
>
> diff --git a/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt b/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt
> new file mode 100644
> index 0000000..9b58ede
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt
> @@ -0,0 +1,30 @@
> +* Qualcomm Atheros ath9k wireless devices
> +
> +This node provides properties for configuring the ath9k wireless device. The
> +node is expected to be specified as a child node of the PCI controller to
> +which the wireless chip is connected.
> +
> +Required properties:
> +- compatible: For PCI and PCIe devices this should be an identifier following
> + the format as defined in "PCI Bus Binding to Open Firmware"
> + Revision 2.1. One of the possible formats is "pciVVVV,DDDD"
> + where VVVV is the PCI vendor ID and DDDD is PCI device ID.
Are there some known values you can document here? Like the one in the
example.
> +- reg: Address and length of the register set for the device.
> +
> +Optional properties:
> +- qca,no-eeprom: Indicates that there is no physical EEPROM connected to the
> + ath9k wireless chip (in this case the calibration /
> + EEPROM data will be loaded from userspace using the
> + kernel firmware loader).
> +- mac-address: See ethernet.txt in the parent directory
> +- local-mac-address: See ethernet.txt in the parent directory
> +
> +
> +In this example, the node is defined as child node of the PCI controller:
> +&pci0 {
> + ath9k at 168c,002d {
wifi at ...
> + compatible = "pci168c,002d";
> + reg = <0x7000 0 0 0 0x1000>;
> + qca,no-eeprom;
> + };
> +};
> --
> 2.10.0
>
^ permalink raw reply
* Re: [PATCH v3] drm: tilcdc: add a da850-specific compatible string
From: Rob Herring @ 2016-10-08 23:15 UTC (permalink / raw)
To: Bartosz Golaszewski, linux-arm-kernel
Cc: Jyri Sarha, Tomi Valkeinen, David Airlie, Kevin Hilman,
Michael Turquette, Sekhar Nori, Frank Rowand, Mark Rutland, LKML,
arm-soc, linux-drm, linux-devicetree
In-Reply-To: <1475509519-29516-1-git-send-email-bgolaszewski@baylibre.com>
On Mon, Oct 03, 2016 at 05:45:19PM +0200, Bartosz Golaszewski wrote:
> Due to some potential tweaks for the da850 LCDC (for example: the
> required memory bandwith settings) we need a separate compatible
> for the IP present on the da850 boards.
>
> Suggested-by: Sekhar Nori <nsekhar@ti.com>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> v1 -> v2:
> - added the new compatible to the bindings documentation
>
> v2 -> v3:
> - made the documentation more detailed
>
> Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt | 6 ++++--
> drivers/gpu/drm/tilcdc/tilcdc_drv.c | 1 +
> 2 files changed, 5 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 3/3] dt-bindings: oxnas: Update Pinctrl and GPIO for OX820 Support
From: Rob Herring @ 2016-10-08 23:29 UTC (permalink / raw)
To: Neil Armstrong, linux-arm-kernel; +Cc: linus.walleij
In-Reply-To: <20161004134148.23028-4-narmstrong@baylibre.com>
On Tue, Oct 04, 2016 at 03:41:48PM +0200, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Documentation/devicetree/bindings/gpio/gpio_oxnas.txt | 2 +-
> Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
> index 928ed4f..9665147 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
> @@ -3,7 +3,7 @@
> Please refer to gpio.txt for generic information regarding GPIO bindings.
>
> Required properties:
> - - compatible: "oxsemi,ox810se-gpio"
> + - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
It is preferred to have one per line, but it's fine unless you respin
the series.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [RFC 05/10] dt-bindings: pinctrl: meson: update gpio dt-bindings
From: Rob Herring @ 2016-10-08 23:33 UTC (permalink / raw)
To: Jerome Brunet, linux-arm-kernel
Cc: Kevin Hilman, Carlo Caione, Thomas Gleixner, Jason Cooper,
Marc Zyngier, linux-amlogic
In-Reply-To: <1475593708-10526-6-git-send-email-jbrunet@baylibre.com>
On Tue, Oct 04, 2016 at 05:08:23PM +0200, Jerome Brunet wrote:
> Add description for the interrupt-parent property of the gpio sub-node
> If provided here, this property must be a phandle to an interrupt
> controller suitable for meson pinctrl, like the meson gpio interrupt
> controller.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 4 ++++
> 1 file changed, 4 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH] clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init
From: Shawn Guo @ 2016-10-09 0:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475933892-16021-1-git-send-email-shawn.guo@linaro.org>
On Sat, Oct 08, 2016 at 09:38:12PM +0800, Shawn Guo wrote:
> The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
> also reset controller. It worked fine that single sysctrl/mediactrl
> device node in DT can be used to initialize clock driver and populate
> platform device for reset controller. But it stops working after
> commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
> gets merged. The commit sets flag OF_POPULATED during clock
> initialization to skip the platform device populating for the same
> device node. On hi6220, it effectively makes hi6220-sysctrl reset
> driver not probe any more.
>
> The patch changes hi6220 sysctrl and mediactrl clock init macro from
> CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using
> the same hardware block can continue working.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> It fixes an issue that is seen on linux-next, i.e. the new added
> hi6220-sysctrl reset driver doesn't probe at all, and consequently the
> mmc driver fails to register.
Correction: the hi6220-sysctrl has been there for a while, and the issue
is discovered by mmc driver which adds reset support recently. So
technically, this is a regression fix.
Shawn
^ permalink raw reply
* [PATCH 3/3] bindings: add compatible "fsl, ls1043-ucc-hdlc" to bindings
From: Rob Herring @ 2016-10-09 1:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475034038-7217-3-git-send-email-qiang.zhao@nxp.com>
On Wed, Sep 28, 2016 at 11:40:38AM +0800, Zhao Qiang wrote:
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> ---
> Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt
> index 03c7416..325e3e2 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt
> @@ -45,7 +45,7 @@ Example:
> * HDLC
>
> Currently defined compatibles:
> -- fsl,ucc-hdlc
> +- "fsl,ucc-hdlc", "fsl,ls1043-ucc-hdlc"
What's the relationship of these 2 compatibles? Both should be specified
for LS1043 or ...? The former only applies to certain SoCs? Rework this
text to answer these questions.
Rob
^ permalink raw reply
* [PATCH v3 1/3] Documentation: dt-bindings: update the meson-usb2-phy example
From: Rob Herring @ 2016-10-09 1:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161001121900.1168-2-martin.blumenstingl@googlemail.com>
On Sat, Oct 01, 2016 at 02:18:58PM +0200, Martin Blumenstingl wrote:
> Update the example so the node name uses a dash (instead of an
> underscore) as per convention.
> Additionally it updates the example register offset to a real example
> (the old value was taken from a draft where there was an additional PHY
> bus).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> Documentation/devicetree/bindings/phy/meson-usb2-phy.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 2/3] Documentation: dt-bindings: rename meson-usb2-phy to meson8b-usb2-phy
From: Rob Herring @ 2016-10-09 1:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161001121900.1168-3-martin.blumenstingl@googlemail.com>
On Sat, Oct 01, 2016 at 02:18:59PM +0200, Martin Blumenstingl wrote:
> The corresponding driver only supports the USB PHY on Meson8b and GXBB
> SoCs. Newer SoC versions are using a different USB PHY implementation,
> which will mean that a new driver is required. Thus make sure that our
> naming is specific enough so it does not conflict with upcoming drivers.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> .../bindings/phy/{meson-usb2-phy.txt => meson8b-usb2-phy.txt} | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> rename Documentation/devicetree/bindings/phy/{meson-usb2-phy.txt => meson8b-usb2-phy.txt} (95%)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH 05/12] ASoC: sun4i-codec: Add support for A31 playback through headphone output
From: Rob Herring @ 2016-10-09 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161003110804.28235-6-wens@csie.org>
On Mon, Oct 03, 2016 at 07:07:57PM +0800, Chen-Yu Tsai wrote:
> The A31 has a similar codec to the A10/A20. The PCM parts are very
> similar, with just different register offsets. The analog paths are
> very different. There are more inputs and outputs.
>
> The quirks structure is expanded to include different register offsets
> and separate callbacks for creating the ASoC card. Also the DMA burst
> length is increased to 8. While the A10 DMA engine supports bursts of
> 1, 4 and 8, the A31 engine only supports 1 and 8.
>
> This patch adds support for the basic playback path of the A31 codec,
> from the DAC to the headphones. Headphone detection, microphone,
> signaling, other inputs/outputs and capture will be added later.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> .../devicetree/bindings/sound/sun4i-codec.txt | 6 +-
Acked-by: Rob Herring <robh@kernel.org>
> sound/soc/sunxi/sun4i-codec.c | 396 +++++++++++++++++----
> 2 files changed, 334 insertions(+), 68 deletions(-)
^ permalink raw reply
* [PATCH 10/12] ASoC: sun4i-codec: Add support for A31 board level audio routing
From: Rob Herring @ 2016-10-09 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161003110804.28235-11-wens@csie.org>
On Mon, Oct 03, 2016 at 07:08:02PM +0800, Chen-Yu Tsai wrote:
> The A31 SoC's codec has various inputs, outputs and microphone bias
> supplies. These can be routed on the board in different ways, such as:
>
> - Microphones all use the MBIAS main microphone supply or one mic may
> use the HBIAS supply, which supports headset detection and buttons.
>
> - Line Out may be routed to an audio jack, or an onboard speaker amp
> with power controls.
>
> Add support for specifying the audio routes in the device tree.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> .../devicetree/bindings/sound/sun4i-codec.txt | 35 ++++++++++++++++++++++
Acked-by: Rob Herring <robh@kernel.org>
> sound/soc/sunxi/sun4i-codec.c | 21 +++++++++++--
> 2 files changed, 54 insertions(+), 2 deletions(-)
^ permalink raw reply
* [PATCH v3] drm: tilcdc: add a da850-specific compatible string
From: Rob Herring @ 2016-10-09 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475509519-29516-1-git-send-email-bgolaszewski@baylibre.com>
On Mon, Oct 03, 2016 at 05:45:19PM +0200, Bartosz Golaszewski wrote:
> Due to some potential tweaks for the da850 LCDC (for example: the
> required memory bandwith settings) we need a separate compatible
> for the IP present on the da850 boards.
>
> Suggested-by: Sekhar Nori <nsekhar@ti.com>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> v1 -> v2:
> - added the new compatible to the bindings documentation
>
> v2 -> v3:
> - made the documentation more detailed
>
> Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt | 6 ++++--
> drivers/gpu/drm/tilcdc/tilcdc_drv.c | 1 +
> 2 files changed, 5 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH 3/3] dt-bindings: oxnas: Update Pinctrl and GPIO for OX820 Support
From: Rob Herring @ 2016-10-09 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004134148.23028-4-narmstrong@baylibre.com>
On Tue, Oct 04, 2016 at 03:41:48PM +0200, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Documentation/devicetree/bindings/gpio/gpio_oxnas.txt | 2 +-
> Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
> index 928ed4f..9665147 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
> @@ -3,7 +3,7 @@
> Please refer to gpio.txt for generic information regarding GPIO bindings.
>
> Required properties:
> - - compatible: "oxsemi,ox810se-gpio"
> + - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
It is preferred to have one per line, but it's fine unless you respin
the series.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [RFC 02/10] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller
From: Rob Herring @ 2016-10-09 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475593708-10526-3-git-send-email-jbrunet@baylibre.com>
On Tue, Oct 04, 2016 at 05:08:20PM +0200, Jerome Brunet wrote:
> This commit adds the device tree bindings description for Amlogic's GPIO
> interrupt controller available on the meson8, meson8b and gxbb SoC families
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> .../amlogic,meson-gpio-intc.txt | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
> new file mode 100644
> index 000000000000..bd4cceefcda1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
> @@ -0,0 +1,39 @@
> +Amlogic meson GPIO interrupt controller
> +
> +Meson SoCs contains an interrupt controller which is able watch the SoC pads
> +and generate an interrupt on edges or level. The controller is essentially a
> +256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
> +or level and polarity. We don?t expose all 256 mux inputs because the
> +documentation shows that upper part is not mapped to any pad. The actual number
> +of interrupt exposed depends on the SoC.
> +
> +Required properties:
> +
> +- compatible : should be: "amlogic,meson8-gpio-intc? or
> + ?amlogic,meson8b-gpio-intc? or ?amlogic,gxbb-gpio-intc?
One per line please if you respin the series.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [RFC 05/10] dt-bindings: pinctrl: meson: update gpio dt-bindings
From: Rob Herring @ 2016-10-09 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475593708-10526-6-git-send-email-jbrunet@baylibre.com>
On Tue, Oct 04, 2016 at 05:08:23PM +0200, Jerome Brunet wrote:
> Add description for the interrupt-parent property of the gpio sub-node
> If provided here, this property must be a phandle to an interrupt
> controller suitable for meson pinctrl, like the meson gpio interrupt
> controller.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 4 ++++
> 1 file changed, 4 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v2 1/2] ls1043ardb: add qe node to ls1043ardb
From: Zhao Qiang @ 2016-10-09 2:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
Changes for v2:
- use "fsl,ucc-hdlc" directly
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 66 +++++++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 4084631..a6a39fc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -124,6 +124,22 @@
};
};
+&uqe {
+ ucc_hdlc: ucc at 2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffffffe>;
+ fsl,rx-timeslot-mask = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+};
+
&duart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e669fbd..f6b6775 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -388,6 +388,72 @@
#interrupt-cells = <2>;
};
+ uqe: uqe at 2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x2400000 0x40000>;
+ reg = <0x0 0x2400000 0x0 0x480>;
+ brg-frequency = <100000000>;
+ bus-frequency = <200000000>;
+
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic at 80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0 77 0x04 0 77 0x04>;
+ };
+
+ si1: si at 700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,ls1043-qe-si",
+ "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram at 1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1043-qe-siram",
+ "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc at 2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc at 2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram at 10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only at 0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial at 2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH v2 2/2] ls1043ardb: add ds26522 node to dts
From: Zhao Qiang @ 2016-10-09 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475979159-20597-1-git-send-email-qiang.zhao@nxp.com>
add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
Changes for v2:
- na
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index a6a39fc..7f93bcc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -122,6 +122,22 @@
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
+
+ slic at 2 {
+ compatible = "maxim,ds26522";
+ reg = <2>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
+
+ slic at 3 {
+ compatible = "maxim,ds26522";
+ reg = <3>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
};
&uqe {
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
From: Po Liu @ 2016-10-09 2:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161008204959.GA17455@rob-hp-laptop>
Hi Rob,
Best regards,
Liu Po
> -----Original Message-----
> From: Rob Herring [mailto:robh at kernel.org]
> Sent: Sunday, October 09, 2016 4:50 AM
> To: Po Liu
> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> linux-kernel at vger.kernel.org; devicetree at vger.kernel.org; Bjorn Helgaas;
> Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Leo Li;
> Arnd Bergmann; M.H. Lian; Murali Karicheri
> Subject: Re: [PATCH v6 3/3] pci:add support aer/pme interrupts with none
> MSI/MSI-X/INTx mode
>
> On Fri, Sep 30, 2016 at 05:11:37PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer/pme interrupts with none MSI/MSI-X/INTx
> > mode, maybe there is interrupt line for aer pme etc. Search the
> > interrupt number in the fdt file. Then fixup the dev->irq with it.
>
> Again, explain why you are breaking compatibility. Will an old dtb using
> "intr" still work with this change? It should normally. There are some
> exceptions, but you need to say what they are.
>
Ok, understand.
> >
> > Signed-off-by: Po Liu <po.liu@nxp.com>
> > ---
> > changes for v6:
> > - modify bindings for "aer""pme";
> > - changing to the hood method to implement the aer pme interrupt;
> > - add pme interrupt in the same way;
> >
> > .../devicetree/bindings/pci/layerscape-pci.txt | 13 +++++--
> > arch/arm/kernel/bios32.c | 43
> ++++++++++++++++++++++
> > arch/arm64/kernel/pci.c | 43
> ++++++++++++++++++++++
> > drivers/pci/pcie/portdrv_core.c | 31
> +++++++++++++++-
> > include/linux/pci.h | 1 +
> > 5 files changed, 126 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 41e9f55..51ed49e 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -18,8 +18,12 @@ Required properties:
> > - reg: base addresses and lengths of the PCIe controller
> > - interrupts: A list of interrupt outputs of the controller. Must
> contain an
> > entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > - "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It could include the following entries:
>
> "Could" is not strong enough. Every valid combination of interrupts
> should correspond to a specific compatible string. A given version of
> h/w either has these interrupts or not.
Ok, will change to 'must'.
>
> > + "aer": Asserted for aer interrupt when chip support the aer
> interrupt with
> > + none MSI/MSI-X/INTx mode,but there is interrupt line for
> aer.
> > + "pme": Asserted for pme interrupt when chip support the pme
> interrupt with
> > + none MSI/MSI-X/INTx mode,but there is interrupt line for
> pme.
> > + ......
> > - fsl,pcie-scfg: Must include two entries.
> > The first entry must be a link to the SCFG device node
> > The second entry must be '0' or '1' based on physical PCIe
> controller index.
^ permalink raw reply
* [PATCH] mm/vmalloc: reduce the number of lazy_max_pages to reduce latency
From: Joel Fernandes @ 2016-10-09 3:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160929081818.GE28107@nuc-i3427.alporthouse.com>
On Thu, Sep 29, 2016 at 1:18 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Thu, Sep 29, 2016 at 03:34:11PM +0800, Jisheng Zhang wrote:
>> On Marvell berlin arm64 platforms, I see the preemptoff tracer report
>> a max 26543 us latency at __purge_vmap_area_lazy, this latency is an
>> awfully bad for STB. And the ftrace log also shows __free_vmap_area
>> contributes most latency now. I noticed that Joel mentioned the same
>> issue[1] on x86 platform and gave two solutions, but it seems no patch
>> is sent out for this purpose.
>>
>> This patch adopts Joel's first solution, but I use 16MB per core
>> rather than 8MB per core for the number of lazy_max_pages. After this
>> patch, the preemptoff tracer reports a max 6455us latency, reduced to
>> 1/4 of original result.
>
> My understanding is that
>
> diff --git a/mm/vmalloc.c b/mm/vmalloc.c
> index 91f44e78c516..3f7c6d6969ac 100644
> --- a/mm/vmalloc.c
> +++ b/mm/vmalloc.c
> @@ -626,7 +626,6 @@ void set_iounmap_nonlazy(void)
> static void __purge_vmap_area_lazy(unsigned long *start, unsigned long *end,
> int sync, int force_flush)
> {
> - static DEFINE_SPINLOCK(purge_lock);
> struct llist_node *valist;
> struct vmap_area *va;
> struct vmap_area *n_va;
> @@ -637,12 +636,6 @@ static void __purge_vmap_area_lazy(unsigned long *start, unsigned long *end,
> * should not expect such behaviour. This just simplifies locking for
> * the case that isn't actually used at the moment anyway.
> */
> - if (!sync && !force_flush) {
> - if (!spin_trylock(&purge_lock))
> - return;
> - } else
> - spin_lock(&purge_lock);
> -
> if (sync)
> purge_fragmented_blocks_allcpus();
>
> @@ -667,7 +660,6 @@ static void __purge_vmap_area_lazy(unsigned long *start, unsigned long *end,
> __free_vmap_area(va);
> spin_unlock(&vmap_area_lock);
> }
> - spin_unlock(&purge_lock);
> }
>
[..]
> should now be safe. That should significantly reduce the preempt-disabled
> section, I think.
I believe that the purge_lock is supposed to prevent concurrent purges
from happening.
For the case where if you have another concurrent overflow happen in
alloc_vmap_area() between the spin_unlock and purge :
spin_unlock(&vmap_area_lock);
if (!purged)
purge_vmap_area_lazy();
Then the 2 purges would happen at the same time and could subtract
vmap_lazy_nr twice.
I had proposed to change it to mutex in [1]. How do you feel about
that? Let me know your suggestions, thanks. I am also Ok with reducing
the lazy_max_pages value.
[1] http://lkml.iu.edu/hypermail/linux/kernel/1603.2/04803.html
Regards,
Joel
^ permalink raw reply
* [PATCH] MAINTAINERS: Add ARM64-specific ACPI maintainers entry
From: Hanjun Guo @ 2016-10-09 3:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161005112540.22189-1-lorenzo.pieralisi@arm.com>
On 10/05/2016 07:25 PM, Lorenzo Pieralisi wrote:
> The ARM64 architecture defines ARM64 specific ACPI bindings to
> configure and set-up arch specific components. To simplify
> code reviews/updates and streamline the maintainership structure
> supporting the arch specific code, a new arm64 directory was created in
> /drivers/acpi, to contain ACPI code that is specific to ARM64
> architecture.
>
> Add the ARM64-specific ACPI maintainers entry in MAINTAINERS for
> the newly created subdirectory and respective code content.
>
> Lorenzo Pieralisi will be in charge of submitting and managing
> the pull requests on behalf of all maintainers listed.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Hanjun Guo <hanjun.guo@linaro.org>
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> Link: http://lkml.kernel.org/r/1603704.EGiVTcCxLR at vostro.rjw.lan
Acked-by: Hanjun Guo <hanjun.guo@linaro.org>
Thanks
Hanjun
^ permalink raw reply
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