* [PATCH 1/2] iommu/arm-smmu: Don't inadvertently reject multiple SMMUv3s
From: Lorenzo Pieralisi @ 2016-10-17 13:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5cf1acbf9c42cc99e5cc0dacb50b7a92c3bd0feb.1476702234.git.robin.murphy@arm.com>
On Mon, Oct 17, 2016 at 12:06:20PM +0100, Robin Murphy wrote:
> We now delay installing our per-bus iommu_ops until we know an SMMU has
> successfully probed, as they don't serve much purpose beforehand, and
> doing so also avoids fights between multiple IOMMU drivers in a single
> kernel. However, the upshot of passing the return value of bus_set_iommu()
> back from our probe function is that if there happens to be more than
> one SMMUv3 device in a system, the second and subsequent probes will
> wind up returning -EBUSY to the driver core and getting torn down again.
>
> There are essentially 3 cases in which bus_set_iommu() returns nonzero:
> 1. The bus already has iommu_ops installed
> 2. One of the add_device callbacks from the initial notifier failed
> 3. Allocating or installing the notifier itself failed
>
> The first two are down to devices other than the SMMU in question, so
> shouldn't abort an otherwise-successful SMMU probe, whilst the third is
> indicative of the kind of catastrophic system failure which isn't going
> to get much further anyway. Consequently, there is little harm in
> ignoring the return value either way.
>
> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> drivers/iommu/arm-smmu-v3.c | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 15c01c3cd540..74fbef384deb 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -2637,16 +2637,13 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
> of_iommu_set_ops(dev->of_node, &arm_smmu_ops);
> #ifdef CONFIG_PCI
> pci_request_acs();
> - ret = bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
> - if (ret)
> - return ret;
> + bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
> #endif
> #ifdef CONFIG_ARM_AMBA
> - ret = bus_set_iommu(&amba_bustype, &arm_smmu_ops);
> - if (ret)
> - return ret;
> + bus_set_iommu(&amba_bustype, &arm_smmu_ops);
> #endif
> - return bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
> + bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
> + return 0;
Nit: I do not see why you would not take the same approach as
the ARM SMMUv1/v2, namely checking if ops are already set and
skip the call if that's the case.
Anyway:
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> }
>
> static int arm_smmu_device_remove(struct platform_device *pdev)
> --
> 1.9.1
>
^ permalink raw reply
* ARM64-cpuinfo: Combine six calls for sequence output into one seq_printf() call in c_show()
From: Mark Rutland @ 2016-10-17 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d012ad47-9688-5c9c-6ffd-78300c7b21ae@users.sourceforge.net>
On Mon, Oct 17, 2016 at 02:50:57PM +0200, SF Markus Elfring wrote:
> > I prefer the code as-is. Unless there's a compelling reason to change it.
>
> Is the chance for faster log output interesting enough?
Is there a particular user that cares today, or are we trying to work
backwards to a rationale?
Thanks,
Mark.
^ permalink raw reply
* [PATCH v4 0/1] Armada 7k/8k CP110 system controller fixes
From: Marcin Wojtas @ 2016-10-17 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPv3WKf13FJxGkpt+OcNO--hRQoZr-TtuzCcAJrQwFXjqRgM2Q@mail.gmail.com>
Hi Stephen,
Since merge window is closed, I kindly remind about remaining patch.
Best regards,
Marcin
2016-10-06 21:24 GMT+02:00 Marcin Wojtas <mw@semihalf.com>:
> Hi Stephen,
>
> Do you have any further comments on the remaining patch?
>
> Best regards,
> Marcin
>
> 2016-09-25 9:47 GMT+02:00 Marcin Wojtas <mw@semihalf.com>:
>> Hi,
>>
>> Two patches from the third version of the patchset have already been
>> applied, so I re-send the last one with corrected allocation of
>> clock data, which was pointed in the review.
>>
>> Any feedback would be very welcome.
>>
>> Best regards,
>> Marcin
>>
>> Changelog:
>> v4 <- v3
>> * fix allocation of clock data
>>
>> v3 <- v2
>> * return -ENOMEM on alloc failures
>>
>> v1 <- v2
>> * replace setting CLK_IS_BASIC flag with clearing init structure fields
>> with memset
>> * minor improvements of allocation and error checking
>> * add migration to clk_hw
>>
>>
>> Marcin Wojtas (1):
>> clk: mvebu: migrate CP110 system controller to clk_hw API and
>> registration
>>
>> drivers/clk/mvebu/cp110-system-controller.c | 150 +++++++++++++---------------
>> 1 file changed, 72 insertions(+), 78 deletions(-)
>>
>> --
>> 1.8.3.1
>>
^ permalink raw reply
* [PATCH] usb: ehci-platform: increase EHCI_MAX_RSTS to 4
From: Masahiro Yamada @ 2016-10-17 12:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017123043.GA15142@kroah.com>
Hi Greg,
2016-10-17 21:30 GMT+09:00 Greg Kroah-Hartman <gregkh@linuxfoundation.org>:
> On Mon, Oct 17, 2016 at 08:11:59PM +0900, Masahiro Yamada wrote:
>> Socionext LD11 SoC (arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi)
>> needs to handle 4 reset lines for EHCI.
>
> Why? What makes it different from other EHCI implementations?
>
> thanks,
>
> greg k-h
This is a generic EHCI driver, but the number of clocks/resets
are SoC-specific.
The following patch you picked up will remind you something?
commit 73577d61799e8d8bb7d69a9acdc54923e5998138
Author: Icenowy Zheng <icenowy@aosc.xyz>
Date: Fri Aug 12 11:06:22 2016 +0800
ehci-platform: add the max clock number to 4
Allwinner A64 EHCI requires 4 clocks to be enabled.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* Regression: usb serial gadget on sama5d3 broken
From: Peter Rosin @ 2016-10-17 12:53 UTC (permalink / raw)
To: linux-arm-kernel
Hi!
I'm suffering from a regression while using the usb gadget port on the
sama5d3 to get terminal access to the device in question (CONFIG_USB_G_SERIAL).
I get this message when I try to connect:
udc: ep: Invalid setup request: 02.01 v0000 i0081 l0, halting endpoint...
A bisect blames commit v4.7-rc1-21-gc32b5bcfa3c4 "ARM: dts: at91: Fix
USB endpoint nodes".
And indeed, reverting that commit on top of v4.9-rc1 fixes things,
although that doesn't look like the best of fixes...
BTW, the bisect was extremely painful since v4.7-rc1 seemed broken
somewhere in the overlayfs area. I hope I will never ever need to bisect
in the v4.6..v4.7 area again. This was the second time, the first time
I was chasing a gpio interrupt bug, but I never found out what was wrong
and stopped looking when v4.9-rc1 turned out to be ok even though v4.8
was bad, it was just too painful to look for things that already seemed
fixed.
Cheers,
Peter
^ permalink raw reply
* [GIT PULL] ARM: mvebu: fixes for v4.8 (#3)
From: Gregory CLEMENT @ 2016-10-17 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4853532.G9HOlQ47QA@wuerfel>
Hi Arnd,
On mer., sept. 21 2016, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tuesday, September 20, 2016 6:14:47 PM CEST Gregory CLEMENT wrote:
>> mvebu fixes for 4.8 (part 3)
>>
>> - Select corediv clk for all mvebu v7 SoC
>> - Fix clocksource for CP110 master SPI0 for Armada 7K/8K
>>
>
> Pulled into fixes, thanks!
I don't see this patch in the v4.8 or the v4.9-rc1.
I think it slipped through the cracks as there were the only one in the
fixes branches.
Do you think you could make them part of your next pull request for
fixes for 4.9-rc2?
Thanks,
Gregory
>
> Arnd
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* ARM64-cpuinfo: Combine six calls for sequence output into one seq_printf() call in c_show()
From: SF Markus Elfring @ 2016-10-17 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017123726.GE29095@leverpostej>
> I prefer the code as-is. Unless there's a compelling reason to change it.
Is the chance for faster log output interesting enough?
Regards,
Markus
^ permalink raw reply
* [PATCHv2 4/4] arm64: dump: Add checking for writable and exectuable pages
From: Mark Rutland @ 2016-10-17 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476311522-15381-5-git-send-email-labbott@redhat.com>
On Wed, Oct 12, 2016 at 03:32:02PM -0700, Laura Abbott wrote:
> +config DEBUG_WX
> + bool "Warn on W+X mappings at boot"
> + select ARM64_PTDUMP_CORE
> + ---help---
> + Generate a warning if any W+X mappings are found at boot.
> +
> + This is useful for discovering cases where the kernel is leaving
> + W+X mappings after applying NX, as such mappings are a security risk.
> + This check also includes UXN, which should be set on all kernel
> + mappings.
> +
> + Look for a message in dmesg output like this:
> +
> + arm64/mm: Checked W+X mappings: passed, no W+X pages found.
> +
> + or like this, if the check failed:
> +
> + arm64/mm: Checked W+X mappings: FAILED, <N> W+X pages found.
> +
> + Note that even if the check fails, your kernel is possibly
> + still fine, as W+X mappings are not a security hole in
> + themselves, what they do is that they make the exploitation
> + of other unfixed kernel bugs easier.
> +
> + There is no runtime or memory usage effect of this option
> + once the kernel has booted up - it's a one time check.
> +
> + If in doubt, say "Y".
> +
> +
Trivial nit: for consistency with the rest of the file, there should
only be one line space between options.
> config DEBUG_SET_MODULE_RONX
> bool "Set loadable kernel module data as NX and text as RO"
> depends on MODULES
> diff --git a/arch/arm64/include/asm/ptdump.h b/arch/arm64/include/asm/ptdump.h
> index 8fc0957..6afd847 100644
> --- a/arch/arm64/include/asm/ptdump.h
> +++ b/arch/arm64/include/asm/ptdump.h
> @@ -42,5 +42,13 @@ static inline int ptdump_debugfs_register(struct ptdump_info *info,
> return 0;
> }
> #endif
> +void ptdump_check_wx(void);
> +#endif /* CONFIG_ARM64_PTDUMP_CORE */
... ah, here's the missing #endif from patch 1.
Assuming that gets sorted out, this looks good to me, and works on juno,
so FWIW:
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
[...]
> +static void note_prot_uxn(struct pg_state *st, unsigned long addr)
> +{
> + if (!st->check_wx)
> + return;
> +
> + if ((st->current_prot & PTE_UXN) == PTE_UXN)
> + return;
> +
> + WARN_ONCE(1, "arm64/mm: Found non-UXN mapping at address %p/%pS\n",
> + (void *)st->start_address, (void *)st->start_address);
> +
> + st->wx_pages += (addr - st->start_address) / PAGE_SIZE;
> +}
As a future thought (I've scope-creeped this enough with the UXN check),
there are some other checks that we could add, like verifying the AP
bits don't allow user data access. That might be worth considering, with
DEBUG_WX becoming a more general kernel page table sanity check.
Thanks,
Mark.
^ permalink raw reply
* [PATCH 2/2] ARM: dts: da850: add a node for the LCD controller
From: Laurent Pinchart @ 2016-10-17 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <daf49046-ad0a-d9e2-d744-1e06085c6585@ti.com>
Hi Tomi,
On Monday 17 Oct 2016 15:29:23 Tomi Valkeinen wrote:
> On 17/10/16 14:40, Laurent Pinchart wrote:
> > On Monday 17 Oct 2016 10:33:58 Tomi Valkeinen wrote:
> >> On 17/10/16 10:12, Sekhar Nori wrote:
> >>> On Monday 17 October 2016 11:26 AM, Tomi Valkeinen wrote:
> >>>> On 15/10/16 20:42, Sekhar Nori wrote:
> >>>>>> diff --git a/arch/arm/boot/dts/da850.dtsi
> >>>>>> b/arch/arm/boot/dts/da850.dtsi
> >>>>>> index f79e1b9..32908ae 100644
> >>>>>> --- a/arch/arm/boot/dts/da850.dtsi
> >>>>>> +++ b/arch/arm/boot/dts/da850.dtsi
> >>>>>> @@ -399,6 +420,14 @@
> >>>>>> <&edma0 0 1>;
> >>>>>> dma-names = "tx", "rx";
> >>>>>> };
> >>>>>> +
> >>>>>> + display: display at 213000 {
> >>>>>> + compatible = "ti,am33xx-tilcdc", "ti,da850-
tilcdc";
> >>>>>
> >>>>> This should instead be:
> >>>>>
> >>>>> compatible = "ti,da850-tilcdc", "ti,am33xx-tilcdc";
> >>>>>
> >>>>> as the closest match should appear first in the list.
> >>>>
> >>>> Actually I don't think that's correct. The LCDC on da850 is not
> >>>> compatible with the LCDC on AM335x. I think it should be just
> >>>> "ti,da850-tilcdc".
> >>>
> >>> So if "ti,am33xx-tilcdc" is used, the display wont work at all? If thats
> >>> the case, I wonder how the patch passed testing. Bartosz?
> >>
> >> AM3 has "version 2" of LCDC, whereas DA850 is v1. They are quite
> >> similar, but different.
> >>
> >> The driver gets the version number from LCDC's register, and acts based
> >> on that, so afaik the compatible string doesn't really affect the
> >> functionality (as long as it matches).
> >>
> >> But even if it works with the current driver, I don't think
> >> "ti,am33xx-tilcdc" and "ti,da850-tilcdc" are compatible in the HW level.
> >
> > If the hardware provides IP revision information, how about just "ti,lcdc"
> > ?
>
> Maybe, and I agree that's the "correct" way, but looking at the history,
> it's not just once or twice when we've suddenly found out some
> difference or bug or such in an IP revision, or the integration to a
> SoC, that can't be found based on the IP revision.
>
> That's why I feel it's usually safer to have the SoC revision there in
> the compatible string.
>
> That said, we have only a few different old SoCs with LCDC (compared to,
> say, OMAP DSS) so in this case perhaps just "ti,lcdc" would be fine.
You obviously know more than I do on this topic so I'll trust your opinion. If
the version register isn't enough I'm fine with multiple compatible strings.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [RFC PATCH 3/3] MAINTAINERS: oxnas: Add new files definitions
From: Neil Armstrong @ 2016-10-17 12:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017124001.23820-1-narmstrong@baylibre.com>
Fix the dts files maintained by the OXNAS platform, add a new board.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 71aa5da..9f4bc60 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1444,8 +1444,9 @@ M: Neil Armstrong <narmstrong@baylibre.com>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-oxnas/
-F: arch/arm/boot/dts/oxnas*
+F: arch/arm/boot/dts/ox8*.dtsi
F: arch/arm/boot/dts/wd-mbwe.dts
+F: arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
N: oxnas
ARM/Mediatek RTC DRIVER
--
2.7.0
^ permalink raw reply related
* [RFC PATCH 2/3] ARM: dts: OX810: Update with dt-bindings includes
From: Neil Armstrong @ 2016-10-17 12:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017124001.23820-1-narmstrong@baylibre.com>
Add OX810SE dt-bindings includes files for clocks and resets, replace
resets numbers by human readable defines.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm/boot/dts/ox810se.dtsi | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi
index ce13705..46aa6db 100644
--- a/arch/arm/boot/dts/ox810se.dtsi
+++ b/arch/arm/boot/dts/ox810se.dtsi
@@ -7,6 +7,8 @@
*/
/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/oxsemi,ox810se.h>
+#include <dt-bindings/reset/oxsemi,ox810se.h>
/ {
compatible = "oxsemi,ox810se";
@@ -242,7 +244,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 17>;
+ resets = <&reset RESET_UART1>;
};
uart1: serial at 300000 {
@@ -256,7 +258,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 18>;
+ resets = <&reset RESET_UART2>;
};
uart2: serial at 900000 {
@@ -270,7 +272,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 22>;
+ resets = <&reset RESET_UART3>;
};
uart3: serial at a00000 {
@@ -284,7 +286,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 23>;
+ resets = <&reset RESET_UART4>;
};
};
--
2.7.0
^ permalink raw reply related
* [RFC PATCH 1/3] ARM: dts: Add support for OX820 and Pogoplug V3
From: Neil Armstrong @ 2016-10-17 12:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017124001.23820-1-narmstrong@baylibre.com>
Add device tree for the Oxford Seminconductor OX820 SoC and the
Cloud Engines PogoPlug v3 board.
Add the SoC and board compatible strings to oxnas bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/oxnas.txt | 5 +
arch/arm/boot/dts/Makefile | 3 +-
.../boot/dts/cloudengines-pogoplug-series-3.dts | 60 +++++
arch/arm/boot/dts/ox820.dtsi | 259 +++++++++++++++++++++
4 files changed, 326 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
create mode 100644 arch/arm/boot/dts/ox820.dtsi
diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt
index b9e4971..ac64e60 100644
--- a/Documentation/devicetree/bindings/arm/oxnas.txt
+++ b/Documentation/devicetree/bindings/arm/oxnas.txt
@@ -5,5 +5,10 @@ Boards with the OX810SE SoC shall have the following properties:
Required root node property:
compatible: "oxsemi,ox810se"
+Boards with the OX820 SoC shall have the following properties:
+ Required root node property:
+ compatible: "oxsemi,ox820"
+
Board compatible values:
- "wd,mbwe" (OX810SE)
+ - "cloudengines,pogoplugv3" (OX820)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faacd52..5d9e8d5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -588,7 +588,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
- wd-mbwe.dtb
+ wd-mbwe.dtb \
+ cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-arrow-sd-600eval.dtb \
diff --git a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
new file mode 100644
index 0000000..78d9149
--- /dev/null
+++ b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
@@ -0,0 +1,60 @@
+/*
+ * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+ model = "Cloud Engines PogoPlug Series 3";
+
+ compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+ };
+
+ memory {
+ /* 128Mbytes DDR */
+ reg = <0x60000000 0x8000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "pogoplug:blue";
+ gpios = <&gpio0 2 0>;
+ default-state = "keep";
+ };
+
+ orange {
+ label = "pogoplug:orange";
+ gpios = <&gpio1 16 1>;
+ default-state = "keep";
+ };
+
+ green {
+ label = "pogoplug:green";
+ gpios = <&gpio1 17 1>;
+ default-state = "keep";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+};
diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi
new file mode 100644
index 0000000..fe251f180
--- /dev/null
+++ b/arch/arm/boot/dts/ox820.dtsi
@@ -0,0 +1,259 @@
+/*
+ * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/oxsemi,ox820.h>
+#include <dt-bindings/reset/oxsemi,ox820.h>
+
+/ {
+ compatible = "oxsemi,ox820";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "oxsemi,ox820-smp";
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,arm11mpcore";
+ clocks = <&armclk>;
+ reg = <0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,arm11mpcore";
+ clocks = <&armclk>;
+ reg = <1>;
+ };
+ };
+
+ memory {
+ /* Max 512MB @ 0x60000000 */
+ reg = <0x60000000 0x20000000>;
+ };
+
+ clocks {
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ gmacclk: gmacclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&osc>;
+ };
+
+ plla: plla {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <850000000>;
+ };
+
+ armclk: armclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&plla>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&gic>;
+
+ apb-bridge at 44000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x44000000 0x1000000>;
+
+ pinctrl: pinctrl {
+ compatible = "oxsemi,ox820-pinctrl";
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ pinctrl_uart0: uart0 {
+ uart0 {
+ pins = "gpio30", "gpio31";
+ function = "fct5";
+ };
+ };
+
+ pinctrl_uart0_modem: uart0_modem {
+ uart0_modem_a {
+ pins = "gpio24", "gpio24", "gpio26", "gpio27";
+ function = "fct4";
+ };
+ uart0_modem_b {
+ pins = "gpio28", "gpio29";
+ function = "fct5";
+ };
+ };
+
+ pinctrl_uart1: uart1 {
+ uart1 {
+ pins = "gpio7", "gpio8";
+ function = "fct4";
+ };
+ };
+
+ pinctrl_uart1_modem: uart1_modem {
+ uart1_modem {
+ pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
+ function = "fct4";
+ };
+ };
+
+ pinctrl_etha_mdio: etha_mdio {
+ etha_mdio {
+ pins = "gpio3", "gpio4";
+ function = "fct1";
+ };
+ };
+ };
+
+ gpio0: gpio at 000000 {
+ compatible = "oxsemi,ox820-gpio";
+ reg = <0x000000 0x100000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <32>;
+ oxsemi,gpio-bank = <0>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+
+ gpio1: gpio at 100000 {
+ compatible = "oxsemi,ox820-gpio";
+ reg = <0x100000 0x100000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <18>;
+ oxsemi,gpio-bank = <1>;
+ gpio-ranges = <&pinctrl 0 32 18>;
+ };
+
+ uart0: serial at 200000 {
+ compatible = "ns16550a";
+ reg = <0x200000 0x100000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ clocks = <&sysclk>;
+ resets = <&reset RESET_UART1>;
+ };
+
+ uart1: serial at 300000 {
+ compatible = "ns16550a";
+ reg = <0x200000 0x100000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ clocks = <&sysclk>;
+ resets = <&reset RESET_UART2>;
+ };
+
+ rps at 400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x400000 0x100000>;
+
+ intc: interrupt-controller at 0 {
+ compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
+ interrupt-controller;
+ reg = <0 0x200>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ valid-mask = <0xFFFFFFFF>;
+ clear-mask = <0>;
+ };
+
+ timer0: timer at 200 {
+ compatible = "oxsemi,ox820-rps-timer";
+ reg = <0x200 0x40>;
+ clocks = <&sysclk>;
+ interrupt-parent = <&intc>;
+ interrupts = <4>;
+ };
+ };
+
+ sys: sys-ctrl at e00000 {
+ compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
+ reg = <0xe00000 0x200000>;
+
+ reset: reset-controller {
+ compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
+ #reset-cells = <1>;
+ };
+
+ stdclk: stdclk {
+ compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ apb-bridge at 47000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x47000000 0x1000000>;
+
+ scu: scu at 0 {
+ compatible = "arm,arm11mp-scu";
+ reg = <0x0 0x100>;
+ };
+
+ local-timer at 600 {
+ compatible = "arm,arm11mp-twd-timer";
+ reg = <0x600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&armclk>;
+ };
+
+ gic: gic at 1000 {
+ compatible = "arm,arm11mp-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1000 0x1000>,
+ <0x100 0x500>;
+ };
+ };
+ };
+};
--
2.7.0
^ permalink raw reply related
* [RFC PATCH 0/3] ARM: dts: oxnas: Update support for OX820 and use dt-bindings
From: Neil Armstrong @ 2016-10-17 12:39 UTC (permalink / raw)
To: linux-arm-kernel
This patchset updates the ARM DTS for the Oxnas platform by :
- Add support for the Oxford Semicondutor OX820 and the PogoPlug V3
- Update the OX810SE to use the dt-bindings includes files introduced in [1] and [2]
- Fix the MAINTAINERS entry and add the PogoPlug V3 file maintainance
This patchset remains RFC until dependent patches [1] and [2] are merged.
[1] https://listengine.tuxfamily.org/lists.tuxfamily.org/linux-oxnas/2016/10/msg00008.html
[2] https://listengine.tuxfamily.org/lists.tuxfamily.org/linux-oxnas/2016/10/msg00007.html
Neil Armstrong (3):
ARM: dts: Add support for OX820 and Pogoplug V3
ARM: dts: OX810: Update with dt-bindings includes
MAINTAINERS: oxnas: Add new files definitions
Documentation/devicetree/bindings/arm/oxnas.txt | 5 +
MAINTAINERS | 3 +-
arch/arm/boot/dts/Makefile | 3 +-
.../boot/dts/cloudengines-pogoplug-series-3.dts | 60 +++++
arch/arm/boot/dts/ox810se.dtsi | 10 +-
arch/arm/boot/dts/ox820.dtsi | 259 +++++++++++++++++++++
6 files changed, 334 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
create mode 100644 arch/arm/boot/dts/ox820.dtsi
--
2.7.0
^ permalink raw reply
* ARM64-cpuinfo: Combine six calls for sequence output into one seq_printf() call in c_show()
From: Mark Rutland @ 2016-10-17 12:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a09542e6-9851-45ef-583d-338205217cfc@users.sourceforge.net>
On Mon, Oct 17, 2016 at 01:30:59PM +0200, SF Markus Elfring wrote:
> >> Some data were printed into a sequence by six separate function calls.
> >> Print the same data by a single function call instead.
> >
> > ... why?
> >
> > Beyond simply having fewer function calls, is there an upside?
>
> Will it matter to improve run time characteristics at this source code
> place?
I do not know. If that's not the aim of your existing patch, then I have
no idea what you're trying to achieve.
> > This makes it harder to see the relationship between the format strings
> > and their associated data, and makes the code longer.
>
> Do you prefer an other layout for the passed data so that the increase
> of line count in my update suggestion would look differently?
I prefer the code as-is. Unless there's a compelling reason to change
it.
Thanks,
Mark.
^ permalink raw reply
* [PATCH] usb: ehci-platform: increase EHCI_MAX_RSTS to 4
From: Greg Kroah-Hartman @ 2016-10-17 12:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476702719-10337-1-git-send-email-yamada.masahiro@socionext.com>
On Mon, Oct 17, 2016 at 08:11:59PM +0900, Masahiro Yamada wrote:
> Socionext LD11 SoC (arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi)
> needs to handle 4 reset lines for EHCI.
Why? What makes it different from other EHCI implementations?
thanks,
greg k-h
^ permalink raw reply
* [PATCH 2/2] ARM: dts: da850: add a node for the LCD controller
From: Tomi Valkeinen @ 2016-10-17 12:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4975084.EGQPv58AK6@avalon>
On 17/10/16 14:40, Laurent Pinchart wrote:
> Hello,
>
> On Monday 17 Oct 2016 10:33:58 Tomi Valkeinen wrote:
>> On 17/10/16 10:12, Sekhar Nori wrote:
>>> On Monday 17 October 2016 11:26 AM, Tomi Valkeinen wrote:
>>>> On 15/10/16 20:42, Sekhar Nori wrote:
>>>>>> diff --git a/arch/arm/boot/dts/da850.dtsi
>>>>>> b/arch/arm/boot/dts/da850.dtsi
>>>>>> index f79e1b9..32908ae 100644
>>>>>> --- a/arch/arm/boot/dts/da850.dtsi
>>>>>> +++ b/arch/arm/boot/dts/da850.dtsi
>>>>>> @@ -399,6 +420,14 @@
>>>>>> <&edma0 0 1>;
>>>>>> dma-names = "tx", "rx";
>>>>>> };
>>>>>> +
>>>>>> + display: display at 213000 {
>>>>>> + compatible = "ti,am33xx-tilcdc", "ti,da850-tilcdc";
>>>>>
>>>>> This should instead be:
>>>>>
>>>>> compatible = "ti,da850-tilcdc", "ti,am33xx-tilcdc";
>>>>>
>>>>> as the closest match should appear first in the list.
>>>>
>>>> Actually I don't think that's correct. The LCDC on da850 is not
>>>> compatible with the LCDC on AM335x. I think it should be just
>>>> "ti,da850-tilcdc".
>>>
>>> So if "ti,am33xx-tilcdc" is used, the display wont work at all? If thats
>>> the case, I wonder how the patch passed testing. Bartosz?
>>
>> AM3 has "version 2" of LCDC, whereas DA850 is v1. They are quite
>> similar, but different.
>>
>> The driver gets the version number from LCDC's register, and acts based
>> on that, so afaik the compatible string doesn't really affect the
>> functionality (as long as it matches).
>>
>> But even if it works with the current driver, I don't think
>> "ti,am33xx-tilcdc" and "ti,da850-tilcdc" are compatible in the HW level.
>
> If the hardware provides IP revision information, how about just "ti,lcdc" ?
Maybe, and I agree that's the "correct" way, but looking at the history,
it's not just once or twice when we've suddenly found out some
difference or bug or such in an IP revision, or the integration to a
SoC, that can't be found based on the IP revision.
That's why I feel it's usually safer to have the SoC revision there in
the compatible string.
That said, we have only a few different old SoCs with LCDC (compared to,
say, OMAP DSS) so in this case perhaps just "ti,lcdc" would be fine.
Tomi
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161017/6c32126e/attachment.sig>
^ permalink raw reply
* [PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding
From: Robin Murphy @ 2016-10-17 12:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <acf4f770eab43fec8c5b6e9cddb6dd0defc52138.1476706244.git.robin.murphy@arm.com>
With the "mmu-masters" property now deprecated and optional, the
generic binding offers a more efficient way to specify no masters.
CC: Ray Jui <rjui@broadcom.com>
CC: Scott Branden <sbranden@broadcom.com>
CC: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc408629a..65530e193e8a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -248,7 +248,7 @@
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- mmu-masters;
+ #iommu-cells = <1>;
};
pinctrl: pinctrl at 6501d130 {
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: Update AMD Seattle to generic IOMMU binding
From: Robin Murphy @ 2016-10-17 12:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <acf4f770eab43fec8c5b6e9cddb6dd0defc52138.1476706244.git.robin.murphy@arm.com>
MMU-401 supports stream matching, so with the SMMU implementation of
the generic "iommus" binding we can use masks to nicely simplify the
XGBE's blocks of contiguous stream IDs.
CC: Tom Lendacky <thomas.lendacky@amd.com>
CC: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
CC: Brijesh Singh <brijeshkumar.singh@amd.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
index 8e8631952497..4cd0a443d4f6 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
@@ -54,8 +54,8 @@
clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
- #stream-id-cells = <16>;
dma-coherent;
+ iommus = <&xgmac0_smmu 0x00 0x17>;
};
xgmac1: xgmac at e0900000 {
@@ -80,8 +80,8 @@
clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
- #stream-id-cells = <16>;
dma-coherent;
+ iommus = <&xgmac1_smmu 0x00 0x17>;
};
xgmac0_smmu: smmu at e0600000 {
@@ -93,11 +93,7 @@
*/
<0 336 4>,
<0 336 4>;
-
- mmu-masters = <&xgmac0
- 0 1 2 3 4 5 6 7
- 16 17 18 19 20 21 22 23
- >;
+ #iommu-cells = <2>;
};
xgmac1_smmu: smmu at e0800000 {
@@ -109,9 +105,5 @@
*/
<0 335 4>,
<0 335 4>;
-
- mmu-masters = <&xgmac1
- 0 1 2 3 4 5 6 7
- 16 17 18 19 20 21 22 23
- >;
+ #iommu-cells = <2>;
};
--
1.9.1
^ permalink raw reply related
* [PATCH 1/3] arm64/dts: Add SMMUs to Juno
From: Robin Murphy @ 2016-10-17 12:13 UTC (permalink / raw)
To: linux-arm-kernel
Juno has seperate MMU-401 instances in front of the DMA-330, both HDLCD
controllers, the USB host controller, the PCIe root complex, and the
CoreSight ETR. Since there is still work to do to make all the relevant
subsystems interact nicely with the presence of an IOMMU, add the nodes
to aid develompent and testing but leave them disabled by default to
avoid nasty surprises.
CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Sudeep Holla <sudeep.holla@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 80 ++++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 334271a25f70..100810a8b929 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -29,6 +29,28 @@
clock-names = "apb_pclk";
};
+ smmu_pcie: iommu at 2b500000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x2b500000 0x0 0x10000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ smmu_etr: iommu at 2b600000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x2b600000 0x0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
gic: interrupt-controller at 2c010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
reg = <0x0 0x2c010000 0 0x1000>,
@@ -146,6 +168,7 @@
etr at 20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20070000 0 0x1000>;
+ iommus = <&smmu_etr 0>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
@@ -404,6 +427,8 @@
<0 0 0 4 &gic 0 0 0 139 4>;
msi-parent = <&v2m_0>;
status = "disabled";
+ iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
+ iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
};
scpi {
@@ -484,6 +509,48 @@
/include/ "juno-clocks.dtsi"
+ smmu_dma: iommu at 7fb00000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ smmu_hdlcd1: iommu at 7fb10000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ status = "disabled";
+ };
+
+ smmu_hdlcd0: iommu at 7fb20000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ status = "disabled";
+ };
+
+ smmu_usb: iommu at 7fb30000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
dma at 7ff00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x7ff00000 0 0x1000>;
@@ -499,6 +566,15 @@
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_dma 0>,
+ <&smmu_dma 1>,
+ <&smmu_dma 2>,
+ <&smmu_dma 3>,
+ <&smmu_dma 4>,
+ <&smmu_dma 5>,
+ <&smmu_dma 6>,
+ <&smmu_dma 7>,
+ <&smmu_dma 8>;
clocks = <&soc_faxiclk>;
clock-names = "apb_pclk";
};
@@ -507,6 +583,7 @@
compatible = "arm,hdlcd";
reg = <0 0x7ff50000 0 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_hdlcd1 0>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
@@ -521,6 +598,7 @@
compatible = "arm,hdlcd";
reg = <0 0x7ff60000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_hdlcd0 0>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
@@ -574,6 +652,7 @@
compatible = "generic-ohci";
reg = <0x0 0x7ffb0000 0x0 0x10000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_usb 0>;
clocks = <&soc_usb48mhz>;
};
@@ -581,6 +660,7 @@
compatible = "generic-ehci";
reg = <0x0 0x7ffc0000 0x0 0x10000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_usb 0>;
clocks = <&soc_usb48mhz>;
};
--
1.9.1
^ permalink raw reply related
* [PATCH 3/3] dts: hisi: add dts files for Hi3516CV300 demo board
From: Pan Wen @ 2016-10-17 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017120705.3726-1-wenpan@hisilicon.com>
Add dts files for Hi3516CV300 demo board.
Signed-off-by: Pan Wen <wenpan@hisilicon.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/hi3516cv300-demb.dts | 148 ++++++++++++
arch/arm/boot/dts/hi3516cv300.dtsi | 397 +++++++++++++++++++++++++++++++++
3 files changed, 546 insertions(+)
create mode 100644 arch/arm/boot/dts/hi3516cv300-demb.dts
create mode 100644 arch/arm/boot/dts/hi3516cv300.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd26..1f25530 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ARCH_HIP01) += \
dtb-$(CONFIG_ARCH_HIP04) += \
hip04-d01.dtb
dtb-$(CONFIG_ARCH_HISI) += \
+ hi3516cv300-demb.dtb \
hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
diff --git a/arch/arm/boot/dts/hi3516cv300-demb.dts b/arch/arm/boot/dts/hi3516cv300-demb.dts
new file mode 100644
index 0000000..6a75cd6
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516cv300-demb.dts
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+
+/dts-v1/;
+#include "hi3516cv300.dtsi"
+
+/ {
+ model = "Hisilicon Hi3516CV300 DEMO Board";
+ compatible = "hisilicon,hi3516cv300";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ i2c0 = &i2c_bus0;
+ i2c1 = &i2c_bus1;
+ spi0 = &spi_bus0;
+ spi1 = &spi_bus1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&dual_timer0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&pwm {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c_bus0 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pmux>;
+};
+
+&i2c_bus1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pmux>;
+};
+
+&spi_bus0{
+ status = "disabled";
+ num-cs = <1>;
+ cs-gpios = <&gpio_chip0 6 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pmux>;
+};
+
+&spi_bus1{
+ status = "okay";
+ num-cs = <2>;
+ cs-gpios = <&gpio_chip5 3 0>, <&gpio_chip5 4 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pmux>;
+};
+
+&fmc {
+ spi-nor at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <160000000>;
+ m25p,fast-read;
+ };
+};
+
+&mdio {
+ phy0: phy at 1 {
+ reg = <1>;
+ };
+};
+
+&hisi_femac {
+ mac-address = [00 00 00 00 00 00];
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+ hisilicon,phy-reset-delays-us = <10000 10000 150000>;
+};
+
+&dmac {
+ status = "okay";
+};
+
+&pmux {
+ i2c0_pmux: i2c0_pmux {
+ pinctrl-single,pins = <
+ 0x2c 0x3
+ 0x30 0x3>;
+ };
+
+ i2c1_pmux: i2c1_pmux {
+ pinctrl-single,pins = <
+ 0x20 0x1
+ 0x24 0x1>;
+ };
+
+ spi0_pmux: spi0_pmux {
+ pinctrl-single,pins = <
+ 0x28 0x1
+ 0x2c 0x1
+ 0x30 0x1
+ 0x34 0x1>;
+ };
+
+ spi1_pmux: spi1_pmux {
+ pinctrl-single,pins = <
+ 0xc4 0x1
+ 0xc8 0x1
+ 0xcc 0x1
+ 0xd0 0x1
+ 0xd4 0x1>;
+ };
+};
diff --git a/arch/arm/boot/dts/hi3516cv300.dtsi b/arch/arm/boot/dts/hi3516cv300.dtsi
new file mode 100644
index 0000000..1da41ab
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516cv300.dtsi
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/hi3516cv300-clock.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ reg = <0>;
+ };
+ };
+
+ vic: interrupt-controller at 10040000 {
+ compatible = "arm,pl190-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x10040000 0x1000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&vic>;
+ ranges;
+
+ clk_3m: clk_3m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
+ };
+
+ clk_apb: clk_apb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ crg: clock-reset-controller at 12010000 {
+ compatible = "hisilicon,hi3516cv300-crg";
+ reg = <0x12010000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+ };
+
+ sysctrl: system-controller at 12020000 {
+ compatible = "hisilicon,hi3516cv300-sysctrl", "syscon";
+ reg = <0x12020000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&sysctrl>;
+ offset = <0x4>;
+ mask = <0xdeadbeef>;
+ };
+
+ dual_timer0: dual_timer at 12000000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x12000000 0x1000>;
+ interrupts = <3>;
+ clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
+ clock-names = "timer0", "timer1", "apb_pclk";
+ status = "disabled";
+ };
+
+ dual_timer1: dual_timer at 12001000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x12001000 0x1000>;
+ interrupts = <4>;
+ clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
+ clock-names = "timer0", "timer1", "apb_pclk";
+ status = "disabled";
+ };
+
+ watchdog: watchdog at 12080000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ arm,primecell-periphid = <0x00141805>;
+ reg = <0x12080000 0x1000>;
+ clocks = <&sysctrl HI3516CV300_WDT_CLK>,
+ <&crg HI3516CV300_APB_CLK>;
+ clock-names = "wdog_clk", "apb_pclk";
+ status = "disabled";
+ };
+
+ pwm: pwm at 12130000 {
+ compatible = "hisilicon,hi3516cv300-pwm",
+ "hisilicon,hibvt-pwm";
+ reg = <0x12130000 0x10000>;
+ clocks = <&crg HI3516CV300_PWM_CLK>;
+ resets = <&crg 0x38 0>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ uart0: uart at 12100000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12100000 0x1000>;
+ interrupts = <5>;
+ clocks = <&crg HI3516CV300_UART0_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart1: uart at 12101000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12101000 0x1000>;
+ interrupts = <30>;
+ clocks = <&crg HI3516CV300_UART1_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart2: uart at 12102000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12102000 0x1000>;
+ interrupts = <25>;
+ clocks = <&crg HI3516CV300_UART2_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ i2c_bus0: i2c at 12110000 {
+ compatible = "hisilicon,hi3516cv300-i2c",
+ "hisilicon,hibvt-i2c";
+ reg = <0x12110000 0x1000>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ status = "disabled";
+ };
+
+ i2c_bus1: i2c at 12112000 {
+ compatible = "hisilicon,hi3516cv300-i2c",
+ "hisilicon,hibvt-i2c";
+ reg = <0x12112000 0x1000>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ status = "disabled";
+ };
+
+ spi_bus0: spi at 12120000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12120000 0x1000>;
+ interrupts = <6>;
+ clocks = <&crg HI3516CV300_SPI0_CLK>;
+ clock-names = "apb_pclk";
+ dmas = <&dmac 12 1>, <&dmac 13 2>;
+ dma-names = "rx", "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi_bus1: spi at 12121000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12121000 0x1000>, <0x12030000 0x4>;
+ interrupts = <7>;
+ clocks = <&crg HI3516CV300_SPI1_CLK>;
+ clock-names = "apb_pclk";
+ dmas = <&dmac 14 1>, <&dmac 15 2>;
+ dma-names = "rx", "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ fmc: spi-nor-controller at 10000000 {
+ compatible = "hisilicon,fmc-spi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
+ reg-names = "control", "memory";
+ clocks = <&crg HI3516CV300_FMC_CLK>;
+ assigned-clocks = <&crg HI3516CV300_FMC_CLK>;
+ assigned-clock-rates = <24000000>;
+ };
+
+ mdio: mdio at 10051100 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x10051100 0x10>;
+ clocks = <&crg HI3516CV300_ETH_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ hisi_femac: ethernet at 10090000 {
+ compatible = "hisilicon,hi3516cv300-femac",
+ "hisilicon,hisi-femac-v2";
+ reg = <0x10050000 0x1000>,<0x10051300 0x200>;
+ interrupts = <12>;
+ clocks = <&crg HI3516CV300_ETH_CLK>;
+ resets = <&crg 0xec 0>, <&crg 0xec 3>;
+ reset-names = "mac","phy";
+ };
+
+ dmac: dma-controller at 10030000 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x10030000 0x1000>;
+ interrupts = <14>;
+ clocks = <&crg HI3516CV300_DMAC_CLK>;
+ clock-names = "apb_pclk";
+ lli-bus-interface-ahb1;
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb1;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio_chip0: gpio at 12140000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12140000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 61 2>,
+ <&pmux 4 11 1>,
+ <&pmux 5 10 1>,
+ <&pmux 6 13 2>;
+
+ status = "disabled";
+ };
+
+ gpio_chip1: gpio at 12141000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12141000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 16 7>,
+ <&pmux 7 0 1>;
+ status = "disabled";
+ };
+
+ gpio_chip2: gpio at 12142000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12142000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 46 1>,
+ <&pmux 1 45 1>,
+ <&pmux 2 44 1>,
+ <&pmux 3 43 1>,
+ <&pmux 4 39 1>,
+ <&pmux 5 38 1>,
+ <&pmux 6 40 1>,
+ <&pmux 7 48 1>;
+ status = "disabled";
+ };
+
+ gpio_chip3: gpio at 12143000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12143000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 37 1>,
+ <&pmux 1 36 1>,
+ <&pmux 2 35 1>,
+ <&pmux 3 34 1>,
+ <&pmux 4 23 2>,
+ <&pmux 6 8 2>;
+ status = "disabled";
+ };
+
+ gpio_chip4: gpio at 12144000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12144000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 27 1>,
+ <&pmux 1 26 1>,
+ <&pmux 2 31 1>,
+ <&pmux 3 30 1>,
+ <&pmux 4 28 2>,
+ <&pmux 6 33 1>,
+ <&pmux 7 32 1>;
+ status = "disabled";
+ };
+
+ gpio_chip5: gpio at 12145000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12145000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 53 1>,
+ <&pmux 1 51 2>,
+ <&pmux 3 50 1>,
+ <&pmux 4 49 1>,
+ <&pmux 5 47 1>,
+ <&pmux 6 40 2>;
+ status = "disabled";
+ };
+
+ gpio_chip6: gpio at 12146000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12146000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 7 1>,
+ <&pmux 1 6 1>,
+ <&pmux 2 4 1>,
+ <&pmux 3 5 1>,
+ <&pmux 4 15 1>,
+ <&pmux 5 1 3>;
+ status = "disabled";
+ };
+
+ gpio_chip7: gpio at 12147000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12147000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 1 55 6>,
+ <&pmux 7 25 1>;
+ status = "disabled";
+ };
+
+ gpio_chip8: gpio at 12148000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x12148000 0x1000>;
+ interrupts = <31>;
+ clocks = <&crg HI3516CV300_APB_CLK>;
+ clock-names = "apb_pclk";
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmux 0 63 3>,
+ <&pmux 3 12 1>;
+ status = "disabled";
+ };
+
+ pmux: pinmux at 12040000 {
+ compatible = "pinctrl-single";
+ reg = <0x12040000 0x108>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #gpio-range-cells = <3>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 54 0
+ &range 55 6 1 &range 61 5 0>;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ pconf: pinconf at 12040800 {
+ compatible = "pinconf-single";
+ reg = <0x12040800 0x130>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ };
+ };
+};
--
2.9.3
^ permalink raw reply related
* [PATCH 2/3] clk: hisilicon: add CRG driver for Hi3516CV300 SoC
From: Pan Wen @ 2016-10-17 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017120705.3726-1-wenpan@hisilicon.com>
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Pan Wen <wenpan@hisilicon.com>
---
.../devicetree/bindings/clock/hisi-crg.txt | 50 ++++
drivers/clk/hisilicon/Kconfig | 8 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/crg-hi3516cv300.c | 330 +++++++++++++++++++++
drivers/clk/hisilicon/crg.h | 34 +++
include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++
6 files changed, 471 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt
create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c
create mode 100644 drivers/clk/hisilicon/crg.h
create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h
diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt
new file mode 100644
index 0000000..cc60b3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt
@@ -0,0 +1,50 @@
+* HiSilicon Clock and Reset Generator(CRG)
+
+The CRG module provides clock and reset signals to various
+modules within the SoC.
+
+This binding uses the following bindings:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - "hisilicon,hi3516cv300-crg"
+ - "hisilicon,hi3516cv300-sysctrl"
+ - "hisilicon,hi3519-crg"
+ - "hisilicon,hi3798cv200-crg"
+ - "hisilicon,hi3798cv200-sysctrl"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller at 12010000 {
+ compatible = "hisilicon,hi3519-crg";
+ reg = <0x12010000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c at 12110000 {
+ compatible = "hisilicon,hi3519-i2c";
+ reg = <0x12110000 0x1000>;
+ clocks = <&CRG HI3519_I2C0_RST>;
+ resets = <&CRG 0xe4 0>;
+};
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 3f537a0..5ceb42f 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,11 @@
+config COMMON_CLK_HI3516CV300
+ tristate "HI3516CV300 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ select RESET_HISI
+ default ARCH_HISI
+ help
+ Build the clock driver for hi3516cv300.
+
config COMMON_CLK_HI3519
tristate "Hi3519 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index e169ec7..6c5c34d 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -7,6 +7,7 @@ obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o
diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c
new file mode 100644
index 0000000..2007123
--- /dev/null
+++ b/drivers/clk/hisilicon/crg-hi3516cv300.c
@@ -0,0 +1,330 @@
+/*
+ * Hi3516CV300 Clock and Reset Generator Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/hi3516cv300-clock.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "clk.h"
+#include "crg.h"
+#include "reset.h"
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_INNER_CLK_OFFSET 64
+#define HI3516CV300_FIXED_3M 65
+#define HI3516CV300_FIXED_6M 66
+#define HI3516CV300_FIXED_24M 67
+#define HI3516CV300_FIXED_49P5 68
+#define HI3516CV300_FIXED_50M 69
+#define HI3516CV300_FIXED_83P3M 70
+#define HI3516CV300_FIXED_99M 71
+#define HI3516CV300_FIXED_100M 72
+#define HI3516CV300_FIXED_148P5M 73
+#define HI3516CV300_FIXED_198M 74
+#define HI3516CV300_FIXED_297M 75
+#define HI3516CV300_UART_MUX 76
+#define HI3516CV300_FMC_MUX 77
+#define HI3516CV300_MMC0_MUX 78
+#define HI3516CV300_MMC1_MUX 79
+#define HI3516CV300_MMC2_MUX 80
+#define HI3516CV300_MMC3_MUX 81
+#define HI3516CV300_PWM_MUX 82
+#define HI3516CV300_CRG_NR_CLKS 128
+
+static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = {
+ { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
+ { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
+ { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
+ { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
+ { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
+ { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
+ { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
+ { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
+ { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
+ { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
+ { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
+ { HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, },
+};
+
+static const char *const uart_mux_p[] = {"24m", "6m"};
+static const char *const fmc_mux_p[] = {
+ "24m", "83.3m", "148.5m", "198m", "297m"
+};
+static const char *const mmc_mux_p[] = {"49.5m"};
+static const char *const mmc2_mux_p[] = {"99m", "49.5m"};
+static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"};
+
+static u32 uart_mux_table[] = {0, 1};
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4};
+static u32 mmc_mux_table[] = {0};
+static u32 mmc2_mux_table[] = {0, 2};
+static u32 pwm_mux_table[] = {0, 1, 2, 3};
+
+static const struct hisi_mux_clock hi3516cv300_mux_clks[] = {
+ { HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
+ CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
+ { HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
+ { HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
+ { HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
+ { HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p),
+ CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
+ { HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
+ { HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p),
+ CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
+
+ { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
+ 0xe4, 15, 0, },
+ { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
+ 0xe4, 16, 0, },
+ { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
+ 0xe4, 17, 0, },
+
+ { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
+ 0xe4, 13, 0, },
+ { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
+ 0xe4, 14, 0, },
+
+ { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
+ 0xc0, 1, 0, },
+ { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
+ 0xc4, 1, 0, },
+ { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
+ 0xc4, 9, 0, },
+ { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
+ 0xc4, 17, 0, },
+ { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
+ 0xc8, 1, 0, },
+
+ { HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, },
+
+ { HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, },
+ { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
+ 0x38, 1, 0, },
+
+ { HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, },
+ { HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0,
+ 0xb8, 1, 0, },
+ { HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0,
+ 0xb8, 2, 0, },
+ { HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0,
+ 0xb8, 3, 0, },
+ { HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0,
+ 0xb8, 4, 0, },
+ { HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, },
+ { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
+};
+
+static struct hisi_clock_data *hi3516cv300_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
+ ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
+ ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
+ ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3516cv300_gate_clks,
+ ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3516cv300_mux_clks,
+ ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
+ ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3516cv300_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3516cv300_gate_clks,
+ ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
+ hisi_clk_unregister_mux(hi3516cv300_mux_clks,
+ ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
+ hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
+ ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
+ .register_clks = hi3516cv300_clk_register,
+ .unregister_clks = hi3516cv300_clk_unregister,
+};
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_SYSCTRL_NR_CLKS 16
+
+static const char *wdt_mux_p[] __initconst = { "3m", "apb" };
+static u32 wdt_mux_table[] = {0, 1};
+
+static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
+ { HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p),
+ CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
+};
+
+static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
+ ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ return clk_data;
+
+unregister_mux:
+ hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
+ ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
+ ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
+ crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
+ .register_clks = hi3516cv300_sysctrl_clk_register,
+ .unregister_clks = hi3516cv300_sysctrl_clk_unregister,
+};
+
+static const struct of_device_id hi3516cv300_crg_match_table[] = {
+ {
+ .compatible = "hisilicon,hi3516cv300-crg",
+ .data = &hi3516cv300_crg_funcs
+ },
+ {
+ .compatible = "hisilicon,hi3516cv300-sysctrl",
+ .data = &hi3516cv300_sysctrl_funcs
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
+
+static int hi3516cv300_crg_probe(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg;
+
+ crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
+ if (!crg)
+ return -ENOMEM;
+
+ crg->funcs = of_device_get_match_data(&pdev->dev);
+ if (!crg->funcs)
+ return -ENOENT;
+
+ crg->rstc = hisi_reset_init(pdev);
+ if (!crg->rstc)
+ return -ENOMEM;
+
+ crg->clk_data = crg->funcs->register_clks(pdev);
+ if (IS_ERR(crg->clk_data)) {
+ hisi_reset_exit(crg->rstc);
+ return PTR_ERR(crg->clk_data);
+ }
+
+ platform_set_drvdata(pdev, crg);
+ return 0;
+}
+
+static int hi3516cv300_crg_remove(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ hisi_reset_exit(crg->rstc);
+ crg->funcs->unregister_clks(pdev);
+ return 0;
+}
+
+static struct platform_driver hi3516cv300_crg_driver = {
+ .probe = hi3516cv300_crg_probe,
+ .remove = hi3516cv300_crg_remove,
+ .driver = {
+ .name = "hi3516cv300-crg",
+ .of_match_table = hi3516cv300_crg_match_table,
+ },
+};
+
+static int __init hi3516cv300_crg_init(void)
+{
+ return platform_driver_register(&hi3516cv300_crg_driver);
+}
+core_initcall(hi3516cv300_crg_init);
+
+static void __exit hi3516cv300_crg_exit(void)
+{
+ platform_driver_unregister(&hi3516cv300_crg_driver);
+}
+module_exit(hi3516cv300_crg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");
diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
new file mode 100644
index 0000000..e073971
--- /dev/null
+++ b/drivers/clk/hisilicon/crg.h
@@ -0,0 +1,34 @@
+/*
+ * HiSilicon Clock and Reset Driver Header
+ *
+ * Copyright (c) 2016 HiSilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HISI_CRG_H
+#define __HISI_CRG_H
+
+struct hisi_clock_data;
+struct hisi_reset_controller;
+
+struct hisi_crg_funcs {
+ struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
+ void (*unregister_clks)(struct platform_device *pdev);
+};
+
+struct hisi_crg_dev {
+ struct hisi_clock_data *clk_data;
+ struct hisi_reset_controller *rstc;
+ const struct hisi_crg_funcs *funcs;
+};
+
+#endif /* __HISI_CRG_H */
diff --git a/include/dt-bindings/clock/hi3516cv300-clock.h b/include/dt-bindings/clock/hi3516cv300-clock.h
new file mode 100644
index 0000000..5ba51b8
--- /dev/null
+++ b/include/dt-bindings/clock/hi3516cv300-clock.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3516CV300_CLOCK_H
+#define __DTS_HI3516CV300_CLOCK_H
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_APB_CLK 0
+#define HI3516CV300_UART0_CLK 1
+#define HI3516CV300_UART1_CLK 2
+#define HI3516CV300_UART2_CLK 3
+#define HI3516CV300_SPI0_CLK 4
+#define HI3516CV300_SPI1_CLK 5
+#define HI3516CV300_FMC_CLK 6
+#define HI3516CV300_MMC0_CLK 7
+#define HI3516CV300_MMC1_CLK 8
+#define HI3516CV300_MMC2_CLK 9
+#define HI3516CV300_MMC3_CLK 10
+#define HI3516CV300_ETH_CLK 11
+#define HI3516CV300_ETH_MACIF_CLK 12
+#define HI3516CV300_DMAC_CLK 13
+#define HI3516CV300_PWM_CLK 14
+#define HI3516CV300_USB2_BUS_CLK 15
+#define HI3516CV300_USB2_OHCI48M_CLK 16
+#define HI3516CV300_USB2_OHCI12M_CLK 17
+#define HI3516CV300_USB2_OTG_UTMI_CLK 18
+#define HI3516CV300_USB2_HST_PHY_CLK 19
+#define HI3516CV300_USB2_UTMI0_CLK 20
+#define HI3516CV300_USB2_PHY_CLK 21
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_WDT_CLK 1
+
+#endif /* __DTS_HI3516CV300_CLOCK_H */
--
2.9.3
^ permalink raw reply related
* [PATCH 1/3] arm: hisi: add ARCH_MULTI_V5 support
From: Pan Wen @ 2016-10-17 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017120705.3726-1-wenpan@hisilicon.com>
Add support for some HiSilicon SoCs which depend on ARCH_MULTI_V5.
Signed-off-by: Pan Wen <wenpan@hisilicon.com>
---
arch/arm/mach-hisi/Kconfig | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index a3b091a..03d8379 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,12 +1,14 @@
config ARCH_HISI
bool "Hisilicon SoC Support"
- depends on ARCH_MULTI_V7
select ARM_AMBA
- select ARM_GIC
+ select ARM_GIC if ARCH_MULTI_V7
+ select ARM_VIC if ARCH_MULTI_V5
select ARM_TIMER_SP804
select POWER_RESET
select POWER_RESET_HISI
select POWER_SUPPLY
+ select PINCTRL
+ select PINCTRL_SINGLE
if ARCH_HISI
@@ -18,8 +20,6 @@ config ARCH_HI3xxx
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
- select PINCTRL
- select PINCTRL_SINGLE
help
Support for Hisilicon Hi36xx SoC family
@@ -48,8 +48,6 @@ config ARCH_HIX5HD2
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
- select PINCTRL
- select PINCTRL_SINGLE
help
Support for Hisilicon HIX5HD2 SoC family
endmenu
--
2.9.3
^ permalink raw reply related
* [PATCH 0/3] add basic SoC support for HiSilicon Hi3516CV300
From: Pan Wen @ 2016-10-17 12:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi3516CV300 is a SoC designed for HD IP camera. It has an integrated ISP and
H.265 video compression encoder. This patch set is mainly used to add basic SoC
support for Hi3516CV300. It includes crg driver and basic dts files.
Pan Wen (3):
arm: hisi: add ARCH_MULTI_V5 support
clk: hisilicon: add CRG driver for Hi3516CV300 SoC
dts: hisi: add dts files for Hi3516CV300 demo board
.../devicetree/bindings/clock/hisi-crg.txt | 50 +++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/hi3516cv300-demb.dts | 148 ++++++++
arch/arm/boot/dts/hi3516cv300.dtsi | 397 +++++++++++++++++++++
arch/arm/mach-hisi/Kconfig | 10 +-
drivers/clk/hisilicon/Kconfig | 8 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/crg-hi3516cv300.c | 330 +++++++++++++++++
drivers/clk/hisilicon/crg.h | 34 ++
include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++
10 files changed, 1021 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt
create mode 100644 arch/arm/boot/dts/hi3516cv300-demb.dts
create mode 100644 arch/arm/boot/dts/hi3516cv300.dtsi
create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c
create mode 100644 drivers/clk/hisilicon/crg.h
create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h
--
2.9.3
^ permalink raw reply
* [PATCH 2/2] arm64: Wire up iommu_dma_{map, unmap}_resource()
From: Robin Murphy @ 2016-10-17 12:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b6c78e6c18d98069b0fdfa219da51d2aed129aed.1476705500.git.robin.murphy@arm.com>
With no coherency to worry about, just plug'em straight in.
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Will Deacon <will.deacon@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/mm/dma-mapping.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 3f74d0d98de6..5cd0a383b14b 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -796,6 +796,8 @@ static void __iommu_unmap_sg_attrs(struct device *dev,
.sync_single_for_device = __iommu_sync_single_for_device,
.sync_sg_for_cpu = __iommu_sync_sg_for_cpu,
.sync_sg_for_device = __iommu_sync_sg_for_device,
+ .map_resource = iommu_dma_map_resource,
+ .unmap_resource = iommu_dma_unmap_resource,
.dma_supported = iommu_dma_supported,
.mapping_error = iommu_dma_mapping_error,
};
--
1.9.1
^ permalink raw reply related
* [PATCH 1/2] iommu/dma: Implement dma_{map,unmap}_resource()
From: Robin Murphy @ 2016-10-17 12:05 UTC (permalink / raw)
To: linux-arm-kernel
With the new dma_{map,unmap}_resource() functions added to the DMA API
for the benefit of cases like slave DMA, add suitable implementations to
the arsenal of our generic layer. Since cache maintenance should not be
a concern, these can both be standalone versions without the need for
architecture-specific wrappers.
CC: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
Since patch 2 has a build dependency on this one, they should probably
go together through either the arm64 tree or the iommu tree, but I can't
make up my mind which one seems more appropriate...
Robin.
drivers/iommu/dma-iommu.c | 13 +++++++++++++
include/linux/dma-iommu.h | 4 ++++
2 files changed, 17 insertions(+)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index c5ab8667e6f2..50acd71915db 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -624,6 +624,19 @@ void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
__iommu_dma_unmap(iommu_get_domain_for_dev(dev), sg_dma_address(sg));
}
+dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
+ size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+ return iommu_dma_map_page(dev, phys_to_page(phys), offset_in_page(phys),
+ size, dma_direction_to_prot(dir, false) | IOMMU_MMIO);
+}
+
+void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+ __iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle);
+}
+
int iommu_dma_supported(struct device *dev, u64 mask)
{
/*
diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h
index 32c589062bd9..7f7e9a7e3839 100644
--- a/include/linux/dma-iommu.h
+++ b/include/linux/dma-iommu.h
@@ -61,6 +61,10 @@ void iommu_dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
enum dma_data_direction dir, unsigned long attrs);
void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction dir, unsigned long attrs);
+dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
+ size_t size, enum dma_data_direction dir, unsigned long attrs);
+void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir, unsigned long attrs);
int iommu_dma_supported(struct device *dev, u64 mask);
int iommu_dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
--
1.9.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox