* [PATCH v2] MAINTAINERS: add myself as Marvell berlin SoC maintainer
From: Olof Johansson @ 2016-10-17 21:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160929105120.374-1-jszhang@marvell.com>
On Thu, Sep 29, 2016 at 06:51:20PM +0800, Jisheng Zhang wrote:
> I would like to take maintainership for Marvell berlin SoCs.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Applied to fixes. Thanks.
-Olof
^ permalink raw reply
* [PATCH V4 1/2] ACPI: Add support for ResourceSource/IRQ domain mapping
From: Timur Tabi @ 2016-10-17 21:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476738177-24979-2-git-send-email-agustinv@codeaurora.org>
Just a few nits:
Agustin Vega-Frias wrote:
> +int acpi_irq_domain_register_irq(struct acpi_resource_source *source, u32 hwirq,
> + int trigger, int polarity)
> +{
> + struct irq_fwspec fwspec;
> + struct acpi_device *device;
> + acpi_handle handle;
> + acpi_status status;
> + int ret;
> +
> + if (source->string_length == 0)
Would (!source->string_length) be more meaningful?
> + return acpi_register_gsi(NULL, hwirq, trigger, polarity);
> +
> + status = acpi_get_handle(NULL, source->string_ptr, &handle);
> + if (ACPI_FAILURE(status))
> + return -ENODEV;
> +
> + device = acpi_bus_get_acpi_device(handle);
> + if (!device)
> + return -ENODEV;
> +
> + if (acpi_irq_domain_ensure_probed(device))
> + return -ENODEV;
> +
> + fwspec.fwnode = &device->fwnode;
> + fwspec.param[0] = hwirq;
> + fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
> + fwspec.param_count = 2;
> +
> + ret = irq_create_fwspec_mapping(&fwspec);
> + acpi_bus_put_acpi_device(device);
> + return ret;
Blank line before 'return'.
> -static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
> +static void acpi_dev_get_irqresource(struct resource *res, u32 hwirq,
> + struct acpi_resource_source *source,
This should probably be a 'const', because ...
> @@ -448,6 +449,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
> {
> struct acpi_resource_irq *irq;
> struct acpi_resource_extended_irq *ext_irq;
> + struct acpi_resource_source dummy = { 0, 0, NULL };
... then you can make this a static const, which will reduce code size
and improve performance.
> @@ -1024,6 +1030,43 @@ struct acpi_probe_entry {
> (&ACPI_PROBE_TABLE_END(t) - \
> &ACPI_PROBE_TABLE(t))); \
> })
> +
> +#define ACPI_HID_LEN 9
Please add a comment for this.
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH V4 2/2] irqchip: qcom: Add IRQ combiner driver
From: Agustin Vega-Frias @ 2016-10-17 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476738177-24979-1-git-send-email-agustinv@codeaurora.org>
Driver for interrupt combiners in the Top-level Control and Status
Registers (TCSR) hardware block in Qualcomm Technologies chips.
An interrupt combiner in this block combines a set of interrupts by
OR'ing the individual interrupt signals into a summary interrupt
signal routed to a parent interrupt controller, and provides read-
only, 32-bit registers to query the status of individual interrupts.
The status bit for IRQ n is bit (n % 32) within register (n / 32)
of the given combiner. Thus, each combiner can be described as a set
of register offsets and the number of IRQs managed.
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
---
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/qcom-irq-combiner.c | 332 ++++++++++++++++++++++++++++++++++++
3 files changed, 341 insertions(+)
create mode 100644 drivers/irqchip/qcom-irq-combiner.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 82b0b5d..05ecd91 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -279,3 +279,11 @@ config EZNPS_GIC
config STM32_EXTI
bool
select IRQ_DOMAIN
+
+config QCOM_IRQ_COMBINER
+ bool "QCOM IRQ combiner support"
+ depends on ARCH_QCOM
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for the IRQ combiner devices embedded
+ in Qualcomm Technologies chips.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e4dbfc8..1818a0b 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
+obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
diff --git a/drivers/irqchip/qcom-irq-combiner.c b/drivers/irqchip/qcom-irq-combiner.c
new file mode 100644
index 0000000..b117cd7
--- /dev/null
+++ b/drivers/irqchip/qcom-irq-combiner.c
@@ -0,0 +1,332 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Driver for interrupt combiners in the Top-level Control and Status
+ * Registers (TCSR) hardware block in Qualcomm Technologies chips.
+ * An interrupt combiner in this block combines a set of interrupts by
+ * OR'ing the individual interrupt signals into a summary interrupt
+ * signal routed to a parent interrupt controller, and provides read-
+ * only, 32-bit registers to query the status of individual interrupts.
+ * The status bit for IRQ n is bit (n % 32) within register (n / 32)
+ * of the given combiner. Thus, each combiner can be described as a set
+ * of register offsets and the number of IRQs managed.
+ */
+
+#include <linux/acpi.h>
+#include <linux/err.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+
+#define REG_SIZE 32
+
+struct combiner_reg {
+ void __iomem *addr;
+ unsigned long mask;
+};
+
+struct combiner {
+ struct irq_chip irq_chip;
+ struct irq_domain *domain;
+ int parent_irq;
+ u32 nirqs;
+ u32 nregs;
+ struct combiner_reg regs[0];
+};
+
+static inline u32 irq_register(int irq)
+{
+ return irq / REG_SIZE;
+}
+
+static inline u32 irq_bit(int irq)
+{
+ return irq % REG_SIZE;
+
+}
+
+static inline int irq_nr(u32 reg, u32 bit)
+{
+ return reg * REG_SIZE + bit;
+}
+
+/*
+ * Handler for the cascaded IRQ.
+ */
+static void combiner_handle_irq(struct irq_desc *desc)
+{
+ struct combiner *combiner = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 reg;
+
+ chained_irq_enter(chip, desc);
+
+ for (reg = 0; reg < combiner->nregs; reg++) {
+ int virq;
+ int hwirq;
+ u32 bit;
+ u32 status;
+
+ if (combiner->regs[reg].mask == 0)
+ continue;
+
+ status = readl_relaxed(combiner->regs[reg].addr);
+ status &= combiner->regs[reg].mask;
+
+ while (status) {
+ bit = __ffs(status);
+ status &= ~(1 << bit);
+ hwirq = irq_nr(reg, bit);
+ virq = irq_find_mapping(combiner->domain, hwirq);
+ if (virq >= 0)
+ generic_handle_irq(virq);
+
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+/*
+ * irqchip callbacks
+ */
+
+static void combiner_irq_chip_mask_irq(struct irq_data *data)
+{
+ struct combiner *combiner = irq_data_get_irq_chip_data(data);
+ struct combiner_reg *reg = combiner->regs + irq_register(data->hwirq);
+
+ clear_bit(irq_bit(data->hwirq), ®->mask);
+}
+
+static void combiner_irq_chip_unmask_irq(struct irq_data *data)
+{
+ struct combiner *combiner = irq_data_get_irq_chip_data(data);
+ struct combiner_reg *reg = combiner->regs + irq_register(data->hwirq);
+
+ set_bit(irq_bit(data->hwirq), ®->mask);
+}
+
+/*
+ * irq_domain_ops callbacks
+ */
+
+static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct combiner *combiner = domain->host_data;
+
+ if (hwirq >= combiner->nirqs)
+ return -EINVAL;
+
+ irq_set_chip_and_handler(irq, &combiner->irq_chip, handle_level_irq);
+ irq_set_chip_data(irq, combiner);
+ irq_set_parent(irq, combiner->parent_irq);
+ irq_set_noprobe(irq);
+ return 0;
+}
+
+static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
+{
+ irq_set_chip_and_handler(irq, NULL, NULL);
+ irq_set_chip_data(irq, NULL);
+ irq_set_parent(irq, -1);
+}
+
+#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
+static int combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws,
+ unsigned long *hwirq, unsigned int *type)
+{
+ if (is_acpi_node(fws->fwnode)) {
+ if (fws->param_count != 2)
+ return -EINVAL;
+
+ *hwirq = fws->param[0];
+ *type = fws->param[1];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+#endif
+
+static const struct irq_domain_ops domain_ops = {
+ .map = combiner_irq_map,
+ .unmap = combiner_irq_unmap,
+#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
+ .translate = combiner_irq_translate
+#endif
+};
+
+/*
+ * Device probing
+ */
+
+static acpi_status count_registers_cb(struct acpi_resource *ares, void *context)
+{
+ int *count = context;
+
+ if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
+ ++(*count);
+ return AE_OK;
+}
+
+static int count_registers(struct acpi_device *adev)
+{
+ acpi_status status;
+ int count = 0;
+
+ if (!acpi_has_method(adev->handle, METHOD_NAME__CRS))
+ return -EINVAL;
+
+ status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS,
+ count_registers_cb, &count);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+ return count;
+}
+
+struct get_registers_context {
+ struct device *dev;
+ struct combiner *combiner;
+ int err;
+};
+
+static acpi_status get_registers_cb(struct acpi_resource *ares, void *context)
+{
+ struct get_registers_context *ctx = context;
+ struct acpi_resource_generic_register *reg;
+ phys_addr_t paddr;
+ void __iomem *vaddr;
+
+ if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
+ return AE_OK;
+
+ reg = &ares->data.generic_reg;
+ paddr = reg->address;
+ if ((reg->space_id != ACPI_SPACE_MEM) ||
+ (reg->bit_offset != 0) ||
+ (reg->bit_width > REG_SIZE)) {
+ dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
+ ctx->err = -EINVAL;
+ return AE_ERROR;
+ }
+
+ vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
+ if (IS_ERR(vaddr)) {
+ dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
+ ctx->err = PTR_ERR(vaddr);
+ return AE_ERROR;
+ }
+
+ ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
+ ctx->combiner->nirqs += reg->bit_width;
+ ctx->combiner->nregs++;
+ return AE_OK;
+}
+
+static int get_registers(struct acpi_device *adev, struct combiner *comb)
+{
+ acpi_status status;
+ struct get_registers_context ctx;
+
+ if (!acpi_has_method(adev->handle, METHOD_NAME__CRS))
+ return -EINVAL;
+
+ ctx.dev = &adev->dev;
+ ctx.combiner = comb;
+ ctx.err = 0;
+
+ status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS,
+ get_registers_cb, &ctx);
+ if (ACPI_FAILURE(status))
+ return ctx.err;
+ return 0;
+}
+
+static acpi_status get_parent_irq_cb(struct acpi_resource *ares, void *context)
+{
+ int *irq = context;
+ struct acpi_resource_extended_irq *eirq;
+
+ if (ares->type != ACPI_RESOURCE_TYPE_EXTENDED_IRQ)
+ return AE_OK;
+
+ eirq = &ares->data.extended_irq;
+ *irq = acpi_irq_domain_register_irq(&eirq->resource_source,
+ eirq->interrupts[0],
+ eirq->triggering, eirq->polarity);
+ return AE_OK;
+}
+
+static int get_parent_irq(struct acpi_device *adev)
+{
+ acpi_status status;
+ int irq = -1;
+
+ if (!acpi_has_method(adev->handle, METHOD_NAME__CRS))
+ return -EINVAL;
+
+ status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS,
+ get_parent_irq_cb, &irq);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+ return irq;
+}
+
+static int __init combiner_probe(struct acpi_device *adev)
+{
+ struct combiner *combiner;
+ size_t alloc_sz;
+ u32 nregs;
+ int err;
+
+ nregs = count_registers(adev);
+ if (nregs <= 0) {
+ dev_err(&adev->dev, "Error reading register resources\n");
+ return -EINVAL;
+ }
+
+ alloc_sz = sizeof(*combiner) + sizeof(struct combiner_reg) * nregs;
+ combiner = devm_kzalloc(&adev->dev, alloc_sz, GFP_KERNEL);
+ if (!combiner)
+ return -ENOMEM;
+
+ err = get_registers(adev, combiner);
+ if (err < 0)
+ return err;
+
+ combiner->parent_irq = get_parent_irq(adev);
+ if (combiner->parent_irq <= 0) {
+ dev_err(&adev->dev, "Error getting IRQ resource\n");
+ return -EINVAL;
+ }
+
+ combiner->domain = irq_domain_create_linear(
+ &adev->fwnode, combiner->nirqs, &domain_ops, combiner);
+ if (!combiner->domain)
+ /* Errors printed by irq_domain_create_linear */
+ return -ENODEV;
+
+ irq_set_chained_handler_and_data(combiner->parent_irq,
+ combiner_handle_irq, combiner);
+ combiner->irq_chip.irq_mask = combiner_irq_chip_mask_irq;
+ combiner->irq_chip.irq_unmask = combiner_irq_chip_unmask_irq;
+ combiner->irq_chip.name = dev_name(&adev->dev);
+
+ dev_info(&adev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
+ combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
+ return 0;
+}
+
+IRQCHIP_ACPI_DECLARE(qcom_combiner, "QCOM80B1", combiner_probe);
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [PATCH V4 1/2] ACPI: Add support for ResourceSource/IRQ domain mapping
From: Agustin Vega-Frias @ 2016-10-17 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476738177-24979-1-git-send-email-agustinv@codeaurora.org>
This allows irqchip drivers to associate an ACPI DSDT device to
an IRQ domain and provides support for using the ResourceSource
in Extended IRQ Resources to find the domain and map the IRQs
specified on that domain.
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
---
drivers/acpi/Makefile | 1 +
drivers/acpi/irqdomain.c | 135 ++++++++++++++++++++++++++++++++++++++
drivers/acpi/resource.c | 21 +++---
include/asm-generic/vmlinux.lds.h | 1 +
include/linux/acpi.h | 50 ++++++++++++++
include/linux/irqchip.h | 17 ++++-
6 files changed, 213 insertions(+), 12 deletions(-)
create mode 100644 drivers/acpi/irqdomain.c
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index 9ed0878..81bdc95 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -57,6 +57,7 @@ acpi-$(CONFIG_ACPI_PROCFS_POWER) += cm_sbs.o
acpi-y += acpi_lpat.o
acpi-$(CONFIG_ACPI_GENERIC_GSI) += gsi.o
acpi-$(CONFIG_ACPI_WATCHDOG) += acpi_watchdog.o
+acpi-y += irqdomain.o
# These are (potentially) separate modules
diff --git a/drivers/acpi/irqdomain.c b/drivers/acpi/irqdomain.c
new file mode 100644
index 0000000..0429607
--- /dev/null
+++ b/drivers/acpi/irqdomain.c
@@ -0,0 +1,135 @@
+/*
+ * ACPI ResourceSource/IRQ domain mapping support
+ *
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/acpi.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+
+/**
+ * acpi_irq_domain_ensure_probed() - Check if the device has registered
+ * an IRQ domain and probe as necessary
+ *
+ * @device: Device to check and probe
+ *
+ * Returns: 0 on success, -ENODEV otherwise
+ */
+static int acpi_irq_domain_ensure_probed(struct acpi_device *device)
+{
+ struct acpi_dsdt_probe_entry *entry;
+
+ if (irq_find_matching_fwnode(&device->fwnode, DOMAIN_BUS_ANY) != 0)
+ return 0;
+
+ for (entry = &__dsdt_acpi_probe_table;
+ entry < &__dsdt_acpi_probe_table_end; e++)
+ if (strcmp(e->_hid, acpi_device_hid(device)) == 0)
+ return e->probe(device);
+
+ return -ENODEV;
+}
+
+/**
+ * acpi_irq_domain_register_irq() - Register the mapping for an IRQ produced
+ * by the given acpi_resource_source to a
+ * Linux IRQ number
+ * @source: IRQ source
+ * @hwirq: Hardware IRQ number
+ * @trigger: trigger type of the IRQ number to be mapped
+ * @polarity: polarity of the IRQ to be mapped
+ *
+ * Returns: a valid linux IRQ number on success
+ * -ENODEV if the given acpi_resource_source cannot be found
+ * -EPROBE_DEFER if the IRQ domain has not been registered
+ * -EINVAL for all other errors
+ */
+int acpi_irq_domain_register_irq(struct acpi_resource_source *source, u32 hwirq,
+ int trigger, int polarity)
+{
+ struct irq_fwspec fwspec;
+ struct acpi_device *device;
+ acpi_handle handle;
+ acpi_status status;
+ int ret;
+
+ if (source->string_length == 0)
+ return acpi_register_gsi(NULL, hwirq, trigger, polarity);
+
+ status = acpi_get_handle(NULL, source->string_ptr, &handle);
+ if (ACPI_FAILURE(status))
+ return -ENODEV;
+
+ device = acpi_bus_get_acpi_device(handle);
+ if (!device)
+ return -ENODEV;
+
+ if (acpi_irq_domain_ensure_probed(device))
+ return -ENODEV;
+
+ fwspec.fwnode = &device->fwnode;
+ fwspec.param[0] = hwirq;
+ fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
+ fwspec.param_count = 2;
+
+ ret = irq_create_fwspec_mapping(&fwspec);
+ acpi_bus_put_acpi_device(device);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(acpi_irq_domain_register_irq);
+
+/**
+ * acpi_irq_domain_unregister_irq() - Delete the mapping for an IRQ produced
+ * by the given acpi_resource_source to a
+ * Linux IRQ number
+ * @source: IRQ source
+ * @hwirq: Hardware IRQ number
+ *
+ * Returns: 0 on success
+ * -ENODEV if the given acpi_resource_source cannot be found
+ * -EINVAL for all other errors
+ */
+int acpi_irq_domain_unregister_irq(struct acpi_resource_source *source,
+ u32 hwirq)
+{
+ struct irq_domain *domain;
+ struct acpi_device *device;
+ acpi_handle handle;
+ acpi_status status;
+ int ret = 0;
+
+ if (source->string_length == 0) {
+ acpi_unregister_gsi(hwirq);
+ return 0;
+ }
+
+ status = acpi_get_handle(NULL, source->string_ptr, &handle);
+ if (ACPI_FAILURE(status))
+ return -ENODEV;
+
+ device = acpi_bus_get_acpi_device(handle);
+ if (!device)
+ return -ENODEV;
+
+ domain = irq_find_matching_fwnode(&device->fwnode, DOMAIN_BUS_ANY);
+ if (!domain) {
+ ret = -EINVAL;
+ goto out_put_device;
+ }
+
+ irq_dispose_mapping(irq_find_mapping(domain, hwirq));
+
+out_put_device:
+ acpi_bus_put_acpi_device(device);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(acpi_irq_domain_unregister_irq);
diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c
index 56241eb..8e69a7a 100644
--- a/drivers/acpi/resource.c
+++ b/drivers/acpi/resource.c
@@ -381,14 +381,15 @@ static void acpi_dev_irqresource_disabled(struct resource *res, u32 gsi)
res->flags = IORESOURCE_IRQ | IORESOURCE_DISABLED | IORESOURCE_UNSET;
}
-static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
+static void acpi_dev_get_irqresource(struct resource *res, u32 hwirq,
+ struct acpi_resource_source *source,
u8 triggering, u8 polarity, u8 shareable,
bool legacy)
{
int irq, p, t;
- if (!valid_IRQ(gsi)) {
- acpi_dev_irqresource_disabled(res, gsi);
+ if ((source->string_length == 0) && !valid_IRQ(hwirq)) {
+ acpi_dev_irqresource_disabled(res, hwirq);
return;
}
@@ -402,25 +403,25 @@ static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
* using extended IRQ descriptors we take the IRQ configuration
* from _CRS directly.
*/
- if (legacy && !acpi_get_override_irq(gsi, &t, &p)) {
+ if (legacy && !acpi_get_override_irq(hwirq, &t, &p)) {
u8 trig = t ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
u8 pol = p ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
if (triggering != trig || polarity != pol) {
- pr_warning("ACPI: IRQ %d override to %s, %s\n", gsi,
- t ? "level" : "edge", p ? "low" : "high");
+ pr_warn("ACPI: IRQ %d override to %s, %s\n", hwirq,
+ t ? "level" : "edge", p ? "low" : "high");
triggering = trig;
polarity = pol;
}
}
res->flags = acpi_dev_irq_flags(triggering, polarity, shareable);
- irq = acpi_register_gsi(NULL, gsi, triggering, polarity);
+ irq = acpi_irq_domain_register_irq(source, hwirq, triggering, polarity);
if (irq >= 0) {
res->start = irq;
res->end = irq;
} else {
- acpi_dev_irqresource_disabled(res, gsi);
+ acpi_dev_irqresource_disabled(res, hwirq);
}
}
@@ -448,6 +449,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
{
struct acpi_resource_irq *irq;
struct acpi_resource_extended_irq *ext_irq;
+ struct acpi_resource_source dummy = { 0, 0, NULL };
switch (ares->type) {
case ACPI_RESOURCE_TYPE_IRQ:
@@ -460,7 +462,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
acpi_dev_irqresource_disabled(res, 0);
return false;
}
- acpi_dev_get_irqresource(res, irq->interrupts[index],
+ acpi_dev_get_irqresource(res, irq->interrupts[index], &dummy,
irq->triggering, irq->polarity,
irq->sharable, true);
break;
@@ -471,6 +473,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
return false;
}
acpi_dev_get_irqresource(res, ext_irq->interrupts[index],
+ &ext_irq->resource_source,
ext_irq->triggering, ext_irq->polarity,
ext_irq->sharable, false);
break;
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 3074796..f808afdc 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -563,6 +563,7 @@
IRQCHIP_OF_MATCH_TABLE() \
ACPI_PROBE_TABLE(irqchip) \
ACPI_PROBE_TABLE(clksrc) \
+ ACPI_PROBE_TABLE(dsdt) \
EARLYCON_TABLE()
#define INIT_TEXT \
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index ddbeda6..619cd4f 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -26,6 +26,7 @@
#include <linux/resource_ext.h>
#include <linux/device.h>
#include <linux/property.h>
+#include <linux/irqdomain.h>
#ifndef _LINUX
#define _LINUX
@@ -309,6 +310,11 @@ static inline bool acpi_sci_irq_valid(void)
void acpi_set_irq_model(enum acpi_irq_model_id model,
struct fwnode_handle *fwnode);
+int acpi_irq_domain_register_irq(struct acpi_resource_source *source, u32 hwirq,
+ int trigger, int polarity);
+int acpi_irq_domain_unregister_irq(struct acpi_resource_source *source,
+ u32 hwirq);
+
#ifdef CONFIG_X86_IO_APIC
extern int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
#else
@@ -1024,6 +1030,43 @@ struct acpi_probe_entry {
(&ACPI_PROBE_TABLE_END(t) - \
&ACPI_PROBE_TABLE(t))); \
})
+
+#define ACPI_HID_LEN 9
+
+typedef int (*acpi_dsdt_handler)(struct acpi_device *);
+
+/**
+ * struct acpi_probe_dsdt_entry - boot-time probing entry for DSDT devices
+ * @hid: _HID of the device
+ * @fn: Callback to the driver being probed
+ * @driver_data: Sideband data provided back to the driver
+ */
+struct acpi_dsdt_probe_entry {
+ __u8 _hid[ACPI_HID_LEN];
+ acpi_dsdt_handler probe;
+};
+
+#define ACPI_DECLARE_DSDT_PROBE_ENTRY(name, hid, fn) \
+ static const struct acpi_dsdt_probe_entry __acpi_probe_##name \
+ __used __section(__dsdt_acpi_probe_table) = \
+ { \
+ ._hid = hid, \
+ .probe = fn, \
+ }
+
+extern struct acpi_dsdt_probe_entry __dsdt_acpi_probe_table;
+extern struct acpi_dsdt_probe_entry __dsdt_acpi_probe_table_end;
+
+#define MADT_IRQCHIP_ACPI_DECLARE(name, subtable, validate, data, fn) \
+ ACPI_DECLARE_PROBE_ENTRY(irqchip, name, ACPI_SIG_MADT, \
+ subtable, validate, data, fn)
+
+#define DSDT_IRQCHIP_ACPI_DECLARE(name, hid, fn) \
+ ACPI_DECLARE_DSDT_PROBE_ENTRY(name, hid, fn)
+
+#define __IRQCHIP_ACPI_DECLARE(_a1, _a2, _a3, _a4, _a5, type, ...) \
+ type##_IRQCHIP_ACPI_DECLARE
+
#else
static inline int acpi_dev_get_property(struct acpi_device *adev,
const char *name, acpi_object_type type,
@@ -1101,6 +1144,13 @@ static inline struct fwnode_handle *acpi_get_next_subnode(struct device *dev,
(void *) data }
#define acpi_probe_device_table(t) ({ int __r = 0; __r;})
+
+#define ACPI_DECLARE_DSDT_PROBE_ENTRY(name, hid, fn) \
+ static const void *__acpi_probe_##name[] \
+ __attribute__((unused)) \
+ = { (void *) hid, \
+ (void *) fn }
+
#endif
#ifdef CONFIG_ACPI_TABLE_UPGRADE
diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h
index 89c34b2..c2d0c12 100644
--- a/include/linux/irqchip.h
+++ b/include/linux/irqchip.h
@@ -29,6 +29,10 @@
/*
* This macro must be used by the different irqchip drivers to declare
* the association between their version and their initialization function.
+ * Two syntaxes are supported depending on the table where the irqchip device
+ * is declared:
+ *
+ * - MADT irqchip syntax, which requires the following five arguments:
*
* @name: name that must be unique accross all IRQCHIP_ACPI_DECLARE of the
* same file.
@@ -37,10 +41,17 @@
* Can be NULL.
* @data: data to be checked by the validate function.
* @fn: initialization function
+ *
+ * - DSDT irqchip syntax, which requires the following three arguments:
+ *
+ * @name: name that must be unique across all IRQCHIP_ACPI_DECLARE of the
+ * same file.
+ * @hid: _HID of the DSDT device
+ * @fn: initialization function
*/
-#define IRQCHIP_ACPI_DECLARE(name, subtable, validate, data, fn) \
- ACPI_DECLARE_PROBE_ENTRY(irqchip, name, ACPI_SIG_MADT, \
- subtable, validate, data, fn)
+
+#define IRQCHIP_ACPI_DECLARE(...) \
+ __IRQCHIP_ACPI_DECLARE(__VA_ARGS__, MADT, _unused, DSDT)(__VA_ARGS__)
#ifdef CONFIG_IRQCHIP
void irqchip_init(void);
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [PATCH V4 0/2] irqchip: qcom: Add IRQ combiner driver
From: Agustin Vega-Frias @ 2016-10-17 21:02 UTC (permalink / raw)
To: linux-arm-kernel
Add support for IRQ combiners in the Top-level Control and Status
Registers (TCSR) hardware block in Qualcomm Technologies chips.
The first patch adds support for ResourceSource/IRQ domain mapping
when using Extended IRQ Resources with a specific ResourceSource.
The core ACPI resource management code has been changed to lookup
the IRQ domain when an IRQ resource indicates a ResourceSource,
and register the IRQ on that domain, instead of a GSI.
The second patch takes advantage of the new capabilities to implement
the driver for the IRQ combiners.
Changes V1 -> V2:
* Remove use of GPIO library for the combiner
* Refactor to use fwnode/ResourceSource to IRQ domain mapping
introduced in ACPI core
Changes V2 -> V3:
* Removed parsing of _PRS to find IRQs
* Removed acpi_irq_domain_create and acpi_irq_domain_remove
Changes V3 -> V3:
* Add a DSDT device probe table that is used to probe DSDT IRQ chips
as necessary when converting HW IRQs to Linux IRQs
* Describe IRQ combiner registers as ACPI Register resources
Agustin Vega-Frias (2):
ACPI: Add support for ResourceSource/IRQ domain mapping
irqchip: qcom: Add IRQ combiner driver
drivers/acpi/Makefile | 1 +
drivers/acpi/irqdomain.c | 135 +++++++++++++++
drivers/acpi/resource.c | 21 ++-
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/qcom-irq-combiner.c | 332 ++++++++++++++++++++++++++++++++++++
include/asm-generic/vmlinux.lds.h | 1 +
include/linux/acpi.h | 50 ++++++
include/linux/irqchip.h | 17 +-
9 files changed, 554 insertions(+), 12 deletions(-)
create mode 100644 drivers/acpi/irqdomain.c
create mode 100644 drivers/irqchip/qcom-irq-combiner.c
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH v20 02/10] doc: fpga-mgr: add fpga image info to api
From: Moritz Fischer @ 2016-10-17 21:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017160941.4205-3-atull@opensource.altera.com>
Hi Alan,
couple of nits inline and some comments on ordering the patches ;-)
On Mon, Oct 17, 2016 at 6:09 PM, Alan Tull <atull@opensource.altera.com> wrote:
> This patch adds a minor change in the FPGA Mangager API
s/Mangager/Manager/
> to hold information that is specific to an FPGA image
> file. This change is expected to bring little, if any,
> pain.
>
> An FPGA image file will have particulars that affect how the
> image is programmed to the FPGA. One example is that
> current 'flags' currently has one bit which shows whether the
> FPGA image was built for full reconfiguration or partial
> reconfiguration. Another example is timeout values for
> enabling or disabling the bridges in the FPGA. As the
> complexity of the FPGA design increases, the bridges in the
> FPGA may take longer times to enable or disable.
According for the current ordering bridges are not yet defined if we
merge patches in this order?
Not terrible imho, but I thought I'd point it out. Would swapping the
order make sense?
I also think [5/10] should be squashed together with this commit to
make it an atomic change.
Apart from my comments above feel free to add my Acked-by
Thanks for keeping this going,
Moritz
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: Updated NAND DT properties for NS2 SVK
From: Ray Jui @ 2016-10-17 20:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1469051631-7896-3-git-send-email-ray.jui@broadcom.com>
Hi Florian,
Would you be able to help to queue the following patch for v4.10? Sorry
I did not include you in the "To" field of the original email.
Thanks,
Ray
On 7/20/2016 2:53 PM, Ray Jui wrote:
> This patch adds NAND DT properties for NS2 SVK to configure the bus
> width width and OOB sector size
>
> Signed-off-by: Prafulla Kota <prafulla.kota@broadcom.com>
> Signed-off-by: Ray Jui <ray.jui@broadcom.com>
> ---
> arch/arm64/boot/dts/broadcom/ns2-svk.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
> index 54ca40c..5ef0407 100644
> --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
> +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
> @@ -128,6 +128,8 @@
> nand-ecc-mode = "hw";
> nand-ecc-strength = <8>;
> nand-ecc-step-size = <512>;
> + nand-bus-width = <16>;
> + brcm,nand-oob-sector-size = <16>;
> #address-cells = <1>;
> #size-cells = <1>;
> };
>
^ permalink raw reply
* [PATCH v2 1/2] arm64: dts: zx: Fix gic GICR property
From: Olof Johansson @ 2016-10-17 20:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476361881-19685-2-git-send-email-jun.nie@linaro.org>
On Thu, Oct 13, 2016 at 08:31:20PM +0800, Jun Nie wrote:
> GICR for multiple CPU can be described with start address and stride,
> or with multiple address. Current multiple address and stride are
> both used. Fix it.
>
> vmalloc patch 727a7f5a9 triggered this bug:
> [ 0.097146] Unable to handle kernel paging request at virtual address ffff000008060008
> [ 0.097150] pgd = ffff000008602000
> [ 0.097160] [ffff000008060008] *pgd=000000007fffe003, *pud=000000007fffd003, *pmd=000000007fffc003, *pte=0000000000000000
> [ 0.097165] Internal error: Oops: 96000007 [#1] PREEMPT SMP
> [ 0.097170] Modules linked in:
> [ 0.097177] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.8.0+ #1474
> [ 0.097179] Hardware name: ZTE zx296718 evaluation board (DT)
> [ 0.097183] task: ffff80003e8c8b80 task.stack: ffff80003e8d0000
> [ 0.097197] PC is at gic_populate_rdist+0x74/0x15c
> [ 0.097202] LR is at gic_starting_cpu+0xc/0x20
> [ 0.097206] pc : [<ffff0000082b1b18>] lr : [<ffff0000082b26e0>] pstate: 600001c5
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
A Fixes: tag would be useful on a patch like this, to tell what patch
introduced the problem. Please consider using them in the future.
I've applied this one to fixes now.
-Olof
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: zx: Add clock controller nodes
From: Olof Johansson @ 2016-10-17 20:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476361881-19685-3-git-send-email-jun.nie@linaro.org>
On Thu, Oct 13, 2016 at 08:31:21PM +0800, Jun Nie wrote:
> Add clock controller nodes, including one top controller
> two low speed controllers and one audio controller.
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
> arch/arm64/boot/dts/zte/zx296718.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
This isn't a fix for a bug, so please send this with your other updates for
v4.10.
Thanks,
-Olof
^ permalink raw reply
* [GIT PULL] ARM: mvebu: fixes for v4.8 (#3)
From: Olof Johansson @ 2016-10-17 20:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6481361.Tzq3EBKYRj@wuerfel>
On Mon, Oct 17, 2016 at 03:42:30PM +0200, Arnd Bergmann wrote:
> On Monday, October 17, 2016 2:51:03 PM CEST Gregory CLEMENT wrote:
> > Hi Arnd,
> >
> > On mer., sept. 21 2016, Arnd Bergmann <arnd@arndb.de> wrote:
> >
> > > On Tuesday, September 20, 2016 6:14:47 PM CEST Gregory CLEMENT wrote:
> > >> mvebu fixes for 4.8 (part 3)
> > >>
> > >> - Select corediv clk for all mvebu v7 SoC
> > >> - Fix clocksource for CP110 master SPI0 for Armada 7K/8K
> > >>
> > >
> > > Pulled into fixes, thanks!
> >
> > I don't see this patch in the v4.8 or the v4.9-rc1.
> >
> > I think it slipped through the cracks as there were the only one in the
> > fixes branches.
> >
> > Do you think you could make them part of your next pull request for
> > fixes for 4.9-rc2?
>
> Indeed, I missed how this was still on the fixes branch during
> the merge window. It is still on that branch (and nothing else
> is so far), and it will be part of the next fixes pull request.
>
> Thanks for the reminder.
I've re-merged it since I wanted to forward the fixes branch to
v4.9-rc1, but I've made sure it's applied again.
Agreed, thanks for the reminder.
-Olof
^ permalink raw reply
* [PATCH] bus: qcom-ebi2: depend on ARCH_QCOM or COMPILE_TEST
From: Olof Johansson @ 2016-10-17 20:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475582179-5085-1-git-send-email-linus.walleij@linaro.org>
On Tue, Oct 04, 2016 at 01:56:19PM +0200, Linus Walleij wrote:
> This hides the option for people who do not want their Kconfig
> vision cluttered (i.e. x86) and enables compile testing apart
> from the supported main arch.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ARM SoC people: please apply this to next/drivers as well
> or as a fix depending on timing.
Applied to fixes. Thanks.
-Olof
^ permalink raw reply
* [PATCH] ARM: dts: fix the SD card on the Snowball
From: Olof Johansson @ 2016-10-17 20:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475830337-13016-1-git-send-email-linus.walleij@linaro.org>
On Fri, Oct 07, 2016 at 10:52:17AM +0200, Linus Walleij wrote:
> This fixes a very annoying regression on the Snowball SD card
> that has been around for a while. It turns out that the device
> tree does not configure the direction pins properly, nor sets
> up the pins for the voltage converter properly at boot. Unless
> all things are correctly set up, the feedback clock will not
> work, and makes the driver spew messages in the console (but
> it works, very slowly):
>
> root at Ux500:/ mount /dev/mmcblk0p2 /mnt/
> [ 9.953460] mmci-pl18x 80126000.sdi0_per1: error during DMA transfer!
> [ 9.960296] mmcblk0: error -110 sending status command, retrying
> [ 9.966461] mmcblk0: error -110 sending status command, retrying
> [ 9.972534] mmcblk0: error -110 sending status command, aborting
>
> Fix this by rectifying the device tree to correspond to that of
> the Ux500 HREF boards plus the DAT31DIR setting that is unique for
> the Snowball, and things start working smoothly. Add in the SDR12
> and SDR25 modes which this host can do without any problems.
>
> I don't know if this has ever been correct, sadly. It works after
> this patch.
>
> Cc: stable at vger.kernel.org
> Reported-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ARM SoC folks: please apply this directly for fixes.
Applied, thanks.
-Olof
^ permalink raw reply
* [PATCH 1/5] staging/vchi: Fix build error in debugfs ops on aarch64.
From: Greg Kroah-Hartman @ 2016-10-17 20:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017194406.1080-2-eric@anholt.net>
On Mon, Oct 17, 2016 at 12:44:02PM -0700, Eric Anholt wrote:
> file_operations.write returns a ssize_t, which worked out fine on 32
> bit but errors out on 64 bit.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
> ---
> drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
I also have already fixed this one :)
^ permalink raw reply
* [PATCH 2/5] staging/vchi: Fix build warnings when formatting pointers on aarch64.
From: Greg Kroah-Hartman @ 2016-10-17 20:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017194406.1080-3-eric@anholt.net>
On Mon, Oct 17, 2016 at 12:44:03PM -0700, Eric Anholt wrote:
> The code was generally using "%x" to print and "(unsigned int)" to
> cast the pointers, but we have %p for printing pointers in the same
> format without any broken casts.
I already did this work, it's all checked into my tree, and is in
linux-next now. You were cc:ed on the patches as well.
Also, please use "%pK" for kernel pointers, you never want to print an
address to userspace unless debugging is enabled, as it is a security
leak.
thanks,
greg k-h
^ permalink raw reply
* [PATCH v20 06/10] fpga: add fpga bridge framework
From: atull @ 2016-10-17 20:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017160941.4205-7-atull@opensource.altera.com>
On Mon, 17 Oct 2016, Alan Tull wrote:
> +/**
> + * of_fpga_bridge_get - get an exclusive reference to a fpga bridge
> + *
> + * @np: node pointer of a FPGA bridge
> + * @info: fpga image specific information
> + *
> + * Return fpga_bridge struct if successful.
> + * Return -EBUSY if someone already has a reference to the bridge.
> + * Return -ENODEV if @np is not a FPGA Bridge.
> + */
> +struct fpga_bridge *of_fpga_bridge_get(struct device_node *np,
> + struct fpga_image_info *info)
> +
> +{
> + struct device *dev;
> + struct fpga_bridge *bridge;
> + int ret = -ENODEV;
> +
> + of_node_get(np);
I thought I had fixed this. This of_node_get is unmatched,
never called in fpga_bridge_put. And it's not necessary
since class_find_device will do kobject_get on the child
device anyway. So I should remove this of_node_get
and the of_node_put below.
> +
> + dev = class_find_device(fpga_bridge_class, NULL, np,
> + fpga_bridge_of_node_match);
> + if (!dev)
> + goto err_dev;
> +
> + bridge = to_fpga_bridge(dev);
> + if (!bridge)
> + goto err_dev;
> +
> + bridge->info = info;
> +
> + if (!mutex_trylock(&bridge->mutex)) {
> + ret = -EBUSY;
> + goto err_dev;
> + }
> +
> + if (!try_module_get(dev->parent->driver->owner))
> + goto err_ll_mod;
> +
> + dev_dbg(&bridge->dev, "get\n");
> +
> + return bridge;
> +
> +err_ll_mod:
> + mutex_unlock(&bridge->mutex);
> +err_dev:
> + put_device(dev);
> + of_node_put(np);
Remove of_node_put.
> + return ERR_PTR(ret);
> +}
> +EXPORT_SYMBOL_GPL(of_fpga_bridge_get);
> +
> +/**
> + * fpga_bridge_put - release a reference to a bridge
> + *
> + * @bridge: FPGA bridge
> + */
> +void fpga_bridge_put(struct fpga_bridge *bridge)
> +{
> + dev_dbg(&bridge->dev, "put\n");
> +
> + bridge->info = NULL;
> + module_put(bridge->dev.parent->driver->owner);
> + mutex_unlock(&bridge->mutex);
> + put_device(&bridge->dev);
> +}
> +EXPORT_SYMBOL_GPL(fpga_bridge_put);
^ permalink raw reply
* [PATCH] hwrng: meson: Fix module autoload for OF registration
From: Javier Martinez Canillas @ 2016-10-17 19:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5B+iDyNJ-heFU2Th-HQHocLS3Lz5zV7hFhiLs7ESJt2gw@mail.gmail.com>
Hello Fabio,
On 10/17/2016 04:45 PM, Fabio Estevam wrote:
> On Mon, Oct 17, 2016 at 5:40 PM, Javier Martinez Canillas
> <javier@osg.samsung.com> wrote:
>
>> --- a/drivers/char/tpm/Kconfig
>> +++ b/drivers/char/tpm/Kconfig
>> @@ -32,7 +32,7 @@ config TCG_TIS_CORE
>>
>> config TCG_TIS
>> tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface"
>> - depends on X86
>> + depends on X86 || COMPILE_TEST
>
> This is a separate change.
>
Yes, I did a commit by mistake. Sorry about that.
Jason already pointed out and I posted a v2.
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH v2] hwrng: meson: Fix module autoload for OF registration
From: Javier Martinez Canillas @ 2016-10-17 19:51 UTC (permalink / raw)
To: linux-arm-kernel
If the driver is built as a module, autoload won't work because the module
alias information is not filled. So user-space can't match the registered
device with the corresponding module.
Export the module alias information using the MODULE_DEVICE_TABLE() macro.
Before this patch:
$ modinfo drivers/char/hw_random/meson-rng.ko | grep alias
alias: platform:meson-rng
After this patch:
$ modinfo drivers/char/hw_random/meson-rng.ko | grep alias
alias: platform:meson-rng
alias: of:N*T*Camlogic,meson-rngC*
alias: of:N*T*Camlogic,meson-rng
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v2:
- Remove unrelated changes added by mistake. Suggested by Jason Gunthorpe.
drivers/char/hw_random/meson-rng.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/char/hw_random/meson-rng.c b/drivers/char/hw_random/meson-rng.c
index 58bef39f7286..51864a509be7 100644
--- a/drivers/char/hw_random/meson-rng.c
+++ b/drivers/char/hw_random/meson-rng.c
@@ -110,6 +110,7 @@ static const struct of_device_id meson_rng_of_match[] = {
{ .compatible = "amlogic,meson-rng", },
{},
};
+MODULE_DEVICE_TABLE(of, meson_rng_of_match);
static struct platform_driver meson_rng_driver = {
.probe = meson_rng_probe,
--
2.7.4
^ permalink raw reply related
* [PATCH] hwrng: meson: Fix module autoload for OF registration
From: Javier Martinez Canillas @ 2016-10-17 19:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017194501.GD8122@obsidianresearch.com>
Hello Jason,
On 10/17/2016 04:45 PM, Jason Gunthorpe wrote:
> On Mon, Oct 17, 2016 at 04:40:14PM -0300, Javier Martinez Canillas wrote:
>
>> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
>>
>> drivers/char/hw_random/meson-rng.c | 1 +
>> drivers/char/tpm/Kconfig | 2 +-
>
> Looks like this patch should not have tpm in it.
>
Argh, yes. I had some unrelated changes in my staging area and did a
commit by mistake. Thanks a lot for pointing out and sorry for that.
I'll post a v2 without this.
> Jason
>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH] hwrng: meson: Fix module autoload for OF registration
From: Fabio Estevam @ 2016-10-17 19:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733214-19044-1-git-send-email-javier@osg.samsung.com>
On Mon, Oct 17, 2016 at 5:40 PM, Javier Martinez Canillas
<javier@osg.samsung.com> wrote:
> --- a/drivers/char/tpm/Kconfig
> +++ b/drivers/char/tpm/Kconfig
> @@ -32,7 +32,7 @@ config TCG_TIS_CORE
>
> config TCG_TIS
> tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface"
> - depends on X86
> + depends on X86 || COMPILE_TEST
This is a separate change.
^ permalink raw reply
* [PATCH v3 4/4] net: smsc91x: add u16 workaround for pxa platforms
From: Robert Jarzmik @ 2016-10-17 19:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733532-29716-1-git-send-email-robert.jarzmik@free.fr>
Add a workaround for mainstone, idp and stargate2 boards, for u16 writes
which must be aligned on 32 bits addresses.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Jeremy Linton <jeremy.linton@arm.com>
---
Since v1: rename dt property to pxa-u16-align4
change the binding documentation file
---
Documentation/devicetree/bindings/net/smsc-lan91c111.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
index e77e167593db..309e37eb7c7c 100644
--- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
+++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
@@ -13,3 +13,5 @@ Optional properties:
16-bit access only.
- power-gpios: GPIO to control the PWRDWN pin
- reset-gpios: GPIO to control the RESET pin
+- pxa-u16-align4 : Boolean, put in place the workaround the force all
+ u16 writes to be 32 bits aligned
--
2.1.4
^ permalink raw reply related
* [PATCH v3 3/4] net: smc91x: take into account half-word workaround
From: Robert Jarzmik @ 2016-10-17 19:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733532-29716-1-git-send-email-robert.jarzmik@free.fr>
For device-tree builds, platforms such as mainstone, idp and stargate2
must have their u16 writes all aligned on 32 bit boundaries. This is
already enabled in platform data builds, and this patch adds it to
device-tree builds.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
Since v1: rename dt property to pxa-u16-align4
---
drivers/net/ethernet/smsc/smc91x.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/smsc/smc91x.c b/drivers/net/ethernet/smsc/smc91x.c
index 705d99b2d947..65077c77082a 100644
--- a/drivers/net/ethernet/smsc/smc91x.c
+++ b/drivers/net/ethernet/smsc/smc91x.c
@@ -2326,6 +2326,8 @@ static int smc_drv_probe(struct platform_device *pdev)
if (!device_property_read_u32(&pdev->dev, "reg-shift",
&val))
lp->io_shift = val;
+ lp->cfg.pxa_u16_align4 =
+ device_property_read_bool(&pdev->dev, "pxa-u16-align4");
}
#endif
--
2.1.4
^ permalink raw reply related
* [PATCH v3 2/4] net: smc91x: isolate u16 writes alignment workaround
From: Robert Jarzmik @ 2016-10-17 19:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733532-29716-1-git-send-email-robert.jarzmik@free.fr>
Writes to u16 has a special handling on 3 PXA platforms, where the
hardware wiring forces these writes to be u32 aligned.
This patch isolates this handling for PXA platforms as before, but
enables this "workaround" to be set up dynamically, which will be the
case in device-tree build types.
This patch was tested on 2 PXA platforms : mainstone, which relies on
the workaround, and lubbock, which doesn't.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
--
Since v2: fixed arch/mn10300 case
removed machine_is_*() calls
---
arch/mn10300/unit-asb2303/include/unit/smc91111.h | 2 +-
drivers/net/ethernet/smsc/smc91x.c | 3 +-
drivers/net/ethernet/smsc/smc91x.h | 82 ++++++++++++-----------
3 files changed, 47 insertions(+), 40 deletions(-)
diff --git a/arch/mn10300/unit-asb2303/include/unit/smc91111.h b/arch/mn10300/unit-asb2303/include/unit/smc91111.h
index dd456e9c513f..dd4e2946438e 100644
--- a/arch/mn10300/unit-asb2303/include/unit/smc91111.h
+++ b/arch/mn10300/unit-asb2303/include/unit/smc91111.h
@@ -30,7 +30,7 @@
#if SMC_CAN_USE_16BIT
#define SMC_inw(a, r) inw((unsigned long) ((a) + (r)))
-#define SMC_outw(v, a, r) outw(v, (unsigned long) ((a) + (r)))
+#define SMC_outw(lp, v, a, r) outw(v, (unsigned long) ((a) + (r)))
#define SMC_insw(a, r, p, l) insw((unsigned long) ((a) + (r)), (p), (l))
#define SMC_outsw(a, r, p, l) outsw((unsigned long) ((a) + (r)), (p), (l))
#endif
diff --git a/drivers/net/ethernet/smsc/smc91x.c b/drivers/net/ethernet/smsc/smc91x.c
index 9b4780f87863..705d99b2d947 100644
--- a/drivers/net/ethernet/smsc/smc91x.c
+++ b/drivers/net/ethernet/smsc/smc91x.c
@@ -602,7 +602,8 @@ static void smc_hardware_send_pkt(unsigned long data)
SMC_PUSH_DATA(lp, buf, len & ~1);
/* Send final ctl word with the last byte if there is one */
- SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
+ SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr,
+ DATA_REG(lp));
/*
* If THROTTLE_TX_PKTS is set, we stop the queue here. This will
diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h
index ea8465467469..45e6b81a6a92 100644
--- a/drivers/net/ethernet/smsc/smc91x.h
+++ b/drivers/net/ethernet/smsc/smc91x.h
@@ -63,8 +63,6 @@
#if defined(CONFIG_ARM)
-#include <asm/mach-types.h>
-
/* Now the bus width is specified in the platform data
* pretend here to support all I/O access types
*/
@@ -86,11 +84,11 @@
#define SMC_inl(a, r) readl((a) + (r))
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
-#define SMC_outw(v, a, r) \
+#define SMC_outw(lp, v, a, r) \
do { \
unsigned int __v = v, __smc_r = r; \
if (SMC_16BIT(lp)) \
- __SMC_outw(__v, a, __smc_r); \
+ __SMC_outw(lp, __v, a, __smc_r); \
else if (SMC_8BIT(lp)) \
SMC_outw_b(__v, a, __smc_r); \
else \
@@ -107,10 +105,10 @@
#define SMC_IRQ_FLAGS (-1) /* from resource */
/* We actually can't write halfwords properly if not word aligned */
-static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
+static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg,
+ bool use_align4_workaround)
{
- if ((machine_is_mainstone() || machine_is_stargate2() ||
- machine_is_pxa_idp()) && reg & 2) {
+ if (use_align4_workaround) {
unsigned int v = val << 16;
v |= readl(ioaddr + (reg & ~2)) & 0xffff;
writel(v, ioaddr + (reg & ~2));
@@ -119,6 +117,12 @@ static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
}
}
+#define __SMC_outw(lp, v, a, r) \
+ _SMC_outw_align4((v), (a), (r), \
+ IS_BUILTIN(CONFIG_ARCH_PXA) && ((r) & 2) && \
+ (lp)->cfg.pxa_u16_align4)
+
+
#elif defined(CONFIG_SH_SH4202_MICRODEV)
#define SMC_CAN_USE_8BIT 0
@@ -129,7 +133,7 @@ static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
-#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
+#define SMC_outw(lp, v, a, r) outw(v, (a) + (r) - 0xa0000000)
#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
@@ -147,7 +151,7 @@ static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
#define SMC_inb(a, r) inb(((u32)a) + (r))
#define SMC_inw(a, r) inw(((u32)a) + (r))
#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
-#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
+#define SMC_outw(lp, v, a, r) outw(v, ((u32)a) + (r))
#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
@@ -175,7 +179,7 @@ static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
#define SMC_inw(a, r) readw((a) + (r))
#define SMC_inl(a, r) readl((a) + (r))
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
-#define SMC_outw(v, a, r) writew(v, (a) + (r))
+#define SMC_outw(lp, v, a, r) writew(v, (a) + (r))
#define SMC_outl(v, a, r) writel(v, (a) + (r))
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
@@ -207,7 +211,7 @@ static inline void mcf_outsw(void *a, unsigned char *p, int l)
}
#define SMC_inw(a, r) _swapw(readw((a) + (r)))
-#define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
+#define SMC_outw(lp, v, a, r) writew(_swapw(v), (a) + (r))
#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
@@ -241,7 +245,7 @@ static inline void mcf_outsw(void *a, unsigned char *p, int l)
#define SMC_inw(a, r) ioread16((a) + (r))
#define SMC_inl(a, r) ioread32((a) + (r))
#define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
-#define SMC_outw(v, a, r) iowrite16(v, (a) + (r))
+#define SMC_outw(lp, v, a, r) iowrite16(v, (a) + (r))
#define SMC_outl(v, a, r) iowrite32(v, (a) + (r))
#define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l)
@@ -303,6 +307,8 @@ struct smc_local {
/* the low address lines on some platforms aren't connected... */
int io_shift;
+ /* on some platforms a u16 write must be 4-bytes aligned */
+ bool half_word_align4;
struct smc91x_platdata cfg;
};
@@ -457,7 +463,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
#if ! SMC_CAN_USE_16BIT
-#define SMC_outw(x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg)
+#define SMC_outw(lp, x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg)
#define SMC_inw(ioaddr, reg) SMC_inw_b(ioaddr, reg)
#define SMC_insw(a, r, p, l) BUG()
#define SMC_outsw(a, r, p, l) BUG()
@@ -909,7 +915,7 @@ static const char * chip_ids[ 16 ] = {
else if (SMC_8BIT(lp)) \
SMC_outb(x, ioaddr, PN_REG(lp)); \
else \
- SMC_outw(x, ioaddr, PN_REG(lp)); \
+ SMC_outw(lp, x, ioaddr, PN_REG(lp)); \
} while (0)
#define SMC_GET_AR(lp) \
@@ -937,7 +943,7 @@ static const char * chip_ids[ 16 ] = {
int __mask; \
local_irq_save(__flags); \
__mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
- SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
+ SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
local_irq_restore(__flags); \
} \
} while (0)
@@ -951,7 +957,7 @@ static const char * chip_ids[ 16 ] = {
if (SMC_8BIT(lp)) \
SMC_outb(x, ioaddr, IM_REG(lp)); \
else \
- SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
+ SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp)); \
} while (0)
#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
@@ -961,22 +967,22 @@ static const char * chip_ids[ 16 ] = {
if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
else \
- SMC_outw(x, ioaddr, BANK_SELECT); \
+ SMC_outw(lp, x, ioaddr, BANK_SELECT); \
} while (0)
#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
-#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
+#define SMC_SET_BASE(lp, x) SMC_outw(lp, x, ioaddr, BASE_REG(lp))
#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
-#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
+#define SMC_SET_CONFIG(lp, x) SMC_outw(lp, x, ioaddr, CONFIG_REG(lp))
#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
-#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
+#define SMC_SET_CTL(lp, x) SMC_outw(lp, x, ioaddr, CTL_REG(lp))
#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
@@ -987,20 +993,20 @@ static const char * chip_ids[ 16 ] = {
if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
else \
- SMC_outw(x, ioaddr, GP_REG(lp)); \
+ SMC_outw(lp, x, ioaddr, GP_REG(lp)); \
} while (0)
-#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
+#define SMC_SET_MII(lp, x) SMC_outw(lp, x, ioaddr, MII_REG(lp))
#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
-#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
+#define SMC_SET_MIR(lp, x) SMC_outw(lp, x, ioaddr, MIR_REG(lp))
#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
-#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
+#define SMC_SET_MMU_CMD(lp, x) SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp))
-#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
+#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
@@ -1009,14 +1015,14 @@ static const char * chip_ids[ 16 ] = {
if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
else \
- SMC_outw(x, ioaddr, PTR_REG(lp)); \
+ SMC_outw(lp, x, ioaddr, PTR_REG(lp)); \
} while (0)
#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
-#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
+#define SMC_SET_RCR(lp, x) SMC_outw(lp, x, ioaddr, RCR_REG(lp))
#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
@@ -1027,12 +1033,12 @@ static const char * chip_ids[ 16 ] = {
if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
else \
- SMC_outw(x, ioaddr, RPC_REG(lp)); \
+ SMC_outw(lp, x, ioaddr, RPC_REG(lp)); \
} while (0)
#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
-#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
+#define SMC_SET_TCR(lp, x) SMC_outw(lp, x, ioaddr, TCR_REG(lp))
#ifndef SMC_GET_MAC_ADDR
#define SMC_GET_MAC_ADDR(lp, addr) \
@@ -1049,18 +1055,18 @@ static const char * chip_ids[ 16 ] = {
#define SMC_SET_MAC_ADDR(lp, addr) \
do { \
- SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
- SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
- SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
+ SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
+ SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
+ SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
} while (0)
#define SMC_SET_MCAST(lp, x) \
do { \
const unsigned char *mt = (x); \
- SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
- SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
- SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
- SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
+ SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
+ SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
+ SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
+ SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
} while (0)
#define SMC_PUT_PKT_HDR(lp, status, length) \
@@ -1069,8 +1075,8 @@ static const char * chip_ids[ 16 ] = {
SMC_outl((status) | (length)<<16, ioaddr, \
DATA_REG(lp)); \
else { \
- SMC_outw(status, ioaddr, DATA_REG(lp)); \
- SMC_outw(length, ioaddr, DATA_REG(lp)); \
+ SMC_outw(lp, status, ioaddr, DATA_REG(lp)); \
+ SMC_outw(lp, length, ioaddr, DATA_REG(lp)); \
} \
} while (0)
--
2.1.4
^ permalink raw reply related
* [PATCH v3 1/4] ARM: pxa: enhance smc91x platform data
From: Robert Jarzmik @ 2016-10-17 19:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733532-29716-1-git-send-email-robert.jarzmik@free.fr>
Instead of having the smc91x driver relying on machine_is_*() calls,
provide this data through platform data, ie. idp, mainstone and
stargate.
This way, the driver doesn't need anymore machine_is_*() calls, which
wouldn't work anymore with a device-tree build.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
arch/arm/mach-pxa/idp.c | 1 +
arch/arm/mach-pxa/mainstone.c | 1 +
arch/arm/mach-pxa/stargate2.c | 1 +
include/linux/smc91x.h | 1 +
4 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 66070acaa888..d1db32b1a2c6 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -85,6 +85,7 @@ static struct resource smc91x_resources[] = {
static struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
SMC91X_USE_DMA | SMC91X_NOWAIT,
+ .pxa_u16_align4 = true,
};
static struct platform_device smc91x_device = {
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 40964069a17c..a2d851a3a546 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -140,6 +140,7 @@ static struct resource smc91x_resources[] = {
static struct smc91x_platdata mainstone_smc91x_info = {
.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
SMC91X_NOWAIT | SMC91X_USE_DMA,
+ .pxa_u16_align4 = true,
};
static struct platform_device smc91x_device = {
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 702f4f14b708..7b6610e9dae4 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -673,6 +673,7 @@ static struct resource smc91x_resources[] = {
static struct smc91x_platdata stargate2_smc91x_info = {
.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT
| SMC91X_NOWAIT | SMC91X_USE_DMA,
+ .pxa_u16_align4 = true,
};
static struct platform_device smc91x_device = {
diff --git a/include/linux/smc91x.h b/include/linux/smc91x.h
index e302c447e057..129bc674dcf5 100644
--- a/include/linux/smc91x.h
+++ b/include/linux/smc91x.h
@@ -39,6 +39,7 @@ struct smc91x_platdata {
unsigned long flags;
unsigned char leda;
unsigned char ledb;
+ bool pxa_u16_align4; /* PXA buggy u16 writes on 4*n+2 addresses */
};
#endif /* __SMC91X_H__ */
--
2.1.4
^ permalink raw reply related
* [PATCH v3 0/4] support smc91x on mainstone and devicetree
From: Robert Jarzmik @ 2016-10-17 19:45 UTC (permalink / raw)
To: linux-arm-kernel
This serie aims at bringing support to mainstone board on a device-tree based
build, as what is already in place for legacy mainstone.
The bulk of the mainstone "specific" behavior is that a u16 write doesn't work
on a address of the form 4*n + 2, while it works on 4*n.
The legacy workaround was in SMC_outw(), with calls to
machine_is_mainstone(). These calls don't work with a pxa27x-dt machine type,
which is used when a generic device-tree pxa27x machine is used to boot the
mainstone board.
Therefore, this serie enables the smc91c111 adapter of the mainstone board to
work on a device-tree build, exaclty as it's been working for years with the
legacy arch/arm/mach-pxa/mainstone.c definition.
As a sum up, this extends an existing mechanism to device-tree based pxa platforms.
Cheers.
--
Robert
Robert Jarzmik (4):
ARM: pxa: enhance smc91x platform data
net: smc91x: isolate u16 writes alignment workaround
net: smc91x: take into account half-word workaround
net: smsc91x: add u16 workaround for pxa platforms
.../devicetree/bindings/net/smsc-lan91c111.txt | 2 +
arch/arm/mach-pxa/idp.c | 1 +
arch/arm/mach-pxa/mainstone.c | 1 +
arch/arm/mach-pxa/stargate2.c | 1 +
arch/mn10300/unit-asb2303/include/unit/smc91111.h | 2 +-
drivers/net/ethernet/smsc/smc91x.c | 5 +-
drivers/net/ethernet/smsc/smc91x.h | 82 ++++++++++++----------
include/linux/smc91x.h | 1 +
8 files changed, 55 insertions(+), 40 deletions(-)
--
2.1.4
^ permalink raw reply
* [PATCH] hwrng: meson: Fix module autoload for OF registration
From: Jason Gunthorpe @ 2016-10-17 19:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733214-19044-1-git-send-email-javier@osg.samsung.com>
On Mon, Oct 17, 2016 at 04:40:14PM -0300, Javier Martinez Canillas wrote:
> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
>
> drivers/char/hw_random/meson-rng.c | 1 +
> drivers/char/tpm/Kconfig | 2 +-
Looks like this patch should not have tpm in it.
Jason
^ permalink raw reply
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