* [PATCH 8/8] ARM: gr8: Add CHIP Pro support
From: Maxime Ripard @ 2016-10-20 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.bb1e4a568bc16ada5254cad063f4afbaa1ca5906.1476951078.git-series.maxime.ripard@free-electrons.com>
The CHIP Pro is a small embeddable board. It features a GR8, an AXP209
PMIC, a 512MB SLC NAND and a WiFi/BT chip.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 1 +-
arch/arm/boot/dts/ntc-gr8-chip-pro.dts | 266 ++++++++++++++++++++++++++-
2 files changed, 267 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/ntc-gr8-chip-pro.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..3dab5b593158 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -745,6 +745,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-pcduino2.dtb \
sun4i-a10-pov-protab2-ips9.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
+ ntc-gr8-chip-pro.dtb \
ntc-gr8-evb.dtb \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
diff --git a/arch/arm/boot/dts/ntc-gr8-chip-pro.dts b/arch/arm/boot/dts/ntc-gr8-chip-pro.dts
new file mode 100644
index 000000000000..3c86f214c493
--- /dev/null
+++ b/arch/arm/boot/dts/ntc-gr8-chip-pro.dts
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2016 Free Electrons
+ * Copyright 2016 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "ntc-gr8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "NextThing C.H.I.P. Pro";
+ compatible = "nextthing,chip-pro", "nextthing,gr8";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "chip-pro:white:status";
+ gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ mmc0_pwrseq: mmc0_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_pin_chip_pro>;
+ reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic at 34 {
+ reg = <0x34>;
+
+ /*
+ * The interrupt is routed through the "External Fast
+ * Interrupt Request" pin (ball G13 of the module)
+ * directly to the main interrupt controller, without
+ * any other controller interfering.
+ */
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "disabled";
+};
+
+&i2s0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>;
+ status = "disabled";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc0_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+ status = "okay";
+
+ nand at 0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-mode = "hw";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_pin_chip_pro: usb0-id-pin at 0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ wifi_reg_on_pin_chip_pro: wifi-reg-on-pin at 0 {
+ allwinner,pins = "PB10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>;
+ status = "disabled";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+ regulator-always-on;
+};
+
+®_dcdc3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-sys";
+ regulator-always-on;
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+ regulator-always-on;
+};
+
+/*
+ * Both LDO3 and LDO4 are used in parallel to power up the
+ * WiFi/BT chip.
+ */
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ regulator-always-on;
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ regulator-always-on;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ /*
+ * The CHIP Pro doesn't have a controllable VBUS, nor does it
+ * have any 5v rail on the board itself.
+ *
+ * If one wants to use it as a true OTG port, it should be
+ * done in the baseboard, and its DT / overlay will add it.
+ */
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_pin_chip_pro>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb1_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
--
git-series 0.8.10
^ permalink raw reply related
* [PATCH v3 3/6] pwm: imx: support output polarity inversion
From: Lukasz Majewski @ 2016-10-20 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161013065812.0da91859@jawa>
Hi Stefan,
> Hi Stefan,
>
> > On 2016-10-12 15:15, Lukasz Majewski wrote:
> > > Hi Stefan,
> > >
> > >> On 2016-10-07 08:11, Bhuvanchandra DV wrote:
> > >> > From: Lothar Wassmann <LW@KARO-electronics.de>
> > >> >
> > >> > The i.MX pwm unit on i.MX27 and newer SoCs provides a
> > >> > configurable output polarity. This patch adds support to
> > >> > utilize this feature where available.
> > >> >
> > >> > Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> > >> > Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> > >> > Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> > >> > Acked-by: Shawn Guo <shawn.guo@linaro.org>
> > >> > Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
> > >> > ---
> > >> > Documentation/devicetree/bindings/pwm/imx-pwm.txt | 6 +--
> > >> > drivers/pwm/pwm-imx.c | 51
> > >> > +++++++++++++++++++++-- 2 files changed, 51 insertions(+), 6
> > >> > deletions(-)
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > >> > b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > >> > index e00c2e9..c61bdf8 100644
> > >> > --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > >> > +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > >> > @@ -6,8 +6,8 @@ Required properties:
> > >> > - "fsl,imx1-pwm" for PWM compatible with the one integrated
> > >> > on i.MX1
> > >> > - "fsl,imx27-pwm" for PWM compatible with the one integrated
> > >> > on i.MX27
> > >> > - reg: physical base address and length of the controller's
> > >> > registers -- #pwm-cells: should be 2. See pwm.txt in this
> > >> > directory for a description of
> > >> > - the cells format.
> > >> > +- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See
> > >> > pwm.txt
> > >> > + in this directory for a description of the cells format.
> > >> > - clocks : Clock specifiers for both ipg and per clocks.
> > >> > - clock-names : Clock names should include both "ipg" and
> > >> > "per" See the clock consumer binding,
> > >> > @@ -17,7 +17,7 @@ See the clock consumer binding,
> > >> > Example:
> > >> >
> > >> > pwm1: pwm at 53fb4000 {
> > >> > - #pwm-cells = <2>;
> > >> > + #pwm-cells = <3>;
> > >> > compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
> > >> > reg = <0x53fb4000 0x4000>;
> > >> > clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
> > >> > diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> > >> > index d600fd5..c37d223 100644
> > >> > --- a/drivers/pwm/pwm-imx.c
> > >> > +++ b/drivers/pwm/pwm-imx.c
> > >> > @@ -38,6 +38,7 @@
> > >> > #define MX3_PWMCR_DOZEEN (1 << 24)
> > >> > #define MX3_PWMCR_WAITEN (1 << 23)
> > >> > #define MX3_PWMCR_DBGEN (1 << 22)
> > >> > +#define MX3_PWMCR_POUTC (1 << 18)
> > >> > #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> > >> > #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> > >> > #define MX3_PWMCR_SWR (1 << 3)
> > >> > @@ -180,6 +181,9 @@ static int imx_pwm_config_v2(struct
> > >> > pwm_chip *chip, if (enable)
> > >> > cr |= MX3_PWMCR_EN;
> > >> >
> > >> > + if (pwm->args.polarity == PWM_POLARITY_INVERSED)
> > >> > + cr |= MX3_PWMCR_POUTC;
> > >> > +
> > >>
> > >> This seems wrong to me, the config callback is meant for
> > >> period/duty cycle only.
Unfortunately, it also resets the PWM IP block and setups it again (by
writing to PWMCR register). In that function we setup for example MX3_PWMCR_DOZEEN
and MX3_PWMCR_DBGEN. Why cannot we setup polarity as well?
I've double checked the backlight and pwm code flow.
Please find following snippet:
[ 0.135545] ######### imx_pwm_probe
[ 0.135581] PWM supports output inversion
[ 0.136864] ######### pwm_backlight_probe
[ 0.136913] backlight supply power not found, using dummy regulator
[ 0.136984] ######### imx_pwm_set_polarity 1
[ 0.136995] imx_pwm_set_polarity: polarity set to inverted cr: 0x40000 0xf08f8000
[ 0.137005] #########0 imx_pwm_config_v2 cr: 0x40000
[ 0.137683] #########1 imx_pwm_config_v2 cr: 0x0 0xf08f8000
[ 0.137693] #########2 imx_pwm_config_v2 cr: 0x1c20050
[ 0.137702] #########3 imx_pwm_config_v2 cr: 0x1c20050 0xf08f8000
[ 0.137711] @@@@@@@@@@ pwm_apply_state
Here the pwm_backlight_probe calls set_polarity callback available in
pwm - the polarity is set (the 0x40000 value).
The above operation is performed in pwm_apply_state (@ drivers/pwm/core.c).
In the same function, latter we call the pwm->chip->ops->config(), which is the
pointer to config_v2.
Since the PWM is not yet enabled, this function performs SW reset and
PWM inversion setting is cleared.
Possible solutions:
1. Leave the original patch from Bhuvanchandra as it was (I'm for this
option)
2. Enable early PWM (in core, or in bl driver) so the config_v2 is not
calling SW reset on the PWM. (but this solutions seems _really_ bad to me)
3. Perform defer probe of pwm backlight driver (pwm_bl.c) until the pwm
is fully configured (it might be a bit tricky).
Best regards,
?ukasz Majewski
> > >
> > > If it is meant only for that, then the polarity should be removed
> > > from it.
> > >
> > > However after very quick testing, at least on my setup, it turns
> > > out that removing this lines causes polarity to _not_ being set
> > > (and the polarity is not inverted).
> > >
> > > I will investigate this further on my setup and hopefully sent
> > > proper patch.
> > >
> > >> The set_polarity callback should get called in case a
> > >> different polarity is requested.
> > >
> > > On my setup the pwm2 is set from DT and pwm_backlight_probe()
> > > calls pwm_apply_args(), so everything should work. However, as I
> > > mentioned above there still is some problem with inversion
> > > setting.
> > >
> > >>
> > >>
> > >> > writel(cr, imx->mmio_base + MX3_PWMCR);
> > >> >
> > >> > return 0;
> > >> > @@ -240,27 +244,62 @@ static void imx_pwm_disable(struct
> > >> > pwm_chip *chip, struct pwm_device *pwm)
> > >> > clk_disable_unprepare(imx->clk_per);
> > >> > }
> > >> >
> > >> > -static struct pwm_ops imx_pwm_ops = {
> > >> > +static int imx_pwm_set_polarity(struct pwm_chip *chip, struct
> > >> > pwm_device *pwm,
> > >> > + enum pwm_polarity polarity)
> > >> > +{
> > >> > + struct imx_chip *imx = to_imx_chip(chip);
> > >> > + u32 val;
> > >> > +
> > >> > + if (polarity == pwm->args.polarity)
> > >> > + return 0;
> > >>
> > >> I don't think that this is right. Today, pwm_apply_args (in
> > >> include/linux/pwm.h) copies the polarity from args to
> > >> state.polarity, which is then passed as polarity argument to this
> > >> function. So this will always return 0 afaict.
> > >
> > > Yes, I've overlooked it (that the state is copied).
> > >
> > > It can be dropped.
> >
> > Did you do the above test with that line dropped?
>
> Yes. The above code has been also removed.
>
> Best regards,
> ?ukasz Majewski
>
> >
> > >
> > >>
> > >> I would just drop that.
> > >>
> > >> There is probably one little problem in the current state of
> > >> affairs: If the bootloader makes use of a PWM channel with
> > >> inverted state, then the kernel would not know about that and
> > >> currently assume a wrong initial state... I guess at one point in
> > >> time we should implement the state retrieval callback and move to
> > >> the new atomic PWM API, which would mean to implement apply
> > >> callback.
> > >
> > > Are there any patches on the horizon?
> > >
> >
> > Not that I know of...
> >
> > --
> > Stefan
> >
> > >>
> > >> --
> > >> Stefan
> > >>
> > >>
> > >> > +
> > >> > + val = readl(imx->mmio_base + MX3_PWMCR);
> > >> > +
> > >> > + if (polarity == PWM_POLARITY_INVERSED)
> > >> > + val |= MX3_PWMCR_POUTC;
> > >> > + else
> > >> > + val &= ~MX3_PWMCR_POUTC;
> > >> > +
> > >> > + writel(val, imx->mmio_base + MX3_PWMCR);
> > >> > +
> > >> > + dev_dbg(imx->chip.dev, "%s: polarity set to %s\n",
> > >> > __func__,
> > >> > + polarity == PWM_POLARITY_INVERSED ?
> > >> > "inverted" : "normal"); +
> > >> > + return 0;
> > >> > +}
> > >> > +
> > >> > +static struct pwm_ops imx_pwm_ops_v1 = {
> > >> > .enable = imx_pwm_enable,
> > >> > .disable = imx_pwm_disable,
> > >> > .config = imx_pwm_config,
> > >> > .owner = THIS_MODULE,
> > >> > };
> > >> >
> > >> > +static struct pwm_ops imx_pwm_ops_v2 = {
> > >> > + .enable = imx_pwm_enable,
> > >> > + .disable = imx_pwm_disable,
> > >> > + .set_polarity = imx_pwm_set_polarity,
> > >> > + .config = imx_pwm_config,
> > >> > + .owner = THIS_MODULE,
> > >> > +};
> > >> > +
> > >> > struct imx_pwm_data {
> > >> > int (*config)(struct pwm_chip *chip,
> > >> > struct pwm_device *pwm, int duty_ns, int
> > >> > period_ns); void (*set_enable)(struct pwm_chip *chip, bool
> > >> > enable);
> > >> > + struct pwm_ops *pwm_ops;
> > >> > };
> > >> >
> > >> > static struct imx_pwm_data imx_pwm_data_v1 = {
> > >> > .config = imx_pwm_config_v1,
> > >> > .set_enable = imx_pwm_set_enable_v1,
> > >> > + .pwm_ops = &imx_pwm_ops_v1,
> > >> > };
> > >> >
> > >> > static struct imx_pwm_data imx_pwm_data_v2 = {
> > >> > .config = imx_pwm_config_v2,
> > >> > .set_enable = imx_pwm_set_enable_v2,
> > >> > + .pwm_ops = &imx_pwm_ops_v2,
> > >> > };
> > >> >
> > >> > static const struct of_device_id imx_pwm_dt_ids[] = {
> > >> > @@ -282,6 +321,8 @@ static int imx_pwm_probe(struct
> > >> > platform_device *pdev) if (!of_id)
> > >> > return -ENODEV;
> > >> >
> > >> > + data = of_id->data;
> > >> > +
> > >> > imx = devm_kzalloc(&pdev->dev, sizeof(*imx),
> > >> > GFP_KERNEL); if (imx == NULL)
> > >> > return -ENOMEM;
> > >> > @@ -300,18 +341,22 @@ static int imx_pwm_probe(struct
> > >> > platform_device *pdev) return PTR_ERR(imx->clk_ipg);
> > >> > }
> > >> >
> > >> > - imx->chip.ops = &imx_pwm_ops;
> > >> > + imx->chip.ops = data->pwm_ops;
> > >> > imx->chip.dev = &pdev->dev;
> > >> > imx->chip.base = -1;
> > >> > imx->chip.npwm = 1;
> > >> > imx->chip.can_sleep = true;
> > >> > + if (data->pwm_ops->set_polarity) {
> > >> > + dev_dbg(&pdev->dev, "PWM supports output
> > >> > inversion\n");
> > >> > + imx->chip.of_xlate = of_pwm_xlate_with_flags;
> > >> > + imx->chip.of_pwm_n_cells = 3;
> > >> > + }
> > >> >
> > >> > r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > >> > imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
> > >> > if (IS_ERR(imx->mmio_base))
> > >> > return PTR_ERR(imx->mmio_base);
> > >> >
> > >> > - data = of_id->data;
> > >> > imx->config = data->config;
> > >> > imx->set_enable = data->set_enable;
> > >>
> > >
> > > Best regards,
> > >
> > > ?ukasz Majewski
>
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^ permalink raw reply
* [PATCH v2] mtd: nand: Add OX820 NAND Support
From: Neil Armstrong @ 2016-10-20 8:49 UTC (permalink / raw)
To: linux-arm-kernel
Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller.
This is a simple memory mapped NAND controller with single chip select and
software ECC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../devicetree/bindings/mtd/oxnas-nand.txt | 41 +++++
drivers/mtd/nand/Kconfig | 5 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/oxnas_nand.c | 196 +++++++++++++++++++++
4 files changed, 243 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/oxnas-nand.txt
create mode 100644 drivers/mtd/nand/oxnas_nand.c
Changes since v1 http://lkml.kernel.org/r/20161019145523.6763-1-narmstrong at baylibre.com :
- Simplify cmd_ctrl command and drop the ctrl address offset
- Change oxnas_nand struct name to oxnas_nand_ctrl
- Update DT-Bindings example to reflect the ctrl->chip->partitions hierarchy
Changes since RFC http://lkml.kernel.org/r/20161018090927.1990-1-narmstrong at baylibre.com :
- Avoid using chip->IO_ADDR*
- Use new DT structure
- Assign a chip for the subnode
- Use the nand_hw_control structure
- Cleanup probe
- Cleanup cmd_ctrl by using a context ctrl offset used in write_bytes
diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
new file mode 100644
index 0000000..33a77b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
@@ -0,0 +1,41 @@
+* Oxford Semiconductor OXNAS NAND Controller
+
+Please refer to nand.txt for generic information regarding MTD NAND bindings.
+
+Required properties:
+ - compatible: "oxsemi,ox820-nand"
+ - reg: Base address and length for NAND mapped memory.
+
+Optional Properties:
+ - clocks: phandle to the NAND gate clock if needed.
+ - resets: phandle to the NAND reset control if needed.
+
+Example:
+
+nand: nand-controller at 41000000 {
+ compatible = "oxsemi,ox820-nand";
+ reg = <0x41000000 0x100000>;
+ clocks = <&stdclk CLK_820_NAND>;
+ resets = <&reset RESET_NAND>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "hamming";
+
+ partition at 0 {
+ label = "boot";
+ reg = <0x00000000 0x00e00000>;
+ read-only;
+ };
+
+ partition at e00000 {
+ label = "ubi";
+ reg = <0x00e00000 0x07200000>;
+ };
+ };
+};
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7b7a887..c023125 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -426,6 +426,11 @@ config MTD_NAND_ORION
No board specific support is done by this driver, each board
must advertise a platform_device for the driver to attach.
+config MTD_NAND_OXNAS
+ tristate "NAND Flash support for Oxford Semiconductor SoC"
+ help
+ This enables the NAND flash controller on Oxford Semiconductor SoCs.
+
config MTD_NAND_FSL_ELBC
tristate "NAND support for Freescale eLBC controllers"
depends on FSL_SOC
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index cafde6f..05fc054 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
+obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o
obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
diff --git a/drivers/mtd/nand/oxnas_nand.c b/drivers/mtd/nand/oxnas_nand.c
new file mode 100644
index 0000000..35c94af
--- /dev/null
+++ b/drivers/mtd/nand/oxnas_nand.c
@@ -0,0 +1,196 @@
+/*
+ * Oxford Semiconductor OXNAS NAND driver
+
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ * Heavily based on plat_nand.c :
+ * Author: Vitaly Wool <vitalywool@gmail.com>
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+
+/* Nand commands */
+#define OXNAS_NAND_CMD_ALE BIT(18)
+#define OXNAS_NAND_CMD_CLE BIT(19)
+
+#define OXNAS_NAND_MAX_CHIPS 1
+
+struct oxnas_nand_ctrl {
+ struct nand_hw_control base;
+ void __iomem *io_base;
+ struct clk *clk;
+ struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
+};
+
+static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
+
+ return readb(oxnas->io_base);
+}
+
+static void oxnas_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
+
+ ioread8_rep(oxnas->io_base, buf, len);
+}
+
+static void oxnas_nand_write_buf(struct mtd_info *mtd,
+ const uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
+
+ iowrite8_rep(oxnas->io_base, buf, len);
+}
+
+/* Single CS command control */
+static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
+
+ if (ctrl & NAND_CLE)
+ writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
+ else if (ctrl & NAND_ALE)
+ writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
+}
+
+/*
+ * Probe for the NAND device.
+ */
+static int oxnas_nand_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *nand_np;
+ struct oxnas_nand_ctrl *oxnas;
+ struct nand_chip *chip;
+ struct mtd_info *mtd;
+ struct resource *res;
+ int nchips = 0;
+ int count = 0;
+ int err = 0;
+
+ /* Allocate memory for the device structure (and zero it) */
+ oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
+ GFP_KERNEL);
+ if (!oxnas)
+ return -ENOMEM;
+
+ nand_hw_control_init(&oxnas->base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(oxnas->io_base))
+ return PTR_ERR(oxnas->io_base);
+
+ oxnas->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(oxnas->clk))
+ oxnas->clk = NULL;
+
+ /* Only a single chip node is supported */
+ count = of_get_child_count(np);
+ if (count > 1)
+ return -EINVAL;
+
+ clk_prepare_enable(oxnas->clk);
+ device_reset_optional(&pdev->dev);
+
+ for_each_child_of_node(np, nand_np) {
+ chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
+ GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->controller = &oxnas->base;
+
+ nand_set_flash_node(chip, nand_np);
+ nand_set_controller_data(chip, oxnas);
+
+ mtd = nand_to_mtd(chip);
+ mtd->dev.parent = &pdev->dev;
+ mtd->priv = chip;
+
+ chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
+ chip->read_buf = oxnas_nand_read_buf;
+ chip->read_byte = oxnas_nand_read_byte;
+ chip->write_buf = oxnas_nand_write_buf;
+ chip->chip_delay = 30;
+
+ /* Scan to find existence of the device */
+ err = nand_scan(mtd, 1);
+ if (err)
+ return err;
+
+ err = mtd_device_register(mtd, NULL, 0);
+ if (err) {
+ nand_release(mtd);
+ return err;
+ }
+
+ oxnas->chips[nchips] = chip;
+ ++nchips;
+ }
+
+ /* Exit if no chips found */
+ if (!nchips)
+ return -ENODEV;
+
+ platform_set_drvdata(pdev, oxnas);
+
+ return 0;
+}
+
+static int oxnas_nand_remove(struct platform_device *pdev)
+{
+ struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
+
+ if (oxnas->chips[0])
+ nand_release(nand_to_mtd(oxnas->chips[0]));
+
+ clk_disable_unprepare(oxnas->clk);
+
+ return 0;
+}
+
+static const struct of_device_id oxnas_nand_match[] = {
+ { .compatible = "oxsemi,ox820-nand" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, oxnas_nand_match);
+
+static struct platform_driver oxnas_nand_driver = {
+ .probe = oxnas_nand_probe,
+ .remove = oxnas_nand_remove,
+ .driver = {
+ .name = "oxnas_nand",
+ .of_match_table = oxnas_nand_match,
+ },
+};
+
+module_platform_driver(oxnas_nand_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_DESCRIPTION("Oxnas NAND driver");
+MODULE_ALIAS("platform:oxnas_nand");
--
2.7.0
^ permalink raw reply related
* [PATCH v9 0/4] Mediatek MT2701 SCPSYS power domain support
From: James Liao @ 2016-10-20 8:56 UTC (permalink / raw)
To: linux-arm-kernel
This series is based on v4.9-rc1 and adds scpsys power domain support
for Mediatek MT2701.
To share the code between MT2701 and MT8173, this patchset also refined
original mtk-scpsys.c to separate common codes and platform codes, so
that mtk-scpsys.c can support new SoCs more easily.
MT8173 and MT2701 scpsys init level are now subsys_init. Please refer to [1]
to see discussion details.
changes since v8:
- Rebase to v4.9-rc1.
- Refine implementation in init_clks() and init_scp().
changes since v7:
- Add clk_id for each scp_domain_data define.
- Minor coding style changes.
changes since v6:
- Minor changes in the dt-binding document.
changes since v5:
- Rebase to v4.6-rc1.
- Add dependent clocks for MFG, ISP, ETH and HIF power domains.
- Add "ethif" as a dependent clock in scpsys dt-binding document.
changes since v4:
- Rebase to v4.5-rc4.
- Remove mtk-scpsys.h and Merge its code into mtk-scpsys.c.
- Add names for every controlling registers and bits.
- Include dt-bindings headers at the beginning of mtk-scpsys.c.
- Sort compatible string in dt-binding documents.
changes since v3:
- Implement MT8173 and MT2701 scpsys drivers in a signle file.
- Remove naming of registers that can't be shared among SoCs.
changes since v2:
- Rebase to mbgg/linux-mediatek v4.4-next/soc [1].
- Remove MTK_SCPSYS_MT8173 and MTK_SCPSYS_MT2701.
- Modify scpsys dt-binding document to support MT2701.
changes since v1:
- Make MTK_SCPSYS in Kconfig invisible from users.
- Add comments for changing scpsys init level to subsys_init.
[1] http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003416.html
James Liao (2):
soc: mediatek: Refine scpsys to support multiple platform
soc: mediatek: Init MT8173 scpsys driver earlier
Shunli Wang (2):
soc: mediatek: Add MT2701 power dt-bindings
soc: mediatek: Add MT2701 scpsys driver
.../devicetree/bindings/soc/mediatek/scpsys.txt | 13 +-
drivers/soc/mediatek/Kconfig | 2 +-
drivers/soc/mediatek/mtk-scpsys.c | 484 +++++++++++++++------
include/dt-bindings/power/mt2701-power.h | 27 ++
4 files changed, 380 insertions(+), 146 deletions(-)
create mode 100644 include/dt-bindings/power/mt2701-power.h
--
1.9.1
^ permalink raw reply
* [PATCH v9 1/4] soc: mediatek: Refine scpsys to support multiple platform
From: James Liao @ 2016-10-20 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476953798-23263-1-git-send-email-jamesjj.liao@mediatek.com>
Refine scpsys driver common code to support multiple SoC / platform.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 348 +++++++++++++++++++++++---------------
1 file changed, 210 insertions(+), 138 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 837effe..fa9ee69 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,17 +11,15 @@
* GNU General Public License for more details.
*/
#include <linux/clk.h>
-#include <linux/delay.h>
+#include <linux/init.h>
#include <linux/io.h>
-#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
-#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
-#include <linux/regmap.h>
-#include <linux/soc/mediatek/infracfg.h>
#include <linux/regulator/consumer.h>
+#include <linux/soc/mediatek/infracfg.h>
+
#include <dt-bindings/power/mt8173-power.h>
#define SPM_VDE_PWR_CON 0x0210
@@ -34,6 +32,7 @@
#define SPM_MFG_2D_PWR_CON 0x02c0
#define SPM_MFG_ASYNC_PWR_CON 0x02c4
#define SPM_USB_PWR_CON 0x02cc
+
#define SPM_PWR_STATUS 0x060c
#define SPM_PWR_STATUS_2ND 0x0610
@@ -55,12 +54,21 @@
#define PWR_STATUS_USB BIT(25)
enum clk_id {
- MT8173_CLK_NONE,
- MT8173_CLK_MM,
- MT8173_CLK_MFG,
- MT8173_CLK_VENC,
- MT8173_CLK_VENC_LT,
- MT8173_CLK_MAX,
+ CLK_NONE,
+ CLK_MM,
+ CLK_MFG,
+ CLK_VENC,
+ CLK_VENC_LT,
+ CLK_MAX,
+};
+
+static const char * const clk_names[] = {
+ NULL,
+ "mm",
+ "mfg",
+ "venc",
+ "venc_lt",
+ NULL,
};
#define MAX_CLKS 2
@@ -76,98 +84,6 @@ struct scp_domain_data {
bool active_wakeup;
};
-static const struct scp_domain_data scp_domain_data[] = {
- [MT8173_POWER_DOMAIN_VDEC] = {
- .name = "vdec",
- .sta_mask = PWR_STATUS_VDEC,
- .ctl_offs = SPM_VDE_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {MT8173_CLK_MM},
- },
- [MT8173_POWER_DOMAIN_VENC] = {
- .name = "venc",
- .sta_mask = PWR_STATUS_VENC,
- .ctl_offs = SPM_VEN_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
- },
- [MT8173_POWER_DOMAIN_ISP] = {
- .name = "isp",
- .sta_mask = PWR_STATUS_ISP,
- .ctl_offs = SPM_ISP_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {MT8173_CLK_MM},
- },
- [MT8173_POWER_DOMAIN_MM] = {
- .name = "mm",
- .sta_mask = PWR_STATUS_DISP,
- .ctl_offs = SPM_DIS_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {MT8173_CLK_MM},
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1,
- },
- [MT8173_POWER_DOMAIN_VENC_LT] = {
- .name = "venc_lt",
- .sta_mask = PWR_STATUS_VENC_LT,
- .ctl_offs = SPM_VEN2_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
- },
- [MT8173_POWER_DOMAIN_AUDIO] = {
- .name = "audio",
- .sta_mask = PWR_STATUS_AUDIO,
- .ctl_offs = SPM_AUDIO_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {MT8173_CLK_NONE},
- },
- [MT8173_POWER_DOMAIN_USB] = {
- .name = "usb",
- .sta_mask = PWR_STATUS_USB,
- .ctl_offs = SPM_USB_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {MT8173_CLK_NONE},
- .active_wakeup = true,
- },
- [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
- .name = "mfg_async",
- .sta_mask = PWR_STATUS_MFG_ASYNC,
- .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = 0,
- .clk_id = {MT8173_CLK_MFG},
- },
- [MT8173_POWER_DOMAIN_MFG_2D] = {
- .name = "mfg_2d",
- .sta_mask = PWR_STATUS_MFG_2D,
- .ctl_offs = SPM_MFG_2D_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {MT8173_CLK_NONE},
- },
- [MT8173_POWER_DOMAIN_MFG] = {
- .name = "mfg",
- .sta_mask = PWR_STATUS_MFG,
- .ctl_offs = SPM_MFG_PWR_CON,
- .sram_pdn_bits = GENMASK(13, 8),
- .sram_pdn_ack_bits = GENMASK(21, 16),
- .clk_id = {MT8173_CLK_NONE},
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
- },
-};
-
-#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
-
struct scp;
struct scp_domain {
@@ -179,7 +95,7 @@ struct scp_domain {
};
struct scp {
- struct scp_domain domains[NUM_DOMAINS];
+ struct scp_domain *domains;
struct genpd_onecell_data pd_data;
struct device *dev;
void __iomem *base;
@@ -408,57 +324,55 @@ static bool scpsys_active_wakeup(struct device *dev)
return scpd->data->active_wakeup;
}
-static int scpsys_probe(struct platform_device *pdev)
+static void init_clks(struct platform_device *pdev, struct clk *clk[CLK_MAX])
+{
+ int i;
+
+ for (i = CLK_NONE + 1; i < CLK_MAX; i++)
+ clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
+}
+
+static struct scp *init_scp(struct platform_device *pdev,
+ const struct scp_domain_data *scp_domain_data, int num)
{
struct genpd_onecell_data *pd_data;
struct resource *res;
- int i, j, ret;
+ int i, j;
struct scp *scp;
- struct clk *clk[MT8173_CLK_MAX];
+ struct clk *clk[CLK_MAX];
scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
if (!scp)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
scp->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
scp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(scp->base))
- return PTR_ERR(scp->base);
+ return ERR_CAST(scp->base);
+
+ scp->domains = devm_kzalloc(&pdev->dev,
+ sizeof(*scp->domains) * num, GFP_KERNEL);
+ if (!scp->domains)
+ return ERR_PTR(-ENOMEM);
pd_data = &scp->pd_data;
pd_data->domains = devm_kzalloc(&pdev->dev,
- sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
+ sizeof(*pd_data->domains) * num, GFP_KERNEL);
if (!pd_data->domains)
- return -ENOMEM;
-
- clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
- if (IS_ERR(clk[MT8173_CLK_MM]))
- return PTR_ERR(clk[MT8173_CLK_MM]);
-
- clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
- if (IS_ERR(clk[MT8173_CLK_MFG]))
- return PTR_ERR(clk[MT8173_CLK_MFG]);
-
- clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
- if (IS_ERR(clk[MT8173_CLK_VENC]))
- return PTR_ERR(clk[MT8173_CLK_VENC]);
-
- clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
- if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
- return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
+ return ERR_PTR(-ENOMEM);
scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"infracfg");
if (IS_ERR(scp->infracfg)) {
dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
PTR_ERR(scp->infracfg));
- return PTR_ERR(scp->infracfg);
+ return ERR_CAST(scp->infracfg);
}
- for (i = 0; i < NUM_DOMAINS; i++) {
+ for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
const struct scp_domain_data *data = &scp_domain_data[i];
@@ -467,13 +381,15 @@ static int scpsys_probe(struct platform_device *pdev)
if (PTR_ERR(scpd->supply) == -ENODEV)
scpd->supply = NULL;
else
- return PTR_ERR(scpd->supply);
+ return ERR_CAST(scpd->supply);
}
}
- pd_data->num_domains = NUM_DOMAINS;
+ pd_data->num_domains = num;
- for (i = 0; i < NUM_DOMAINS; i++) {
+ init_clks(pdev, clk);
+
+ for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
const struct scp_domain_data *data = &scp_domain_data[i];
@@ -482,13 +398,37 @@ static int scpsys_probe(struct platform_device *pdev)
scpd->scp = scp;
scpd->data = data;
- for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
- scpd->clk[j] = clk[data->clk_id[j]];
+
+ for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
+ struct clk *c = clk[data->clk_id[j]];
+
+ if (IS_ERR(c)) {
+ dev_err(&pdev->dev, "%s: clk unavailable\n",
+ data->name);
+ return ERR_CAST(c);
+ }
+
+ scpd->clk[j] = c;
+ }
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
+ }
+
+ return scp;
+}
+
+static void mtk_register_power_domains(struct platform_device *pdev,
+ struct scp *scp, int num)
+{
+ struct genpd_onecell_data *pd_data;
+ int i, ret;
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *genpd = &scpd->genpd;
/*
* Initially turn on all domains to make the domains usable
@@ -507,6 +447,123 @@ static int scpsys_probe(struct platform_device *pdev)
* valid.
*/
+ pd_data = &scp->pd_data;
+
+ ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
+}
+
+/*
+ * MT8173 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8173[] = {
+ [MT8173_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT8173_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = SPM_VEN_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_MM, CLK_VENC},
+ },
+ [MT8173_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT8173_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1,
+ },
+ [MT8173_POWER_DOMAIN_VENC_LT] = {
+ .name = "venc_lt",
+ .sta_mask = PWR_STATUS_VENC_LT,
+ .ctl_offs = SPM_VEN2_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_MM, CLK_VENC_LT},
+ },
+ [MT8173_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = SPM_AUDIO_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8173_POWER_DOMAIN_USB] = {
+ .name = "usb",
+ .sta_mask = PWR_STATUS_USB,
+ .ctl_offs = SPM_USB_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_MFG},
+ },
+ [MT8173_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = SPM_MFG_2D_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8173_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(13, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 16),
+ .clk_id = {CLK_NONE},
+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
+ },
+};
+
+#define NUM_DOMAINS_MT8173 ARRAY_SIZE(scp_domain_data_mt8173)
+
+static int __init scpsys_probe_mt8173(struct platform_device *pdev)
+{
+ struct scp *scp;
+ struct genpd_onecell_data *pd_data;
+ int ret;
+
+ scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173);
+ if (IS_ERR(scp))
+ return PTR_ERR(scp);
+
+ mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT8173);
+
+ pd_data = &scp->pd_data;
+
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
if (ret && IS_ENABLED(CONFIG_PM))
@@ -517,21 +574,36 @@ static int scpsys_probe(struct platform_device *pdev)
if (ret && IS_ENABLED(CONFIG_PM))
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
- ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
- if (ret)
- dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
-
return 0;
}
+/*
+ * scpsys driver init
+ */
+
static const struct of_device_id of_scpsys_match_tbl[] = {
{
.compatible = "mediatek,mt8173-scpsys",
+ .data = scpsys_probe_mt8173,
}, {
/* sentinel */
}
};
+static int scpsys_probe(struct platform_device *pdev)
+{
+ int (*probe)(struct platform_device *);
+ const struct of_device_id *of_id;
+
+ of_id = of_match_node(of_scpsys_match_tbl, pdev->dev.of_node);
+ if (!of_id || !of_id->data)
+ return -EINVAL;
+
+ probe = of_id->data;
+
+ return probe(pdev);
+}
+
static struct platform_driver scpsys_drv = {
.probe = scpsys_probe,
.driver = {
--
1.9.1
^ permalink raw reply related
* [PATCH v9 2/4] soc: mediatek: Init MT8173 scpsys driver earlier
From: James Liao @ 2016-10-20 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476953798-23263-1-git-send-email-jamesjj.liao@mediatek.com>
Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized
earlier too.
Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
between IOMMU and multimedia HW. SMI is responsible to
enable/disable iommu and help transfer data for each multimedia
HW. Both of them have to wait until the power and clocks are
enabled.
So scpsys driver should be initialized before SMI, and SMI should
be initialized before IOMMU, and then init IOMMU consumers
(display/vdec/venc/camera etc.).
IOMMU is subsys_init by default. So we need to init scpsys driver
before subsys_init.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index fa9ee69..dd7a07d 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -613,4 +613,21 @@ static int scpsys_probe(struct platform_device *pdev)
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
},
};
-builtin_platform_driver(scpsys_drv);
+
+static int __init scpsys_drv_init(void)
+{
+ return platform_driver_register(&scpsys_drv);
+}
+
+/*
+ * There are some Mediatek drivers which depend on the power domain driver need
+ * to probe in earlier initcall levels. So scpsys driver also need to probe
+ * earlier.
+ *
+ * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU and
+ * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
+ * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
+ * IOMMU drivers are initialized during subsys_init by default, so we need to
+ * move SMI and scpsys drivers to subsys_init or earlier init levels.
+ */
+subsys_initcall(scpsys_drv_init);
--
1.9.1
^ permalink raw reply related
* [PATCH v9 3/4] soc: mediatek: Add MT2701 power dt-bindings
From: James Liao @ 2016-10-20 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476953798-23263-1-git-send-email-jamesjj.liao@mediatek.com>
From: Shunli Wang <shunli.wang@mediatek.com>
Add power dt-bindings for MT2701.
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 13 +++++++----
include/dt-bindings/power/mt2701-power.h | 27 ++++++++++++++++++++++
2 files changed, 35 insertions(+), 5 deletions(-)
create mode 100644 include/dt-bindings/power/mt2701-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index e8f15e3..16fe94d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -9,17 +9,20 @@ domain control.
The driver implements the Generic PM domain bindings described in
power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h.
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
Required properties:
-- compatible: Must be "mediatek,mt8173-scpsys"
+- compatible: Should be one of:
+ - "mediatek,mt2701-scpsys"
+ - "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
- The clocks needed "mm", "mfg", "venc" and "venc_lt".
- These are the clocks which hardware needs to be enabled
- before enabling certain power domains.
+ These are clocks which hardware needs to be
+ enabled before enabling certain power domains.
+ Required clocks for MT2701: "mm", "mfg", "ethif"
+ Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
- vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt2701-power.h b/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 0000000..64cc826
--- /dev/null
+++ b/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN 0
+#define MT2701_POWER_DOMAIN_DISP 1
+#define MT2701_POWER_DOMAIN_MFG 2
+#define MT2701_POWER_DOMAIN_VDEC 3
+#define MT2701_POWER_DOMAIN_ISP 4
+#define MT2701_POWER_DOMAIN_BDP 5
+#define MT2701_POWER_DOMAIN_ETH 6
+#define MT2701_POWER_DOMAIN_HIF 7
+#define MT2701_POWER_DOMAIN_IFR_MSC 8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
--
1.9.1
^ permalink raw reply related
* [PATCH v9 4/4] soc: mediatek: Add MT2701 scpsys driver
From: James Liao @ 2016-10-20 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476953798-23263-1-git-send-email-jamesjj.liao@mediatek.com>
From: Shunli Wang <shunli.wang@mediatek.com>
Add scpsys driver for MT2701.
mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
be enabled on both arm64 and arm platforms.
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
---
drivers/soc/mediatek/Kconfig | 2 +-
drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++++++++++++++++++-
2 files changed, 117 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..609bb34 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
- default ARM64 && ARCH_MEDIATEK
+ default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index dd7a07d..4a1c636 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
#include <linux/regulator/consumer.h>
#include <linux/soc/mediatek/infracfg.h>
+#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt8173-power.h>
#define SPM_VDE_PWR_CON 0x0210
@@ -27,8 +28,13 @@
#define SPM_VEN_PWR_CON 0x0230
#define SPM_ISP_PWR_CON 0x0238
#define SPM_DIS_PWR_CON 0x023c
+#define SPM_CONN_PWR_CON 0x0280
#define SPM_VEN2_PWR_CON 0x0298
-#define SPM_AUDIO_PWR_CON 0x029c
+#define SPM_AUDIO_PWR_CON 0x029c /* MT8173 */
+#define SPM_BDP_PWR_CON 0x029c /* MT2701 */
+#define SPM_ETH_PWR_CON 0x02a0
+#define SPM_HIF_PWR_CON 0x02a4
+#define SPM_IFR_MSC_PWR_CON 0x02a8
#define SPM_MFG_2D_PWR_CON 0x02c0
#define SPM_MFG_ASYNC_PWR_CON 0x02c4
#define SPM_USB_PWR_CON 0x02cc
@@ -42,10 +48,15 @@
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
#define PWR_STATUS_MFG BIT(4)
#define PWR_STATUS_ISP BIT(5)
#define PWR_STATUS_VDEC BIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
#define PWR_STATUS_VENC_LT BIT(20)
#define PWR_STATUS_VENC BIT(21)
#define PWR_STATUS_MFG_2D BIT(22)
@@ -59,6 +70,7 @@ enum clk_id {
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
+ CLK_ETHIF,
CLK_MAX,
};
@@ -68,6 +80,7 @@ enum clk_id {
"mfg",
"venc",
"venc_lt",
+ "ethif",
NULL,
};
@@ -455,6 +468,105 @@ static void mtk_register_power_domains(struct platform_device *pdev,
}
/*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+ [MT2701_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .bus_prot_mask = 0x0104,
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .clk_id = {CLK_MM},
+ .bus_prot_mask = 0x0002,
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MFG},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_MM},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_BDP] = {
+ .name = "bdp",
+ .sta_mask = PWR_STATUS_BDP,
+ .ctl_offs = SPM_BDP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_ETH] = {
+ .name = "eth",
+ .sta_mask = PWR_STATUS_ETH,
+ .ctl_offs = SPM_ETH_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_ETHIF},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_HIF] = {
+ .name = "hif",
+ .sta_mask = PWR_STATUS_HIF,
+ .ctl_offs = SPM_HIF_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_ETHIF},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_IFR_MSC] = {
+ .name = "ifr_msc",
+ .sta_mask = PWR_STATUS_IFR_MSC,
+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+};
+
+#define NUM_DOMAINS_MT2701 ARRAY_SIZE(scp_domain_data_mt2701)
+
+static int __init scpsys_probe_mt2701(struct platform_device *pdev)
+{
+ struct scp *scp;
+
+ scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
+ if (IS_ERR(scp))
+ return PTR_ERR(scp);
+
+ mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);
+
+ return 0;
+}
+
+/*
* MT8173 power domain support
*/
@@ -583,6 +695,9 @@ static int __init scpsys_probe_mt8173(struct platform_device *pdev)
static const struct of_device_id of_scpsys_match_tbl[] = {
{
+ .compatible = "mediatek,mt2701-scpsys",
+ .data = scpsys_probe_mt2701,
+ }, {
.compatible = "mediatek,mt8173-scpsys",
.data = scpsys_probe_mt8173,
}, {
--
1.9.1
^ permalink raw reply related
* [PATCH v2] ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions
From: Simon Horman @ 2016-10-20 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476712744-32619-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
On Mon, Oct 17, 2016 at 04:59:04PM +0300, Laurent Pinchart wrote:
> The four SoCs use identical machine operations, consolidate them into
> two machine definitions in a single file.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Tested-by: Simon Horman <horms+renesas@verge.net.au>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Changes since v1:
>
> - Rebased on top of Simon's latest devel branch, thus including R8A7743
> consolidation
>
> arch/arm/mach-shmobile/Makefile | 4 ----
> arch/arm/mach-shmobile/setup-r8a7743.c | 34 -------------------------------
> arch/arm/mach-shmobile/setup-r8a7792.c | 35 --------------------------------
> arch/arm/mach-shmobile/setup-r8a7793.c | 33 ------------------------------
> arch/arm/mach-shmobile/setup-r8a7794.c | 33 ------------------------------
> arch/arm/mach-shmobile/setup-rcar-gen2.c | 33 ++++++++++++++++++++++++++++++
> 6 files changed, 33 insertions(+), 139 deletions(-)
> delete mode 100644 arch/arm/mach-shmobile/setup-r8a7743.c
> delete mode 100644 arch/arm/mach-shmobile/setup-r8a7792.c
> delete mode 100644 arch/arm/mach-shmobile/setup-r8a7793.c
> delete mode 100644 arch/arm/mach-shmobile/setup-r8a7794.c
Thanks for this Laurent, its a very nice diffstat.
I have queued it up for v4.10.
^ permalink raw reply
* [PATCH v2] mtd: nand: Add OX820 NAND Support
From: Boris Brezillon @ 2016-10-20 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020084901.6486-1-narmstrong@baylibre.com>
On Thu, 20 Oct 2016 10:49:01 +0200
Neil Armstrong <narmstrong@baylibre.com> wrote:
> Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller.
> This is a simple memory mapped NAND controller with single chip select and
> software ECC.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../devicetree/bindings/mtd/oxnas-nand.txt | 41 +++++
> drivers/mtd/nand/Kconfig | 5 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/oxnas_nand.c | 196 +++++++++++++++++++++
> 4 files changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> create mode 100644 drivers/mtd/nand/oxnas_nand.c
>
> Changes since v1 http://lkml.kernel.org/r/20161019145523.6763-1-narmstrong at baylibre.com :
> - Simplify cmd_ctrl command and drop the ctrl address offset
> - Change oxnas_nand struct name to oxnas_nand_ctrl
> - Update DT-Bindings example to reflect the ctrl->chip->partitions hierarchy
>
> Changes since RFC http://lkml.kernel.org/r/20161018090927.1990-1-narmstrong at baylibre.com :
> - Avoid using chip->IO_ADDR*
> - Use new DT structure
> - Assign a chip for the subnode
> - Use the nand_hw_control structure
> - Cleanup probe
> - Cleanup cmd_ctrl by using a context ctrl offset used in write_bytes
>
> diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> new file mode 100644
> index 0000000..33a77b8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> @@ -0,0 +1,41 @@
> +* Oxford Semiconductor OXNAS NAND Controller
> +
> +Please refer to nand.txt for generic information regarding MTD NAND bindings.
> +
> +Required properties:
> + - compatible: "oxsemi,ox820-nand"
> + - reg: Base address and length for NAND mapped memory.
> +
> +Optional Properties:
> + - clocks: phandle to the NAND gate clock if needed.
> + - resets: phandle to the NAND reset control if needed.
> +
> +Example:
> +
> +nand: nand-controller at 41000000 {
'nandc:' or 'nand_ctrl:'
Otherwise it may conflict with a NAND chip alias.
The rest looks good, so no need to send a new version (I can fix it when
applying the patch).
One last thing, I saw there was other people owning boards with this
controller. Can I get one or two Tested-by?
Thanks taking my reviews into account.
Regards,
Boris
^ permalink raw reply
* [PATCH v2] mtd: nand: Add OX820 NAND Support
From: Neil Armstrong @ 2016-10-20 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020110025.11b06090@bbrezillon>
On 10/20/2016 11:00 AM, Boris Brezillon wrote:
> On Thu, 20 Oct 2016 10:49:01 +0200
> Neil Armstrong <narmstrong@baylibre.com> wrote:
>
>> Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller.
>> This is a simple memory mapped NAND controller with single chip select and
>> software ECC.
>>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> .../devicetree/bindings/mtd/oxnas-nand.txt | 41 +++++
>> drivers/mtd/nand/Kconfig | 5 +
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/oxnas_nand.c | 196 +++++++++++++++++++++
>> 4 files changed, 243 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mtd/oxnas-nand.txt
>> create mode 100644 drivers/mtd/nand/oxnas_nand.c
>>
>> Changes since v1 http://lkml.kernel.org/r/20161019145523.6763-1-narmstrong at baylibre.com :
>> - Simplify cmd_ctrl command and drop the ctrl address offset
>> - Change oxnas_nand struct name to oxnas_nand_ctrl
>> - Update DT-Bindings example to reflect the ctrl->chip->partitions hierarchy
>>
>> Changes since RFC http://lkml.kernel.org/r/20161018090927.1990-1-narmstrong at baylibre.com :
>> - Avoid using chip->IO_ADDR*
>> - Use new DT structure
>> - Assign a chip for the subnode
>> - Use the nand_hw_control structure
>> - Cleanup probe
>> - Cleanup cmd_ctrl by using a context ctrl offset used in write_bytes
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
>> new file mode 100644
>> index 0000000..33a77b8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
>> @@ -0,0 +1,41 @@
>> +* Oxford Semiconductor OXNAS NAND Controller
>> +
>> +Please refer to nand.txt for generic information regarding MTD NAND bindings.
>> +
>> +Required properties:
>> + - compatible: "oxsemi,ox820-nand"
>> + - reg: Base address and length for NAND mapped memory.
>> +
>> +Optional Properties:
>> + - clocks: phandle to the NAND gate clock if needed.
>> + - resets: phandle to the NAND reset control if needed.
>> +
>> +Example:
>> +
>> +nand: nand-controller at 41000000 {
>
> 'nandc:' or 'nand_ctrl:'
>
> Otherwise it may conflict with a NAND chip alias.
> The rest looks good, so no need to send a new version (I can fix it when
> applying the patch).
OK, thanks, I will fix in the dtsi accordingly.
>
> One last thing, I saw there was other people owning boards with this
> controller. Can I get one or two Tested-by?
I would like too, but it seems I'm the only one working upstream for now....
I hope it will change in near future once there is enough upstream for booting the platform.
>
> Thanks taking my reviews into account.
Thanks for reviewing !
Neil
>
> Regards,
>
> Boris
>
^ permalink raw reply
* [RESEND PATCH v3 2/2] ARM: dts: imx6ul: Add DTS for liteBoard
From: Shawn Guo @ 2016-10-20 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930093626.3843-2-m.niestroj@grinn-global.com>
On Fri, Sep 30, 2016 at 5:36 PM, Marcin Niestroj
<m.niestroj@grinn-global.com> wrote:
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg_usb_otg1_vbus: usb_otg1_regulator {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
> + regulator-name = "usb_otg1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio2 8 GPIO_ACTIVE_LOW>;
> + };
> + };
Please put it directly under root in the following naming schema to
save that fake simple-bus container node.
reg_xxx: regulator-xxx {
...
}
Note: underscore is in label name, while hyphen is in node name.
Shawn
> +};
^ permalink raw reply
* Handling of enet_out on i.MX28
From: Uwe Kleine-König @ 2016-10-20 9:11 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
The i.MX28 reference manual specifies for HW_CLKCTRL_ENET.CLK_OUT_EN:
"NOTE: This bit must be configured before ENET PLL is enabled.".
Currently this is not implemented: ENET PLL (aka pll2) is the parent of
enet_out and so common clk enables the PLL first and only then sets
HW_CLKCTRL_ENET.CLK_OUT_EN.
For now this is a theoretical problem because I don't see any issues. I
only notice the discrepancy between manual and reality.
Do you think this is a problem?
Apart from that I'm not happy with the handling of this clk. IMHO it
should better be called "enet-ref" or similar (for the fec). imx28.dtsi
specifies that the clk is in use[1] and if my machine doesn't I have to
do:
&mac0 {
...
/* overwrite clocks and clock-names to remove enet_out */
clocks = <&clks 57>, <&clks 57>;
clock-names = "ipg", "ahb";
...
};
in my board.dts. This is ugly because I have to repeat stuff that is
already in imx28.dtsi and it's not understandable without the comment.
It would be nice if dtc allowed to modify an array, then we could do:
clocks += <&clks 64>;
clock-names = += "enet_out";
(assuming the included dtsi doesn't specify this clock).
I first though it would be a good idea to specify the enet-ref clk as
follows:
&mac0 {
...
mdio {
clocks = <&clks 64>;
clock-names = "enet-ref";
...
};
};
but while this makes it easier for the board.dts to add (or remove) it,
it's not really right this way because the reference clock is needed for
data RX and TX, not the mdio bus. Technically these are two different
buses even though the "passengers" are often the same. (Even if two
MACs are in use, the enet-ref signal is shared.)
What do you think?
Best regards
Uwe
[1] clocks = <&clks 57>, <&clks 57>, <&clks 64>; clock-names = "ipg",
"ahb", "enet_out"; in &mac0.
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH V4 0/3] ARM64 LPC: legacy ISA I/O support
From: zhichang.yuan @ 2016-10-20 9:15 UTC (permalink / raw)
To: linux-arm-kernel
This patch supports the IPMI-bt device attached to the Low-Pin-Count interface
implemented on Hisilicon Hip06 SoC.
-----------
| LPC host|
| |
-----------
|
_____________V_______________LPC
| |
V V
------------
| BT(ipmi)|
------------
When master accesses those periperals beneath the Hip06 LPC, a specific LPC
driver is needed to make LPC host generate the standard LPC I/O cycles with
the target periperals'I/O port addresses. But on curent arm64 world, there is
no real I/O accesses. All the I/O operations through in/out pair are based on
MMIO which is not satisfied the I/O mechanism on Hip06 LPC.
To solve this issue and keep the relevant existing peripherals' driver
unchanged, this patch set redefines the in/out pair to support both the IO
operations for Hip06 LPC and the original MMIO. The way specific to Hip06 is
named as indirect-IO in this patchset.
Changes from V3:
- UART support deferred to a separate patchset; This patchset only support
ipmi device under LPC;
- LPC bus I/O range is fixed to 0 ~ (PCIBIOS_MIN_IO - 1), which is separeted
from PCI/PCIE PIO space;
- Based on Arnd's remarks, removed the ranges property from Hip06 lpc dts and
added a new fixup function, of_isa_indirect_io(), to get the I/O address
directly from LPC dts configurations;
- Support in(w,l)/out(w,l) for Hip06 lpc I/O;
- Decouple the header file dependency on the gerenic io.h by defining in/out
as normal functions in c file;
- removed unused macro definitions in the LPC driver;
Changes from V2:
- Support the PIO retrieval from the linux PIO generated by
pci_address_to_pio. This method replace the 4K PIO reservation in V2;
- Support the flat-tree earlycon;
- Some revises based on Arnd's remarks;
- Make sure the linux PIO range allocated to Hip06 LPC peripherals starts
from non-ZERO;
Changes from V1:
- Support the ACPI LPC device;
- Optimize the dts LPC driver in ISA compatible mode;
- Reserve the IO range below 4K in avoid the possible conflict with PCI host
IO ranges;
- Support the LPC uart and relevant earlycon;
Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com>
zhichang.yuan (3):
ARM64 LPC: Indirect ISA port IO introduced
ARM64 LPC: Add missing range exception for special ISA
ARM64 LPC: LPC driver implementation on Hip06
.../arm/hisilicon/hisilicon-low-pin-count.txt | 31 ++
MAINTAINERS | 8 +
arch/arm64/Kconfig | 6 +
arch/arm64/include/asm/extio.h | 94 ++++
arch/arm64/include/asm/io.h | 36 ++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/extio.c | 53 +++
drivers/bus/Kconfig | 8 +
drivers/bus/Makefile | 1 +
drivers/bus/hisi_lpc.c | 501 +++++++++++++++++++++
drivers/of/address.c | 47 +-
drivers/pci/pci.c | 6 +-
include/linux/of_address.h | 17 +
13 files changed, 804 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
create mode 100644 arch/arm64/include/asm/extio.h
create mode 100644 arch/arm64/kernel/extio.c
create mode 100644 drivers/bus/hisi_lpc.c
--
1.9.1
^ permalink raw reply
* [PATCH V4 1/3] ARM64 LPC: Indirect ISA port IO introduced
From: zhichang.yuan @ 2016-10-20 9:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476954940-242159-1-git-send-email-yuanzhichang@hisilicon.com>
For arm64, there is no I/O space as other architectural platforms, such as
X86. Most I/O accesses are achieved based on MMIO. But for some arm64 SoCs,
such as Hip06, when accessing some legacy ISA devices connected to LPC, those
known port addresses are used to control the corresponding target devices, for
example, 0x2f8 is for UART, 0xe4 is for ipmi-bt. It is different from the
normal MMIO mode in using.
To drive these devices, this patch introduces a method named indirect-IO.
In this method the in/out pair in arch/arm64/include/asm/io.h will be
redefined. When upper layer drivers call in/out with those known legacy port
addresses to access the peripherals, the hooking functions corrresponding to
those target peripherals will be called. Through this way, those upper layer
drivers which depend on in/out can run on Hip06 without any changes.
Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
arch/arm64/Kconfig | 6 +++
arch/arm64/include/asm/extio.h | 94 ++++++++++++++++++++++++++++++++++++++++++
arch/arm64/include/asm/io.h | 29 +++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/extio.c | 29 +++++++++++++
5 files changed, 159 insertions(+)
create mode 100644 arch/arm64/include/asm/extio.h
create mode 100644 arch/arm64/kernel/extio.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 30398db..103dbea 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -163,6 +163,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MIN
config ARCH_MMAP_RND_COMPAT_BITS_MAX
default 16
+config ARM64_INDIRECT_PIO
+ bool "access peripherals with legacy I/O port"
+ help
+ Support special accessors for ISA I/O devices. This is needed for
+ SoCs that do not support standard read/write for the ISA range.
+
config NO_IOPORT_MAP
def_bool y if !PCI
diff --git a/arch/arm64/include/asm/extio.h b/arch/arm64/include/asm/extio.h
new file mode 100644
index 0000000..6ae0787
--- /dev/null
+++ b/arch/arm64/include/asm/extio.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved.
+ * Author: Zhichang Yuan <yuanzhichang@hisilicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __LINUX_EXTIO_H
+#define __LINUX_EXTIO_H
+
+struct extio_ops {
+ unsigned long start;/* inclusive, sys io addr */
+ unsigned long end;/* inclusive, sys io addr */
+
+ u64 (*pfin)(void *devobj, unsigned long ptaddr, size_t dlen);
+ void (*pfout)(void *devobj, unsigned long ptaddr, u32 outval,
+ size_t dlen);
+ u64 (*pfins)(void *devobj, unsigned long ptaddr, void *inbuf,
+ size_t dlen, unsigned int count);
+ void (*pfouts)(void *devobj, unsigned long ptaddr,
+ const void *outbuf, size_t dlen,
+ unsigned int count);
+ void *devpara;
+};
+
+extern struct extio_ops *arm64_extio_ops;
+
+#define DECLARE_EXTIO(bw, type) \
+extern type in##bw(unsigned long addr); \
+extern void out##bw(type value, unsigned long addr); \
+extern void ins##bw(unsigned long addr, void *buffer, unsigned int count);\
+extern void outs##bw(unsigned long addr, const void *buffer, unsigned int count);
+
+#define BUILD_EXTIO(bw, type) \
+type in##bw(unsigned long addr) \
+{ \
+ if (!arm64_extio_ops || arm64_extio_ops->start > addr || \
+ arm64_extio_ops->end < addr) \
+ return read##bw(PCI_IOBASE + addr); \
+ return arm64_extio_ops->pfin ? \
+ arm64_extio_ops->pfin(arm64_extio_ops->devpara, \
+ addr, sizeof(type)) : -1; \
+} \
+ \
+void out##bw(type value, unsigned long addr) \
+{ \
+ if (!arm64_extio_ops || arm64_extio_ops->start > addr || \
+ arm64_extio_ops->end < addr) \
+ write##bw(value, PCI_IOBASE + addr); \
+ else \
+ if (arm64_extio_ops->pfout) \
+ arm64_extio_ops->pfout(arm64_extio_ops->devpara,\
+ addr, value, sizeof(type)); \
+} \
+ \
+void ins##bw(unsigned long addr, void *buffer, unsigned int count) \
+{ \
+ if (!arm64_extio_ops || arm64_extio_ops->start > addr || \
+ arm64_extio_ops->end < addr) \
+ reads##bw(PCI_IOBASE + addr, buffer, count); \
+ else \
+ if (arm64_extio_ops->pfins) \
+ arm64_extio_ops->pfins(arm64_extio_ops->devpara,\
+ addr, buffer, sizeof(type), count); \
+} \
+ \
+void outs##bw(unsigned long addr, const void *buffer, unsigned int count) \
+{ \
+ if (!arm64_extio_ops || arm64_extio_ops->start > addr || \
+ arm64_extio_ops->end < addr) \
+ writes##bw(PCI_IOBASE + addr, buffer, count); \
+ else \
+ if (arm64_extio_ops->pfouts) \
+ arm64_extio_ops->pfouts(arm64_extio_ops->devpara,\
+ addr, buffer, sizeof(type), count); \
+}
+
+static inline void arm64_set_extops(struct extio_ops *ops)
+{
+ if (ops)
+ WRITE_ONCE(arm64_extio_ops, ops);
+}
+
+#endif /* __LINUX_EXTIO_H*/
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 0bba427..136735d 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -31,6 +31,7 @@
#include <asm/early_ioremap.h>
#include <asm/alternative.h>
#include <asm/cpufeature.h>
+#include <asm/extio.h>
#include <xen/xen.h>
@@ -149,6 +150,34 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
+
+/*
+ * redefine the in(s)b/out(s)b for indirect-IO.
+ */
+#ifdef CONFIG_ARM64_INDIRECT_PIO
+#define inb inb
+#define outb outb
+#define insb insb
+#define outsb outsb
+/* external declaration */
+DECLARE_EXTIO(b, u8)
+
+#define inw inw
+#define outw outw
+#define insw insw
+#define outsw outsw
+
+DECLARE_EXTIO(w, u16)
+
+#define inl inl
+#define outl outl
+#define insl insl
+#define outsl outsl
+
+DECLARE_EXTIO(l, u32)
+#endif
+
+
/*
* String version of I/O memory access operations.
*/
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 7d66bba..60e0482 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -31,6 +31,7 @@ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
sys_compat.o entry32.o
arm64-obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o
arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o
+arm64-obj-$(CONFIG_ARM64_INDIRECT_PIO) += extio.o
arm64-obj-$(CONFIG_ARM64_MODULE_PLTS) += module-plts.o
arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o perf_callchain.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
diff --git a/arch/arm64/kernel/extio.c b/arch/arm64/kernel/extio.c
new file mode 100644
index 0000000..80cafd5
--- /dev/null
+++ b/arch/arm64/kernel/extio.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved.
+ * Author: Zhichang Yuan <yuanzhichang@hisilicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/io.h>
+
+struct extio_ops *arm64_extio_ops;
+
+
+BUILD_EXTIO(b, u8)
+
+BUILD_EXTIO(w, u16)
+
+BUILD_EXTIO(l, u32)
+
+#endif
--
1.9.1
^ permalink raw reply related
* [PATCH V4 2/3] ARM64 LPC: Add missing range exception for special ISA
From: zhichang.yuan @ 2016-10-20 9:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476954940-242159-1-git-send-email-yuanzhichang@hisilicon.com>
Currently if the range property is not specified of_translate_one
returns an error. There are some special devices that work on a
range of I/O ports where it's is not correct to specify a range
property as the cpu addresses are used by special accessors.
Here we add a new exception in of_translate_one to return
the cpu address if the range property is not there. The exception
checks if the parent bus is ISA and if the special accessors are
defined.
Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
arch/arm64/include/asm/io.h | 7 +++++++
arch/arm64/kernel/extio.c | 24 +++++++++++++++++++++++
drivers/of/address.c | 47 +++++++++++++++++++++++++++++++++++++++++++--
drivers/pci/pci.c | 6 +++---
include/linux/of_address.h | 17 ++++++++++++++++
5 files changed, 96 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 136735d..e480199 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -175,6 +175,13 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
#define outsl outsl
DECLARE_EXTIO(l, u32)
+
+
+#define indirect_io_ison indirect_io_ison
+extern int indirect_io_ison(void);
+
+#define chk_indirect_range chk_indirect_range
+extern int chk_indirect_range(u64 taddr);
#endif
diff --git a/arch/arm64/kernel/extio.c b/arch/arm64/kernel/extio.c
index 80cafd5..55df8dc 100644
--- a/arch/arm64/kernel/extio.c
+++ b/arch/arm64/kernel/extio.c
@@ -19,6 +19,30 @@
struct extio_ops *arm64_extio_ops;
+/**
+ * indirect_io_ison - check whether indirectIO can work well. This function only call
+ * before the target I/O address was obtained.
+ *
+ * Returns 1 when indirectIO can work.
+ */
+int indirect_io_ison()
+{
+ return arm64_extio_ops ? 1 : 0;
+}
+
+/**
+ * check_indirect_io - check whether the input taddr is for indirectIO.
+ * @taddr: the io address to be checked.
+ *
+ * Returns 1 when taddr is in the range; otherwise return 0.
+ */
+int chk_indirect_range(u64 taddr)
+{
+ if (arm64_extio_ops->start > taddr || arm64_extio_ops->end < taddr)
+ return 0;
+
+ return 1;
+}
BUILD_EXTIO(b, u8)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 02b2903..0bee822 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -479,6 +479,39 @@ static int of_empty_ranges_quirk(struct device_node *np)
return false;
}
+
+/*
+ * Check whether the current device being translating use indirectIO.
+ *
+ * return 1 if the check is past, or 0 represents fail checking.
+ */
+static int of_isa_indirect_io(struct device_node *parent,
+ struct of_bus *bus, __be32 *addr,
+ int na, u64 *presult)
+{
+ unsigned int flags;
+ unsigned int rlen;
+
+ /* whether support indirectIO */
+ if (!indirect_io_ison())
+ return 0;
+
+ if (!of_bus_isa_match(parent))
+ return 0;
+
+ flags = bus->get_flags(addr);
+ if (!(flags & IORESOURCE_IO))
+ return 0;
+
+ /* there is ranges property, apply the normal translation directly. */
+ if (of_get_property(parent, "ranges", &rlen))
+ return 0;
+
+ *presult = of_read_number(addr + 1, na - 1);
+
+ return chk_indirect_range(*presult);
+}
+
static int of_translate_one(struct device_node *parent, struct of_bus *bus,
struct of_bus *pbus, __be32 *addr,
int na, int ns, int pna, const char *rprop)
@@ -532,7 +565,7 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
}
memcpy(addr, ranges + na, 4 * pna);
- finish:
+finish:
of_dump_addr("parent translation for:", addr, pna);
pr_debug("with offset: %llx\n", (unsigned long long)offset);
@@ -595,6 +628,15 @@ static u64 __of_translate_address(struct device_node *dev,
result = of_read_number(addr, na);
break;
}
+ /*
+ * For indirectIO device which has no ranges property, get
+ * the address from reg directly.
+ */
+ if (of_isa_indirect_io(dev, bus, addr, na, &result)) {
+ pr_info("isa indirectIO matched(%s)..addr = 0x%llx\n",
+ of_node_full_name(dev), result);
+ break;
+ }
/* Get new parent bus and counts */
pbus = of_match_bus(parent);
@@ -688,8 +730,9 @@ static int __of_address_to_resource(struct device_node *dev,
if (taddr == OF_BAD_ADDR)
return -EINVAL;
memset(r, 0, sizeof(struct resource));
- if (flags & IORESOURCE_IO) {
+ if (flags & IORESOURCE_IO && taddr >= PCIBIOS_MIN_IO) {
unsigned long port;
+
port = pci_address_to_pio(taddr);
if (port == (unsigned long)-1)
return -EINVAL;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index ba34907..1a08511 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3263,7 +3263,7 @@ int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
#ifdef PCI_IOBASE
struct io_range *range;
- resource_size_t allocated_size = 0;
+ resource_size_t allocated_size = PCIBIOS_MIN_IO;
/* check if the range hasn't been previously recorded */
spin_lock(&io_range_lock);
@@ -3312,7 +3312,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
#ifdef PCI_IOBASE
struct io_range *range;
- resource_size_t allocated_size = 0;
+ resource_size_t allocated_size = PCIBIOS_MIN_IO;
if (pio > IO_SPACE_LIMIT)
return address;
@@ -3335,7 +3335,7 @@ unsigned long __weak pci_address_to_pio(phys_addr_t address)
{
#ifdef PCI_IOBASE
struct io_range *res;
- resource_size_t offset = 0;
+ resource_size_t offset = PCIBIOS_MIN_IO;
unsigned long addr = -1;
spin_lock(&io_range_lock);
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index 3786473..0ba7e21 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -24,6 +24,23 @@ struct of_pci_range {
#define for_each_of_pci_range(parser, range) \
for (; of_pci_range_parser_one(parser, range);)
+
+#ifndef indirect_io_ison
+#define indirect_io_ison indirect_io_ison
+static inline int indirect_io_ison(void)
+{
+ return 0;
+}
+#endif
+
+#ifndef chk_indirect_range
+#define chk_indirect_range chk_indirect_range
+static inline int chk_indirect_range(u64 taddr)
+{
+ return 0;
+}
+#endif
+
/* Translate a DMA address from device space to CPU space */
extern u64 of_translate_dma_address(struct device_node *dev,
const __be32 *in_addr);
--
1.9.1
^ permalink raw reply related
* [PATCH V4 3/3] ARM64 LPC: LPC driver implementation on Hip06
From: zhichang.yuan @ 2016-10-20 9:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476954940-242159-1-git-send-email-yuanzhichang@hisilicon.com>
On Hip06, the accesses to LPC peripherals work in an indirect way. A
corresponding LPC driver configure some registers in LPC master at first, then
the real accesses on LPC slave devices are finished by the LPC master, which
is transparent to LPC driver.
This patch implement the relevant driver for Hip06 LPC. Cooperating with
indirect-IO, ipmi messages is in service without any changes on ipmi driver.
Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 31 ++
MAINTAINERS | 8 +
drivers/bus/Kconfig | 8 +
drivers/bus/Makefile | 1 +
drivers/bus/hisi_lpc.c | 501 +++++++++++++++++++++
5 files changed, 549 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
create mode 100644 drivers/bus/hisi_lpc.c
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
new file mode 100644
index 0000000..e681419
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
@@ -0,0 +1,31 @@
+Hisilicon Hip06 low-pin-count device
+ Usually LPC controller is part of PCI host bridge, so the legacy ISA ports
+ locate on LPC bus can be accessed direclty. But some SoCs have independent
+ LPC controller, and access the legacy ports by triggering LPC I/O cycles.
+ Hisilicon Hip06 implements this LPC device.
+
+Required properties:
+- compatible: should be "hisilicon,low-pin-count"
+- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
+- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
+- reg: base memory range where the register set for this device is mapped.
+
+Note:
+ The node name before '@' must be "isa" to represent the binding stick to the
+ ISA/EISA binding specification.
+
+Example:
+
+isa at a01b0000 {
+ compatible = "hisilicom,low-pin-count";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0x0 0xa01b0000 0x0 0x1000>;
+
+ ipmi0: bt at e4 {
+ compatible = "ipmi-bt";
+ device_type = "ipmi";
+ reg = <0x01 0xe4 0x04>;
+ status = "disabled";
+ };
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..7c69410 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5716,6 +5716,14 @@ F: include/uapi/linux/if_hippi.h
F: net/802/hippi.c
F: drivers/net/hippi/
+HISILICON LPC BUS DRIVER
+M: Zhichang Yuan <yuanzhichang@hisilicon.com>
+L: linux-arm-kernel at lists.infradead.org
+W: http://www.hisilicon.com
+S: Maintained
+F: drivers/bus/hisi_lpc.c
+F: Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
+
HISILICON NETWORK SUBSYSTEM DRIVER
M: Yisen Zhuang <yisen.zhuang@huawei.com>
M: Salil Mehta <salil.mehta@huawei.com>
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 7010dca..a108abc 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -64,6 +64,14 @@ config BRCMSTB_GISB_ARB
arbiter. This driver provides timeout and target abort error handling
and internal bus master decoding.
+config HISILICON_LPC
+ bool "Workaround for nonstandard ISA I/O space on Hisilicon Hip0X"
+ depends on (ARCH_HISI || COMPILE_TEST) && ARM64
+ select ARM64_INDIRECT_PIO
+ help
+ Driver needed for some legacy ISA devices attached to Low-Pin-Count
+ on Hisilicon Hip0X SoC.
+
config IMX_WEIM
bool "Freescale EIM DRIVER"
depends on ARCH_MXC
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index c6cfa6b..10b4983 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_ARM_CCI) += arm-cci.o
obj-$(CONFIG_ARM_CCN) += arm-ccn.o
obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
+obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o
obj-$(CONFIG_IMX_WEIM) += imx-weim.o
obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o
obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c
new file mode 100644
index 0000000..9f48a1a
--- /dev/null
+++ b/drivers/bus/hisi_lpc.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved.
+ * Author: Zhichang Yuan <yuanzhichang@hisilicon.com>
+ * Author: Zou Rongrong <zourongrong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/acpi.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+
+/*
+ * this bit set means each IO operation will target to different port address;
+ * 0 means repeatly IO operations will be sticked on the same port, such as BT;
+ */
+#define FG_INCRADDR_LPC 0x02
+
+struct lpc_cycle_para {
+ unsigned int opflags;
+ unsigned int csize;/* the data length of each operation */
+};
+
+struct hisilpc_dev {
+ spinlock_t cycle_lock;
+ void __iomem *membase;
+ struct extio_ops io_ops;
+};
+
+
+/* The maximum continous operations*/
+#define LPC_MAX_OPCNT 16
+/* only support IO data unit length is four at maximum */
+#define LPC_MAX_DULEN 4
+#if LPC_MAX_DULEN > LPC_MAX_OPCNT
+#error "LPC.. MAX_DULEN must be not bigger than MAX_OPCNT!"
+#endif
+
+#define LPC_REG_START 0x00/* start a new LPC cycle */
+#define LPC_REG_OP_STATUS 0x04/* the current LPC status */
+#define LPC_REG_IRQ_ST 0x08/* interrupt enable&status */
+#define LPC_REG_OP_LEN 0x10/* how many LPC cycles each start */
+#define LPC_REG_CMD 0x14/* command for the required LPC cycle */
+#define LPC_REG_ADDR 0x20/* LPC target address */
+#define LPC_REG_WDATA 0x24/* data to be written */
+#define LPC_REG_RDATA 0x28/* data coming from peer */
+
+
+/* The command register fields*/
+#define LPC_CMD_SAMEADDR 0x08
+#define LPC_CMD_TYPE_IO 0x00
+#define LPC_CMD_WRITE 0x01
+#define LPC_CMD_READ 0x00
+/* the bit attribute is W1C. 1 represents OK. */
+#define LPC_STAT_BYIRQ 0x02
+
+#define LPC_STATUS_IDLE 0x01
+#define LPC_OP_FINISHED 0x02
+
+#define START_WORK 0x01
+
+/*
+ * The minimal waiting interval... Suggest it is not less than 10.
+ * Bigger value probably will lower the performance.
+ */
+#define LPC_NSEC_PERWAIT 100
+/*
+ * The maximum waiting time is about 128us.
+ * The fastest IO cycle time is about 390ns, but the worst case will wait
+ * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum
+ * burst cycles is 16. So, the maximum waiting time is about 128us under
+ * worst case.
+ * choose 1300 as the maximum.
+ */
+#define LPC_MAX_WAITCNT 1300
+/* About 10us. This is specfic for single IO operation, such as inb. */
+#define LPC_PEROP_WAITCNT 100
+
+
+static inline int wait_lpc_idle(unsigned char *mbase,
+ unsigned int waitcnt) {
+ u32 opstatus;
+
+ while (waitcnt--) {
+ ndelay(LPC_NSEC_PERWAIT);
+ opstatus = readl(mbase + LPC_REG_OP_STATUS);
+ if (opstatus & LPC_STATUS_IDLE)
+ return (opstatus & LPC_OP_FINISHED) ? 0 : (-EIO);
+ }
+ return -ETIME;
+}
+
+
+/**
+ * hisilpc_target_in - trigger a series of lpc cycles to read required data
+ * from target periperal.
+ * @pdev: pointer to hisi lpc device
+ * @para: some paramerters used to control the lpc I/O operations
+ * @ptaddr: the lpc I/O target port address
+ * @buf: where the read back data is stored
+ * @opcnt: how many I/O operations required in this calling
+ *
+ * only one byte data is read each I/O operation.
+ *
+ * Returns 0 on success, non-zero on fail.
+ *
+ */
+static int hisilpc_target_in(struct hisilpc_dev *pdev,
+ struct lpc_cycle_para *para,
+ unsigned long ptaddr, unsigned char *buf,
+ unsigned long opcnt)
+{
+ unsigned int cmd_word;
+ unsigned int waitcnt;
+ int retval;
+ unsigned long flags;
+ unsigned long cnt_per_trans;
+
+ if (!buf || !opcnt || !para || !para->csize || !pdev)
+ return -EINVAL;
+
+ if (opcnt > LPC_MAX_OPCNT)
+ return -EINVAL;
+
+ cmd_word = LPC_CMD_TYPE_IO | LPC_CMD_READ;
+ waitcnt = (LPC_PEROP_WAITCNT);
+ if (!(para->opflags & FG_INCRADDR_LPC)) {
+ cmd_word |= LPC_CMD_SAMEADDR;
+ waitcnt = LPC_MAX_WAITCNT;
+ }
+
+ retval = 0;
+ cnt_per_trans = (para->csize == 1) ? opcnt : para->csize;
+ for (; opcnt && !retval; cnt_per_trans = para->csize) {
+ /* whole operation must be atomic */
+ spin_lock_irqsave(&pdev->cycle_lock, flags);
+
+ writel(cnt_per_trans, pdev->membase + LPC_REG_OP_LEN);
+
+ writel(cmd_word, pdev->membase + LPC_REG_CMD);
+
+ writel(ptaddr, pdev->membase + LPC_REG_ADDR);
+
+ writel(START_WORK, pdev->membase + LPC_REG_START);
+
+ /* whether the operation is finished */
+ retval = wait_lpc_idle(pdev->membase, waitcnt);
+ if (!retval) {
+ opcnt -= cnt_per_trans;
+ for (; cnt_per_trans--; buf++)
+ *buf = readl(pdev->membase + LPC_REG_RDATA);
+ }
+
+ spin_unlock_irqrestore(&pdev->cycle_lock, flags);
+ }
+
+ return retval;
+}
+
+/**
+ * hisilpc_target_out - trigger a series of lpc cycles to write required data
+ * to target periperal.
+ * @pdev: pointer to hisi lpc device
+ * @para: some paramerters used to control the lpc I/O operations
+ * @ptaddr: the lpc I/O target port address
+ * @buf: where the data to be written is stored
+ * @opcnt: how many I/O operations required
+ *
+ * only one byte data is read each I/O operation.
+ *
+ * Returns 0 on success, non-zero on fail.
+ *
+ */
+static int hisilpc_target_out(struct hisilpc_dev *pdev,
+ struct lpc_cycle_para *para,
+ unsigned long ptaddr,
+ const unsigned char *buf,
+ unsigned long opcnt)
+{
+ unsigned int cmd_word;
+ unsigned int waitcnt;
+ int retval;
+ unsigned long flags;
+ unsigned long cnt_per_trans;
+
+ if (!buf || !opcnt || !para || !pdev)
+ return -EINVAL;
+
+ if (opcnt > LPC_MAX_OPCNT)
+ return -EINVAL;
+ /* default is increasing address */
+ cmd_word = LPC_CMD_TYPE_IO | LPC_CMD_WRITE;
+ waitcnt = (LPC_PEROP_WAITCNT);
+ if (!(para->opflags & FG_INCRADDR_LPC)) {
+ cmd_word |= LPC_CMD_SAMEADDR;
+ waitcnt = LPC_MAX_WAITCNT;
+ }
+
+ retval = 0;
+ cnt_per_trans = (para->csize == 1) ? opcnt : para->csize;
+ for (; opcnt && !retval; cnt_per_trans = para->csize) {
+ spin_lock_irqsave(&pdev->cycle_lock, flags);
+
+ writel(cnt_per_trans, pdev->membase + LPC_REG_OP_LEN);
+ opcnt -= cnt_per_trans;
+ for (; cnt_per_trans--; buf++)
+ writel(*buf, pdev->membase + LPC_REG_WDATA);
+
+ writel(cmd_word, pdev->membase + LPC_REG_CMD);
+
+ writel(ptaddr, pdev->membase + LPC_REG_ADDR);
+
+ writel(START_WORK, pdev->membase + LPC_REG_START);
+
+ /* whether the operation is finished */
+ retval = wait_lpc_idle(pdev->membase, waitcnt);
+
+ spin_unlock_irqrestore(&pdev->cycle_lock, flags);
+ }
+
+ return retval;
+}
+
+
+/**
+ * hisilpc_comm_in - read/input the data from the I/O peripheral through LPC.
+ * @devobj: pointer to the device information relevant to LPC controller.
+ * @ptaddr: the target I/O port address.
+ * @dlen: the data length required to read from the target I/O port.
+ *
+ * when succeed, the data read back is stored in buffer pointed by inbuf.
+ * For inb, return the data read from I/O or -1 when error occur.
+ */
+static u64 hisilpc_comm_in(void *devobj, unsigned long ptaddr, size_t dlen)
+{
+ struct hisilpc_dev *lpcdev;
+ struct lpc_cycle_para iopara;
+ u32 rd_data;
+ unsigned char *newbuf;
+ int ret = 0;
+
+ if (!devobj || !dlen || dlen > LPC_MAX_DULEN || (dlen & (dlen - 1)))
+ return -1;
+
+ /* the local buffer must be enough for one data unit */
+ if (sizeof(rd_data) < dlen)
+ return -1;
+
+ newbuf = (unsigned char *)&rd_data;
+
+ lpcdev = (struct hisilpc_dev *)devobj;
+
+ iopara.opflags = FG_INCRADDR_LPC;
+ iopara.csize = dlen;
+
+ ret = hisilpc_target_in(lpcdev, &iopara, ptaddr, newbuf, dlen);
+ if (ret)
+ return -1;
+
+ return le32_to_cpu(rd_data);
+}
+
+/**
+ * hisilpc_comm_out - write/output the data whose maximal length is four bytes to
+ * the I/O peripheral through LPC.
+ * @devobj: pointer to the device information relevant to LPC controller.
+ * @outval: a value to be outputed from caller, maximum is four bytes.
+ * @ptaddr: the target I/O port address.
+ * @dlen: the data length required writing to the target I/O port .
+ *
+ * This function is corresponding to out(b,w,l) only
+ *
+ */
+static void hisilpc_comm_out(void *devobj, unsigned long ptaddr,
+ u32 outval, size_t dlen)
+{
+ struct hisilpc_dev *lpcdev;
+ struct lpc_cycle_para iopara;
+ const unsigned char *newbuf;
+
+ if (!devobj || !dlen || dlen > LPC_MAX_DULEN)
+ return;
+
+ if (sizeof(outval) < dlen)
+ return;
+
+ outval = cpu_to_le32(outval);
+
+ newbuf = (const unsigned char *)&outval;
+ lpcdev = (struct hisilpc_dev *)devobj;
+
+ iopara.opflags = FG_INCRADDR_LPC;
+ iopara.csize = dlen;
+
+ hisilpc_target_out(lpcdev, &iopara, ptaddr, newbuf, dlen);
+}
+
+
+/**
+ * hisilpc_comm_ins - read/input the data in buffer to the I/O peripheral
+ * through LPC, it corresponds to ins(b,w,l)
+ * @devobj: pointer to the device information relevant to LPC controller.
+ * @ptaddr: the target I/O port address.
+ * @inbuf: a buffer where read/input data bytes are stored.
+ * @dlen: the data length required writing to the target I/O port .
+ * @count: how many data units whose length is dlen will be read.
+ *
+ */
+static u64 hisilpc_comm_ins(void *devobj, unsigned long ptaddr,
+ void *inbuf, size_t dlen, unsigned int count)
+{
+ struct hisilpc_dev *lpcdev;
+ struct lpc_cycle_para iopara;
+ unsigned char *newbuf;
+ unsigned int loopcnt, cntleft;
+ unsigned int max_perburst;
+ int ret = 0;
+
+ if (!devobj || !inbuf || !count || !dlen ||
+ dlen > LPC_MAX_DULEN || (dlen & (dlen - 1)))
+ return -1;
+
+ iopara.opflags = 0;
+ if (dlen > 1)
+ iopara.opflags |= FG_INCRADDR_LPC;
+ iopara.csize = dlen;
+
+ lpcdev = (struct hisilpc_dev *)devobj;
+ newbuf = (unsigned char *)inbuf;
+ /*
+ * ensure data stream whose lenght is multiple of dlen to be processed
+ * each IO input
+ */
+ max_perburst = LPC_MAX_OPCNT & (~(dlen - 1));
+ cntleft = count * dlen;
+ do {
+ loopcnt = (cntleft >= max_perburst) ? max_perburst : cntleft;
+ ret = hisilpc_target_in(lpcdev, &iopara, ptaddr, newbuf,
+ loopcnt);
+ if (ret)
+ break;
+ newbuf += loopcnt;
+ cntleft -= loopcnt;
+ } while (cntleft);
+
+ return ret;
+}
+
+/**
+ * hisilpc_comm_outs - write/output the data in buffer to the I/O peripheral
+ * through LPC, it corresponds to outs(b,w,l)
+ * @devobj: pointer to the device information relevant to LPC controller.
+ * @ptaddr: the target I/O port address.
+ * @outbuf: a buffer where write/output data bytes are stored.
+ * @dlen: the data length required writing to the target I/O port .
+ * @count: how many data units whose length is dlen will be written.
+ *
+ */
+static void hisilpc_comm_outs(void *devobj, unsigned long ptaddr,
+ const void *outbuf, size_t dlen, unsigned int count)
+{
+ struct hisilpc_dev *lpcdev;
+ struct lpc_cycle_para iopara;
+ const unsigned char *newbuf;
+ unsigned int loopcnt, cntleft;
+ unsigned int max_perburst;
+ int ret = 0;
+
+ if (!devobj || !outbuf || !count || !dlen ||
+ dlen > LPC_MAX_DULEN || (dlen & (dlen - 1)))
+ return;
+
+ iopara.opflags = 0;
+ if (dlen > 1)
+ iopara.opflags |= FG_INCRADDR_LPC;
+ iopara.csize = dlen;
+
+ lpcdev = (struct hisilpc_dev *)devobj;
+ newbuf = (unsigned char *)outbuf;
+ /*
+ * ensure data stream whose lenght is multiple of dlen to be processed
+ * each IO input
+ */
+ max_perburst = LPC_MAX_OPCNT & (~(dlen - 1));
+ cntleft = count * dlen;
+ do {
+ loopcnt = (cntleft >= max_perburst) ? max_perburst : cntleft;
+ ret = hisilpc_target_out(lpcdev, &iopara, ptaddr, newbuf,
+ loopcnt);
+ if (ret)
+ break;
+ newbuf += loopcnt;
+ cntleft -= loopcnt;
+ } while (cntleft);
+}
+
+
+/**
+ * hisilpc_probe - the probe callback function for hisi lpc device,
+ * will finish all the intialization.
+ * @pdev: the platform device corresponding to hisi lpc
+ *
+ * Returns 0 on success, non-zero on fail.
+ *
+ */
+static int hisilpc_probe(struct platform_device *pdev)
+{
+ struct resource *iores;
+ struct hisilpc_dev *lpcdev;
+ int ret;
+
+ dev_info(&pdev->dev, "hslpc start probing...\n");
+
+ lpcdev = devm_kzalloc(&pdev->dev,
+ sizeof(struct hisilpc_dev), GFP_KERNEL);
+ if (!lpcdev)
+ return -ENOMEM;
+
+ spin_lock_init(&lpcdev->cycle_lock);
+ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ lpcdev->membase = devm_ioremap_resource(&pdev->dev, iores);
+ if (IS_ERR(lpcdev->membase)) {
+ dev_err(&pdev->dev, "No mem resource for memory mapping!\n");
+ return PTR_ERR(lpcdev->membase);
+ }
+ /*
+ * The first PCIBIOS_MIN_IO is reserved specific for indirectIO.
+ * It will separate indirectIO range from pci host bridge to
+ * avoid the possible PIO conflict.
+ * Set the indirectIO range directly here.
+ */
+ lpcdev->io_ops.start = 0;
+ lpcdev->io_ops.end = PCIBIOS_MIN_IO - 1;
+ lpcdev->io_ops.devpara = lpcdev;
+ lpcdev->io_ops.pfin = hisilpc_comm_in;
+ lpcdev->io_ops.pfout = hisilpc_comm_out;
+ lpcdev->io_ops.pfins = hisilpc_comm_ins;
+ lpcdev->io_ops.pfouts = hisilpc_comm_outs;
+
+ platform_set_drvdata(pdev, lpcdev);
+
+ arm64_set_extops(&lpcdev->io_ops);
+
+ /*
+ * The children scanning is only for dts mode. For ACPI children,
+ * the corresponding devices had be created during acpi scanning.
+ */
+ ret = 0;
+ if (!has_acpi_companion(&pdev->dev))
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+
+ if (!ret)
+ dev_info(&pdev->dev, "hslpc end probing. range[0x%lx - %lx]\n",
+ arm64_extio_ops->start, arm64_extio_ops->end);
+ else
+ dev_info(&pdev->dev, "hslpc probing is fail(%d)\n", ret);
+
+ return ret;
+}
+
+static const struct of_device_id hisilpc_of_match[] = {
+ {
+ .compatible = "hisilicon,low-pin-count",
+ },
+ {},
+};
+
+static const struct acpi_device_id hisilpc_acpi_match[] = {
+ {"HISI0191", },
+ {},
+};
+
+static struct platform_driver hisilpc_driver = {
+ .driver = {
+ .name = "hisi_lpc",
+ .of_match_table = hisilpc_of_match,
+ .acpi_match_table = hisilpc_acpi_match,
+ },
+ .probe = hisilpc_probe,
+};
+
+
+builtin_platform_driver(hisilpc_driver);
--
1.9.1
^ permalink raw reply related
* [PATCH v7 10/11] arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3
From: Simon Horman @ 2016-10-20 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916103317.GN1411@katana>
On Fri, Sep 16, 2016 at 12:33:17PM +0200, Wolfram Sang wrote:
> On Tue, Sep 13, 2016 at 12:57:07PM +0200, Simon Horman wrote:
> > Based on work for the r8a7796 by Wolfram Sang.
> >
> > Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks, I have queued this up.
^ permalink raw reply
* [PATCH v7 08/11] arm64: dts: r8a7796: add SDHI nodes
From: Simon Horman @ 2016-10-20 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916105321.GB7566@verge.net.au>
On Fri, Sep 16, 2016 at 12:53:22PM +0200, Simon Horman wrote:
> On Fri, Sep 16, 2016 at 12:30:48PM +0200, Wolfram Sang wrote:
> > On Tue, Sep 13, 2016 at 12:57:05PM +0200, Simon Horman wrote:
> > > Add SDHI nodes to the DT of the r8a7796 SoC.
> > >
> > > Based on the DT of the r8a7795 SoC.
> > >
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > If you remove the two lines you removed from H3 already:
>
> Thanks, done.
>
> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
I have queued this up for v4.10.
^ permalink raw reply
* [PATCH v7 09/11] arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3
From: Simon Horman @ 2016-10-20 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916103218.GM1411@katana>
On Fri, Sep 16, 2016 at 12:32:18PM +0200, Wolfram Sang wrote:
> On Tue, Sep 13, 2016 at 12:57:06PM +0200, Simon Horman wrote:
> > Enable the exposed SD card slots in the DT of the r8a7796/salvator-x.
> >
> > Based on work for the r8a7795/salvator-x by Ai Kyuse.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks, I have queued this up.
^ permalink raw reply
* [PATCH v3 0/11] Add R8A7743/SK-RZG1M board support
From: Simon Horman @ 2016-10-20 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cea44556-a578-fb54-11b8-f21f5b991caa@cogentembedded.com>
On Wed, Oct 12, 2016 at 11:29:56AM +0300, Sergei Shtylyov wrote:
> On 10/12/2016 11:09 AM, Simon Horman wrote:
>
> >>> Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
> >>>'renesas-devel-20161003-v4.8' tag. I'm adding the device tree support for
> >>>the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board
> >>>seems identical to the R8A7791/Porter board. The device tree patches depend on
> >>>the R8A7743 CPG/MSSR driver series just posted in order to compile and work.
> >>
> >> Forgot to mention that this version causes a regression with the sh_eth
> >>driver (well, actually with phylib): since IRQC now gets a deferred probing,
> >>PHY IRQ doesn't work anymore -- phylib falls back to polling.
> >
> >Is there a resolution to that problem?
>
> Geert has posted his IRQC driver patch recently. Not sure if it was
> intended for merging but it solves the issue.
Ok. I think it is ok to merge support for a new board even if there are
problems as its not regressing (can't break something that previously
didn't exist imho). But of course it would be best if things did work.
Geert, do you have any comments on the relevance of your IRQC driver patch?
^ permalink raw reply
* [PATCH v3 0/5] Cavium ThunderX uncore PMU support
From: Jan Glauber @ 2016-10-20 9:30 UTC (permalink / raw)
To: linux-arm-kernel
Sorry for the long time it took for re-cooking this patch set.
The v3 should address all of Marks previous comments, things I didn't
change are listed below.
Not changed:
- Stick to NUMA node ID to detect the socket a device belongs to but made
uncore depend on CONFIG_NUMA.
- Stick to initcall for uncore framework because it is easier to do the
scanning for the same type of PCI devices, also I don't know if the PCI layer
would allow for several drivers to register for the same device ID.
Note:
I'm using perf_sw_context in difference to perf_invalid_context
(see WARN_ON in perf_pmu_register). Reason is that with perf_invalid_context
add() is never called and the counter results are shown as "unsupported" by
perf. With perf_sw_context everything works as expected.
Patches are against 4.9.0-rc1
Changes to v2:
- Embedded struct pmu and killed uncore->type
- Simplified add functions
- Unified functions where possible into a common implementation
- Use arrays to translate non-contiguous counter addresses to event_id's
visible to the user
- Sorted includes
- Got rid of division for previous counter values
- Removed unneeded WARN_ONs
- Use sizeof(*ptr)
- Use bool for event_valid return
- Fixed HES_STOPPED logic
- Added some design notes and improved (hopefully) comments
- Removed pass1 counter support for now
- Merged EVENT_ATTR and EVENT_PTR defines into one (unreadable) thing
- Use pmu_enable|disable to start|stop the OCX TLK counter set
- Moved cpumask into thunder_uncore struct
- Switched to new cpuhp stuff. I still don't care about the CPU location
used to access an uncore device, it may cross the CCPI and
we'll pay a performance penalty. We might optimize this later, for now
I feel it is not worth the time optimizing it.
------------------------
Jan Glauber (5):
arm64: perf: Basic uncore counter support for Cavium ThunderX SOC
arm64: perf: Cavium ThunderX L2C TAD uncore support
arm64: perf: Cavium ThunderX L2C CBC uncore support
arm64: perf: Cavium ThunderX LMC uncore support
arm64: perf: Cavium ThunderX OCX TLK uncore support
drivers/perf/Kconfig | 13 +
drivers/perf/Makefile | 1 +
drivers/perf/uncore/Makefile | 5 +
drivers/perf/uncore/uncore_cavium.c | 355 ++++++++++++++++++++++++++
drivers/perf/uncore/uncore_cavium.h | 75 ++++++
drivers/perf/uncore/uncore_cavium_l2c_cbc.c | 148 +++++++++++
drivers/perf/uncore/uncore_cavium_l2c_tad.c | 379 ++++++++++++++++++++++++++++
drivers/perf/uncore/uncore_cavium_lmc.c | 118 +++++++++
drivers/perf/uncore/uncore_cavium_ocx_tlk.c | 344 +++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
10 files changed, 1439 insertions(+)
create mode 100644 drivers/perf/uncore/Makefile
create mode 100644 drivers/perf/uncore/uncore_cavium.c
create mode 100644 drivers/perf/uncore/uncore_cavium.h
create mode 100644 drivers/perf/uncore/uncore_cavium_l2c_cbc.c
create mode 100644 drivers/perf/uncore/uncore_cavium_l2c_tad.c
create mode 100644 drivers/perf/uncore/uncore_cavium_lmc.c
create mode 100644 drivers/perf/uncore/uncore_cavium_ocx_tlk.c
--
1.9.1
^ permalink raw reply
* [PATCH v3 1/5] arm64: perf: Basic uncore counter support for Cavium ThunderX SOC
From: Jan Glauber @ 2016-10-20 9:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476955841-27898-1-git-send-email-jglauber@cavium.com>
Provide "uncore" facilities for different non-CPU performance
counter units.
The uncore PMUs can be found under /sys/bus/event_source/devices.
All counters are exported via sysfs in the corresponding events
files under the PMU directory so the perf tool can list the event names.
There are some points that are special in this implementation:
1) The PMU detection relies on PCI device detection. If a
matching PCI device is found the PMU is created. The code can deal
with multiple units of the same type, e.g. more than one memory
controller.
2) Counters are summarized across different units of the same type
on one NUMA node but not across NUMA nodes.
For instance L2C TAD 0..7 are presented as a single counter
(adding the values from TAD 0 to 7). Although losing the ability
to read a single value the merged values are easier to use.
3) The counters are not CPU related. A random CPU is picked regardless
of the NUMA node. There is a small performance penalty for accessing
counters on a remote note but reading a performance counter is a
slow operation anyway.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
drivers/perf/Kconfig | 13 ++
drivers/perf/Makefile | 1 +
drivers/perf/uncore/Makefile | 1 +
drivers/perf/uncore/uncore_cavium.c | 351 ++++++++++++++++++++++++++++++++++++
drivers/perf/uncore/uncore_cavium.h | 71 ++++++++
include/linux/cpuhotplug.h | 1 +
6 files changed, 438 insertions(+)
create mode 100644 drivers/perf/uncore/Makefile
create mode 100644 drivers/perf/uncore/uncore_cavium.c
create mode 100644 drivers/perf/uncore/uncore_cavium.h
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..3266c87 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -19,4 +19,17 @@ config XGENE_PMU
help
Say y if you want to use APM X-Gene SoC performance monitors.
+config UNCORE_PMU
+ bool
+
+config UNCORE_PMU_CAVIUM
+ depends on PERF_EVENTS && NUMA && ARM64
+ bool "Cavium uncore PMU support"
+ select UNCORE_PMU
+ default y
+ help
+ Say y if you want to access performance counters of subsystems
+ on a Cavium SOC like cache controller, memory controller or
+ processor interconnect.
+
endmenu
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index b116e98..144374b 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ARM_PMU) += arm_pmu.o
+obj-y += uncore/
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
diff --git a/drivers/perf/uncore/Makefile b/drivers/perf/uncore/Makefile
new file mode 100644
index 0000000..6130e18
--- /dev/null
+++ b/drivers/perf/uncore/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_UNCORE_PMU_CAVIUM) += uncore_cavium.o
diff --git a/drivers/perf/uncore/uncore_cavium.c b/drivers/perf/uncore/uncore_cavium.c
new file mode 100644
index 0000000..a7b4277
--- /dev/null
+++ b/drivers/perf/uncore/uncore_cavium.c
@@ -0,0 +1,351 @@
+/*
+ * Cavium Thunder uncore PMU support.
+ *
+ * Copyright (C) 2015,2016 Cavium Inc.
+ * Author: Jan Glauber <jan.glauber@cavium.com>
+ */
+
+#include <linux/cpufeature.h>
+#include <linux/numa.h>
+#include <linux/slab.h>
+
+#include "uncore_cavium.h"
+
+/*
+ * Some notes about the various counters supported by this "uncore" PMU
+ * and the design:
+ *
+ * All counters are 64 bit long.
+ * There are no overflow interrupts.
+ * Counters are summarized per node/socket.
+ * Most devices appear as separate PCI devices per socket with the exception
+ * of OCX TLK which appears as one PCI device per socket and contains several
+ * units with counters that are merged.
+ * Some counters are selected via a control register (L2C TAD) and read by
+ * a number of counter registers, others (L2C CBC, LMC & OCX TLK) have
+ * one dedicated counter per event.
+ * Some counters are not stoppable (L2C CBC & LMC).
+ * Some counters are read-only (LMC).
+ * All counters belong to PCI devices, the devices may have additional
+ * drivers but we assume we are the only user of the counter registers.
+ * We map the whole PCI BAR so we must be careful to forbid access to
+ * addresses that contain neither counters nor counter control registers.
+ */
+
+void thunder_uncore_read(struct perf_event *event)
+{
+ struct thunder_uncore *uncore = to_uncore(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ struct thunder_uncore_unit *unit;
+ u64 prev, delta, new = 0;
+
+ node = get_node(hwc->config, uncore);
+
+ /* read counter values from all units on the node */
+ list_for_each_entry(unit, &node->unit_list, entry)
+ new += readq(hwc->event_base + unit->map);
+
+ prev = local64_read(&hwc->prev_count);
+ local64_set(&hwc->prev_count, new);
+ delta = new - prev;
+ local64_add(delta, &event->count);
+}
+
+int thunder_uncore_add(struct perf_event *event, int flags, u64 config_base,
+ u64 event_base)
+{
+ struct thunder_uncore *uncore = to_uncore(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ int id;
+
+ node = get_node(hwc->config, uncore);
+ id = get_id(hwc->config);
+
+ if (!cmpxchg(&node->events[id], NULL, event))
+ hwc->idx = id;
+
+ if (hwc->idx == -1)
+ return -EBUSY;
+
+ hwc->config_base = config_base;
+ hwc->event_base = event_base;
+ hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+ if (flags & PERF_EF_START)
+ uncore->pmu.start(event, PERF_EF_RELOAD);
+
+ return 0;
+}
+
+void thunder_uncore_del(struct perf_event *event, int flags)
+{
+ struct thunder_uncore *uncore = to_uncore(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ int i;
+
+ event->pmu->stop(event, PERF_EF_UPDATE);
+
+ /*
+ * For programmable counters we need to check where we installed it.
+ * To keep this function generic always test the more complicated
+ * case (free running counters won't need the loop).
+ */
+ node = get_node(hwc->config, uncore);
+ for (i = 0; i < node->num_counters; i++) {
+ if (cmpxchg(&node->events[i], event, NULL) == event)
+ break;
+ }
+ hwc->idx = -1;
+}
+
+void thunder_uncore_start(struct perf_event *event, int flags)
+{
+ struct thunder_uncore *uncore = to_uncore(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ struct thunder_uncore_unit *unit;
+ u64 new = 0;
+
+ /* read counter values from all units on the node */
+ node = get_node(hwc->config, uncore);
+ list_for_each_entry(unit, &node->unit_list, entry)
+ new += readq(hwc->event_base + unit->map);
+ local64_set(&hwc->prev_count, new);
+
+ hwc->state = 0;
+ perf_event_update_userpage(event);
+}
+
+void thunder_uncore_stop(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ hwc->state |= PERF_HES_STOPPED;
+
+ if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
+ thunder_uncore_read(event);
+ hwc->state |= PERF_HES_UPTODATE;
+ }
+}
+
+int thunder_uncore_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ struct thunder_uncore *uncore;
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /* we do not support sampling */
+ if (is_sampling_event(event))
+ return -EINVAL;
+
+ /* counters do not have these bits */
+ if (event->attr.exclude_user ||
+ event->attr.exclude_kernel ||
+ event->attr.exclude_host ||
+ event->attr.exclude_guest ||
+ event->attr.exclude_hv ||
+ event->attr.exclude_idle)
+ return -EINVAL;
+
+ uncore = to_uncore(event->pmu);
+ if (!uncore)
+ return -ENODEV;
+ if (!uncore->event_valid(event->attr.config & UNCORE_EVENT_ID_MASK))
+ return -EINVAL;
+
+ /* check NUMA node */
+ node = get_node(event->attr.config, uncore);
+ if (!node) {
+ pr_debug("Invalid NUMA node selected\n");
+ return -EINVAL;
+ }
+
+ hwc->config = event->attr.config;
+ hwc->idx = -1;
+ return 0;
+}
+
+static ssize_t thunder_uncore_attr_show_cpumask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct pmu *pmu = dev_get_drvdata(dev);
+ struct thunder_uncore *uncore =
+ container_of(pmu, struct thunder_uncore, pmu);
+
+ return cpumap_print_to_pagebuf(true, buf, &uncore->active_mask);
+}
+static DEVICE_ATTR(cpumask, S_IRUGO, thunder_uncore_attr_show_cpumask, NULL);
+
+static struct attribute *thunder_uncore_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+struct attribute_group thunder_uncore_attr_group = {
+ .attrs = thunder_uncore_attrs,
+};
+
+ssize_t thunder_events_sysfs_show(struct device *dev,
+ struct device_attribute *attr,
+ char *page)
+{
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, struct perf_pmu_events_attr, attr);
+
+ if (pmu_attr->event_str)
+ return sprintf(page, "%s", pmu_attr->event_str);
+
+ return 0;
+}
+
+/* node attribute depending on number of NUMA nodes */
+static ssize_t node_show(struct device *dev, struct device_attribute *attr,
+ char *page)
+{
+ if (NODES_SHIFT)
+ return sprintf(page, "config:16-%d\n", 16 + NODES_SHIFT - 1);
+ else
+ return sprintf(page, "config:16\n");
+}
+
+struct device_attribute format_attr_node = __ATTR_RO(node);
+
+/*
+ * Thunder uncore events are independent from CPUs. Provide a cpumask
+ * nevertheless to prevent perf from adding the event per-cpu and just
+ * set the mask to one online CPU. Use the same cpumask for all uncore
+ * devices.
+ *
+ * There is a performance penalty for accessing a device from a CPU on
+ * another socket, but we do not care (yet).
+ */
+static int thunder_uncore_offline_cpu(unsigned int old_cpu, struct hlist_node *node)
+{
+ struct thunder_uncore *uncore = hlist_entry_safe(node, struct thunder_uncore, node);
+ int new_cpu;
+
+ if (!cpumask_test_and_clear_cpu(old_cpu, &uncore->active_mask))
+ return 0;
+ new_cpu = cpumask_any_but(cpu_online_mask, old_cpu);
+ if (new_cpu >= nr_cpu_ids)
+ return 0;
+ perf_pmu_migrate_context(&uncore->pmu, old_cpu, new_cpu);
+ cpumask_set_cpu(new_cpu, &uncore->active_mask);
+ return 0;
+}
+
+static struct thunder_uncore_node * __init alloc_node(struct thunder_uncore *uncore,
+ int node_id, int counters)
+{
+ struct thunder_uncore_node *node;
+
+ node = kzalloc(sizeof(*node), GFP_KERNEL);
+ if (!node)
+ return NULL;
+ node->num_counters = counters;
+ INIT_LIST_HEAD(&node->unit_list);
+ return node;
+}
+
+int __init thunder_uncore_setup(struct thunder_uncore *uncore, int device_id,
+ struct pmu *pmu, int counters)
+{
+ unsigned int vendor_id = PCI_VENDOR_ID_CAVIUM;
+ struct thunder_uncore_unit *unit, *tmp;
+ struct thunder_uncore_node *node;
+ struct pci_dev *pdev = NULL;
+ int ret, node_id, found = 0;
+
+ /* detect PCI devices */
+ while ((pdev = pci_get_device(vendor_id, device_id, pdev))) {
+ if (!pdev)
+ break;
+
+ node_id = dev_to_node(&pdev->dev);
+
+ /* allocate node if necessary */
+ if (!uncore->nodes[node_id])
+ uncore->nodes[node_id] = alloc_node(uncore, node_id, counters);
+
+ node = uncore->nodes[node_id];
+ if (!node) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ unit = kzalloc(sizeof(*unit), GFP_KERNEL);
+ if (!unit) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ unit->pdev = pdev;
+ unit->map = ioremap(pci_resource_start(pdev, 0),
+ pci_resource_len(pdev, 0));
+ list_add(&unit->entry, &node->unit_list);
+ node->nr_units++;
+ found++;
+ }
+
+ if (!found)
+ return -ENODEV;
+
+ cpuhp_state_add_instance_nocalls(CPUHP_AP_UNCORE_CAVIUM_ONLINE,
+ &uncore->node);
+
+ /*
+ * perf PMU is CPU dependent in difference to our uncore devices.
+ * Just pick a CPU and migrate away if it goes offline.
+ */
+ cpumask_set_cpu(smp_processor_id(), &uncore->active_mask);
+
+ uncore->pmu = *pmu;
+ ret = perf_pmu_register(&uncore->pmu, uncore->pmu.name, -1);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ node_id = 0;
+ while (uncore->nodes[node_id]) {
+ node = uncore->nodes[node_id];
+
+ list_for_each_entry_safe(unit, tmp, &node->unit_list, entry) {
+ if (unit->pdev) {
+ if (unit->map)
+ iounmap(unit->map);
+ pci_dev_put(unit->pdev);
+ }
+ kfree(unit);
+ }
+ kfree(uncore->nodes[node_id]);
+ node_id++;
+ }
+ return ret;
+}
+
+static int __init thunder_uncore_init(void)
+{
+ unsigned long implementor = read_cpuid_implementor();
+ int ret;
+
+ if (implementor != ARM_CPU_IMP_CAVIUM)
+ return -ENODEV;
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_UNCORE_CAVIUM_ONLINE,
+ "AP_PERF_UNCORE_CAVIUM_ONLINE", NULL,
+ thunder_uncore_offline_cpu);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+late_initcall(thunder_uncore_init);
diff --git a/drivers/perf/uncore/uncore_cavium.h b/drivers/perf/uncore/uncore_cavium.h
new file mode 100644
index 0000000..b5d64b5
--- /dev/null
+++ b/drivers/perf/uncore/uncore_cavium.h
@@ -0,0 +1,71 @@
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/perf_event.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "thunderx_uncore: " fmt
+
+#define to_uncore(x) container_of((x), struct thunder_uncore, pmu)
+
+#define UNCORE_EVENT_ID_MASK 0xffff
+#define UNCORE_EVENT_ID_SHIFT 16
+
+/* maximum number of parallel hardware counters for all uncore parts */
+#define MAX_COUNTERS 64
+
+struct thunder_uncore_unit {
+ struct list_head entry;
+ void __iomem *map;
+ struct pci_dev *pdev;
+};
+
+struct thunder_uncore_node {
+ int nr_units;
+ int num_counters;
+ struct list_head unit_list;
+ struct perf_event *events[MAX_COUNTERS];
+};
+
+/* generic uncore struct for different pmu types */
+struct thunder_uncore {
+ struct pmu pmu;
+ bool (*event_valid)(u64);
+ struct hlist_node node;
+ struct thunder_uncore_node *nodes[MAX_NUMNODES];
+ cpumask_t active_mask;
+};
+
+#define UC_EVENT_ENTRY(_name, _id) \
+ &((struct perf_pmu_events_attr[]) { \
+ { \
+ __ATTR(_name, S_IRUGO, thunder_events_sysfs_show, NULL), \
+ 0, \
+ "event=" __stringify(_id), \
+ } \
+ })[0].attr.attr
+
+static inline struct thunder_uncore_node *get_node(u64 config,
+ struct thunder_uncore *uncore)
+{
+ return uncore->nodes[config >> UNCORE_EVENT_ID_SHIFT];
+}
+
+#define get_id(config) (config & UNCORE_EVENT_ID_MASK)
+
+extern struct attribute_group thunder_uncore_attr_group;
+extern struct device_attribute format_attr_node;
+
+/* Prototypes */
+void thunder_uncore_read(struct perf_event *event);
+int thunder_uncore_add(struct perf_event *event, int flags, u64 config_base,
+ u64 event_base);
+void thunder_uncore_del(struct perf_event *event, int flags);
+void thunder_uncore_start(struct perf_event *event, int flags);
+void thunder_uncore_stop(struct perf_event *event, int flags);
+int thunder_uncore_event_init(struct perf_event *event);
+int thunder_uncore_setup(struct thunder_uncore *uncore, int id,
+ struct pmu *pmu, int counters);
+ssize_t thunder_events_sysfs_show(struct device *dev,
+ struct device_attribute *attr,
+ char *page);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 9b207a8..370a7a2 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -117,6 +117,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
+ CPUHP_AP_UNCORE_CAVIUM_ONLINE,
CPUHP_AP_WORKQUEUE_ONLINE,
CPUHP_AP_RCUTREE_ONLINE,
CPUHP_AP_NOTIFY_ONLINE,
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/5] arm64: perf: Cavium ThunderX L2C TAD uncore support
From: Jan Glauber @ 2016-10-20 9:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476955841-27898-1-git-send-email-jglauber@cavium.com>
Support counters of the L2 Cache tag and data units.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
drivers/perf/uncore/Makefile | 3 +-
drivers/perf/uncore/uncore_cavium.c | 1 +
drivers/perf/uncore/uncore_cavium.h | 1 +
drivers/perf/uncore/uncore_cavium_l2c_tad.c | 379 ++++++++++++++++++++++++++++
4 files changed, 383 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/uncore/uncore_cavium_l2c_tad.c
diff --git a/drivers/perf/uncore/Makefile b/drivers/perf/uncore/Makefile
index 6130e18..90850a2 100644
--- a/drivers/perf/uncore/Makefile
+++ b/drivers/perf/uncore/Makefile
@@ -1 +1,2 @@
-obj-$(CONFIG_UNCORE_PMU_CAVIUM) += uncore_cavium.o
+obj-$(CONFIG_UNCORE_PMU_CAVIUM) += uncore_cavium.o \
+ uncore_cavium_l2c_tad.o
diff --git a/drivers/perf/uncore/uncore_cavium.c b/drivers/perf/uncore/uncore_cavium.c
index a7b4277..15e1aec 100644
--- a/drivers/perf/uncore/uncore_cavium.c
+++ b/drivers/perf/uncore/uncore_cavium.c
@@ -346,6 +346,7 @@ static int __init thunder_uncore_init(void)
if (ret)
return ret;
+ thunder_uncore_l2c_tad_setup();
return 0;
}
late_initcall(thunder_uncore_init);
diff --git a/drivers/perf/uncore/uncore_cavium.h b/drivers/perf/uncore/uncore_cavium.h
index b5d64b5..70a8214 100644
--- a/drivers/perf/uncore/uncore_cavium.h
+++ b/drivers/perf/uncore/uncore_cavium.h
@@ -69,3 +69,4 @@ int thunder_uncore_setup(struct thunder_uncore *uncore, int id,
ssize_t thunder_events_sysfs_show(struct device *dev,
struct device_attribute *attr,
char *page);
+int thunder_uncore_l2c_tad_setup(void);
diff --git a/drivers/perf/uncore/uncore_cavium_l2c_tad.c b/drivers/perf/uncore/uncore_cavium_l2c_tad.c
new file mode 100644
index 0000000..2de37b2
--- /dev/null
+++ b/drivers/perf/uncore/uncore_cavium_l2c_tad.c
@@ -0,0 +1,379 @@
+/*
+ * Cavium Thunder uncore PMU support,
+ * L2 Cache tag-and-data-units (L2C TAD) counters.
+ *
+ * Copyright 2016 Cavium Inc.
+ * Author: Jan Glauber <jan.glauber@cavium.com>
+ */
+
+#include <linux/perf_event.h>
+#include <linux/slab.h>
+
+#include "uncore_cavium.h"
+
+struct thunder_uncore *thunder_uncore_l2c_tad;
+
+#define L2C_TAD_NR_COUNTERS 4
+#define L2C_TAD_PRF_OFFSET 0x10000
+#define L2C_TAD_PFC_OFFSET 0x10100
+
+/*
+ * Counters are selected via L2C_TAD(x)_PRF:
+ *
+ * 63 32
+ * +---------------------------------------+
+ * | Reserved |
+ * +---------------------------------------+
+ * | CNT3SEL | CNT2SEL | CNT1SEL | CNT0SEL |
+ * +---------------------------------------+
+ * 31 24 16 8 0
+ *
+ * config_base contains the offset of the selected CNTxSEL in the mapped BAR.
+ *
+ * Counters are read via L2C_TAD(x)_PFC(0..3).
+ * event_base contains the associated address to read the counter.
+ */
+
+/* L2C TAD event list */
+#define L2C_TAD_EVENTS_DISABLED 0x00
+#define L2C_TAD_EVENT_L2T_HIT 0x01
+#define L2C_TAD_EVENT_L2T_MISS 0x02
+#define L2C_TAD_EVENT_L2T_NOALLOC 0x03
+#define L2C_TAD_EVENT_L2_VIC 0x04
+#define L2C_TAD_EVENT_SC_FAIL 0x05
+#define L2C_TAD_EVENT_SC_PASS 0x06
+#define L2C_TAD_EVENT_LFB_OCC 0x07
+#define L2C_TAD_EVENT_WAIT_LFB 0x08
+#define L2C_TAD_EVENT_WAIT_VAB 0x09
+#define L2C_TAD_EVENT_OPEN_CCPI 0x0a
+#define L2C_TAD_EVENT_LOOKUP 0x40
+#define L2C_TAD_EVENT_LOOKUP_XMC_LCL 0x41
+#define L2C_TAD_EVENT_LOOKUP_XMC_RMT 0x42
+#define L2C_TAD_EVENT_LOOKUP_MIB 0x43
+#define L2C_TAD_EVENT_LOOKUP_ALL 0x44
+#define L2C_TAD_EVENT_TAG_ALC_HIT 0x48
+#define L2C_TAD_EVENT_TAG_ALC_MISS 0x49
+#define L2C_TAD_EVENT_TAG_ALC_NALC 0x4a
+#define L2C_TAD_EVENT_TAG_NALC_HIT 0x4b
+#define L2C_TAD_EVENT_TAG_NALC_MISS 0x4c
+#define L2C_TAD_EVENT_LMC_WR 0x4e
+#define L2C_TAD_EVENT_LMC_SBLKDTY 0x4f
+#define L2C_TAD_EVENT_TAG_ALC_RTG_HIT 0x50
+#define L2C_TAD_EVENT_TAG_ALC_RTG_HITE 0x51
+#define L2C_TAD_EVENT_TAG_ALC_RTG_HITS 0x52
+#define L2C_TAD_EVENT_TAG_ALC_RTG_MISS 0x53
+#define L2C_TAD_EVENT_TAG_NALC_RTG_HIT 0x54
+#define L2C_TAD_EVENT_TAG_NALC_RTG_MISS 0x55
+#define L2C_TAD_EVENT_TAG_NALC_RTG_HITE 0x56
+#define L2C_TAD_EVENT_TAG_NALC_RTG_HITS 0x57
+#define L2C_TAD_EVENT_TAG_ALC_LCL_EVICT 0x58
+#define L2C_TAD_EVENT_TAG_ALC_LCL_CLNVIC 0x59
+#define L2C_TAD_EVENT_TAG_ALC_LCL_DTYVIC 0x5a
+#define L2C_TAD_EVENT_TAG_ALC_RMT_EVICT 0x5b
+#define L2C_TAD_EVENT_TAG_ALC_RMT_VIC 0x5c
+#define L2C_TAD_EVENT_RTG_ALC 0x5d
+#define L2C_TAD_EVENT_RTG_ALC_HIT 0x5e
+#define L2C_TAD_EVENT_RTG_ALC_HITWB 0x5f
+#define L2C_TAD_EVENT_STC_TOTAL 0x60
+#define L2C_TAD_EVENT_STC_TOTAL_FAIL 0x61
+#define L2C_TAD_EVENT_STC_RMT 0x62
+#define L2C_TAD_EVENT_STC_RMT_FAIL 0x63
+#define L2C_TAD_EVENT_STC_LCL 0x64
+#define L2C_TAD_EVENT_STC_LCL_FAIL 0x65
+#define L2C_TAD_EVENT_OCI_RTG_WAIT 0x68
+#define L2C_TAD_EVENT_OCI_FWD_CYC_HIT 0x69
+#define L2C_TAD_EVENT_OCI_FWD_RACE 0x6a
+#define L2C_TAD_EVENT_OCI_HAKS 0x6b
+#define L2C_TAD_EVENT_OCI_FLDX_TAG_E_NODAT 0x6c
+#define L2C_TAD_EVENT_OCI_FLDX_TAG_E_DAT 0x6d
+#define L2C_TAD_EVENT_OCI_RLDD 0x6e
+#define L2C_TAD_EVENT_OCI_RLDD_PEMD 0x6f
+#define L2C_TAD_EVENT_OCI_RRQ_DAT_CNT 0x70
+#define L2C_TAD_EVENT_OCI_RRQ_DAT_DMASK 0x71
+#define L2C_TAD_EVENT_OCI_RSP_DAT_CNT 0x72
+#define L2C_TAD_EVENT_OCI_RSP_DAT_DMASK 0x73
+#define L2C_TAD_EVENT_OCI_RSP_DAT_VICD_CNT 0x74
+#define L2C_TAD_EVENT_OCI_RSP_DAT_VICD_DMASK 0x75
+#define L2C_TAD_EVENT_OCI_RTG_ALC_EVICT 0x76
+#define L2C_TAD_EVENT_OCI_RTG_ALC_VIC 0x77
+#define L2C_TAD_EVENT_QD0_IDX 0x80
+#define L2C_TAD_EVENT_QD0_RDAT 0x81
+#define L2C_TAD_EVENT_QD0_BNKS 0x82
+#define L2C_TAD_EVENT_QD0_WDAT 0x83
+#define L2C_TAD_EVENT_QD1_IDX 0x90
+#define L2C_TAD_EVENT_QD1_RDAT 0x91
+#define L2C_TAD_EVENT_QD1_BNKS 0x92
+#define L2C_TAD_EVENT_QD1_WDAT 0x93
+#define L2C_TAD_EVENT_QD2_IDX 0xa0
+#define L2C_TAD_EVENT_QD2_RDAT 0xa1
+#define L2C_TAD_EVENT_QD2_BNKS 0xa2
+#define L2C_TAD_EVENT_QD2_WDAT 0xa3
+#define L2C_TAD_EVENT_QD3_IDX 0xb0
+#define L2C_TAD_EVENT_QD3_RDAT 0xb1
+#define L2C_TAD_EVENT_QD3_BNKS 0xb2
+#define L2C_TAD_EVENT_QD3_WDAT 0xb3
+#define L2C_TAD_EVENT_QD4_IDX 0xc0
+#define L2C_TAD_EVENT_QD4_RDAT 0xc1
+#define L2C_TAD_EVENT_QD4_BNKS 0xc2
+#define L2C_TAD_EVENT_QD4_WDAT 0xc3
+#define L2C_TAD_EVENT_QD5_IDX 0xd0
+#define L2C_TAD_EVENT_QD5_RDAT 0xd1
+#define L2C_TAD_EVENT_QD5_BNKS 0xd2
+#define L2C_TAD_EVENT_QD5_WDAT 0xd3
+#define L2C_TAD_EVENT_QD6_IDX 0xe0
+#define L2C_TAD_EVENT_QD6_RDAT 0xe1
+#define L2C_TAD_EVENT_QD6_BNKS 0xe2
+#define L2C_TAD_EVENT_QD6_WDAT 0xe3
+#define L2C_TAD_EVENT_QD7_IDX 0xf0
+#define L2C_TAD_EVENT_QD7_RDAT 0xf1
+#define L2C_TAD_EVENT_QD7_BNKS 0xf2
+#define L2C_TAD_EVENT_QD7_WDAT 0xf3
+
+static void thunder_uncore_start_l2c_tad(struct perf_event *event, int flags)
+{
+ struct thunder_uncore *uncore = to_uncore(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ struct thunder_uncore_unit *unit;
+ int id;
+
+ node = get_node(hwc->config, uncore);
+ id = get_id(hwc->config);
+
+ /* reset counter values to zero */
+ if (flags & PERF_EF_RELOAD)
+ list_for_each_entry(unit, &node->unit_list, entry)
+ writeq(0, hwc->event_base + unit->map);
+
+ /* start counters on all units on the node */
+ list_for_each_entry(unit, &node->unit_list, entry)
+ writeb(id, hwc->config_base + unit->map);
+
+ hwc->state = 0;
+ perf_event_update_userpage(event);
+}
+
+static void thunder_uncore_stop_l2c_tad(struct perf_event *event, int flags)
+{
+ struct thunder_uncore *uncore = to_uncore(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ struct thunder_uncore_unit *unit;
+
+ node = get_node(hwc->config, uncore);
+
+ /* disable counters for all units on the node */
+ list_for_each_entry(unit, &node->unit_list, entry)
+ writeb(L2C_TAD_EVENTS_DISABLED, hwc->config_base + unit->map);
+ hwc->state |= PERF_HES_STOPPED;
+
+ if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
+ thunder_uncore_read(event);
+ hwc->state |= PERF_HES_UPTODATE;
+ }
+}
+
+static int thunder_uncore_add_l2c_tad(struct perf_event *event, int flags)
+{
+ struct thunder_uncore *uncore = to_uncore(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ struct thunder_uncore_node *node;
+ int i;
+
+ node = get_node(hwc->config, uncore);
+
+ /* take the first available counter */
+ for (i = 0; i < node->num_counters; i++) {
+ if (!cmpxchg(&node->events[i], NULL, event)) {
+ hwc->idx = i;
+ break;
+ }
+ }
+
+ if (hwc->idx == -1)
+ return -EBUSY;
+
+ /* see comment at beginning of file */
+ hwc->config_base = L2C_TAD_PRF_OFFSET + hwc->idx;
+ hwc->event_base = L2C_TAD_PFC_OFFSET + hwc->idx * sizeof(u64);
+
+ hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+ if (flags & PERF_EF_START)
+ thunder_uncore_start(event, PERF_EF_RELOAD);
+ return 0;
+}
+
+PMU_FORMAT_ATTR(event, "config:0-7");
+
+static struct attribute *thunder_l2c_tad_format_attr[] = {
+ &format_attr_event.attr,
+ &format_attr_node.attr,
+ NULL,
+};
+
+static struct attribute_group thunder_l2c_tad_format_group = {
+ .name = "format",
+ .attrs = thunder_l2c_tad_format_attr,
+};
+
+static struct attribute *thunder_l2c_tad_events_attr[] = {
+ UC_EVENT_ENTRY(l2t_hit, L2C_TAD_EVENT_L2T_HIT),
+ UC_EVENT_ENTRY(l2t_miss, L2C_TAD_EVENT_L2T_MISS),
+ UC_EVENT_ENTRY(l2t_noalloc, L2C_TAD_EVENT_L2T_NOALLOC),
+ UC_EVENT_ENTRY(l2_vic, L2C_TAD_EVENT_L2_VIC),
+ UC_EVENT_ENTRY(sc_fail, L2C_TAD_EVENT_SC_FAIL),
+ UC_EVENT_ENTRY(sc_pass, L2C_TAD_EVENT_SC_PASS),
+ UC_EVENT_ENTRY(lfb_occ, L2C_TAD_EVENT_LFB_OCC),
+ UC_EVENT_ENTRY(wait_lfb, L2C_TAD_EVENT_WAIT_LFB),
+ UC_EVENT_ENTRY(wait_vab, L2C_TAD_EVENT_WAIT_VAB),
+ UC_EVENT_ENTRY(open_ccpi, L2C_TAD_EVENT_OPEN_CCPI),
+ UC_EVENT_ENTRY(lookup, L2C_TAD_EVENT_LOOKUP),
+ UC_EVENT_ENTRY(lookup_xmc_lcl, L2C_TAD_EVENT_LOOKUP_XMC_LCL),
+ UC_EVENT_ENTRY(lookup_xmc_rmt, L2C_TAD_EVENT_LOOKUP_XMC_RMT),
+ UC_EVENT_ENTRY(lookup_mib, L2C_TAD_EVENT_LOOKUP_MIB),
+ UC_EVENT_ENTRY(lookup_all, L2C_TAD_EVENT_LOOKUP_ALL),
+ UC_EVENT_ENTRY(tag_alc_hit, L2C_TAD_EVENT_TAG_ALC_HIT),
+ UC_EVENT_ENTRY(tag_alc_miss, L2C_TAD_EVENT_TAG_ALC_MISS),
+ UC_EVENT_ENTRY(tag_alc_nalc, L2C_TAD_EVENT_TAG_ALC_NALC),
+ UC_EVENT_ENTRY(tag_nalc_hit, L2C_TAD_EVENT_TAG_NALC_HIT),
+ UC_EVENT_ENTRY(tag_nalc_miss, L2C_TAD_EVENT_TAG_NALC_MISS),
+ UC_EVENT_ENTRY(lmc_wr, L2C_TAD_EVENT_LMC_WR),
+ UC_EVENT_ENTRY(lmc_sblkdty, L2C_TAD_EVENT_LMC_SBLKDTY),
+ UC_EVENT_ENTRY(tag_alc_rtg_hit, L2C_TAD_EVENT_TAG_ALC_RTG_HIT),
+ UC_EVENT_ENTRY(tag_alc_rtg_hite, L2C_TAD_EVENT_TAG_ALC_RTG_HITE),
+ UC_EVENT_ENTRY(tag_alc_rtg_hits, L2C_TAD_EVENT_TAG_ALC_RTG_HITS),
+ UC_EVENT_ENTRY(tag_alc_rtg_miss, L2C_TAD_EVENT_TAG_ALC_RTG_MISS),
+ UC_EVENT_ENTRY(tag_alc_nalc_rtg_hit, L2C_TAD_EVENT_TAG_NALC_RTG_HIT),
+ UC_EVENT_ENTRY(tag_nalc_rtg_miss, L2C_TAD_EVENT_TAG_NALC_RTG_MISS),
+ UC_EVENT_ENTRY(tag_nalc_rtg_hite, L2C_TAD_EVENT_TAG_NALC_RTG_HITE),
+ UC_EVENT_ENTRY(tag_nalc_rtg_hits, L2C_TAD_EVENT_TAG_NALC_RTG_HITS),
+ UC_EVENT_ENTRY(tag_alc_lcl_evict, L2C_TAD_EVENT_TAG_ALC_LCL_EVICT),
+ UC_EVENT_ENTRY(tag_alc_lcl_clnvic, L2C_TAD_EVENT_TAG_ALC_LCL_CLNVIC),
+ UC_EVENT_ENTRY(tag_alc_lcl_dtyvic, L2C_TAD_EVENT_TAG_ALC_LCL_DTYVIC),
+ UC_EVENT_ENTRY(tag_alc_rmt_evict, L2C_TAD_EVENT_TAG_ALC_RMT_EVICT),
+ UC_EVENT_ENTRY(tag_alc_rmt_vic, L2C_TAD_EVENT_TAG_ALC_RMT_VIC),
+ UC_EVENT_ENTRY(rtg_alc, L2C_TAD_EVENT_RTG_ALC),
+ UC_EVENT_ENTRY(rtg_alc_hit, L2C_TAD_EVENT_RTG_ALC_HIT),
+ UC_EVENT_ENTRY(rtg_alc_hitwb, L2C_TAD_EVENT_RTG_ALC_HITWB),
+ UC_EVENT_ENTRY(stc_total, L2C_TAD_EVENT_STC_TOTAL),
+ UC_EVENT_ENTRY(stc_total_fail, L2C_TAD_EVENT_STC_TOTAL_FAIL),
+ UC_EVENT_ENTRY(stc_rmt, L2C_TAD_EVENT_STC_RMT),
+ UC_EVENT_ENTRY(stc_rmt_fail, L2C_TAD_EVENT_STC_RMT_FAIL),
+ UC_EVENT_ENTRY(stc_lcl, L2C_TAD_EVENT_STC_LCL),
+ UC_EVENT_ENTRY(stc_lcl_fail, L2C_TAD_EVENT_STC_LCL_FAIL),
+ UC_EVENT_ENTRY(oci_rtg_wait, L2C_TAD_EVENT_OCI_RTG_WAIT),
+ UC_EVENT_ENTRY(oci_fwd_cyc_hit, L2C_TAD_EVENT_OCI_FWD_CYC_HIT),
+ UC_EVENT_ENTRY(oci_fwd_race, L2C_TAD_EVENT_OCI_FWD_RACE),
+ UC_EVENT_ENTRY(oci_haks, L2C_TAD_EVENT_OCI_HAKS),
+ UC_EVENT_ENTRY(oci_fldx_tag_e_nodat, L2C_TAD_EVENT_OCI_FLDX_TAG_E_NODAT),
+ UC_EVENT_ENTRY(oci_fldx_tag_e_dat, L2C_TAD_EVENT_OCI_FLDX_TAG_E_DAT),
+ UC_EVENT_ENTRY(oci_rldd, L2C_TAD_EVENT_OCI_RLDD),
+ UC_EVENT_ENTRY(oci_rldd_pemd, L2C_TAD_EVENT_OCI_RLDD_PEMD),
+ UC_EVENT_ENTRY(oci_rrq_dat_cnt, L2C_TAD_EVENT_OCI_RRQ_DAT_CNT),
+ UC_EVENT_ENTRY(oci_rrq_dat_dmask, L2C_TAD_EVENT_OCI_RRQ_DAT_DMASK),
+ UC_EVENT_ENTRY(oci_rsp_dat_cnt, L2C_TAD_EVENT_OCI_RSP_DAT_CNT),
+ UC_EVENT_ENTRY(oci_rsp_dat_dmaks, L2C_TAD_EVENT_OCI_RSP_DAT_DMASK),
+ UC_EVENT_ENTRY(oci_rsp_dat_vicd_cnt, L2C_TAD_EVENT_OCI_RSP_DAT_VICD_CNT),
+ UC_EVENT_ENTRY(oci_rsp_dat_vicd_dmask, L2C_TAD_EVENT_OCI_RSP_DAT_VICD_DMASK),
+ UC_EVENT_ENTRY(oci_rtg_alc_evict, L2C_TAD_EVENT_OCI_RTG_ALC_EVICT),
+ UC_EVENT_ENTRY(oci_rtg_alc_vic, L2C_TAD_EVENT_OCI_RTG_ALC_VIC),
+ UC_EVENT_ENTRY(qd0_idx, L2C_TAD_EVENT_QD0_IDX),
+ UC_EVENT_ENTRY(qd0_rdat, L2C_TAD_EVENT_QD0_RDAT),
+ UC_EVENT_ENTRY(qd0_bnks, L2C_TAD_EVENT_QD0_BNKS),
+ UC_EVENT_ENTRY(qd0_wdat, L2C_TAD_EVENT_QD0_WDAT),
+ UC_EVENT_ENTRY(qd1_idx, L2C_TAD_EVENT_QD1_IDX),
+ UC_EVENT_ENTRY(qd1_rdat, L2C_TAD_EVENT_QD1_RDAT),
+ UC_EVENT_ENTRY(qd1_bnks, L2C_TAD_EVENT_QD1_BNKS),
+ UC_EVENT_ENTRY(qd1_wdat, L2C_TAD_EVENT_QD1_WDAT),
+ UC_EVENT_ENTRY(qd2_idx, L2C_TAD_EVENT_QD2_IDX),
+ UC_EVENT_ENTRY(qd2_rdat, L2C_TAD_EVENT_QD2_RDAT),
+ UC_EVENT_ENTRY(qd2_bnks, L2C_TAD_EVENT_QD2_BNKS),
+ UC_EVENT_ENTRY(qd2_wdat, L2C_TAD_EVENT_QD2_WDAT),
+ UC_EVENT_ENTRY(qd3_idx, L2C_TAD_EVENT_QD3_IDX),
+ UC_EVENT_ENTRY(qd3_rdat, L2C_TAD_EVENT_QD3_RDAT),
+ UC_EVENT_ENTRY(qd3_bnks, L2C_TAD_EVENT_QD3_BNKS),
+ UC_EVENT_ENTRY(qd3_wdat, L2C_TAD_EVENT_QD3_WDAT),
+ UC_EVENT_ENTRY(qd4_idx, L2C_TAD_EVENT_QD4_IDX),
+ UC_EVENT_ENTRY(qd4_rdat, L2C_TAD_EVENT_QD4_RDAT),
+ UC_EVENT_ENTRY(qd4_bnks, L2C_TAD_EVENT_QD4_BNKS),
+ UC_EVENT_ENTRY(qd4_wdat, L2C_TAD_EVENT_QD4_WDAT),
+ UC_EVENT_ENTRY(qd5_idx, L2C_TAD_EVENT_QD5_IDX),
+ UC_EVENT_ENTRY(qd5_rdat, L2C_TAD_EVENT_QD5_RDAT),
+ UC_EVENT_ENTRY(qd5_bnks, L2C_TAD_EVENT_QD5_BNKS),
+ UC_EVENT_ENTRY(qd5_wdat, L2C_TAD_EVENT_QD5_WDAT),
+ UC_EVENT_ENTRY(qd6_idx, L2C_TAD_EVENT_QD6_IDX),
+ UC_EVENT_ENTRY(qd6_rdat, L2C_TAD_EVENT_QD6_RDAT),
+ UC_EVENT_ENTRY(qd6_bnks, L2C_TAD_EVENT_QD6_BNKS),
+ UC_EVENT_ENTRY(qd6_wdat, L2C_TAD_EVENT_QD6_WDAT),
+ UC_EVENT_ENTRY(qd7_idx, L2C_TAD_EVENT_QD7_IDX),
+ UC_EVENT_ENTRY(qd7_rdat, L2C_TAD_EVENT_QD7_RDAT),
+ UC_EVENT_ENTRY(qd7_bnks, L2C_TAD_EVENT_QD7_BNKS),
+ UC_EVENT_ENTRY(qd7_wdat, L2C_TAD_EVENT_QD7_WDAT),
+ NULL,
+};
+
+static struct attribute_group thunder_l2c_tad_events_group = {
+ .name = "events",
+ .attrs = thunder_l2c_tad_events_attr,
+};
+
+static const struct attribute_group *thunder_l2c_tad_attr_groups[] = {
+ &thunder_uncore_attr_group,
+ &thunder_l2c_tad_format_group,
+ &thunder_l2c_tad_events_group,
+ NULL,
+};
+
+struct pmu thunder_l2c_tad_pmu = {
+ .name = "thunder_l2c_tad",
+ .task_ctx_nr = perf_sw_context,
+ .event_init = thunder_uncore_event_init,
+ .add = thunder_uncore_add_l2c_tad,
+ .del = thunder_uncore_del,
+ .start = thunder_uncore_start_l2c_tad,
+ .stop = thunder_uncore_stop_l2c_tad,
+ .read = thunder_uncore_read,
+ .attr_groups = thunder_l2c_tad_attr_groups,
+};
+
+static bool event_valid(u64 c)
+{
+ if ((c > 0 &&
+ c <= L2C_TAD_EVENT_OPEN_CCPI) ||
+ (c >= L2C_TAD_EVENT_LOOKUP &&
+ c <= L2C_TAD_EVENT_LOOKUP_ALL) ||
+ (c >= L2C_TAD_EVENT_TAG_ALC_HIT &&
+ c <= L2C_TAD_EVENT_TAG_NALC_MISS) ||
+ (c >= L2C_TAD_EVENT_LMC_WR &&
+ c <= L2C_TAD_EVENT_STC_LCL_FAIL) ||
+ (c >= L2C_TAD_EVENT_OCI_RTG_WAIT &&
+ c <= L2C_TAD_EVENT_OCI_RTG_ALC_VIC) ||
+ /* L2C_TAD_EVENT_QD[0..7] IDX,RDAT,BNKS,WDAT => 0x80 .. 0xf3 */
+ ((c & 0x80) && ((c & 0xf) <= 3)))
+ return true;
+
+ return false;
+}
+
+int __init thunder_uncore_l2c_tad_setup(void)
+{
+ int ret = -ENOMEM;
+
+ thunder_uncore_l2c_tad = kzalloc(sizeof(*thunder_uncore_l2c_tad),
+ GFP_KERNEL);
+ if (!thunder_uncore_l2c_tad)
+ goto fail_nomem;
+
+ ret = thunder_uncore_setup(thunder_uncore_l2c_tad, 0xa02e,
+ &thunder_l2c_tad_pmu, L2C_TAD_NR_COUNTERS);
+ if (ret)
+ goto fail;
+
+ thunder_uncore_l2c_tad->event_valid = event_valid;
+ return 0;
+
+fail:
+ kfree(thunder_uncore_l2c_tad);
+fail_nomem:
+ return ret;
+}
--
1.9.1
^ permalink raw reply related
* [PATCH v3 3/5] arm64: perf: Cavium ThunderX L2C CBC uncore support
From: Jan Glauber @ 2016-10-20 9:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476955841-27898-1-git-send-email-jglauber@cavium.com>
Support counters of the L2 cache crossbar connect.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
drivers/perf/uncore/Makefile | 3 +-
drivers/perf/uncore/uncore_cavium.c | 1 +
drivers/perf/uncore/uncore_cavium.h | 1 +
drivers/perf/uncore/uncore_cavium_l2c_cbc.c | 148 ++++++++++++++++++++++++++++
4 files changed, 152 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/uncore/uncore_cavium_l2c_cbc.c
diff --git a/drivers/perf/uncore/Makefile b/drivers/perf/uncore/Makefile
index 90850a2..d5ef3db 100644
--- a/drivers/perf/uncore/Makefile
+++ b/drivers/perf/uncore/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_UNCORE_PMU_CAVIUM) += uncore_cavium.o \
- uncore_cavium_l2c_tad.o
+ uncore_cavium_l2c_tad.o \
+ uncore_cavium_l2c_cbc.o
diff --git a/drivers/perf/uncore/uncore_cavium.c b/drivers/perf/uncore/uncore_cavium.c
index 15e1aec..051f0fa 100644
--- a/drivers/perf/uncore/uncore_cavium.c
+++ b/drivers/perf/uncore/uncore_cavium.c
@@ -347,6 +347,7 @@ static int __init thunder_uncore_init(void)
return ret;
thunder_uncore_l2c_tad_setup();
+ thunder_uncore_l2c_cbc_setup();
return 0;
}
late_initcall(thunder_uncore_init);
diff --git a/drivers/perf/uncore/uncore_cavium.h b/drivers/perf/uncore/uncore_cavium.h
index 70a8214..91d674a 100644
--- a/drivers/perf/uncore/uncore_cavium.h
+++ b/drivers/perf/uncore/uncore_cavium.h
@@ -70,3 +70,4 @@ ssize_t thunder_events_sysfs_show(struct device *dev,
struct device_attribute *attr,
char *page);
int thunder_uncore_l2c_tad_setup(void);
+int thunder_uncore_l2c_cbc_setup(void);
diff --git a/drivers/perf/uncore/uncore_cavium_l2c_cbc.c b/drivers/perf/uncore/uncore_cavium_l2c_cbc.c
new file mode 100644
index 0000000..4d6c2c4
--- /dev/null
+++ b/drivers/perf/uncore/uncore_cavium_l2c_cbc.c
@@ -0,0 +1,148 @@
+/*
+ * Cavium Thunder uncore PMU support, L2 Cache,
+ * Crossbar connect (CBC) counters.
+ *
+ * Copyright 2016 Cavium Inc.
+ * Author: Jan Glauber <jan.glauber@cavium.com>
+ */
+
+#include <linux/perf_event.h>
+#include <linux/slab.h>
+
+#include "uncore_cavium.h"
+
+struct thunder_uncore *thunder_uncore_l2c_cbc;
+
+/* L2C CBC event list */
+#define L2C_CBC_EVENT_XMC0 0x00
+#define L2C_CBC_EVENT_XMD0 0x08
+#define L2C_CBC_EVENT_RSC0 0x10
+#define L2C_CBC_EVENT_RSD0 0x18
+#define L2C_CBC_EVENT_INV0 0x20
+#define L2C_CBC_EVENT_IOC0 0x28
+#define L2C_CBC_EVENT_IOR0 0x30
+#define L2C_CBC_EVENT_XMC1 0x40
+#define L2C_CBC_EVENT_XMD1 0x48
+#define L2C_CBC_EVENT_RSC1 0x50
+#define L2C_CBC_EVENT_RSD1 0x58
+#define L2C_CBC_EVENT_INV1 0x60
+#define L2C_CBC_EVENT_XMC2 0x80
+#define L2C_CBC_EVENT_XMD2 0x88
+#define L2C_CBC_EVENT_RSC2 0x90
+#define L2C_CBC_EVENT_RSD2 0x98
+
+static int l2c_cbc_events[] = {
+ L2C_CBC_EVENT_XMC0,
+ L2C_CBC_EVENT_XMD0,
+ L2C_CBC_EVENT_RSC0,
+ L2C_CBC_EVENT_RSD0,
+ L2C_CBC_EVENT_INV0,
+ L2C_CBC_EVENT_IOC0,
+ L2C_CBC_EVENT_IOR0,
+ L2C_CBC_EVENT_XMC1,
+ L2C_CBC_EVENT_XMD1,
+ L2C_CBC_EVENT_RSC1,
+ L2C_CBC_EVENT_RSD1,
+ L2C_CBC_EVENT_INV1,
+ L2C_CBC_EVENT_XMC2,
+ L2C_CBC_EVENT_XMD2,
+ L2C_CBC_EVENT_RSC2,
+ L2C_CBC_EVENT_RSD2,
+};
+
+static int thunder_uncore_add_l2c_cbc(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ return thunder_uncore_add(event, flags, 0,
+ l2c_cbc_events[get_id(hwc->config)]);
+}
+
+PMU_FORMAT_ATTR(event, "config:0-4");
+
+static struct attribute *thunder_l2c_cbc_format_attr[] = {
+ &format_attr_event.attr,
+ &format_attr_node.attr,
+ NULL,
+};
+
+static struct attribute_group thunder_l2c_cbc_format_group = {
+ .name = "format",
+ .attrs = thunder_l2c_cbc_format_attr,
+};
+
+static struct attribute *thunder_l2c_cbc_events_attr[] = {
+ UC_EVENT_ENTRY(xmc0, 0),
+ UC_EVENT_ENTRY(xmd0, 1),
+ UC_EVENT_ENTRY(rsc0, 2),
+ UC_EVENT_ENTRY(rsd0, 3),
+ UC_EVENT_ENTRY(inv0, 4),
+ UC_EVENT_ENTRY(ioc0, 5),
+ UC_EVENT_ENTRY(ior0, 6),
+ UC_EVENT_ENTRY(xmc1, 7),
+ UC_EVENT_ENTRY(xmd1, 8),
+ UC_EVENT_ENTRY(rsc1, 9),
+ UC_EVENT_ENTRY(rsd1, 10),
+ UC_EVENT_ENTRY(inv1, 11),
+ UC_EVENT_ENTRY(xmc2, 12),
+ UC_EVENT_ENTRY(xmd2, 13),
+ UC_EVENT_ENTRY(rsc2, 14),
+ UC_EVENT_ENTRY(rsd2, 15),
+ NULL,
+};
+
+static struct attribute_group thunder_l2c_cbc_events_group = {
+ .name = "events",
+ .attrs = thunder_l2c_cbc_events_attr,
+};
+
+static const struct attribute_group *thunder_l2c_cbc_attr_groups[] = {
+ &thunder_uncore_attr_group,
+ &thunder_l2c_cbc_format_group,
+ &thunder_l2c_cbc_events_group,
+ NULL,
+};
+
+struct pmu thunder_l2c_cbc_pmu = {
+ .name = "thunder_l2c_cbc",
+ .task_ctx_nr = perf_sw_context,
+ .event_init = thunder_uncore_event_init,
+ .add = thunder_uncore_add_l2c_cbc,
+ .del = thunder_uncore_del,
+ .start = thunder_uncore_start,
+ .stop = thunder_uncore_stop,
+ .read = thunder_uncore_read,
+ .attr_groups = thunder_l2c_cbc_attr_groups,
+};
+
+static bool event_valid(u64 config)
+{
+ if (config < ARRAY_SIZE(l2c_cbc_events))
+ return true;
+
+ return false;
+}
+
+int __init thunder_uncore_l2c_cbc_setup(void)
+{
+ int ret = -ENOMEM;
+
+ thunder_uncore_l2c_cbc = kzalloc(sizeof(*thunder_uncore_l2c_cbc),
+ GFP_KERNEL);
+ if (!thunder_uncore_l2c_cbc)
+ goto fail_nomem;
+
+ ret = thunder_uncore_setup(thunder_uncore_l2c_cbc, 0xa02f,
+ &thunder_l2c_cbc_pmu,
+ ARRAY_SIZE(l2c_cbc_events));
+ if (ret)
+ goto fail;
+
+ thunder_uncore_l2c_cbc->event_valid = event_valid;
+ return 0;
+
+fail:
+ kfree(thunder_uncore_l2c_cbc);
+fail_nomem:
+ return ret;
+}
--
1.9.1
^ permalink raw reply related
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