* [PATCH v2 3/8] drm/sun4i: tcon: Move SoC specific quirks to a DT matched data structure
From: Maxime Ripard @ 2016-10-20 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-4-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:39AM +0800, Chen-Yu Tsai wrote:
> We already have some differences between the 2 supported SoCs.
> More will be added as we support other SoCs. To avoid bloating
> the probe function with even more conditionals, move the quirks
> to a separate data structure that's tied to the compatible string.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 2/8] drm/sun4i: sun6i-drc: Support DRC on A31 and A31s
From: Maxime Ripard @ 2016-10-20 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-3-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:38AM +0800, Chen-Yu Tsai wrote:
> The A31 and A31s also have the DRC as part of the display pipeline.
> As we know virtually nothing about them, just add compatible strings
> for both SoCs to the stub driver.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Acked-by: Rob Herring <robh@kernel.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [RFC PATCH] net: stmmac: Add OXNAS Glue Driver
From: Neil Armstrong @ 2016-10-20 15:54 UTC (permalink / raw)
To: linux-arm-kernel
Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../devicetree/bindings/net/oxnas-dwmac.txt | 44 ++++++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c | 173 +++++++++++++++++++++
4 files changed, 229 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/oxnas-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
diff --git a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt
new file mode 100644
index 0000000..5d2696c
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt
@@ -0,0 +1,44 @@
+* Oxford Semiconductor OXNAS DWMAC Ethernet controller
+
+The device inherits all the properties of the dwmac/stmmac devices
+described in the file stmmac.txt in the current directory with the
+following changes.
+
+Required properties on all platforms:
+
+- compatible: Depending on the platform this should be one of:
+ - "oxsemi,ox820-dwmac"
+ Additionally "snps,dwmac" and any applicable more
+ detailed version number described in net/stmmac.txt
+ should be used.
+
+- reg: The first register range should be the one of the DWMAC
+ controller.
+
+- clocks: Should contain phandles to the following clocks
+- clock-names: Should contain the following:
+ - "stmmaceth" - see stmmac.txt
+ - "gmac" - peripheral gate clock
+
+- oxsemi,sys-ctrl: a phandle to the system controller syscon node
+
+Example :
+
+etha: ethernet at 40400000 {
+ compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
+ reg = <0x40400000 0x2000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ mac-address = [000000000000]; /* Filled in by U-Boot */
+ phy-mode = "rgmii";
+
+ clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
+ clock-names = "gmac", "stmmaceth";
+ resets = <&reset RESET_MAC>;
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ status = "disabled";
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 3818c5e..27ed913 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -62,6 +62,7 @@ config DWMAC_MESON
tristate "Amlogic Meson dwmac support"
default ARCH_MESON
depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select MFD_SYSCON
help
Support for Ethernet controller on Amlogic Meson SoCs.
@@ -69,6 +70,16 @@ config DWMAC_MESON
the stmmac device driver. This driver is used for Meson6,
Meson8, Meson8b and GXBB SoCs.
+config DWMAC_OXNAS
+ tristate "Oxford Semiconductor OXNAS dwmac support"
+ default ARCH_OXNAS
+ depends on OF && COMMON_CLK && (ARCH_OXNAS || COMPILE_TEST)
+ help
+ Support for Ethernet controller on Oxford Semiconductor OXNAS SoCs.
+
+ This selects the Oxford Semiconductor OXNASSoC glue layer support for
+ the stmmac device driver. This driver is used for OX820.
+
config DWMAC_ROCKCHIP
tristate "Rockchip dwmac support"
default ARCH_ROCKCHIP
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 5d6ece5..8f83a86 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o
obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
+obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o
obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
new file mode 100644
index 0000000..c65f3a6
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
@@ -0,0 +1,173 @@
+/*
+ * Oxford Semiconductor OXNAS DWMAC glue layer
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/stmmac.h>
+
+#include "stmmac_platform.h"
+
+/* System Control regmap offsets */
+#define OXNAS_DWMAC_CTRL_REGOFFSET 0x78
+#define OXNAS_DWMAC_DELAY_REGOFFSET 0x100
+
+/* Control Register */
+#define DWMAC_CKEN_RX_IN 14
+#define DWMAC_CKEN_RXN_OUT 13
+#define DWMAC_CKEN_RX_OUT 12
+#define DWMAC_CKEN_TX_IN 10
+#define DWMAC_CKEN_TXN_OUT 9
+#define DWMAC_CKEN_TX_OUT 8
+#define DWMAC_RX_SOURCE 7
+#define DWMAC_TX_SOURCE 6
+#define DWMAC_LOW_TX_SOURCE 4
+#define DWMAC_AUTO_TX_SOURCE 3
+#define DWMAC_RGMII 2
+#define DWMAC_SIMPLE_MUX 1
+#define DWMAC_CKEN_GTX 0
+
+/* Delay register */
+#define DWMAC_TX_VARDELAY_SHIFT 0
+#define DWMAC_TXN_VARDELAY_SHIFT 8
+#define DWMAC_RX_VARDELAY_SHIFT 16
+#define DWMAC_RXN_VARDELAY_SHIFT 24
+#define DWMAC_TX_VARDELAY(d) ((d) << DWMAC_TX_VARDELAY_SHIFT)
+#define DWMAC_TXN_VARDELAY(d) ((d) << DWMAC_TXN_VARDELAY_SHIFT)
+#define DWMAC_RX_VARDELAY(d) ((d) << DWMAC_RX_VARDELAY_SHIFT)
+#define DWMAC_RXN_VARDELAY(d) ((d) << DWMAC_RXN_VARDELAY_SHIFT)
+
+struct oxnas_dwmac {
+ struct clk *clk;
+ struct regmap *regmap;
+};
+
+static int oxnas_dwmac_init(struct platform_device *pdev, void *priv)
+{
+ struct oxnas_dwmac *dwmac = priv;
+ unsigned int value;
+ int ret;
+
+ /* Reset HW here before changing the glue configuration */
+ ret = device_reset(&pdev->dev);
+ if (ret)
+ return ret;
+
+ clk_prepare_enable(dwmac->clk);
+
+ ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value);
+ if (ret < 0)
+ return ret;
+
+ /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
+ value |= BIT(DWMAC_CKEN_GTX);
+ /* Use simple mux for 25/125 Mhz clock switching */
+ value |= BIT(DWMAC_SIMPLE_MUX);
+ /* set auto switch tx clock source */
+ value |= BIT(DWMAC_AUTO_TX_SOURCE);
+ /* enable tx & rx vardelay */
+ value |= BIT(DWMAC_CKEN_TX_OUT);
+ value |= BIT(DWMAC_CKEN_TXN_OUT);
+ value |= BIT(DWMAC_CKEN_TX_IN);
+ value |= BIT(DWMAC_CKEN_RX_OUT);
+ value |= BIT(DWMAC_CKEN_RXN_OUT);
+ value |= BIT(DWMAC_CKEN_RX_IN);
+ regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value);
+
+ /* set tx & rx vardelay */
+ value = DWMAC_TX_VARDELAY(4);
+ value |= DWMAC_TXN_VARDELAY(2);
+ value |= DWMAC_RX_VARDELAY(10);
+ value |= DWMAC_RXN_VARDELAY(8);
+ regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value);
+
+ return 0;
+}
+
+static void oxnas_dwmac_exit(struct platform_device *pdev, void *priv)
+{
+ struct oxnas_dwmac *dwmac = priv;
+
+ clk_disable_unprepare(dwmac->clk);
+}
+
+static int oxnas_dwmac_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ struct device_node *sysctrl;
+ struct oxnas_dwmac *dwmac;
+ int ret;
+
+ sysctrl = of_parse_phandle(pdev->dev.of_node, "oxsemi,sys-ctrl", 0);
+ if (!sysctrl) {
+ dev_err(&pdev->dev, "failed to get sys-ctrl node\n");
+ return -EINVAL;
+ }
+
+ ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ if (ret)
+ return ret;
+
+ plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return PTR_ERR(plat_dat);
+
+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
+ if (!dwmac)
+ return -ENOMEM;
+
+ dwmac->regmap = syscon_node_to_regmap(sysctrl);
+ if (IS_ERR(dwmac->regmap)) {
+ dev_err(&pdev->dev, "failed to have sysctrl regmap\n");
+ return PTR_ERR(dwmac->regmap);
+ }
+
+ dwmac->clk = devm_clk_get(&pdev->dev, "gmac");
+ if (IS_ERR(dwmac->clk))
+ return PTR_ERR(dwmac->clk);
+
+ plat_dat->bsp_priv = dwmac;
+ plat_dat->init = oxnas_dwmac_init;
+ plat_dat->exit = oxnas_dwmac_exit;
+
+ return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+}
+
+static const struct of_device_id oxnas_dwmac_match[] = {
+ { .compatible = "oxsemi,ox820-dwmac" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, oxnas_dwmac_match);
+
+static struct platform_driver oxnas_dwmac_driver = {
+ .probe = oxnas_dwmac_probe,
+ .remove = stmmac_pltfr_remove,
+ .driver = {
+ .name = "oxnas-dwmac",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = oxnas_dwmac_match,
+ },
+};
+module_platform_driver(oxnas_dwmac_driver);
+
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_DESCRIPTION("Oxford Semiconductor OXNAS DWMAC glue layer");
+MODULE_LICENSE("GPL v2");
--
2.7.0
^ permalink raw reply related
* [linux-sunxi] [PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks
From: Chen-Yu Tsai @ 2016-10-20 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cd4dd81821b8910d40626baab2dbfdabd94b1b98.1476196031.git-series.maxime.ripard@free-electrons.com>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Add the A64 CCU clocks set.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +-
> drivers/clk/sunxi-ng/Kconfig | 11 +-
> drivers/clk/sunxi-ng/Makefile | 1 +-
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 918 +++++++++++-
> drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 72 +-
> include/dt-bindings/clock/sun50i-a64-ccu.h | 134 ++-
> include/dt-bindings/reset/sun50i-a64-ccu.h | 98 +-
> 7 files changed, 1235 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
> create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 3868458a5feb..74d44a4273f2 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,6 +7,7 @@ Required properties :
> - "allwinner,sun8i-a23-ccu"
> - "allwinner,sun8i-a33-ccu"
> - "allwinner,sun8i-h3-ccu"
> + - "allwinner,sun50i-a64-ccu"
>
> - reg: Must contain the registers base address and length
> - clocks: phandle to the oscillators feeding the CCU. Two are needed:
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 1b4c55a53d7a..8454c6e3dd65 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -53,6 +53,17 @@ config SUNXI_CCU_MP
>
> # SoC Drivers
>
> +config SUN50I_A64_CCU
> + bool "Support for the Allwinner A64 CCU"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_NK
> + select SUNXI_CCU_NKM
> + select SUNXI_CCU_NKMP
> + select SUNXI_CCU_NM
> + select SUNXI_CCU_MP
> + select SUNXI_CCU_PHASE
> + default ARM64 && ARCH_SUNXI
> +
> config SUN6I_A31_CCU
> bool "Support for the Allwinner A31/A31s CCU"
> select SUNXI_CCU_DIV
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 106cba27c331..24fbc6e5deb8 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o
> obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
>
> # SoC support
> +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
> obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
> obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
> obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> new file mode 100644
> index 000000000000..c0e96bf6d104
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -0,0 +1,918 @@
> +/*
> + * Copyright (c) 2016 Maxime Ripard. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +#include "ccu_phase.h"
> +
> +#include "ccu-sun50i-a64.h"
> +
> +static struct ccu_nkmp pll_cpux_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 5),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m = _SUNXI_CCU_DIV(0, 2),
> + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
> + .common = {
> + .reg = 0x000,
> + .hw.init = CLK_HW_INIT("pll-cpux",
> + "osc24M",
> + &ccu_nkmp_ops,
> + 0),
> + },
> +};
> +
> +/*
> + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> + * the base (2x, 4x and 8x), and one variable divider (the one true
> + * pll audio).
> + *
> + * We don't have any need for the variable divider for now, so we just
> + * hardcode it to match with the clock names
> + */
> +#define SUN50I_A64_PLL_AUDIO_REG 0x008
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
> + "osc24M", 0x008,
> + 8, 7, /* N */
> + 0, 5, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
> + "osc24M", 0x010,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
> + "osc24M", 0x018,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
> + "osc24M", 0x020,
> + 8, 5, /* N */
> + 4, 2, /* K */
> + 0, 2, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static struct ccu_nk pll_periph0_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 5),
> + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> + .fixed_post_div = 2,
> + .common = {
> + .reg = 0x028,
> + .features = CCU_FEATURE_FIXED_POSTDIV,
> + .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
> + &ccu_nk_ops, 0),
> + },
> +};
> +
> +static struct ccu_nk pll_periph1_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 5),
> + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> + .fixed_post_div = 2,
> + .common = {
> + .reg = 0x02c,
> + .features = CCU_FEATURE_FIXED_POSTDIV,
> + .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
> + &ccu_nk_ops, 0),
> + },
> +};
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
> + "osc24M", 0x030,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
> + "osc24M", 0x038,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +/*
> + * The output function can be changed to something more complex that
> + * we do not handle yet.
> + *
> + * Hardcode the mode so that we don't fall in that case.
> + */
> +#define SUN50I_A64_PLL_MIPI_REG 0x040
> +
> +struct ccu_nkm pll_mipi_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 4),
> + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> + .m = _SUNXI_CCU_DIV(0, 4),
> + .common = {
> + .reg = 0x040,
> + .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
> + &ccu_nkm_ops, 0),
> + },
> +};
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
> + "osc24M", 0x044,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
> + "osc24M", 0x048,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
> + "osc24M", 0x04c,
> + 8, 7, /* N */
> + 0, 2, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
CLK_SET_RATE_UNGATE for all the PLLs?
> +
> +static const char * const cpux_parents[] = { "osc32k", "osc24M",
> + "pll-cpux" , "pll-cpux" };
> +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> + 0x050, 16, 2, CLK_IS_CRITICAL);
CLK_SET_RATE_PARENT.
[...]
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +
Extra newline.
[...]
> +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
> +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
> + 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
The divider is only 2 bits wide.
> +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> +static const u8 tcon1_table[] = { 0, 2, };
> +struct ccu_div tcon1_clk = {
> + .enable = BIT(31),
> + .div = _SUNXI_CCU_DIV(0, 4),
> + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table),
Mux is only 2 bits wide.
> + .common = {
> + .reg = 0x11c,
> + .hw.init = CLK_HW_INIT_PARENTS("tcon1",
> + tcon1_parents,
> + &ccu_div_ops,
> + CLK_SET_RATE_PARENT),
> + },
> +};
> +
[...]
> +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
> +static const u8 dsi_dphy_table[] = { 0, 2, };
> +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
> + dsi_dphy_parents, dsi_dphy_table,
> + 0x168, 0, 3, 24, 2, BIT(31), 0);
Divider is 4 bits wide, and mux offset is 8.
[...]
Regards
ChenYu
^ permalink raw reply
* [PATCH] ahci: use pci_alloc_irq_vectors
From: Robert Richter @ 2016-10-20 15:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160906163946.GB24268@htj.duckdns.org>
On 06.09.16 12:39:46, Tejun Heo wrote:
> On Mon, Sep 05, 2016 at 05:21:45PM +0200, Christoph Hellwig wrote:
> > Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors.
> > The big advantage over the old code is that we can use the same API for
> > MSI and MSI-X, and that we don't need to store the MSI-X vector mapping
> > in driver-private data structures.
> >
> > This first conversion keeps the probe order as-is: MSI-X multi vector,
> > MSI multi vector, MSI single vector, MSI-X single vector and last a
> > single least legacy interrupt line. There is one small change of
> > behavior: we now check the "MSI Revert to Single Message" flag for
> > MSI-X in addition to MSI.
> >
> > Because the API to find the Linux IRQ number for a MSI/MSI-X vector
> > is PCI specific, but libahaci is bus-agnostic I had to a
> > get_irq_vector function pointer to struct ahci_host_priv. The
> > alternative would be to move the multi-vector case of ahci_host_activate
> > to ahci.c and just call ata_host_activate directly from the others
> > users of ahci_host_activate.
>
> Applied to libata/for-4.9 after pulling in the mainline.
Hm, this broke SATA on ThunderX. Log below.
I could not yet look into this closer but reverting this patch
helped:
0b9e2988ab22 ahci: use pci_alloc_irq_vectors
-Robert
[ 14.940982] ata1.00: qc timeout (cmd 0x27)
[ 14.941017] ata2.00: qc timeout (cmd 0x27)
[ 14.941021] ata2.00: failed to read native max address (err_mask=0x4)
[ 14.941023] ata2.00: HPA support seems broken, skipping HPA handling
[ 14.961969] ata1.00: failed to read native max address (err_mask=0x4)
[ 14.968401] ata1.00: HPA support seems broken, skipping HPA handling
[ 15.405004] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 15.437004] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 20.573007] ata2.00: qc timeout (cmd 0xef)
[ 20.573037] ata1.00: qc timeout (cmd 0xef)
[ 20.573041] ata1.00: failed to enable AA (error_mask=0x4)
[ 20.573044] ata1: limiting SATA link speed to 3.0 Gbps
[ 20.591691] ata2.00: failed to enable AA (error_mask=0x4)
[ 20.597083] ata2: limiting SATA link speed to 3.0 Gbps
[ 21.037003] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 21.043861] ata1.00: ATA-8: WDC WD5003ABYZ-011FA0, 01.01S03, max UDMA/133
[ 21.050647] ata1.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32)
[ 21.061007] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 21.067683] ata2.00: ATA-8: WDC WD5003ABYZ-011FA0, 01.01S03, max UDMA/133
[ 21.074468] ata2.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32)
[ 36.444979] ata1.00: qc timeout (cmd 0xef)
[ 36.445011] ata2.00: qc timeout (cmd 0xef)
[ 36.445014] ata2.00: failed to set xfermode (err_mask=0x4)
[ 36.445016] ata2.00: disabled
[ 36.445026] ata2: hard resetting link
[ 36.465268] ata1.00: failed to set xfermode (err_mask=0x4)
[ 36.470750] ata1.00: disabled
[ 36.473718] ata1: hard resetting link
[ 36.909003] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 36.915184] ata2: EH complete
[ 36.941013] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 36.947196] ata1: EH complete
[ 36.960294] Freeing unused kernel memory: 1024K (fffffe0001f70000 -
fffffe0002070000)
../..
[ 161.266664] dracut-initqueue[624]: Warning: dracut-initqueue timeout
- starting timeout scripts
[ 161.793311] dracut-initqueue[624]: Warning: dracut-initqueue timeout
- starting timeout scripts
[ 162.309073] dracut-initqueue[624]: Warning: dracut-initqueue timeout
- starting timeout scripts
^ permalink raw reply
* [PATCH v2 5/6] clk: stm32f469: Add QSPI clock
From: Gabriel Fernandez @ 2016-10-20 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161019203228.GC8871@codeaurora.org>
Hi Stephen
On 10/19/2016 10:32 PM, Stephen Boyd wrote:
> On 10/14, gabriel.fernandez at st.com wrote:
>> @@ -532,10 +618,42 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>> { 0 },
>> };
>>
>> +struct stm32f4_clk_data {
>> + const struct stm32f4_gate_data *gates_data;
>> + const u64 *gates_map;
>> + int gates_num;
>> +};
>> @@ -549,6 +667,19 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>> goto fail;
>> }
>>
>> + match = of_match_node(stm32f4_of_match, np);
>> + if (WARN_ON(!match))
>> + return;
>> +
>> + data = match->data;
>> +
>> + clks = kmalloc_array(data->gates_num + END_PRIMARY_CLK,
>> + sizeof(struct clk_hw *), GFP_KERNEL);
> sizeof(*clks)?
ok
>
>> + if (!clks)
>> + goto fail;
>> +
>> + stm32f4_gate_map = data->gates_map;
>> +
>> hse_clk = of_clk_get_parent_name(np, 0);
>>
>> clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
>> @@ -581,11 +712,15 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>> clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
>> 0, 1, 1);
>>
>> - for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) {
>> - const struct stm32f4_gate_data *gd = &stm32f4_gates[n];
>> - unsigned int secondary =
>> - 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx;
>> - int idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
>> + for (n = 0; n < data->gates_num; n++) {
>> + const struct stm32f4_gate_data *gd;
>> + unsigned int secondary;
>> + int idx;
>> +
>> + gd = (struct stm32f4_gate_data *) &data->gates_data[n];
> Why do we cast here? Get rid of const? Perhaps the struct
> shouldn't have const on the member instead?
we don't need cast here.
Thank's Stephen
BR
Gabriel
>
>> + secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
>> + gd->bit_idx;
>> + idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
>>
>> if (idx < 0)
^ permalink raw reply
* [PATCH] ARM: dts: sun8i: Add SPI controller node in H3
From: Maxime Ripard @ 2016-10-20 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161019134608.12850-1-woogyom.kim@gmail.com>
Hi Milo,
On Wed, Oct 19, 2016 at 10:46:08PM +0900, Milo Kim wrote:
> H3 supports two SPI controllers. Four pins (MOSI, MISO, SCLK, SS) are
> configured through the pinctrl subsystem. It is almost same as A31 SPI
> except buffer size, so those DT properties are reusable.
>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> Cc: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Ideally, this would be part of your serie to add the H3 support to the
spi driver. This way, you make it explicit that there is a dependency
between the two, and it's easier for us :)
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 75a8654..c38b028 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -381,6 +381,20 @@
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
>
> + spi0_pins: spi0 {
> + allwinner,pins = "PC0", "PC1", "PC2", "PC3";
> + allwinner,function = "spi0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + spi1_pins: spi1 {
> + allwinner,pins = "PA15", "PA16", "PA14", "PA13";
> + allwinner,function = "spi1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
This needs to be in a separate patch
> uart0_pins_a: uart0 at 0 {
> allwinner,pins = "PA4", "PA5";
> allwinner,function = "uart0";
> @@ -425,6 +439,38 @@
> clocks = <&osc24M>;
> };
>
> + spi0: spi at 01c68000 {
> + compatible = "allwinner,sun8i-h3-spi";
> + reg = <0x01c68000 0x1000>;
> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 23>, <&dma 23>;
> + dma-names = "rx", "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>;
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi at 01c69000 {
> + compatible = "allwinner,sun8i-h3-spi";
> + reg = <0x01c69000 0x1000>;
> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 24>, <&dma 24>;
> + dma-names = "rx", "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_pins>;
> + resets = <&ccu RST_BUS_SPI1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v3 5/6] ARM: sunxi: Remove useless allwinner,pull property
From: Jean-Francois Moine @ 2016-10-20 15:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <42e249454ccf6b14e9ec266cb8d42a24f6d71d7b.1476971126.git-series.maxime.ripard@free-electrons.com>
On Thu, 20 Oct 2016 15:49:06 +0200
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> The allwinner,pull property set to NO_PULL was really considered our
> default (and wasn't even changing the default value in the code).
>
> Remove these properties to make it obvious that we do not set anything in
> such a case.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/ntc-gr8-evb.dts | 4 +-
> arch/arm/boot/dts/ntc-gr8.dtsi | 14 +-----
> arch/arm/boot/dts/sun4i-a10-a1000.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 4 +-
> arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-marsboard.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-mk802.dts | 3 +-
> arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 3 +-
> arch/arm/boot/dts/sun4i-a10.dtsi | 24 +--------
> arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 1 +-
> arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-mk802.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +--
> arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 1 +-
> arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 3 +-
> arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 +-
> arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 1 +-
> arch/arm/boot/dts/sun5i-a13.dtsi | 3 +-
> arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +-
> arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +-
> arch/arm/boot/dts/sun5i.dtsi | 7 +--
> arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31-colombus.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31-i7.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31.dtsi | 13 +----
> arch/arm/boot/dts/sun6i-a31s-primo81.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-bananapi.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-bananapro.dts | 5 +--
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 +--
> arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-m3.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-orangepi.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20.dtsi | 37 +------------
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 +---
> arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 1 +-
> arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 1 +-
> arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 1 +-
> arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 3 +-
> arch/arm/boot/dts/sun8i-a33.dtsi | 1 +-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 3 +-
> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 2 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 1 +-
> arch/arm/boot/dts/sun8i-h3.dtsi | 12 +----
> arch/arm/boot/dts/sun8i-r16-parrot.dts | 3 +-
> arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +-
> arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 1 +-
> arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 +-
> arch/arm/boot/dts/sun9i-a80.dtsi | 6 +--
> arch/arm/boot/dts/sunxi-common-regulators.dtsi | 4 +-
> 85 files changed, 0 insertions(+), 302 deletions(-)
[snip]
Is it really usefull to change all these files while in a previous
patch you were writing:
> The generic pin configuration and multiplexing should be preferred now,
> even though we still support the old one.
?
--
Ken ar c'henta? | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
^ permalink raw reply
* [PATCH v2] ARM: at91/dt: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx
From: Alexandre Belloni @ 2016-10-20 15:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161016162145.26193-2-sylvain.rochet@finsecur.com>
On 16/10/2016 at 18:21:45 +0200, Sylvain Rochet wrote :
> Remove pullup on dbgu DTXD signal, it is a push-pull output thus the
> pullup is pointless.
>
> Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left
> floating and so consuming a useless extra amount of power in crowbarred
> state if nothing is externally connected to dbgu.
>
> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
> ---
> arch/arm/boot/dts/at91rm9200.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9260.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9261.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9263.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9g45.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++--
> arch/arm/boot/dts/sama5d3.dtsi | 4 ++--
> arch/arm/boot/dts/sama5d4.dtsi | 4 ++--
> 10 files changed, 20 insertions(+), 20 deletions(-)
>
Applied, thanks.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH 0/4] ARM: boot: mxs: Add On-Chip RAM
From: Stefan Wahren @ 2016-10-20 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473789066-8955-1-git-send-email-stefan.wahren@i2se.com>
Am 13.09.2016 um 19:51 schrieb Stefan Wahren:
> The i.MX23 / i.MX28 have a small amount of On-Chip RAM which is also necessary
> for suspend to RAM and standby mode. But before we need to remove the fake reg
> properties of all internal bus nodes as discussed in this thread [1].
>
> This patch series requires Fabio Estevam's recent series "ARM: dts: imx23:
> Remove skeleton.dtsi inclusion" [2].
>
> [1] - https://marc.info/?l=devicetree&m=146139948426520&w=2
> [2] - http://www.spinics.net/lists/arm-kernel/msg528974.html
>
> Stefan Wahren (4):
> ARM: dts: imx23: Remove fake "reg" properties from bus nodes
> ARM: dts: imx28: Remove fake "reg" properties from bus nodes
> ARM: dts: imx23: add On-Chip RAM
> ARM: dts: imx28: add On-Chip RAM
>
> arch/arm/boot/dts/imx23-evk.dts | 8 ++++----
> arch/arm/boot/dts/imx23-olinuxino.dts | 8 ++++----
> arch/arm/boot/dts/imx23-sansa.dts | 8 ++++----
> arch/arm/boot/dts/imx23-stmp378x_devb.dts | 6 +++---
> arch/arm/boot/dts/imx23-xfi3.dts | 8 ++++----
> arch/arm/boot/dts/imx23.dtsi | 15 +++++++++------
> arch/arm/boot/dts/imx28-apf28.dts | 8 ++++----
> arch/arm/boot/dts/imx28-apf28dev.dts | 8 ++++----
> arch/arm/boot/dts/imx28-apx4devkit.dts | 8 ++++----
> arch/arm/boot/dts/imx28-cfa10036.dts | 8 ++++----
> arch/arm/boot/dts/imx28-cfa10037.dts | 8 ++++----
> arch/arm/boot/dts/imx28-cfa10049.dts | 10 +++++-----
> arch/arm/boot/dts/imx28-cfa10055.dts | 6 +++---
> arch/arm/boot/dts/imx28-cfa10056.dts | 4 ++--
> arch/arm/boot/dts/imx28-cfa10057.dts | 10 +++++-----
> arch/arm/boot/dts/imx28-cfa10058.dts | 10 +++++-----
> arch/arm/boot/dts/imx28-duckbill.dts | 8 ++++----
> arch/arm/boot/dts/imx28-evk.dts | 8 ++++----
> arch/arm/boot/dts/imx28-m28.dtsi | 6 +++---
> arch/arm/boot/dts/imx28-m28cu3.dts | 8 ++++----
> arch/arm/boot/dts/imx28-m28evk.dts | 8 ++++----
> arch/arm/boot/dts/imx28-sps1.dts | 8 ++++----
> arch/arm/boot/dts/imx28.dtsi | 17 +++++++++--------
> 23 files changed, 100 insertions(+), 96 deletions(-)
>
Any comments about this series or should i resend it without Fabio's
patch series applied?
^ permalink raw reply
* [PATCH v14 3/9] clocksource/drivers/arm_arch_timer: Improve printk relevant code
From: Mark Rutland @ 2016-10-20 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475086637-1914-4-git-send-email-fu.wei@linaro.org>
On Thu, Sep 29, 2016 at 02:17:11AM +0800, fu.wei at linaro.org wrote:
> static void arch_timer_banner(unsigned type)
> {
> - pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
> - type & ARCH_CP15_TIMER ? "cp15" : "",
> - type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
> - type & ARCH_MEM_TIMER ? "mmio" : "",
> - (unsigned long)arch_timer_rate / 1000000,
> - (unsigned long)(arch_timer_rate / 10000) % 100,
> - type & ARCH_CP15_TIMER ?
> - (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
> - "",
> - type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
> - type & ARCH_MEM_TIMER ?
> - arch_timer_mem_use_virtual ? "virt" : "phys" :
> - "");
> + pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
> + type & ARCH_CP15_TIMER ? "cp15" : "",
> + type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
> + type & ARCH_MEM_TIMER ? "mmio" : "",
> + (unsigned long)arch_timer_rate / 1000000,
> + (unsigned long)(arch_timer_rate / 10000) % 100,
> + type & ARCH_CP15_TIMER ?
> + (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
> + "",
Please restore the additional indent on this line...
> + type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
> + type & ARCH_MEM_TIMER ?
> + arch_timer_mem_use_virtual ? "virt" : "phys" :
> + "");
... and these two.
No matter what checkpatch says, I prefer the code that way so as to keep
the ternary clear.
[...]
> @@ -768,7 +769,7 @@ static int __init arch_timer_init(void)
> return ret;
>
> arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
> -
> +
Please mention the whitespace fixup in the commit message. It's
surprising otherwise.
With all that:
Acked-by: Mark Rutland <mark.rutland@arm.com>
Thanks,
Mark.
^ permalink raw reply
* [PATCH 4/4] ARM: dts: stm32f429: remove Ethernet wake on Lan support
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
This patch removes WoL (Wake on Lan) support as it is not yet
fully supported and tested.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 6350117b..ad0bc6a 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -377,8 +377,8 @@
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
- interrupts = <61>, <62>;
- interrupt-names = "macirq", "eth_wake_irq";
+ interrupts = <61>;
+ interrupt-names = "macirq";
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
--
1.9.1
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: stm32f429: Fix Ethernet node on Eval Board
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
"phy-handle" entry is mandatory when mdio subnode is used in
Ethernet node.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index fa30bf1..a11b108 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -99,7 +99,7 @@
pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
phy-mode = "mii";
-
+ phy-handle = <&phy1>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
^ permalink raw reply related
* [PATCH 2/4] ARM: dts: stm32f429: Update Ethernet node on Eval board
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
Update new pinctrl phandle name and use new node name.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 13c7cd2..fa30bf1 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -94,11 +94,12 @@
clock-frequency = <25000000>;
};
-ðernet0 {
+&mac {
status = "okay";
- pinctrl-0 = <ðernet0_mii>;
+ pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
- phy-mode = "mii-id";
+ phy-mode = "mii";
+
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
^ permalink raw reply related
* [PATCH 1/4] ARM: dts: stm32f429: Align Ethernet node with new bindings properties
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
This patch aligns clocks names and node reference according to new
stm32-dwmac glue binding. It also renames Ethernet pinctrl phandle
(indeed there is no need to add 0 as Ethernet instance as there is only
one IP in SOC).
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 336ee4f..6350117b 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -313,7 +313,7 @@
};
};
- ethernet0_mii: mii at 0 {
+ ethernet_mii: mii at 0 {
pins {
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
@@ -373,13 +373,13 @@
st,mem2mem;
};
- ethernet0: dwmac at 40028000 {
+ mac: ethernet at 40028000 {
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
- clock-names = "stmmaceth", "tx-clk", "rx-clk";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
snps,pbl = <8>;
--
1.9.1
^ permalink raw reply related
* [PATCH 0/4] STM32F429: Add Ethernet fixes
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
This series adds several fixes for Ethernet for stm32f429 MCU.
First 2 patches have already been reviewed some months ago when
stm32 Ethernet glue has been pushed (I added in this series to keep
history). Fixes are:
-Change DT to be compliant to stm32 ethernet glue binding
-Add phy-handle to correctly use mdio subnode
-Remove WoL support
Regards
Alex
Alexandre TORGUE (4):
ARM: dts: stm32f429: Align Ethernet node with new bindings properties
ARM: dts: stm32f429: Update Ethernet node on Eval board
ARM: dts: stm32f429: Fix Ethernet node on Eval Board
ARM: dts: stm32f429: remove Ethernet wake on Lan support
arch/arm/boot/dts/stm32429i-eval.dts | 7 ++++---
arch/arm/boot/dts/stm32f429.dtsi | 10 +++++-----
2 files changed, 9 insertions(+), 8 deletions(-)
--
1.9.1
^ permalink raw reply
* [GIT PULL] STi defconfig updates for v4.10
From: Patrice Chotard @ 2016-10-20 15:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Arnd and Kevin,
Please consider this first round of multi_v7_defconfig updates for v4.10 :
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git tags/sti-defconfig-for-4.10
for you to fetch changes up to 620c52f4db4d47e1f33c64e641392fe575d5397f:
ARM: multi_v7_defconfig: Remove stih41x phy Kconfig symbol. (2016-10-20 17:05:08 +0200)
----------------------------------------------------------------
Remove STiH415/416 specific IPs
As STiH415/416 have been removed from kernel, remove IPs only found
on these socs, remove CONFIG_PHY_MIPHY365X and CONFIG_PHY_STIH41X_USB.
----------------------------------------------------------------
Peter Griffin (2):
ARM: multi_v7_defconfig: Remove miphy365 phy Kconfig symbol.
ARM: multi_v7_defconfig: Remove stih41x phy Kconfig symbol.
arch/arm/configs/multi_v7_defconfig | 2 --
1 file changed, 2 deletions(-)
^ permalink raw reply
* [linux-sunxi] [PATCH v4 9/9] arm64: dts: add Pine64 support
From: Chen-Yu Tsai @ 2016-10-20 15:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0ceb2e4d03b16b3c7edf1550ba4a79fbbfac925b.1476196031.git-series.maxime.ripard@free-electrons.com>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Andre Przywara <andre.przywara@arm.com>
>
> The Pine64 is a cost-efficient development board based on the
> Allwinner A64 SoC.
> There are three models: the basic version with Fast Ethernet and
> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
> feature Gigabit Ethernet and additional connectors for touchscreens
> and a camera. Or as my son put it: "Those are smaller and these are
> missing." ;-)
> The two Pine64+ models just differ in the amount of DRAM
> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and
> patches the DT accordingly we just need to provide one DT for the
> Pine64+.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> [Maxime: Removed the common DTSI and include directly the pine64 DTS]
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply
* [PATCH v14 0/9] acpi, clocksource: add GTDT driver and GTDT support in arm_arch_timer
From: Mark Rutland @ 2016-10-20 15:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020145752.GC8731@red-moon>
On Thu, Oct 20, 2016 at 03:57:52PM +0100, Lorenzo Pieralisi wrote:
> On Thu, Oct 20, 2016 at 03:31:01PM +0100, Mark Rutland wrote:
> > Hi,
> >
> > On Thu, Sep 29, 2016 at 02:17:08AM +0800, fu.wei at linaro.org wrote:
> > > From: Fu Wei <fu.wei@linaro.org>
> >
> > > This patchset depends on the following patchset:
> > > [UPDATE PATCH V11 1/8] ACPI: I/O Remapping Table (IORT) initial support
> > > https://lkml.org/lkml/2016/9/12/949
> >
> > Is there a branch with these anywhere? I wasn't Cc'd on those and it's
> > rather difficult to get at the series from an LKML link.
>
> For the records, the dependency above has now been merged and it was
> just a directory creation dependency (drivers/acpi/arm64, where some of
> the code in this series will live).
Ah, I see. That saves us all some trouble, then. :)
Thanks,
Mark.
^ permalink raw reply
* [linux-sunxi] [PATCH v4 7/9] arm64: dts: add Allwinner A64 SoC .dtsi
From: Chen-Yu Tsai @ 2016-10-20 15:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <41ac6bd7d95fcabcae23ed4356f5f72b3aaf282d.1476196031.git-series.maxime.ripard@free-electrons.com>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Andre Przywara <andre.przywara@arm.com>
>
> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> [Maxime: Convert to CCU binding, drop the MMC support for now]
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +-
> MAINTAINERS | 1 +-
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 263 +++++++++++++++++-
> 3 files changed, 265 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 3975d0a0e4c2..4d6467cc2aa2 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,4 +14,5 @@ using one of the following compatible strings:
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> allwinner,sun9i-a80
> + allwinner,sun50i-a64
> nextthing,gr8
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7be47efb2159..926879c05dc6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -983,6 +983,7 @@ L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> N: sun[x456789]i
> F: arch/arm/boot/dts/ntc-gr8*
> +F: arch/arm64/boot/dts/allwinner/
>
> ARM/Allwinner SoC Clock Support
> M: Emilio L?pez <emilio@elopez.com.ar>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> new file mode 100644
> index 000000000000..0f75fec23dc9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -0,0 +1,263 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/clock/sun50i-a64-ccu.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +#include <dt-bindings/reset/sun50i-a64-ccu.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu at 1 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <1>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu at 2 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu at 3 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <3>;
> + enable-method = "psci";
> + };
> + };
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + ccu: clock at 01c20000 {
> + compatible = "allwinner,sun50i-a64-ccu";
> + reg = <0x01c20000 0x400>;
> + clocks = <&osc24M>, <&osc32k>;
> + clock-names = "hosc", "losc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pio: pinctrl at 1c20800 {
> + compatible = "allwinner,sun50i-a64-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_PIO>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
I think this should be 3? <bank index flags>?
> +
> + i2c1_pins: i2c1_pins {
> + allwinner,pins = "PH2", "PH3";
> + allwinner,function = "i2c1";
> + };
> +
> + uart0_pins_a: uart0 at 0 {
> + allwinner,pins = "PB8", "PB9";
> + allwinner,function = "uart0";
> + };
> + };
> +
> + uart0: serial at 1c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + status = "disabled";
> + };
> +
> + uart1: serial at 1c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + status = "disabled";
> + };
> +
> + uart2: serial at 1c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + status = "disabled";
> + };
> +
> + uart3: serial at 1c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + status = "disabled";
> + };
> +
> + uart4: serial at 1c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + status = "disabled";
> + };
> +
> + rtc: rtc at 1f00000 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01f00000 0x54>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
Should sort by address.
You can keep my Ack after fixing these.
ChenYu
> +
> + i2c0: i2c at 1c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c at 1c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c at 1c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + gic: interrupt-controller at 1c81000 {
> + compatible = "arm,gic-400";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x2000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> + };
> +};
> --
> git-series 0.8.10
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* [PATCH v14 2/9] clocksource/drivers/arm_arch_timer: Add a new enum for spi type
From: Mark Rutland @ 2016-10-20 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475086637-1914-3-git-send-email-fu.wei@linaro.org>
On Thu, Sep 29, 2016 at 02:17:10AM +0800, fu.wei at linaro.org wrote:
> diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
> index 6f06481..16dcd10 100644
> --- a/include/clocksource/arm_arch_timer.h
> +++ b/include/clocksource/arm_arch_timer.h
> @@ -45,6 +45,12 @@ enum ppi_nr {
> MAX_TIMER_PPI
> };
>
> +enum spi_nr {
> + PHYS_SPI,
> + VIRT_SPI,
> + MAX_TIMER_SPI
> +};
Please rename this to arch_timer_spi_nr (as with patch 1 for
s/ppi_nr/arch_timer_ppi_nr/). With that:
Acked-by: Mark Rutland <mark.rutland@arm.com>
Thanks,
Mark.
^ permalink raw reply
* [PATCH v4 5/9] clk: sunxi-ng: Implement minimum for multipliers
From: Chen-Yu Tsai @ 2016-10-20 15:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <dc2601d4f35d9921ec50ed443cdd413f699fa270.1476196031.git-series.maxime.ripard@free-electrons.com>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Allow the CCU drivers to specify a multiplier for their clocks.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu_mult.c | 2 +-
> drivers/clk/sunxi-ng/ccu_mult.h | 13 +++++++++----
> drivers/clk/sunxi-ng/ccu_nk.c | 8 ++++----
> drivers/clk/sunxi-ng/ccu_nkm.c | 8 ++++----
> drivers/clk/sunxi-ng/ccu_nkmp.c | 4 ++--
> drivers/clk/sunxi-ng/ccu_nm.c | 2 +-
> 6 files changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> index 6a02ffee5386..678b6cb49f01 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.c
> +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> @@ -105,7 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
> ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
> &parent_rate);
>
> - _cm.min = 1;
> + _cm.min = cm->mult.min;
> _cm.max = 1 << cm->mult.width;
> ccu_mult_find_best(parent_rate, rate, &_cm);
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> index 113780b7558e..c1a2134bdc71 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.h
> +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> @@ -7,14 +7,19 @@
> struct ccu_mult_internal {
> u8 shift;
> u8 width;
> + u8 min;
> };
>
> -#define _SUNXI_CCU_MULT(_shift, _width) \
> - { \
> - .shift = _shift, \
> - .width = _width, \
> +#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> + { \
> + .shift = _shift, \
> + .width = _width, \
> + .min = _min, \
> }
>
> +#define _SUNXI_CCU_MULT(_shift, _width) \
> + _SUNXI_CCU_MULT_MIN(_shift, _width, 1)
> +
> struct ccu_mult {
> u32 enable;
>
> diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> index a42d870ba0ef..eaf0fdf78d2b 100644
> --- a/drivers/clk/sunxi-ng/ccu_nk.c
> +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> @@ -97,9 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
> if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> rate *= nk->fixed_post_div;
>
> - _nk.min_n = 1;
> + _nk.min_n = nk->n.min;
> _nk.max_n = 1 << nk->n.width;
> - _nk.min_k = 1;
> + _nk.min_k = nk->k.min;
> _nk.max_k = 1 << nk->k.width;
>
> ccu_nk_find_best(*parent_rate, rate, &_nk);
> @@ -122,9 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
> if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> rate = rate * nk->fixed_post_div;
>
> - _nk.min_n = 1;
> + _nk.min_n = nk->n.min;
> _nk.max_n = 1 << nk->n.width;
> - _nk.min_k = 1;
> + _nk.min_k = nk->k.min;
> _nk.max_k = 1 << nk->k.width;
>
> ccu_nk_find_best(parent_rate, rate, &_nk);
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index b2a5fccf2f8c..715b49211ddb 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -100,9 +100,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> struct ccu_nkm *nkm = data;
> struct _ccu_nkm _nkm;
>
> - _nkm.min_n = 1;
> + _nkm.min_n = nkm->n.min;
> _nkm.max_n = 1 << nkm->n.width;
> - _nkm.min_k = 1;
> + _nkm.min_n = nkm->k.min;
Typo here.
> _nkm.max_k = 1 << nkm->k.width;
> _nkm.min_m = 1;
> _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> @@ -129,9 +129,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long flags;
> u32 reg;
>
> - _nkm.min_n = 1;
> + _nkm.min_n = nkm->n.min;
> _nkm.max_n = 1 << nkm->n.width;
> - _nkm.min_k = 1;
> + _nkm.min_n = nkm->k.min;
And here.
> _nkm.max_k = 1 << nkm->k.width;
> _nkm.min_m = 1;
> _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> index 2c1398192e48..7968e0bac5db 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> @@ -107,9 +107,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
> struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
> struct _ccu_nkmp _nkmp;
>
> - _nkmp.min_n = 1;
> + _nkmp.min_n = nkmp->n.min;
> _nkmp.max_n = 1 << nkmp->n.width;
> - _nkmp.min_k = 1;
> + _nkmp.min_n = nkmp->k.min;
And here.
> _nkmp.max_k = 1 << nkmp->k.width;
> _nkmp.min_m = 1;
> _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> index 2a190bc032a9..b1f3f0e8899d 100644
> --- a/drivers/clk/sunxi-ng/ccu_nm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> @@ -93,7 +93,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
> struct ccu_nm *nm = hw_to_ccu_nm(hw);
> struct _ccu_nm _nm;
>
> - _nm.min_n = 1;
> + _nm.min_n = nm->n.min;
> _nm.max_n = 1 << nm->n.width;
> _nm.min_m = 1;
> _nm.max_m = nm->m.max ?: 1 << nm->m.width;
> --
> git-series 0.8.10
Otherwise,
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply
* [PATCH v4 4/9] clk: sunxi-ng: Add minimums for all the relevant structures and clocks
From: Chen-Yu Tsai @ 2016-10-20 15:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a96b56fb7bda849e087b63a04ff76d1396c44d72.1476196031.git-series.maxime.ripard@free-electrons.com>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Modify the current clocks we have to be able to specify the minimum for
> each clocks we support, just like we support the max.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Including the bits from patch 2.
^ permalink raw reply
* [PATCH v14 0/9] acpi, clocksource: add GTDT driver and GTDT support in arm_arch_timer
From: Lorenzo Pieralisi @ 2016-10-20 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020143101.GI10234@leverpostej>
On Thu, Oct 20, 2016 at 03:31:01PM +0100, Mark Rutland wrote:
> Hi,
>
> On Thu, Sep 29, 2016 at 02:17:08AM +0800, fu.wei at linaro.org wrote:
> > From: Fu Wei <fu.wei@linaro.org>
>
> > This patchset depends on the following patchset:
> > [UPDATE PATCH V11 1/8] ACPI: I/O Remapping Table (IORT) initial support
> > https://lkml.org/lkml/2016/9/12/949
>
> Is there a branch with these anywhere? I wasn't Cc'd on those and it's
> rather difficult to get at the series from an LKML link.
For the records, the dependency above has now been merged and it was
just a directory creation dependency (drivers/acpi/arm64, where some of
the code in this series will live). So basically this means that at
present this series is self-contained, probably it would have been
better to wait for -rc1 before posting it (so that dependencies were
settled) but anyway I think it can be reviewed as-is.
Thanks for having a look,
Lorenzo
^ permalink raw reply
* [PATCH v3] drivers: psci: PSCI checker module
From: Kevin Brodsky @ 2016-10-20 14:51 UTC (permalink / raw)
To: linux-arm-kernel
On arm and arm64, PSCI is one of the possible firmware interfaces
used for power management. This includes both turning CPUs on and off,
and suspending them (entering idle states).
This patch adds a PSCI checker module that enables basic testing of
PSCI operations during startup. There are two main tests: CPU
hotplugging and suspending.
In the hotplug tests, the hotplug API is used to turn off and on again
all CPUs in the system, and then all CPUs in each cluster, checking
the consistency of the return codes.
In the suspend tests, a high-priority thread is created on each core
and uses low-level cpuidle functionalities to enter suspend, in all
the possible states and multiple times. This should allow a maximum
number of CPUs to enter the same sleep state at the same or slightly
different time.
In essence, the suspend tests use a principle similar to that of the
intel_powerclamp driver (drivers/thermal/intel_powerclamp.c), but the
threads are only kept for the duration of the test (they are already
gone when userspace is started).
While in theory power management PSCI functions (CPU_{ON,OFF,SUSPEND})
could be directly called, this proved too difficult as it would imply
the duplication of all the logic used by the kernel to allow for a
clean shutdown/bringup/suspend of the CPU (the deepest sleep states
implying potentially the shutdown of the CPU).
Note that this file cannot be compiled as a loadable module, since it
uses a number of non-exported identifiers (essentially for
PSCI-specific checks and direct use of cpuidle) and relies on the
absence of userspace to avoid races when calling hotplug and cpuidle
functions.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kevin Hilman <khilman@kernel.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
---
Changelog v2..v3:
* Rebase on 4.9-rc1. a65d40961dc7 ("kthread/smpboot: do not park in
kthread_create_on_cpu()") modified the behavior of
kthread_create_on_cpu(), so that the created kthread is not parked
anymore. Using wake_up_process() instead of kthread_unpark() should
work. Thanks Jean-Philippe Brucker for reporting the issue!
* s/suspend_stress/suspend_test/, this is not really a stress test.
Cheers,
Kevin
drivers/firmware/Kconfig | 7 +
drivers/firmware/Makefile | 1 +
drivers/firmware/psci_checker.c | 487 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 495 insertions(+)
create mode 100644 drivers/firmware/psci_checker.c
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index bca172d42c74..904dd4942993 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -206,6 +206,13 @@ config QCOM_SCM_64
config HAVE_ARM_SMCCC
bool
+config PSCI_CHECKER
+ bool "PSCI checker"
+ depends on ARM_PSCI_FW && HOTPLUG_CPU
+ help
+ Run the PSCI checker during startup. This checks that hotplug and
+ suspend operations work correctly when using PSCI.
+
source "drivers/firmware/broadcom/Kconfig"
source "drivers/firmware/google/Kconfig"
source "drivers/firmware/efi/Kconfig"
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 898ac41fa8b3..e7248eacc796 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o
obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a
+obj-$(CONFIG_PSCI_CHECKER) += psci_checker.o
obj-y += broadcom/
obj-y += meson/
diff --git a/drivers/firmware/psci_checker.c b/drivers/firmware/psci_checker.c
new file mode 100644
index 000000000000..c1bf961d13ce
--- /dev/null
+++ b/drivers/firmware/psci_checker.c
@@ -0,0 +1,487 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2016 ARM Limited
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/atomic.h>
+#include <linux/completion.h>
+#include <linux/cpu.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/module.h>
+#include <linux/preempt.h>
+#include <linux/psci.h>
+#include <linux/slab.h>
+#include <linux/tick.h>
+#include <linux/topology.h>
+
+#include <asm/cpuidle.h>
+
+#include <uapi/linux/psci.h>
+
+#define NUM_SUSPEND_CYCLE (10)
+
+static unsigned int nb_available_cpus;
+static int tos_resident_cpu = -1;
+
+static atomic_t nb_active_threads;
+static struct completion suspend_threads_started =
+ COMPLETION_INITIALIZER(suspend_threads_started);
+static struct completion suspend_threads_done =
+ COMPLETION_INITIALIZER(suspend_threads_done);
+
+/*
+ * We assume that PSCI operations are used if they are available. This is not
+ * necessarily true on arm64, since the decision is based on the
+ * "enable-method" property of each CPU in the DT, but given that there is no
+ * arch-specific way to check this, we assume that the DT is sensible.
+ */
+static int psci_ops_check(void)
+{
+ int migrate_type = -1;
+ int cpu;
+
+ if (!(psci_ops.cpu_off && psci_ops.cpu_on && psci_ops.cpu_suspend)) {
+ pr_warn("Missing PSCI operations, aborting tests\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (psci_ops.migrate_info_type)
+ migrate_type = psci_ops.migrate_info_type();
+
+ if (migrate_type == PSCI_0_2_TOS_UP_MIGRATE ||
+ migrate_type == PSCI_0_2_TOS_UP_NO_MIGRATE) {
+ /* There is a UP Trusted OS, find on which core it resides. */
+ for_each_online_cpu(cpu)
+ if (psci_tos_resident_on(cpu)) {
+ tos_resident_cpu = cpu;
+ break;
+ }
+ if (tos_resident_cpu == -1)
+ pr_warn("UP Trusted OS resides on no online CPU\n");
+ }
+
+ return 0;
+}
+
+static int find_clusters(const struct cpumask *cpus,
+ const struct cpumask **clusters)
+{
+ unsigned int nb = 0;
+ cpumask_var_t tmp;
+
+ if (!alloc_cpumask_var(&tmp, GFP_KERNEL))
+ return -ENOMEM;
+ cpumask_copy(tmp, cpus);
+
+ while (!cpumask_empty(tmp)) {
+ const struct cpumask *cluster =
+ topology_core_cpumask(cpumask_any(tmp));
+
+ clusters[nb++] = cluster;
+ cpumask_andnot(tmp, tmp, cluster);
+ }
+
+ free_cpumask_var(tmp);
+ return nb;
+}
+
+/*
+ * offlined_cpus is a temporary array but passing it as an argument avoids
+ * multiple allocations.
+ */
+static unsigned int down_and_up_cpus(const struct cpumask *cpus,
+ struct cpumask *offlined_cpus)
+{
+ int cpu;
+ int err = 0;
+
+ cpumask_clear(offlined_cpus);
+
+ /* Try to power down all CPUs in the mask. */
+ for_each_cpu(cpu, cpus) {
+ int ret = cpu_down(cpu);
+
+ /*
+ * cpu_down() checks the number of online CPUs before the TOS
+ * resident CPU.
+ */
+ if (cpumask_weight(offlined_cpus) + 1 == nb_available_cpus) {
+ if (ret != -EBUSY) {
+ pr_err("Unexpected return code %d while trying "
+ "to power down last online CPU %d\n",
+ ret, cpu);
+ ++err;
+ }
+ } else if (cpu == tos_resident_cpu) {
+ if (ret != -EPERM) {
+ pr_err("Unexpected return code %d while trying "
+ "to power down TOS resident CPU %d\n",
+ ret, cpu);
+ ++err;
+ }
+ } else if (ret != 0) {
+ pr_err("Error occurred (%d) while trying "
+ "to power down CPU %d\n", ret, cpu);
+ ++err;
+ }
+
+ if (ret == 0)
+ cpumask_set_cpu(cpu, offlined_cpus);
+ }
+
+ /* Try to power up all the CPUs that have been offlined. */
+ for_each_cpu(cpu, offlined_cpus) {
+ int ret = cpu_up(cpu);
+
+ if (ret != 0) {
+ pr_err("Error occurred (%d) while trying "
+ "to power up CPU %d\n", ret, cpu);
+ ++err;
+ } else {
+ cpumask_clear_cpu(cpu, offlined_cpus);
+ }
+ }
+
+ /*
+ * Something went bad at some point and some CPUs could not be turned
+ * back on.
+ */
+ WARN_ON(!cpumask_empty(offlined_cpus) ||
+ num_online_cpus() != nb_available_cpus);
+
+ return err;
+}
+
+static int hotplug_tests(void)
+{
+ int err;
+ cpumask_var_t offlined_cpus;
+ int i, nb_cluster;
+ const struct cpumask **clusters;
+ char *page_buf;
+
+ err = -ENOMEM;
+ if (!alloc_cpumask_var(&offlined_cpus, GFP_KERNEL))
+ return err;
+ /* We may have up to nb_available_cpus clusters. */
+ clusters = kmalloc_array(nb_available_cpus, sizeof(*clusters),
+ GFP_KERNEL);
+ if (!clusters)
+ goto out_free_cpus;
+ page_buf = (char *)__get_free_page(GFP_KERNEL);
+ if (!page_buf)
+ goto out_free_clusters;
+
+ err = 0;
+ nb_cluster = find_clusters(cpu_online_mask, clusters);
+
+ /*
+ * Of course the last CPU cannot be powered down and cpu_down() should
+ * refuse doing that.
+ */
+ pr_info("Trying to turn off and on again all CPUs\n");
+ err += down_and_up_cpus(cpu_online_mask, offlined_cpus);
+
+ /*
+ * Take down CPUs by cluster this time. When the last CPU is turned
+ * off, the cluster itself should shut down.
+ */
+ for (i = 0; i < nb_cluster; ++i) {
+ int cluster_id =
+ topology_physical_package_id(cpumask_any(clusters[i]));
+ ssize_t len = cpumap_print_to_pagebuf(true, page_buf,
+ clusters[i]);
+ /* Remove trailing newline. */
+ page_buf[len - 1] = '\0';
+ pr_info("Trying to turn off and on again cluster %d "
+ "(CPUs %s)\n", cluster_id, page_buf);
+ err += down_and_up_cpus(clusters[i], offlined_cpus);
+ }
+
+ free_page((unsigned long)page_buf);
+out_free_clusters:
+ kfree(clusters);
+out_free_cpus:
+ free_cpumask_var(offlined_cpus);
+ return err;
+}
+
+static void dummy_callback(unsigned long ignored) {}
+
+static int suspend_cpu(int index, bool broadcast)
+{
+ int ret;
+
+ arch_cpu_idle_enter();
+
+ if (broadcast) {
+ /*
+ * The local timer will be shut down, we need to enter tick
+ * broadcast.
+ */
+ ret = tick_broadcast_enter();
+ if (ret) {
+ /*
+ * In the absence of hardware broadcast mechanism,
+ * this CPU might be used to broadcast wakeups, which
+ * may be why entering tick broadcast has failed.
+ * There is little the kernel can do to work around
+ * that, so enter WFI instead (idle state 0).
+ */
+ cpu_do_idle();
+ ret = 0;
+ goto out_arch_exit;
+ }
+ }
+
+ /*
+ * Replicate the common ARM cpuidle enter function
+ * (arm_enter_idle_state).
+ */
+ ret = CPU_PM_CPU_IDLE_ENTER(arm_cpuidle_suspend, index);
+
+ if (broadcast)
+ tick_broadcast_exit();
+
+out_arch_exit:
+ arch_cpu_idle_exit();
+
+ return ret;
+}
+
+static int suspend_test_thread(void *arg)
+{
+ int cpu = (long)arg;
+ int i, nb_suspend = 0, nb_shallow_sleep = 0, nb_err = 0;
+ struct sched_param sched_priority = { .sched_priority = MAX_RT_PRIO-1 };
+ struct cpuidle_device *dev;
+ struct cpuidle_driver *drv;
+ /* No need for an actual callback, we just want to wake up the CPU. */
+ struct timer_list wakeup_timer =
+ TIMER_INITIALIZER(dummy_callback, 0, 0);
+
+ /* Wait for the main thread to give the start signal. */
+ wait_for_completion(&suspend_threads_started);
+
+ /* Set maximum priority to preempt all other threads on this CPU. */
+ if (sched_setscheduler_nocheck(current, SCHED_FIFO, &sched_priority))
+ pr_warn("Failed to set suspend thread scheduler on CPU %d\n",
+ cpu);
+
+ dev = this_cpu_read(cpuidle_devices);
+ drv = cpuidle_get_cpu_driver(dev);
+
+ pr_info("CPU %d entering suspend cycles, states 1 through %d\n",
+ cpu, drv->state_count - 1);
+
+ for (i = 0; i < NUM_SUSPEND_CYCLE; ++i) {
+ int index;
+ /*
+ * Test all possible states, except 0 (which is usually WFI and
+ * doesn't use PSCI).
+ */
+ for (index = 1; index < drv->state_count; ++index) {
+ struct cpuidle_state *state = &drv->states[index];
+ bool broadcast = state->flags & CPUIDLE_FLAG_TIMER_STOP;
+ int ret;
+
+ /*
+ * Set the timer to wake this CPU up in some time (which
+ * should be largely sufficient for entering suspend).
+ * If the local tick is disabled when entering suspend,
+ * suspend_cpu() takes care of switching to a broadcast
+ * tick, so the timer will still wake us up.
+ */
+ mod_timer(&wakeup_timer, jiffies +
+ usecs_to_jiffies(state->target_residency));
+
+ /* IRQs must be disabled during suspend operations. */
+ local_irq_disable();
+
+ ret = suspend_cpu(index, broadcast);
+
+ /*
+ * We have woken up. Re-enable IRQs to handle any
+ * pending interrupt, do not wait until the end of the
+ * loop.
+ */
+ local_irq_enable();
+
+ if (ret == index) {
+ ++nb_suspend;
+ } else if (ret >= 0) {
+ /* We did not enter the expected state. */
+ ++nb_shallow_sleep;
+ } else {
+ pr_err("Failed to suspend CPU %d: error %d "
+ "(requested state %d, cycle %d)\n",
+ cpu, ret, index, i);
+ ++nb_err;
+ }
+ }
+ }
+
+ /*
+ * Disable the timer to make sure that the timer will not trigger
+ * later.
+ */
+ del_timer(&wakeup_timer);
+
+ if (atomic_dec_return_relaxed(&nb_active_threads) == 0)
+ complete(&suspend_threads_done);
+
+ /* Give up on RT scheduling and wait for termination. */
+ sched_priority.sched_priority = 0;
+ if (sched_setscheduler_nocheck(current, SCHED_NORMAL, &sched_priority))
+ pr_warn("Failed to set suspend thread scheduler on CPU %d\n",
+ cpu);
+ for (;;) {
+ /* Needs to be set first to avoid missing a wakeup. */
+ set_current_state(TASK_INTERRUPTIBLE);
+ if (kthread_should_stop()) {
+ __set_current_state(TASK_RUNNING);
+ break;
+ }
+ schedule();
+ }
+
+ pr_info("CPU %d suspend test results: success %d, shallow states %d, errors %d\n",
+ cpu, nb_suspend, nb_shallow_sleep, nb_err);
+
+ return nb_err;
+}
+
+static int suspend_tests(void)
+{
+ int i, cpu, err = 0;
+ struct task_struct **threads;
+ int nb_threads = 0;
+
+ threads = kmalloc_array(nb_available_cpus, sizeof(*threads),
+ GFP_KERNEL);
+ if (!threads)
+ return -ENOMEM;
+
+ for_each_online_cpu(cpu) {
+ struct task_struct *thread;
+ /* Check that cpuidle is available on that CPU. */
+ struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu);
+ struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev);
+
+ if (cpuidle_not_available(drv, dev)) {
+ pr_warn("cpuidle not available on CPU %d, ignoring\n",
+ cpu);
+ continue;
+ }
+
+ thread = kthread_create_on_cpu(suspend_test_thread,
+ (void *)(long)cpu, cpu,
+ "psci_suspend_test");
+ if (IS_ERR(thread))
+ pr_err("Failed to create kthread on CPU %d\n", cpu);
+ else
+ threads[nb_threads++] = thread;
+ }
+ if (nb_threads < 1) {
+ kfree(threads);
+ return -ENODEV;
+ }
+
+ atomic_set(&nb_active_threads, nb_threads);
+
+ /*
+ * Stop cpuidle to prevent the idle tasks from entering a deep sleep
+ * mode, as it might interfere with the suspend threads on other CPUs.
+ * This does not prevent the suspend threads from using cpuidle (only
+ * the idle tasks check this status).
+ */
+ cpuidle_pause();
+
+ /*
+ * Wake up the suspend threads. To avoid the main thread being preempted
+ * before all the threads have been unparked, the suspend threads will
+ * wait for the completion of suspend_threads_started.
+ */
+ for (i = 0; i < nb_threads; ++i)
+ wake_up_process(threads[i]);
+ complete_all(&suspend_threads_started);
+
+ wait_for_completion(&suspend_threads_done);
+
+ cpuidle_resume();
+
+ /* Stop and destroy all threads, get return status. */
+ for (i = 0; i < nb_threads; ++i)
+ err += kthread_stop(threads[i]);
+
+ kfree(threads);
+ return err;
+}
+
+static int __init psci_checker(void)
+{
+ int ret;
+
+ /*
+ * Since we're in an initcall, we assume that all the CPUs that all
+ * CPUs that can be onlined have been onlined.
+ *
+ * The tests assume that hotplug is enabled but nobody else is using it,
+ * otherwise the results will be unpredictable. However, since there
+ * is no userspace yet in initcalls, that should be fine.
+ */
+ nb_available_cpus = num_online_cpus();
+
+ /* Check PSCI operations are set up and working. */
+ ret = psci_ops_check();
+ if (ret)
+ return ret;
+
+ pr_info("PSCI checker started using %u CPUs\n", nb_available_cpus);
+
+ pr_info("Starting hotplug tests\n");
+ ret = hotplug_tests();
+ if (ret == 0)
+ pr_info("Hotplug tests passed OK\n");
+ else if (ret > 0)
+ pr_err("%d error(s) encountered in hotplug tests\n", ret);
+ else {
+ pr_err("Out of memory\n");
+ return ret;
+ }
+
+ pr_info("Starting suspend tests (%d cycles per state)\n",
+ NUM_SUSPEND_CYCLE);
+ ret = suspend_tests();
+ if (ret == 0)
+ pr_info("Suspend tests passed OK\n");
+ else if (ret > 0)
+ pr_err("%d error(s) encountered in suspend tests\n", ret);
+ else {
+ switch (ret) {
+ case -ENOMEM:
+ pr_err("Out of memory\n");
+ break;
+ case -ENODEV:
+ pr_warn("Could not start suspend tests on any CPU\n");
+ break;
+ }
+ }
+
+ pr_info("PSCI checker completed\n");
+ return ret < 0 ? ret : 0;
+}
+late_initcall(psci_checker);
--
2.10.0
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