* [PATCH v2 1/6] clk: stm32f4: Add LSI & LSE clocks
From: Gabriel Fernandez @ 2016-10-20 16:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161019202433.GA8871@codeaurora.org>
Hi Stephen,
On 10/19/2016 10:24 PM, Stephen Boyd wrote:
> On 10/14, gabriel.fernandez at st.com wrote:
>> @@ -292,8 +298,110 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
>> return clks[i];
>> }
>>
>> +static struct regmap *pdrm;
> This can't be part of the stm32_rgate structure?
Finally i prefer not, because i need also to disable power domain write
protection in the patch 4 (clk: stm32f4: Add RTC clock).
its will complicate the code.
BR
Gabriel
^ permalink raw reply
* [PATCH 2/3] ARM: dts: sun8i: Use the common file in NanoPi NEO SBC
From: Maxime Ripard @ 2016-10-20 16:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020080701.15993-3-woogyom.kim@gmail.com>
Hi Milo,
On Thu, Oct 20, 2016 at 05:07:00PM +0900, Milo Kim wrote:
> Cc: James Pettigrew <james@innovum.com.au>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Please add a commit log.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 1/3] ARM: dts: sun8i: Add common dtsi file for NanoPi SBCs
From: Maxime Ripard @ 2016-10-20 16:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020080701.15993-2-woogyom.kim@gmail.com>
Hi,
On Thu, Oct 20, 2016 at 05:06:59PM +0900, Milo Kim wrote:
> This patch provides a common file for NanoPi M1 and Neo SBC.
>
> Those have common features below.
> * UART0
> * 2 LEDs
> * USB host (EHCI3, OHCI3) and PHY
> * MicroSD
> * GPIO key switch
>
> Cc: James Pettigrew <james@innovum.com.au>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
> ---
> arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 143 +++++++++++++++++++++++++++++++++
> 1 file changed, 143 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
> new file mode 100644
> index 0000000..e89ca6f
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
> @@ -0,0 +1,143 @@
> +/*
> + * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
This looks like a copy of James' DT. Keeping him as the copyright
holder seems like the right thing to do.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h3.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
> +
> + status {
> + label = "nanopi:blue:status";
> + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + pwr {
> + label = "nanopi:green:pwr";
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> + };
> +
> + r_gpio_keys {
> + compatible = "gpio-keys";
> + input-name = "k1";
> + pinctrl-names = "default";
> + pinctrl-0 = <&sw_r_npi>;
> +
> + k1 at 0 {
> + label = "k1";
> + linux,code = <KEY_POWER>;
> + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> +
> +&ehci3 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
> + status = "okay";
> + vmmc-supply = <®_vcc3v3>;
> +};
> +
> +&ohci3 {
> + status = "okay";
> +};
> +
> +&pio {
> + leds_npi: led_pins at 0 {
> + allwinner,pins = "PA10";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +};
> +
> +&r_pio {
> + leds_r_npi: led_pins at 0 {
> + allwinner,pins = "PL10";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + sw_r_npi: key_pins at 0 {
> + allwinner,pins = "PL3";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&usbphy {
> + status = "okay";
> +};
> --
> 2.9.3
>
Looks good otherwise.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 8/8] ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA bridge
From: Maxime Ripard @ 2016-10-20 16:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-9-wens@csie.org>
1;4402;0c
On Thu, Oct 20, 2016 at 11:43:44AM +0800, Chen-Yu Tsai wrote:
> The Hummingbird A31 board has a RGB-to-VGA bridge which converts RGB
> output from the LCD interface to VGA signals.
>
> Enable this part of the display pipeline.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This one looks nice, but I'm going to wait for Archit answers before
merging it.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 6/8] ARM: dts: sun6i: Add device nodes for first display pipeline
From: Maxime Ripard @ 2016-10-20 16:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-7-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:42AM +0800, Chen-Yu Tsai wrote:
> The A31 has 2 parallel display pipelines, which can be intermixed.
> However the driver currently only supports one of them.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 7/8] ARM: dts: sun6i: Add A31 LCD0 RGB888 pins
From: Maxime Ripard @ 2016-10-20 16:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-8-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:43AM +0800, Chen-Yu Tsai wrote:
> The LCD0 controller on the A31 can do RGB output up to 8 bits per
> channel. Add the pins for RGB888 output.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 5/8] drm/sun4i: Add compatible strings for A31/A31s display pipelines
From: Maxime Ripard @ 2016-10-20 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-6-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:41AM +0800, Chen-Yu Tsai wrote:
> The A31's display pipeline has 2 frontends, 2 backends, and 2 TCONs. It
> also has new display enhancement blocks, such as the DRC (Dynamic Range
> Controller), the DEU (Display Enhancement Unit), and the CMU (Color
> Management Unit). It supports HDMI, MIPI DSI, and 2 LCD/LVDS channels.
>
> The A31s display pipeline is almost the same, just without MIPI DSI.
> Only the TCON seems to be different, due to the missing mux for MIPI
> DSI.
>
> Add compatible strings for both of them.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Acked-by: Rob Herring <robh@kernel.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 4/8] drm/sun4i: Add compatible string for A31/A31s TCON (timing controller)
From: Maxime Ripard @ 2016-10-20 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-5-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:40AM +0800, Chen-Yu Tsai wrote:
> The A31 TCON has mux controls for how TCON outputs are routed to the
> HDMI and MIPI DSI blocks.
>
> Since the A31s does not have MIPI DSI, it only has a mux for the HDMI
> controller input.
>
> This patch only adds support for the compatible strings. Actual support
> for the mux controls should be added with HDMI and MIPI DSI support.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 3/8] drm/sun4i: tcon: Move SoC specific quirks to a DT matched data structure
From: Maxime Ripard @ 2016-10-20 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-4-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:39AM +0800, Chen-Yu Tsai wrote:
> We already have some differences between the 2 supported SoCs.
> More will be added as we support other SoCs. To avoid bloating
> the probe function with even more conditionals, move the quirks
> to a separate data structure that's tied to the compatible string.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 2/8] drm/sun4i: sun6i-drc: Support DRC on A31 and A31s
From: Maxime Ripard @ 2016-10-20 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020034344.14154-3-wens@csie.org>
On Thu, Oct 20, 2016 at 11:43:38AM +0800, Chen-Yu Tsai wrote:
> The A31 and A31s also have the DRC as part of the display pipeline.
> As we know virtually nothing about them, just add compatible strings
> for both SoCs to the stub driver.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Acked-by: Rob Herring <robh@kernel.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [RFC PATCH] net: stmmac: Add OXNAS Glue Driver
From: Neil Armstrong @ 2016-10-20 15:54 UTC (permalink / raw)
To: linux-arm-kernel
Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../devicetree/bindings/net/oxnas-dwmac.txt | 44 ++++++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c | 173 +++++++++++++++++++++
4 files changed, 229 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/oxnas-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
diff --git a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt
new file mode 100644
index 0000000..5d2696c
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt
@@ -0,0 +1,44 @@
+* Oxford Semiconductor OXNAS DWMAC Ethernet controller
+
+The device inherits all the properties of the dwmac/stmmac devices
+described in the file stmmac.txt in the current directory with the
+following changes.
+
+Required properties on all platforms:
+
+- compatible: Depending on the platform this should be one of:
+ - "oxsemi,ox820-dwmac"
+ Additionally "snps,dwmac" and any applicable more
+ detailed version number described in net/stmmac.txt
+ should be used.
+
+- reg: The first register range should be the one of the DWMAC
+ controller.
+
+- clocks: Should contain phandles to the following clocks
+- clock-names: Should contain the following:
+ - "stmmaceth" - see stmmac.txt
+ - "gmac" - peripheral gate clock
+
+- oxsemi,sys-ctrl: a phandle to the system controller syscon node
+
+Example :
+
+etha: ethernet at 40400000 {
+ compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
+ reg = <0x40400000 0x2000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ mac-address = [000000000000]; /* Filled in by U-Boot */
+ phy-mode = "rgmii";
+
+ clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
+ clock-names = "gmac", "stmmaceth";
+ resets = <&reset RESET_MAC>;
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ status = "disabled";
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 3818c5e..27ed913 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -62,6 +62,7 @@ config DWMAC_MESON
tristate "Amlogic Meson dwmac support"
default ARCH_MESON
depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select MFD_SYSCON
help
Support for Ethernet controller on Amlogic Meson SoCs.
@@ -69,6 +70,16 @@ config DWMAC_MESON
the stmmac device driver. This driver is used for Meson6,
Meson8, Meson8b and GXBB SoCs.
+config DWMAC_OXNAS
+ tristate "Oxford Semiconductor OXNAS dwmac support"
+ default ARCH_OXNAS
+ depends on OF && COMMON_CLK && (ARCH_OXNAS || COMPILE_TEST)
+ help
+ Support for Ethernet controller on Oxford Semiconductor OXNAS SoCs.
+
+ This selects the Oxford Semiconductor OXNASSoC glue layer support for
+ the stmmac device driver. This driver is used for OX820.
+
config DWMAC_ROCKCHIP
tristate "Rockchip dwmac support"
default ARCH_ROCKCHIP
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 5d6ece5..8f83a86 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o
obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
+obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o
obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
new file mode 100644
index 0000000..c65f3a6
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
@@ -0,0 +1,173 @@
+/*
+ * Oxford Semiconductor OXNAS DWMAC glue layer
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/stmmac.h>
+
+#include "stmmac_platform.h"
+
+/* System Control regmap offsets */
+#define OXNAS_DWMAC_CTRL_REGOFFSET 0x78
+#define OXNAS_DWMAC_DELAY_REGOFFSET 0x100
+
+/* Control Register */
+#define DWMAC_CKEN_RX_IN 14
+#define DWMAC_CKEN_RXN_OUT 13
+#define DWMAC_CKEN_RX_OUT 12
+#define DWMAC_CKEN_TX_IN 10
+#define DWMAC_CKEN_TXN_OUT 9
+#define DWMAC_CKEN_TX_OUT 8
+#define DWMAC_RX_SOURCE 7
+#define DWMAC_TX_SOURCE 6
+#define DWMAC_LOW_TX_SOURCE 4
+#define DWMAC_AUTO_TX_SOURCE 3
+#define DWMAC_RGMII 2
+#define DWMAC_SIMPLE_MUX 1
+#define DWMAC_CKEN_GTX 0
+
+/* Delay register */
+#define DWMAC_TX_VARDELAY_SHIFT 0
+#define DWMAC_TXN_VARDELAY_SHIFT 8
+#define DWMAC_RX_VARDELAY_SHIFT 16
+#define DWMAC_RXN_VARDELAY_SHIFT 24
+#define DWMAC_TX_VARDELAY(d) ((d) << DWMAC_TX_VARDELAY_SHIFT)
+#define DWMAC_TXN_VARDELAY(d) ((d) << DWMAC_TXN_VARDELAY_SHIFT)
+#define DWMAC_RX_VARDELAY(d) ((d) << DWMAC_RX_VARDELAY_SHIFT)
+#define DWMAC_RXN_VARDELAY(d) ((d) << DWMAC_RXN_VARDELAY_SHIFT)
+
+struct oxnas_dwmac {
+ struct clk *clk;
+ struct regmap *regmap;
+};
+
+static int oxnas_dwmac_init(struct platform_device *pdev, void *priv)
+{
+ struct oxnas_dwmac *dwmac = priv;
+ unsigned int value;
+ int ret;
+
+ /* Reset HW here before changing the glue configuration */
+ ret = device_reset(&pdev->dev);
+ if (ret)
+ return ret;
+
+ clk_prepare_enable(dwmac->clk);
+
+ ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value);
+ if (ret < 0)
+ return ret;
+
+ /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
+ value |= BIT(DWMAC_CKEN_GTX);
+ /* Use simple mux for 25/125 Mhz clock switching */
+ value |= BIT(DWMAC_SIMPLE_MUX);
+ /* set auto switch tx clock source */
+ value |= BIT(DWMAC_AUTO_TX_SOURCE);
+ /* enable tx & rx vardelay */
+ value |= BIT(DWMAC_CKEN_TX_OUT);
+ value |= BIT(DWMAC_CKEN_TXN_OUT);
+ value |= BIT(DWMAC_CKEN_TX_IN);
+ value |= BIT(DWMAC_CKEN_RX_OUT);
+ value |= BIT(DWMAC_CKEN_RXN_OUT);
+ value |= BIT(DWMAC_CKEN_RX_IN);
+ regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value);
+
+ /* set tx & rx vardelay */
+ value = DWMAC_TX_VARDELAY(4);
+ value |= DWMAC_TXN_VARDELAY(2);
+ value |= DWMAC_RX_VARDELAY(10);
+ value |= DWMAC_RXN_VARDELAY(8);
+ regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value);
+
+ return 0;
+}
+
+static void oxnas_dwmac_exit(struct platform_device *pdev, void *priv)
+{
+ struct oxnas_dwmac *dwmac = priv;
+
+ clk_disable_unprepare(dwmac->clk);
+}
+
+static int oxnas_dwmac_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ struct device_node *sysctrl;
+ struct oxnas_dwmac *dwmac;
+ int ret;
+
+ sysctrl = of_parse_phandle(pdev->dev.of_node, "oxsemi,sys-ctrl", 0);
+ if (!sysctrl) {
+ dev_err(&pdev->dev, "failed to get sys-ctrl node\n");
+ return -EINVAL;
+ }
+
+ ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ if (ret)
+ return ret;
+
+ plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return PTR_ERR(plat_dat);
+
+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
+ if (!dwmac)
+ return -ENOMEM;
+
+ dwmac->regmap = syscon_node_to_regmap(sysctrl);
+ if (IS_ERR(dwmac->regmap)) {
+ dev_err(&pdev->dev, "failed to have sysctrl regmap\n");
+ return PTR_ERR(dwmac->regmap);
+ }
+
+ dwmac->clk = devm_clk_get(&pdev->dev, "gmac");
+ if (IS_ERR(dwmac->clk))
+ return PTR_ERR(dwmac->clk);
+
+ plat_dat->bsp_priv = dwmac;
+ plat_dat->init = oxnas_dwmac_init;
+ plat_dat->exit = oxnas_dwmac_exit;
+
+ return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+}
+
+static const struct of_device_id oxnas_dwmac_match[] = {
+ { .compatible = "oxsemi,ox820-dwmac" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, oxnas_dwmac_match);
+
+static struct platform_driver oxnas_dwmac_driver = {
+ .probe = oxnas_dwmac_probe,
+ .remove = stmmac_pltfr_remove,
+ .driver = {
+ .name = "oxnas-dwmac",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = oxnas_dwmac_match,
+ },
+};
+module_platform_driver(oxnas_dwmac_driver);
+
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_DESCRIPTION("Oxford Semiconductor OXNAS DWMAC glue layer");
+MODULE_LICENSE("GPL v2");
--
2.7.0
^ permalink raw reply related
* [linux-sunxi] [PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks
From: Chen-Yu Tsai @ 2016-10-20 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cd4dd81821b8910d40626baab2dbfdabd94b1b98.1476196031.git-series.maxime.ripard@free-electrons.com>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Add the A64 CCU clocks set.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +-
> drivers/clk/sunxi-ng/Kconfig | 11 +-
> drivers/clk/sunxi-ng/Makefile | 1 +-
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 918 +++++++++++-
> drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 72 +-
> include/dt-bindings/clock/sun50i-a64-ccu.h | 134 ++-
> include/dt-bindings/reset/sun50i-a64-ccu.h | 98 +-
> 7 files changed, 1235 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
> create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 3868458a5feb..74d44a4273f2 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,6 +7,7 @@ Required properties :
> - "allwinner,sun8i-a23-ccu"
> - "allwinner,sun8i-a33-ccu"
> - "allwinner,sun8i-h3-ccu"
> + - "allwinner,sun50i-a64-ccu"
>
> - reg: Must contain the registers base address and length
> - clocks: phandle to the oscillators feeding the CCU. Two are needed:
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 1b4c55a53d7a..8454c6e3dd65 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -53,6 +53,17 @@ config SUNXI_CCU_MP
>
> # SoC Drivers
>
> +config SUN50I_A64_CCU
> + bool "Support for the Allwinner A64 CCU"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_NK
> + select SUNXI_CCU_NKM
> + select SUNXI_CCU_NKMP
> + select SUNXI_CCU_NM
> + select SUNXI_CCU_MP
> + select SUNXI_CCU_PHASE
> + default ARM64 && ARCH_SUNXI
> +
> config SUN6I_A31_CCU
> bool "Support for the Allwinner A31/A31s CCU"
> select SUNXI_CCU_DIV
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 106cba27c331..24fbc6e5deb8 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o
> obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
>
> # SoC support
> +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
> obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
> obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
> obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> new file mode 100644
> index 000000000000..c0e96bf6d104
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -0,0 +1,918 @@
> +/*
> + * Copyright (c) 2016 Maxime Ripard. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +#include "ccu_phase.h"
> +
> +#include "ccu-sun50i-a64.h"
> +
> +static struct ccu_nkmp pll_cpux_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 5),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m = _SUNXI_CCU_DIV(0, 2),
> + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
> + .common = {
> + .reg = 0x000,
> + .hw.init = CLK_HW_INIT("pll-cpux",
> + "osc24M",
> + &ccu_nkmp_ops,
> + 0),
> + },
> +};
> +
> +/*
> + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> + * the base (2x, 4x and 8x), and one variable divider (the one true
> + * pll audio).
> + *
> + * We don't have any need for the variable divider for now, so we just
> + * hardcode it to match with the clock names
> + */
> +#define SUN50I_A64_PLL_AUDIO_REG 0x008
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
> + "osc24M", 0x008,
> + 8, 7, /* N */
> + 0, 5, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
> + "osc24M", 0x010,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
> + "osc24M", 0x018,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
> + "osc24M", 0x020,
> + 8, 5, /* N */
> + 4, 2, /* K */
> + 0, 2, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static struct ccu_nk pll_periph0_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 5),
> + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> + .fixed_post_div = 2,
> + .common = {
> + .reg = 0x028,
> + .features = CCU_FEATURE_FIXED_POSTDIV,
> + .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
> + &ccu_nk_ops, 0),
> + },
> +};
> +
> +static struct ccu_nk pll_periph1_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 5),
> + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> + .fixed_post_div = 2,
> + .common = {
> + .reg = 0x02c,
> + .features = CCU_FEATURE_FIXED_POSTDIV,
> + .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
> + &ccu_nk_ops, 0),
> + },
> +};
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
> + "osc24M", 0x030,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
> + "osc24M", 0x038,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +/*
> + * The output function can be changed to something more complex that
> + * we do not handle yet.
> + *
> + * Hardcode the mode so that we don't fall in that case.
> + */
> +#define SUN50I_A64_PLL_MIPI_REG 0x040
> +
> +struct ccu_nkm pll_mipi_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT(8, 4),
> + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> + .m = _SUNXI_CCU_DIV(0, 4),
> + .common = {
> + .reg = 0x040,
> + .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
> + &ccu_nkm_ops, 0),
> + },
> +};
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
> + "osc24M", 0x044,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
> + "osc24M", 0x048,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
> + "osc24M", 0x04c,
> + 8, 7, /* N */
> + 0, 2, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
CLK_SET_RATE_UNGATE for all the PLLs?
> +
> +static const char * const cpux_parents[] = { "osc32k", "osc24M",
> + "pll-cpux" , "pll-cpux" };
> +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> + 0x050, 16, 2, CLK_IS_CRITICAL);
CLK_SET_RATE_PARENT.
[...]
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +
Extra newline.
[...]
> +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
> +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
> + 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
The divider is only 2 bits wide.
> +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> +static const u8 tcon1_table[] = { 0, 2, };
> +struct ccu_div tcon1_clk = {
> + .enable = BIT(31),
> + .div = _SUNXI_CCU_DIV(0, 4),
> + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table),
Mux is only 2 bits wide.
> + .common = {
> + .reg = 0x11c,
> + .hw.init = CLK_HW_INIT_PARENTS("tcon1",
> + tcon1_parents,
> + &ccu_div_ops,
> + CLK_SET_RATE_PARENT),
> + },
> +};
> +
[...]
> +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
> +static const u8 dsi_dphy_table[] = { 0, 2, };
> +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
> + dsi_dphy_parents, dsi_dphy_table,
> + 0x168, 0, 3, 24, 2, BIT(31), 0);
Divider is 4 bits wide, and mux offset is 8.
[...]
Regards
ChenYu
^ permalink raw reply
* [PATCH] ahci: use pci_alloc_irq_vectors
From: Robert Richter @ 2016-10-20 15:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160906163946.GB24268@htj.duckdns.org>
On 06.09.16 12:39:46, Tejun Heo wrote:
> On Mon, Sep 05, 2016 at 05:21:45PM +0200, Christoph Hellwig wrote:
> > Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors.
> > The big advantage over the old code is that we can use the same API for
> > MSI and MSI-X, and that we don't need to store the MSI-X vector mapping
> > in driver-private data structures.
> >
> > This first conversion keeps the probe order as-is: MSI-X multi vector,
> > MSI multi vector, MSI single vector, MSI-X single vector and last a
> > single least legacy interrupt line. There is one small change of
> > behavior: we now check the "MSI Revert to Single Message" flag for
> > MSI-X in addition to MSI.
> >
> > Because the API to find the Linux IRQ number for a MSI/MSI-X vector
> > is PCI specific, but libahaci is bus-agnostic I had to a
> > get_irq_vector function pointer to struct ahci_host_priv. The
> > alternative would be to move the multi-vector case of ahci_host_activate
> > to ahci.c and just call ata_host_activate directly from the others
> > users of ahci_host_activate.
>
> Applied to libata/for-4.9 after pulling in the mainline.
Hm, this broke SATA on ThunderX. Log below.
I could not yet look into this closer but reverting this patch
helped:
0b9e2988ab22 ahci: use pci_alloc_irq_vectors
-Robert
[ 14.940982] ata1.00: qc timeout (cmd 0x27)
[ 14.941017] ata2.00: qc timeout (cmd 0x27)
[ 14.941021] ata2.00: failed to read native max address (err_mask=0x4)
[ 14.941023] ata2.00: HPA support seems broken, skipping HPA handling
[ 14.961969] ata1.00: failed to read native max address (err_mask=0x4)
[ 14.968401] ata1.00: HPA support seems broken, skipping HPA handling
[ 15.405004] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 15.437004] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 20.573007] ata2.00: qc timeout (cmd 0xef)
[ 20.573037] ata1.00: qc timeout (cmd 0xef)
[ 20.573041] ata1.00: failed to enable AA (error_mask=0x4)
[ 20.573044] ata1: limiting SATA link speed to 3.0 Gbps
[ 20.591691] ata2.00: failed to enable AA (error_mask=0x4)
[ 20.597083] ata2: limiting SATA link speed to 3.0 Gbps
[ 21.037003] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 21.043861] ata1.00: ATA-8: WDC WD5003ABYZ-011FA0, 01.01S03, max UDMA/133
[ 21.050647] ata1.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32)
[ 21.061007] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 21.067683] ata2.00: ATA-8: WDC WD5003ABYZ-011FA0, 01.01S03, max UDMA/133
[ 21.074468] ata2.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32)
[ 36.444979] ata1.00: qc timeout (cmd 0xef)
[ 36.445011] ata2.00: qc timeout (cmd 0xef)
[ 36.445014] ata2.00: failed to set xfermode (err_mask=0x4)
[ 36.445016] ata2.00: disabled
[ 36.445026] ata2: hard resetting link
[ 36.465268] ata1.00: failed to set xfermode (err_mask=0x4)
[ 36.470750] ata1.00: disabled
[ 36.473718] ata1: hard resetting link
[ 36.909003] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 36.915184] ata2: EH complete
[ 36.941013] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 36.947196] ata1: EH complete
[ 36.960294] Freeing unused kernel memory: 1024K (fffffe0001f70000 -
fffffe0002070000)
../..
[ 161.266664] dracut-initqueue[624]: Warning: dracut-initqueue timeout
- starting timeout scripts
[ 161.793311] dracut-initqueue[624]: Warning: dracut-initqueue timeout
- starting timeout scripts
[ 162.309073] dracut-initqueue[624]: Warning: dracut-initqueue timeout
- starting timeout scripts
^ permalink raw reply
* [PATCH v2 5/6] clk: stm32f469: Add QSPI clock
From: Gabriel Fernandez @ 2016-10-20 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161019203228.GC8871@codeaurora.org>
Hi Stephen
On 10/19/2016 10:32 PM, Stephen Boyd wrote:
> On 10/14, gabriel.fernandez at st.com wrote:
>> @@ -532,10 +618,42 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>> { 0 },
>> };
>>
>> +struct stm32f4_clk_data {
>> + const struct stm32f4_gate_data *gates_data;
>> + const u64 *gates_map;
>> + int gates_num;
>> +};
>> @@ -549,6 +667,19 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>> goto fail;
>> }
>>
>> + match = of_match_node(stm32f4_of_match, np);
>> + if (WARN_ON(!match))
>> + return;
>> +
>> + data = match->data;
>> +
>> + clks = kmalloc_array(data->gates_num + END_PRIMARY_CLK,
>> + sizeof(struct clk_hw *), GFP_KERNEL);
> sizeof(*clks)?
ok
>
>> + if (!clks)
>> + goto fail;
>> +
>> + stm32f4_gate_map = data->gates_map;
>> +
>> hse_clk = of_clk_get_parent_name(np, 0);
>>
>> clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
>> @@ -581,11 +712,15 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>> clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
>> 0, 1, 1);
>>
>> - for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) {
>> - const struct stm32f4_gate_data *gd = &stm32f4_gates[n];
>> - unsigned int secondary =
>> - 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx;
>> - int idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
>> + for (n = 0; n < data->gates_num; n++) {
>> + const struct stm32f4_gate_data *gd;
>> + unsigned int secondary;
>> + int idx;
>> +
>> + gd = (struct stm32f4_gate_data *) &data->gates_data[n];
> Why do we cast here? Get rid of const? Perhaps the struct
> shouldn't have const on the member instead?
we don't need cast here.
Thank's Stephen
BR
Gabriel
>
>> + secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
>> + gd->bit_idx;
>> + idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
>>
>> if (idx < 0)
^ permalink raw reply
* [PATCH] ARM: dts: sun8i: Add SPI controller node in H3
From: Maxime Ripard @ 2016-10-20 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161019134608.12850-1-woogyom.kim@gmail.com>
Hi Milo,
On Wed, Oct 19, 2016 at 10:46:08PM +0900, Milo Kim wrote:
> H3 supports two SPI controllers. Four pins (MOSI, MISO, SCLK, SS) are
> configured through the pinctrl subsystem. It is almost same as A31 SPI
> except buffer size, so those DT properties are reusable.
>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> Cc: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Ideally, this would be part of your serie to add the H3 support to the
spi driver. This way, you make it explicit that there is a dependency
between the two, and it's easier for us :)
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 75a8654..c38b028 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -381,6 +381,20 @@
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
>
> + spi0_pins: spi0 {
> + allwinner,pins = "PC0", "PC1", "PC2", "PC3";
> + allwinner,function = "spi0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + spi1_pins: spi1 {
> + allwinner,pins = "PA15", "PA16", "PA14", "PA13";
> + allwinner,function = "spi1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
This needs to be in a separate patch
> uart0_pins_a: uart0 at 0 {
> allwinner,pins = "PA4", "PA5";
> allwinner,function = "uart0";
> @@ -425,6 +439,38 @@
> clocks = <&osc24M>;
> };
>
> + spi0: spi at 01c68000 {
> + compatible = "allwinner,sun8i-h3-spi";
> + reg = <0x01c68000 0x1000>;
> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 23>, <&dma 23>;
> + dma-names = "rx", "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>;
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi at 01c69000 {
> + compatible = "allwinner,sun8i-h3-spi";
> + reg = <0x01c69000 0x1000>;
> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 24>, <&dma 24>;
> + dma-names = "rx", "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_pins>;
> + resets = <&ccu RST_BUS_SPI1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v3 5/6] ARM: sunxi: Remove useless allwinner,pull property
From: Jean-Francois Moine @ 2016-10-20 15:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <42e249454ccf6b14e9ec266cb8d42a24f6d71d7b.1476971126.git-series.maxime.ripard@free-electrons.com>
On Thu, 20 Oct 2016 15:49:06 +0200
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> The allwinner,pull property set to NO_PULL was really considered our
> default (and wasn't even changing the default value in the code).
>
> Remove these properties to make it obvious that we do not set anything in
> such a case.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/ntc-gr8-evb.dts | 4 +-
> arch/arm/boot/dts/ntc-gr8.dtsi | 14 +-----
> arch/arm/boot/dts/sun4i-a10-a1000.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 4 +-
> arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-marsboard.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-mk802.dts | 3 +-
> arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 1 +-
> arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 3 +-
> arch/arm/boot/dts/sun4i-a10.dtsi | 24 +--------
> arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 1 +-
> arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-mk802.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 2 +-
> arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +--
> arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 1 +-
> arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 3 +-
> arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 +-
> arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 1 +-
> arch/arm/boot/dts/sun5i-a13.dtsi | 3 +-
> arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +-
> arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +-
> arch/arm/boot/dts/sun5i.dtsi | 7 +--
> arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31-colombus.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31-i7.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +-
> arch/arm/boot/dts/sun6i-a31.dtsi | 13 +----
> arch/arm/boot/dts/sun6i-a31s-primo81.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 1 +-
> arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-bananapi.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-bananapro.dts | 5 +--
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 +--
> arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-m3.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-orangepi.dts | 4 +-
> arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 3 +-
> arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 1 +-
> arch/arm/boot/dts/sun7i-a20.dtsi | 37 +------------
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 +---
> arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 1 +-
> arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 1 +-
> arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 1 +-
> arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 3 +-
> arch/arm/boot/dts/sun8i-a33.dtsi | 1 +-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 3 +-
> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 2 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 1 +-
> arch/arm/boot/dts/sun8i-h3.dtsi | 12 +----
> arch/arm/boot/dts/sun8i-r16-parrot.dts | 3 +-
> arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +-
> arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 1 +-
> arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 +-
> arch/arm/boot/dts/sun9i-a80.dtsi | 6 +--
> arch/arm/boot/dts/sunxi-common-regulators.dtsi | 4 +-
> 85 files changed, 0 insertions(+), 302 deletions(-)
[snip]
Is it really usefull to change all these files while in a previous
patch you were writing:
> The generic pin configuration and multiplexing should be preferred now,
> even though we still support the old one.
?
--
Ken ar c'henta? | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
^ permalink raw reply
* [PATCH v2] ARM: at91/dt: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx
From: Alexandre Belloni @ 2016-10-20 15:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161016162145.26193-2-sylvain.rochet@finsecur.com>
On 16/10/2016 at 18:21:45 +0200, Sylvain Rochet wrote :
> Remove pullup on dbgu DTXD signal, it is a push-pull output thus the
> pullup is pointless.
>
> Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left
> floating and so consuming a useless extra amount of power in crowbarred
> state if nothing is externally connected to dbgu.
>
> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
> ---
> arch/arm/boot/dts/at91rm9200.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9260.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9261.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9263.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9g45.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++--
> arch/arm/boot/dts/sama5d3.dtsi | 4 ++--
> arch/arm/boot/dts/sama5d4.dtsi | 4 ++--
> 10 files changed, 20 insertions(+), 20 deletions(-)
>
Applied, thanks.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH 0/4] ARM: boot: mxs: Add On-Chip RAM
From: Stefan Wahren @ 2016-10-20 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473789066-8955-1-git-send-email-stefan.wahren@i2se.com>
Am 13.09.2016 um 19:51 schrieb Stefan Wahren:
> The i.MX23 / i.MX28 have a small amount of On-Chip RAM which is also necessary
> for suspend to RAM and standby mode. But before we need to remove the fake reg
> properties of all internal bus nodes as discussed in this thread [1].
>
> This patch series requires Fabio Estevam's recent series "ARM: dts: imx23:
> Remove skeleton.dtsi inclusion" [2].
>
> [1] - https://marc.info/?l=devicetree&m=146139948426520&w=2
> [2] - http://www.spinics.net/lists/arm-kernel/msg528974.html
>
> Stefan Wahren (4):
> ARM: dts: imx23: Remove fake "reg" properties from bus nodes
> ARM: dts: imx28: Remove fake "reg" properties from bus nodes
> ARM: dts: imx23: add On-Chip RAM
> ARM: dts: imx28: add On-Chip RAM
>
> arch/arm/boot/dts/imx23-evk.dts | 8 ++++----
> arch/arm/boot/dts/imx23-olinuxino.dts | 8 ++++----
> arch/arm/boot/dts/imx23-sansa.dts | 8 ++++----
> arch/arm/boot/dts/imx23-stmp378x_devb.dts | 6 +++---
> arch/arm/boot/dts/imx23-xfi3.dts | 8 ++++----
> arch/arm/boot/dts/imx23.dtsi | 15 +++++++++------
> arch/arm/boot/dts/imx28-apf28.dts | 8 ++++----
> arch/arm/boot/dts/imx28-apf28dev.dts | 8 ++++----
> arch/arm/boot/dts/imx28-apx4devkit.dts | 8 ++++----
> arch/arm/boot/dts/imx28-cfa10036.dts | 8 ++++----
> arch/arm/boot/dts/imx28-cfa10037.dts | 8 ++++----
> arch/arm/boot/dts/imx28-cfa10049.dts | 10 +++++-----
> arch/arm/boot/dts/imx28-cfa10055.dts | 6 +++---
> arch/arm/boot/dts/imx28-cfa10056.dts | 4 ++--
> arch/arm/boot/dts/imx28-cfa10057.dts | 10 +++++-----
> arch/arm/boot/dts/imx28-cfa10058.dts | 10 +++++-----
> arch/arm/boot/dts/imx28-duckbill.dts | 8 ++++----
> arch/arm/boot/dts/imx28-evk.dts | 8 ++++----
> arch/arm/boot/dts/imx28-m28.dtsi | 6 +++---
> arch/arm/boot/dts/imx28-m28cu3.dts | 8 ++++----
> arch/arm/boot/dts/imx28-m28evk.dts | 8 ++++----
> arch/arm/boot/dts/imx28-sps1.dts | 8 ++++----
> arch/arm/boot/dts/imx28.dtsi | 17 +++++++++--------
> 23 files changed, 100 insertions(+), 96 deletions(-)
>
Any comments about this series or should i resend it without Fabio's
patch series applied?
^ permalink raw reply
* [PATCH v14 3/9] clocksource/drivers/arm_arch_timer: Improve printk relevant code
From: Mark Rutland @ 2016-10-20 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475086637-1914-4-git-send-email-fu.wei@linaro.org>
On Thu, Sep 29, 2016 at 02:17:11AM +0800, fu.wei at linaro.org wrote:
> static void arch_timer_banner(unsigned type)
> {
> - pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
> - type & ARCH_CP15_TIMER ? "cp15" : "",
> - type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
> - type & ARCH_MEM_TIMER ? "mmio" : "",
> - (unsigned long)arch_timer_rate / 1000000,
> - (unsigned long)(arch_timer_rate / 10000) % 100,
> - type & ARCH_CP15_TIMER ?
> - (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
> - "",
> - type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
> - type & ARCH_MEM_TIMER ?
> - arch_timer_mem_use_virtual ? "virt" : "phys" :
> - "");
> + pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
> + type & ARCH_CP15_TIMER ? "cp15" : "",
> + type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
> + type & ARCH_MEM_TIMER ? "mmio" : "",
> + (unsigned long)arch_timer_rate / 1000000,
> + (unsigned long)(arch_timer_rate / 10000) % 100,
> + type & ARCH_CP15_TIMER ?
> + (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
> + "",
Please restore the additional indent on this line...
> + type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
> + type & ARCH_MEM_TIMER ?
> + arch_timer_mem_use_virtual ? "virt" : "phys" :
> + "");
... and these two.
No matter what checkpatch says, I prefer the code that way so as to keep
the ternary clear.
[...]
> @@ -768,7 +769,7 @@ static int __init arch_timer_init(void)
> return ret;
>
> arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
> -
> +
Please mention the whitespace fixup in the commit message. It's
surprising otherwise.
With all that:
Acked-by: Mark Rutland <mark.rutland@arm.com>
Thanks,
Mark.
^ permalink raw reply
* [PATCH 4/4] ARM: dts: stm32f429: remove Ethernet wake on Lan support
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
This patch removes WoL (Wake on Lan) support as it is not yet
fully supported and tested.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 6350117b..ad0bc6a 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -377,8 +377,8 @@
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
- interrupts = <61>, <62>;
- interrupt-names = "macirq", "eth_wake_irq";
+ interrupts = <61>;
+ interrupt-names = "macirq";
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
--
1.9.1
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: stm32f429: Fix Ethernet node on Eval Board
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
"phy-handle" entry is mandatory when mdio subnode is used in
Ethernet node.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index fa30bf1..a11b108 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -99,7 +99,7 @@
pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
phy-mode = "mii";
-
+ phy-handle = <&phy1>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
^ permalink raw reply related
* [PATCH 2/4] ARM: dts: stm32f429: Update Ethernet node on Eval board
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
Update new pinctrl phandle name and use new node name.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 13c7cd2..fa30bf1 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -94,11 +94,12 @@
clock-frequency = <25000000>;
};
-ðernet0 {
+&mac {
status = "okay";
- pinctrl-0 = <ðernet0_mii>;
+ pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
- phy-mode = "mii-id";
+ phy-mode = "mii";
+
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
^ permalink raw reply related
* [PATCH 1/4] ARM: dts: stm32f429: Align Ethernet node with new bindings properties
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476976886-23781-1-git-send-email-alexandre.torgue@st.com>
This patch aligns clocks names and node reference according to new
stm32-dwmac glue binding. It also renames Ethernet pinctrl phandle
(indeed there is no need to add 0 as Ethernet instance as there is only
one IP in SOC).
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 336ee4f..6350117b 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -313,7 +313,7 @@
};
};
- ethernet0_mii: mii at 0 {
+ ethernet_mii: mii at 0 {
pins {
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
@@ -373,13 +373,13 @@
st,mem2mem;
};
- ethernet0: dwmac at 40028000 {
+ mac: ethernet at 40028000 {
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
- clock-names = "stmmaceth", "tx-clk", "rx-clk";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
snps,pbl = <8>;
--
1.9.1
^ permalink raw reply related
* [PATCH 0/4] STM32F429: Add Ethernet fixes
From: Alexandre TORGUE @ 2016-10-20 15:21 UTC (permalink / raw)
To: linux-arm-kernel
This series adds several fixes for Ethernet for stm32f429 MCU.
First 2 patches have already been reviewed some months ago when
stm32 Ethernet glue has been pushed (I added in this series to keep
history). Fixes are:
-Change DT to be compliant to stm32 ethernet glue binding
-Add phy-handle to correctly use mdio subnode
-Remove WoL support
Regards
Alex
Alexandre TORGUE (4):
ARM: dts: stm32f429: Align Ethernet node with new bindings properties
ARM: dts: stm32f429: Update Ethernet node on Eval board
ARM: dts: stm32f429: Fix Ethernet node on Eval Board
ARM: dts: stm32f429: remove Ethernet wake on Lan support
arch/arm/boot/dts/stm32429i-eval.dts | 7 ++++---
arch/arm/boot/dts/stm32f429.dtsi | 10 +++++-----
2 files changed, 9 insertions(+), 8 deletions(-)
--
1.9.1
^ permalink raw reply
* [GIT PULL] STi defconfig updates for v4.10
From: Patrice Chotard @ 2016-10-20 15:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Arnd and Kevin,
Please consider this first round of multi_v7_defconfig updates for v4.10 :
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git tags/sti-defconfig-for-4.10
for you to fetch changes up to 620c52f4db4d47e1f33c64e641392fe575d5397f:
ARM: multi_v7_defconfig: Remove stih41x phy Kconfig symbol. (2016-10-20 17:05:08 +0200)
----------------------------------------------------------------
Remove STiH415/416 specific IPs
As STiH415/416 have been removed from kernel, remove IPs only found
on these socs, remove CONFIG_PHY_MIPHY365X and CONFIG_PHY_STIH41X_USB.
----------------------------------------------------------------
Peter Griffin (2):
ARM: multi_v7_defconfig: Remove miphy365 phy Kconfig symbol.
ARM: multi_v7_defconfig: Remove stih41x phy Kconfig symbol.
arch/arm/configs/multi_v7_defconfig | 2 --
1 file changed, 2 deletions(-)
^ permalink raw reply
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