* [PATCH -next] net: ethernet: mediatek: use dev_kfree_skb_any instead of dev_kfree_skb
From: Wei Yongjun @ 2016-10-20 17:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Wei Yongjun <weiyongjun1@huawei.com>
Replace dev_kfree_skb with dev_kfree_skb_any in mtk_start_xmit()
which can be called from hard irq context (netpoll) and from
other contexts. mtk_start_xmit() only frees skbs that it has
dropped.
This is detected by Coccinelle semantic patch.
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 8f80e61..d716274 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -843,7 +843,7 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
drop:
spin_unlock(ð->page_lock);
stats->tx_dropped++;
- dev_kfree_skb(skb);
+ dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
}
^ permalink raw reply related
* [PATCH v2] ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
From: Eric Anholt @ 2016-10-20 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdb++5Xb6a=0Zz5eZURNmrkfVyvsBR-pLK9iRiyTu1g8Rw@mail.gmail.com>
Linus Walleij <linus.walleij@linaro.org> writes:
> On Tue, Oct 18, 2016 at 10:44 PM, Gottfried Haider
> <gottfried.haider@gmail.com wrote:
>
>> Regarding the proposed format using the header pin numbers: From what I've
>> seen in terms of existing educational materials, it seems the overwhelming
>> majority ends up using GPIO numbers instead of physical pin header
>> numbering. (e.g. [1] [2])
>
> What does that number mean? If you are referring to the global
> GPIO numberspace it is obsolete and just reflecting the fact that
> people up until now was referring to Linux-internal GPIO numbers.
The number within the SOC's GPIOs. Until the 8-line expander that's
been hung off the SOC GPIOs in the Pi3, they were the only GPIOs in the
system.
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* [PATCH 3/8] ARM: gr8: Add the UART3
From: Maxime Ripard @ 2016-10-20 17:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65iR=mZyCQrF64HOku5Sq7fNKGhV=Yy3zUFYzB=4ozkWg@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:06:47PM +0800, Chen-Yu Tsai wrote:
> On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The GR8 has access to the UART3 controller, which was missing in the
> > DTSI. Add it.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 4/8] ARM: gr8: Fix typo in the i2s mclk pin group
From: Maxime Ripard @ 2016-10-20 17:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65P6WEZCy8AXCk5mV4gWgiWuZJiDZzJnEgr+sj9qf8ORA@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:07:46PM +0800, Chen-Yu Tsai wrote:
> On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > There was a dumb copy and paste mistake here, fix it.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 5/8] ARM: gr8: Add missing pwm channel 1 pin
From: Maxime Ripard @ 2016-10-20 17:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v66w0sTzn_SWH4rrpWKOosSxALV8ot3CBQbGhwLxvX1vxw@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:10:03PM +0800, Chen-Yu Tsai wrote:
> On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The PWM controller has two different channels, but only the first pin was
> > exposed in the DTSI. Add the other one.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
>
> > ---
> > arch/arm/boot/dts/ntc-gr8.dtsi | 7 +++++++
> > 1 file changed, 7 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/arm/boot/dts/ntc-gr8.dtsi
> > index 74aff795e723..fad7381630f3 100644
> > --- a/arch/arm/boot/dts/ntc-gr8.dtsi
> > +++ b/arch/arm/boot/dts/ntc-gr8.dtsi
> > @@ -854,6 +854,13 @@
> > allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> > };
> >
> > + pwm1_pins_a: pwm1 at 0 {
>
> Nit: really don't need "_a" and "@0" here.
Fixed and applied.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 6/8] ARM: gr8: Add UART2 pins
From: Maxime Ripard @ 2016-10-20 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v641SWJTG=3AmHE3zAypuoq7fL7gFLBXwfXpmCYw7K0Guw@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:14:09PM +0800, Chen-Yu Tsai wrote:
> On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The UART2 pins were missing from the DTSI. Add them.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 7/8] ARM: gr8: Add UART3 pins
From: Maxime Ripard @ 2016-10-20 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65OXss+_jKMSJD-KUDeK2iH96mmvDvPEzgW60PUXoS90g@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:16:11PM +0800, Chen-Yu Tsai wrote:
> On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The UART3 pins were missing from the DTSI. Add them.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 8/8] ARM: gr8: Add CHIP Pro support
From: Maxime Ripard @ 2016-10-20 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67S8rK6Hdkvkgtfz6hDtiR4a4yUUqB01AnQ4sJ3-SQc0A@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:26:09PM +0800, Chen-Yu Tsai wrote:
> On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The CHIP Pro is a small embeddable board. It features a GR8, an AXP209
> > PMIC, a 512MB SLC NAND and a WiFi/BT chip.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied. Thanks for reviewing!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [GIT PULL] arm64: fixes for -rc2
From: Will Deacon @ 2016-10-20 17:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
Please pull these arm64 fixes for -rc2. Most of these are CC'd for
stable, but there are a few fixing issues introduced during the recent
merge window too. There's also a fix for the xgene PMU driver, but it
seemed daft to send as a separate pull request, so I've included it
here with the rest of the fixes. More details in the tag.
Thanks,
Will
--->8
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git tags/arm64-fixes
for you to fetch changes up to f7881bd644474a4a62d7bd1ec801176f635f59ae:
arm64: remove pr_cont abuse from mem_init (2016-10-20 15:27:56 +0100)
----------------------------------------------------------------
arm64 fixes:
- Fix ACPI boot due to recent broken NUMA changes
- Fix remote enabling of CPU features requiring PSTATE bit manipulation
- Add address range check when emulating user cache maintenance
- Fix LL/SC loops that allow compiler to introduce memory accesses
- Fix recently added write_sysreg_s macro
- Ensure MDCR_EL2 is initialised on qemu targets without a PMU
- Avoid kaslr breakage due to MODVERSIONs and DYNAMIC_FTRACE
- Correctly drive recent ld when building relocatable Image
- Remove junk IS_ERR check from xgene PMU driver added during merge window
- pr_cont fixes after core changes in the merge window
----------------------------------------------------------------
Andre Przywara (1):
arm64: Cortex-A53 errata workaround: check for kernel addresses
Ard Biesheuvel (3):
arm64: kaslr: fix breakage with CONFIG_MODVERSIONS=y
arm64: kaslr: keep modules close to the kernel when DYNAMIC_FTRACE=y
arm64: kernel: force ET_DYN ELF type for CONFIG_RELOCATABLE=y
James Morse (3):
arm64: cpufeature: Schedule enable() calls instead of calling them via IPI
arm64: mm: Set PSTATE.PAN from the cpu_enable_pan() call
arm64: suspend: Reconfigure PSTATE after resume from idle
Lorenzo Pieralisi (1):
arm64: kernel: numa: fix ACPI boot cpu numa node mapping
Marc Zyngier (1):
arm64: kernel: Init MDCR_EL2 even in the absence of a PMU
Mark Rutland (2):
arm64: fix show_regs fallout from KERN_CONT changes
arm64: remove pr_cont abuse from mem_init
Tai Nguyen (1):
perf: xgene: Remove bogus IS_ERR() check
Will Deacon (3):
arm64: sysreg: Fix use of XZR in write_sysreg_s
arm64: swp emulation: bound LL/SC retries before rescheduling
arm64: percpu: rewrite ll/sc loops in assembly
arch/arm64/Kconfig | 2 +-
arch/arm64/Makefile | 2 +-
arch/arm64/include/asm/cpufeature.h | 2 +-
arch/arm64/include/asm/exec.h | 3 +
arch/arm64/include/asm/module.h | 5 ++
arch/arm64/include/asm/percpu.h | 120 ++++++++++++++++-------------------
arch/arm64/include/asm/processor.h | 6 +-
arch/arm64/include/asm/sysreg.h | 2 +-
arch/arm64/include/asm/uaccess.h | 8 +++
arch/arm64/kernel/armv8_deprecated.c | 36 +++++++----
arch/arm64/kernel/cpu_errata.c | 3 +-
arch/arm64/kernel/cpufeature.c | 10 ++-
arch/arm64/kernel/head.S | 3 +-
arch/arm64/kernel/process.c | 18 ++++--
arch/arm64/kernel/smp.c | 1 +
arch/arm64/kernel/suspend.c | 11 ++++
arch/arm64/kernel/traps.c | 30 +++++----
arch/arm64/mm/fault.c | 15 ++++-
arch/arm64/mm/init.c | 26 ++++----
drivers/perf/xgene_pmu.c | 2 +-
20 files changed, 184 insertions(+), 121 deletions(-)
^ permalink raw reply
* [linux-sunxi] [PATCH v4 1/9] clk: sunxi-ng: Rename the internal structures
From: Maxime Ripard @ 2016-10-20 17:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65VpRU8pp_Y4RtquSj-gdJbf5S2jK5HqHKF3RnZEODmMg@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:27:48PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Rename the structures meant to be embedded in other structures to make it
> > consistent with the mux structure name
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v4 2/9] clk: sunxi-ng: Remove the use of rational computations
From: Maxime Ripard @ 2016-10-20 17:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65=xM3HpV05zt+q2vshX49MGkB88s7cfpwVYASodK11Nw@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:30:36PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > While the rational library works great, it doesn't really allow us to add
> > more constraints, like the minimum.
> >
> > Remove that in order to be able to deal with the constraints we'll need.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/clk/sunxi-ng/Kconfig | 3 +--
> > drivers/clk/sunxi-ng/ccu_nkm.c | 31 +++++++++-----------
> > drivers/clk/sunxi-ng/ccu_nkmp.c | 45 +++++++++++++---------------
> > drivers/clk/sunxi-ng/ccu_nm.c | 54 +++++++++++++++++++++++++---------
> > 4 files changed, 78 insertions(+), 55 deletions(-)
> >
>
> [...]
>
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > index 9769dee99511..4b457d8cce11 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > @@ -9,16 +9,15 @@
> > */
> >
> > #include <linux/clk-provider.h>
> > -#include <linux/rational.h>
> >
> > #include "ccu_gate.h"
> > #include "ccu_nkmp.h"
> >
> > struct _ccu_nkmp {
> > - unsigned long n, max_n;
> > - unsigned long k, max_k;
> > - unsigned long m, max_m;
> > - unsigned long p, max_p;
> > + unsigned long n, min_n, max_n;
> > + unsigned long k, min_k, max_k;
> > + unsigned long m, min_m, max_m;
> > + unsigned long p, min_p, max_p;
>
> Wrong patch? Otherwise,
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Indeed, fixed and applied.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v4 3/9] clk: sunxi-ng: Finish to convert to structures for arguments
From: Maxime Ripard @ 2016-10-20 17:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67CWEEcC+AQ9MqsyKokTx2ZVXKqBSUFW_x7CfjHrL_JFA@mail.gmail.com>
On Thu, Oct 20, 2016 at 10:35:18PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Some clocks still use an explicit list of arguments, which make it a bit
> > more tedious to add new parameters.
> >
> > Convert those over to a structure pointer argument to add as many
> > arguments as possible without having to many noise in our patches, or a
> > very long list of arguments.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v4 4/9] clk: sunxi-ng: Add minimums for all the relevant structures and clocks
From: Maxime Ripard @ 2016-10-20 17:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v64itwTvMoxvtYDqOALL-XJYvhv-5daPPjPzb9DfY3o62A@mail.gmail.com>
On Thu, Oct 20, 2016 at 11:04:18PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Modify the current clocks we have to be able to specify the minimum for
> > each clocks we support, just like we support the max.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
>
> Including the bits from patch 2.
Applied with those bits merged in this patch.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH] ARM: imx: gpc: Initialize all power domains
From: Fabio Estevam @ 2016-10-20 17:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161019141556.GA18806@tiger>
Hi Shawn,
On Wed, Oct 19, 2016 at 12:15 PM, Shawn Guo <shawnguo@kernel.org> wrote:
> It's not clear to me why this is only with multi_v7_defconfig, not
> imx_v6_v7_defconfig. Also, is it a regression or long-standing issue?
Investigated this a bit further and the problem seems to be in the
power domain driver.
The change below fixes the problem on mx6:
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index e023066..461d03c 100644
--- a/drivers/base/power/domain.c
+++ b/drivers/base/power/domain.c
@@ -1572,8 +1572,6 @@ int of_genpd_add_provider_onecell(struct device_node *np,
for (i = 0; i < data->num_domains; i++) {
if (!data->domains[i])
continue;
- if (!pm_genpd_present(data->domains[i]))
- goto error;
data->domains[i]->provider = &np->fwnode;
data->domains[i]->has_provider = true;
, will submit this to the power domain folks.
^ permalink raw reply related
* [PATCH v4 5/9] clk: sunxi-ng: Implement minimum for multipliers
From: Maxime Ripard @ 2016-10-20 17:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67Mo41RHiWd=9+ggcDDmWJ2Miyo17Nni3p3mmAzoJng3w@mail.gmail.com>
On Thu, Oct 20, 2016 at 11:06:21PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Allow the CCU drivers to specify a multiplier for their clocks.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/clk/sunxi-ng/ccu_mult.c | 2 +-
> > drivers/clk/sunxi-ng/ccu_mult.h | 13 +++++++++----
> > drivers/clk/sunxi-ng/ccu_nk.c | 8 ++++----
> > drivers/clk/sunxi-ng/ccu_nkm.c | 8 ++++----
> > drivers/clk/sunxi-ng/ccu_nkmp.c | 4 ++--
> > drivers/clk/sunxi-ng/ccu_nm.c | 2 +-
> > 6 files changed, 21 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> > index 6a02ffee5386..678b6cb49f01 100644
> > --- a/drivers/clk/sunxi-ng/ccu_mult.c
> > +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> > @@ -105,7 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
> > ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
> > &parent_rate);
> >
> > - _cm.min = 1;
> > + _cm.min = cm->mult.min;
> > _cm.max = 1 << cm->mult.width;
> > ccu_mult_find_best(parent_rate, rate, &_cm);
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> > index 113780b7558e..c1a2134bdc71 100644
> > --- a/drivers/clk/sunxi-ng/ccu_mult.h
> > +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> > @@ -7,14 +7,19 @@
> > struct ccu_mult_internal {
> > u8 shift;
> > u8 width;
> > + u8 min;
> > };
> >
> > -#define _SUNXI_CCU_MULT(_shift, _width) \
> > - { \
> > - .shift = _shift, \
> > - .width = _width, \
> > +#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> > + { \
> > + .shift = _shift, \
> > + .width = _width, \
> > + .min = _min, \
> > }
> >
> > +#define _SUNXI_CCU_MULT(_shift, _width) \
> > + _SUNXI_CCU_MULT_MIN(_shift, _width, 1)
> > +
> > struct ccu_mult {
> > u32 enable;
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> > index a42d870ba0ef..eaf0fdf78d2b 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nk.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> > @@ -97,9 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
> > if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > rate *= nk->fixed_post_div;
> >
> > - _nk.min_n = 1;
> > + _nk.min_n = nk->n.min;
> > _nk.max_n = 1 << nk->n.width;
> > - _nk.min_k = 1;
> > + _nk.min_k = nk->k.min;
> > _nk.max_k = 1 << nk->k.width;
> >
> > ccu_nk_find_best(*parent_rate, rate, &_nk);
> > @@ -122,9 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
> > if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > rate = rate * nk->fixed_post_div;
> >
> > - _nk.min_n = 1;
> > + _nk.min_n = nk->n.min;
> > _nk.max_n = 1 << nk->n.width;
> > - _nk.min_k = 1;
> > + _nk.min_k = nk->k.min;
> > _nk.max_k = 1 << nk->k.width;
> >
> > ccu_nk_find_best(parent_rate, rate, &_nk);
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> > index b2a5fccf2f8c..715b49211ddb 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> > @@ -100,9 +100,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> > struct ccu_nkm *nkm = data;
> > struct _ccu_nkm _nkm;
> >
> > - _nkm.min_n = 1;
> > + _nkm.min_n = nkm->n.min;
> > _nkm.max_n = 1 << nkm->n.width;
> > - _nkm.min_k = 1;
> > + _nkm.min_n = nkm->k.min;
>
> Typo here.
>
> > _nkm.max_k = 1 << nkm->k.width;
> > _nkm.min_m = 1;
> > _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> > @@ -129,9 +129,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
> > unsigned long flags;
> > u32 reg;
> >
> > - _nkm.min_n = 1;
> > + _nkm.min_n = nkm->n.min;
> > _nkm.max_n = 1 << nkm->n.width;
> > - _nkm.min_k = 1;
> > + _nkm.min_n = nkm->k.min;
>
> And here.
>
> > _nkm.max_k = 1 << nkm->k.width;
> > _nkm.min_m = 1;
> > _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > index 2c1398192e48..7968e0bac5db 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > @@ -107,9 +107,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
> > struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
> > struct _ccu_nkmp _nkmp;
> >
> > - _nkmp.min_n = 1;
> > + _nkmp.min_n = nkmp->n.min;
> > _nkmp.max_n = 1 << nkmp->n.width;
> > - _nkmp.min_k = 1;
> > + _nkmp.min_n = nkmp->k.min;
>
> And here.
>
> > _nkmp.max_k = 1 << nkmp->k.width;
> > _nkmp.min_m = 1;
> > _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> > diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> > index 2a190bc032a9..b1f3f0e8899d 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> > @@ -93,7 +93,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
> > struct ccu_nm *nm = hw_to_ccu_nm(hw);
> > struct _ccu_nm _nm;
> >
> > - _nm.min_n = 1;
> > + _nm.min_n = nm->n.min;
> > _nm.max_n = 1 << nm->n.width;
> > _nm.min_m = 1;
> > _nm.max_m = nm->m.max ?: 1 << nm->m.width;
> > --
> > git-series 0.8.10
>
> Otherwise,
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Fixed and applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v14 00/16] KVM PCIe/MSI passthrough on ARM/ARM64
From: Will Deacon @ 2016-10-20 17:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476278544-3397-1-git-send-email-eric.auger@redhat.com>
Hi Eric,
Thanks for posting this.
On Wed, Oct 12, 2016 at 01:22:08PM +0000, Eric Auger wrote:
> This is the second respin on top of Robin's series [1], addressing Alex' comments.
>
> Major changes are:
> - MSI-doorbell API now is moved to DMA IOMMU API following Alex suggestion
> to put all API pieces at the same place (so eventually in the IOMMU
> subsystem)
> - new iommu_domain_msi_resv struct and accessor through DOMAIN_ATTR_MSI_RESV
> domain with mirror VFIO capability
> - more robustness I think in the VFIO layer
> - added "iommu/iova: fix __alloc_and_insert_iova_range" since with the current
> code I failed allocating an IOVA page in a single page domain with upper part
> reserved
>
> IOVA range exclusion will be handled in a separate series
>
> The priority really is to discuss and freeze the API and especially the MSI
> doorbell's handling. Do we agree to put that in DMA IOMMU?
>
> Note: the size computation does not take into account possible page overlaps
> between doorbells but it would add quite a lot of complexity i think.
>
> Tested on AMD Overdrive (single GICv2m frame) with I350 VF assignment.
Marc, Robin and I sat down and had a look at the series and, whilst it's
certainly addressing a problem that we desperately want to see fixed, we
think that it's slightly over-engineering in places and could probably
be simplified in the interest of getting something upstream that can be
used as a base, on which the ABI can be extended as concrete use-cases
become clear.
Stepping back a minute, we're trying to reserve some of the VFIO virtual
address space so that it can be used by devices to map their MSI doorbells
using the SMMU. With your patches, this requires that (a) the kernel
tells userspace about the size and alignment of the doorbell region
(MSI_RESV) and (b) userspace tells the kernel the VA-range that can be
used (RESERVED_MSI_IOVA).
However, this is all special-cased for MSI doorbells and there are
potentially other regions of the VFIO address space that are reserved
and need to be communicated to userspace as well. We already know of
hardware where the PCI RC intercepts p2p accesses before they make it
to the SMMU, and other hardware where the MSI doorbell is at a fixed
address. This means that we need a mechanism to communicate *fixed*
regions of virtual address space that are reserved by VFIO. I don't
even particularly care if VFIO_MAP_DMA enforces that, but we do need
a way to tell userspace "hey, you don't want to put memory here because
it won't work well with devices".
In that case, we end up with something like your MSI_RESV capability,
but actually specifying a virtual address range that is simply not to
be used by MAP_DMA -- we don't say anything about MSIs. Now, taking this
to its logical conclusion, we no longer need to distinguish between
remappable reserved regions and fixed reserved regions in the ABI.
Instead, we can have the kernel allocate the virtual address space for
the remappable reserved regions (probably somewhere in the bottom 4GB)
and expose them via the capability. This simplifies things in the
following ways:
* You don't need to keep track of MSI vs DMA addresses in the VFIO rbtree
* You don't need to try collapsing doorbells into a single region
* You don't need a special MAP flavour to map MSI doorbells
* The ABI is reusable for PCI p2p and fixed doorbells
I really think it would make your patch series both generally useful and
an awful lot smaller, whilst leaving the door open to ABI extension on
a case-by-case basis when we determine that it's really needed.
Thoughts?
Will
^ permalink raw reply
* [PATCH] Revert "dmaengine: pxa_dma: add support for legacy transition"
From: Robert Jarzmik @ 2016-10-20 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8371252.IL4ByDpZCD@wuerfel>
Arnd Bergmann <arnd@arndb.de> writes:
> On Tuesday, October 18, 2016 8:46:32 AM CEST Robert Jarzmik wrote:
>> This reverts commit c91134d9194478144ba579ca6efeddf628055650.
>>
>> The conversion of the pxa architecture is now finished for all
>> drivers, so this functions has fullfilled its purpose and can
>> now be removed.
>>
>> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
>
> Nice!
>
> That reminds me, do you have plans to work on the conversion away from
> IORESOURCE_DMA and pxad_filter_fn towards the dma_slave_map interface?
>
> I see that all pxa drivers already use dma_request_slave_channel_compat,
> so this should be fairly straightforward to do, changing only the
> driver and the arch/arm/mach-pxa/devices.c file.
I didn't so far, as I wasn't aware of this interface, but I'll gladly put that
on my todo list.
Cheers.
--
Robert
^ permalink raw reply
* [PATCH V6 00/10] dmaengine: qcom_hidma: add MSI interrupt support
From: Sinan Kaya @ 2016-10-20 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020164321.GZ2467@localhost>
On 10/20/2016 9:43 AM, Vinod Koul wrote:
>> slave-dma git://git.infradead.org/users/vkoul/slave-dma.git (fetch)
>> > slave-dma git://git.infradead.org/users/vkoul/slave-dma.git (push)
> You seem to have missed topic/qcom which I pushed last night. next would have worked too!!
>
OK. Let me pick that up and test.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH 1/4] ARM64: dts: meson-gxbb: add MMC support
From: Kevin Hilman @ 2016-10-20 17:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476963777-1804-2-git-send-email-narmstrong@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> From: Kevin Hilman <khilman@baylibre.com>
>
> Add binding and basic support for the SD/eMMC controller on Amlogic
> S905/GXBB devices.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
nit: you added a couple things from my original patch, and it's
customary to make a summary note of changes in the changelog, so before
applying, I added a line here:
[narmstrong: added nodes for GX, enabled SDIO on P20x]
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Applied to v4.10/dt64
Kevin
^ permalink raw reply
* [linux-sunxi] [PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks
From: Maxime Ripard @ 2016-10-20 17:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67YnusPeJhQ-__ntW1MsVc6QMj4DY0YQn71xFteHDW3OA@mail.gmail.com>
On Thu, Oct 20, 2016 at 11:50:21PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Add the A64 CCU clocks set.
> >
> > Acked-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +-
> > drivers/clk/sunxi-ng/Kconfig | 11 +-
> > drivers/clk/sunxi-ng/Makefile | 1 +-
> > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 918 +++++++++++-
> > drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 72 +-
> > include/dt-bindings/clock/sun50i-a64-ccu.h | 134 ++-
> > include/dt-bindings/reset/sun50i-a64-ccu.h | 98 +-
> > 7 files changed, 1235 insertions(+), 0 deletions(-)
> > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
> > create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
> > create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> > index 3868458a5feb..74d44a4273f2 100644
> > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> > @@ -7,6 +7,7 @@ Required properties :
> > - "allwinner,sun8i-a23-ccu"
> > - "allwinner,sun8i-a33-ccu"
> > - "allwinner,sun8i-h3-ccu"
> > + - "allwinner,sun50i-a64-ccu"
> >
> > - reg: Must contain the registers base address and length
> > - clocks: phandle to the oscillators feeding the CCU. Two are needed:
> > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> > index 1b4c55a53d7a..8454c6e3dd65 100644
> > --- a/drivers/clk/sunxi-ng/Kconfig
> > +++ b/drivers/clk/sunxi-ng/Kconfig
> > @@ -53,6 +53,17 @@ config SUNXI_CCU_MP
> >
> > # SoC Drivers
> >
> > +config SUN50I_A64_CCU
> > + bool "Support for the Allwinner A64 CCU"
> > + select SUNXI_CCU_DIV
> > + select SUNXI_CCU_NK
> > + select SUNXI_CCU_NKM
> > + select SUNXI_CCU_NKMP
> > + select SUNXI_CCU_NM
> > + select SUNXI_CCU_MP
> > + select SUNXI_CCU_PHASE
> > + default ARM64 && ARCH_SUNXI
> > +
> > config SUN6I_A31_CCU
> > bool "Support for the Allwinner A31/A31s CCU"
> > select SUNXI_CCU_DIV
> > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> > index 106cba27c331..24fbc6e5deb8 100644
> > --- a/drivers/clk/sunxi-ng/Makefile
> > +++ b/drivers/clk/sunxi-ng/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o
> > obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
> >
> > # SoC support
> > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
> > obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
> > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
> > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > new file mode 100644
> > index 000000000000..c0e96bf6d104
> > --- /dev/null
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > @@ -0,0 +1,918 @@
> > +/*
> > + * Copyright (c) 2016 Maxime Ripard. All rights reserved.
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "ccu_common.h"
> > +#include "ccu_reset.h"
> > +
> > +#include "ccu_div.h"
> > +#include "ccu_gate.h"
> > +#include "ccu_mp.h"
> > +#include "ccu_mult.h"
> > +#include "ccu_nk.h"
> > +#include "ccu_nkm.h"
> > +#include "ccu_nkmp.h"
> > +#include "ccu_nm.h"
> > +#include "ccu_phase.h"
> > +
> > +#include "ccu-sun50i-a64.h"
> > +
> > +static struct ccu_nkmp pll_cpux_clk = {
> > + .enable = BIT(31),
> > + .lock = BIT(28),
> > + .n = _SUNXI_CCU_MULT(8, 5),
> > + .k = _SUNXI_CCU_MULT(4, 2),
> > + .m = _SUNXI_CCU_DIV(0, 2),
> > + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
> > + .common = {
> > + .reg = 0x000,
> > + .hw.init = CLK_HW_INIT("pll-cpux",
> > + "osc24M",
> > + &ccu_nkmp_ops,
> > + 0),
> > + },
> > +};
> > +
> > +/*
> > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> > + * the base (2x, 4x and 8x), and one variable divider (the one true
> > + * pll audio).
> > + *
> > + * We don't have any need for the variable divider for now, so we just
> > + * hardcode it to match with the clock names
> > + */
> > +#define SUN50I_A64_PLL_AUDIO_REG 0x008
> > +
> > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
> > + "osc24M", 0x008,
> > + 8, 7, /* N */
> > + 0, 5, /* M */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
> > + "osc24M", 0x010,
> > + 8, 7, /* N */
> > + 0, 4, /* M */
> > + BIT(24), /* frac enable */
> > + BIT(25), /* frac select */
> > + 270000000, /* frac rate 0 */
> > + 297000000, /* frac rate 1 */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
> > + "osc24M", 0x018,
> > + 8, 7, /* N */
> > + 0, 4, /* M */
> > + BIT(24), /* frac enable */
> > + BIT(25), /* frac select */
> > + 270000000, /* frac rate 0 */
> > + 297000000, /* frac rate 1 */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
> > + "osc24M", 0x020,
> > + 8, 5, /* N */
> > + 4, 2, /* K */
> > + 0, 2, /* M */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +static struct ccu_nk pll_periph0_clk = {
> > + .enable = BIT(31),
> > + .lock = BIT(28),
> > + .n = _SUNXI_CCU_MULT(8, 5),
> > + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> > + .fixed_post_div = 2,
> > + .common = {
> > + .reg = 0x028,
> > + .features = CCU_FEATURE_FIXED_POSTDIV,
> > + .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
> > + &ccu_nk_ops, 0),
> > + },
> > +};
> > +
> > +static struct ccu_nk pll_periph1_clk = {
> > + .enable = BIT(31),
> > + .lock = BIT(28),
> > + .n = _SUNXI_CCU_MULT(8, 5),
> > + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> > + .fixed_post_div = 2,
> > + .common = {
> > + .reg = 0x02c,
> > + .features = CCU_FEATURE_FIXED_POSTDIV,
> > + .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
> > + &ccu_nk_ops, 0),
> > + },
> > +};
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
> > + "osc24M", 0x030,
> > + 8, 7, /* N */
> > + 0, 4, /* M */
> > + BIT(24), /* frac enable */
> > + BIT(25), /* frac select */
> > + 270000000, /* frac rate 0 */
> > + 297000000, /* frac rate 1 */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
> > + "osc24M", 0x038,
> > + 8, 7, /* N */
> > + 0, 4, /* M */
> > + BIT(24), /* frac enable */
> > + BIT(25), /* frac select */
> > + 270000000, /* frac rate 0 */
> > + 297000000, /* frac rate 1 */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +/*
> > + * The output function can be changed to something more complex that
> > + * we do not handle yet.
> > + *
> > + * Hardcode the mode so that we don't fall in that case.
> > + */
> > +#define SUN50I_A64_PLL_MIPI_REG 0x040
> > +
> > +struct ccu_nkm pll_mipi_clk = {
> > + .enable = BIT(31),
> > + .lock = BIT(28),
> > + .n = _SUNXI_CCU_MULT(8, 4),
> > + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> > + .m = _SUNXI_CCU_DIV(0, 4),
> > + .common = {
> > + .reg = 0x040,
> > + .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
> > + &ccu_nkm_ops, 0),
> > + },
> > +};
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
> > + "osc24M", 0x044,
> > + 8, 7, /* N */
> > + 0, 4, /* M */
> > + BIT(24), /* frac enable */
> > + BIT(25), /* frac select */
> > + 270000000, /* frac rate 0 */
> > + 297000000, /* frac rate 1 */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
> > + "osc24M", 0x048,
> > + 8, 7, /* N */
> > + 0, 4, /* M */
> > + BIT(24), /* frac enable */
> > + BIT(25), /* frac select */
> > + 270000000, /* frac rate 0 */
> > + 297000000, /* frac rate 1 */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
> > +
> > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
> > + "osc24M", 0x04c,
> > + 8, 7, /* N */
> > + 0, 2, /* M */
> > + BIT(31), /* gate */
> > + BIT(28), /* lock */
> > + 0);
>
> CLK_SET_RATE_UNGATE for all the PLLs?
>
> > +
> > +static const char * const cpux_parents[] = { "osc32k", "osc24M",
> > + "pll-cpux" , "pll-cpux" };
> > +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> > + 0x050, 16, 2, CLK_IS_CRITICAL);
>
> CLK_SET_RATE_PARENT.
>
> [...]
>
> > +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
> > + 0, 4, /* M */
> > + 16, 2, /* P */
> > + 24, 2, /* mux */
> > + BIT(31), /* gate */
> > + 0);
> > +
> > +
>
> Extra newline.
>
> [...]
>
> > +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
> > +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
> > + 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
>
> The divider is only 2 bits wide.
>
> > +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> > +static const u8 tcon1_table[] = { 0, 2, };
> > +struct ccu_div tcon1_clk = {
> > + .enable = BIT(31),
> > + .div = _SUNXI_CCU_DIV(0, 4),
> > + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table),
>
> Mux is only 2 bits wide.
>
> > + .common = {
> > + .reg = 0x11c,
> > + .hw.init = CLK_HW_INIT_PARENTS("tcon1",
> > + tcon1_parents,
> > + &ccu_div_ops,
> > + CLK_SET_RATE_PARENT),
> > + },
> > +};
> > +
>
> [...]
>
> > +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
> > +static const u8 dsi_dphy_table[] = { 0, 2, };
> > +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
> > + dsi_dphy_parents, dsi_dphy_table,
> > + 0x168, 0, 3, 24, 2, BIT(31), 0);
>
> Divider is 4 bits wide, and mux offset is 8.
Good catches.
This is fixed, and I'll resend a new serie.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 2/3] clk: hisilicon: add CRG driver for Hi3516CV300 SoC
From: Stephen Boyd @ 2016-10-20 17:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5dc55eef-808e-fa78-a5a0-4fccb31e5ceb@hisilicon.com>
On 10/19, Jiancheng Xue wrote:
>
> I'm pretty sure that the patch was sent to the DT list devicetree at vger.kernel.org.
> You had asked a question about "hi3798cv200-sysctrl" and I replied (https://lkml.org/lkml/2016/10/10/517).
> I'm waiting for your new comments. If there's some misunderstatnding, please let me know.
>
Are there two patch series that touch the same clk binding
document? Can you please combine them and resend them if that's
the case?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [linux-sunxi] [PATCH v4 7/9] arm64: dts: add Allwinner A64 SoC .dtsi
From: Maxime Ripard @ 2016-10-20 17:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65X5Gzx7H_jgLt80MY8tOrwgLX_uYrHo49-mScPsanJ2g@mail.gmail.com>
On Thu, Oct 20, 2016 at 11:14:05PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > From: Andre Przywara <andre.przywara@arm.com>
> >
> > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> > and the typical tablet / TV box peripherals.
> > The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
> > the peripherals and the memory map.
> > Although the cores are proper 64-bit ones, the whole SoC is actually
> > limited to 4GB (including all the supported DRAM), so we use 32-bit
> > address and size cells. This has the nice feature of us being able to
> > reuse the DT for 32-bit kernels as well.
> > This .dtsi lists the hardware that we support so far.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> > [Maxime: Convert to CCU binding, drop the MMC support for now]
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > Documentation/devicetree/bindings/arm/sunxi.txt | 1 +-
> > MAINTAINERS | 1 +-
> > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 263 +++++++++++++++++-
> > 3 files changed, 265 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >
> > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> > index 3975d0a0e4c2..4d6467cc2aa2 100644
> > --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> > @@ -14,4 +14,5 @@ using one of the following compatible strings:
> > allwinner,sun8i-a83t
> > allwinner,sun8i-h3
> > allwinner,sun9i-a80
> > + allwinner,sun50i-a64
> > nextthing,gr8
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 7be47efb2159..926879c05dc6 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -983,6 +983,7 @@ L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> > S: Maintained
> > N: sun[x456789]i
> > F: arch/arm/boot/dts/ntc-gr8*
> > +F: arch/arm64/boot/dts/allwinner/
> >
> > ARM/Allwinner SoC Clock Support
> > M: Emilio L?pez <emilio@elopez.com.ar>
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > new file mode 100644
> > index 000000000000..0f75fec23dc9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > @@ -0,0 +1,263 @@
> > +/*
> > + * Copyright (C) 2016 ARM Ltd.
> > + * based on the Allwinner H3 dtsi:
> > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + * a) This file is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of the
> > + * License, or (at your option) any later version.
> > + *
> > + * This file is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + * b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > + * sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following
> > + * conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > + * included in all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#include <dt-bindings/clock/sun50i-a64-ccu.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/sun4i-a10.h>
> > +#include <dt-bindings/reset/sun50i-a64-ccu.h>
> > +
> > +/ {
> > + interrupt-parent = <&gic>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu at 0 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <0>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu1: cpu at 1 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <1>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu2: cpu at 2 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <2>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu3: cpu at 3 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <3>;
> > + enable-method = "psci";
> > + };
> > + };
> > +
> > + osc24M: osc24M_clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <24000000>;
> > + clock-output-names = "osc24M";
> > + };
> > +
> > + osc32k: osc32k_clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <32768>;
> > + clock-output-names = "osc32k";
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 14
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 11
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 10
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + ccu: clock at 01c20000 {
> > + compatible = "allwinner,sun50i-a64-ccu";
> > + reg = <0x01c20000 0x400>;
> > + clocks = <&osc24M>, <&osc32k>;
> > + clock-names = "hosc", "losc";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + pio: pinctrl at 1c20800 {
> > + compatible = "allwinner,sun50i-a64-pinctrl";
> > + reg = <0x01c20800 0x400>;
> > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_PIO>;
> > + gpio-controller;
> > + #gpio-cells = <3>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
>
> I think this should be 3? <bank index flags>?
>
> > +
> > + i2c1_pins: i2c1_pins {
> > + allwinner,pins = "PH2", "PH3";
> > + allwinner,function = "i2c1";
> > + };
> > +
> > + uart0_pins_a: uart0 at 0 {
> > + allwinner,pins = "PB8", "PB9";
> > + allwinner,function = "uart0";
> > + };
> > + };
> > +
> > + uart0: serial at 1c28000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x01c28000 0x400>;
> > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART0>;
> > + resets = <&ccu RST_BUS_UART0>;
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial at 1c28400 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x01c28400 0x400>;
> > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART1>;
> > + resets = <&ccu RST_BUS_UART1>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial at 1c28800 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x01c28800 0x400>;
> > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART2>;
> > + resets = <&ccu RST_BUS_UART2>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial at 1c28c00 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x01c28c00 0x400>;
> > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART3>;
> > + resets = <&ccu RST_BUS_UART3>;
> > + status = "disabled";
> > + };
> > +
> > + uart4: serial at 1c29000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x01c29000 0x400>;
> > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART4>;
> > + resets = <&ccu RST_BUS_UART4>;
> > + status = "disabled";
> > + };
> > +
> > + rtc: rtc at 1f00000 {
> > + compatible = "allwinner,sun6i-a31-rtc";
> > + reg = <0x01f00000 0x54>;
> > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > + };
>
> Should sort by address.
>
> You can keep my Ack after fixing these.
Indeed, fixed.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 2/3] dt-bindings: mtd: add DT binding for s3c2410 flash controller
From: Krzysztof Kozlowski @ 2016-10-20 17:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476906725-22613-3-git-send-email-sergio.prado@e-labworks.com>
On Wed, Oct 19, 2016 at 05:52:04PM -0200, Sergio Prado wrote:
> Adds the device tree bindings description for Samsung S3C2410 and
> compatible NAND flash controller.
>
> Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> ---
> .../devicetree/bindings/mtd/samsung-s3c2410.txt | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt
>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH V5 1/2] ACPI: Add support for ResourceSource/IRQ domain mapping
From: Marc Zyngier @ 2016-10-20 17:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020164812.GD8731@red-moon>
On 20/10/16 17:48, Lorenzo Pieralisi wrote:
> Hi Agustin,
>
> On Tue, Oct 18, 2016 at 01:41:48PM -0400, Agustin Vega-Frias wrote:
>> This allows irqchip drivers to associate an ACPI DSDT device to
>> an IRQ domain and provides support for using the ResourceSource
>> in Extended IRQ Resources to find the domain and map the IRQs
>> specified on that domain.
>>
>> Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
>> ---
>> drivers/acpi/Makefile | 1 +
>> drivers/acpi/irqdomain.c | 141 ++++++++++++++++++++++++++++++++++++++
>> drivers/acpi/resource.c | 21 +++---
>> include/asm-generic/vmlinux.lds.h | 1 +
>> include/linux/acpi.h | 71 +++++++++++++++++++
>> include/linux/irqchip.h | 17 ++++-
>> 6 files changed, 240 insertions(+), 12 deletions(-)
>> create mode 100644 drivers/acpi/irqdomain.c
>>
>> diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
>> index 9ed0878..880401b 100644
>> --- a/drivers/acpi/Makefile
>> +++ b/drivers/acpi/Makefile
>> @@ -57,6 +57,7 @@ acpi-$(CONFIG_ACPI_PROCFS_POWER) += cm_sbs.o
>> acpi-y += acpi_lpat.o
>> acpi-$(CONFIG_ACPI_GENERIC_GSI) += gsi.o
>> acpi-$(CONFIG_ACPI_WATCHDOG) += acpi_watchdog.o
>> +acpi-$(CONFIG_IRQ_DOMAIN) += irqdomain.o
>>
>> # These are (potentially) separate modules
>>
>> diff --git a/drivers/acpi/irqdomain.c b/drivers/acpi/irqdomain.c
>> new file mode 100644
>> index 0000000..c53b9f4
>> --- /dev/null
>> +++ b/drivers/acpi/irqdomain.c
>> @@ -0,0 +1,141 @@
>> +/*
>> + * ACPI ResourceSource/IRQ domain mapping support
>> + *
>> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +#include <linux/acpi.h>
>> +#include <linux/irq.h>
>> +#include <linux/irqdomain.h>
>> +
>> +/**
>> + * acpi_irq_domain_ensure_probed() - Check if the device has registered
>> + * an IRQ domain and probe as necessary
>> + *
>> + * @device: Device to check and probe
>> + *
>> + * Returns: 0 on success, -ENODEV otherwise
>
> This is not correct (ie it depends on what
>
> struct acpi_dsdt_probe_entry.probe
>
> returns) and I would like to take this nit as an opportunity
> to take a step back and ask you a question below.
>
>> + */
>> +static int acpi_irq_domain_ensure_probed(struct acpi_device *device)
>> +{
>> + struct acpi_dsdt_probe_entry *entry;
>> +
>> + if (irq_find_matching_fwnode(&device->fwnode, DOMAIN_BUS_ANY) != 0)
>> + return 0;
>> +
>> + for (entry = &__dsdt_acpi_probe_table;
>> + entry < &__dsdt_acpi_probe_table_end; entry++)
>> + if (strcmp(entry->_hid, acpi_device_hid(device)) == 0)
>> + return entry->probe(device);
>
> Through this approch we are forcing an irqchip (that by the way it
> has a physical node ACPI companion by being a DSDT device object so it
> could be managed by a platform driver) to be probed. The question is: is
> there a reason (apart from the current ACPI resource parsing API) why
> this can't be implemented through deferred probing and the device
> dependencies framework Rafael is working on:
>
> http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg1246897.html
>
> The DT layer, through the of_irq_get() API, supports probe deferral
> and what I am asking you is if there is any blocking point (again,
> apart from the current ACPI API) to implement the same mechanism.
>
> I have not reviewed the previous versions so I am certainly missing
> some of the bits and pieces already discussed, apologies for that.
Also, this function scares me to no end: lack of locking and recursion
are the main things that worry me. My vote would be to implement
something based on Rafael's approach (which conveniently solves all kind
of other issues).
I'll review this patch series in a more in-depth way soon, but I wanted
to chime in and add my own weight to Lorenzo's proposal.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v2 1/3] mtd: s3c2410: make ecc mode configurable via platform data
From: Krzysztof Kozlowski @ 2016-10-20 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476906725-22613-2-git-send-email-sergio.prado@e-labworks.com>
On Wed, Oct 19, 2016 at 05:52:03PM -0200, Sergio Prado wrote:
> Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode
> field in the drivers's platform data structure so it can be selectable
> via platform data.
>
> Also setting this field to NAND_ECC_SOFT in all boards using this
> driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.
>
> Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> ---
> arch/arm/mach-s3c24xx/common-smdk.c | 1 +
> arch/arm/mach-s3c24xx/mach-anubis.c | 1 +
> arch/arm/mach-s3c24xx/mach-at2440evb.c | 1 +
> arch/arm/mach-s3c24xx/mach-bast.c | 1 +
> arch/arm/mach-s3c24xx/mach-gta02.c | 1 +
> arch/arm/mach-s3c24xx/mach-jive.c | 1 +
> arch/arm/mach-s3c24xx/mach-mini2440.c | 1 +
> arch/arm/mach-s3c24xx/mach-osiris.c | 1 +
> arch/arm/mach-s3c24xx/mach-qt2410.c | 1 +
> arch/arm/mach-s3c24xx/mach-rx1950.c | 1 +
> arch/arm/mach-s3c24xx/mach-rx3715.c | 1 +
> arch/arm/mach-s3c24xx/mach-vstms.c | 1 +
> arch/arm/mach-s3c64xx/mach-hmt.c | 1 +
> arch/arm/mach-s3c64xx/mach-mini6410.c | 1 +
> arch/arm/mach-s3c64xx/mach-real6410.c | 1 +
You missed cc-ing Samsung Soc maintainers on v2 and these files belong
to this tree. Please, don't forget next time.
The change itself looks atomic so I guess these files cannot go through
separate tree. In that case:
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
> drivers/mtd/nand/Kconfig | 9 --
> drivers/mtd/nand/s3c2410.c | 119 +++++++++++++------------
> include/linux/platform_data/mtd-nand-s3c2410.h | 6 +-
> 18 files changed, 79 insertions(+), 70 deletions(-)
>
> diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
> index e9fbcc91c5c0..9e0bc46e90ec 100644
> --- a/arch/arm/mach-s3c24xx/common-smdk.c
> +++ b/arch/arm/mach-s3c24xx/common-smdk.c
> @@ -171,6 +171,7 @@
> .twrph1 = 20,
> .nr_sets = ARRAY_SIZE(smdk_nand_sets),
> .sets = smdk_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> /* devices we initialise */
> diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
> index d03df0df01fa..029ef1b58925 100644
> --- a/arch/arm/mach-s3c24xx/mach-anubis.c
> +++ b/arch/arm/mach-s3c24xx/mach-anubis.c
> @@ -223,6 +223,7 @@ static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
> .nr_sets = ARRAY_SIZE(anubis_nand_sets),
> .sets = anubis_nand_sets,
> .select_chip = anubis_nand_select,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> /* IDE channels */
> diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
> index 9ae170fef2a7..7b28eb623fc1 100644
> --- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
> +++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
> @@ -114,6 +114,7 @@
> .twrph1 = 40,
> .nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
> .sets = at2440evb_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> /* DM9000AEP 10/100 ethernet controller */
> diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
> index ed07cf392d4b..5185036765db 100644
> --- a/arch/arm/mach-s3c24xx/mach-bast.c
> +++ b/arch/arm/mach-s3c24xx/mach-bast.c
> @@ -299,6 +299,7 @@ static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
> .nr_sets = ARRAY_SIZE(bast_nand_sets),
> .sets = bast_nand_sets,
> .select_chip = bast_nand_select,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> /* DM9000 */
> diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
> index 27ae6877550f..b0ed401da3a3 100644
> --- a/arch/arm/mach-s3c24xx/mach-gta02.c
> +++ b/arch/arm/mach-s3c24xx/mach-gta02.c
> @@ -443,6 +443,7 @@ static void gta02_udc_vbus_draw(unsigned int ma)
> .twrph1 = 15,
> .nr_sets = ARRAY_SIZE(gta02_nand_sets),
> .sets = gta02_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
>
> diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
> index 7d99fe8f6157..895aca225952 100644
> --- a/arch/arm/mach-s3c24xx/mach-jive.c
> +++ b/arch/arm/mach-s3c24xx/mach-jive.c
> @@ -232,6 +232,7 @@
> .twrph1 = 40,
> .sets = jive_nand_sets,
> .nr_sets = ARRAY_SIZE(jive_nand_sets),
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> static int __init jive_mtdset(char *options)
> diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
> index ec60bd4a1646..71af8d2fd320 100644
> --- a/arch/arm/mach-s3c24xx/mach-mini2440.c
> +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
> @@ -287,6 +287,7 @@
> .nr_sets = ARRAY_SIZE(mini2440_nand_sets),
> .sets = mini2440_nand_sets,
> .ignore_unset_ecc = 1,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> /* DM9000AEP 10/100 ethernet controller */
> diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
> index 2f6fdc326835..70b0eb7d3134 100644
> --- a/arch/arm/mach-s3c24xx/mach-osiris.c
> +++ b/arch/arm/mach-s3c24xx/mach-osiris.c
> @@ -238,6 +238,7 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
> .nr_sets = ARRAY_SIZE(osiris_nand_sets),
> .sets = osiris_nand_sets,
> .select_chip = osiris_nand_select,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> /* PCMCIA control and configuration */
> diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
> index 984516e8307a..868c82087403 100644
> --- a/arch/arm/mach-s3c24xx/mach-qt2410.c
> +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
> @@ -284,6 +284,7 @@
> .twrph1 = 20,
> .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
> .sets = qt2410_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> /* UDC */
> diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
> index 25a139bb9826..e86ad6a68a0b 100644
> --- a/arch/arm/mach-s3c24xx/mach-rx1950.c
> +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
> @@ -611,6 +611,7 @@ static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd)
> .twrph1 = 15,
> .nr_sets = ARRAY_SIZE(rx1950_nand_sets),
> .sets = rx1950_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
> diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
> index cf55196f89ca..a39fb9780dd3 100644
> --- a/arch/arm/mach-s3c24xx/mach-rx3715.c
> +++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
> @@ -164,6 +164,7 @@
> .twrph1 = 15,
> .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
> .sets = rx3715_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> static struct platform_device *rx3715_devices[] __initdata = {
> diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
> index b4460d5f7011..f5e6322145fa 100644
> --- a/arch/arm/mach-s3c24xx/mach-vstms.c
> +++ b/arch/arm/mach-s3c24xx/mach-vstms.c
> @@ -117,6 +117,7 @@
> .twrph1 = 20,
> .nr_sets = ARRAY_SIZE(vstms_nand_sets),
> .sets = vstms_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> static struct platform_device *vstms_devices[] __initdata = {
> diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
> index bc7dc1fcbf7d..59b5531f1987 100644
> --- a/arch/arm/mach-s3c64xx/mach-hmt.c
> +++ b/arch/arm/mach-s3c64xx/mach-hmt.c
> @@ -204,6 +204,7 @@ static void hmt_bl_exit(struct device *dev)
> .twrph1 = 40,
> .nr_sets = ARRAY_SIZE(hmt_nand_sets),
> .sets = hmt_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> static struct gpio_led hmt_leds[] = {
> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
> index ae999fb3fe6d..a3e3e25728b4 100644
> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
> @@ -142,6 +142,7 @@
> .twrph1 = 40,
> .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
> .sets = mini6410_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
> index 4e240ffa7ac7..d6b3ffd7704b 100644
> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
> @@ -194,6 +194,7 @@
> .twrph1 = 40,
> .nr_sets = ARRAY_SIZE(real6410_nand_sets),
> .sets = real6410_nand_sets,
> + .ecc_mode = NAND_ECC_SOFT,
> };
>
> static struct platform_device *real6410_devices[] __initdata = {
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 7b7a887b4709..9748f3580d4b 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -179,15 +179,6 @@ config MTD_NAND_S3C2410_DEBUG
> help
> Enable debugging of the S3C NAND driver
>
> -config MTD_NAND_S3C2410_HWECC
> - bool "Samsung S3C NAND Hardware ECC"
> - depends on MTD_NAND_S3C2410
> - help
> - Enable the use of the controller's internal ECC generator when
> - using NAND. Early versions of the chips have had problems with
> - incorrect ECC generation, and if using these, the default of
> - software ECC is preferable.
> -
> config MTD_NAND_NDFC
> tristate "NDFC NanD Flash Controller"
> depends on 4xx
> diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
> index d459c19d78de..371db0d48135 100644
> --- a/drivers/mtd/nand/s3c2410.c
> +++ b/drivers/mtd/nand/s3c2410.c
> @@ -497,7 +497,6 @@ static int s3c2412_nand_devready(struct mtd_info *mtd)
>
> /* ECC handling functions */
>
> -#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
> static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
> u_char *read_ecc, u_char *calc_ecc)
> {
> @@ -649,7 +648,6 @@ static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
>
> return 0;
> }
> -#endif
>
> /* over-ride the standard functions for a little more speed. We can
> * use read/write block to move the data buffers to/from the controller
> @@ -858,50 +856,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
> nmtd->info = info;
> nmtd->set = set;
>
> -#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
> - chip->ecc.calculate = s3c2410_nand_calculate_ecc;
> - chip->ecc.correct = s3c2410_nand_correct_data;
> - chip->ecc.mode = NAND_ECC_HW;
> - chip->ecc.strength = 1;
> -
> - switch (info->cpu_type) {
> - case TYPE_S3C2410:
> - chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
> - chip->ecc.calculate = s3c2410_nand_calculate_ecc;
> - break;
> -
> - case TYPE_S3C2412:
> - chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
> - chip->ecc.calculate = s3c2412_nand_calculate_ecc;
> - break;
> -
> - case TYPE_S3C2440:
> - chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
> - chip->ecc.calculate = s3c2440_nand_calculate_ecc;
> - break;
> - }
> -#else
> - chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> -#endif
> -
> - if (set->disable_ecc)
> - chip->ecc.mode = NAND_ECC_NONE;
> -
> - switch (chip->ecc.mode) {
> - case NAND_ECC_NONE:
> - dev_info(info->device, "NAND ECC disabled\n");
> - break;
> - case NAND_ECC_SOFT:
> - dev_info(info->device, "NAND soft ECC\n");
> - break;
> - case NAND_ECC_HW:
> - dev_info(info->device, "NAND hardware ECC\n");
> - break;
> - default:
> - dev_info(info->device, "NAND ECC UNKNOWN\n");
> - break;
> - }
> + chip->ecc.mode = info->platform->ecc_mode;
>
> /* If you use u-boot BBT creation code, specifying this flag will
> * let the kernel fish out the BBT from the NAND, and also skip the
> @@ -923,28 +878,72 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
> *
> * The internal state is currently limited to the ECC state information.
> */
> -static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
> +static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
> struct s3c2410_nand_mtd *nmtd)
> {
> struct nand_chip *chip = &nmtd->chip;
>
> - dev_dbg(info->device, "chip %p => page shift %d\n",
> - chip, chip->page_shift);
> + switch (chip->ecc.mode) {
>
> - if (chip->ecc.mode != NAND_ECC_HW)
> - return;
> + case NAND_ECC_NONE:
> + dev_info(info->device, "ECC disabled\n");
> + break;
> +
> + case NAND_ECC_SOFT:
> + /*
> + * This driver expects Hamming based ECC when ecc_mode is set
> + * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
> + * avoid adding an extra ecc_algo field to s3c2410_platform_nand.
> + */
> + chip->ecc.algo = NAND_ECC_HAMMING;
> + dev_info(info->device, "soft ECC\n");
> + break;
> +
> + case NAND_ECC_HW:
> + chip->ecc.calculate = s3c2410_nand_calculate_ecc;
> + chip->ecc.correct = s3c2410_nand_correct_data;
> + chip->ecc.strength = 1;
> +
> + switch (info->cpu_type) {
> + case TYPE_S3C2410:
> + chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
> + chip->ecc.calculate = s3c2410_nand_calculate_ecc;
> + break;
> +
> + case TYPE_S3C2412:
> + chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
> + chip->ecc.calculate = s3c2412_nand_calculate_ecc;
> + break;
> +
> + case TYPE_S3C2440:
> + chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
> + chip->ecc.calculate = s3c2440_nand_calculate_ecc;
> + break;
> + }
> +
> + dev_dbg(info->device, "chip %p => page shift %d\n",
> + chip, chip->page_shift);
>
> /* change the behaviour depending on whether we are using
> * the large or small page nand device */
> + if (chip->page_shift > 10) {
> + chip->ecc.size = 256;
> + chip->ecc.bytes = 3;
> + } else {
> + chip->ecc.size = 512;
> + chip->ecc.bytes = 3;
> + mtd_set_ooblayout(nand_to_mtd(chip), &s3c2410_ooblayout_ops);
> + }
>
> - if (chip->page_shift > 10) {
> - chip->ecc.size = 256;
> - chip->ecc.bytes = 3;
> - } else {
> - chip->ecc.size = 512;
> - chip->ecc.bytes = 3;
> - mtd_set_ooblayout(nand_to_mtd(chip), &s3c2410_ooblayout_ops);
> + dev_info(info->device, "hardware ECC\n");
> + break;
> +
> + default:
> + dev_err(info->device, "invalid ECC mode!\n");
> + return -EINVAL;
> }
> +
> + return 0;
> }
>
> /* s3c24xx_nand_probe
> @@ -1046,7 +1045,9 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
> NULL);
>
> if (nmtd->scan_res == 0) {
> - s3c2410_nand_update_chip(info, nmtd);
> + err = s3c2410_nand_update_chip(info, nmtd);
> + if (err < 0)
> + goto exit_error;
> nand_scan_tail(mtd);
> s3c2410_nand_add_partition(info, nmtd, sets);
> }
> diff --git a/include/linux/platform_data/mtd-nand-s3c2410.h b/include/linux/platform_data/mtd-nand-s3c2410.h
> index c55e42ee57fa..729af13d1773 100644
> --- a/include/linux/platform_data/mtd-nand-s3c2410.h
> +++ b/include/linux/platform_data/mtd-nand-s3c2410.h
> @@ -12,9 +12,10 @@
> #ifndef __MTD_NAND_S3C2410_H
> #define __MTD_NAND_S3C2410_H
>
> +#include <linux/mtd/nand.h>
> +
> /**
> * struct s3c2410_nand_set - define a set of one or more nand chips
> - * @disable_ecc: Entirely disable ECC - Dangerous
> * @flash_bbt: Openmoko u-boot can create a Bad Block Table
> * Setting this flag will allow the kernel to
> * look for it at boot time and also skip the NAND
> @@ -31,7 +32,6 @@
> * a warning at boot time.
> */
> struct s3c2410_nand_set {
> - unsigned int disable_ecc:1;
> unsigned int flash_bbt:1;
>
> unsigned int options;
> @@ -51,6 +51,8 @@ struct s3c2410_platform_nand {
>
> unsigned int ignore_unset_ecc:1;
>
> + nand_ecc_modes_t ecc_mode;
> +
> int nr_sets;
> struct s3c2410_nand_set *sets;
>
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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