* [RFC PATCH 03/13] ARM64: dts: meson-gxl: Add pinctrl nodes
From: Neil Armstrong @ 2016-10-21 14:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477060838-14164-1-git-send-email-narmstrong@baylibre.com>
Add pinctrl nodes and pin definitions for Amlogic Meson GXL.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 168 +++++++++++++++++++++++++++++
1 file changed, 168 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 13b10ee..ce7f550 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -42,7 +42,175 @@
*/
#include "meson-gx.dtsi"
+#include <dt-bindings/gpio/meson-gxl-gpio.h>
/ {
compatible = "amlogic,meson-gxl";
};
+
+&aobus {
+ pinctrl_aobus: pinctrl at 14 {
+ compatible = "amlogic,meson-gxl-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio_ao: bank at 14 {
+ reg = <0x0 0x00014 0x0 0x8>,
+ <0x0 0x0002c 0x0 0x4>,
+ <0x0 0x00024 0x0 0x8>;
+ reg-names = "mux", "pull", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ uart_ao_a_pins: uart_ao_a {
+ mux {
+ groups = "uart_tx_ao_a", "uart_rx_ao_a";
+ function = "uart_ao";
+ };
+ };
+
+ remote_input_ao_pins: remote_input_ao {
+ mux {
+ groups = "remote_input_ao";
+ function = "remote_input_ao";
+ };
+ };
+ };
+};
+
+&periphs {
+ pinctrl_periphs: pinctrl at 4b0 {
+ compatible = "amlogic,meson-gxl-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank at 4b0 {
+ reg = <0x0 0x004b0 0x0 0x28>,
+ <0x0 0x004e8 0x0 0x14>,
+ <0x0 0x00120 0x0 0x14>,
+ <0x0 0x00430 0x0 0x40>;
+ reg-names = "mux", "pull", "pull-enable", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d07",
+ "emmc_cmd",
+ "emmc_clk",
+ "emmc_ds";
+ function = "emmc";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0",
+ "sdcard_d1",
+ "sdcard_d2",
+ "sdcard_d3",
+ "sdcard_cmd",
+ "sdcard_clk";
+ function = "sdcard";
+ };
+ };
+
+ sdio_pins: sdio {
+ mux {
+ groups = "sdio_d0",
+ "sdio_d1",
+ "sdio_d2",
+ "sdio_d3",
+ "sdio_cmd",
+ "sdio_clk";
+ function = "sdio";
+ };
+ };
+
+ sdio_irq_pins: sdio_irq {
+ mux {
+ groups = "sdio_irq";
+ function = "sdio";
+ };
+ };
+
+ uart_a_pins: uart_a {
+ mux {
+ groups = "uart_tx_a",
+ "uart_rx_a";
+ function = "uart_a";
+ };
+ };
+
+ uart_b_pins: uart_b {
+ mux {
+ groups = "uart_tx_b",
+ "uart_rx_b";
+ function = "uart_b";
+ };
+ };
+
+ uart_c_pins: uart_c {
+ mux {
+ groups = "uart_tx_c",
+ "uart_rx_c";
+ function = "uart_c";
+ };
+ };
+
+ i2c_a_pins: i2c_a {
+ mux {
+ groups = "i2c_sck_a",
+ "i2c_sda_a";
+ function = "i2c_a";
+ };
+ };
+
+ i2c_b_pins: i2c_b {
+ mux {
+ groups = "i2c_sck_b",
+ "i2c_sda_b";
+ function = "i2c_b";
+ };
+ };
+
+ i2c_c_pins: i2c_c {
+ mux {
+ groups = "i2c_sck_c",
+ "i2c_sda_c";
+ function = "i2c_c";
+ };
+ };
+
+ eth_pins: eth_c {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_clk_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_rxd2",
+ "eth_rxd3",
+ "eth_rgmii_tx_clk",
+ "eth_tx_en",
+ "eth_txd0",
+ "eth_txd1",
+ "eth_txd2",
+ "eth_txd3";
+ function = "eth";
+ };
+ };
+
+ pwm_e_pins: pwm_e {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 02/13] ARM64: dts: meson-gxbb: Move common nodes to meson-gx
From: Neil Armstrong @ 2016-10-21 14:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477060838-14164-1-git-send-email-narmstrong@baylibre.com>
Move common nodes between GXBB and GXL in to the common GX dtsi.
Leave the clock attributes in the GXBB dtsi for now.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 131 +++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 155 ++++------------------------
2 files changed, 149 insertions(+), 137 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index fd1d0de..91be4f2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -129,6 +129,30 @@
#clock-cells = <0>;
};
+ firmware {
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
+ };
+ };
+
+ efuse: efuse {
+ compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sn: sn at 14 {
+ reg = <0x14 0x10>;
+ };
+
+ eth_mac: eth_mac at 34 {
+ reg = <0x34 0x10>;
+ };
+
+ bid: bid at 46 {
+ reg = <0x46 0x30>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -142,6 +166,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+ reset: reset-controller at 4404 {
+ compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x04404 0x0 0x20>;
+ #reset-cells = <1>;
+ };
+
uart_A: serial at 84c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84c0 0x0 0x14>;
@@ -149,6 +179,76 @@
clocks = <&xtal>;
status = "disabled";
};
+
+ uart_B: serial at 84dc {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x84dc 0x0 0x14>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ i2c_A: i2c at 8500 {
+ compatible = "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x08500 0x0 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm_ab: pwm at 8550 {
+ compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x08550 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm at 8650 {
+ compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x08650 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm at 86c0 {
+ compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x086c0 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ uart_C: serial at 8700 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x8700 0x0 0x14>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ i2c_B: i2c at 87c0 {
+ compatible = "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x087c0 0x0 0x20>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c_C: i2c at 87e0 {
+ compatible = "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x087e0 0x0 0x20>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ watchdog at 98d0 {
+ compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
+ reg = <0x0 0x098d0 0x0 0x10>;
+ clocks = <&xtal>;
+ };
};
gic: interrupt-controller at c4301000 {
@@ -178,6 +278,13 @@
clocks = <&xtal>;
status = "disabled";
};
+
+ ir: ir at 580 {
+ compatible = "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x00580 0x0 0x40>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
};
periphs: periphs at c8834000 {
@@ -186,6 +293,11 @@
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
+
+ rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
};
@@ -195,6 +307,25 @@
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+
+ mailbox: mailbox at 404 {
+ compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+ reg = <0 0x404 0 0x4c>;
+ interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+ <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
+ };
+
+ ethmac: ethernet at c9410000 {
+ compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+ reg = <0x0 0xc9410000 0x0 0x10000
+ 0x0 0xc8834540 0x0 0x4>;
+ interrupts = <0 8 1>;
+ interrupt-names = "macirq";
+ phy-mode = "rgmii";
+ status = "disabled";
};
apb: apb at d0000000 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 22940bb..7c5bf14 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -50,30 +50,6 @@
/ {
compatible = "amlogic,meson-gxbb";
- firmware {
- sm: secure-monitor {
- compatible = "amlogic,meson-gxbb-sm";
- };
- };
-
- efuse: efuse {
- compatible = "amlogic,meson-gxbb-efuse";
- #address-cells = <1>;
- #size-cells = <1>;
-
- sn: sn at 14 {
- reg = <0x14 0x10>;
- };
-
- eth_mac: eth_mac at 34 {
- reg = <0x34 0x10>;
- };
-
- bid: bid at 46 {
- reg = <0x46 0x30>;
- };
- };
-
soc {
usb0_phy: phy at c0000000 {
compatible = "amlogic,meson-gxbb-usb2-phy";
@@ -117,73 +93,17 @@
dr_mode = "host";
status = "disabled";
};
-
- ethmac: ethernet at c9410000 {
- compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
- reg = <0x0 0xc9410000 0x0 0x10000
- 0x0 0xc8834540 0x0 0x4>;
- interrupts = <0 8 1>;
- interrupt-names = "macirq";
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
- phy-mode = "rgmii";
- status = "disabled";
- };
};
};
-&cbus {
- reset: reset-controller at 4404 {
- compatible = "amlogic,meson-gxbb-reset";
- reg = <0x0 0x04404 0x0 0x20>;
- #reset-cells = <1>;
- };
-
- uart_B: serial at 84dc {
- compatible = "amlogic,meson-uart";
- reg = <0x0 0x84dc 0x0 0x14>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
- status = "disabled";
- };
-
- pwm_ab: pwm at 8550 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x08550 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm_cd: pwm at 8650 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x08650 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm_ef: pwm at 86c0 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x086c0 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- uart_C: serial at 8700 {
- compatible = "amlogic,meson-uart";
- reg = <0x0 0x8700 0x0 0x14>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
- status = "disabled";
- };
-
- watchdog at 98d0 {
- compatible = "amlogic,meson-gxbb-wdt";
- reg = <0x0 0x098d0 0x0 0x10>;
- clocks = <&xtal>;
- };
+ðmac {
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+};
+&cbus {
spifc: spi at 8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
@@ -192,36 +112,6 @@
clocks = <&clkc CLKID_SPI>;
status = "disabled";
};
-
- i2c_A: i2c at 8500 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x08500 0x0 0x20>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c_B: i2c at 87c0 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x087c0 0x0 0x20>;
- interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c_C: i2c at 87e0 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x087e0 0x0 0x20>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
};
&aobus {
@@ -298,13 +188,6 @@
#reset-cells = <1>;
};
- ir: ir at 580 {
- compatible = "amlogic,meson-gxbb-ir";
- reg = <0x0 0x00580 0x0 0x40>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
pwm_ab_AO: pwm at 550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x0550 0x0 0x10>;
@@ -324,11 +207,6 @@
};
&periphs {
- rng {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0x0 0x0 0x4>;
- };
-
pinctrl_periphs: pinctrl at 4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
#address-cells = <2>;
@@ -536,15 +414,18 @@
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
+};
- mailbox: mailbox at 404 {
- compatible = "amlogic,meson-gxbb-mhu";
- reg = <0 0x404 0 0x4c>;
- interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
- <0 209 IRQ_TYPE_EDGE_RISING>,
- <0 210 IRQ_TYPE_EDGE_RISING>;
- #mbox-cells = <1>;
- };
+&i2c_A {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+ clocks = <&clkc CLKID_I2C>;
};
&sd_emmc_a {
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 01/13] pinctrl: meson: Add GXL pinctrl definitions
From: Neil Armstrong @ 2016-10-21 14:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477060838-14164-1-git-send-email-narmstrong@baylibre.com>
Add support for the Amlogic Meson GXL SoC, this is a partially complete
definition only based on the Amlogic Vendor tree.
This definition differs a lot from the GXBB and needs a separate entry.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 +
drivers/pinctrl/meson/Makefile | 3 +-
drivers/pinctrl/meson/pinctrl-meson-gxl.c | 589 +++++++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 8 +
drivers/pinctrl/meson/pinctrl-meson.h | 2 +
include/dt-bindings/gpio/meson-gxl-gpio.h | 131 +++++
6 files changed, 734 insertions(+), 1 deletion(-)
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxl.c
create mode 100644 include/dt-bindings/gpio/meson-gxl-gpio.h
diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index fe7fe0b..2392557 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -7,6 +7,8 @@ Required properties for the root node:
"amlogic,meson8b-aobus-pinctrl"
"amlogic,meson-gxbb-periphs-pinctrl"
"amlogic,meson-gxbb-aobus-pinctrl"
+ "amlogic,meson-gxl-periphs-pinctrl"
+ "amlogic,meson-gxl-aobus-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 24434f1..27c5b51 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -1,2 +1,3 @@
-obj-y += pinctrl-meson8.o pinctrl-meson8b.o pinctrl-meson-gxbb.o
+obj-y += pinctrl-meson8.o pinctrl-meson8b.o
+obj-y += pinctrl-meson-gxbb.o pinctrl-meson-gxl.o
obj-y += pinctrl-meson.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
new file mode 100644
index 0000000..25694f7
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -0,0 +1,589 @@
+/*
+ * Pin controller and GPIO driver for Amlogic Meson GXL.
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/gpio/meson-gxl-gpio.h>
+#include "pinctrl-meson.h"
+
+#define EE_OFF 10
+
+static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = {
+ MESON_PIN(GPIOZ_0, EE_OFF),
+ MESON_PIN(GPIOZ_1, EE_OFF),
+ MESON_PIN(GPIOZ_2, EE_OFF),
+ MESON_PIN(GPIOZ_3, EE_OFF),
+ MESON_PIN(GPIOZ_4, EE_OFF),
+ MESON_PIN(GPIOZ_5, EE_OFF),
+ MESON_PIN(GPIOZ_6, EE_OFF),
+ MESON_PIN(GPIOZ_7, EE_OFF),
+ MESON_PIN(GPIOZ_8, EE_OFF),
+ MESON_PIN(GPIOZ_9, EE_OFF),
+ MESON_PIN(GPIOZ_10, EE_OFF),
+ MESON_PIN(GPIOZ_11, EE_OFF),
+ MESON_PIN(GPIOZ_12, EE_OFF),
+ MESON_PIN(GPIOZ_13, EE_OFF),
+ MESON_PIN(GPIOZ_14, EE_OFF),
+ MESON_PIN(GPIOZ_15, EE_OFF),
+
+ MESON_PIN(GPIOH_0, EE_OFF),
+ MESON_PIN(GPIOH_1, EE_OFF),
+ MESON_PIN(GPIOH_2, EE_OFF),
+ MESON_PIN(GPIOH_3, EE_OFF),
+ MESON_PIN(GPIOH_4, EE_OFF),
+ MESON_PIN(GPIOH_5, EE_OFF),
+ MESON_PIN(GPIOH_6, EE_OFF),
+ MESON_PIN(GPIOH_7, EE_OFF),
+ MESON_PIN(GPIOH_8, EE_OFF),
+ MESON_PIN(GPIOH_9, EE_OFF),
+
+ MESON_PIN(BOOT_0, EE_OFF),
+ MESON_PIN(BOOT_1, EE_OFF),
+ MESON_PIN(BOOT_2, EE_OFF),
+ MESON_PIN(BOOT_3, EE_OFF),
+ MESON_PIN(BOOT_4, EE_OFF),
+ MESON_PIN(BOOT_5, EE_OFF),
+ MESON_PIN(BOOT_6, EE_OFF),
+ MESON_PIN(BOOT_7, EE_OFF),
+ MESON_PIN(BOOT_8, EE_OFF),
+ MESON_PIN(BOOT_9, EE_OFF),
+ MESON_PIN(BOOT_10, EE_OFF),
+ MESON_PIN(BOOT_11, EE_OFF),
+ MESON_PIN(BOOT_12, EE_OFF),
+ MESON_PIN(BOOT_13, EE_OFF),
+ MESON_PIN(BOOT_14, EE_OFF),
+ MESON_PIN(BOOT_15, EE_OFF),
+
+ MESON_PIN(CARD_0, EE_OFF),
+ MESON_PIN(CARD_1, EE_OFF),
+ MESON_PIN(CARD_2, EE_OFF),
+ MESON_PIN(CARD_3, EE_OFF),
+ MESON_PIN(CARD_4, EE_OFF),
+ MESON_PIN(CARD_5, EE_OFF),
+ MESON_PIN(CARD_6, EE_OFF),
+
+ MESON_PIN(GPIODV_0, EE_OFF),
+ MESON_PIN(GPIODV_1, EE_OFF),
+ MESON_PIN(GPIODV_2, EE_OFF),
+ MESON_PIN(GPIODV_3, EE_OFF),
+ MESON_PIN(GPIODV_4, EE_OFF),
+ MESON_PIN(GPIODV_5, EE_OFF),
+ MESON_PIN(GPIODV_6, EE_OFF),
+ MESON_PIN(GPIODV_7, EE_OFF),
+ MESON_PIN(GPIODV_8, EE_OFF),
+ MESON_PIN(GPIODV_9, EE_OFF),
+ MESON_PIN(GPIODV_10, EE_OFF),
+ MESON_PIN(GPIODV_11, EE_OFF),
+ MESON_PIN(GPIODV_12, EE_OFF),
+ MESON_PIN(GPIODV_13, EE_OFF),
+ MESON_PIN(GPIODV_14, EE_OFF),
+ MESON_PIN(GPIODV_15, EE_OFF),
+ MESON_PIN(GPIODV_16, EE_OFF),
+ MESON_PIN(GPIODV_17, EE_OFF),
+ MESON_PIN(GPIODV_19, EE_OFF),
+ MESON_PIN(GPIODV_20, EE_OFF),
+ MESON_PIN(GPIODV_21, EE_OFF),
+ MESON_PIN(GPIODV_22, EE_OFF),
+ MESON_PIN(GPIODV_23, EE_OFF),
+ MESON_PIN(GPIODV_24, EE_OFF),
+ MESON_PIN(GPIODV_25, EE_OFF),
+ MESON_PIN(GPIODV_26, EE_OFF),
+ MESON_PIN(GPIODV_27, EE_OFF),
+ MESON_PIN(GPIODV_28, EE_OFF),
+ MESON_PIN(GPIODV_29, EE_OFF),
+
+ MESON_PIN(GPIOX_0, EE_OFF),
+ MESON_PIN(GPIOX_1, EE_OFF),
+ MESON_PIN(GPIOX_2, EE_OFF),
+ MESON_PIN(GPIOX_3, EE_OFF),
+ MESON_PIN(GPIOX_4, EE_OFF),
+ MESON_PIN(GPIOX_5, EE_OFF),
+ MESON_PIN(GPIOX_6, EE_OFF),
+ MESON_PIN(GPIOX_7, EE_OFF),
+ MESON_PIN(GPIOX_8, EE_OFF),
+ MESON_PIN(GPIOX_9, EE_OFF),
+ MESON_PIN(GPIOX_10, EE_OFF),
+ MESON_PIN(GPIOX_11, EE_OFF),
+ MESON_PIN(GPIOX_12, EE_OFF),
+ MESON_PIN(GPIOX_13, EE_OFF),
+ MESON_PIN(GPIOX_14, EE_OFF),
+ MESON_PIN(GPIOX_15, EE_OFF),
+ MESON_PIN(GPIOX_16, EE_OFF),
+ MESON_PIN(GPIOX_17, EE_OFF),
+ MESON_PIN(GPIOX_18, EE_OFF),
+
+ MESON_PIN(GPIOCLK_0, EE_OFF),
+ MESON_PIN(GPIOCLK_1, EE_OFF),
+
+ MESON_PIN(GPIO_TEST_N, EE_OFF),
+};
+
+static const unsigned int emmc_nand_d07_pins[] = {
+ PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
+ PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
+ PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
+};
+static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
+
+static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
+static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
+static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
+static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
+static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
+static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
+
+static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) };
+static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) };
+static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) };
+static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) };
+static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) };
+static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) };
+static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) };
+
+static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) };
+
+static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) };
+
+static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) };
+static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) };
+
+static const unsigned int uart_tx_c_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int uart_rx_c_pins[] = { PIN(GPIOX_9, EE_OFF) };
+
+static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) };
+static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) };
+
+static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
+static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
+
+static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) };
+static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) };
+
+static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
+static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) };
+static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) };
+
+static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) };
+
+static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = {
+ MESON_PIN(GPIOAO_0, 0),
+ MESON_PIN(GPIOAO_1, 0),
+ MESON_PIN(GPIOAO_2, 0),
+ MESON_PIN(GPIOAO_3, 0),
+ MESON_PIN(GPIOAO_4, 0),
+ MESON_PIN(GPIOAO_5, 0),
+ MESON_PIN(GPIOAO_6, 0),
+ MESON_PIN(GPIOAO_7, 0),
+ MESON_PIN(GPIOAO_8, 0),
+ MESON_PIN(GPIOAO_9, 0),
+};
+
+static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) };
+static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
+static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_1, 0),
+ PIN(GPIOAO_5, 0) };
+static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
+
+static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) };
+
+static struct meson_pmx_group meson_gxl_periphs_groups[] = {
+ GPIO_GROUP(GPIOZ_0, EE_OFF),
+ GPIO_GROUP(GPIOZ_1, EE_OFF),
+ GPIO_GROUP(GPIOZ_2, EE_OFF),
+ GPIO_GROUP(GPIOZ_3, EE_OFF),
+ GPIO_GROUP(GPIOZ_4, EE_OFF),
+ GPIO_GROUP(GPIOZ_5, EE_OFF),
+ GPIO_GROUP(GPIOZ_6, EE_OFF),
+ GPIO_GROUP(GPIOZ_7, EE_OFF),
+ GPIO_GROUP(GPIOZ_8, EE_OFF),
+ GPIO_GROUP(GPIOZ_9, EE_OFF),
+ GPIO_GROUP(GPIOZ_10, EE_OFF),
+ GPIO_GROUP(GPIOZ_11, EE_OFF),
+ GPIO_GROUP(GPIOZ_12, EE_OFF),
+ GPIO_GROUP(GPIOZ_13, EE_OFF),
+ GPIO_GROUP(GPIOZ_14, EE_OFF),
+ GPIO_GROUP(GPIOZ_15, EE_OFF),
+
+ GPIO_GROUP(GPIOH_0, EE_OFF),
+ GPIO_GROUP(GPIOH_1, EE_OFF),
+ GPIO_GROUP(GPIOH_2, EE_OFF),
+ GPIO_GROUP(GPIOH_3, EE_OFF),
+ GPIO_GROUP(GPIOH_4, EE_OFF),
+ GPIO_GROUP(GPIOH_5, EE_OFF),
+ GPIO_GROUP(GPIOH_6, EE_OFF),
+ GPIO_GROUP(GPIOH_7, EE_OFF),
+ GPIO_GROUP(GPIOH_8, EE_OFF),
+ GPIO_GROUP(GPIOH_9, EE_OFF),
+
+ GPIO_GROUP(BOOT_0, EE_OFF),
+ GPIO_GROUP(BOOT_1, EE_OFF),
+ GPIO_GROUP(BOOT_2, EE_OFF),
+ GPIO_GROUP(BOOT_3, EE_OFF),
+ GPIO_GROUP(BOOT_4, EE_OFF),
+ GPIO_GROUP(BOOT_5, EE_OFF),
+ GPIO_GROUP(BOOT_6, EE_OFF),
+ GPIO_GROUP(BOOT_7, EE_OFF),
+ GPIO_GROUP(BOOT_8, EE_OFF),
+ GPIO_GROUP(BOOT_9, EE_OFF),
+ GPIO_GROUP(BOOT_10, EE_OFF),
+ GPIO_GROUP(BOOT_11, EE_OFF),
+ GPIO_GROUP(BOOT_12, EE_OFF),
+ GPIO_GROUP(BOOT_13, EE_OFF),
+ GPIO_GROUP(BOOT_14, EE_OFF),
+ GPIO_GROUP(BOOT_15, EE_OFF),
+
+ GPIO_GROUP(CARD_0, EE_OFF),
+ GPIO_GROUP(CARD_1, EE_OFF),
+ GPIO_GROUP(CARD_2, EE_OFF),
+ GPIO_GROUP(CARD_3, EE_OFF),
+ GPIO_GROUP(CARD_4, EE_OFF),
+ GPIO_GROUP(CARD_5, EE_OFF),
+ GPIO_GROUP(CARD_6, EE_OFF),
+
+ GPIO_GROUP(GPIODV_0, EE_OFF),
+ GPIO_GROUP(GPIODV_1, EE_OFF),
+ GPIO_GROUP(GPIODV_2, EE_OFF),
+ GPIO_GROUP(GPIODV_3, EE_OFF),
+ GPIO_GROUP(GPIODV_4, EE_OFF),
+ GPIO_GROUP(GPIODV_5, EE_OFF),
+ GPIO_GROUP(GPIODV_6, EE_OFF),
+ GPIO_GROUP(GPIODV_7, EE_OFF),
+ GPIO_GROUP(GPIODV_8, EE_OFF),
+ GPIO_GROUP(GPIODV_9, EE_OFF),
+ GPIO_GROUP(GPIODV_10, EE_OFF),
+ GPIO_GROUP(GPIODV_11, EE_OFF),
+ GPIO_GROUP(GPIODV_12, EE_OFF),
+ GPIO_GROUP(GPIODV_13, EE_OFF),
+ GPIO_GROUP(GPIODV_14, EE_OFF),
+ GPIO_GROUP(GPIODV_15, EE_OFF),
+ GPIO_GROUP(GPIODV_16, EE_OFF),
+ GPIO_GROUP(GPIODV_17, EE_OFF),
+ GPIO_GROUP(GPIODV_19, EE_OFF),
+ GPIO_GROUP(GPIODV_20, EE_OFF),
+ GPIO_GROUP(GPIODV_21, EE_OFF),
+ GPIO_GROUP(GPIODV_22, EE_OFF),
+ GPIO_GROUP(GPIODV_23, EE_OFF),
+ GPIO_GROUP(GPIODV_24, EE_OFF),
+ GPIO_GROUP(GPIODV_25, EE_OFF),
+ GPIO_GROUP(GPIODV_26, EE_OFF),
+ GPIO_GROUP(GPIODV_27, EE_OFF),
+ GPIO_GROUP(GPIODV_28, EE_OFF),
+ GPIO_GROUP(GPIODV_29, EE_OFF),
+
+ GPIO_GROUP(GPIOX_0, EE_OFF),
+ GPIO_GROUP(GPIOX_1, EE_OFF),
+ GPIO_GROUP(GPIOX_2, EE_OFF),
+ GPIO_GROUP(GPIOX_3, EE_OFF),
+ GPIO_GROUP(GPIOX_4, EE_OFF),
+ GPIO_GROUP(GPIOX_5, EE_OFF),
+ GPIO_GROUP(GPIOX_6, EE_OFF),
+ GPIO_GROUP(GPIOX_7, EE_OFF),
+ GPIO_GROUP(GPIOX_8, EE_OFF),
+ GPIO_GROUP(GPIOX_9, EE_OFF),
+ GPIO_GROUP(GPIOX_10, EE_OFF),
+ GPIO_GROUP(GPIOX_11, EE_OFF),
+ GPIO_GROUP(GPIOX_12, EE_OFF),
+ GPIO_GROUP(GPIOX_13, EE_OFF),
+ GPIO_GROUP(GPIOX_14, EE_OFF),
+ GPIO_GROUP(GPIOX_15, EE_OFF),
+ GPIO_GROUP(GPIOX_16, EE_OFF),
+ GPIO_GROUP(GPIOX_17, EE_OFF),
+ GPIO_GROUP(GPIOX_18, EE_OFF),
+
+ GPIO_GROUP(GPIOCLK_0, EE_OFF),
+ GPIO_GROUP(GPIOCLK_1, EE_OFF),
+
+ GPIO_GROUP(GPIO_TEST_N, EE_OFF),
+
+ /* Bank X */
+ GROUP(sdio_d0, 5, 31),
+ GROUP(sdio_d1, 5, 30),
+ GROUP(sdio_d2, 5, 29),
+ GROUP(sdio_d3, 5, 28),
+ GROUP(sdio_cmd, 5, 27),
+ GROUP(sdio_clk, 5, 26),
+ GROUP(sdio_irq, 5, 24),
+ GROUP(uart_tx_a, 5, 19),
+ GROUP(uart_rx_a, 5, 18),
+ GROUP(uart_cts_a, 5, 17),
+ GROUP(uart_rts_a, 5, 16),
+ GROUP(uart_tx_c, 5, 13),
+ GROUP(uart_rx_c, 5, 12),
+ GROUP(pwm_e, 5, 15),
+
+ /* Bank Z */
+ GROUP(eth_mdio, 4, 22),
+ GROUP(eth_mdc, 4, 23),
+ GROUP(eth_clk_rx_clk, 4, 21),
+ GROUP(eth_rx_dv, 4, 20),
+ GROUP(eth_rxd0, 4, 19),
+ GROUP(eth_rxd1, 4, 18),
+ GROUP(eth_rxd2, 4, 17),
+ GROUP(eth_rxd3, 4, 16),
+ GROUP(eth_rgmii_tx_clk, 4, 15),
+ GROUP(eth_tx_en, 4, 14),
+ GROUP(eth_txd0, 4, 13),
+ GROUP(eth_txd1, 4, 12),
+ GROUP(eth_txd2, 4, 11),
+ GROUP(eth_txd3, 4, 10),
+
+ /* Bank DV */
+ GROUP(uart_tx_b, 2, 16),
+ GROUP(uart_rx_b, 2, 15),
+ GROUP(i2c_sck_a, 1, 15),
+ GROUP(i2c_sda_a, 1, 14),
+ GROUP(i2c_sck_b, 1, 13),
+ GROUP(i2c_sda_b, 1, 12),
+ GROUP(i2c_sck_c, 1, 11),
+ GROUP(i2c_sda_c, 1, 10),
+
+ /* Bank BOOT */
+ GROUP(emmc_nand_d07, 7, 31),
+ GROUP(emmc_clk, 7, 30),
+ GROUP(emmc_cmd, 7, 29),
+ GROUP(emmc_ds, 7, 28),
+ GROUP(nand_ce0, 7, 7),
+ GROUP(nand_ce1, 7, 6),
+ GROUP(nand_rb0, 7, 5),
+ GROUP(nand_ale, 7, 4),
+ GROUP(nand_cle, 7, 3),
+ GROUP(nand_wen_clk, 7, 2),
+ GROUP(nand_ren_wr, 7, 1),
+ GROUP(nand_dqs, 7, 0),
+
+ /* Bank CARD */
+ GROUP(sdcard_d1, 6, 5),
+ GROUP(sdcard_d0, 6, 4),
+ GROUP(sdcard_d3, 6, 1),
+ GROUP(sdcard_d2, 6, 0),
+ GROUP(sdcard_cmd, 6, 2),
+ GROUP(sdcard_clk, 6, 3),
+};
+
+static struct meson_pmx_group meson_gxl_aobus_groups[] = {
+ GPIO_GROUP(GPIOAO_0, 0),
+ GPIO_GROUP(GPIOAO_1, 0),
+ GPIO_GROUP(GPIOAO_2, 0),
+ GPIO_GROUP(GPIOAO_3, 0),
+ GPIO_GROUP(GPIOAO_4, 0),
+ GPIO_GROUP(GPIOAO_5, 0),
+ GPIO_GROUP(GPIOAO_6, 0),
+ GPIO_GROUP(GPIOAO_7, 0),
+ GPIO_GROUP(GPIOAO_8, 0),
+ GPIO_GROUP(GPIOAO_9, 0),
+
+ /* bank AO */
+ GROUP(uart_tx_ao_b, 0, 26),
+ GROUP(uart_rx_ao_b, 0, 25),
+ GROUP(uart_tx_ao_a, 0, 12),
+ GROUP(uart_rx_ao_a, 0, 11),
+ GROUP(uart_cts_ao_a, 0, 10),
+ GROUP(uart_rts_ao_a, 0, 9),
+ GROUP(uart_cts_ao_b, 0, 8),
+ GROUP(uart_rts_ao_b, 0, 7),
+ GROUP(remote_input_ao, 0, 0),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
+ "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
+ "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
+ "GPIOZ_15",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
+ "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
+
+ "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
+ "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
+ "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
+ "BOOT_15",
+
+ "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
+ "CARD_5", "CARD_6",
+
+ "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
+ "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
+ "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
+ "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
+ "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
+ "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18",
+
+ "GPIO_TEST_N",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
+ "sdcard_cmd", "sdcard_clk",
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
+ "sdio_cmd", "sdio_clk", "sdio_irq",
+};
+
+static const char * const nand_groups[] = {
+ "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+ "nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_tx_b", "uart_rx_b",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_tx_c", "uart_rx_c",
+};
+
+static const char * const i2c_a_groups[] = {
+ "i2c_sck_a", "i2c_sda_a",
+};
+
+static const char * const i2c_b_groups[] = {
+ "i2c_sck_b", "i2c_sda_b",
+};
+
+static const char * const i2c_c_groups[] = {
+ "i2c_sck_c", "i2c_sda_c",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
+ "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
+ "eth_rgmii_tx_clk", "eth_tx_en",
+ "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e",
+};
+
+static const char * const gpio_aobus_groups[] = {
+ "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
+ "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
+};
+
+static const char * const uart_ao_groups[] = {
+ "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
+};
+
+static const char * const remote_input_ao_groups[] = {
+ "remote_input_ao",
+};
+
+static struct meson_pmx_func meson_gxl_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(emmc),
+ FUNCTION(sdcard),
+ FUNCTION(sdio),
+ FUNCTION(nand),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(i2c_a),
+ FUNCTION(i2c_b),
+ FUNCTION(i2c_c),
+ FUNCTION(eth),
+ FUNCTION(pwm_e),
+};
+
+static struct meson_pmx_func meson_gxl_aobus_functions[] = {
+ FUNCTION(gpio_aobus),
+ FUNCTION(uart_ao),
+ FUNCTION(uart_ao_b),
+ FUNCTION(remote_input_ao),
+};
+
+static struct meson_bank meson_gxl_periphs_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
+ BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
+ BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+ BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
+};
+
+static struct meson_bank meson_gxl_aobus_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
+};
+
+struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .pin_base = 10,
+ .pins = meson_gxl_periphs_pins,
+ .groups = meson_gxl_periphs_groups,
+ .funcs = meson_gxl_periphs_functions,
+ .banks = meson_gxl_periphs_banks,
+ .num_pins = ARRAY_SIZE(meson_gxl_periphs_pins),
+ .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks),
+};
+
+struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
+ .name = "aobus-banks",
+ .pin_base = 0,
+ .pins = meson_gxl_aobus_pins,
+ .groups = meson_gxl_aobus_groups,
+ .funcs = meson_gxl_aobus_functions,
+ .banks = meson_gxl_aobus_banks,
+ .num_pins = ARRAY_SIZE(meson_gxl_aobus_pins),
+ .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups),
+ .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions),
+ .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks),
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 57122ed..a579126 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -524,6 +524,14 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
.compatible = "amlogic,meson-gxbb-aobus-pinctrl",
.data = &meson_gxbb_aobus_pinctrl_data,
},
+ {
+ .compatible = "amlogic,meson-gxl-periphs-pinctrl",
+ .data = &meson_gxl_periphs_pinctrl_data,
+ },
+ {
+ .compatible = "amlogic,meson-gxl-aobus-pinctrl",
+ .data = &meson_gxl_aobus_pinctrl_data,
+ },
{ },
};
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 98b5080..1aa871d 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -169,3 +169,5 @@ struct meson_pinctrl {
extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data;
extern struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data;
extern struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data;
+extern struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data;
+extern struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data;
diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h
new file mode 100644
index 0000000..684d0d7
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-gxl-gpio.h
@@ -0,0 +1,131 @@
+/*
+ * GPIO definitions for Amlogic Meson GXL SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H
+#define _DT_BINDINGS_MESON_GXL_GPIO_H
+
+#define GPIOAO_0 0
+#define GPIOAO_1 1
+#define GPIOAO_2 2
+#define GPIOAO_3 3
+#define GPIOAO_4 4
+#define GPIOAO_5 5
+#define GPIOAO_6 6
+#define GPIOAO_7 7
+#define GPIOAO_8 8
+#define GPIOAO_9 9
+
+#define GPIOZ_0 0
+#define GPIOZ_1 1
+#define GPIOZ_2 2
+#define GPIOZ_3 3
+#define GPIOZ_4 4
+#define GPIOZ_5 5
+#define GPIOZ_6 6
+#define GPIOZ_7 7
+#define GPIOZ_8 8
+#define GPIOZ_9 9
+#define GPIOZ_10 10
+#define GPIOZ_11 11
+#define GPIOZ_12 12
+#define GPIOZ_13 13
+#define GPIOZ_14 14
+#define GPIOZ_15 15
+#define GPIOH_0 16
+#define GPIOH_1 17
+#define GPIOH_2 18
+#define GPIOH_3 19
+#define GPIOH_4 20
+#define GPIOH_5 21
+#define GPIOH_6 22
+#define GPIOH_7 23
+#define GPIOH_8 24
+#define GPIOH_9 25
+#define BOOT_0 26
+#define BOOT_1 27
+#define BOOT_2 28
+#define BOOT_3 29
+#define BOOT_4 30
+#define BOOT_5 31
+#define BOOT_6 32
+#define BOOT_7 33
+#define BOOT_8 34
+#define BOOT_9 35
+#define BOOT_10 36
+#define BOOT_11 37
+#define BOOT_12 38
+#define BOOT_13 39
+#define BOOT_14 40
+#define BOOT_15 41
+#define CARD_0 42
+#define CARD_1 43
+#define CARD_2 44
+#define CARD_3 45
+#define CARD_4 46
+#define CARD_5 47
+#define CARD_6 48
+#define GPIODV_0 49
+#define GPIODV_1 50
+#define GPIODV_2 51
+#define GPIODV_3 52
+#define GPIODV_4 53
+#define GPIODV_5 54
+#define GPIODV_6 55
+#define GPIODV_7 56
+#define GPIODV_8 57
+#define GPIODV_9 58
+#define GPIODV_10 59
+#define GPIODV_11 60
+#define GPIODV_12 61
+#define GPIODV_13 62
+#define GPIODV_14 63
+#define GPIODV_15 64
+#define GPIODV_16 65
+#define GPIODV_17 66
+#define GPIODV_18 67
+#define GPIODV_19 68
+#define GPIODV_20 69
+#define GPIODV_21 70
+#define GPIODV_22 71
+#define GPIODV_23 72
+#define GPIODV_24 73
+#define GPIODV_25 74
+#define GPIODV_26 75
+#define GPIODV_27 76
+#define GPIODV_28 77
+#define GPIODV_29 78
+#define GPIOX_0 79
+#define GPIOX_1 80
+#define GPIOX_2 81
+#define GPIOX_3 82
+#define GPIOX_4 83
+#define GPIOX_5 84
+#define GPIOX_6 85
+#define GPIOX_7 86
+#define GPIOX_8 87
+#define GPIOX_9 88
+#define GPIOX_10 89
+#define GPIOX_11 90
+#define GPIOX_12 91
+#define GPIOX_13 92
+#define GPIOX_14 93
+#define GPIOX_15 94
+#define GPIOX_16 95
+#define GPIOX_17 96
+#define GPIOX_18 97
+#define GPIOCLK_0 98
+#define GPIOCLK_1 99
+#define GPIO_TEST_N 100
+
+#endif
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 00/13] ARM64: meson-gxl: Add extended support
From: Neil Armstrong @ 2016-10-21 14:40 UTC (permalink / raw)
To: linux-arm-kernel
This RFC patchset provides extended peripheral support for the Amlogix GXL SoCs.
The final patchs will be split among the correct subsystems.
In order to support more functionalities, this patchset :
- Moves peripheral nodes to the common Meson arm64 dtsi
- Add i2c, mmc, sd, sdio, pinctrl and clock nodes for GXL
- Adds correct GXL P23X boards uart pinctrl
- Adds the GXL Internal PHY driver
- Add a temporary workaround to select the internal PHY
- Add Ethernet nodes for GXL and the P23X boards
- Add SD/MMC and SDIO WiFi support support for P23X boards
Neil Armstrong (13):
pinctrl: meson: Add GXL pinctrl definitions
ARM64: dts: meson-gxbb: Move common nodes to meson-gx
ARM64: dts: meson-gxl: Add pinctrl nodes
ARM64: dts: meson-gxl: Add clock nodes
ARM64: dts: meson-gxl: Add i2c nodes
ARM64: dts: meson-gxl: Add MMC/SD/SDIO nodes
ARM64: dts: meson-gxl-p23x: Add uart pinctrl
dwmac-meson8b: add support for phy selection
net: phy: Add Meson GXL Internal PHY driver
ARM64: dts: meson-gxl: Add ethernet nodes with internal PHY
ARM64: dts: meson-gxl-p23x: Enable ethernet
ARM64: dts: meson-gxl-p23x: Add SD/SDIO/MMC and PWM nodes
ARM64: dts: meson-gxl-p23x: Enable IR receiver
.../devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 131 +++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 155 +-----
.../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 125 +++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 238 +++++++++
.../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 25 +
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/meson-gxl.c | 175 ++++++
drivers/pinctrl/meson/Makefile | 3 +-
drivers/pinctrl/meson/pinctrl-meson-gxl.c | 589 +++++++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 8 +
drivers/pinctrl/meson/pinctrl-meson.h | 2 +
include/dt-bindings/gpio/meson-gxl-gpio.h | 131 +++++
14 files changed, 1452 insertions(+), 138 deletions(-)
create mode 100644 drivers/net/phy/meson-gxl.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxl.c
create mode 100644 include/dt-bindings/gpio/meson-gxl-gpio.h
--
1.9.1
^ permalink raw reply
* [PATCH] PM / Domains: Restrict "samsung, power-domain" checks to ARCH_EXYNOS
From: Geert Uytterhoeven @ 2016-10-21 14:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cb15013d-9694-b27c-dd5e-8c916c2e9fb7@osg.samsung.com>
Hi Javier,
On Fri, Oct 21, 2016 at 4:18 PM, Javier Martinez Canillas
<javier@osg.samsung.com> wrote:
> On 10/21/2016 11:14 AM, Sylwester Nawrocki wrote:
>> On 10/21/2016 03:58 PM, Krzysztof Kozlowski wrote:
>>> The samsung,power-domain was made deprecated (although not explicitly)
>>> in January 2015 (0da658704136 ("ARM: dts: convert to generic power
>>> domain bindings for exynos DT")) so how about:
>>> 1. Printing a dev_warn() about usage of deprecated bindings.
>>> 2. Complete removal in January 2017?
>>
>> I doubt anyone will ever use new mainline kernel with older dts/dtb
>> so IMHO it makes sense to queue a patch removing support for the
>> deprecated compatible just now and don't bother with a warning.
>>
>
> FWIW I agree with you. I don't know of any Exynos machine that ships a DT
> as read-only. Even consumer devices like the Exynos Chromebooks use a FIT
> image (kernel + FDT bundled), so the DT can always be updated.
>
> Removing the support for the deprecated property sound sensible to me.
I'm happy to hear that!
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 1/2] iommu/dma: Implement dma_{map,unmap}_resource()
From: Robin Murphy @ 2016-10-21 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161019140252.GR9193@arm.com>
On 19/10/16 15:02, Will Deacon wrote:
> On Mon, Oct 17, 2016 at 01:05:29PM +0100, Robin Murphy wrote:
>> With the new dma_{map,unmap}_resource() functions added to the DMA API
>> for the benefit of cases like slave DMA, add suitable implementations to
>> the arsenal of our generic layer. Since cache maintenance should not be
>> a concern, these can both be standalone versions without the need for
>> architecture-specific wrappers.
>>
>> CC: Joerg Roedel <joro@8bytes.org>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>
>> Since patch 2 has a build dependency on this one, they should probably
>> go together through either the arm64 tree or the iommu tree, but I can't
>> make up my mind which one seems more appropriate...
>
> I can take it via the smmu tree, if you like. However, comment below.
I'm surprised that didn't occur to me - makes sense, thanks.
>> drivers/iommu/dma-iommu.c | 13 +++++++++++++
>> include/linux/dma-iommu.h | 4 ++++
>> 2 files changed, 17 insertions(+)
>>
>> diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
>> index c5ab8667e6f2..50acd71915db 100644
>> --- a/drivers/iommu/dma-iommu.c
>> +++ b/drivers/iommu/dma-iommu.c
>> @@ -624,6 +624,19 @@ void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
>> __iommu_dma_unmap(iommu_get_domain_for_dev(dev), sg_dma_address(sg));
>> }
>>
>> +dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
>> + size_t size, enum dma_data_direction dir, unsigned long attrs)
>> +{
>> + return iommu_dma_map_page(dev, phys_to_page(phys), offset_in_page(phys),
>> + size, dma_direction_to_prot(dir, false) | IOMMU_MMIO);
>> +}
>>
>> +void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
>> + size_t size, enum dma_data_direction dir, unsigned long attrs)
>> +{
>> + __iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle);
>> +}
>
> I think it's better to call iommu_dma_unmap_page instead. That said, are
> you sure it's safe to ignore the "size" parameter here? Is it permitted
> to unmap part of a region? If not, why does that parameter exist?
Actually, "#define iommu_dma_unmap_resource iommu_dma_unmap_page" in the
header would make life even simpler. Or is that too evil?
Glossing over the size parameter is a detail of this particular
implementation. Equivalently to iommu_dma_unmap_page(), it's there
(along with dir and attrs) to match the signature of
dma_unmap_resource(), so that arch code doesn't need yet another wrapper
for its .unmap_resource callback in dma_ops (see patch 2). As it
happens, ignoring the size is effectively extra-safe in the sense that
we're enforcing the API and not even trusting the caller - since we have
to look up the iova to free it, and that iova records the size
originally mapped, we simply unmap that original size because it makes
for simpler code and can't be wrong. See the __iommu_dma_unmap()
implementation itself.
Robin.
>
> Will
>
^ permalink raw reply
* [PATCH] dt-bindings: video: exynos7-decon: Remove obsolete samsung,power-domain property
From: Sylwester Nawrocki @ 2016-10-21 14:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477058754-13866-1-git-send-email-krzk@kernel.org>
On 10/21/2016 04:05 PM, Krzysztof Kozlowski wrote:
> The samsung,power-domain property is obsolete since commit 0da658704136
> ("ARM: dts: convert to generic power domain bindings for exynos DT").
> Replace it with generic one.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
^ permalink raw reply
* [RFC] ARM: dts: exynos: Remove exynos4415.dtsi
From: Sylwester Nawrocki @ 2016-10-21 14:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477059331-14586-1-git-send-email-krzk@kernel.org>
On 10/21/2016 04:15 PM, Krzysztof Kozlowski wrote:
> There are no boards in mainline using exynos4415.dtsi. This is DTS
> was not tested for long. I am also not aware of any popular out-of-tree
> boards using this (except consumer devices released by Samsung but those
> cannot use mainline).
>
> Keeping Exynos4415 costs some useless effort so remove it.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
It seems a sane thing to do, I don't know of any active platform that
uses Exynos4415.
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
^ permalink raw reply
* [RFC,v1,2/2] vfio/iommu-type1: set only stage 2 translation
From: Alex Williamson @ 2016-10-21 14:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477024764-79882-2-git-send-email-songwenjun@huawei.com>
On Fri, 21 Oct 2016 12:39:24 +0800
Rick Song <songwenjun@huawei.com> wrote:
> Normally, VFIO should use only stage 2 translation of
> iommu, to create the address mapping. If nesting translation
> is disabled from VFIO core, enable iommu domain only stage 2
> attribute, otherwise, enable iommu domain nesting attribute.
>
> Signed-off-by: Rick Song <songwenjun@huawei.com>
> ---
> drivers/vfio/vfio_iommu_type1.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
> index 2ba1942..c0265fe 100644
> --- a/drivers/vfio/vfio_iommu_type1.c
> +++ b/drivers/vfio/vfio_iommu_type1.c
> @@ -741,7 +741,7 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
> struct vfio_group *group, *g;
> struct vfio_domain *domain, *d;
> struct bus_type *bus = NULL;
> - int ret;
> + int attr, ret;
>
> mutex_lock(&iommu->lock);
>
> @@ -775,13 +775,22 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
> goto out_free;
> }
>
> + /*
> + * Set iommu nesting domain attribute if nesting translation
> + * is enabled from iommu vfio, otherwise set iommu only stage
> + * 2 domain attribute.
> + */
> + attr = 1;
> if (iommu->nesting) {
> - int attr = 1;
> -
> ret = iommu_domain_set_attr(domain->domain, DOMAIN_ATTR_NESTING,
> &attr);
> if (ret)
> goto out_domain;
> + } else {
> + ret = iommu_domain_set_attr(domain->domain, DOMAIN_ATTR_S2,
> + &attr);
> + if (ret)
> + goto out_domain;
> }
This attribute is not relevant to the majority of current users, why
would we assume that we need to call it for all non-nesting cases? Why
do we need to set the attribute at all, what benefit does it provide?
If this is the normal case for an IOMMU API domain, why is there an
option for it at all? Maybe this should be the default and S1
(whatever that means) should be the alternate option. Thanks,
Alex
>
> ret = iommu_attach_group(domain->domain, iommu_group);
^ permalink raw reply
* [PATCH] PM / Domains: Restrict "samsung,power-domain" checks to ARCH_EXYNOS
From: Javier Martinez Canillas @ 2016-10-21 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <96efd5b7-5f62-8146-13de-44b5ff7dd496@samsung.com>
Hello Sylwester,
On 10/21/2016 11:14 AM, Sylwester Nawrocki wrote:
> On 10/21/2016 03:58 PM, Krzysztof Kozlowski wrote:
>> The samsung,power-domain was made deprecated (although not explicitly)
>> in January 2015 (0da658704136 ("ARM: dts: convert to generic power
>> domain bindings for exynos DT")) so how about:
>> 1. Printing a dev_warn() about usage of deprecated bindings.
>> 2. Complete removal in January 2017?
>
> I doubt anyone will ever use new mainline kernel with older dts/dtb
> so IMHO it makes sense to queue a patch removing support for the
> deprecated compatible just now and don't bother with a warning.
>
FWIW I agree with you. I don't know of any Exynos machine that ships a DT
as read-only. Even consumer devices like the Exynos Chromebooks use a FIT
image (kernel + FDT bundled), so the DT can always be updated.
Removing the support for the deprecated property sound sensible to me.
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [RFC] ARM: dts: exynos: Remove exynos4415.dtsi
From: Krzysztof Kozlowski @ 2016-10-21 14:15 UTC (permalink / raw)
To: linux-arm-kernel
There are no boards in mainline using exynos4415.dtsi. This is DTS
was not tested for long. I am also not aware of any popular out-of-tree
boards using this (except consumer devices released by Samsung but those
cannot use mainline).
Keeping Exynos4415 costs some useless effort so remove it.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
First, get rid of the Exynos4415 DTSI. In next steps, remove also
drivers. Really no one uses it.
---
arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 575 --------------------------
arch/arm/boot/dts/exynos4415.dtsi | 650 ------------------------------
2 files changed, 1225 deletions(-)
delete mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/exynos4415.dtsi
diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
deleted file mode 100644
index 76cfd872ead3..000000000000
--- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source
- *
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- *
- * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device
- * tree nodes are listed in this file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <dt-bindings/pinctrl/samsung.h>
-
-&pinctrl_0 {
- gpa0: gpa0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpa1: gpa1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpb: gpb {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc0: gpc0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc1: gpc1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd0: gpd0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd1: gpd1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf0: gpf0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf1: gpf1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf2: gpf2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- uart0_data: uart0-data {
- samsung,pins = "gpa0-0", "gpa0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart0_fctl: uart0-fctl {
- samsung,pins = "gpa0-2", "gpa0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_data: uart1-data {
- samsung,pins = "gpa0-4", "gpa0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_fctl: uart1-fctl {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_data: uart2-data {
- samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_fctl: uart2-fctl {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart3_data: uart3-data {
- samsung,pins = "gpa1-4", "gpa1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c2_bus: i2c2-bus {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c3_bus: i2c3-bus {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi0_bus: spi0-bus {
- samsung,pins = "gpb-0", "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c4_bus: i2c4-bus {
- samsung,pins = "gpb-0", "gpb-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi1_bus: spi1-bus {
- samsung,pins = "gpb-4", "gpb-6", "gpb-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c5_bus: i2c5-bus {
- samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s1_bus: i2s1-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s2_bus: i2s2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm2_bus: pcm2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c6_bus: i2c6-bus {
- samsung,pins = "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi2_bus: spi2-bus {
- samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm0_out: pwm0-out {
- samsung,pins = "gpd0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm1_out: pwm1-out {
- samsung,pins = "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm2_out: pwm2-out {
- samsung,pins = "gpd0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm3_out: pwm3-out {
- samsung,pins = "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c7_bus: i2c7-bus {
- samsung,pins = "gpd0-2", "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c0_bus: i2c0-bus {
- samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c1_bus: i2c1-bus {
- samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_1 {
- gpk0: gpk0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk1: gpk1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk2: gpk2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk3: gpk3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl0: gpl0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm0: gpm0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm1: gpm1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm2: gpm2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm3: gpm3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm4: gpm4 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx0: gpx0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
- <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
- #interrupt-cells = <2>;
- };
-
- gpx1: gpx1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
- <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
- #interrupt-cells = <2>;
- };
-
- gpx2: gpx2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx3: gpx3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd0_clk: sd0-clk {
- samsung,pins = "gpk0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cmd: sd0-cmd {
- samsung,pins = "gpk0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cd: sd0-cd {
- samsung,pins = "gpk0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_rdqs: sd0-rdqs {
- samsung,pins = "gpk0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus1: sd0-bus-width1 {
- samsung,pins = "gpk0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus4: sd0-bus-width4 {
- samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus8: sd0-bus-width8 {
- samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_clk: sd1-clk {
- samsung,pins = "gpk1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cmd: sd1-cmd {
- samsung,pins = "gpk1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cd: sd1-cd {
- samsung,pins = "gpk1-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus1: sd1-bus-width1 {
- samsung,pins = "gpk1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus4: sd1-bus-width4 {
- samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_clk: sd2-clk {
- samsung,pins = "gpk2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cmd: sd2-cmd {
- samsung,pins = "gpk2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cd: sd2-cd {
- samsung,pins = "gpk2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus1: sd2-bus-width1 {
- samsung,pins = "gpk2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus4: sd2-bus-width4 {
- samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_io: cam-port-b-io {
- samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
- "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
- "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_b_clk_active: cam-port-b-clk-active {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_clk_idle: cam-port-b-clk-idle {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c0: fimc-is-i2c0 {
- samsung,pins = "gpm4-0", "gpm4-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c1: fimc-is-i2c1 {
- samsung,pins = "gpm4-2", "gpm4-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_uart: fimc-is-uart {
- samsung,pins = "gpm3-5", "gpm3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_2 {
- gpz: gpz {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- i2s0_bus: i2s0-bus {
- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
- "gpz-4", "gpz-5", "gpz-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi
deleted file mode 100644
index 3c40f8a956dd..000000000000
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ /dev/null
@@ -1,650 +0,0 @@
-/*
- * Samsung's Exynos4415 SoC device tree source
- *
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- *
- * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
- * based board files can include this file and provide values for board
- * specific bindings.
- *
- * Note: This file does not include device nodes for all the controllers in
- * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
- * nodes can be added to this file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <dt-bindings/clock/exynos4415.h>
-#include <dt-bindings/clock/exynos-audss-clk.h>
-
-/ {
- compatible = "samsung,exynos4415";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- pinctrl0 = &pinctrl_0;
- pinctrl1 = &pinctrl_1;
- pinctrl2 = &pinctrl_2;
- mshc0 = &mshc_0;
- mshc1 = &mshc_1;
- mshc2 = &mshc_2;
- spi0 = &spi_0;
- spi1 = &spi_1;
- spi2 = &spi_2;
- i2c0 = &i2c_0;
- i2c1 = &i2c_1;
- i2c2 = &i2c_2;
- i2c3 = &i2c_3;
- i2c4 = &i2c_4;
- i2c5 = &i2c_5;
- i2c6 = &i2c_6;
- i2c7 = &i2c_7;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu at a00 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa00>;
- clock-frequency = <1600000000>;
- };
-
- cpu1: cpu at a01 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa01>;
- clock-frequency = <1600000000>;
- };
-
- cpu2: cpu at a02 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa02>;
- clock-frequency = <1600000000>;
- };
-
- cpu3: cpu at a03 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa03>;
- clock-frequency = <1600000000>;
- };
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sysram at 02020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x50000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x02020000 0x50000>;
-
- smp-sysram at 0 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x0 0x1000>;
- };
-
- smp-sysram at 4f000 {
- compatible = "samsung,exynos4210-sysram-ns";
- reg = <0x4f000 0x1000>;
- };
- };
-
- pinctrl_2: pinctrl at 03860000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x03860000 0x1000>;
- interrupts = <0 242 0>;
- };
-
- chipid at 10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
- };
-
- sysreg_system_controller: syscon at 10010000 {
- compatible = "samsung,exynos4-sysreg", "syscon";
- reg = <0x10010000 0x400>;
- };
-
- pmu_system_controller: system-controller at 10020000 {
- compatible = "samsung,exynos4415-pmu", "syscon";
- reg = <0x10020000 0x4000>;
- };
-
- mipi_phy: video-phy at 10020710 {
- compatible = "samsung,s5pv210-mipi-video-phy";
- #phy-cells = <1>;
- syscon = <&pmu_system_controller>;
- };
-
- pd_cam: cam-power-domain at 10024000 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024000 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_tv: tv-power-domain at 10024020 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024020 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_mfc: mfc-power-domain at 10024040 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024040 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_g3d: g3d-power-domain at 10024060 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024060 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_lcd0: lcd0-power-domain at 10024080 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024080 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_isp0: isp0-power-domain at 100240A0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x100240A0 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_isp1: isp1-power-domain at 100240E0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x100240E0 0x20>;
- #power-domain-cells = <0>;
- };
-
- cmu: clock-controller at 10030000 {
- compatible = "samsung,exynos4415-cmu";
- reg = <0x10030000 0x18000>;
- #clock-cells = <1>;
- };
-
- rtc: rtc at 10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <0 73 0>, <0 74 0>;
- status = "disabled";
- };
-
- mct at 10050000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x800>;
- interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
- <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
- clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
- clock-names = "fin_pll", "mct";
- };
-
- gic: interrupt-controller at 10481000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
- <0x10484000 0x2000>,
- <0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
- l2c: l2-cache-controller at 10502000 {
- compatible = "arm,pl310-cache";
- reg = <0x10502000 0x1000>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <2 2 1>;
- arm,data-latency = <3 2 1>;
- arm,double-linefill = <1>;
- arm,double-linefill-incr = <0>;
- arm,double-linefill-wrap = <1>;
- arm,prefetch-drop = <1>;
- arm,prefetch-offset = <7>;
- };
-
- cmu_dmc: clock-controller at 105C0000 {
- compatible = "samsung,exynos4415-cmu-dmc";
- reg = <0x105C0000 0x3000>;
- #clock-cells = <1>;
- };
-
- pinctrl_1: pinctrl at 11000000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x11000000 0x1000>;
- interrupts = <0 225 0>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,exynos4210-wakeup-eint";
- interrupt-parent = <&gic>;
- interrupts = <0 48 0>;
- };
- };
-
- pinctrl_0: pinctrl at 11400000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x11400000 0x1000>;
- interrupts = <0 240 0>;
- };
-
- fimd: fimd at 11C00000 {
- compatible = "samsung,exynos4415-fimd";
- reg = <0x11C00000 0x30000>;
- interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
- clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
- clock-names = "sclk_fimd", "fimd";
- samsung,power-domain = <&pd_lcd0>;
- iommus = <&sysmmu_fimd0>;
- samsung,sysreg = <&sysreg_system_controller>;
- status = "disabled";
- };
-
- dsi_0: dsi at 11C80000 {
- compatible = "samsung,exynos4415-mipi-dsi";
- reg = <0x11C80000 0x10000>;
- interrupts = <0 83 0>;
- samsung,phy-type = <0>;
- samsung,power-domain = <&pd_lcd0>;
- phys = <&mipi_phy 1>;
- phy-names = "dsim";
- clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
- clock-names = "bus_clk", "pll_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sysmmu_fimd0: sysmmu at 11E20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11e20000 0x1000>;
- interrupts = <0 80 0>, <0 81 0>;
- clock-names = "sysmmu", "master";
- clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
- power-domains = <&pd_lcd0>;
- #iommu-cells = <0>;
- };
-
- hsotg: hsotg at 12480000 {
- compatible = "samsung,s3c6400-hsotg";
- reg = <0x12480000 0x20000>;
- interrupts = <0 141 0>;
- clocks = <&cmu CLK_USBDEVICE>;
- clock-names = "otg";
- phys = <&exynos_usbphy 0>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- mshc_0: mshc at 12510000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12510000 0x1000>;
- interrupts = <0 142 0>;
- clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mshc_1: mshc at 12520000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12520000 0x1000>;
- interrupts = <0 143 0>;
- clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mshc_2: mshc at 12530000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12530000 0x1000>;
- interrupts = <0 144 0>;
- clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ehci: ehci at 12580000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12580000 0x100>;
- interrupts = <0 140 0>;
- clocks = <&cmu CLK_USBHOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port at 0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
- status = "disabled";
- };
- port at 1 {
- reg = <1>;
- phys = <&exynos_usbphy 2>;
- status = "disabled";
- };
- port at 2 {
- reg = <2>;
- phys = <&exynos_usbphy 3>;
- status = "disabled";
- };
- };
-
- ohci: ohci at 12590000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12590000 0x100>;
- interrupts = <0 140 0>;
- clocks = <&cmu CLK_USBHOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port at 0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
- status = "disabled";
- };
- };
-
- exynos_usbphy: exynos-usbphy at 125B0000 {
- compatible = "samsung,exynos4x12-usb2-phy";
- reg = <0x125B0000 0x100>;
- samsung,pmureg-phandle = <&pmu_system_controller>;
- samsung,sysreg-phandle = <&sysreg_system_controller>;
- clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
- clock-names = "phy", "ref";
- #phy-cells = <1>;
- status = "disabled";
- };
-
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
- ranges;
-
- pdma0: pdma at 12680000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12680000 0x1000>;
- interrupts = <0 138 0>;
- clocks = <&cmu CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma at 12690000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12690000 0x1000>;
- interrupts = <0 139 0>;
- clocks = <&cmu CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
- };
-
- adc: adc at 126C0000 {
- compatible = "samsung,exynos3250-adc",
- "samsung,exynos-adc-v2";
- reg = <0x126C0000 0x100>, <0x10020718 0x4>;
- interrupts = <0 137 0>;
- clock-names = "adc", "sclk";
- clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
- #io-channel-cells = <1>;
- io-channel-ranges;
- status = "disabled";
- };
-
- serial_0: serial at 13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- interrupts = <0 109 0>;
- clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_1: serial at 13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- interrupts = <0 110 0>;
- clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_2: serial at 13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 111 0>;
- clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_3: serial at 13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- interrupts = <0 112 0>;
- clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- i2c_0: i2c at 13860000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13860000 0x100>;
- interrupts = <0 113 0>;
- clocks = <&cmu CLK_I2C0>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_bus>;
- status = "disabled";
- };
-
- i2c_1: i2c at 13870000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <0 114 0>;
- clocks = <&cmu CLK_I2C1>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_bus>;
- status = "disabled";
- };
-
- i2c_2: i2c at 13880000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13880000 0x100>;
- interrupts = <0 115 0>;
- clocks = <&cmu CLK_I2C2>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_bus>;
- status = "disabled";
- };
-
- i2c_3: i2c at 13890000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13890000 0x100>;
- interrupts = <0 116 0>;
- clocks = <&cmu CLK_I2C3>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_bus>;
- status = "disabled";
- };
-
- i2c_4: i2c at 138A0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138A0000 0x100>;
- interrupts = <0 117 0>;
- clocks = <&cmu CLK_I2C4>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_bus>;
- status = "disabled";
- };
-
- i2c_5: i2c at 138B0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138B0000 0x100>;
- interrupts = <0 118 0>;
- clocks = <&cmu CLK_I2C5>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_bus>;
- status = "disabled";
- };
-
- i2c_6: i2c at 138C0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138C0000 0x100>;
- interrupts = <0 119 0>;
- clocks = <&cmu CLK_I2C6>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_bus>;
- status = "disabled";
- };
-
- i2c_7: i2c at 138D0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138D0000 0x100>;
- interrupts = <0 120 0>;
- clocks = <&cmu CLK_I2C7>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7_bus>;
- status = "disabled";
- };
-
- spi_0: spi at 13920000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13920000 0x100>;
- interrupts = <0 121 0>;
- dmas = <&pdma0 7>, <&pdma0 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_bus>;
- status = "disabled";
- };
-
- spi_1: spi at 13930000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13930000 0x100>;
- interrupts = <0 122 0>;
- dmas = <&pdma1 7>, <&pdma1 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_bus>;
- status = "disabled";
- };
-
- spi_2: spi at 13940000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13940000 0x100>;
- interrupts = <0 123 0>;
- dmas = <&pdma0 9>, <&pdma0 8>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_bus>;
- status = "disabled";
- };
-
- clock_audss: clock-controller at 03810000 {
- compatible = "samsung,exynos4210-audss-clock";
- reg = <0x03810000 0x0C>;
- #clock-cells = <1>;
- };
-
- i2s0: i2s at 3830000 {
- compatible = "samsung,s5pv210-i2s";
- reg = <0x03830000 0x100>;
- interrupts = <0 124 0>;
- clocks = <&clock_audss EXYNOS_I2S_BUS>,
- <&clock_audss EXYNOS_SCLK_I2S>;
- clock-names = "iis", "i2s_opclk0";
- dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
- dma-names = "tx", "rx", "tx-sec";
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_bus>;
- samsung,idma-addr = <0x03000000>;
- status = "disabled";
- };
-
- pwm: pwm at 139D0000 {
- compatible = "samsung,exynos4210-pwm";
- reg = <0x139D0000 0x1000>;
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 108 0>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
- };
- };
-};
-
-#include "exynos4415-pinctrl.dtsi"
--
2.7.4
^ permalink raw reply related
* [PATCH] PM / Domains: Restrict "samsung,power-domain" checks to ARCH_EXYNOS
From: Sylwester Nawrocki @ 2016-10-21 14:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021135803.GB3289@kozik-lap>
On 10/21/2016 03:58 PM, Krzysztof Kozlowski wrote:
> The samsung,power-domain was made deprecated (although not explicitly)
> in January 2015 (0da658704136 ("ARM: dts: convert to generic power
> domain bindings for exynos DT")) so how about:
> 1. Printing a dev_warn() about usage of deprecated bindings.
> 2. Complete removal in January 2017?
I doubt anyone will ever use new mainline kernel with older dts/dtb
so IMHO it makes sense to queue a patch removing support for the
deprecated compatible just now and don't bother with a warning.
Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt
arch/arm/boot/dts/exynos4415.dtsi
would just need to be updated in same release, I can prepare a patch
for these files.
--
Thanks,
Sylwester
^ permalink raw reply
* [PATCH] hwrng: meson: Remove unneeded platform MODULE_ALIAS
From: Neil Armstrong @ 2016-10-21 14:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476906618-14455-1-git-send-email-javier@osg.samsung.com>
On 10/19/2016 09:50 PM, Javier Martinez Canillas wrote:
> The Amlogic Meson is a DT-only platform, which means the devices are
> registered via OF and not using the legacy platform devices support.
>
> So there's no need to have a MODULE_ALIAS("platform:meson-rng") since
> the reported uevent MODALIAS to user-space will always be the OF one.
>
> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
>
> drivers/char/hw_random/meson-rng.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/char/hw_random/meson-rng.c b/drivers/char/hw_random/meson-rng.c
> index 51864a509be7..119d698439ae 100644
> --- a/drivers/char/hw_random/meson-rng.c
> +++ b/drivers/char/hw_random/meson-rng.c
> @@ -122,7 +122,6 @@ static struct platform_driver meson_rng_driver = {
>
> module_platform_driver(meson_rng_driver);
>
> -MODULE_ALIAS("platform:meson-rng");
> MODULE_DESCRIPTION("Meson H/W Random Number Generator driver");
> MODULE_AUTHOR("Lawrence Mok <lawrence.mok@amlogic.com>");
> MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
* [PATCH V4 1/3] ACPI, PCI, IRQ: assign ISA IRQ directly during early boot stages
From: Bjorn Helgaas @ 2016-10-21 14:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021013930.GB31044@localhost>
On Thu, Oct 20, 2016 at 08:39:30PM -0500, Bjorn Helgaas wrote:
> On Wed, Oct 19, 2016 at 06:21:02PM -0400, Sinan Kaya wrote:
> > The penalty determination of ISA IRQ goes through 4 paths.
> > 1. assign PCI_USING during power up via acpi_irq_penalty_init.
> > 2. update the penalty with acpi_penalize_isa_irq function based on the
> > active parameter.
> > 3. kernel command line penalty update via acpi_irq_penalty_update function.
> > 4. increment the penalty as USING right after the IRQ is assign to PCI.
> >
> > acpi_penalize_isa_irq and acpi_irq_penalty_update functions get called
> > before the ACPI subsystem is started.
> >
> > These API need to bypass the acpi_irq_get_penalty function.
>
> I don't mind this patch, but the changelog doesn't tell me what's
> broken and why we need this fix. Apparently acpi_irq_get_penalty()
> doesn't work before ACPI is initialized, but I don't see *why* it
> wouldn't work.
>
> However, I see one bug it *does* fix: we do not store the SCI penalty
> in the acpi_isa_irq_penalty[] table because acpi_isa_irq_penalty[]
> only holds ISA IRQ penalties, and there's no guarantee that the SCI is
> an ISA IRQ. But prior to this patch, we added in the SCI penalty to
> the acpi_isa_irq_penalty[] entry when the SCI was an ISA IRQ, which
> makes acpi_irq_get_penalty() return the wrong thing. Consider:
>
> Initially acpi_isa_irq_penalty[9] = 0.
> Assume sci_interrupt = 9.
> Then acpi_irq_get_penalty(9) returns X.
> If we call acpi_penalize_isa_irq(9, 1),
> it sets acpi_isa_irq_penalty[9] = X,
> and now acpi_irq_get_penalty(9) returns X + X.
Oops, I forgot the penalty we *intended* to add with
acpi_penalize_isa_irq(). It's really like this, where X is the SCI
penalty and Y is the part added by acpi_penalize_isa_irq():
Initially acpi_isa_irq_penalty[9] = 0.
Assume sci_interrupt = 9.
Then acpi_irq_get_penalty(9) returns X.
If we call acpi_penalize_isa_irq(9, 1),
it sets acpi_isa_irq_penalty[9] = X + Y,
and now acpi_irq_get_penalty(9) returns X + X + Y.
At the end, acpi_irq_get_penalty(9) *should* return X + Y, but instead
it returns X + X + Y, i.e., the SCI penalty is included twice.
^ permalink raw reply
* [PATCH] PM / Domains: Restrict "samsung,power-domain" checks to ARCH_EXYNOS
From: Krzysztof Kozlowski @ 2016-10-21 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJZ5v0iOQyCwCuMBVcJjX1mMHFb=NkfXFf6yBNdswRw1HMYC=Q@mail.gmail.com>
On Fri, Oct 21, 2016 at 02:29:05PM +0200, Rafael J. Wysocki wrote:
> On Fri, Oct 21, 2016 at 1:34 PM, Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
> > Currently the generic PM Domain code code checks for the presence of
> > both (generic) "power-domains" and (Samsung Exynos legacy)
> > "samsung,power-domain" properties in all device tree nodes representing
> > devices.
> >
> > There are two issues with this:
> > 1. This imposes a small boot-time penalty on all platforms using DT,
> > 2. Platform-specific checks do not really belong in core framework
> > code.
> >
> > While moving the check from platform-agnostic code to Samsung-specific
> > code is non-trivial, the runtime overhead can be restricted to kernels
> > including support for 32-bit Samsung Exynos platforms.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > "samsung,power-domain" was only ever used in:
> > - arch/arm/boot/dts/exynos4415.dtsi: Unused?
> > - arch/arm/boot/dts/exynos3250.dtsi: CONFIG_ARCH_EXYNOS3
> > - arch/arm/boot/dts/exynos4.dtsi: CONFIG_ARCH_EXYNOS4
> > - arch/arm/boot/dts/exynos4x12.dtsi: CONFIG_ARCH_EXYNOS4
> > exynos4212.dtsi is unused?
> > - arch/arm/boot/dts/exynos5250.dtsi: CONFIG_ARCH_EXYNOS5
> > - arch/arm/boot/dts/exynos5420.dtsi: CONFIG_ARCH_EXYNOS5
> > ---
> > drivers/base/power/domain.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
> > index e023066e421547c5..d94d6a4b9b527108 100644
> > --- a/drivers/base/power/domain.c
> > +++ b/drivers/base/power/domain.c
> > @@ -1853,7 +1853,8 @@ int genpd_dev_pm_attach(struct device *dev)
> > ret = of_parse_phandle_with_args(dev->of_node, "power-domains",
> > "#power-domain-cells", 0, &pd_args);
> > if (ret < 0) {
> > - if (ret != -ENOENT)
> > + if (ret != -ENOENT || !IS_ENABLED(CONFIG_ARCH_EXYNOS) ||
>
> Please don't check things like CONFIG_ARCH_EXYNOS in the core.
>
> If you need to put checks like that here, there is a design problem somewhere.
>
> And imagine someone 5 years ahead from now looking at this code and
> wondering why on Earth the check is here.
Sorry for the noise, sending once again without bogus recipient added by
mistake:
I don't find the argument of performance penalty such important but for
the sake of design, the samsung-specific code could be moved to
drivers/soc/samsung/pm_domains.c, called "legacy_pm_parse" and exported
through a header. Thus with !ARCH_EXYNOS that would be 'static inline
{}'. However that is not a nice solution - there will be still
direct call to platform-specific code in the core. I am not sure if it
is worth the effort.
The samsung,power-domain was made deprecated (although not explicitly)
in January 2015 (0da658704136 ("ARM: dts: convert to generic power
domain bindings for exynos DT")) so how about:
1. Printing a dev_warn() about usage of deprecated bindings.
2. Complete removal in January 2017?
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/4] ARM: boot: mxs: Add On-Chip RAM
From: Stefan Wahren @ 2016-10-21 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021135343.GI30578@tiger>
Am 21.10.2016 um 15:53 schrieb Shawn Guo:
> On Tue, Sep 13, 2016 at 05:51:02PM +0000, Stefan Wahren wrote:
>> The i.MX23 / i.MX28 have a small amount of On-Chip RAM which is also necessary
>> for suspend to RAM and standby mode. But before we need to remove the fake reg
>> properties of all internal bus nodes as discussed in this thread [1].
>>
>> This patch series requires Fabio Estevam's recent series "ARM: dts: imx23:
>> Remove skeleton.dtsi inclusion" [2].
>>
>> [1] - https://marc.info/?l=devicetree&m=146139948426520&w=2
> The page cannot be reached. I would like to understand the
> background for this change.
Strange, because i don't have any problems while clicking on the URL.
It's an older discussion on the devicetree / kernel newbie mailing list
with subject "strange dtc errors after adding sram node". Arnd suggested
in the discussion to remove the reg property from the ahb node.
Please try this one: http://www.spinics.net/lists/newbies/msg57652.html
Stefan
^ permalink raw reply
* [PATCH] dt-bindings: video: exynos7-decon: Remove obsolete samsung, power-domain property
From: Krzysztof Kozlowski @ 2016-10-21 14:05 UTC (permalink / raw)
To: linux-arm-kernel
The samsung,power-domain property is obsolete since commit 0da658704136
("ARM: dts: convert to generic power domain bindings for exynos DT").
Replace it with generic one.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt b/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt
index 3938caacf11c..8346fb18a358 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt
@@ -33,7 +33,7 @@ Required properties:
- i80-if-timings: timing configuration for lcd i80 interface support.
Optional Properties:
-- samsung,power-domain: a phandle to DECON power domain node.
+- power-domains: a phandle to DECON power domain node.
- display-timings: timing settings for DECON, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
--
2.7.4
^ permalink raw reply related
* [PATCH 7/7] mfd: tps65217: Fix mismatched interrupt number
From: Milo Kim @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.21531-1-woogyom.kim@gmail.com>
Enum value of 'tps65217_irq_type' is not matched with DT parsed hwirq
number[*].
The MFD driver gets the IRQ data by referencing hwirq, but the value is
different. So, irq_to_tps65217_irq() returns mismatched IRQ data.
Eventually, the power button driver enables not PB but USB interrupt
when it is probed.
According to the TPS65217 register map[**], USB interrupt is the LSB.
This patch synchronizes TPS65217 IRQ index.
[*] include/dt-bindings/mfd/tps65217.h
[**] http://www.ti.com/lit/ds/symlink/tps65217.pdf
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
include/linux/mfd/tps65217.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index 4ccda89..75a3a5f 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -235,9 +235,9 @@ struct tps65217_bl_pdata {
};
enum tps65217_irq_type {
- TPS65217_IRQ_PB,
- TPS65217_IRQ_AC,
TPS65217_IRQ_USB,
+ TPS65217_IRQ_AC,
+ TPS65217_IRQ_PB,
TPS65217_NUM_IRQ
};
--
2.9.3
^ permalink raw reply related
* [PATCH] ahci: use pci_alloc_irq_vectors
From: Robert Richter @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021125918.GA18082@lst.de>
Christoph,
On 21.10.16 14:59:18, Christoph Hellwig wrote:
> can you try the latest fixed in the libata tree:
>
> https://git.kernel.org/cgit/linux/kernel/git/tj/libata.git/log/?h=for-4.9-fixes
I see now this warning:
WARNING: CPU: 0 PID: 1601 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
... and it still fails:
[ 21.765921] ata1.00: qc timeout (cmd 0xec)
[ 21.770031] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 22.249869] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 22.533896] ata4.00: qc timeout (cmd 0xec)
[ 22.537996] ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 23.017874] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 32.261874] ata1.00: qc timeout (cmd 0xec)
[ 32.265972] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 32.272059] ata1: limiting SATA link speed to 3.0 Gbps
[ 32.753873] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 33.029878] ata4.00: qc timeout (cmd 0xec)
[ 33.033978] ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 33.040066] ata4: limiting SATA link speed to 3.0 Gbps
[ 33.521884] ata4: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 63.493874] ata1.00: qc timeout (cmd 0xec)
[ 63.497973] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 63.977867] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 65.541890] ata4.00: qc timeout (cmd 0xec)
[ 65.545987] ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 66.025873] ata4: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 66.032337] VFS: Cannot open root device "sda2" or unknown-block(0,0): error -6
[ 66.039682] Please append a correct "root=" boot option; here are the available partitions:
[ 66.048047] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
Full log below.
(Note that I tested a backported version based on 4.8 with all your 3
patches applied.)
-Robert
[ 15.740362] ahci 0001:00:08.0: version 3.0
[ 15.744577] ahci 0001:00:08.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 15.752670] ahci 0001:00:08.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 15.762239] ahci 0001:00:08.0: port 0 is not capable of FBS
[ 15.767996] ------------[ cut here ]------------
[ 15.772610] WARNING: CPU: 0 PID: 1601 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 15.781815]
[ 15.783298] CPU: 0 PID: 1601 Comm: kworker/0:1 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 15.792677] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 15.801365] Workqueue: events work_for_cpu_fn
[ 15.805714] task: ffff800fcb5e4e00 task.stack: ffff800fcb618000
[ 15.811622] PC is at ata_host_activate+0x138/0x150
[ 15.816401] LR is at ata_host_activate+0x5c/0x150
[ 15.821094] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 15.828476] sp : ffff800fcb61bbb0
[ 15.831780] x29: ffff800fcb61bbb0 x28: 0000000000000001
[ 15.837085] x27: ffff000009245408 x26: ffff000009245bf0
[ 15.842391] x25: ffff800fca8e40a0 x24: ffff800fcb451118
[ 15.847695] x23: 0000000000000080 x22: ffff000009245bf0
[ 15.853000] x21: 0000000000000000 x20: ffff0000087cddc8
[ 15.858305] x19: ffff800fcb451218 x18: ffff0000892f7d77
[ 15.863610] x17: ffff7fe003f2e820 x16: ffffffffffffff98
[ 15.868915] x15: 0000000000000006 x14: ffff0000092f7d85
[ 15.874220] x13: ffff00000979ffff x12: 0000000000000008
[ 15.879525] x11: 0088000000000000 x10: 0140000000000040
[ 15.884829] x9 : 0000000000000000 x8 : ffff000009796500
[ 15.890135] x7 : 0000000000000006 x6 : ffff800fcb618000
[ 15.895439] x5 : ffff800fcb901b00 x4 : 0000000000000000
[ 15.900744] x3 : ffff00001b000104 x2 : ffff800fcb451118
[ 15.906049] x1 : 0000000000000040 x0 : 0000000000000000
[ 15.911354]
[ 15.912835] ---[ end trace 2c145cc81872d49e ]---
[ 15.917440] Call trace:
[ 15.919876] Exception stack(0xffff800fcb61b9e0 to 0xffff800fcb61bb10)
[ 15.926306] b9e0: ffff800fcb451218 0001000000000000 ffff800fcb61bbb0 ffff0000087b7868
[ 15.934124] ba00: ffff000009780000 0000000000020000 0000000000000008 00e800000000070f
[ 15.941942] ba20: 0000000000000000 ffff7fe000300100 ffff800fcb61bab0 ffff000008776250
[ 15.949760] ba40: ffff800fca8e40a0 ffff800fca8e4150 0000000000000004 0000000000000040
[ 15.957578] ba60: 0000000000016500 ffff800fcb451118 ffff800fcb61bab0 ffff0000087d10e8
[ 15.965396] ba80: 0000000000000000 0000000000000040 ffff800fcb451118 ffff00001b000104
[ 15.973214] baa0: 0000000000000000 ffff800fcb901b00 ffff800fcb618000 0000000000000006
[ 15.981032] bac0: ffff000009796500 0000000000000000 0140000000000040 0088000000000000
[ 15.988849] bae0: 0000000000000008 ffff00000979ffff ffff0000092f7d85 0000000000000006
[ 15.996667] bb00: ffffffffffffff98 ffff7fe003f2e820
[ 16.001533] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 16.007356] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 16.013264] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 16.018740] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 16.024214] [<ffff0000080cc458>] work_for_cpu_fn+0x18/0x28
[ 16.029689] [<ffff0000080ce710>] process_one_work+0x118/0x378
[ 16.035424] [<ffff0000080cebd8>] worker_thread+0x268/0x4b0
[ 16.040900] [<ffff0000080d4c10>] kthread+0xd0/0xe8
[ 16.045680] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 16.051483] scsi host0: ahci
[ 16.054531] ata1: SATA max UDMA/133 abar m2097152 at 0x814000000000 port 0x814000000100
[ 16.062464] ahci 0001:00:09.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 16.070558] ahci 0001:00:09.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 16.080121] ahci 0001:00:09.0: port 0 is not capable of FBS
[ 16.085790] ------------[ cut here ]------------
[ 16.090400] WARNING: CPU: 0 PID: 1601 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 16.099604]
[ 16.101086] CPU: 0 PID: 1601 Comm: kworker/0:1 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 16.110464] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 16.119150] Workqueue: events work_for_cpu_fn
[ 16.123498] task: ffff800fcb5e4e00 task.stack: ffff800fcb618000
[ 16.129406] PC is at ata_host_activate+0x138/0x150
[ 16.134186] LR is at ata_host_activate+0x5c/0x150
[ 16.138878] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 16.146260] sp : ffff800fcb61bbb0
[ 16.149563] x29: ffff800fcb61bbb0 x28: 0000000000000001
[ 16.154868] x27: ffff000009245408 x26: ffff000009245bf0
[ 16.160172] x25: ffff800fca8e60a0 x24: ffff800fcb45ff18
[ 16.165477] x23: 0000000000000080 x22: ffff000009245bf0
[ 16.170781] x21: 0000000000000000 x20: ffff0000087cddc8
[ 16.176086] x19: ffff800fcb45fe18 x18: ffff0000892f7d77
[ 16.181390] x17: ffff7fe040029e60 x16: ffffffffffffff98
[ 16.186695] x15: 0000000000000006 x14: ffff0000092f7d85
[ 16.192000] x13: ffff000009f3ffff x12: 0000000000000008
[ 16.197304] x11: 0088000000000000 x10: 0140000000000040
[ 16.202608] x9 : 0000000000000000 x8 : ffff000009f36500
[ 16.207913] x7 : 0000000000000006 x6 : ffff800fcb618000
[ 16.213218] x5 : ffff800fcb903900 x4 : 0000000000000000
[ 16.218522] x3 : ffff00001b400104 x2 : ffff800fcb45ff18
[ 16.223827] x1 : 0000000000000040 x0 : 0000000000000000
[ 16.229131]
[ 16.230612] ---[ end trace 2c145cc81872d49f ]---
[ 16.235216] Call trace:
[ 16.237652] Exception stack(0xffff800fcb61b9e0 to 0xffff800fcb61bb10)
[ 16.244081] b9e0: ffff800fcb45fe18 0001000000000000 ffff800fcb61bbb0 ffff0000087b7868
[ 16.251899] ba00: ffff000009f20000 0000000000020000 0000000000000008 00e800000000070f
[ 16.259717] ba20: 0000000000000000 ffff7fe000300180 ffff800fcb61bab0 ffff000008776250
[ 16.267535] ba40: ffff800fca8e60a0 ffff800fca8e6150 0000000000000004 0000000000000040
[ 16.275353] ba60: 0000000000016500 ffff800fcb45ff18 ffff800fcb61bab0 ffff0000087d10e8
[ 16.283170] ba80: 0000000000000000 0000000000000040 ffff800fcb45ff18 ffff00001b400104
[ 16.290988] baa0: 0000000000000000 ffff800fcb903900 ffff800fcb618000 0000000000000006
[ 16.298806] bac0: ffff000009f36500 0000000000000000 0140000000000040 0088000000000000
[ 16.306623] bae0: 0000000000000008 ffff000009f3ffff ffff0000092f7d85 0000000000000006
[ 16.314440] bb00: ffffffffffffff98 ffff7fe040029e60
[ 16.319307] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 16.325128] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 16.331036] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 16.336510] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 16.341985] [<ffff0000080cc458>] work_for_cpu_fn+0x18/0x28
[ 16.347458] [<ffff0000080ce710>] process_one_work+0x118/0x378
[ 16.353192] [<ffff0000080cebd8>] worker_thread+0x268/0x4b0
[ 16.358667] [<ffff0000080d4c10>] kthread+0xd0/0xe8
[ 16.363447] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 16.369153] scsi host1: ahci
[ 16.372172] ata2: SATA max UDMA/133 abar m2097152 at 0x815000000000 port 0x815000000100
[ 16.380095] ahci 0001:00:0a.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 16.388189] ahci 0001:00:0a.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 16.397752] ahci 0001:00:0a.0: port 0 is not capable of FBS
[ 16.403423] ------------[ cut here ]------------
[ 16.408033] WARNING: CPU: 0 PID: 1601 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 16.417238]
[ 16.418719] CPU: 0 PID: 1601 Comm: kworker/0:1 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 16.428098] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 16.436784] Workqueue: events work_for_cpu_fn
[ 16.441131] task: ffff800fcb5e4e00 task.stack: ffff800fcb618000
[ 16.447039] PC is at ata_host_activate+0x138/0x150
[ 16.451818] LR is at ata_host_activate+0x5c/0x150
[ 16.456511] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 16.463893] sp : ffff800fcb61bbb0
[ 16.467196] x29: ffff800fcb61bbb0 x28: 0000000000000001
[ 16.472501] x27: ffff000009245408 x26: ffff000009245bf0
[ 16.477806] x25: ffff800fca8e80a0 x24: ffff800fcb451b18
[ 16.483111] x23: 0000000000000080 x22: ffff000009245bf0
[ 16.488415] x21: 0000000000000000 x20: ffff0000087cddc8
[ 16.493720] x19: ffff800fcb451c18 x18: ffff0000892f7d77
[ 16.499025] x17: ffff7fe003f2e6a0 x16: ffffffffffffff98
[ 16.504330] x15: 0000000000000006 x14: ffff0000092f7d85
[ 16.509634] x13: ffff000009f6ffff x12: 0000000000000008
[ 16.514939] x11: 0088000000000000 x10: 0140000000000040
[ 16.520244] x9 : 0000000000000000 x8 : ffff000009f66500
[ 16.525548] x7 : 0000000000000006 x6 : ffff800fcb618000
[ 16.530853] x5 : ffff800fcb905780 x4 : 0000000000000000
[ 16.536158] x3 : ffff00001b800104 [ 16.537881] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 16.545541] x2 : ffff800fcb451b18
[ 16.549110] x1 : 0000000000000040 x0 : 0000000000000000
[ 16.554414]
[ 16.555893] ---[ end trace 2c145cc81872d4a0 ]---
[ 16.560499] Call trace:
[ 16.562934] Exception stack(0xffff800fcb61b9e0 to 0xffff800fcb61bb10)
[ 16.569363] b9e0: ffff800fcb451c18 0001000000000000 ffff800fcb61bbb0 ffff0000087b7868
[ 16.577181] ba00: ffff000009f50000 0000000000020000 0000000000000008 00e800000000070f
[ 16.584999] ba20: 0000000000000000 ffff7fe000300200 ffff800fcb61bab0 ffff000008776250
[ 16.592817] ba40: ffff800fca8e80a0 ffff800fca8e8150 0000000000000004 0000000000000040
[ 16.600634] ba60: 0000000000016500 ffff800fcb451b18 ffff800fcb61bab0 ffff0000087d10e8
[ 16.608452] ba80: 0000000000000000 0000000000000040 ffff800fcb451b18 ffff00001b800104
[ 16.616270] baa0: 0000000000000000 ffff800fcb905780 ffff800fcb618000 0000000000000006
[ 16.624088] bac0: ffff000009f66500 0000000000000000 0140000000000040 0088000000000000
[ 16.631905] bae0: 0000000000000008 ffff000009f6ffff ffff0000092f7d85 0000000000000006
[ 16.639723] bb00: ffffffffffffff98 ffff7fe003f2e6a0
[ 16.644589] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 16.650411] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 16.656318] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 16.661793] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 16.667266] [<ffff0000080cc458>] work_for_cpu_fn+0x18/0x28
[ 16.672741] [<ffff0000080ce710>] process_one_work+0x118/0x378
[ 16.678475] [<ffff0000080cebd8>] worker_thread+0x268/0x4b0
[ 16.683949] [<ffff0000080d4c10>] kthread+0xd0/0xe8
[ 16.688728] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 16.692073] ata2: SATA link down (SStatus 0 SControl 300)
[ 16.699826] scsi host2: ahci
[ 16.702835] ata3: SATA max UDMA/133 abar m2097152 at 0x816000000000 port 0x816000000100
[ 16.710759] ahci 0001:00:0b.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 16.718852] ahci 0001:00:0b.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 16.728416] ahci 0001:00:0b.0: port 0 is not capable of FBS
[ 16.734084] ------------[ cut here ]------------
[ 16.738693] WARNING: CPU: 0 PID: 1601 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 16.747898]
[ 16.749379] CPU: 0 PID: 1601 Comm: kworker/0:1 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 16.758758] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 16.767444] Workqueue: events work_for_cpu_fn
[ 16.771792] task: ffff800fcb5e4e00 task.stack: ffff800fcb618000
[ 16.777699] PC is at ata_host_activate+0x138/0x150
[ 16.782479] LR is at ata_host_activate+0x5c/0x150
[ 16.787171] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 16.794553] sp : ffff800fcb61bbb0
[ 16.797856] x29: ffff800fcb61bbb0 x28: 0000000000000001
[ 16.803161] x27: ffff000009245408 x26: ffff000009245bf0
[ 16.808466] x25: ffff800fca8ea0a0 x24: ffff800fcb45f518
[ 16.813770] x23: 0000000000000080 x22: ffff000009245bf0
[ 16.819075] x21: 0000000000000000 x20: ffff0000087cddc8
[ 16.824380] x19: ffff800fcb45f418 x18: ffff0000892f7d77
[ 16.829685] x17: ffff7fe003f2e6a0 x16: ffffffffffffff98
[ 16.834989] x15: 0000000000000006 x14: ffff0000092f7d85
[ 16.840294] x13: ffff000009fbffff x12: 0000000000000008
[ 16.845599] x11: 0088000000000000 x10: 0140000000000040
[ 16.850903] x9 : 0000000000000000 x8 : ffff000009fb6500
[ 16.856208] x7 : 0000000000000006 x6 : ffff800fcb618000
[ 16.861512] x5 : ffff800fcb907500 x4 : 0000000000000000
[ 16.866817] x3 : ffff00001bc00104 x2 : ffff800fcb45f518
[ 16.872122] x1 : 0000000000000040 x0 : 0000000000000000
[ 16.877426]
[ 16.878906] ---[ end trace 2c145cc81872d4a1 ]---
[ 16.883511] Call trace:
[ 16.885946] Exception stack(0xffff800fcb61b9e0 to 0xffff800fcb61bb10)
[ 16.892376] b9e0: ffff800fcb45f418 0001000000000000 ffff800fcb61bbb0 ffff0000087b7868
[ 16.900194] ba00: ffff000009fa0000 0000000000020000 0000000000000008 00e800000000070f
[ 16.908011] ba20: 0000000000000000 ffff7fe000300280 ffff800fcb61bab0 ffff000008776250
[ 16.915829] ba40: ffff800fca8ea0a0 ffff800fca8ea150 0000000000000004 0000000000000040
[ 16.923647] ba60: 0000000000016500 ffff800fcb45f518 ffff800fcb61bab0 ffff0000087d10e8
[ 16.931465] ba80: 0000000000000000 0000000000000040 ffff800fcb45f518 ffff00001bc00104
[ 16.939283] baa0: 0000000000000000 ffff800fcb907500 ffff800fcb618000 0000000000000006
[ 16.947101] bac0: ffff000009fb6500 0000000000000000 0140000000000040 0088000000000000
[ 16.954918] bae0: 0000000000000008 ffff000009fbffff ffff0000092f7d85 0000000000000006
[ 16.962735] bb00: ffffffffffffff98 ffff7fe003f2e6a0
[ 16.967602] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 16.973424] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 16.979332] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 16.984805] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 16.990280] [<ffff0000080cc458>] work_for_cpu_fn+0x18/0x28
[ 16.995753] [<ffff0000080ce710>] process_one_work+0x118/0x378
[ 17.001488] [<ffff0000080cebd8>] worker_thread+0x268/0x4b0
[ 17.006963] [<ffff0000080d4c10>] kthread+0xd0/0xe8
[ 17.011742] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 17.017465] scsi host3: ahci
[ 17.020476] ata4: SATA max UDMA/133 abar m2097152 at 0x817000000000 port 0x817000000100
[ 17.024054] ata3: SATA link down (SStatus 0 SControl 300)
[ 17.033978] ahci 0005:00:08.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 17.042077] ahci 0005:00:08.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 17.051650] ahci 0005:00:08.0: port 0 is not capable of FBS
[ 17.057638] ------------[ cut here ]------------
[ 17.062263] WARNING: CPU: 49 PID: 1 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 17.071295]
[ 17.072781] CPU: 49 PID: 1 Comm: swapper/0 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 17.081814] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 17.090500] task: ffff800fc8340000 task.stack: ffff810000484000
[ 17.096409] PC is at ata_host_activate+0x138/0x150
[ 17.101190] LR is at ata_host_activate+0x5c/0x150
[ 17.105883] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 17.113266] sp : ffff810000487a90
[ 17.116570] x29: ffff810000487a90 x28: 0000000000000001
[ 17.121879] x27: ffff000009245408 x26: ffff000009245bf0
[ 17.127187] x25: ffff8100084810a0 x24: ffff81000a705018
[ 17.132495] x23: 0000000000000080 x22: ffff000009245bf0
[ 17.137803] x21: 0000000000000000 x20: ffff0000087cddc8
[ 17.143110] x19: ffff81000a705118 x18: ffff0000892f7d77
[ 17.148418] x17: ffff7fe003f2e620 x16: 0000000000000002
[ 17.153726] x15: 0000000000000006 x14: ffff0000092f7d85
[ 17.159033] x13: ffff00000a62ffff x12: 0000000000000008
[ 17.164341] x11: 0088000000000000 x10: 0140000000000040
[ 17.169649] x9 : 0000000000000000 x8 : ffff00000a626500
[ 17.174956] x7 : 0000000000000006 x6 : ffff810000484000
[ 17.180264] x5 : ffff81000a71f480 x4 : 0000000000000000
[ 17.185571] x3 : ffff00001e400104 x2 : ffff81000a705018
[ 17.190879] x1 : 0000000000000040 x0 : 0000000000000000
[ 17.196186]
[ 17.197667] ---[ end trace 2c145cc81872d4a2 ]---
[ 17.202274] Call trace:
[ 17.204712] Exception stack(0xffff8100004878c0 to 0xffff8100004879f0)
[ 17.211143] 78c0: ffff81000a705118 0001000000000000 ffff810000487a90 ffff0000087b7868
[ 17.218961] 78e0: ffff00000a610000 0000000000020000 0000000000000008 00e800000000070f
[ 17.226780] 7900: 0000000000000000 ffff7fe000300300 ffff810000487990 ffff000008776250
[ 17.234598] 7920: ffff8100084810a0 ffff810008481150 0000000000000004 0000000000000040
[ 17.242417] 7940: 0000000000016500 ffff81000a705018 ffff810000487990 ffff0000087d10e8
[ 17.250235] 7960: 0000000000000000 0000000000000040 ffff81000a705018 ffff00001e400104
[ 17.258054] 7980: 0000000000000000 ffff81000a71f480 ffff810000484000 0000000000000006
[ 17.265872] 79a0: ffff00000a626500 0000000000000000 0140000000000040 0088000000000000
[ 17.273691] 79c0: 0000000000000008 ffff00000a62ffff ffff0000092f7d85 0000000000000006
[ 17.281508] 79e0: 0000000000000002 ffff7fe003f2e620
[ 17.286376] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 17.292201] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 17.298111] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 17.303590] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 17.309065] [<ffff000008510330>] pci_device_probe+0x110/0x148
[ 17.314808] [<ffff00000876ac54>] driver_probe_device+0x204/0x2b0
[ 17.320803] [<ffff00000876adac>] __driver_attach+0xac/0xb0
[ 17.326279] [<ffff000008768d24>] bus_for_each_dev+0x5c/0xa0
[ 17.331840] [<ffff00000876aee8>] driver_attach+0x20/0x28
[ 17.337141] [<ffff0000087697d0>] bus_add_driver+0x1c8/0x230
[ 17.342703] [<ffff00000876b620>] driver_register+0x60/0xf8
[ 17.348178] [<ffff0000085103a0>] __pci_register_driver+0x38/0x40
[ 17.354183] [<ffff0000090b2fec>] ahci_pci_driver_init+0x20/0x28
[ 17.360100] [<ffff000009080c88>] do_one_initcall+0x84/0x114
[ 17.365662] [<ffff000009080ed0>] kernel_init_freeable+0x1b8/0x25c
[ 17.371754] [<ffff000008c20f30>] kernel_init+0x10/0x108
[ 17.376972] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 17.382862] scsi host4: ahci
[ 17.385910] ata5: SATA max UDMA/133 abar m2097152 at 0x914000000000 port 0x914000000100
[ 17.393763] ahci 0005:00:09.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 17.401864] ahci 0005:00:09.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 17.411425] ahci 0005:00:09.0: port 0 is not capable of FBS
[ 17.417096] ------------[ cut here ]------------
[ 17.421707] WARNING: CPU: 49 PID: 1 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 17.430739]
[ 17.432221] CPU: 49 PID: 1 Comm: swapper/0 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 17.441253] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 17.449939] task: ffff800fc8340000 task.stack: ffff810000484000
[ 17.455847] PC is at ata_host_activate+0x138/0x150
[ 17.460627] LR is at ata_host_activate+0x5c/0x150
[ 17.465320] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 17.472703] sp : ffff810000487a90
[ 17.476007] x29: ffff810000487a90 x28: 0000000000000001
[ 17.481314] x27: ffff000009245408 x26: ffff000009245bf0
[ 17.486621] x25: ffff8100084830a0 x24: ffff81000a70fa18
[ 17.491929] x23: 0000000000000080 x22: ffff000009245bf0
[ 17.497236] x21: 0000000000000000 x20: ffff0000087cddc8
[ 17.502544] x19: ffff81000a70f918 x18: ffff0000892f7d77
[ 17.507851] x17: ffff7fe040029ea0 [ 17.509883] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 17.517234] x16: ffffffffffffff98
[ 17.520804] x15: 0000000000000006 x14: ffff0000092f7d85
[ 17.526112] x13: ffff00000a67ffff x12: 0000000000000008
[ 17.531420] x11: 0088000000000000 x10: 0140000000000040
[ 17.536727] x9 : 0000000000000000 x8 : ffff00000a676500
[ 17.542035] x7 : 0000000000000006 x6 : ffff810000484000
[ 17.547342] x5 : ffff81000a71d680 x4 : 0000000000000000
[ 17.552650] x3 : ffff00001e800104 x2 : ffff81000a70fa18
[ 17.557957] x1 : 0000000000000040 x0 : 0000000000000000
[ 17.563264]
[ 17.564745] ---[ end trace 2c145cc81872d4a3 ]---
[ 17.569351] Call trace:
[ 17.571788] Exception stack(0xffff8100004878c0 to 0xffff8100004879f0)
[ 17.578218] 78c0: ffff81000a70f918 0001000000000000 ffff810000487a90 ffff0000087b7868
[ 17.586036] 78e0: ffff00000a660000 0000000000020000 0000000000000008 00e800000000070f
[ 17.593855] 7900: 0000000000000000 ffff7fe000300380 ffff810000487990 ffff000008776250
[ 17.601673] 7920: ffff8100084830a0 ffff810008483150 0000000000000004 0000000000000040
[ 17.609492] 7940: 0000000000016500 ffff81000a70fa18 ffff810000487990 ffff0000087d10e8
[ 17.617310] 7960: 0000000000000000 0000000000000040 ffff81000a70fa18 ffff00001e800104
[ 17.625129] 7980: 0000000000000000 ffff81000a71d680 ffff810000484000 0000000000000006
[ 17.632947] 79a0: ffff00000a676500 0000000000000000 0140000000000040 0088000000000000
[ 17.640765] 79c0: 0000000000000008 ffff00000a67ffff ffff0000092f7d85 0000000000000006
[ 17.648583] 79e0: ffffffffffffff98 ffff7fe040029ea0
[ 17.653451] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 17.659273] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 17.665182] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 17.670657] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 17.676131] [<ffff000008510330>] pci_device_probe+0x110/0x148
[ 17.681867] [<ffff00000876ac54>] driver_probe_device+0x204/0x2b0
[ 17.687863] [<ffff00000876adac>] __driver_attach+0xac/0xb0
[ 17.693337] [<ffff000008768d24>] bus_for_each_dev+0x5c/0xa0
[ 17.698899] [<ffff00000876aee8>] driver_attach+0x20/0x28
[ 17.704200] [<ffff0000087697d0>] bus_add_driver+0x1c8/0x230
[ 17.708031] ata5: SATA link down (SStatus 0 SControl 300)
[ 17.715147] [<ffff00000876b620>] driver_register+0x60/0xf8
[ 17.720621] [<ffff0000085103a0>] __pci_register_driver+0x38/0x40
[ 17.726617] [<ffff0000090b2fec>] ahci_pci_driver_init+0x20/0x28
[ 17.732527] [<ffff000009080c88>] do_one_initcall+0x84/0x114
[ 17.738089] [<ffff000009080ed0>] kernel_init_freeable+0x1b8/0x25c
[ 17.744172] [<ffff000008c20f30>] kernel_init+0x10/0x108
[ 17.749386] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 17.755136] scsi host5: ahci
[ 17.758152] ata6: SATA max UDMA/133 abar m2097152 at 0x915000000000 port 0x915000000100
[ 17.766004] ahci 0005:00:0a.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 17.774095] ahci 0005:00:0a.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 17.783660] ahci 0005:00:0a.0: port 0 is not capable of FBS
[ 17.789335] ------------[ cut here ]------------
[ 17.793946] WARNING: CPU: 49 PID: 1 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 17.802977]
[ 17.804460] CPU: 49 PID: 1 Comm: swapper/0 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 17.813491] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 17.822177] task: ffff800fc8340000 task.stack: ffff810000484000
[ 17.828085] PC is at ata_host_activate+0x138/0x150
[ 17.832866] LR is at ata_host_activate+0x5c/0x150
[ 17.837559] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 17.844942] sp : ffff810000487a90
[ 17.848246] x29: ffff810000487a90 x28: 0000000000000001
[ 17.853553] x27: ffff000009245408 x26: ffff000009245bf0
[ 17.858861] x25: ffff8100084850a0 x24: ffff81000a705e18
[ 17.864169] x23: 0000000000000080 x22: ffff000009245bf0
[ 17.869477] x21: 0000000000000000 x20: ffff0000087cddc8
[ 17.874784] x19: ffff81000a705f18 x18: ffff0000892f7d77
[ 17.880092] x17: ffff7fe040029ea0 x16: ffffffffffffff98
[ 17.885399] x15: 0000000000000006 x14: ffff0000092f7d85
[ 17.890707] x13: ffff00000a6dffff x12: 0000000000000008
[ 17.896014] x11: 0088000000000000 x10: 0140000000000040
[ 17.901321] x9 : 0000000000000000 x8 : ffff00000a6d6500
[ 17.906628] x7 : 0000000000000006 x6 : ffff810000484000
[ 17.911936] x5 : ffff81000a71b880 x4 : 0000000000000000
[ 17.917244] x3 : ffff00001ec00104 x2 : ffff81000a705e18
[ 17.922551] x1 : 0000000000000040 x0 : 0000000000000000
[ 17.927858]
[ 17.929339] ---[ end trace 2c145cc81872d4a4 ]---
[ 17.933945] Call trace:
[ 17.936381] Exception stack(0xffff8100004878c0 to 0xffff8100004879f0)
[ 17.942811] 78c0: ffff81000a705f18 0001000000000000 ffff810000487a90 ffff0000087b7868
[ 17.950630] 78e0: ffff00000a6c0000 0000000000020000 0000000000000008 00e800000000070f
[ 17.958449] 7900: 0000000000000000 ffff7fe000300400 ffff810000487990 ffff000008776250
[ 17.966267] 7920: ffff8100084850a0 ffff810008485150 0000000000000004 0000000000000040
[ 17.974085] 7940: 0000000000016500 ffff81000a705e18 ffff810000487990 ffff0000087d10e8
[ 17.981904] 7960: 0000000000000000 0000000000000040 ffff81000a705e18 ffff00001ec00104
[ 17.989722] 7980: 0000000000000000 ffff81000a71b880 ffff810000484000 0000000000000006
[ 17.997541] 79a0: ffff00000a6d6500 0000000000000000 0140000000000040 0088000000000000
[ 18.005359] 79c0: 0000000000000008 ffff00000a6dffff ffff0000092f7d85 0000000000000006
[ 18.013177] 79e0: ffffffffffffff98 ffff7fe040029ea0
[ 18.018044] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 18.023867] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 18.029775] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 18.035250] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 18.040725] [<ffff000008510330>] pci_device_probe+0x110/0x148
[ 18.046460] [<ffff00000876ac54>] driver_probe_device+0x204/0x2b0
[ 18.052456] [<ffff00000876adac>] __driver_attach+0xac/0xb0
[ 18.057931] [<ffff000008768d24>] bus_for_each_dev+0x5c/0xa0
[ 18.063492] [<ffff00000876aee8>] driver_attach+0x20/0x28
[ 18.068793] [<ffff0000087697d0>] bus_add_driver+0x1c8/0x230
[ 18.074355] [<ffff00000876b620>] driver_register+0x60/0xf8
[ 18.079829] [<ffff0000085103a0>] __pci_register_driver+0x38/0x40
[ 18.080051] ata6: SATA link down (SStatus 0 SControl 300)
[ 18.091210] [<ffff0000090b2fec>] ahci_pci_driver_init+0x20/0x28
[ 18.097120] [<ffff000009080c88>] do_one_initcall+0x84/0x114
[ 18.102682] [<ffff000009080ed0>] kernel_init_freeable+0x1b8/0x25c
[ 18.108765] [<ffff000008c20f30>] kernel_init+0x10/0x108
[ 18.113979] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 18.119725] scsi host6: ahci
[ 18.122747] ata7: SATA max UDMA/133 abar m2097152 at 0x916000000000 port 0x916000000100
[ 18.130601] ahci 0005:00:0b.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 18.138693] ahci 0005:00:0b.0: flags: 64bit ncq sntf ilck pm led clo only pmp fbs pio slum part ccc apst
[ 18.148258] ahci 0005:00:0b.0: port 0 is not capable of FBS
[ 18.153931] ------------[ cut here ]------------
[ 18.158542] WARNING: CPU: 49 PID: 1 at drivers/ata/libata-core.c:6426 ata_host_activate+0x138/0x150
[ 18.167574]
[ 18.169057] CPU: 49 PID: 1 Comm: swapper/0 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 18.178089] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 18.186774] task: ffff800fc8340000 task.stack: ffff810000484000
[ 18.192683] PC is at ata_host_activate+0x138/0x150
[ 18.197463] LR is at ata_host_activate+0x5c/0x150
[ 18.202156] pc : [<ffff0000087b7868>] lr : [<ffff0000087b778c>] pstate: 60000045
[ 18.209539] sp : ffff810000487a90
[ 18.212843] x29: ffff810000487a90 x28: 0000000000000001
[ 18.218150] x27: ffff000009245408 x26: ffff000009245bf0
[ 18.223458] x25: ffff8100084870a0 x24: ffff81000a70ec18
[ 18.228765] x23: 0000000000000080 x22: ffff000009245bf0
[ 18.234073] x21: 0000000000000000 x20: ffff0000087cddc8
[ 18.239380] x19: ffff81000a70eb18 x18: ffff0000892f7d77
[ 18.244688] x17: ffff7fe040029ee0 x16: ffffffffffffff98
[ 18.249995] x15: 0000000000000006 x14: ffff0000092f7d85
[ 18.255303] x13: ffff00000a73ffff x12: 0000000000000008
[ 18.260611] x11: 0088000000000000 x10: 0140000000000040
[ 18.265918] x9 : 0000000000000000 x8 : ffff00000a736500
[ 18.271225] x7 : 0000000000000006 x6 : ffff810000484000
[ 18.276533] x5 : ffff81000a719a80 x4 : 0000000000000000
[ 18.281840] x3 : ffff00001f000104 x2 : ffff81000a70ec18
[ 18.287148] x1 : 0000000000000040 x0 : 0000000000000000
[ 18.292455]
[ 18.293936] ---[ end trace 2c145cc81872d4a5 ]---
[ 18.298542] Call trace:
[ 18.300979] Exception stack(0xffff8100004878c0 to 0xffff8100004879f0)
[ 18.307409] 78c0: ffff81000a70eb18 0001000000000000 ffff810000487a90 ffff0000087b7868
[ 18.315228] 78e0: ffff00000a720000 0000000000020000 0000000000000008 00e800000000070f
[ 18.323046] 7900: 0000000000000000 ffff7fe000300480 ffff810000487990 ffff000008776250
[ 18.330865] 7920: ffff8100084870a0 ffff810008487150 0000000000000004 0000000000000040
[ 18.338683] 7940: 0000000000016500 ffff81000a70ec18 ffff810000487990 ffff0000087d10e8
[ 18.346502] 7960: 0000000000000000 0000000000000040 ffff81000a70ec18 ffff00001f000104
[ 18.354320] 7980: 0000000000000000 ffff81000a719a80 ffff810000484000 0000000000000006
[ 18.362139] 79a0: ffff00000a736500 0000000000000000 0140000000000040 0088000000000000
[ 18.369957] 79c0: 0000000000000008 ffff00000a73ffff ffff0000092f7d85 0000000000000006
[ 18.377775] 79e0: ffffffffffffff98 ffff7fe040029ee0
[ 18.382643] [<ffff0000087b7868>] ata_host_activate+0x138/0x150
[ 18.388465] [<ffff0000087d2950>] ahci_host_activate+0x138/0x170
[ 18.394373] [<ffff0000087ced84>] ahci_init_one+0x8d4/0xd50
[ 18.399848] [<ffff00000850f394>] local_pci_probe+0x3c/0xb8
[ 18.405323] [<ffff000008510330>] pci_device_probe+0x110/0x148
[ 18.411059] [<ffff00000876ac54>] driver_probe_device+0x204/0x2b0
[ 18.417055] [<ffff00000876adac>] __driver_attach+0xac/0xb0
[ 18.422529] [<ffff000008768d24>] bus_for_each_dev+0x5c/0xa0
[ 18.428091] [<ffff00000876aee8>] driver_attach+0x20/0x28
[ 18.433392] [<ffff0000087697d0>] bus_add_driver+0x1c8/0x230
[ 18.438954] [<ffff00000876b620>] driver_register+0x60/0xf8
[ 18.444010] ata7: SATA link down (SStatus 0 SControl 300)
[ 18.449813] [<ffff0000085103a0>] __pci_register_driver+0x38/0x40
[ 18.455809] [<ffff0000090b2fec>] ahci_pci_driver_init+0x20/0x28
[ 18.461719] [<ffff000009080c88>] do_one_initcall+0x84/0x114
[ 18.467281] [<ffff000009080ed0>] kernel_init_freeable+0x1b8/0x25c
[ 18.473364] [<ffff000008c20f30>] kernel_init+0x10/0x108
[ 18.478578] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 18.484409] scsi host7: ahci
[ 18.487425] ata8: SATA max UDMA/133 abar m2097152 at 0x917000000000 port 0x917000000100
...
[ 18.808074] ata8: SATA link down (SStatus 0 SControl 300)
...
[ 21.765921] ata1.00: qc timeout (cmd 0xec)
[ 21.770031] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 22.249869] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 22.533896] ata4.00: qc timeout (cmd 0xec)
[ 22.537996] ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 23.017874] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 32.261874] ata1.00: qc timeout (cmd 0xec)
[ 32.265972] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 32.272059] ata1: limiting SATA link speed to 3.0 Gbps
[ 32.753873] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 33.029878] ata4.00: qc timeout (cmd 0xec)
[ 33.033978] ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 33.040066] ata4: limiting SATA link speed to 3.0 Gbps
[ 33.521884] ata4: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 63.493874] ata1.00: qc timeout (cmd 0xec)
[ 63.497973] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 63.977867] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 65.541890] ata4.00: qc timeout (cmd 0xec)
[ 65.545987] ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 66.025873] ata4: SATA link up 3.0 Gbps (SStatus 123 SControl 320)
[ 66.032337] VFS: Cannot open root device "sda2" or unknown-block(0,0): error -6
[ 66.039682] Please append a correct "root=" boot option; here are the available partitions:
[ 66.048047] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[ 66.056304] CPU: 55 PID: 1 Comm: swapper/0 Tainted: G W 4.8.1-00004-gf0dadca853a2 #171
[ 66.065337] Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
[ 66.074023] Call trace:
[ 66.076474] [<ffff0000080883c8>] dump_backtrace+0x0/0x1a0
[ 66.081863] [<ffff00000808857c>] show_stack+0x14/0x20
[ 66.086908] [<ffff00000849adf4>] dump_stack+0x94/0xb8
[ 66.091956] [<ffff00000815df94>] panic+0x10c/0x26c
[ 66.096744] [<ffff000009081318>] mount_block_root+0x18c/0x264
[ 66.102480] [<ffff00000908150c>] mount_root+0x11c/0x134
[ 66.107695] [<ffff000009081660>] prepare_namespace+0x13c/0x184
[ 66.113517] [<ffff000009080f50>] kernel_init_freeable+0x238/0x25c
[ 66.119607] [<ffff000008c20f30>] kernel_init+0x10/0x108
[ 66.124822] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 66.130125] SMP: stopping secondary CPUs
^ permalink raw reply
* [PATCH 6/7] ARM: dts: am335x: Add the power button interrupt
From: Milo Kim @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.21531-1-woogyom.kim@gmail.com>
This enables the power button driver gets corresponding IRQ number by
using platform_get_irq().
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index cec9d91..0c0a90c 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -324,6 +324,11 @@
status = "okay";
};
+ pwrbutton {
+ interrupts = <TPS65217_IRQ_PB>;
+ status = "okay";
+ };
+
regulators {
dcdc1_reg: regulator at 0 {
regulator-name = "vdds_dpr";
--
2.9.3
^ permalink raw reply related
* [PATCH 5/7] ARM: dts: am335x: Add the charger interrupt
From: Milo Kim @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.21531-1-woogyom.kim@gmail.com>
This enables the charger driver gets corresponding IRQ number by using
platform_get_irq_byname() helper.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 25303d9..cec9d91 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -6,6 +6,8 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/mfd/tps65217.h>
+
/ {
cpus {
cpu at 0 {
@@ -316,6 +318,12 @@
ti,pmic-shutdown-controller;
+ charger {
+ interrupts = <TPS65217_IRQ_AC>, <TPS65217_IRQ_USB>;
+ interrupts-names = "AC", "USB";
+ status = "okay";
+ };
+
regulators {
dcdc1_reg: regulator at 0 {
regulator-name = "vdds_dpr";
--
2.9.3
^ permalink raw reply related
* [PATCH 4/7] ARM: dts: am335x: Support the PMIC interrupt
From: Milo Kim @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.21531-1-woogyom.kim@gmail.com>
AM335x bone based boards have the PMIC interrupt named NMI which is
connected to TPS65217 device. AM335x main interrupt controller provides it
and the number is 7.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 007b5e5..25303d9 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -310,6 +310,10 @@
* by the hardware problems. (Tip: double-check by performing a current
* measurement after shutdown: it should be less than 1 mA.)
*/
+
+ interrupts = <7>; /* NMI */
+ interrupt-parent = <&intc>;
+
ti,pmic-shutdown-controller;
regulators {
--
2.9.3
^ permalink raw reply related
* [PATCH 3/7] ARM: dts: tps65217: Add the power button device
From: Milo Kim @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.21531-1-woogyom.kim@gmail.com>
Support the power button driver and disable it by default.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/tps65217.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
index 8f77d0d..02de56b 100644
--- a/arch/arm/boot/dts/tps65217.dtsi
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -21,6 +21,11 @@
status = "disabled";
};
+ pwrbutton {
+ compatible = "ti,tps65217-pwrbutton";
+ status = "disabled";
+ };
+
regulators {
#address-cells = <1>;
#size-cells = <0>;
--
2.9.3
^ permalink raw reply related
* [PATCH 2/7] ARM: dts: tps65217: Add the charger device
From: Milo Kim @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.21531-1-woogyom.kim@gmail.com>
Support the charger driver and disable it by default.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/tps65217.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
index 27935f8..8f77d0d 100644
--- a/arch/arm/boot/dts/tps65217.dtsi
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -16,6 +16,11 @@
interrupt-controller;
#interrupt-cells = <1>;
+ charger {
+ compatible = "ti,tps65217-charger";
+ status = "disabled";
+ };
+
regulators {
#address-cells = <1>;
#size-cells = <0>;
--
2.9.3
^ permalink raw reply related
* [PATCH 1/7] ARM: dts: tps65217: Specify the interrupt controller
From: Milo Kim @ 2016-10-21 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.21531-1-woogyom.kim@gmail.com>
TPS65217 MFD driver supports the IRQ domain to handle the charger input
interrupts and push button status event. The interrupt controller enables
corresponding IRQ handling in the charger[*] and power button driver[**].
[*] drivers/power/supply/tps65217_charger.c
[**] drivers/input/misc/tps65218-pwrbutton.c
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/tps65217.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
index a632724..27935f8 100644
--- a/arch/arm/boot/dts/tps65217.dtsi
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -13,6 +13,8 @@
&tps {
compatible = "ti,tps65217";
+ interrupt-controller;
+ #interrupt-cells = <1>;
regulators {
#address-cells = <1>;
--
2.9.3
^ permalink raw reply related
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