* [PATCH V4 2/3] Revert "ACPI,PCI,IRQ: remove SCI penalize function"
From: Bjorn Helgaas @ 2016-10-22 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2a824792-486a-6251-4931-c5cc6fd67978@codeaurora.org>
On Fri, Oct 21, 2016 at 09:13:06AM -0700, Sinan Kaya wrote:
> On 10/21/2016 7:45 AM, Bjorn Helgaas wrote:
> > [1] http://marc.info/?l=linux-acpi&m=145580159209240&w=2)
> >
> >> > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> > Wait a minute, I still have a question here: what about other ACPI
> > arches (ia64, arm64)? Don't they need to call acpi_penalize_sci_irq()
> > somewhere?
> >
>
> ACPI ARM64 architecture implements reduced ACPI profile which doesn't
> have GED object. Instead, ARM64 architecture uses onchip peripherals
> for similar functionality. If there is a need to signal interrupts,
> this is done by ACPI Notify in ASL or if absolutely needed using
> ACPI Generic Event Device (GED).
OK. I guess ia64 never did call acpi_penalize_sci_irq(), so while it
could be added someday to unify things, we don't need to add it now.
Same for arm64.
So I'd like it if you updated the changelog, but I'm OK with the
patch:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
^ permalink raw reply
* [PATCH 1/1] arm: dts: imx6ul: 14x14-evk: add the optee node
From: Jason Liu @ 2016-10-22 14:57 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the optee node for the i.MX6UL 14x14 evk board
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
---
arch/arm/boot/dts/imx6ul-14x14-evk.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index e281d50..e68dc19 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -30,6 +30,13 @@
status = "okay";
};
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
--
1.9.1
^ permalink raw reply related
* [PATCH -next] phy: meson8b-usb2: fix missing clk_disable_unprepare() on error
From: Wei Yongjun @ 2016-10-22 14:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Wei Yongjun <weiyongjun1@huawei.com>
Fix the missing clk_disable_unprepare() before return from
phy_meson8b_usb2_power_on() in the error handling case.
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/phy/phy-meson8b-usb2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/phy-meson8b-usb2.c b/drivers/phy/phy-meson8b-usb2.c
index 73bf632..dca3947 100644
--- a/drivers/phy/phy-meson8b-usb2.c
+++ b/drivers/phy/phy-meson8b-usb2.c
@@ -158,6 +158,7 @@ static int phy_meson8b_usb2_power_on(struct phy *phy)
ret = clk_prepare_enable(priv->clk_usb);
if (ret) {
dev_err(&phy->dev, "Failed to enable USB DDR clock\n");
+ clk_disable_unprepare(priv->clk_usb_general);
return ret;
}
@@ -190,6 +191,8 @@ static int phy_meson8b_usb2_power_on(struct phy *phy)
if (phy_meson8b_usb2_read(priv, REG_ADP_BC) &
REG_ADP_BC_ACA_PIN_FLOAT) {
dev_warn(&phy->dev, "USB ID detect failed!\n");
+ clk_disable_unprepare(priv->clk_usb);
+ clk_disable_unprepare(priv->clk_usb_general);
return -EINVAL;
}
}
^ permalink raw reply related
* [GIT PULL] ARM: uniphier: fixes for v4.9
From: Masahiro Yamada @ 2016-10-22 14:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Olof,
Here are some fixes for v4.9.
It is touching a reset controller driver, but Philipp gave me Acked-by
for including it in my pull-request.
Here is a question; do you have a chance to send a pull-request for fixes
to Linus before -rc4? In my understanding, pull requests for the next merge
window are generally required to be based on a tag prior to -rc4.
In the previous development cycle, I remember the fixes pull-request was
sent around v4.8-rc7. In this case, it would be a problem if a fixup commit
and a new-development commit have a conflict with each other.
If the first round of fixes pull-request is sent before -rc4, commits for
the next merge window can be queued up based on -rc4 without any conflicts.
Thanks,
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
tags/uniphier-fixes-v4.9
for you to fetch changes up to 8e68c65d111a57a4cbe41dc886bb2a1e671e0b6e:
arm64: dts: uniphier: change MIO node to SD control node (2016-10-22
21:59:21 +0900)
----------------------------------------------------------------
UniPhier ARM SoC fixes for v4.9
- Add "select ARCH_HAS_RESET_CONTROLLER" in Kconfig
- Rename wrongly-named mioctrl to sdctrl
----------------------------------------------------------------
Masahiro Yamada (5):
ARM: uniphier: select ARCH_HAS_RESET_CONTROLLER
arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER
reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs
ARM: dts: uniphier: change MIO node to SD control node
arm64: dts: uniphier: change MIO node to SD control node
.../devicetree/bindings/reset/uniphier-reset.txt | 62 +++++++++++-----------
arch/arm/boot/dts/uniphier-pro5.dtsi | 4 +-
arch/arm/boot/dts/uniphier-pxs2.dtsi | 4 +-
arch/arm/mach-uniphier/Kconfig | 1 +
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 12 ++---
drivers/reset/reset-uniphier.c | 16 +++---
7 files changed, 51 insertions(+), 49 deletions(-)
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH] ahci: use pci_alloc_irq_vectors
From: Christoph Hellwig @ 2016-10-22 14:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021140106.GU25086@rric.localdomain>
Hi Robert,
is this a controller that's using MSI-X?
If so can you try the patch below?
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index ba5f11c..5fe852d 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1617,7 +1617,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
/* legacy intx interrupts */
pci_intx(pdev, 1);
}
- hpriv->irq = pdev->irq;
+ hpriv->irq = pci_irq_vector(pdev, 0);
if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
host->flags |= ATA_HOST_PARALLEL_SCAN;
^ permalink raw reply related
* [PATCH] nvmem: sunxi-sid: SID content is not a valid source of randomness
From: Corentin Labbe @ 2016-10-22 13:53 UTC (permalink / raw)
To: linux-arm-kernel
Since SID's content is constant over reboot, it must not be used
as source of randomness.
This patch remove the use of SID content as source of randomness.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
drivers/nvmem/sunxi_sid.c | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index 1567ccc..c82d5d1 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -21,8 +21,6 @@
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/random.h>
static struct nvmem_config econfig = {
.name = "sunxi-sid",
@@ -70,8 +68,6 @@ static int sunxi_sid_probe(struct platform_device *pdev)
struct resource *res;
struct nvmem_device *nvmem;
struct sunxi_sid *sid;
- int ret, i, size;
- char *randomness;
sid = devm_kzalloc(dev, sizeof(*sid), GFP_KERNEL);
if (!sid)
@@ -82,7 +78,6 @@ static int sunxi_sid_probe(struct platform_device *pdev)
if (IS_ERR(sid->base))
return PTR_ERR(sid->base);
- size = resource_size(res) - 1;
econfig.size = resource_size(res);
econfig.dev = dev;
econfig.reg_read = sunxi_sid_read;
@@ -91,25 +86,9 @@ static int sunxi_sid_probe(struct platform_device *pdev)
if (IS_ERR(nvmem))
return PTR_ERR(nvmem);
- randomness = kzalloc(sizeof(u8) * (size), GFP_KERNEL);
- if (!randomness) {
- ret = -EINVAL;
- goto err_unreg_nvmem;
- }
-
- for (i = 0; i < size; i++)
- randomness[i] = sunxi_sid_read_byte(sid, i);
-
- add_device_randomness(randomness, size);
- kfree(randomness);
-
platform_set_drvdata(pdev, nvmem);
return 0;
-
-err_unreg_nvmem:
- nvmem_unregister(nvmem);
- return ret;
}
static int sunxi_sid_remove(struct platform_device *pdev)
--
2.7.3
^ permalink raw reply related
* [PATCH v5 0/7] ARM: ASoC: drm: sun8i: Add DE2 HDMI audio and video
From: Jean-Francois Moine @ 2016-10-22 13:28 UTC (permalink / raw)
To: linux-arm-kernel
This patchset series adds HDMI audio and video support to the Allwinner
sun8i SoCs which include the display engine 2 (DE2).
A first submission in January for video on the H3 could not enter into
the mainline kernel due to the lack of license headers in Allwinner's
sources.
Recently, an announce about Tina OS for the R series
https://www.youtube.com/watch?v=h7KD-6HblAU
was followed by the upload of a new linux-3.4 source tree
https://github.com/tinalinux/linux-3.4
with files containing GPL headers.
Well, I don't know if these sources are really from Allwinner, but
anyway, this is the opportunity to propose a new version of my DRM
HDMI driver.
v5:
- add overlay plane
- add audio support
- add support for the A83T
- add back the HDMI driver
- many bug fixes
v4:
- drivers/clk/sunxi/Makefile was missing (Emil Velikov)
v3:
- add the hardware cursor
- simplify and fix the DE2 init sequences
- generation for all SUNXI SoCs (Andre Przywara)
v2:
- remove the HDMI driver
- remarks from Chen-Yu Tsai and Russell King
- DT documentation added
Jean-Francois Moine (7):
drm: sunxi: Add a basic DRM driver for Allwinner DE2
ASoC: sunxi: Add a simple HDMI CODEC
drm: sunxi: add DE2 HDMI support
ASoC: sunxi: Add sun8i I2S driver
ARM: dts: sun8i-h3: add HDMI audio and video nodes
ARM: dts: sun8i-h3: Add HDMI audio and video to the Banana Pi M2+
ARM: dts: sun8i-h3: Add HDMI audio and video to the Orange PI 2
.../devicetree/bindings/display/sunxi/hdmi.txt | 52 ++
.../bindings/display/sunxi/sunxi-de2.txt | 83 ++
.../devicetree/bindings/sound/sun4i-i2s.txt | 38 +-
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 17 +
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 17 +
arch/arm/boot/dts/sun8i-h3.dtsi | 67 ++
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/sunxi/Kconfig | 29 +
drivers/gpu/drm/sunxi/Makefile | 9 +
drivers/gpu/drm/sunxi/de2_crtc.c | 475 +++++++++++
drivers/gpu/drm/sunxi/de2_crtc.h | 63 ++
drivers/gpu/drm/sunxi/de2_de.c | 591 +++++++++++++
drivers/gpu/drm/sunxi/de2_drm.h | 47 ++
drivers/gpu/drm/sunxi/de2_drv.c | 378 +++++++++
drivers/gpu/drm/sunxi/de2_hdmi.c | 396 +++++++++
drivers/gpu/drm/sunxi/de2_hdmi.h | 40 +
drivers/gpu/drm/sunxi/de2_hdmi_io.c | 927 +++++++++++++++++++++
drivers/gpu/drm/sunxi/de2_hdmi_io.h | 25 +
drivers/gpu/drm/sunxi/de2_plane.c | 119 +++
include/sound/sunxi_hdmi.h | 23 +
sound/soc/codecs/Kconfig | 9 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/sunxi-hdmi.c | 106 +++
sound/soc/sunxi/Kconfig | 8 +
sound/soc/sunxi/Makefile | 3 +
sound/soc/sunxi/sun8i-i2s.c | 700 ++++++++++++++++
27 files changed, 4222 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
create mode 100644 drivers/gpu/drm/sunxi/Kconfig
create mode 100644 drivers/gpu/drm/sunxi/Makefile
create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c
create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h
create mode 100644 drivers/gpu/drm/sunxi/de2_de.c
create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h
create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.c
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.h
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_io.c
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_io.h
create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c
create mode 100644 include/sound/sunxi_hdmi.h
create mode 100644 sound/soc/codecs/sunxi-hdmi.c
create mode 100644 sound/soc/sunxi/sun8i-i2s.c
--
2.10.1
^ permalink raw reply
* [PATCH 2/2] ARM64: dts: rockchip: use pin constants to describe gpios
From: Andy Yan @ 2016-10-22 12:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477140706-6886-1-git-send-email-andy.yan@rock-chips.com>
Use macros to describe gpios will make the dts easier to
read and write.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 10 +++++-----
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 8 ++++----
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 14 +++++++-------
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 4 ++--
arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 16 ++++++++--------
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 6 +++---
6 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
index fff8b19..4772917 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
@@ -90,7 +90,7 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
- enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
@@ -101,7 +101,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
keys: gpio-keys {
@@ -111,7 +111,7 @@
power {
wakeup-source;
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
@@ -121,7 +121,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -166,7 +166,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rmii";
clock_in_out = "output";
- snps,reset-gpio = <&gpio3 12 0>;
+ snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
index e5eeca2..e5b92d2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
@@ -66,7 +66,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -77,7 +77,7 @@
pinctrl-0 = <&pwr_key>;
power {
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
wakeup-source;
@@ -88,13 +88,13 @@
compatible = "gpio-leds";
blue {
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "geekbox:blue:led";
default-state = "on";
};
red {
- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
label = "geekbox:red:led";
default-state = "off";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
index ea0a8ec..2e431f13 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
@@ -61,7 +61,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
ext_gmac: external-gmac-clock {
@@ -78,7 +78,7 @@
power {
wakeup-source;
- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
@@ -88,7 +88,7 @@
compatible = "gpio-leds";
red {
- gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
label = "orion:red:led";
pinctrl-names = "default";
pinctrl-0 = <&led_ctl>;
@@ -96,7 +96,7 @@
};
blue {
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
label = "orion:blue:led";
pinctrl-names = "default";
pinctrl-0 = <&stby_pwren>;
@@ -117,7 +117,7 @@
/* supplies both host and otg */
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -149,7 +149,7 @@
vcc_sd: vcc-sd-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sd";
- gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
@@ -217,7 +217,7 @@
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 12 0>;
+ snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
index 85f7a24..62919c4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
@@ -63,7 +63,7 @@
pinctrl-0 = <&pwr_key>;
power {
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
wakeup-source;
@@ -248,7 +248,7 @@
reg = <0x40>;
interrupt-parent = <&gpio3>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
- power-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
silead,max-fingers = <5>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index eed1ef6..7134181 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -61,7 +61,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
keys: gpio-keys {
@@ -71,7 +71,7 @@
power {
wakeup-source;
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
@@ -81,7 +81,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
label = "r88:green:led";
pinctrl-names = "default";
pinctrl-0 = <&led_ctl>;
@@ -90,7 +90,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -104,10 +104,10 @@
reset-gpios =
/* BT_RST_N */
- <&gpio3 5 GPIO_ACTIVE_LOW>,
+ <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>,
/* WL_REG_ON */
- <&gpio3 4 GPIO_ACTIVE_LOW>;
+ <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
};
vcc_18: vcc18-regulator {
@@ -124,7 +124,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -199,7 +199,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rmii";
clock_in_out = "output";
- snps,reset-gpio = <&gpio3 12 0>;
+ snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 8e82497..f00e0d5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -88,7 +88,7 @@
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
@@ -123,7 +123,7 @@
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
@@ -156,7 +156,7 @@
};
&pcie0 {
- ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: rockchip: use pin constants to describe gpios
From: Andy Yan @ 2016-10-22 12:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477140706-6886-1-git-send-email-andy.yan@rock-chips.com>
Use macros to describe gpios will make the dts easier to
read and write.
All the modifications done with sed:
sed -i -e 's/ 0 GPIO_ACTIVE_/ RK_PA0 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
sed -i -e 's/ 1 GPIO_ACTIVE_/ RK_PA1 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
sed -i -e 's/ 2 GPIO_ACTIVE_/ RK_PA2 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
.......
.......
sed -i -e 's/ 30 GPIO_ACTIVE_/ RK_PD6 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
sed -i -e 's/ 31 GPIO_ACTIVE_/ RK_PD7 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
Tested with:
for i in dts-old/*dtb; do scripts/dtc/dtx_diff $i dts-new/$(basename $i); done
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/boot/dts/rk3036-evb.dts | 2 +-
arch/arm/boot/dts/rk3036-kylin.dts | 10 +++++-----
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 6 +++---
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-mk808.dts | 10 +++++-----
arch/arm/boot/dts/rk3066a-rayeager.dts | 12 ++++++------
arch/arm/boot/dts/rk3188-px3-evb.dts | 4 ++--
arch/arm/boot/dts/rk3188-radxarock.dts | 16 +++++++--------
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3288-evb-act8846.dts | 4 ++--
arch/arm/boot/dts/rk3288-evb.dtsi | 14 ++++++-------
arch/arm/boot/dts/rk3288-fennec.dts | 4 ++--
arch/arm/boot/dts/rk3288-firefly-beta.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload.dts | 24 +++++++++++------------
arch/arm/boot/dts/rk3288-firefly.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly.dtsi | 16 +++++++--------
arch/arm/boot/dts/rk3288-miqi.dts | 8 ++++----
arch/arm/boot/dts/rk3288-popmetal.dts | 2 +-
arch/arm/boot/dts/rk3288-r89.dts | 12 ++++++------
arch/arm/boot/dts/rk3288-rock2-som.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-rock2-square.dts | 12 ++++++------
arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-veyron-brain.dts | 8 ++++----
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 10 +++++-----
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 14 ++++++-------
arch/arm/boot/dts/rk3288-veyron-jerry.dts | 10 +++++-----
arch/arm/boot/dts/rk3288-veyron-mickey.dts | 6 +++---
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 16 +++++++--------
arch/arm/boot/dts/rk3288-veyron-pinky.dts | 4 ++--
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 2 +-
arch/arm/boot/dts/rk3288-veyron-speedy.dts | 10 +++++-----
arch/arm/boot/dts/rk3288-veyron.dtsi | 8 ++++----
33 files changed, 131 insertions(+), 131 deletions(-)
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
index 2f5f155..c095341 100644
--- a/arch/arm/boot/dts/rk3036-evb.dts
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -56,7 +56,7 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
- phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 3de958e..2518259 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -55,7 +55,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
label = "kylin:red:led";
pinctrl-names = "default";
pinctrl-0 = <&led_ctl>;
@@ -74,9 +74,9 @@
* - SDIO_RESET_L_WL_RST
* - SDIO_RESET_L_BT_EN
*/
- reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
- <&gpio0 27 GPIO_ACTIVE_LOW>, /* WL_RST */
- <&gpio2 9 GPIO_ACTIVE_LOW>; /* BT_EN */
+ reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
+ <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */
+ <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */
};
sound {
@@ -121,7 +121,7 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
- phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index c0d8b54..9e852c6 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -71,7 +71,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
@@ -81,7 +81,7 @@
autorepeat;
power {
- gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
+ gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -89,7 +89,7 @@
debounce-interval = <100>;
};
volume-down {
- gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
linux,code = <KEY_VOLUMEDOWN>;
label = "GPIO Key Vol-";
linux,input-type = <1>;
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index 0a54c4b..cdf0a88 100644
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -69,7 +69,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index 658eb7d..7ca1cf5 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -61,7 +61,7 @@
blue {
label = "mk808:blue:power";
- gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "default-on";
};
@@ -77,7 +77,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&host_drv>;
pinctrl-names = "default";
regulator-always-on;
@@ -91,7 +91,7 @@
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&otg_drv>;
pinctrl-names = "default";
regulator-always-on;
@@ -104,7 +104,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdmmc_pwr>;
pinctrl-names = "default";
regulator-name = "vcc_sd";
@@ -117,7 +117,7 @@
vcc_wifi: sdio-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&wifi_pwr>;
pinctrl-names = "default";
regulator-name = "vcc_wifi";
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 82465b6..7c05e8b 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -55,7 +55,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio6 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -65,7 +65,7 @@
power {
wakeup-source;
- gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
pinctrl-names = "default";
@@ -115,7 +115,7 @@
vcc_sata: sata-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sata_pwr>;
regulator-name = "usb_5v";
@@ -127,7 +127,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -140,7 +140,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_drv>;
regulator-name = "host-pwr";
@@ -153,7 +153,7 @@
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_drv>;
regulator-name = "vcc_otg";
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index df727ba..4afd9d8 100644
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -62,7 +62,7 @@
autorepeat;
power {
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -248,7 +248,7 @@
reg = <0x40>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- power-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
silead,max-fingers = <5>;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 5e8a235..28a2931 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -58,7 +58,7 @@
autorepeat;
power {
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -72,19 +72,19 @@
green {
label = "rock:green:user1";
- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
blue {
label = "rock:blue:user2";
- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
sleep {
label = "rock:red:power";
- gpios = <&gpio0 15 0>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
@@ -106,7 +106,7 @@
ir_recv: gpio-ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio0 10 1>;
+ gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_recv_pin>;
};
@@ -114,7 +114,7 @@
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "otg-vbus";
@@ -129,7 +129,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
@@ -137,7 +137,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "host-pwr";
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index dcdd0ce..275092a 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -77,7 +77,7 @@
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 041dd5d..f4f29fe 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -47,7 +47,7 @@
vcc_lcd: vcc-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
regulator-name = "vcc_lcd";
@@ -57,7 +57,7 @@
vcc_wl: vcc-wl {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pwr>;
regulator-name = "vcc_wl";
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index bf7ccfa..0dec94c 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -84,7 +84,7 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
- enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
@@ -100,7 +100,7 @@
panel: panel {
compatible ="lg,lp079qx1-sp0v", "simple-panel";
backlight = <&backlight>;
- enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;
ports {
@@ -120,7 +120,7 @@
pinctrl-0 = <&pwrbtn>;
power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -133,7 +133,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -144,7 +144,7 @@
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <ð_phy_pwr>;
regulator-name = "vcc_phy";
@@ -170,7 +170,7 @@
*/
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -236,7 +236,7 @@
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts
index 805c0d2..dc00f12 100644
--- a/arch/arm/boot/dts/rk3288-fennec.dts
+++ b/arch/arm/boot/dts/rk3288-fennec.dts
@@ -93,7 +93,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "okay";
@@ -345,7 +345,7 @@
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&host_drv>;
- vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ vbus_drv-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts
index 75d77e3..0195d97 100644
--- a/arch/arm/boot/dts/rk3288-firefly-beta.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts
@@ -49,7 +49,7 @@
};
&ir {
- gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
};
&pinctrl {
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
index d242588..8134966 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
@@ -96,7 +96,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
index 751bee8..d28c8c3 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
@@ -53,7 +53,7 @@
power {
wakeup-source;
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
pinctrl-names = "default";
@@ -63,14 +63,14 @@
ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
};
leds {
compatible = "gpio-leds";
power {
- gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
label = "firefly:blue:power";
pinctrl-names = "default";
pinctrl-0 = <&power_led>;
@@ -78,7 +78,7 @@
};
work {
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
pinctrl-names = "default";
@@ -92,7 +92,7 @@
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable>;
- reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
sound {
@@ -112,7 +112,7 @@
vcc_host_5v: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host_5v";
@@ -133,7 +133,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -146,7 +146,7 @@
vcc_otg_5v: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_5v";
@@ -159,7 +159,7 @@
dovdd_1v8: dovdd-1v8-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "dovdd_1v8";
@@ -171,7 +171,7 @@
vcc28_dvp: vcc28-dvp-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "vcc28_dvp";
@@ -183,7 +183,7 @@
af_28: af_28-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "af_28";
@@ -195,7 +195,7 @@
dvdd_1v2: af_28-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cif_pwr>;
regulator-name = "dvdd_1v2";
diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts
index c07fe92..14271be 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dts
+++ b/arch/arm/boot/dts/rk3288-firefly.dts
@@ -49,7 +49,7 @@
};
&ir {
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
};
&pinctrl {
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 44935af..e4dd758 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -75,7 +75,7 @@
power {
wakeup-source;
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
pinctrl-names = "default";
@@ -87,7 +87,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
pinctrl-names = "default";
@@ -95,7 +95,7 @@
};
power {
- gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
label = "firefly:green:power";
linux,default-trigger = "default-on";
pinctrl-names = "default";
@@ -114,7 +114,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -145,7 +145,7 @@
vcc_host_5v: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host_5v";
@@ -158,7 +158,7 @@
vcc_otg_5v: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_5v";
@@ -175,7 +175,7 @@
vcc28_dvp: vcc28-dvp-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "vcc28_dvp";
@@ -213,7 +213,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 441d450..21326f3 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -68,7 +68,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_LOW>;
label = "miqi:green:user";
linux,default-trigger = "default-on";
pinctrl-names = "default";
@@ -87,7 +87,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -99,7 +99,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -146,7 +146,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index bc6d100..e0b5e84 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -180,7 +180,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
clock_in_out = "input";
- snps,reset-gpio = <&gpio4 RK_PB0 0>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index 04faa72..54a0fc0 100644
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -68,7 +68,7 @@
pinctrl-0 = <&pwrbtn>;
power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -79,7 +79,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -87,7 +87,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -98,7 +98,7 @@
vcc_otg: vcc-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg";
@@ -111,7 +111,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
@@ -134,7 +134,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index b25ba80..1c0bbc9 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -51,7 +51,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
};
ext_gmac: external-gmac-clock {
@@ -106,7 +106,7 @@
phy-supply = <&vccio_pmu>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins &phy_rst>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
rx_delay = <0x10>;
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index dd3ad2e..6cc83fe 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -53,13 +53,13 @@
compatible = "gpio-leds";
heartbeat {
- gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>;
label = "rock2:green:state1";
linux,default-trigger = "heartbeat";
};
mmc {
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
label = "rock2:blue:state2";
linux,default-trigger = "mmc0";
};
@@ -67,7 +67,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -92,13 +92,13 @@
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable>;
- reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_usb_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
/* Always on as the rockchip usb phy doesn't have a vbus-supply
@@ -110,7 +110,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
index 6d105914..f8c5a47 100644
--- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
@@ -17,8 +17,8 @@
rockchip,model = "VEYRON-I2S";
rockchip,i2s-controller = <&i2s>;
rockchip,audio-codec = <&max98090>;
- rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
- rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>;
+ rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>;
rockchip,headset-codec = <&headsetcodec>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts
index cf5311d..ed42552 100644
--- a/arch/arm/boot/dts/rk3288-veyron-brain.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts
@@ -67,7 +67,7 @@
vcc5_host2: vcc5-host2-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb2_pwr_en>;
regulator-name = "vcc5_host2";
@@ -103,8 +103,8 @@
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
/delete-property/ vcc6-supply;
@@ -133,7 +133,7 @@
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index ce1f879..9e882f3 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -91,7 +91,7 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
- enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
backlight-boot-off;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
@@ -102,7 +102,7 @@
gpio-charger {
compatible = "gpio-charger";
charger-type = "mains";
- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ac_present_ap>;
};
@@ -142,7 +142,7 @@
vcc5_host1: vcc5-host1-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host1_pwr_en>;
regulator-name = "vcc5_host1";
@@ -154,7 +154,7 @@
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usbotg_pwren_h>;
regulator-name = "vcc5_host2";
@@ -190,7 +190,7 @@
pinctrl-0 = <&pwr_key_l &ap_lid_int_l>;
lid {
label = "Lid";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <0>; /* SW_LID */
linux,input-type = <5>; /* EV_SW */
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index 3748abf..d33f576 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -57,7 +57,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -68,7 +68,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -80,7 +80,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -134,8 +134,8 @@
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
regulators {
mic_vcc: LDO_REG2 {
@@ -160,14 +160,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
index f6b2eaa..6107f76 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
@@ -56,7 +56,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -67,7 +67,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -79,7 +79,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -123,14 +123,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
index f36f6f4..f0994f0 100644
--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
@@ -182,8 +182,8 @@
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
/delete-property/ vcc6-supply;
/delete-property/ vcc12-supply;
@@ -244,7 +244,7 @@
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&power_hdmi_on>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index f72d616d..53c7205 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -55,7 +55,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -66,7 +66,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -77,7 +77,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -134,14 +134,14 @@
volum_down {
label = "Volum_down";
- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <100>;
};
volum_up {
label = "Volum_up";
- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <100>;
};
@@ -168,7 +168,7 @@
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int &touch_rst>;
- reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
vcc33-supply = <&vcc33_touch>;
vccio-supply = <&vcc33_touch>;
};
@@ -211,14 +211,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index d44351e..995cff4 100644
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -76,7 +76,7 @@
pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
power {
- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
};
};
@@ -126,7 +126,7 @@
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
&sdmmc_wp_gpio &sdmmc_bus4>;
- wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>;
};
&tsadc {
diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
index fec076e..aef0710 100644
--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
@@ -115,7 +115,7 @@
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
- cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
rockchip,default-sample-phase = <90>;
num-slots = <1>;
sd-uhs-sdr12;
diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
index a0d033f..cc0b78c 100644
--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
@@ -57,7 +57,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -68,7 +68,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -80,7 +80,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -126,14 +126,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 2251d28..e2ecd57 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -61,7 +61,7 @@
pinctrl-0 = <&pwr_key_l>;
power {
label = "Power";
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <100>;
wakeup-source;
@@ -70,7 +70,7 @@
gpio-restart {
compatible = "gpio-restart";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ap_warm_reset_h>;
priority = <200>;
@@ -80,7 +80,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
};
sdio_pwrseq: sdio-pwrseq {
@@ -96,7 +96,7 @@
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
- reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_5v: vcc-5v {
--
2.7.4
^ permalink raw reply related
* [PATCH 0/2] Use macros to describe gpios on rockchip platform
From: Andy Yan @ 2016-10-22 12:51 UTC (permalink / raw)
To: linux-arm-kernel
As patch 150696e2e3a4("Add GPIO pin index definition for rockchip pinctrl") has
been applied, now we can use these macros to describe the corresponding gpio
ranther than hard code numbers, this will make the dts easier to read and
write.
Some ideas from Krzysztof's patch on EXYNOS[0].
[0]https://lkml.org/lkml/2016/9/4/71
Andy Yan (2):
ARM: dts: rockchip: use pin constants to describe gpios
ARM64: dts: rockchip: use pin constants to describe gpios
arch/arm/boot/dts/rk3036-evb.dts | 2 +-
arch/arm/boot/dts/rk3036-kylin.dts | 10 ++++-----
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 6 +++---
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-mk808.dts | 10 ++++-----
arch/arm/boot/dts/rk3066a-rayeager.dts | 12 +++++------
arch/arm/boot/dts/rk3188-px3-evb.dts | 4 ++--
arch/arm/boot/dts/rk3188-radxarock.dts | 16 +++++++--------
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3288-evb-act8846.dts | 4 ++--
arch/arm/boot/dts/rk3288-evb.dtsi | 14 ++++++-------
arch/arm/boot/dts/rk3288-fennec.dts | 4 ++--
arch/arm/boot/dts/rk3288-firefly-beta.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload.dts | 24 +++++++++++-----------
arch/arm/boot/dts/rk3288-firefly.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly.dtsi | 16 +++++++--------
arch/arm/boot/dts/rk3288-miqi.dts | 8 ++++----
arch/arm/boot/dts/rk3288-popmetal.dts | 2 +-
arch/arm/boot/dts/rk3288-r89.dts | 12 +++++------
arch/arm/boot/dts/rk3288-rock2-som.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-rock2-square.dts | 12 +++++------
arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-veyron-brain.dts | 8 ++++----
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 10 ++++-----
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 14 ++++++-------
arch/arm/boot/dts/rk3288-veyron-jerry.dts | 10 ++++-----
arch/arm/boot/dts/rk3288-veyron-mickey.dts | 6 +++---
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 16 +++++++--------
arch/arm/boot/dts/rk3288-veyron-pinky.dts | 4 ++--
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 2 +-
arch/arm/boot/dts/rk3288-veyron-speedy.dts | 10 ++++-----
arch/arm/boot/dts/rk3288-veyron.dtsi | 8 ++++----
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 10 ++++-----
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 8 ++++----
.../boot/dts/rockchip/rk3368-orion-r68-meta.dts | 14 ++++++-------
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 4 ++--
arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 16 +++++++--------
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 6 +++---
39 files changed, 160 insertions(+), 160 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v2 1/3] ARM: dts: imx6qdl-apalis: Do not rely on DDC I2C bus bitbang for HDMI
From: Vladimir Zapolskiy @ 2016-10-22 12:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161022032559.GL30578@tiger>
Hi Shawn,
On 10/22/2016 06:25 AM, Shawn Guo wrote:
> On Mon, Sep 19, 2016 at 10:41:51AM +0530, Sanchayan Maity wrote:
>> Remove the use of DDC I2C bus bitbang to support reading of EDID
>> and rely on support from internal HDMI I2C master controller instead.
>> As a result remove the device tree property ddc-i2c-bus.
>>
>> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
>
> I think that the dw-hdmi i2c support [1] is a prerequisite of this
> patch. I do not see it lands on v4.9-rc1. Or am I missing something?
>
> Shawn
>
> [1] https://patchwork.kernel.org/patch/9296883/
>
I'm adding Philipp to Cc, since he is the last one who tested the change
and helped me to push the change to the mainline:
https://lists.freedesktop.org/archives/dri-devel/2016-September/118569.html
The problem is that there is no official DW HDMI bridge maintainer, may be
you can review the change, and if you find it satisfactory push it through
ARM/iMX tree.
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH v2] mtd: nand: Add OX820 NAND Support
From: Boris Brezillon @ 2016-10-22 12:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020084901.6486-1-narmstrong@baylibre.com>
On Thu, 20 Oct 2016 10:49:01 +0200
Neil Armstrong <narmstrong@baylibre.com> wrote:
> Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller.
> This is a simple memory mapped NAND controller with single chip select and
> software ECC.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Applied.
Thanks,
Boris
> ---
> .../devicetree/bindings/mtd/oxnas-nand.txt | 41 +++++
> drivers/mtd/nand/Kconfig | 5 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/oxnas_nand.c | 196 +++++++++++++++++++++
> 4 files changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> create mode 100644 drivers/mtd/nand/oxnas_nand.c
>
> Changes since v1 http://lkml.kernel.org/r/20161019145523.6763-1-narmstrong at baylibre.com :
> - Simplify cmd_ctrl command and drop the ctrl address offset
> - Change oxnas_nand struct name to oxnas_nand_ctrl
> - Update DT-Bindings example to reflect the ctrl->chip->partitions hierarchy
>
> Changes since RFC http://lkml.kernel.org/r/20161018090927.1990-1-narmstrong at baylibre.com :
> - Avoid using chip->IO_ADDR*
> - Use new DT structure
> - Assign a chip for the subnode
> - Use the nand_hw_control structure
> - Cleanup probe
> - Cleanup cmd_ctrl by using a context ctrl offset used in write_bytes
>
> diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> new file mode 100644
> index 0000000..33a77b8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> @@ -0,0 +1,41 @@
> +* Oxford Semiconductor OXNAS NAND Controller
> +
> +Please refer to nand.txt for generic information regarding MTD NAND bindings.
> +
> +Required properties:
> + - compatible: "oxsemi,ox820-nand"
> + - reg: Base address and length for NAND mapped memory.
> +
> +Optional Properties:
> + - clocks: phandle to the NAND gate clock if needed.
> + - resets: phandle to the NAND reset control if needed.
> +
> +Example:
> +
> +nand: nand-controller at 41000000 {
> + compatible = "oxsemi,ox820-nand";
> + reg = <0x41000000 0x100000>;
> + clocks = <&stdclk CLK_820_NAND>;
> + resets = <&reset RESET_NAND>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nand at 0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-ecc-mode = "soft";
> + nand-ecc-algo = "hamming";
> +
> + partition at 0 {
> + label = "boot";
> + reg = <0x00000000 0x00e00000>;
> + read-only;
> + };
> +
> + partition at e00000 {
> + label = "ubi";
> + reg = <0x00e00000 0x07200000>;
> + };
> + };
> +};
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 7b7a887..c023125 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -426,6 +426,11 @@ config MTD_NAND_ORION
> No board specific support is done by this driver, each board
> must advertise a platform_device for the driver to attach.
>
> +config MTD_NAND_OXNAS
> + tristate "NAND Flash support for Oxford Semiconductor SoC"
> + help
> + This enables the NAND flash controller on Oxford Semiconductor SoCs.
> +
> config MTD_NAND_FSL_ELBC
> tristate "NAND support for Freescale eLBC controllers"
> depends on FSL_SOC
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index cafde6f..05fc054 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
> obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
> obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
> obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
> +obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o
> obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
> obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
> obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
> diff --git a/drivers/mtd/nand/oxnas_nand.c b/drivers/mtd/nand/oxnas_nand.c
> new file mode 100644
> index 0000000..35c94af
> --- /dev/null
> +++ b/drivers/mtd/nand/oxnas_nand.c
> @@ -0,0 +1,196 @@
> +/*
> + * Oxford Semiconductor OXNAS NAND driver
> +
> + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
> + * Heavily based on plat_nand.c :
> + * Author: Vitaly Wool <vitalywool@gmail.com>
> + * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
> + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of.h>
> +
> +/* Nand commands */
> +#define OXNAS_NAND_CMD_ALE BIT(18)
> +#define OXNAS_NAND_CMD_CLE BIT(19)
> +
> +#define OXNAS_NAND_MAX_CHIPS 1
> +
> +struct oxnas_nand_ctrl {
> + struct nand_hw_control base;
> + void __iomem *io_base;
> + struct clk *clk;
> + struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
> +};
> +
> +static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + return readb(oxnas->io_base);
> +}
> +
> +static void oxnas_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + ioread8_rep(oxnas->io_base, buf, len);
> +}
> +
> +static void oxnas_nand_write_buf(struct mtd_info *mtd,
> + const uint8_t *buf, int len)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + iowrite8_rep(oxnas->io_base, buf, len);
> +}
> +
> +/* Single CS command control */
> +static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
> + unsigned int ctrl)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + if (ctrl & NAND_CLE)
> + writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
> + else if (ctrl & NAND_ALE)
> + writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
> +}
> +
> +/*
> + * Probe for the NAND device.
> + */
> +static int oxnas_nand_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device_node *nand_np;
> + struct oxnas_nand_ctrl *oxnas;
> + struct nand_chip *chip;
> + struct mtd_info *mtd;
> + struct resource *res;
> + int nchips = 0;
> + int count = 0;
> + int err = 0;
> +
> + /* Allocate memory for the device structure (and zero it) */
> + oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
> + GFP_KERNEL);
> + if (!oxnas)
> + return -ENOMEM;
> +
> + nand_hw_control_init(&oxnas->base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(oxnas->io_base))
> + return PTR_ERR(oxnas->io_base);
> +
> + oxnas->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(oxnas->clk))
> + oxnas->clk = NULL;
> +
> + /* Only a single chip node is supported */
> + count = of_get_child_count(np);
> + if (count > 1)
> + return -EINVAL;
> +
> + clk_prepare_enable(oxnas->clk);
> + device_reset_optional(&pdev->dev);
> +
> + for_each_child_of_node(np, nand_np) {
> + chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
> + GFP_KERNEL);
> + if (!chip)
> + return -ENOMEM;
> +
> + chip->controller = &oxnas->base;
> +
> + nand_set_flash_node(chip, nand_np);
> + nand_set_controller_data(chip, oxnas);
> +
> + mtd = nand_to_mtd(chip);
> + mtd->dev.parent = &pdev->dev;
> + mtd->priv = chip;
> +
> + chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
> + chip->read_buf = oxnas_nand_read_buf;
> + chip->read_byte = oxnas_nand_read_byte;
> + chip->write_buf = oxnas_nand_write_buf;
> + chip->chip_delay = 30;
> +
> + /* Scan to find existence of the device */
> + err = nand_scan(mtd, 1);
> + if (err)
> + return err;
> +
> + err = mtd_device_register(mtd, NULL, 0);
> + if (err) {
> + nand_release(mtd);
> + return err;
> + }
> +
> + oxnas->chips[nchips] = chip;
> + ++nchips;
> + }
> +
> + /* Exit if no chips found */
> + if (!nchips)
> + return -ENODEV;
> +
> + platform_set_drvdata(pdev, oxnas);
> +
> + return 0;
> +}
> +
> +static int oxnas_nand_remove(struct platform_device *pdev)
> +{
> + struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
> +
> + if (oxnas->chips[0])
> + nand_release(nand_to_mtd(oxnas->chips[0]));
> +
> + clk_disable_unprepare(oxnas->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id oxnas_nand_match[] = {
> + { .compatible = "oxsemi,ox820-nand" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, oxnas_nand_match);
> +
> +static struct platform_driver oxnas_nand_driver = {
> + .probe = oxnas_nand_probe,
> + .remove = oxnas_nand_remove,
> + .driver = {
> + .name = "oxnas_nand",
> + .of_match_table = oxnas_nand_match,
> + },
> +};
> +
> +module_platform_driver(oxnas_nand_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
> +MODULE_DESCRIPTION("Oxnas NAND driver");
> +MODULE_ALIAS("platform:oxnas_nand");
^ permalink raw reply
* [PATCH v3 1/3] mtd: s3c2410: make ecc mode configurable via platform data
From: Boris Brezillon @ 2016-10-22 12:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021182710.GA17279@kozik-lap>
Hi Krzysztof,
On Fri, 21 Oct 2016 21:27:10 +0300
Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Thu, Oct 20, 2016 at 07:42:44PM -0200, Sergio Prado wrote:
> > Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode
> > field in the drivers's platform data structure so it can be selectable
> > via platform data.
> >
> > Also setting this field to NAND_ECC_SOFT in all boards using this
> > driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.
> >
> > Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> > ---
> > arch/arm/mach-s3c24xx/common-smdk.c | 1 +
> > arch/arm/mach-s3c24xx/mach-anubis.c | 1 +
> > arch/arm/mach-s3c24xx/mach-at2440evb.c | 1 +
> > arch/arm/mach-s3c24xx/mach-bast.c | 1 +
> > arch/arm/mach-s3c24xx/mach-gta02.c | 1 +
> > arch/arm/mach-s3c24xx/mach-jive.c | 1 +
> > arch/arm/mach-s3c24xx/mach-mini2440.c | 1 +
> > arch/arm/mach-s3c24xx/mach-osiris.c | 1 +
> > arch/arm/mach-s3c24xx/mach-qt2410.c | 1 +
> > arch/arm/mach-s3c24xx/mach-rx1950.c | 1 +
> > arch/arm/mach-s3c24xx/mach-rx3715.c | 1 +
> > arch/arm/mach-s3c24xx/mach-vstms.c | 1 +
> > arch/arm/mach-s3c64xx/mach-hmt.c | 1 +
> > arch/arm/mach-s3c64xx/mach-mini6410.c | 1 +
> > arch/arm/mach-s3c64xx/mach-real6410.c | 1 +
> > drivers/mtd/nand/Kconfig | 9 --
> > drivers/mtd/nand/s3c2410.c | 119 +++++++++++++------------
> > include/linux/platform_data/mtd-nand-s3c2410.h | 6 +-
> > 18 files changed, 79 insertions(+), 70 deletions(-)
> >
>
> I acked this twice (v1 and v2)... and still you are ignoring them. I am
> sorry, I am not gonna to ack this third time!
>
> For v2 I acked also other patches but it it is not there as well...
I'll collect your acks (and Rob ones) when applying the patches. BTW,
how should I proceed with patch 1? Do you want an topic branch
containing this patch?
Regards,
Boris
^ permalink raw reply
* [PATCH v3 2/2] ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path
From: Fabio Estevam @ 2016-10-22 12:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477138856-31696-1-git-send-email-festevam@gmail.com>
From: Fabio Estevam <fabio.estevam@nxp.com>
If of_genpd_add_provider_onecell() fails the following kernel crash is
observed on a kernel built with multi_v7_defconfig:
[ 1.739301] [00000040] *pgd=00000000
[ 1.739310] Internal error: Oops: 5 [#1] SMP ARM
[ 1.739319] Modules linked in:
[ 1.739328] CPU: 1 PID: 95 Comm: kworker/1:4 Not tainted 4.8.0-11897-g6b5e09a #1
[ 1.739331] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[ 1.739352] Workqueue: pm genpd_power_off_work_fn
[ 1.739356] task: ee63d400 task.stack: ee70a000
[ 1.739365] PC is at mutex_lock+0xc/0x4c
[ 1.739374] LR is at regulator_disable+0x2c/0x60
[ 1.739379] pc : [<c0bc0da0>] lr : [<c06e4b10>] psr: 60000013
[ 1.739379] sp : ee70beb0 ip : 10624dd3 fp : ee6e6280
[ 1.739382] r10: eefb0900 r9 : 00000000 r8 : c1309918
[ 1.739385] r7 : 00000000 r6 : 00000040 r5 : 00000000 r4 : 00000040
[ 1.739390] r3 : 0000004c r2 : 7fffd540 r1 : 000001e4 r0 : 00000040
Instead of returning of_genpd_add_provider_onecell() directly,
we should check its return value and in the case of error we
should unwind the previously taken actions, which in these case are:
- Call imx6q_pm_pu_power_off()
- Set imx6q_pu_domain.reg back to NULL
Setting imx6q_pu_domain.reg to NULL in the error case is important
as it will prevent further operations in the pu_reg regulator.
This kernel crash is not observed with imx_v6_v7_defconfig because
it selects GPU and VPU drivers, which are consumers of the GPC block
and thus change the refcount of the pu_reg regulator.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
Changes since v2:
- Newly introduced
arch/arm/mach-imx/gpc.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index d0463e9..b54db47 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -408,7 +408,7 @@ static struct genpd_onecell_data imx_gpc_onecell_data = {
static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
{
struct clk *clk;
- int i;
+ int i, ret;
imx6q_pu_domain.reg = pu_reg;
@@ -432,12 +432,20 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
pm_genpd_init(imx_gpc_domains[i], NULL, false);
- return of_genpd_add_provider_onecell(dev->of_node,
+
+ ret = of_genpd_add_provider_onecell(dev->of_node,
&imx_gpc_onecell_data);
+ if (ret)
+ goto power_off;
+
+ return 0;
+power_off:
+ imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
clk_err:
while (i--)
clk_put(imx6q_pu_domain.clk[i]);
+ imx6q_pu_domain.reg = NULL;
return -EINVAL;
}
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/2] ARM: imx: gpc: Initialize all power domains
From: Fabio Estevam @ 2016-10-22 12:20 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
Since commit 0159ec670763dd ("PM / Domains: Verify the PM domain is present
when adding a provider") the following regression is observed on imx6:
imx-gpc: probe of 20dc000.gpc failed with error -22
The gpc probe fails because of_genpd_add_provider_onecell() now checks
if all the domains are initialized via pm_genpd_present() function
and it fails because not all the power domains are initialized.
In order to fix this error, initialize all the power domains from
imx_gpc_domains[], not only the imx6q_pu_domain.base one.
Reported-by: Olof's autobooter <build@lixom.net>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
Changes since v2:
- Adjust commit log
arch/arm/mach-imx/gpc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 0df062d..d0463e9 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -430,7 +430,8 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
return 0;
- pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
+ for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
+ pm_genpd_init(imx_gpc_domains[i], NULL, false);
return of_genpd_add_provider_onecell(dev->of_node,
&imx_gpc_onecell_data);
--
2.7.4
^ permalink raw reply related
* [PATCH] asm-generic: Drop getrlimit and setrlimit syscalls from default list
From: Yury Norov @ 2016-10-22 12:14 UTC (permalink / raw)
To: linux-arm-kernel
The newer prlimit64 syscall provides all the functionality provided by
the getrlimit and setrlimit syscalls and adds the pid of target process,
so future architectures won't need to include getrlimit and setrlimit.
Therefore drop getrlimit and setrlimit syscalls from the generic syscall
list unless __ARCH_WANT_SET_GET_RLIMIT is defined by the architecture's
unistd.h prior to including asm-generic/unistd.h, and adjust all
architectures using the generic syscall list to define it so that no
in-tree architectures are affected.
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Salter <msalter@redhat.com>
Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Ley Foon Tan <lftan@altera.com>
Cc: Jonas Bonn <jonas@southpole.se>
Cc: Chen Liqin <liqin.linux@gmail.com>
Cc: Lennox Wu <lennox.wu@gmail.com>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andrew Pinski <Andrew.Pinski@cavium.com>
Cc: linux-snps-arc at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-c6x-dev at linux-c6x.org
Cc: uclinux-h8-devel at lists.sourceforge.jp
Cc: linux-hexagon at vger.kernel.org
Cc: linux-metag at vger.kernel.org
Cc: nios2-dev at lists.rocketboards.org
Cc: linux-arch at vger.kernel.or
Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
---
arch/arc/include/uapi/asm/unistd.h | 1 +
arch/arm64/include/uapi/asm/unistd.h | 1 +
arch/c6x/include/uapi/asm/unistd.h | 1 +
arch/h8300/include/uapi/asm/unistd.h | 1 +
arch/hexagon/include/uapi/asm/unistd.h | 1 +
arch/metag/include/uapi/asm/unistd.h | 1 +
arch/nios2/include/uapi/asm/unistd.h | 1 +
arch/openrisc/include/uapi/asm/unistd.h | 1 +
arch/score/include/uapi/asm/unistd.h | 1 +
arch/tile/include/uapi/asm/unistd.h | 1 +
arch/unicore32/include/uapi/asm/unistd.h | 1 +
include/uapi/asm-generic/unistd.h | 5 +++++
12 files changed, 16 insertions(+)
diff --git a/arch/arc/include/uapi/asm/unistd.h b/arch/arc/include/uapi/asm/unistd.h
index 41fa2ec..928546d 100644
--- a/arch/arc/include/uapi/asm/unistd.h
+++ b/arch/arc/include/uapi/asm/unistd.h
@@ -16,6 +16,7 @@
#define _UAPI_ASM_ARC_UNISTD_H
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#define __ARCH_WANT_SYS_EXECVE
#define __ARCH_WANT_SYS_CLONE
#define __ARCH_WANT_SYS_VFORK
diff --git a/arch/arm64/include/uapi/asm/unistd.h b/arch/arm64/include/uapi/asm/unistd.h
index 043d17a..48355a6 100644
--- a/arch/arm64/include/uapi/asm/unistd.h
+++ b/arch/arm64/include/uapi/asm/unistd.h
@@ -15,5 +15,6 @@
*/
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#include <asm-generic/unistd.h>
diff --git a/arch/c6x/include/uapi/asm/unistd.h b/arch/c6x/include/uapi/asm/unistd.h
index 12d73d9..f676231 100644
--- a/arch/c6x/include/uapi/asm/unistd.h
+++ b/arch/c6x/include/uapi/asm/unistd.h
@@ -15,6 +15,7 @@
*/
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#define __ARCH_WANT_SYS_CLONE
/* Use the standard ABI for syscalls. */
diff --git a/arch/h8300/include/uapi/asm/unistd.h b/arch/h8300/include/uapi/asm/unistd.h
index 7dd20ef..2f98394 100644
--- a/arch/h8300/include/uapi/asm/unistd.h
+++ b/arch/h8300/include/uapi/asm/unistd.h
@@ -1,5 +1,6 @@
#define __ARCH_NOMMU
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#include <asm-generic/unistd.h>
diff --git a/arch/hexagon/include/uapi/asm/unistd.h b/arch/hexagon/include/uapi/asm/unistd.h
index 2151760..52d585c 100644
--- a/arch/hexagon/include/uapi/asm/unistd.h
+++ b/arch/hexagon/include/uapi/asm/unistd.h
@@ -28,6 +28,7 @@
#define sys_mmap2 sys_mmap_pgoff
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#define __ARCH_WANT_SYS_EXECVE
#define __ARCH_WANT_SYS_CLONE
#define __ARCH_WANT_SYS_VFORK
diff --git a/arch/metag/include/uapi/asm/unistd.h b/arch/metag/include/uapi/asm/unistd.h
index 459b6ec..16b5cb3 100644
--- a/arch/metag/include/uapi/asm/unistd.h
+++ b/arch/metag/include/uapi/asm/unistd.h
@@ -8,6 +8,7 @@
*/
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
/* Use the standard ABI for syscalls. */
#include <asm-generic/unistd.h>
diff --git a/arch/nios2/include/uapi/asm/unistd.h b/arch/nios2/include/uapi/asm/unistd.h
index 51a32c7..b0dda4d 100644
--- a/arch/nios2/include/uapi/asm/unistd.h
+++ b/arch/nios2/include/uapi/asm/unistd.h
@@ -18,6 +18,7 @@
#define sys_mmap2 sys_mmap_pgoff
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
/* Use the standard ABI for syscalls */
#include <asm-generic/unistd.h>
diff --git a/arch/openrisc/include/uapi/asm/unistd.h b/arch/openrisc/include/uapi/asm/unistd.h
index 471905b..6812d81 100644
--- a/arch/openrisc/include/uapi/asm/unistd.h
+++ b/arch/openrisc/include/uapi/asm/unistd.h
@@ -21,6 +21,7 @@
#define sys_mmap2 sys_mmap_pgoff
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#define __ARCH_WANT_SYS_FORK
#define __ARCH_WANT_SYS_CLONE
diff --git a/arch/score/include/uapi/asm/unistd.h b/arch/score/include/uapi/asm/unistd.h
index d4008c3..7ad1bdc 100644
--- a/arch/score/include/uapi/asm/unistd.h
+++ b/arch/score/include/uapi/asm/unistd.h
@@ -1,6 +1,7 @@
#define __ARCH_HAVE_MMU
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#define __ARCH_WANT_SYSCALL_NO_AT
#define __ARCH_WANT_SYSCALL_NO_FLAGS
#define __ARCH_WANT_SYSCALL_OFF_T
diff --git a/arch/tile/include/uapi/asm/unistd.h b/arch/tile/include/uapi/asm/unistd.h
index 24e9187..cf0505f 100644
--- a/arch/tile/include/uapi/asm/unistd.h
+++ b/arch/tile/include/uapi/asm/unistd.h
@@ -13,6 +13,7 @@
*/
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
/* Use the flavor of this syscall that matches the 32-bit API better. */
#define __ARCH_WANT_SYNC_FILE_RANGE2
diff --git a/arch/unicore32/include/uapi/asm/unistd.h b/arch/unicore32/include/uapi/asm/unistd.h
index 1f63c47..ef25aec 100644
--- a/arch/unicore32/include/uapi/asm/unistd.h
+++ b/arch/unicore32/include/uapi/asm/unistd.h
@@ -11,6 +11,7 @@
*/
#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_SET_GET_RLIMIT
/* Use the standard ABI for syscalls. */
#include <asm-generic/unistd.h>
diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h
index 9b1462e..bbaeac0 100644
--- a/include/uapi/asm-generic/unistd.h
+++ b/include/uapi/asm-generic/unistd.h
@@ -465,10 +465,15 @@ __SYSCALL(__NR_uname, sys_newuname)
__SYSCALL(__NR_sethostname, sys_sethostname)
#define __NR_setdomainname 162
__SYSCALL(__NR_setdomainname, sys_setdomainname)
+
+#ifdef __ARCH_WANT_SET_GET_RLIMIT
+/* getrlimit and setrlimit are superseded with prlimit64 */
#define __NR_getrlimit 163
__SC_COMP(__NR_getrlimit, sys_getrlimit, compat_sys_getrlimit)
#define __NR_setrlimit 164
__SC_COMP(__NR_setrlimit, sys_setrlimit, compat_sys_setrlimit)
+#endif
+
#define __NR_getrusage 165
__SC_COMP(__NR_getrusage, sys_getrusage, compat_sys_getrusage)
#define __NR_umask 166
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/6] pwm: imx: support output polarity inversion
From: Boris Brezillon @ 2016-10-22 12:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021234939.1a4f51f4@jawa>
On Fri, 21 Oct 2016 23:49:39 +0200
Lukasz Majewski <l.majewski@majess.pl> wrote:
> Hi Stefan,
>
> > On 2016-10-20 01:30, Lukasz Majewski wrote:
> > > Hi Stefan,
> > >
> > >> Hi Stefan,
> > >>
> > >> > On 2016-10-12 15:15, Lukasz Majewski wrote:
> > >> > > Hi Stefan,
> > >> > >
> > >> > >> On 2016-10-07 08:11, Bhuvanchandra DV wrote:
> > >> > >> > From: Lothar Wassmann <LW@KARO-electronics.de>
> > >> > >> >
> > >> > >> > The i.MX pwm unit on i.MX27 and newer SoCs provides a
> > >> > >> > configurable output polarity. This patch adds support to
> > >> > >> > utilize this feature where available.
> > >> > >> >
> > >> > >> > Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> > >> > >> > Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> > >> > >> > Signed-off-by: Bhuvanchandra DV
> > >> > >> > <bhuvanchandra.dv@toradex.com> Acked-by: Shawn Guo
> > >> > >> > <shawn.guo@linaro.org> Reviewed-by: Sascha Hauer
> > >> > >> > <s.hauer@pengutronix.de> ---
> > >> > >> > Documentation/devicetree/bindings/pwm/imx-pwm.txt | 6 +--
> > >> > >> > drivers/pwm/pwm-imx.c | 51
> > >> > >> > +++++++++++++++++++++-- 2 files changed, 51 insertions(+), 6
> > >> > >> > deletions(-)
> > >> > >> >
> > >> > >> > diff --git
> > >> > >> > a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > >> > >> > b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index
> > >> > >> > e00c2e9..c61bdf8 100644 ---
> > >> > >> > a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++
> > >> > >> > b/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -6,8
> > >> > >> > +6,8 @@ Required properties:
> > >> > >> > - "fsl,imx1-pwm" for PWM compatible with the one
> > >> > >> > integrated on i.MX1
> > >> > >> > - "fsl,imx27-pwm" for PWM compatible with the one
> > >> > >> > integrated on i.MX27
> > >> > >> > - reg: physical base address and length of the controller's
> > >> > >> > registers -- #pwm-cells: should be 2. See pwm.txt in this
> > >> > >> > directory for a description of
> > >> > >> > - the cells format.
> > >> > >> > +- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs.
> > >> > >> > See pwm.txt
> > >> > >> > + in this directory for a description of the cells format.
> > >> > >> > - clocks : Clock specifiers for both ipg and per clocks.
> > >> > >> > - clock-names : Clock names should include both "ipg" and
> > >> > >> > "per" See the clock consumer binding,
> > >> > >> > @@ -17,7 +17,7 @@ See the clock consumer binding,
> > >> > >> > Example:
> > >> > >> >
> > >> > >> > pwm1: pwm at 53fb4000 {
> > >> > >> > - #pwm-cells = <2>;
> > >> > >> > + #pwm-cells = <3>;
> > >> > >> > compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
> > >> > >> > reg = <0x53fb4000 0x4000>;
> > >> > >> > clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
> > >> > >> > diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> > >> > >> > index d600fd5..c37d223 100644
> > >> > >> > --- a/drivers/pwm/pwm-imx.c
> > >> > >> > +++ b/drivers/pwm/pwm-imx.c
> > >> > >> > @@ -38,6 +38,7 @@
> > >> > >> > #define MX3_PWMCR_DOZEEN (1 << 24)
> > >> > >> > #define MX3_PWMCR_WAITEN (1 << 23)
> > >> > >> > #define MX3_PWMCR_DBGEN (1 << 22)
> > >> > >> > +#define MX3_PWMCR_POUTC (1 << 18)
> > >> > >> > #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> > >> > >> > #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> > >> > >> > #define MX3_PWMCR_SWR (1 << 3)
> > >> > >> > @@ -180,6 +181,9 @@ static int imx_pwm_config_v2(struct
> > >> > >> > pwm_chip *chip, if (enable)
> > >> > >> > cr |= MX3_PWMCR_EN;
> > >> > >> >
> > >> > >> > + if (pwm->args.polarity == PWM_POLARITY_INVERSED)
> > >> > >> > + cr |= MX3_PWMCR_POUTC;
> > >> > >> > +
> > >> > >>
> > >> > >> This seems wrong to me, the config callback is meant for
> > >> > >> period/duty cycle only.
> > >
> > > Unfortunately, it also resets the PWM IP block and setups it again
> > > (by writing to PWMCR register). In that function we setup for
> > > example MX3_PWMCR_DOZEEN
> > > and MX3_PWMCR_DBGEN. Why cannot we setup polarity as well?
> > >
> > >
> > > I've double checked the backlight and pwm code flow.
> > >
> > > Please find following snippet:
> > >
> > > [ 0.135545] ######### imx_pwm_probe
> > > [ 0.135581] PWM supports output inversion
> > > [ 0.136864] ######### pwm_backlight_probe
> > > [ 0.136913] backlight supply power not found, using dummy
> > > regulator [ 0.136984] ######### imx_pwm_set_polarity 1
> > > [ 0.136995] imx_pwm_set_polarity: polarity set to inverted cr:
> > > 0x40000 0xf08f8000
> > > [ 0.137005] #########0 imx_pwm_config_v2 cr: 0x40000
> > > [ 0.137683] #########1 imx_pwm_config_v2 cr: 0x0 0xf08f8000
> > > [ 0.137693] #########2 imx_pwm_config_v2 cr: 0x1c20050
> > > [ 0.137702] #########3 imx_pwm_config_v2 cr: 0x1c20050 0xf08f8000
> > > [ 0.137711] @@@@@@@@@@ pwm_apply_state
>
> Maybe a bit more logs:
>
> [ 0.135451] ######### imx_pwm_probe
> [ 0.135488] PWM supports output inversion
> [ 0.136777] ######### pwm_backlight_probe
> [ 0.136826] backlight supply power not found, using dummy regulator
> [ 0.136893] ********* pwm_apply_state state->enabled: 0
> [ 0.136902] ######### imx_pwm_set_polarity 1
> [ 0.136913] imx_pwm_set_polarity: polarity set to inverted cr: 0x40000 0xf08f8000
> [ 0.136923] #########0 imx_pwm_config_v2 cr: 0x40000
> [ 0.137692] #########1 imx_pwm_config_v2 cr: 0x0 0xf08f8000
> [ 0.137701] #########2 imx_pwm_config_v2 cr: 0x1c20050
> [ 0.137710] #########3 imx_pwm_config_v2 cr: 0x1c20050 0xf08f8000
> [ 0.137720] @@@@@@@@@@ pwm_apply_state
> [ 0.137856] ********* pwm_apply_state state->enabled: 0
> [ 0.137869] #########0 imx_pwm_config_v2 cr: 0x1c20050
> [ 0.138904] #########1 imx_pwm_config_v2 cr: 0x0 0xf08f8000
> [ 0.138913] #########2 imx_pwm_config_v2 cr: 0x1c20050
> [ 0.138921] #########3 imx_pwm_config_v2 cr: 0x1c20050 0xf08f8000
> [ 0.138928] @@@@@@@@@@ pwm_apply_state
> [ 0.138940] ********* pwm_apply_state state->enabled: 1
> ^^^^^^^^^^^^^^^^^^ this is called from
> pwm_backlight_power_on() from pwm_bl probe function
>
> The problem here is not the lack of ->apply() callback, but the requirement to
> perform software reset on the pwm_v2 fifo when the pwm_v2 is NOT enabled (state->enabled: 0).
>
> As fair as I can see the pwm_state has following members: period, duty cycle, polarity and enabled.
> I'm fine to implement ->apply() callback, which would change above values.
>
> However, there is a problem with ->config() (imx_pwm_config_v2 @ pwm-imx.c) and imx pwm_v2 software
> FIFO reset.
> We can set polarity in any other kernel subsystem, which uses PWM (backlight in this example) and
> then this setting would disappear when we call pwm_apply_state with state->enabled = 0 (as presented
> in the log). This imposes setting polarity at ->config when we enable the PWM (as this patch does).
>
>
>
> > >
> > > Here the pwm_backlight_probe calls set_polarity callback available
> > > in pwm - the polarity is set (the 0x40000 value).
> > >
> > > The above operation is performed in pwm_apply_state (@
> > > drivers/pwm/core.c). In the same function, latter we call the
> > > pwm->chip->ops->config(), which is the pointer to config_v2.
> > > Since the PWM is not yet enabled, this function performs SW reset
> > > and PWM inversion setting is cleared.
> >
> > That function should not do that.
>
> I do agree that it shouldn't. Correct me if I'm wrong, but it seems like an
> PWM HW requirement to perform the reset.
>
> >It was probably already problematic
> > in the old times, it is definitely now with the atomic PWM stuff.
>
> The "atomic"[*] code (with ->apply() provided) will not solve this issue.
>
> >
> > >
> > > Possible solutions:
> > >
> > > 1. Leave the original patch from Bhuvanchandra as it was (I'm for
> > > this option)
> >
> > That really seems like a hack to me, and makes transition to the
> > atomic PWM API more complex.
>
> Could you be more specific here?
>
> As I mentioned before, the problem is not with the lack of
> "atomic" API.
Below is a quick and dirty I made on top of this patch to show you how
atomic update can be implemented in this driver. It's not tested, and
probably not working, but it should give you a better idea of what is
expected.
--->8---
>From f4dc9a368a951b619a9c67791cb9515ca70da0ee Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Sat, 22 Oct 2016 13:55:19 +0200
Subject: [PATCH] pwm: imx: switch to the atomic interface and related cleanup
This is just a crappy commit to show you how atomic update can be
implemented. Please do not submit the changes as is.
This commit is based on https://lkml.org/lkml/2016/10/7/454.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
drivers/pwm/pwm-imx.c | 262 +++++++++++++++++++++++---------------------------
1 file changed, 119 insertions(+), 143 deletions(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index c37d22371848..c6d55f92dc40 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -66,8 +66,6 @@ struct imx_chip {
static int imx_pwm_config_v1(struct pwm_chip *chip,
struct pwm_device *pwm, int duty_ns, int period_ns)
{
- struct imx_chip *imx = to_imx_chip(chip);
-
/*
* The PWM subsystem allows for exact frequencies. However,
* I cannot connect a scope on my device to the PWM line and
@@ -85,81 +83,118 @@ static int imx_pwm_config_v1(struct pwm_chip *chip,
* both the prescaler (/1 .. /128) and then by CLKSEL
* (/2 .. /16).
*/
+ struct imx_chip *imx = to_imx_chip(chip);
u32 max = readl(imx->mmio_base + MX1_PWMP);
u32 p = max * duty_ns / period_ns;
+ int ret;
+
+ ret = clk_prepare_enable(imx->clk_ipg);
+ if (ret)
+ return ret;
+
writel(max - p, imx->mmio_base + MX1_PWMS);
+ clk_disable_unprepare(imx->clk_ipg);
+
return 0;
}
-static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
+static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct imx_chip *imx = to_imx_chip(chip);
+ int ret;
u32 val;
+ ret = clk_prepare_enable(imx->clk_ipg);
+ if (ret)
+ return ret;
+
val = readl(imx->mmio_base + MX1_PWMC);
- if (enable)
- val |= MX1_PWMC_EN;
- else
- val &= ~MX1_PWMC_EN;
+ val |= MX1_PWMC_EN;
writel(val, imx->mmio_base + MX1_PWMC);
+
+ clk_disable_unprepare(imx->clk_per);
+
+ return 0;
}
-static int imx_pwm_config_v2(struct pwm_chip *chip,
- struct pwm_device *pwm, int duty_ns, int period_ns)
+static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct imx_chip *imx = to_imx_chip(chip);
+ u32 val;
+
+ val = readl(imx->mmio_base + MX1_PWMC);
+
+ val &= ~MX1_PWMC_EN;
+
+ writel(val, imx->mmio_base + MX1_PWMC);
+
+ clk_disable_unprepare(imx->clk_per);
+}
+
+static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct imx_chip *imx = to_imx_chip(chip);
struct device *dev = chip->dev;
- unsigned long long c;
- unsigned long period_cycles, duty_cycles, prescale;
unsigned int period_ms;
- bool enable = pwm_is_enabled(pwm);
- int wait_count = 0, fifoav;
- u32 cr, sr;
+ int fifoav;
+ u32 sr;
+
+ sr = readl(imx->mmio_base + MX3_PWMSR);
+ fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
+ if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
+ period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
+ NSEC_PER_MSEC);
+ msleep(period_ms);
- /*
- * i.MX PWMv2 has a 4-word sample FIFO.
- * In order to avoid FIFO overflow issue, we do software reset
- * to clear all sample FIFO if the controller is disabled or
- * wait for a full PWM cycle to get a relinquished FIFO slot
- * when the controller is enabled and the FIFO is fully loaded.
- */
- if (enable) {
sr = readl(imx->mmio_base + MX3_PWMSR);
- fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
- if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
- period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
- NSEC_PER_MSEC);
- msleep(period_ms);
-
- sr = readl(imx->mmio_base + MX3_PWMSR);
- if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
- dev_warn(dev, "there is no free FIFO slot\n");
- }
- } else {
- writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
- do {
- usleep_range(200, 1000);
- cr = readl(imx->mmio_base + MX3_PWMCR);
- } while ((cr & MX3_PWMCR_SWR) &&
- (wait_count++ < MX3_PWM_SWR_LOOP));
-
- if (cr & MX3_PWMCR_SWR)
- dev_warn(dev, "software reset timeout\n");
+ if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
+ dev_warn(dev, "there is no free FIFO slot\n");
}
+}
+
+static void imx_pwm_empty_fifo(struct pwm_chip *chip)
+{
+ struct imx_chip *imx = to_imx_chip(chip);
+ struct device *dev = chip->dev;
+ int wait_count = 0;
+ u32 cr;
+
+ writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
+ do {
+ usleep_range(200, 1000);
+ cr = readl(imx->mmio_base + MX3_PWMCR);
+ } while ((cr & MX3_PWMCR_SWR) &&
+ (wait_count++ < MX3_PWM_SWR_LOOP));
+
+ if (cr & MX3_PWMCR_SWR)
+ dev_warn(dev, "software reset timeout\n");
+}
+
+static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct imx_chip *imx = to_imx_chip(chip);
+ unsigned long long c;
+ unsigned long period_cycles, duty_cycles, prescale;
+ struct pwm_state cstate;
+ int ret;
+ u32 cr = 0;
+
+ pwm_get_state(pwm, &cstate);
c = clk_get_rate(imx->clk_per);
- c = c * period_ns;
+ c = c * state->period;
do_div(c, 1000000000);
period_cycles = c;
prescale = period_cycles / 0x10000 + 1;
period_cycles /= prescale;
- c = (unsigned long long)period_cycles * duty_ns;
- do_div(c, period_ns);
+ c = (unsigned long long)period_cycles * state->duty_cycle;
+ do_div(c, state->period);
duty_cycles = c;
/*
@@ -171,134 +206,72 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
else
period_cycles = 0;
- writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
- writel(period_cycles, imx->mmio_base + MX3_PWMPR);
-
- cr = MX3_PWMCR_PRESCALER(prescale) |
- MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
- MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
-
- if (enable)
- cr |= MX3_PWMCR_EN;
-
- if (pwm->args.polarity == PWM_POLARITY_INVERSED)
- cr |= MX3_PWMCR_POUTC;
-
- writel(cr, imx->mmio_base + MX3_PWMCR);
-
- return 0;
-}
-
-static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
-{
- struct imx_chip *imx = to_imx_chip(chip);
- u32 val;
-
- val = readl(imx->mmio_base + MX3_PWMCR);
-
- if (enable)
- val |= MX3_PWMCR_EN;
- else
- val &= ~MX3_PWMCR_EN;
-
- writel(val, imx->mmio_base + MX3_PWMCR);
-}
-
-static int imx_pwm_config(struct pwm_chip *chip,
- struct pwm_device *pwm, int duty_ns, int period_ns)
-{
- struct imx_chip *imx = to_imx_chip(chip);
- int ret;
-
- ret = clk_prepare_enable(imx->clk_ipg);
- if (ret)
- return ret;
-
- ret = imx->config(chip, pwm, duty_ns, period_ns);
-
- clk_disable_unprepare(imx->clk_ipg);
-
- return ret;
-}
-
-static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
- struct imx_chip *imx = to_imx_chip(chip);
- int ret;
-
ret = clk_prepare_enable(imx->clk_per);
if (ret)
return ret;
- imx->set_enable(chip, true);
-
- return 0;
-}
+ /* Enable the clock if the PWM is being enabled. */
+ if (state->enabled && !cstate.enabled) {
+ ret = clk_prepare_enable(imx->clk_per);
+ if (ret)
+ return ret;
+ }
-static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
- struct imx_chip *imx = to_imx_chip(chip);
+ /*
+ * Wait for a free FIFO slot if the PWM is already enabled, and flush
+ * the FIFO if the PWM was disabled and is about to be enabled.
+ */
+ if (cstate.enabled)
+ imx_pwm_wait_fifo_slot(chip, pwm);
+ else if (state->enabled)
+ imx_pwm_empty_fifo(chip);
- imx->set_enable(chip, false);
+ writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
+ writel(period_cycles, imx->mmio_base + MX3_PWMPR);
- clk_disable_unprepare(imx->clk_per);
-}
+ cr |= MX3_PWMCR_PRESCALER(prescale) |
+ MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
+ MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
-static int imx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
- enum pwm_polarity polarity)
-{
- struct imx_chip *imx = to_imx_chip(chip);
- u32 val;
+ if (state->enabled)
+ cr |= MX3_PWMCR_EN;
- if (polarity == pwm->args.polarity)
- return 0;
+ if (state->polarity == PWM_POLARITY_INVERSED)
+ cr |= MX3_PWMCR_POUTC;
- val = readl(imx->mmio_base + MX3_PWMCR);
- if (polarity == PWM_POLARITY_INVERSED)
- val |= MX3_PWMCR_POUTC;
- else
- val &= ~MX3_PWMCR_POUTC;
+ writel(cr, imx->mmio_base + MX3_PWMCR);
- writel(val, imx->mmio_base + MX3_PWMCR);
+ /* Disable the clock if the PWM is being disabled. */
+ if (!state->enabled && cstate.enabled)
+ clk_disable_unprepare(imx->clk_per);
- dev_dbg(imx->chip.dev, "%s: polarity set to %s\n", __func__,
- polarity == PWM_POLARITY_INVERSED ? "inverted" : "normal");
+ clk_disable_unprepare(imx->clk_per);
return 0;
}
static struct pwm_ops imx_pwm_ops_v1 = {
- .enable = imx_pwm_enable,
- .disable = imx_pwm_disable,
- .config = imx_pwm_config,
+ .enable = imx_pwm_enable_v1,
+ .disable = imx_pwm_disable_v1,
+ .config = imx_pwm_config_v1,
.owner = THIS_MODULE,
};
static struct pwm_ops imx_pwm_ops_v2 = {
- .enable = imx_pwm_enable,
- .disable = imx_pwm_disable,
- .set_polarity = imx_pwm_set_polarity,
- .config = imx_pwm_config,
+ .apply = imx_pwm_apply_v2,
.owner = THIS_MODULE,
};
struct imx_pwm_data {
- int (*config)(struct pwm_chip *chip,
- struct pwm_device *pwm, int duty_ns, int period_ns);
- void (*set_enable)(struct pwm_chip *chip, bool enable);
struct pwm_ops *pwm_ops;
};
static struct imx_pwm_data imx_pwm_data_v1 = {
- .config = imx_pwm_config_v1,
- .set_enable = imx_pwm_set_enable_v1,
.pwm_ops = &imx_pwm_ops_v1,
};
static struct imx_pwm_data imx_pwm_data_v2 = {
- .config = imx_pwm_config_v2,
- .set_enable = imx_pwm_set_enable_v2,
.pwm_ops = &imx_pwm_ops_v2,
};
@@ -317,6 +290,7 @@ static int imx_pwm_probe(struct platform_device *pdev)
struct imx_chip *imx;
struct resource *r;
int ret = 0;
+ u32 cells;
if (!of_id)
return -ENODEV;
@@ -346,7 +320,12 @@ static int imx_pwm_probe(struct platform_device *pdev)
imx->chip.base = -1;
imx->chip.npwm = 1;
imx->chip.can_sleep = true;
- if (data->pwm_ops->set_polarity) {
+
+ ret = of_property_read_u32(pdev->dev.of_node, "#pwm-cells", &cells);
+ if (ret)
+ return ret;
+
+ if (cells == 3) {
dev_dbg(&pdev->dev, "PWM supports output inversion\n");
imx->chip.of_xlate = of_pwm_xlate_with_flags;
imx->chip.of_pwm_n_cells = 3;
@@ -357,9 +336,6 @@ static int imx_pwm_probe(struct platform_device *pdev)
if (IS_ERR(imx->mmio_base))
return PTR_ERR(imx->mmio_base);
- imx->config = data->config;
- imx->set_enable = data->set_enable;
-
ret = pwmchip_add(&imx->chip);
if (ret < 0)
return ret;
--
2.7.4
^ permalink raw reply related
* Disabling an interrupt in the handler locks the system up
From: Marc Zyngier @ 2016-10-22 11:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <580A7A2B.5000702@free.fr>
On Fri, 21 Oct 2016 22:27:23 +0200
Mason <slash.tmp@free.fr> wrote:
> On 21/10/2016 21:49, Thomas Gleixner wrote:
> > On Fri, 21 Oct 2016, Mason wrote:
> >> On 21/10/2016 21:14, Marc Zyngier wrote:
> >>> If connecting a device that signals its interrupt as level low to an
> >>> input line configured as level high doesn't strike you as a major
> >>> issue, nothing will. At that point, you can put anything you want in
> >>> your DT.
> >>
> >> If I understand correctly, you are saying that I should have
> >> specified IRQ_TYPE_LEVEL_LOW, instead of IRQ_TYPE_LEVEL_HIGH?
> >>
> >> If the HW outputs 1 when idle, and 0 when busy, that
> >> is level low? (Sorry if this is obvious, I'm absolutely
> >> clueless in this subject matter.)
> >
> > We describe the level which is raising the interrupt. So in your case the
> > line goes to 0 when the interrupt is active, so the level is LOW.
>
> I see. I'll try that on Monday.
>
> In my mental picture of interrupts (which is obviously so
> incomplete as to be wrong) interrupts are a way for hardware
> to tell the CPU that they urgently need the CPU's attention.
That's how the CPU interprets it, but this is even more basic than
that, see below.
> Obviously, the hardware being idle (line high) is not an urgent
> matter which interests the CPU. Likewise, I'm not sure the CPU
> cares that the hardware is busy (line low). It seems to me the
> interesting event from the CPU's perspective is when the
> hardware completes a "task" (transition from low to high).
There is no such thing as "busy" when it comes to interrupts. An
interrupt signals the CPU that some device-specific condition has been
satisfied. It could be "I've received a packet" or "Battery is about to
explode", depending if the device is a network controller or a
temperature sensor. The interrupt doesn't describe the process that
leads to that condition (packet being received or temperature rising),
but the condition itself.
In your cases, as the device seems to do some form of processing
(you're talking about task completion), then the interrupt seems to
describe exactly this ("I'm done").
> So I had originally configured the interrupt as IRQ_TYPE_EDGE_RISING.
> (There is an edge detection block in the irqchip, but the HW designer
> warned me that at low frequencies, it is possible to "miss" some edges,
> and we should prefer level triggers if possible.)
Level and edge are not interchangeable. They do describe very different
thing:
- Level indicates a persistent state, which implies that the device
needs to be serviced so that this condition can be cleared (the UART
has received a character, and won't be able to received another until
it has been read by the CPU). Once the device has been serviced and
that condition cleared, it will lower its interrupt line.
- Edge is indicative of an event having occurred ("I'm done") that
doesn't require any action from the CPU. Because the device can
continue its life without being poked by the CPU, it can continue
delivering interrupts even if the first one hasn't been serviced.
Being edge triggered, the signals get coalesced into a single
interrupt. For example, the temperature sensor will say "Temperature
rising" multiple times before the battery explodes, and it is the
CPU's job to go and read the sensor to find out by how much it has
risen.
If your device only sends a pulse, then it is edge triggered, and it
should be treated as such, no matter what your HW guy is saying. This
usually involves looking at the device to find out how many times the
interrupt has been generated (assuming the device is some kind of
processing element). Of course, this is racy (interrupts can still be
generated whilst you're processing them), and you should design your
interrupt handler to take care of the possible race.
So, to make it short: find out how your device works, and configure
your interrupt controller in a similar way. Write your device driver
with the interrupt policy in mind (state vs event). Keep it simple.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply
* [PATCH v5 7/7] ARM: dts: sun8i-h3: Add HDMI audio and video to the Orange PI 2
From: Jean-Francois Moine @ 2016-10-22 11:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1477142934.git.moinejf@free.fr>
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
The same patch may be applied to other H3 based boards (Orange PI xx).
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index e5bcaba..799ceb9 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -56,6 +56,7 @@
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet1 = &rtl8189;
+ lcd0 = &lcd0;
};
chosen {
@@ -105,16 +106,32 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&lcd0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.10.1
^ permalink raw reply related
* [PATCH v3 3/6] pwm: imx: support output polarity inversion
From: Boris Brezillon @ 2016-10-22 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021234939.1a4f51f4@jawa>
Hi Lukasz,
On Fri, 21 Oct 2016 23:49:39 +0200
Lukasz Majewski <l.majewski@majess.pl> wrote:
> Hi Stefan,
>
> > On 2016-10-20 01:30, Lukasz Majewski wrote:
> > > Hi Stefan,
> > >
> > >> Hi Stefan,
> > >>
> > >> > On 2016-10-12 15:15, Lukasz Majewski wrote:
> > >> > > Hi Stefan,
> > >> > >
> > >> > >> On 2016-10-07 08:11, Bhuvanchandra DV wrote:
> > >> > >> > From: Lothar Wassmann <LW@KARO-electronics.de>
> > >> > >> >
> > >> > >> > The i.MX pwm unit on i.MX27 and newer SoCs provides a
> > >> > >> > configurable output polarity. This patch adds support to
> > >> > >> > utilize this feature where available.
> > >> > >> >
> > >> > >> > Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> > >> > >> > Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> > >> > >> > Signed-off-by: Bhuvanchandra DV
> > >> > >> > <bhuvanchandra.dv@toradex.com> Acked-by: Shawn Guo
> > >> > >> > <shawn.guo@linaro.org> Reviewed-by: Sascha Hauer
> > >> > >> > <s.hauer@pengutronix.de> ---
> > >> > >> > Documentation/devicetree/bindings/pwm/imx-pwm.txt | 6 +--
> > >> > >> > drivers/pwm/pwm-imx.c | 51
> > >> > >> > +++++++++++++++++++++-- 2 files changed, 51 insertions(+), 6
> > >> > >> > deletions(-)
> > >> > >> >
> > >> > >> > diff --git
> > >> > >> > a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > >> > >> > b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index
> > >> > >> > e00c2e9..c61bdf8 100644 ---
> > >> > >> > a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++
> > >> > >> > b/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -6,8
> > >> > >> > +6,8 @@ Required properties:
> > >> > >> > - "fsl,imx1-pwm" for PWM compatible with the one
> > >> > >> > integrated on i.MX1
> > >> > >> > - "fsl,imx27-pwm" for PWM compatible with the one
> > >> > >> > integrated on i.MX27
> > >> > >> > - reg: physical base address and length of the controller's
> > >> > >> > registers -- #pwm-cells: should be 2. See pwm.txt in this
> > >> > >> > directory for a description of
> > >> > >> > - the cells format.
> > >> > >> > +- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs.
> > >> > >> > See pwm.txt
> > >> > >> > + in this directory for a description of the cells format.
> > >> > >> > - clocks : Clock specifiers for both ipg and per clocks.
> > >> > >> > - clock-names : Clock names should include both "ipg" and
> > >> > >> > "per" See the clock consumer binding,
> > >> > >> > @@ -17,7 +17,7 @@ See the clock consumer binding,
> > >> > >> > Example:
> > >> > >> >
> > >> > >> > pwm1: pwm at 53fb4000 {
> > >> > >> > - #pwm-cells = <2>;
> > >> > >> > + #pwm-cells = <3>;
> > >> > >> > compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
> > >> > >> > reg = <0x53fb4000 0x4000>;
> > >> > >> > clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
> > >> > >> > diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> > >> > >> > index d600fd5..c37d223 100644
> > >> > >> > --- a/drivers/pwm/pwm-imx.c
> > >> > >> > +++ b/drivers/pwm/pwm-imx.c
> > >> > >> > @@ -38,6 +38,7 @@
> > >> > >> > #define MX3_PWMCR_DOZEEN (1 << 24)
> > >> > >> > #define MX3_PWMCR_WAITEN (1 << 23)
> > >> > >> > #define MX3_PWMCR_DBGEN (1 << 22)
> > >> > >> > +#define MX3_PWMCR_POUTC (1 << 18)
> > >> > >> > #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> > >> > >> > #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> > >> > >> > #define MX3_PWMCR_SWR (1 << 3)
> > >> > >> > @@ -180,6 +181,9 @@ static int imx_pwm_config_v2(struct
> > >> > >> > pwm_chip *chip, if (enable)
> > >> > >> > cr |= MX3_PWMCR_EN;
> > >> > >> >
> > >> > >> > + if (pwm->args.polarity == PWM_POLARITY_INVERSED)
> > >> > >> > + cr |= MX3_PWMCR_POUTC;
> > >> > >> > +
> > >> > >>
> > >> > >> This seems wrong to me, the config callback is meant for
> > >> > >> period/duty cycle only.
> > >
> > > Unfortunately, it also resets the PWM IP block and setups it again
> > > (by writing to PWMCR register).
Well, this is an implementation problem. If you were reading the
MX3_PWMCR register and masking it with MX3_PWMCR_POUTC to keep the
value set by ->set_polarity() that wouldn't be a problem.
> > > In that function we setup for
> > > example MX3_PWMCR_DOZEEN
> > > and MX3_PWMCR_DBGEN. Why cannot we setup polarity as well?
I think there's no real problem in setting the polarity again in
->config(), it's just that it feels weird to have it set twice (in
->set_polarity() and in ->config()).
> > >
> > >
> > > I've double checked the backlight and pwm code flow.
> > >
> > > Please find following snippet:
> > >
> > > [ 0.135545] ######### imx_pwm_probe
> > > [ 0.135581] PWM supports output inversion
> > > [ 0.136864] ######### pwm_backlight_probe
> > > [ 0.136913] backlight supply power not found, using dummy
> > > regulator [ 0.136984] ######### imx_pwm_set_polarity 1
> > > [ 0.136995] imx_pwm_set_polarity: polarity set to inverted cr:
> > > 0x40000 0xf08f8000
> > > [ 0.137005] #########0 imx_pwm_config_v2 cr: 0x40000
> > > [ 0.137683] #########1 imx_pwm_config_v2 cr: 0x0 0xf08f8000
> > > [ 0.137693] #########2 imx_pwm_config_v2 cr: 0x1c20050
> > > [ 0.137702] #########3 imx_pwm_config_v2 cr: 0x1c20050 0xf08f8000
> > > [ 0.137711] @@@@@@@@@@ pwm_apply_state
>
> Maybe a bit more logs:
>
> [ 0.135451] ######### imx_pwm_probe
> [ 0.135488] PWM supports output inversion
> [ 0.136777] ######### pwm_backlight_probe
> [ 0.136826] backlight supply power not found, using dummy regulator
> [ 0.136893] ********* pwm_apply_state state->enabled: 0
> [ 0.136902] ######### imx_pwm_set_polarity 1
> [ 0.136913] imx_pwm_set_polarity: polarity set to inverted cr: 0x40000 0xf08f8000
> [ 0.136923] #########0 imx_pwm_config_v2 cr: 0x40000
> [ 0.137692] #########1 imx_pwm_config_v2 cr: 0x0 0xf08f8000
> [ 0.137701] #########2 imx_pwm_config_v2 cr: 0x1c20050
> [ 0.137710] #########3 imx_pwm_config_v2 cr: 0x1c20050 0xf08f8000
> [ 0.137720] @@@@@@@@@@ pwm_apply_state
> [ 0.137856] ********* pwm_apply_state state->enabled: 0
> [ 0.137869] #########0 imx_pwm_config_v2 cr: 0x1c20050
> [ 0.138904] #########1 imx_pwm_config_v2 cr: 0x0 0xf08f8000
> [ 0.138913] #########2 imx_pwm_config_v2 cr: 0x1c20050
> [ 0.138921] #########3 imx_pwm_config_v2 cr: 0x1c20050 0xf08f8000
> [ 0.138928] @@@@@@@@@@ pwm_apply_state
> [ 0.138940] ********* pwm_apply_state state->enabled: 1
> ^^^^^^^^^^^^^^^^^^ this is called from
> pwm_backlight_power_on() from pwm_bl probe function
>
> The problem here is not the lack of ->apply() callback, but the requirement to
> perform software reset on the pwm_v2 fifo when the pwm_v2 is NOT enabled (state->enabled: 0).
Not sure what a PWM fifo is, or which software reset you are talking
about. If you're talking about the disable()+set_polarity()+enable()
dance, then, this is required by some PWM controllers which do not
support changing the PWM polarity while the PWM is running.
>
> As fair as I can see the pwm_state has following members: period, duty cycle, polarity and enabled.
> I'm fine to implement ->apply() callback, which would change above values.
>
> However, there is a problem with ->config() (imx_pwm_config_v2 @ pwm-imx.c) and imx pwm_v2 software
> FIFO reset.
->config() will not be used if you implement ->apply(), and ->apply()
should take care of all the nasty details that should be taken care of
on your PWM controller.
Say for example that you need to disable the PWM before changing the
polarity, then your ->apply() function should check if the PWM is
enabled, if that's the case it should disable it, set the new polarity,
possibly re-apply the period and duty config and finally re-enable the
PWM.
> We can set polarity in any other kernel subsystem, which uses PWM (backlight in this example) and
> then this setting would disappear when we call pwm_apply_state with state->enabled = 0 (as presented
> in the log). This imposes setting polarity at ->config when we enable the PWM (as this patch does).
That's really a driver problem, not a PWM user or PWM core problem. If
you have to take extra precautions when enabling the PWM (like
re-applying the polarity), then you can do that in your ->apply()
implementation.
>
>
>
> > >
> > > Here the pwm_backlight_probe calls set_polarity callback available
> > > in pwm - the polarity is set (the 0x40000 value).
> > >
> > > The above operation is performed in pwm_apply_state (@
> > > drivers/pwm/core.c). In the same function, latter we call the
> > > pwm->chip->ops->config(), which is the pointer to config_v2.
> > > Since the PWM is not yet enabled, this function performs SW reset
> > > and PWM inversion setting is cleared.
> >
> > That function should not do that.
>
> I do agree that it shouldn't. Correct me if I'm wrong, but it seems like an
> PWM HW requirement to perform the reset.
>
> >It was probably already problematic
> > in the old times, it is definitely now with the atomic PWM stuff.
>
> The "atomic"[*] code (with ->apply() provided) will not solve this issue.
Of course it will solve the problem, because in ->apply() you're passed
all the information you need, and if you have to re-apply the polarity
setting, you can (which was not the case with the old pwm_ops
interface).
>
> >
> > >
> > > Possible solutions:
> > >
> > > 1. Leave the original patch from Bhuvanchandra as it was (I'm for
> > > this option)
> >
> > That really seems like a hack to me, and makes transition to the
> > atomic PWM API more complex.
>
> Could you be more specific here?
>
> As I mentioned before, the problem is not with the lack of
> "atomic" API.
And I really think it is.
>
> For me the problem is with other subsystems (like pwm backlight)
> which do require polarity inversion to work properly.
Nope, it's just that, with the old pwm_ops interface, your driver was
not able to apply things in the right order. With the ->apply() it can.
>
> >
> > If we can't make it happen properly in the current state of affairs,
>
> We can set polarity properly with this patch. The only thing which needs fixing
> and another revision of the patch) is the removal of condition:
>
> - if (polarity == pwm->args.polarity)
> - return 0;
>
> at imx_pwm_set_polarity() function.
Yes, you can probably add even more hacks, but as Stefan said, it's
probably better to switch to the atomic interface, because by doing you
would greatly simplify the logic.
>
> > we probably should first move to the atomic API.
> >
> > It really should not be that hard, since we already do almost
> > everything in one function (imx_pwm_config_v2). We probably can
> > almost just assign that function to the new apply function pointer
> > and read information from the new state struct.
>
> We do need to configure polarity according to DT value during the pwm
> config_v2 configuration after PWM IP software reset.
And again, forget about ->config(), it should not be called if you
implement ->apply() (actually, you should even drop it completely). So
really, you should try implementing ->apply() and see what happens.
>
> >
> > There are examples for instance here:
> > https://patchwork.kernel.org/patch/7228221/
>
> The atomicity[*]:
>
> - It seems to me that this "atomicity" is just embracing all the ->enable, ->disable
> and ->set_polarity in one -> apply callback. Is this just conceptual clean up or is
> there any other reason for it (I'm just curious) ?
No, it's not just a conceptual cleanup. Some hardware are capable of
updating the PWM config atomically (which means they will update the
config at the end of the current period cycle), and by doing that we
also prevent any glitches on the PWM signal.
With the old API, this was simply impossible to do, because the
enable/disable, set_polarity and config calls were separated. With the
atomic API, we can.
Now, let's say your controller is not guaranteeing atomicity. It's
still interesting to implement the ->apply() function, because this way
you can handle all those complex sequences that are required on some HW.
To sum-up, I really think you should listen to Stefan and try to
implement the atomic hook (AKA ->apply()).
Regards,
Boris
^ permalink raw reply
* [PATCH v3 3/6] pwm: imx: support output polarity inversion
From: Boris Brezillon @ 2016-10-22 10:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161007151129.6043-4-bhuvanchandra.dv@toradex.com>
On Fri, 7 Oct 2016 20:41:26 +0530
Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> wrote:
> From: Lothar Wassmann <LW@KARO-electronics.de>
>
> The i.MX pwm unit on i.MX27 and newer SoCs provides a configurable output
> polarity. This patch adds support to utilize this feature where available.
>
> Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> Documentation/devicetree/bindings/pwm/imx-pwm.txt | 6 +--
> drivers/pwm/pwm-imx.c | 51 +++++++++++++++++++++--
> 2 files changed, 51 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> index e00c2e9..c61bdf8 100644
> --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> @@ -6,8 +6,8 @@ Required properties:
> - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1
> - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27
> - reg: physical base address and length of the controller's registers
> -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
> - the cells format.
> +- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.txt
> + in this directory for a description of the cells format.
> - clocks : Clock specifiers for both ipg and per clocks.
> - clock-names : Clock names should include both "ipg" and "per"
> See the clock consumer binding,
> @@ -17,7 +17,7 @@ See the clock consumer binding,
> Example:
>
> pwm1: pwm at 53fb4000 {
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
> reg = <0x53fb4000 0x4000>;
> clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index d600fd5..c37d223 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -38,6 +38,7 @@
> #define MX3_PWMCR_DOZEEN (1 << 24)
> #define MX3_PWMCR_WAITEN (1 << 23)
> #define MX3_PWMCR_DBGEN (1 << 22)
> +#define MX3_PWMCR_POUTC (1 << 18)
> #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> #define MX3_PWMCR_SWR (1 << 3)
> @@ -180,6 +181,9 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
> if (enable)
> cr |= MX3_PWMCR_EN;
>
> + if (pwm->args.polarity == PWM_POLARITY_INVERSED)
> + cr |= MX3_PWMCR_POUTC;
> +
> writel(cr, imx->mmio_base + MX3_PWMCR);
>
> return 0;
> @@ -240,27 +244,62 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> clk_disable_unprepare(imx->clk_per);
> }
>
> -static struct pwm_ops imx_pwm_ops = {
> +static int imx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
> + enum pwm_polarity polarity)
> +{
> + struct imx_chip *imx = to_imx_chip(chip);
> + u32 val;
> +
> + if (polarity == pwm->args.polarity)
> + return 0;
> +
> + val = readl(imx->mmio_base + MX3_PWMCR);
> +
> + if (polarity == PWM_POLARITY_INVERSED)
> + val |= MX3_PWMCR_POUTC;
> + else
> + val &= ~MX3_PWMCR_POUTC;
> +
> + writel(val, imx->mmio_base + MX3_PWMCR);
> +
> + dev_dbg(imx->chip.dev, "%s: polarity set to %s\n", __func__,
> + polarity == PWM_POLARITY_INVERSED ? "inverted" : "normal");
> +
> + return 0;
> +}
I'll read the discussion Lukasz and Stefan had before reviewing this
part ;-).
> +
> +static struct pwm_ops imx_pwm_ops_v1 = {
> .enable = imx_pwm_enable,
> .disable = imx_pwm_disable,
> .config = imx_pwm_config,
> .owner = THIS_MODULE,
> };
>
> +static struct pwm_ops imx_pwm_ops_v2 = {
> + .enable = imx_pwm_enable,
> + .disable = imx_pwm_disable,
> + .set_polarity = imx_pwm_set_polarity,
> + .config = imx_pwm_config,
> + .owner = THIS_MODULE,
> +};
> +
> struct imx_pwm_data {
> int (*config)(struct pwm_chip *chip,
> struct pwm_device *pwm, int duty_ns, int period_ns);
> void (*set_enable)(struct pwm_chip *chip, bool enable);
> + struct pwm_ops *pwm_ops;
Probably better to make that consistent: drop the ->config() and
->set_enable() hooks, and make both v1 and v2 define their own pwm_ops.
If you have common logic that is shared between v1 and v2, you can just
create helper functions implementing this common logic and call them
from your version-specific implementation.
> };
>
> static struct imx_pwm_data imx_pwm_data_v1 = {
> .config = imx_pwm_config_v1,
> .set_enable = imx_pwm_set_enable_v1,
> + .pwm_ops = &imx_pwm_ops_v1,
> };
>
> static struct imx_pwm_data imx_pwm_data_v2 = {
> .config = imx_pwm_config_v2,
> .set_enable = imx_pwm_set_enable_v2,
> + .pwm_ops = &imx_pwm_ops_v2,
> };
>
> static const struct of_device_id imx_pwm_dt_ids[] = {
> @@ -282,6 +321,8 @@ static int imx_pwm_probe(struct platform_device *pdev)
> if (!of_id)
> return -ENODEV;
>
> + data = of_id->data;
> +
> imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
> if (imx == NULL)
> return -ENOMEM;
> @@ -300,18 +341,22 @@ static int imx_pwm_probe(struct platform_device *pdev)
> return PTR_ERR(imx->clk_ipg);
> }
>
> - imx->chip.ops = &imx_pwm_ops;
> + imx->chip.ops = data->pwm_ops;
> imx->chip.dev = &pdev->dev;
> imx->chip.base = -1;
> imx->chip.npwm = 1;
> imx->chip.can_sleep = true;
> + if (data->pwm_ops->set_polarity) {
> + dev_dbg(&pdev->dev, "PWM supports output inversion\n");
> + imx->chip.of_xlate = of_pwm_xlate_with_flags;
> + imx->chip.of_pwm_n_cells = 3;
> + }
Not that I really care, but you are breaking the DT ABI here. One
solution to avoid that would be to retrieve #pwm-cells here and
decide which ->of_xlate should be used based on this information.
>
> r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
> if (IS_ERR(imx->mmio_base))
> return PTR_ERR(imx->mmio_base);
>
> - data = of_id->data;
> imx->config = data->config;
> imx->set_enable = data->set_enable;
>
^ permalink raw reply
* [PATCH v5 6/7] ARM: dts: sun8i-h3: Add HDMI audio and video to the Banana Pi M2+
From: Jean-Francois Moine @ 2016-10-22 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1477142934.git.moinejf@free.fr>
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
The patch for the Banana Pi M3 (A83T) is the same as this one.
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index 06fddaa..2e81de8 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -55,6 +55,7 @@
aliases {
serial0 = &uart0;
serial1 = &uart1;
+ lcd0 = &lcd0;
};
chosen {
@@ -93,6 +94,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -101,12 +106,24 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&lcd0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.10.1
^ permalink raw reply related
* [PATCH] i2c: rk3x: Give the tuning value 0 during rk3x_i2c_v0_calc_timings
From: David Wu @ 2016-10-22 8:43 UTC (permalink / raw)
To: linux-arm-kernel
We found a bug that i2c transfer sometimes failed on 3066a board with
stabel-4.8, the con register would be updated by uninitialized tuning
value, it made the i2c transfer failed.
So give the tuning value to be zero during rk3x_i2c_v0_calc_timings.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
drivers/i2c/busses/i2c-rk3x.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 50702c7..df22066 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -694,6 +694,8 @@ static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
t_calc->div_low--;
t_calc->div_high--;
+ /* Give the tuning value 0, that would not update con register */
+ t_calc->tuning = 0;
/* Maximum divider supported by hw is 0xffff */
if (t_calc->div_low > 0xffff) {
t_calc->div_low = 0xffff;
--
1.9.1
^ permalink raw reply related
* [PATCH/RFC 4/4] soc: renesas: Identify SoC and register with the SoC bus
From: Geert Uytterhoeven @ 2016-10-22 7:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <12094567.68HcWl4d5O@wuerfel>
Hi Arnd,
On Fri, Oct 21, 2016 at 11:16 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday, October 21, 2016 8:16:00 PM CEST Geert Uytterhoeven wrote:
>> On Wed, Oct 19, 2016 at 12:59 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> > On Wednesday, October 19, 2016 10:02:57 AM CEST Geert Uytterhoeven wrote:
>> >> On Mon, Oct 10, 2016 at 4:23 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> > I'd prefer seeing a separate soc driver for that one.
>> >> Some SoCs have only CCCR, others have only PRR, some have both.
>> >> On some SoCs one of them can be accessed from the RealTime CPU
>> >> core (SH) only.
>> >> On some SoCs the register is not documented, but present.
>> >> If the PRR exists, it's a better choice, as it contains additional information
>> >> in the high order bits (representing the presence of each big (CA15/CA57),
>> >> little (CA7/CA53), and RT (CR7) CPU core). Currently we don't use that
>> >> information, though.
>> >>
>> >> Grouping them in some other way means we would loose the family name,
>> >> which is exposed through soc_dev_attr->family.
>> >> The usefulness of family names is debatable though, as this is more an
>> >> issue of marketing business.
>> >
>> > How about having a table to look up the family name by the value
>> > of the PRR or CCCR then?
>>
>> Unfortunately there exist SoCs from different families using the same
>> product ID.
>>
>> And different SoCs from the same family may have a revision register
>> or not (e.g. R-Car H1 has, M1A hasn't).
>
> Is this something we expect to see more of in the future, or can
> we expect future chips to handle this more consistently?
I expect to see more of these in the future.
Perhaps I just should forget about the product IDs and (marketing) families,
and just stick the CCCR/PRR addresses in the of_device_ids?
Then we'll have SoC names (e.g. "r8a7791") and (optional) revisions
(e.g. "ES1.0") to match on.
>> > How about this:
>> >
>> > The driver could report the hardcoded strings for the SoCs it already
>> > knows about (you have the table anyway) and not report the revision
>> > unless there is a regmap containing the CCCR or the PRR, in which
>> > case you use that. Future SoCs will provide the PRR (I assume
>> > CCCR is only used on the older ones) through a syscon regmap
>> > that we can use to find out the exact revision as well.
>> >
>> > The existing DT files can gain the syscon device so you can report
>> > the revision on those machines as well, unless you use an old DTB.
>>
>> Hmm... That means that if we have to add a driver quirk to distinguish
>> between different revisions of the same SoC, we have to update the
>> DTB anyway, to add the CCCR/PRR device node.
>> We might as well just change the compatible value in that DTB for the
>> device that needs the quirk. Which is what we'd like to avoid in the
>> first place.
>
> Do you have a specific example in mind? If this is only a theoretical
> problem, we can worry about it when we get there, and then decide
> if we add a hardcoded register after all.
For R-Car H3, there are small differences between ES1.0 and ES1.1,
and more and larger differences between ES1.x and ES2.0, which
need different handling (patches already floating around).
For (old) R-Car H1, the SATA driver already handles "renesas,sata-r8a7790-es1",
but so far there didn't exist an established process to specify how that
compatible value would end up in the DTB (the in-kernel DTS doesn't have it).
There may be more differences I'm not aware of.
>> > Why not just drop all the #ifdef here? There should be very little
>> > overhead in size, especially if all the data is __initconst.
>>
>> It still saves ca. 3 KiB for a kernel for a single SoC.
>
> Fair enough, that is more than I was expecting from looking at the
> source. It's probably the of_device_id structures for the most part.
Yep, ca. 200 bytes per ID.
> Please just add the __maybe_unused then, to save us a patch in case
> we make -Wunused-const the default in the future.
Sure.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] iommu: arm-smmu-v2: Enable 16 bit ASID
From: Geetha sowjanya @ 2016-10-22 5:02 UTC (permalink / raw)
To: linux-arm-kernel
Support up to 16 bit ASID. This patch enables
16 bit ASID when supported.
Signed-off-by: Geetha sowjanya <gakula@cavium.com>
Acked-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
---
drivers/iommu/arm-smmu.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index c841eb7..9740846 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -258,6 +258,9 @@ enum arm_smmu_s2cr_privcfg {
#define TTBCR2_SEP_SHIFT 15
#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
+#define TTBCR2_AS_SHIFT 4
+#define TTBCR2_AS_ENABLE (1 << TTBCR2_AS_SHIFT)
+
#define TTBRn_ASID_SHIFT 48
#define FSR_MULTI (1 << 31)
@@ -773,6 +776,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
reg2 |= TTBCR2_SEP_UPSTREAM;
+ /* Enable 16 bit ASID if 16 bit VMID is supported */
+ if (smmu->features & ARM_SMMU_FEAT_VMID16)
+ reg |= TTBCR2_AS_ENABLE;
}
if (smmu->version > ARM_SMMU_V1)
writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
--
1.7.1
^ permalink raw reply related
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