* Add Allwinner Q8 tablets hardware manager
From: Hans de Goede @ 2016-10-27 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9B288597-7812-459D-A5C7-B61107751DA6@konsulko.com>
Hi,
On 27-10-16 17:52, Pantelis Antoniou wrote:
> Hi Hans,
<snip>
>> Right, so again I think we need to split the discussion in 2 steps:
>>
>> 1) How do we apply the fixups, currently I'm using free-form changes
>> done from C-code. I can envision moving to something like the quirk
>> mechanism suggested by Pantelis in the past. Note this is not a perfect
>> fit for my rather corner-case use-case, but I can understand that in
>> general you want the variants to be described in dt, and activated
>> in some way, rather then have c-code make free-form changes to the dt
>>
>
> We?ve had this discussion before, so I guess here it goes again.
>
> I think the biggest objection is the programmatic way of applying
> every quirk by ?hand?.
>
> If there was a way to keep the probing mechanism but just spit out
> a ?model? number we could reasonably map it to an overlay to apply
> with a generic overlay manager.
>
> From an internal s/w standpoint having an expansion board or soldered
> parts makes no difference.
I disagree, with soldered parts it often is the board has
one of "accelerometer a", "b" or "c", where in the simple case
my suggested i2c-probe-stop-at-first-match property will
just work for a new board by creating a new dtb without needing any
kernel changes, where as your suggested model-string generator
C-code module would need updating.
I think that there is a need for both really.
>> 2) How do we select which fixups to apply. Again I can understand
>> you wanting some well defined mechanism for this, but again my
>> use-case is special and simply does not allow for this as there
>> is no id-eeprom to read or some such.
>>
>
> Yes there is no EEPROM but you might be able to map probing results to
> a fake ?model? number.
>
> Let me expand a bit:
>
> Assume that you have a number of probing steps, for example A, B, C each
> returning true or false, and C being executed only when B is ?true? you
> could do this to generate a bit field that identifies it.
>
> For example let?s assume that model FOO?s probing steps are
>
> A false, B true, C false -> 010
>
> Model?s BAR
>
> A true, B false, C don?t care -> 10x
>
> Mapping these to models could be
>
> Model FOO, (010 & 111) == 010 (all three probing steps must match)
>
> Model BAR, (10x & 110) = 100 (the first two probing steps must match)
Interesting this is actually the same direction my thoughts on this
lead me in my reply in the other thread on this started by
Antoine Tenart.
Only difference is that I suggested putting the model-string
generation in the bootloader, so it will just be there when the kernel
boots. But I agree that given things like upgradability having
the model-string generation code in the kernel is better.
<snip>
Regards,
Hans
^ permalink raw reply
* Add Allwinner Q8 tablets hardware manager
From: Hans de Goede @ 2016-10-27 21:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJ-oXjRJrs77yE-skpZ-V4e=rdhRyfNve9bibf1VOaZYy2=tRA@mail.gmail.com>
Hi,
On 27-10-16 19:31, Pierre-Hugues Husson wrote:
> 2016-10-27 16:53 GMT+02:00 Hans de Goede <hdegoede@redhat.com>:
<snip>
>> We could just have:
>>
>> i2c-probe-stop-at-first-match-0 = <&touchscreen1>, <&touchscreen2>,
>> <&touchscreen3>;
>> i2c-probe-stop-at-first-match-1 = <&accelerometer1>,
>> <&accelerometer2>;
>>
>> And have the i2c bus code look for an i2c-probe-stop-at-first-match-[i++]
>> property
>> until it is not found. Having a child-node with its own compatible for this
>> feels wrong, as it uses a hierarchy where there really is none.
> Ok, looks much better indeed.
> I had one case where accelerometers could be on either i2c1 or i2c5.
> Do you think this could be handled as well, or this makes things much
> more complicated to fit in the i2c driver?
Handling that is easy, just add a i2c-probe-stop-at-first-match to
both busses (with separate child nodes to be probed under each bus),
the on one bus the probe-code will just read the end of the list
and stop, I believe we should not treat that as an error anyways
(even if there is only 1 bus).
>
>> So this would require us to be able to filter (to use your example)
>> on if another i2c device is found and on which address it is found,
>> that does not even take the rda559x check into account and is
>> going to cause interesting ordering issues, how do we know when
>> we can actually do the filtering if some of the variables we are
>> filtering on are set by other auto-detected paths. Which auto-detect /
>> i2c-probe-stop-at-first-match list do we execute first ? Worse
>> actually for accelerometer orientation I will likely need to
>> set the mount-matrix based on the detected touchscreen ...
>>
>> The rda559x here is a sdio wifi chip, which is also connected to the
>> i2c, and currently is detected through i2c to be able to separately
>> identify 2 q8 boards which share the same touchscreen + accelerometer
>> combination and who knows what other checks I or other people can
>> come up with to differentiate board variants which do not have
>> a simple eeprom to uniquely id them.
>>
>> So as said before, no this cannot be all done in dt without
>> adding a turing complete language to dt, and that is just to
>> select which touchscreen_variant to use.
> Ok, now that I understand the scope of your needs.
> I agree with you, this needs a (close to) turing complete language.
> I'm still not really happy about doing it in a driver, but I agree the
> full scope you need is scarce enough.
> Assuming this is done in a driver, there would need to be some
> plumbing between i2c-probe-stop-at-first-match, device's probe
> function and your driver, so that your driver only does the various
> if/cases and DT changes, but there is no actual device communication
> done in that driver.
Ah, no I meant dealing with this in the actual device driver,
not in some special intermediate driver, just like the actual x86
device drivers (sometimes) apply quirks based on board DMI strings.
<snip>
Regards,
Hans
^ permalink raw reply
* [PATCH] drivers: mfd: ti_am335x_tscadc: increase ADC ref clock to 24MHz
From: John Syne @ 2016-10-27 21:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161026084811.GI8574@dell>
>
> On Oct 26, 2016, at 1:48 AM, Lee Jones <lee.jones@linaro.org> wrote:
>
> On Tue, 25 Oct 2016, John Syne wrote:
>>> On Oct 24, 2016, at 11:38 PM, Lee Jones <lee.jones@linaro.org> wrote:
>>> On Mon, 24 Oct 2016, John Syne wrote:
>>>>> On Oct 24, 2016, at 11:01 PM, John Syne <john3909@gmail.com> wrote:
>>>>>> On Oct 24, 2016, at 10:52 PM, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>>>>>>
>>>>>> On Tuesday 25 October 2016 02:28 AM, John Syne wrote:
>>>>>>>>> On Oct 23, 2016, at 11:02 PM, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>>>>>>>>>
>>>>>>>>> Increase ADC reference clock from 3MHz to 24MHz so that the
>>>>>>>>> sampling rates goes up from 100K samples per second to 800K
>>>>>>>>> samples per second on AM335x and AM437x SoC.
>>>>>>>>>
>>>>>>>>> Also increase opendelay for touchscreen configuration to
>>>>>>>>> equalize the increase in ADC reference clock frequency,
>>>>>>>>> which results in the same amount touch events reported via
>>>>>>>>> evtest on AM335x GP EVM.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>>>>>>>>> ---
>>>>>>>>>
>>>>>>>>> This patch depends on ADC DMA patch series [1]
>>>>>>>>>
>>>>>>>>> Without DMA support, when ADC ref clock is set at 24MHz, I am
>>>>>>>>> seeing fifo overflow as CPU is not able to pull the ADC samples.
>>>>>>>>> This answers that DMA support is must for ADC to consume the
>>>>>>>>> samples generated at 24MHz with no open, step delay or
>>>>>>>>> averaging with patch [2].
>>>>>>>>>
>>>>>>>>> Measured the performance with the iio_generic_buffer with the
>>>>>>>>> patch [3] applied
>>>>>>>>>
>>>>>>>>> [1] - http://www.spinics.net/lists/devicetree/msg145045.html
>>>>>>>>> [2] - http://pastebin.ubuntu.com/23357935/
>>>>>>>>> [3] - http://pastebin.ubuntu.com/23357939/
>>>>>>>>>
>>>>>>>>> ---
>>>>>>>>> include/linux/mfd/ti_am335x_tscadc.h | 4 ++--
>>>>>>>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
>>>>>>>>> index b9a53e0..96c4207 100644
>>>>>>>>> --- a/include/linux/mfd/ti_am335x_tscadc.h
>>>>>>>>> +++ b/include/linux/mfd/ti_am335x_tscadc.h
>>>>>>>>> @@ -90,7 +90,7 @@
>>>>>>>>> /* Delay register */
>>>>>>>>> #define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
>>>>>>>>> #define STEPDELAY_OPEN(val) ((val) << 0)
>>>>>>>>> -#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
>>>>>>> Wouldn?t this be better to add this to the devicetree?
>>>>>>>
>>>>>>> ti,chan-step-avg = <0x16 0x16 0x16 0x16 0x16 0x16 0x16>;
>>>>>>> ti,chan-step-opendelay = <0x500 0x500 0x500 0x500 0x500 0x500 0x500>;
>>>>>>> ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
>>>>>>
>>>>>> For a touch screen, there is not need to change in these parameter
>>>>>> settings, so my opinion is to keep it as is. Or am I missing something?
>>>>> I was thinking that if you are using this driver as an ADC, you may want the flexibility to make these changes in the DT. I?m doing this by connecting sensors to the ADC inputs. I?m not using this driver for a touchscreen.
>>>>
>>>> Here is a DT overlay were this gets using on the BeagleBoneBlack.
>>>>
>>>> https://github.com/RobertCNelson/bb.org-overlays/blob/master/src/arm/BB-ADC-00A0.dts
>>>>
>>>> Besides, these DT features are already implemented in the driver so it is just a matter of adding these entries to the am33xx.dtsi & am4372.dtsi, which you modified in this patch series.
>>>
>>> This looks like configuration, no?
>>>
>>> DT should be used to describe the hardware.
>> You may be right, but how is this different to setting the baud rate on a serial channel or sampling rate on a audio channel? Looking through the DT, there are many configuration settings, so I?m not sure what is the correct way to handle this. Surely it is better to handle this in DT vs hard coding these settings?
>
> I think setting the UART baud rate is also an invalid DT entry.
>
> It's okay to list all of the options in DT, but to actually select
> one, that should be done either in userspace or as a kernel option.
> Perhaps as a Kconfig selection.
Yeah, this has been inconsistent for a long time. My only point was that these DT parameters had already been implemented in the ti_am335x_adc KM and I thought that this was better than hard coding these settings. Implementing this in Kconfig means rebuilding the KM, which isn?t desirable. Perhaps this should be done via sysfs attributes so as you say, a userspace app can configure this driver. I guess the DT code in ti_am335x_adc.c should be removed.
Regards,
John
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 2/5] Documentation: devicetree: net: add NS2 bindings to amac
From: Jon Mason @ 2016-10-27 21:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027091757.GC12841@lunn.ch>
On Thu, Oct 27, 2016 at 11:17:57AM +0200, Andrew Lunn wrote:
> On Wed, Oct 26, 2016 at 03:35:58PM -0400, Jon Mason wrote:
> > Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> > ---
> > Documentation/devicetree/bindings/net/brcm,amac.txt | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt
> > index ba5ecc1..f92caee 100644
> > --- a/Documentation/devicetree/bindings/net/brcm,amac.txt
> > +++ b/Documentation/devicetree/bindings/net/brcm,amac.txt
> > @@ -2,15 +2,18 @@ Broadcom AMAC Ethernet Controller Device Tree Bindings
> > -------------------------------------------------------------
> >
> > Required properties:
> > - - compatible: "brcm,amac" or "brcm,nsp-amac"
> > + - compatible: "brcm,amac", "brcm,nsp-amac", or "brcm,ns2-amac"
> > - reg: Address and length of the GMAC registers,
> > Address and length of the GMAC IDM registers
> > + Address and length of the NIC Port Manager registers (optional)
> > - reg-names: Names of the registers. Must have both "amac_base" and
> > - "idm_base"
> > + "idm_base". "nicpm_base" is optional (required for NS2)
> > - interrupts: Interrupt number
> >
> > Optional properties:
> > - mac-address: See ethernet.txt file in the same directory
> > +- brcm,enet-phy-lane-swap:
> > + boolean; Swap the PHY lanes (needed on some SKUs of NS2)
>
> Maybe i'm missing something here, but the patch to the PHY swapped the
> lanes. This seems to be a PHY property, not a MAC property. And it
> swapped them unconditionally....
It swapped them based on (from patch 1/5)
if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 &&
phydev->dev_flags & PHY_BRCM_EXP_LANE_SWAP)
That flag is being set in the driver based on whether the lanes need
to be swapped (which depends on the SKU of NS2). The only SKU of NS2
we have upstream right now has it swapped, but one that should be
pushed out in the next few weeks will not have this flag present.
There is no way to detect it, and having a separate compat string
seemed overkill.
Thanks,
Jon
>
> Andrew
^ permalink raw reply
* [kernel-hardening] Re: [PATCH v3 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
From: Kees Cook @ 2016-10-27 21:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027145450.GB3762@e104818-lin.cambridge.arm.com>
On Thu, Oct 27, 2016 at 7:54 AM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Fri, Sep 30, 2016 at 11:42:02AM -0700, Kees Cook wrote:
>> On Thu, Sep 29, 2016 at 3:44 PM, Sami Tolvanen <samitolvanen@google.com> wrote:
>> > On Thu, Sep 15, 2016 at 05:20:45PM +0100, Mark Rutland wrote:
>> >> Likewise, how do we handle __flush_cache_user_range and
>> >> flush_icache_range? Some callers (e.g. __do_compat_cache_op) pass in
>> >> __user addresses.
>> >
>> > Also EXEC_USERSPACE in lkdtm passes a user space address to flush_icache_range
>> > and causes the process to hang when I tested these patches on HiKey.
>> >
>> > Adding uaccess_{enable,disable}_not_uao to __flush_cache_user_range appears to
>> > fix the problem.
>>
>> I had a thought just now on this: is lkdtm maybe doing the wrong thing
>> here? i.e. should lkdtm be the one do to the uaccess_en/disable
>> instead of flush_icache_range() itself, since it's the one abusing the
>> API?
>
> (preparing the v4 series)
>
> I think lkdtm is using the API incorrectly here. The documentation for
> flush_icache_range() (Documentation/cachetlb.txt) states that it is to
> be used on kernel addresses. Even with uaccess_enable/disable in lkdtm,
> faults on user space can still happen and the flush_icache_range()
> function must be able to handle them. It happens to work on arm64
> because of the fall through __flush_cache_user_range() but that's not
> guaranteed on other architectures.
>
> A potential solution is to use access_process_vm() and let the arch code
> handle the cache maintenance automatically:
Ah, perfect! I'll give this a spin, thanks!
-Kees
> ---------------------8<--------------------------------
> From fcbb7c9c30daf9bfc2a215ec10dba79c109ab835 Mon Sep 17 00:00:00 2001
> From: Catalin Marinas <catalin.marinas@arm.com>
> Date: Thu, 27 Oct 2016 15:47:20 +0100
> Subject: [PATCH] lkdtm: Do not use flush_icache_range() on user addresses
>
> The flush_icache_range() API is meant to be used on kernel addresses
> only as it may not have the infrastructure (exception entries) to handle
> user memory faults.
>
> The lkdtm execute_user_location() function tests the kernel execution of
> user space addresses by mmap'ing an anonymous page, copying some code
> together with cache maintenance and attempting to run it. However, the
> cache maintenance step may fail because of the incorrect API usage
> described above. The patch changes lkdtm to use access_process_vm() for
> copying the code into user space which would take care of the necessary
> cache maintenance.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
> drivers/misc/lkdtm_perms.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/misc/lkdtm_perms.c b/drivers/misc/lkdtm_perms.c
> index 45f1c0f96612..c7635a79341f 100644
> --- a/drivers/misc/lkdtm_perms.c
> +++ b/drivers/misc/lkdtm_perms.c
> @@ -60,15 +60,18 @@ static noinline void execute_location(void *dst, bool write)
>
> static void execute_user_location(void *dst)
> {
> + int copied;
> +
> /* Intentionally crossing kernel/user memory boundary. */
> void (*func)(void) = dst;
>
> pr_info("attempting ok execution at %p\n", do_nothing);
> do_nothing();
>
> - if (copy_to_user((void __user *)dst, do_nothing, EXEC_SIZE))
> + copied = access_process_vm(current, (unsigned long)dst, do_nothing,
> + EXEC_SIZE, FOLL_WRITE);
> + if (copied < EXEC_SIZE)
> return;
> - flush_icache_range((unsigned long)dst, (unsigned long)dst + EXEC_SIZE);
> pr_info("attempting bad execution at %p\n", func);
> func();
> }
--
Kees Cook
Nexus Security
^ permalink raw reply
* [PATCH 2/5] Documentation: devicetree: net: add NS2 bindings to amac
From: Florian Fainelli @ 2016-10-27 21:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027212106.GA25693@broadcom.com>
On 10/27/2016 02:21 PM, Jon Mason wrote:
> On Thu, Oct 27, 2016 at 11:17:57AM +0200, Andrew Lunn wrote:
>> On Wed, Oct 26, 2016 at 03:35:58PM -0400, Jon Mason wrote:
>>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>>> ---
>>> Documentation/devicetree/bindings/net/brcm,amac.txt | 7 +++++--
>>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt
>>> index ba5ecc1..f92caee 100644
>>> --- a/Documentation/devicetree/bindings/net/brcm,amac.txt
>>> +++ b/Documentation/devicetree/bindings/net/brcm,amac.txt
>>> @@ -2,15 +2,18 @@ Broadcom AMAC Ethernet Controller Device Tree Bindings
>>> -------------------------------------------------------------
>>>
>>> Required properties:
>>> - - compatible: "brcm,amac" or "brcm,nsp-amac"
>>> + - compatible: "brcm,amac", "brcm,nsp-amac", or "brcm,ns2-amac"
>>> - reg: Address and length of the GMAC registers,
>>> Address and length of the GMAC IDM registers
>>> + Address and length of the NIC Port Manager registers (optional)
>>> - reg-names: Names of the registers. Must have both "amac_base" and
>>> - "idm_base"
>>> + "idm_base". "nicpm_base" is optional (required for NS2)
>>> - interrupts: Interrupt number
>>>
>>> Optional properties:
>>> - mac-address: See ethernet.txt file in the same directory
>>> +- brcm,enet-phy-lane-swap:
>>> + boolean; Swap the PHY lanes (needed on some SKUs of NS2)
>>
>> Maybe i'm missing something here, but the patch to the PHY swapped the
>> lanes. This seems to be a PHY property, not a MAC property. And it
>> swapped them unconditionally....
>
> It swapped them based on (from patch 1/5)
> if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 &&
> phydev->dev_flags & PHY_BRCM_EXP_LANE_SWAP)
>
> That flag is being set in the driver based on whether the lanes need
> to be swapped (which depends on the SKU of NS2). The only SKU of NS2
> we have upstream right now has it swapped, but one that should be
> pushed out in the next few weeks will not have this flag present.
> There is no way to detect it, and having a separate compat string
> seemed overkill.
Andrew has a point thought that this is a property that is associated
with the PHY, and not with the Ethernet MAC per se, as such, you can put
it in the Ethernet PHY node, and look up the proper from
drivers/net/phy/broadcom.c, and come up with a Broadcom Ethernet PHY
binding document (sorry).
There is no need to have a specific compatible string allocated, using
the (mostly) generic Ethernet PHY binding, plus this property documented
would be good enough.
--
Florian
^ permalink raw reply
* [PATCH v7] spi: sun4i: Allow transfers larger than FIFO size
From: Maxime Ripard @ 2016-10-27 21:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027111419.GK25322@sirena.org.uk>
Hi Mark,
On Thu, Oct 27, 2016 at 12:14:19PM +0100, Mark Brown wrote:
> On Wed, Oct 26, 2016 at 10:55:28AM +0200, Maxime Ripard wrote:
> > On Wed, Oct 26, 2016 at 12:00:30AM -0700, Alexandru Gagniuc wrote:
>
> > > When DMA finally takes over, this fallback path is not mutually exclusive.
>
> > I definitely agree, and we had this patch in the CHIP kernel for quite
> > some time, working like a charm.
>
> > I was planning to respin it in the next few days, glad to see you took
> > care of it :)
>
> > Mark, any comments on this? For the record, it already has my Acked-by.
>
> Without knowing what the previous discussion was it's hard to comment,
> it sounds like some prior review comments are just being ignored here
> but since I'm not turning up anything with this subject line I've no
> idea what that might have been (and that's very concerning in itself
> given that this is apparently v7...).
v4 was here: https://patchwork.kernel.org/patch/3893371/
v5: https://patchwork.kernel.org/patch/5455381/
v6: https://patchwork.kernel.org/patch/6975871/
So basically, I really have no idea why, but it really seems like it
was just falling through the cracks, repeatedly (I'm not puting the
blame on anyone though, it just happened). Maybe it was just because
of the lack of comments :)
> I'm also concerned that there isn't a version of this for sun6i,
> it's going to make all the cut'n'pasting between the two drivers
> harder if we make changes in one and not the other.
I think I'll give reg_field a shot though, and try to merge the sun6i
driver into this one and see the results. If it can help your
decision.
> If the concern from the previous reviews to do with not using DMA is
> there some reason it's hard to do DMA?
I think just like Alexandru that it is orthogonal. But to really
answer, no, it's not difficult. There's just been some fundamental
disagreement on whether DMA was supposed to be optional or not that
stalled everything I guess.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v5 0/7] Add R8A7743/SK-RZG1M board support
From: Sergei Shtylyov @ 2016-10-27 21:33 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
Here's the set of 7 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161024-v4.9-rc2' tag. I'm adding the device tree support for
the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board
seems identical to the R8A7791/Porter board. The device tree patches depend on
the R8A7743 CPG/MSSR driver series just re-posted in order to compile and work.
Already merged patches from this series won't be re-posted.
[1/7] ARM: dts: r8a7743: initial SoC device tree
[2/7] ARM: dts: r8a7743: add SYS-DMAC support
[3/7] ARM: dts: r8a7743: add [H]SCIF{A|B} support
[4/7] ARM: dts: r8a7743: add Ether support
[5/7] ARM: dts: r8a7743: add IRQC support
[6/7] ARM: dts: sk-rzg1m: initial device tree
[7/7] ARM: dts: sk-rzg1m: add Ether support
WBR, Sergei
^ permalink raw reply
* [PATCH v5 1/7] ARM: dts: r8a7743: initial SoC device tree
From: Sergei Shtylyov @ 2016-10-27 21:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1580369.yToZzJza1l@wasted.cogentembedded.com>
The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 5:
- added the RST device node, updated the patch description accordingly.
Changes in version 4:
- removed the CPU1 node, updated the patch description accordingly;
- reformatted the "interrupts" props of the GIC/timer device nodes;
- added Geert's tag.
Changes in version 3:
- changed the R8A7743 clock header #include;
- replaced the multiple clock nodes with the single CPG node, updated the
"clocks" property in the CPU0 node, updated the patch description.
Changes in version 2:
- added the IRQC and Ether clocks.
arch/arm/boot/dts/r8a7743.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
+#include <dt-bindings/power/r8a7743-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7743";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
+ power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ L2_CA15: cache-controller at 0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7743_PD_CA15_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller at f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller at e6150000 {
+ compatible = "renesas,r8a7743-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller at e6180000 {
+ compatible = "renesas,r8a7743-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ rst: reset-controller at e6160000 {
+ compatible = "renesas,r8a7743-rst";
+ reg = <0 0xe6160000 0 0x0200>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overriden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
^ permalink raw reply
* [PATCH v5 2/7] ARM: dts: r8a7743: add SYS-DMAC support
From: Sergei Shtylyov @ 2016-10-27 21:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1580369.yToZzJza1l@wasted.cogentembedded.com>
Describe SYS-DMAC0/1 in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 5:
- refreshed the patch.
Changes in version 4:
- refreshed the patch.
Changes in version 3:
- resolved a reject;
- updated the "clocks" properties for the CPG/MSSR driver.
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7743.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -93,6 +93,70 @@
compatible = "renesas,r8a7743-rst";
reg = <0 0xe6160000 0 0x0200>;
};
+
+ dmac0: dma-controller at e6700000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller at e6720000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
};
/* External root clock */
^ permalink raw reply
* [PATCH v5 3/7] ARM: dts: r8a7743: add [H]SCIF{A|B} support
From: Sergei Shtylyov @ 2016-10-27 21:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1580369.yToZzJza1l@wasted.cogentembedded.com>
Describe [H]SCIF{|A|B} ports in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 5:
- refreshed the patch.
Changes in version 4:
- corrected RBNF in the patch description/subject;
- used the R-Car gen2 bindings instead of the RZ/G family ones;
- refreshed the patch;
- added Geert's tag.
Changes in version 3:
- resolved a reject;
- updated the "clocks" properties for the CPG/MSSR driver;
- renamed the patch.
Changes in version 2:
- used the new RZ/G family "compatible" prop values, reformatting where needed;
- fixed the size cells of the SCIFB device nodes' "reg" properties;
- changed the size cells of the "reg" properties to hexadecimal;
- indented the SCIFA1 device node's closing brace correctly
- adjusted the patch description, renamed the patch.
arch/arm/boot/dts/r8a7743.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 261 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -157,6 +157,267 @@
#dma-cells = <1>;
dma-channels = <15>;
};
+
+ scifa0: serial at e6c40000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa1: serial at e6c50000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa2: serial at e6c60000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa3: serial at e6c70000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 0x40>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa4: serial at e6c78000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa5: serial at e6c80000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb0: serial at e6c20000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb1: serial at e6c30000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb2: serial at e6ce0000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif0: serial at e6e60000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial at e6e68000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial at e6e58000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial at e6ea8000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif4: serial at e6ee0000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif5: serial at e6ee8000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial at e62c0000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial at e62c8000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif2: serial at e62d0000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 0x60>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply
* [PATCH v5 4/7] ARM: dts: r8a7743: add Ether support
From: Sergei Shtylyov @ 2016-10-27 21:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1580369.yToZzJza1l@wasted.cogentembedded.com>
Define the generic R8A7743 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 5:
- refreshed the patch.
Changes in version 4:
- refreshed the patch;
- added Geert's tag.
Changes in version 3:
- resolved a reject;
- updated the "clocks" property for the CPG/MSSR driver.
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -418,6 +418,18 @@
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ ether: ethernet at ee700000 {
+ compatible = "renesas,ether-r8a7743";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply
* [PATCH v5 5/7] ARM: dts: r8a7743: add IRQC support
From: Sergei Shtylyov @ 2016-10-27 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1580369.yToZzJza1l@wasted.cogentembedded.com>
Describe the IRQC interrupt controller in the R8A7743 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 4:
- refreshed the patch;
- added Geert's tag.
Changes in version 3:
- updated the "clocks" property for the CPG/MSSR driver.
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller at e61c0000 {
+ compatible = "renesas,irqc-r8a7743", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
^ permalink raw reply
* [PATCH v5 6/7] ARM: dts: sk-rzg1m: initial device tree
From: Sergei Shtylyov @ 2016-10-27 21:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1580369.yToZzJza1l@wasted.cogentembedded.com>
Add the initial device tree for the R8A7743 SoC based SK-RZG1M board.
The board has one debug serial port (SCIF0); include support for it, so
that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 4:
- refreshed the patch.
Changes in version 3:
- added Geert's tag.
arch/arm/boot/dts/Makefile | 1
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 +++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
Index: renesas/arch/arm/boot/dts/Makefile
===================================================================
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -677,6 +677,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
+ r8a7743-sk-rzg1m.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Source for the SK-RZG1M board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743.dtsi"
+
+/ {
+ model = "SK-RZG1M";
+ compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
+
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory at 200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif0 {
+ status = "okay";
+};
^ permalink raw reply
* [PATCH v5 7/7] ARM: dts: sk-rzg1m: add Ether support
From: Sergei Shtylyov @ 2016-10-27 21:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1580369.yToZzJza1l@wasted.cogentembedded.com>
Define the SK-RZG1M board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 4:
- added Geert's tag.
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
+++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -42,3 +42,16 @@
&scif0 {
status = "okay";
};
+
+ðer {
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ interrupt-parent = <&irqc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
^ permalink raw reply
* [PATCH v3 0/3] cpufreq: Introduce TI CPUFreq/OPP Driver
From: Dave Gerlach @ 2016-10-27 21:41 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series is v3 of the series to introduce the ti-cpufreq driver
which parses SoC data and provides opp-supported-hw data to the
OPP core in order to enable the proper OPPs for the silicon in use.
v2 of this series can be found here [1].
Several changes to the dt-binding and ti-cpufreq driver are
present in v3, which are described in detail under scissors line
in patches but mostly focused on moving properties that were added
in cpu node previously to the operating-points node and updating
driver to reflect these changes, along with using a common compatible
for all ti platforms. Also, a new patch was added to expose an internal
OPP core API to allow a common way to get a reference to the OPP table
from a platform driver.
I have just sent the driver and binding here but have held off on the
updated DT nodes, I will send these out once we can agree on the binding
and driver changes but have pushed them if anyone is curious here [2].
Regards,
Dave
[1] http://www.spinics.net/lists/linux-omap/msg131601.html
[2] https://github.com/dgerlach/linux-pm/tree/upstream/v4.9/ti-cpufreq-driver-v3
Dave Gerlach (3):
PM / OPP: Expose _of_get_opp_desc_node as dev_pm_opp API
Documentation: dt: add bindings for ti-cpufreq
cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime
.../devicetree/bindings/cpufreq/ti-cpufreq.txt | 132 ++++++++++
drivers/base/power/opp/of.c | 8 +-
drivers/base/power/opp/opp.h | 1 -
drivers/cpufreq/Kconfig.arm | 11 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/ti-cpufreq.c | 288 +++++++++++++++++++++
include/linux/pm_opp.h | 6 +
7 files changed, 442 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
create mode 100644 drivers/cpufreq/ti-cpufreq.c
--
2.9.3
^ permalink raw reply
* [PATCH v3 1/3] PM / OPP: Expose _of_get_opp_desc_node as dev_pm_opp API
From: Dave Gerlach @ 2016-10-27 21:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027214131.1725-1-d-gerlach@ti.com>
Move _of_get_opp_desc_node into include/linux/pm_opp.h and rename it
dev_pm_opp_of_get_opp_desc_node to allow other drivers, such as platform
OPP and cpufreq drivers, to make use of it.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
drivers/base/power/opp/of.c | 8 ++++----
drivers/base/power/opp/opp.h | 1 -
include/linux/pm_opp.h | 6 ++++++
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/base/power/opp/of.c b/drivers/base/power/opp/of.c
index 5552211e6fcd..215f5a538c78 100644
--- a/drivers/base/power/opp/of.c
+++ b/drivers/base/power/opp/of.c
@@ -198,7 +198,7 @@ void dev_pm_opp_of_remove_table(struct device *dev)
EXPORT_SYMBOL_GPL(dev_pm_opp_of_remove_table);
/* Returns opp descriptor node for a device, caller must do of_node_put() */
-struct device_node *_of_get_opp_desc_node(struct device *dev)
+struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev)
{
/*
* TODO: Support for multiple OPP tables.
@@ -450,7 +450,7 @@ int dev_pm_opp_of_add_table(struct device *dev)
* OPPs have two version of bindings now. The older one is deprecated,
* try for the new binding first.
*/
- opp_np = _of_get_opp_desc_node(dev);
+ opp_np = dev_pm_opp_of_get_opp_desc_node(dev);
if (!opp_np) {
/*
* Try old-deprecated bindings for backward compatibility with
@@ -560,7 +560,7 @@ int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev,
int cpu, ret = 0;
/* Get OPP descriptor node */
- np = _of_get_opp_desc_node(cpu_dev);
+ np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
if (!np) {
dev_dbg(cpu_dev, "%s: Couldn't find cpu_dev node.\n", __func__);
return -ENOENT;
@@ -585,7 +585,7 @@ int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev,
}
/* Get OPP descriptor node */
- tmp_np = _of_get_opp_desc_node(tcpu_dev);
+ tmp_np = dev_pm_opp_of_get_opp_desc_node(tcpu_dev);
if (!tmp_np) {
dev_err(tcpu_dev, "%s: Couldn't find tcpu_dev node.\n",
__func__);
diff --git a/drivers/base/power/opp/opp.h b/drivers/base/power/opp/opp.h
index fabd5ca1a083..96cd30ac6c1d 100644
--- a/drivers/base/power/opp/opp.h
+++ b/drivers/base/power/opp/opp.h
@@ -190,7 +190,6 @@ struct opp_table {
/* Routines internal to opp core */
struct opp_table *_find_opp_table(struct device *dev);
struct opp_device *_add_opp_dev(const struct device *dev, struct opp_table *opp_table);
-struct device_node *_of_get_opp_desc_node(struct device *dev);
void _dev_pm_opp_remove_table(struct device *dev, bool remove_all);
struct dev_pm_opp *_allocate_opp(struct device *dev, struct opp_table **opp_table);
int _opp_add(struct device *dev, struct dev_pm_opp *new_opp, struct opp_table *opp_table);
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index bca26157f5b6..9e8c138f55b7 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -208,6 +208,7 @@ void dev_pm_opp_of_remove_table(struct device *dev);
int dev_pm_opp_of_cpumask_add_table(const struct cpumask *cpumask);
void dev_pm_opp_of_cpumask_remove_table(const struct cpumask *cpumask);
int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask);
+struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev);
#else
static inline int dev_pm_opp_of_add_table(struct device *dev)
{
@@ -231,6 +232,11 @@ static inline int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, struct
{
return -ENOTSUPP;
}
+
+static inline struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev)
+{
+ return NULL;
+}
#endif
#endif /* __LINUX_OPP_H__ */
--
2.9.3
^ permalink raw reply related
* [PATCH v3 2/3] Documentation: dt: add bindings for ti-cpufreq
From: Dave Gerlach @ 2016-10-27 21:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027214131.1725-1-d-gerlach@ti.com>
Add the device tree bindings document for the TI CPUFreq/OPP driver
on AM33xx and AM43xx SoCs. The operating-points-v2 binding allows us
to provide an opp-supported-hw property for each OPP to define when
it is available. This driver is responsible for reading and parsing
registers to determine which OPPs can be selectively enabled based
on the specific SoC in use by matching against the opp-supported-hw
data.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v2->v3:
- Move ti,syscon-* properties under opp table instead of cpu node, as
that is a better location for them.
- For the opp table do not use platform specific compatible strings
but instead a operating-points-v2-ti-cpu
.../devicetree/bindings/cpufreq/ti-cpufreq.txt | 132 +++++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
new file mode 100644
index 000000000000..467ad29c75c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
@@ -0,0 +1,132 @@
+TI CPUFreq and OPP bindings
+================================
+
+Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
+families support different OPPs depending on the silicon variant in use.
+The ti_cpufreq driver can use revision and an efuse value from the SoC to
+provide the OPP framework with supported hardware information. This is
+used to determine which OPPs from the operating-points-v2 table get enabled
+when it is parsed by the OPP framework.
+
+Required properties:
+--------------------
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be 'operating-points-v2-ti-cpu' for am335x, am43xx,
+ and dra7xx/am57xx SoCs
+- ti,syscon-efuse: Syscon phandle, offset to efuse register, efuse register
+ mask, and efuse register shift to get the relevant bits
+ that describe OPP availability.
+- ti,syscon-rev: Syscon and offset used to look up revision value on SoC.
+
+Optional properties:
+--------------------
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: Two bitfields indicating:
+ 1. Which revision of the SoC the OPP is supported by
+ 2. Which eFuse bits indicate this OPP is available
+
+ A bitwise AND is performed against these values and if any bit
+ matches, the OPP gets enabled. Not providing the property for an
+ entry indicates that an OPP is always supported.
+
+Example:
+--------
+
+/* From arch/arm/boot/dts/am33xx.dtsi */
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu at 0 {
+ compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0>;
+
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+};
+
+/*
+ * cpu0 has different OPPs depending on SoC revision and some on revisions
+ * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
+ */
+cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2-ti-am3352-cpu";
+ ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
+ ti,syscon-rev = <&scm_conf 0x600>;
+
+ /*
+ * The three following nodes are marked with opp-suspend
+ * because they can not be enabled simultaneously on a
+ * single SoC.
+ */
+ opp50 at 300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <950000 931000 969000>;
+ opp-supported-hw = <0x06 0x0010>;
+ opp-suspend;
+ };
+
+ opp100 at 275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x01 0x00FF>;
+ opp-suspend;
+ };
+
+ opp100 at 300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x06 0x0020>;
+ opp-suspend;
+ };
+
+ opp100 at 500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x01 0xFFFF>;
+ };
+
+ opp100 at 600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x06 0x0040>;
+ };
+
+ opp120 at 600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000 1176000 1224000>;
+ opp-supported-hw = <0x01 0xFFFF>;
+ };
+
+ opp120 at 720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1200000 1176000 1224000>;
+ opp-supported-hw = <0x06 0x0080>;
+ };
+
+ oppturbo at 720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1260000 1234800 1285200>;
+ opp-supported-hw = <0x01 0xFFFF>;
+ };
+
+ oppturbo at 800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1260000 1234800 1285200>;
+ opp-supported-hw = <0x06 0x0100>;
+ };
+
+ oppnitro at 1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1325000 1298500 1351500>;
+ opp-supported-hw = <0x04 0x0200>;
+ };
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v3 3/3] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime
From: Dave Gerlach @ 2016-10-27 21:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027214131.1725-1-d-gerlach@ti.com>
Some TI SoCs, like those in the AM335x, AM437x, DRA7x, and AM57x families,
have different OPPs available for the MPU depending on which specific
variant of the SoC is in use. This can be determined through use of the
revision and an eFuse register present in the silicon. Introduce a
ti-cpufreq driver that can read the aformentioned values and provide
them as version matching data to the opp framework. Through this the
opp-supported-hw dt binding that is part of the operating-points-v2
table can be used to indicate availability of OPPs for each device.
This driver also creates the "cpufreq-dt" platform_device after passing
the version matching data to the OPP framework so that the cpufreq-dt
handles the actual cpufreq implementation. Even without the necessary
data to pass the version matching data the driver will still create this
device to maintain backwards compatibility with operating-points v1
tables.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v2-v3:
- Use common ti compatible as described in binding and then match
against machine type for platform data.
- Use newly exposed dev_pm_opp_of_get_opp_desc_node to get
operating-points-v2 table now that properties needed by driver are
there.
- Parse syscon properties from operating-points-v2 node rather
than cpu node.
- Do not make ti-cpufreq a module-platform-driver and do not allow
building as module.
drivers/cpufreq/Kconfig.arm | 11 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/ti-cpufreq.c | 288 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 300 insertions(+)
create mode 100644 drivers/cpufreq/ti-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index d89b8afe23b6..665f11dbdaef 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -234,6 +234,17 @@ config ARM_TEGRA124_CPUFREQ
help
This adds the CPUFreq driver support for Tegra124 SOCs.
+config ARM_TI_CPUFREQ
+ bool "Texas Instruments CPUFreq support"
+ depends on ARCH_OMAP2PLUS
+ help
+ This driver enables valid OPPs on the running platform based on
+ values contained within the SoC in use. Enable this in order to
+ use the cpufreq-dt driver on all Texas Instruments platforms that
+ provide dt based operating-points-v2 tables with opp-supported-hw
+ data provided. Required for cpufreq support on AM335x, AM437x,
+ DRA7x, and AM57x platforms.
+
config ARM_PXA2xx_CPUFREQ
tristate "Intel PXA2xx CPUfreq driver"
depends on PXA27x || PXA25x
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 0a9b6a093646..5b1b6ec0a9f0 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o
obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
+obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o
obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
new file mode 100644
index 000000000000..afbaef967b65
--- /dev/null
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -0,0 +1,288 @@
+/*
+ * TI CPUFreq/OPP hw-supported driver
+ *
+ * Copyright (C) 2016 Texas Instruments, Inc.
+ * Dave Gerlach <d-gerlach@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/cpu.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pm_opp.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#define REVISION_MASK 0xF
+#define REVISION_SHIFT 28
+
+#define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
+#define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
+
+#define DRA7_EFUSE_HAS_OD_MPU_OPP 11
+#define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
+#define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
+
+#define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
+#define DRA7_EFUSE_OD_MPU_OPP BIT(1)
+#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
+
+#define VERSION_COUNT 2
+
+struct ti_cpufreq_data;
+
+struct ti_cpufreq_soc_data {
+ unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data,
+ unsigned long efuse);
+ unsigned long efuse_fallback;
+};
+
+struct ti_cpufreq_data {
+ struct device *cpu_dev;
+ struct device_node *opp_node;
+ struct regmap *opp_efuse;
+ struct regmap *revision;
+ const struct ti_cpufreq_soc_data *soc_data;
+};
+
+static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
+ unsigned long efuse)
+{
+ if (!efuse)
+ efuse = opp_data->soc_data->efuse_fallback;
+ /* AM335x and AM437x use "OPP disable" bits, so invert */
+ return ~efuse;
+}
+
+static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
+ unsigned long efuse)
+{
+ unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP;
+
+ /*
+ * The efuse on dra7 and am57 parts contains a specific
+ * value indicating the highest available OPP.
+ */
+
+ switch (efuse) {
+ case DRA7_EFUSE_HAS_ALL_MPU_OPP:
+ case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
+ calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
+ case DRA7_EFUSE_HAS_OD_MPU_OPP:
+ calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
+ }
+
+ return calculated_efuse;
+}
+
+static struct ti_cpufreq_soc_data am3x_soc_data = {
+ .efuse_xlate = amx3_efuse_xlate,
+ .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
+};
+
+static struct ti_cpufreq_soc_data am4x_soc_data = {
+ .efuse_xlate = amx3_efuse_xlate,
+ .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ,
+};
+
+static struct ti_cpufreq_soc_data dra7_soc_data = {
+ .efuse_xlate = dra7_efuse_xlate,
+};
+
+/**
+ * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
+ * @opp_data: pointer to ti_cpufreq_data context
+ * @efuse_value: Set to the value parsed from efuse
+ *
+ * Returns error code if efuse not read properly.
+ */
+static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
+ u32 *efuse_value)
+{
+ struct device *dev = opp_data->cpu_dev;
+ struct device_node *np = opp_data->opp_node;
+ unsigned int efuse_offset;
+ u32 efuse, efuse_mask, efuse_shift, vals[4];
+ int ret;
+
+ ret = of_property_read_u32_array(np, "ti,syscon-efuse", vals, 4);
+ if (ret) {
+ dev_err(dev, "ti,syscon-efuse cannot be read %s: %d\n",
+ np->full_name, ret);
+ return ret;
+ }
+
+ efuse_offset = vals[1];
+ efuse_mask = vals[2];
+ efuse_shift = vals[3];
+
+ ret = regmap_read(opp_data->opp_efuse, efuse_offset, &efuse);
+ if (ret) {
+ dev_err(dev,
+ "Failed to read the efuse value from syscon: %d\n",
+ ret);
+ return ret;
+ }
+
+ efuse = (efuse & efuse_mask) >> efuse_shift;
+
+ *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse);
+
+ return 0;
+}
+
+/**
+ * ti_cpufreq_get_rev() - Parse and return rev value present on SoC
+ * @opp_data: pointer to ti_cpufreq_data context
+ * @revision_value: Set to the value parsed from revision register
+ *
+ * Returns error code if revision not read properly.
+ */
+static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
+ u32 *revision_value)
+{
+ struct device *dev = opp_data->cpu_dev;
+ struct device_node *np = opp_data->opp_node;
+ unsigned int revision_offset;
+ u32 revision;
+ int ret;
+
+ ret = of_property_read_u32_index(np, "ti,syscon-rev",
+ 1, &revision_offset);
+ if (ret) {
+ dev_err(dev,
+ "No revision offset provided %s [%d]\n",
+ np->full_name, ret);
+ return ret;
+ }
+
+ ret = regmap_read(opp_data->revision, revision_offset, &revision);
+ if (ret) {
+ dev_err(dev,
+ "Failed to read the revision number from syscon: %d\n",
+ ret);
+ return ret;
+ }
+
+ *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
+
+ return 0;
+}
+
+static int ti_cpufreq_setup_syscon_registers(struct ti_cpufreq_data *opp_data)
+{
+ struct device *dev = opp_data->cpu_dev;
+ struct device_node *np = opp_data->opp_node;
+
+ opp_data->opp_efuse = syscon_regmap_lookup_by_phandle(np,
+ "ti,syscon-efuse");
+ if (IS_ERR(opp_data->opp_efuse)) {
+ dev_err(dev,
+ "\"ti,syscon-efuse\" is missing, cannot use OPPv2 table.\n");
+ return PTR_ERR(opp_data->opp_efuse);
+ }
+
+ opp_data->revision = syscon_regmap_lookup_by_phandle(np,
+ "ti,syscon-rev");
+ if (IS_ERR(opp_data->revision)) {
+ dev_err(dev,
+ "\"ti,syscon-rev\" is missing, cannot use OPPv2 table.\n");
+ return PTR_ERR(opp_data->revision);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id ti_cpufreq_of_match[] = {
+ { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
+ { .compatible = "ti,am4372", .data = &am4x_soc_data, },
+ { .compatible = "ti,dra7", .data = &dra7_soc_data },
+ {},
+};
+
+static int ti_cpufreq_init(void)
+{
+ u32 version[VERSION_COUNT];
+ struct device_node *np;
+ const struct of_device_id *match;
+ struct ti_cpufreq_data *opp_data;
+ int ret;
+
+ np = of_find_node_by_path("/");
+ match = of_match_node(ti_cpufreq_of_match, np);
+ if (!match)
+ return -ENODEV;
+
+ opp_data = kzalloc(sizeof(*opp_data), GFP_KERNEL);
+ if (!opp_data)
+ return -ENOMEM;
+
+ opp_data->soc_data = match->data;
+
+ opp_data->cpu_dev = get_cpu_device(0);
+ if (!opp_data->cpu_dev) {
+ pr_err("%s: Failed to get device for CPU0\n", __func__);
+ return -ENODEV;
+ }
+
+ opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
+ if (!opp_data->opp_node) {
+ dev_info(opp_data->cpu_dev,
+ "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n");
+ goto register_cpufreq_dt;
+ }
+
+ ret = ti_cpufreq_setup_syscon_registers(opp_data);
+ if (ret)
+ goto fail_put_node;
+
+ /*
+ * OPPs determine whether or not they are supported based on
+ * two metrics:
+ * 0 - SoC Revision
+ * 1 - eFuse value
+ */
+ ret = ti_cpufreq_get_rev(opp_data, &version[0]);
+ if (ret)
+ goto fail_put_node;
+
+ ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
+ if (ret)
+ goto fail_put_node;
+
+ of_node_put(opp_data->opp_node);
+
+ ret = dev_pm_opp_set_supported_hw(opp_data->cpu_dev, version,
+ VERSION_COUNT);
+ if (ret) {
+ dev_err(opp_data->cpu_dev,
+ "Failed to set supported hardware\n");
+ goto fail_put_node;
+ }
+
+register_cpufreq_dt:
+ platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
+
+ return 0;
+
+fail_put_node:
+ of_node_put(opp_data->opp_node);
+
+ return ret;
+}
+module_init(ti_cpufreq_init);
+
+MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
+MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
+MODULE_LICENSE("GPL v2");
--
2.9.3
^ permalink raw reply related
* [PATCH v5 1/7] drm: sunxi: Add a basic DRM driver for Allwinner DE2
From: Maxime Ripard @ 2016-10-27 22:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161025161441.6b248efe9229bd80e3f7a33c@free.fr>
On Tue, Oct 25, 2016 at 04:14:41PM +0200, Jean-Francois Moine wrote:
> > > +Display controller
> > > +==================
> > > +
> > > +Required properties:
> > > +
> > > +- compatible: value should be one of the following
> > > + "allwinner,sun8i-a83t-display-engine"
> > > + "allwinner,sun8i-h3-display-engine"
> > > +
> > > +- clocks: must include clock specifiers corresponding to entries in the
> > > + clock-names property.
> > > +
> > > +- clock-names: must contain
> > > + "gate": for DE activation
> > > + "clock": DE clock
> >
> > We've been calling them bus and mod.
>
> I can understand "bus" (which is better than "apb"), but why "mod"?
Allwinner has been calling the clocks that are supposed to generate
the external signals (depending on where you were looking) module or
mod clocks (which is also why we have mod in the clock
compatibles). The module 1 clocks being used for the audio and the
module 0 for the rest (SPI, MMC, NAND, display, etc.)
> > > +
> > > +- resets: phandle to the reset of the device
> > > +
> > > +- ports: phandle's to the LCD ports
> >
> > Please use the OF graph.
>
> These ports are references to the graph of nodes. See
> http://www.kernelhub.org/?msg=911825&p=2
In an OF-graph, your phandle to the LCD controller would be replaced
by an output endpoint.
>
> [snip]
> > > +struct tcon {
> > > + u32 gctl;
> > > +#define TCON_GCTL_TCON_En BIT(31)
> > > + u32 gint0;
> > > +#define TCON_GINT0_TCON1_Vb_Int_En BIT(30)
> > > +#define TCON_GINT0_TCON1_Vb_Int_Flag BIT(14)
> > > + u32 gint1;
> > > + u32 dum0[13];
> > > + u32 tcon0_ctl; /* 0x40 */
> > > +#define TCON0_CTL_TCON_En BIT(31)
> > > + u32 dum1[19];
> > > + u32 tcon1_ctl; /* 0x90 */
> > > +#define TCON1_CTL_TCON_En BIT(31)
> > > +#define TCON1_CTL_Interlace_En BIT(20)
> > > +#define TCON1_CTL_Start_Delay_SHIFT 4
> > > +#define TCON1_CTL_Start_Delay_MASK GENMASK(8, 4)
> > > + u32 basic0; /* XI/YI */
> > > + u32 basic1; /* LS_XO/LS_YO */
> > > + u32 basic2; /* XO/YO */
> > > + u32 basic3; /* HT/HBP */
> > > + u32 basic4; /* VT/VBP */
> > > + u32 basic5; /* HSPW/VSPW */
> > > + u32 dum2;
> > > + u32 ps_sync; /* 0xb0 */
> > > + u32 dum3[15];
> > > + u32 io_pol; /* 0xf0 */
> > > +#define TCON1_IO_POL_IO0_inv BIT(24)
> > > +#define TCON1_IO_POL_IO1_inv BIT(25)
> > > +#define TCON1_IO_POL_IO2_inv BIT(26)
> > > + u32 io_tri;
> > > + u32 dum4[2];
> > > +
> > > + u32 ceu_ctl; /* 0x100 */
> > > +#define TCON_CEU_CTL_ceu_en BIT(31)
> > > + u32 dum5[3];
> > > + u32 ceu_rr;
> > > + u32 ceu_rg;
> > > + u32 ceu_rb;
> > > + u32 ceu_rc;
> > > + u32 ceu_gr;
> > > + u32 ceu_gg;
> > > + u32 ceu_gb;
> > > + u32 ceu_gc;
> > > + u32 ceu_br;
> > > + u32 ceu_bg;
> > > + u32 ceu_bb;
> > > + u32 ceu_bc;
> > > + u32 ceu_rv;
> > > + u32 ceu_gv;
> > > + u32 ceu_bv;
> > > + u32 dum6[45];
> > > +
> > > + u32 mux_ctl; /* 0x200 */
> > > + u32 dum7[63];
> > > +
> > > + u32 fill_ctl; /* 0x300 */
> > > + u32 fill_start0;
> > > + u32 fill_end0;
> > > + u32 fill_data0;
> > > +};
> >
> > Please use defines instead of the structures.
>
> I think that structures are more readable.
That's not really the point. No one in the kernel uses it (and even
you use defines for registers offset in some places of that
patch). And then you have Andr? arguments.
> > > +void de2_disable_vblank(struct drm_device *drm, unsigned crtc)
> > > +{
> > > + struct priv *priv = drm->dev_private;
> > > + struct lcd *lcd = priv->lcds[crtc];
> > > +
> > > + tcon_write(lcd->mmio, gint0,
> > > + tcon_read(lcd->mmio, gint0) &
> > > + ~TCON_GINT0_TCON1_Vb_Int_En);
> > > +}
> > > +
> > > +/* panel functions */
> >
> > Panel functions? In the CRTC driver?
>
> Yes, dumb panel.
What do you mean by that? Using a Parallel/RGB interface?
>
> > > +static void de2_set_frame_timings(struct lcd *lcd)
> > > +{
> > > + struct drm_crtc *crtc = &lcd->crtc;
> > > + const struct drm_display_mode *mode = &crtc->mode;
> > > + int interlace = mode->flags & DRM_MODE_FLAG_INTERLACE ? 2 : 1;
> > > + int start_delay;
> > > + u32 data;
> > > +
> > > + data = XY(mode->hdisplay - 1, mode->vdisplay / interlace - 1);
> > > + tcon_write(lcd->mmio, basic0, data);
> > > + tcon_write(lcd->mmio, basic1, data);
> > > + tcon_write(lcd->mmio, basic2, data);
> > > + tcon_write(lcd->mmio, basic3,
> > > + XY(mode->htotal - 1,
> > > + mode->htotal - mode->hsync_start - 1));
> > > + tcon_write(lcd->mmio, basic4,
> > > + XY(mode->vtotal * (3 - interlace),
> > > + mode->vtotal - mode->vsync_start - 1));
> > > + tcon_write(lcd->mmio, basic5,
> > > + XY(mode->hsync_end - mode->hsync_start - 1,
> > > + mode->vsync_end - mode->vsync_start - 1));
> > > +
> > > + tcon_write(lcd->mmio, ps_sync, XY(1, 1));
> > > +
> > > + data = TCON1_IO_POL_IO2_inv;
> > > + if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> > > + data |= TCON1_IO_POL_IO0_inv;
> > > + if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> > > + data |= TCON1_IO_POL_IO1_inv;
> > > + tcon_write(lcd->mmio, io_pol, data);
> > > +
> > > + tcon_write(lcd->mmio, ceu_ctl,
> > > + tcon_read(lcd->mmio, ceu_ctl) & ~TCON_CEU_CTL_ceu_en);
> > > +
> > > + data = tcon_read(lcd->mmio, tcon1_ctl);
> > > + if (interlace == 2)
> > > + data |= TCON1_CTL_Interlace_En;
> > > + else
> > > + data &= ~TCON1_CTL_Interlace_En;
> > > + tcon_write(lcd->mmio, tcon1_ctl, data);
> > > +
> > > + tcon_write(lcd->mmio, fill_ctl, 0);
> > > + tcon_write(lcd->mmio, fill_start0, mode->vtotal + 1);
> > > + tcon_write(lcd->mmio, fill_end0, mode->vtotal);
> > > + tcon_write(lcd->mmio, fill_data0, 0);
> > > +
> > > + start_delay = (mode->vtotal - mode->vdisplay) / interlace - 5;
> > > + if (start_delay > 31)
> > > + start_delay = 31;
> > > + data = tcon_read(lcd->mmio, tcon1_ctl);
> > > + data &= ~TCON1_CTL_Start_Delay_MASK;
> > > + data |= start_delay << TCON1_CTL_Start_Delay_SHIFT;
> > > + tcon_write(lcd->mmio, tcon1_ctl, data);
> > > +
> > > + tcon_write(lcd->mmio, io_tri, 0x0fffffff);
> > > +}
> >
> > Some comments here would be nice, there's a lot of non trivial things.
>
> ... and no documentation. I just set the values I saw in the I/O memory
> when running the legacy driver.
That's bad (but definitely not your fault) :/
> > > + lcd->gate = devm_clk_get(dev, "gate"); /* optional */
> >
> > Having some kind of error checking would still be nice.
>
> And cancel the device creation?
Well, yes. If it cannot enable it, it will at best not work properly,
at worst be reset, so it won't be very useful anyway.
> > > + if (!IS_ERR(lcd->rstc)) {
> > > + ret = reset_control_deassert(lcd->rstc);
> > > + if (ret) {
> > > + dev_err(dev, "reset deassert err %d\n", ret);
> > > + goto err;
> > > + }
> > > + }
> > > +
> > > + if (!IS_ERR(lcd->gate)) {
> > > + ret = clk_prepare_enable(lcd->gate);
> > > + if (ret)
> > > + goto err2;
> > > + }
> > > +
> > > + ret = clk_prepare_enable(lcd->clk);
> > > + if (ret)
> > > + goto err2;
> >
> > Is there any reason not to do that in the enable / disable? Leaving
> > clocks running while the device has no guarantee that it's going to be
> > used seems like a waste of resources.
>
> If the machine does not need video (network server, router..), it is simpler
> to prevent the video driver to be loaded (DT, module black list...).
You might not have control on any of it, or you might just have no
monitor attached for example. Recompiling the kernel or updating the
DT when you want to plug an HDMI monitor seems like a poor UX :)
> > > +static const struct {
> > > + char chan;
> > > + char layer;
> > > + char pipe;
> > > +} plane2layer[DE2_N_PLANES] = {
> > > + [DE2_PRIMARY_PLANE] = {0, 0, 0},
> > > + [DE2_CURSOR_PLANE] = {1, 0, 1},
> > > + [DE2_VI_PLANE] = {0, 1, 0},
> > > +};
> >
> > Comments?
>
> This
> primary plane is channel 0 (VI), layer 0, pipe 0
> cursor plane is channel 1 (UI), layer 0, pipe 1
> overlay plane is channel 0 (VI), layer 1, pipe 0
> or the full explanation:
> Constraints:
> The VI channels can do RGB or YUV, while UI channels can do RGB
> only.
> The LCD 0 has 1 VI channel and 4 UI channels, while
> LCD 1 has only 1 VI channel and 1 UI channel.
> The cursor must go to a channel bigger than the primary channel,
> otherwise it is not transparent.
> First try:
> Letting the primary plane (usually RGB) in the 2nd channel (UI),
> as this is done in the legacy driver, asks for the cursor to go
> to the next channel (UI), but this one does not exist in LCD1.
> Retained layout:
> So, we must use only 2 channels for the same behaviour on LCD0
> (H3) and LCD1 (A83T)
> The retained combination is:
> - primary plane in the first channel (VI),
> - cursor plane inthe 2nd channel (UI), and
> - overlay plane in the 1st channel (VI).
>
> Note that there could be 3 overlay planes (a channel has 4
> layers), but I am not sure that the A83T or the H3 could
> support 3 simultaneous video streams...
Do you know if the pipe works in the old display engine?
Especially about the two-steps composition that wouldn't allow you to
have alpha on all the planes?
If it is similar, I think hardcoding the pipe number is pretty bad,
because that would restrict the combination of planes and formats,
while some other might have worked.
> > > +static inline void de_write(struct priv *priv, int reg, u32 data)
> > > +{
> > > + writel_relaxed(data, priv->mmio + reg);
> > > +}
> > > +
> > > +static inline u32 de_read(struct priv *priv, int reg)
> > > +{
> > > + return readl_relaxed(priv->mmio + reg);
> > > +}
> > > +
> > > +static void de_lcd_select(struct priv *priv,
> > > + int lcd_num,
> > > + void __iomem *mux_o)
> > > +{
> > > + u32 data;
> > > +
> > > + /* select the LCD */
> > > + data = de_read(priv, DE_SEL_REG);
> > > + data &= ~1;
> > > + de_write(priv, DE_SEL_REG, data);
> > > +
> > > + /* double register switch */
> > > + glb_write(mux_o + DE_MUX_GLB_REGS, dbuff, 1);
> > > +}
> > > +
> > > +void de2_de_plane_update(struct priv *priv,
> > > + int lcd_num, int plane_ix,
> > > + struct drm_plane_state *state,
> > > + struct drm_plane_state *old_state)
> > > +{
> > > + struct drm_framebuffer *fb = state->fb;
> > > + struct drm_gem_cma_object *gem;
> > > + void __iomem *mux_o = priv->mmio;
> > > + void __iomem *chan_o;
> > > + u32 size = WH(state->crtc_w, state->crtc_h);
> > > + u32 coord;
> > > + u32 screen_size;
> > > + u32 data, fcolor;
> > > + u32 ui_sel, alpha_glob;
> > > + int chan, layer, x, y;
> > > + unsigned fmt;
> > > + unsigned long flags;
> > > +
> > > + chan = plane2layer[plane_ix].chan;
> > > + layer = plane2layer[plane_ix].layer;
> > > +
> > > + mux_o += (lcd_num == 0) ? DE_MUX0_BASE : DE_MUX1_BASE;
> > > + chan_o = mux_o;
> > > + chan_o += DE_MUX_CHAN_REGS + DE_MUX_CHAN_SZ * chan;
> > > +
> > > + x = state->crtc_x >= 0 ? state->crtc_x : 0;
> > > + y = state->crtc_y >= 0 ? state->crtc_y : 0;
> > > + coord = XY(x, y);
> > > +
> > > + /* handle the cursor move */
> > > + if (plane_ix == DE2_CURSOR_PLANE
> > > + && fb == old_state->fb) {
> > > + spin_lock_irqsave(&de_lock, flags);
> > > + de_lcd_select(priv, lcd_num, mux_o);
> > > + if (chan == 0)
> > > + vi_write(chan_o, cfg[layer].coord, coord);
> > > + else
> > > + ui_write(chan_o, cfg[layer].coord, coord);
> > > + spin_unlock_irqrestore(&de_lock, flags);
> > > + return;
> > > + }
> > > +
> > > + gem = drm_fb_cma_get_gem_obj(fb, 0);
> > > +
> > > + ui_sel = alpha_glob = 0;
> > > + switch (fb->pixel_format) {
> > > + case DRM_FORMAT_ARGB8888:
> > > + fmt = DE2_FORMAT_ARGB_8888;
> > > + ui_sel = VI_CFG_ATTR_ui_sel;
> > > + break;
> > > + case DRM_FORMAT_BGRA8888:
> > > + fmt = DE2_FORMAT_BGRA_8888;
> > > + ui_sel = VI_CFG_ATTR_ui_sel;
> > > + break;
> > > + case DRM_FORMAT_XRGB8888:
> > > + fmt = DE2_FORMAT_XRGB_8888;
> > > + ui_sel = VI_CFG_ATTR_ui_sel;
> > > + alpha_glob = (1 << UI_CFG_ATTR_alpmod_SHIFT) |
> > > + (0xff << UI_CFG_ATTR_alpha_SHIFT);
> > > + break;
> > > + case DRM_FORMAT_RGB888:
> > > + fmt = DE2_FORMAT_RGB_888;
> > > + ui_sel = VI_CFG_ATTR_ui_sel;
> > > + break;
> > > + case DRM_FORMAT_BGR888:
> > > + fmt = DE2_FORMAT_BGR_888;
> > > + ui_sel = VI_CFG_ATTR_ui_sel;
> > > + break;
> > > + case DRM_FORMAT_YUYV:
> > > + fmt = DE2_FORMAT_YUV422_I_YUYV;
> > > + break;
> > > + case DRM_FORMAT_YVYU:
> > > + fmt = DE2_FORMAT_YUV422_I_YVYU;
> > > + break;
> > > + case DRM_FORMAT_YUV422:
> > > + fmt = DE2_FORMAT_YUV422_P;
> > > + break;
> > > + case DRM_FORMAT_YUV420:
> > > + fmt = DE2_FORMAT_YUV420_P;
> > > + break;
> > > + case DRM_FORMAT_UYVY:
> > > + fmt = DE2_FORMAT_YUV422_I_UYVY;
> > > + break;
> > > + default:
> > > + pr_err("format %.4s not yet treated\n",
> > > + (char *) &fb->pixel_format);
> > > + return;
> > > + }
> > > +
> > > + spin_lock_irqsave(&de_lock, flags);
> > > +
> > > + screen_size = plane_ix == DE2_PRIMARY_PLANE ?
> > > + size :
> > > + glb_read(mux_o + DE_MUX_GLB_REGS, size);
> > > +
> > > + /* prepare the activation of alpha blending (1 bit per plane) */
> > > + fcolor = bld_read(mux_o + DE_MUX_BLD_REGS, fcolor_ctl)
> > > + | (0x100 << plane2layer[plane_ix].pipe);
> > > +
> > > + de_lcd_select(priv, lcd_num, mux_o);
> > > +
> > > + if (chan == 0) { /* VI channel */
> > > + int i;
> > > +
> > > + data = VI_CFG_ATTR_en | (fmt << VI_CFG_ATTR_fmt_SHIFT) |
> > > + ui_sel;
> > > + vi_write(chan_o, cfg[layer].attr, data);
> > > + vi_write(chan_o, cfg[layer].size, size);
> > > + vi_write(chan_o, cfg[layer].coord, coord);
> > > + for (i = 0; i < VI_N_PLANES; i++) {
> > > + vi_write(chan_o, cfg[layer].pitch[i],
> > > + fb->pitches[i] ? fb->pitches[i] :
> > > + fb->pitches[0]);
> > > + vi_write(chan_o, cfg[layer].top_laddr[i],
> > > + gem->paddr + fb->offsets[i]);
> > > + vi_write(chan_o, fcolor[layer], 0xff000000);
> > > + }
> > > + if (layer == 0)
> > > + vi_write(chan_o, ovl_size[0], screen_size);
> > > +
> > > + } else { /* UI channel */
> > > + data = UI_CFG_ATTR_en | (fmt << UI_CFG_ATTR_fmt_SHIFT) |
> > > + alpha_glob;
> > > + ui_write(chan_o, cfg[layer].attr, data);
> > > + ui_write(chan_o, cfg[layer].size, size);
> > > + ui_write(chan_o, cfg[layer].coord, coord);
> > > + ui_write(chan_o, cfg[layer].pitch, fb->pitches[0]);
> > > + ui_write(chan_o, cfg[layer].top_laddr,
> > > + gem->paddr + fb->offsets[0]);
> > > + if (layer == 0)
> > > + ui_write(chan_o, ovl_size, screen_size);
> > > + }
> > > + bld_write(mux_o + DE_MUX_BLD_REGS, fcolor_ctl, fcolor);
> > > +
> > > + spin_unlock_irqrestore(&de_lock, flags);
> > > +}
> >
> > Splitting that into functions would make it a bit more trivial and
> > readable.
>
> Not sure: there is a lot of common data and different I/O accesses.
You could still have different ones to set the buffers, formats and
coordinates for example.
> > > +void de2_de_plane_disable(struct priv *priv,
> > > + int lcd_num, int plane_ix)
> > > +{
> > > + void __iomem *mux_o = priv->mmio;
> > > + void __iomem *chan_o;
> > > + u32 fcolor;
> > > + int chan, layer, chan_disable = 0;
> > > + unsigned long flags;
> > > +
> > > + chan = plane2layer[plane_ix].chan;
> > > + layer = plane2layer[plane_ix].layer;
> > > +
> > > + mux_o += (lcd_num == 0) ? DE_MUX0_BASE : DE_MUX1_BASE;
> > > + chan_o = mux_o;
> > > + chan_o += DE_MUX_CHAN_REGS + DE_MUX_CHAN_SZ * chan;
> > > +
> > > + /* (only 2 layers) */
> > > + if (chan == 0) {
> > > + if (vi_read(chan_o, cfg[1 - layer].attr) == 0)
> > > + chan_disable = 1;
> > > + } else {
> > > + if (ui_read(chan_o, cfg[1 - layer].attr) == 0)
> > > + chan_disable = 1;
> > > + }
> > > +
> > > + spin_lock_irqsave(&de_lock, flags);
> > > +
> > > + fcolor = bld_read(mux_o + DE_MUX_BLD_REGS, fcolor_ctl);
> > > +
> > > + de_lcd_select(priv, lcd_num, mux_o);
> > > +
> > > + if (chan == 0)
> > > + vi_write(chan_o, cfg[layer].attr, 0);
> > > + else
> > > + ui_write(chan_o, cfg[layer].attr, 0);
> > > +
> > > + if (chan_disable)
> > > + bld_write(mux_o + DE_MUX_BLD_REGS, fcolor_ctl,
> > > + fcolor & ~(0x100 << plane2layer[plane_ix].pipe));
> > > +
> > > + spin_unlock_irqrestore(&de_lock, flags);
> > > +}
> >
> > Can't you just disable it?
>
> Which 'it'? A layer must be disabled and it is not useful to let the
> DE2 processor to scan a pipe (channel) without any layer.
Oh, so that's what it does.
I really think that you should put as much comments as possible on
what you found out working on this, especially because of the lack of
documentation.
> > > +static int __init de2_drm_init(void)
> > > +{
> > > + int ret;
> > > +
> > > +/* uncomment to activate the drm traces at startup time */
> > > +/* drm_debug = DRM_UT_CORE | DRM_UT_DRIVER | DRM_UT_KMS |
> > > + DRM_UT_PRIME | DRM_UT_ATOMIC; */
> >
> > That's useless.
>
> Right, but it seems that some people don't know how to debug a DRM
> driver. This is only a reminder.
>
> > > + DRM_DEBUG_DRIVER("\n");
> > > +
> > > + ret = platform_driver_register(&de2_lcd_platform_driver);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + ret = platform_driver_register(&de2_drm_platform_driver);
> > > + if (ret < 0)
> > > + platform_driver_unregister(&de2_lcd_platform_driver);
> > > +
> > > + return ret;
> > > +}
> >
> > And that really shouldn't be done that way.
>
> May you explain?
This goes against the whole idea of the device and driver
model. Drivers should only register themselves, device should be
created by buses (or by using some external components if the bus
can't: DT, ACPI, etc.). If there's a match, you get probed.
A driver that creates its own device just to probe itself violates
that.
> > > +int de2_plane_init(struct drm_device *drm, struct lcd *lcd)
> > > +{
> > > + int ret, possible_crtcs = 1 << lcd->crtc_idx;
> > > +
> > > + ret = de2_one_plane_init(drm, &lcd->planes[DE2_PRIMARY_PLANE],
> > > + DRM_PLANE_TYPE_PRIMARY, possible_crtcs,
> > > + ui_formats, ARRAY_SIZE(ui_formats));
> > > + if (ret >= 0)
> > > + ret = de2_one_plane_init(drm, &lcd->planes[DE2_CURSOR_PLANE],
> > > + DRM_PLANE_TYPE_CURSOR, possible_crtcs,
> > > + ui_formats, ARRAY_SIZE(ui_formats));
> >
> > Nothing looks really special about that cursor plane. Any reasion not
> > to make it an overlay?
>
> As explained above (channel/layer/pipe plane definitions), the cursor
> cannot go in a channel lower or equal to the one of the primary plane.
> Then, it must be known and, so, have an explicit plane.
If you were to make it a plane, you could use atomic_check to check
this and make sure this doesn't happen. And you would gain a generic
plane that can be used for other purposes if needed.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 4/5] net: ethernet: bgmac: add NS2 support
From: Ray Jui @ 2016-10-27 22:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027205117.GA24397@broadcom.com>
On 10/27/2016 1:51 PM, Jon Mason wrote:
> On Wed, Oct 26, 2016 at 02:50:39PM -0700, Florian Fainelli wrote:
>> On 10/26/2016 12:36 PM, Jon Mason wrote:
>>> Add support for the variant of amac hardware present in the Broadcom
>>> Northstar2 based SoCs. Northstar2 requires an additional register to be
>>> configured with the port speed/duplexity (NICPM). This can be added to
>>> the link callback to hide it from the instances that do not use this.
>>> Also, the bgmac_chip_reset() was intentionally removed to prevent the
>>> resetting of the chip to the default values on open. Finally, clearing
>>> of the pending interrupts on init is required due to observed issues on
>>> some platforms.
>>>
>>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>>> ---
>>
>>> +static void bgmac_nicpm_speed_set(struct net_device *net_dev)
>>> +{
>>> + struct bgmac *bgmac = netdev_priv(net_dev);
>>> + u32 val;
>>> +
>>> + if (!bgmac->plat.nicpm_base)
>>> + return;
>>> +
>>> + val = NICPM_IOMUX_CTRL_INIT_VAL;
>>> + switch (bgmac->net_dev->phydev->speed) {
>>> + default:
>>> + pr_err("Unsupported speed. Defaulting to 1000Mb\n");
>>> + case SPEED_1000:
>>> + val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
>>> + break;
>>> + case SPEED_100:
>>> + val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
>>> + break;
>>> + case SPEED_10:
>>> + val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
>>> + break;
>>> + }
>>> +
>>> + writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
>>> +
>>> + usleep_range(10, 100);
>>
>> Does not seem like a good idea, do you need that sleep?
>
> Oops, that's not supposed to be there. Removed.
>
>
>>> +
>>> + bgmac_adjust_link(bgmac->net_dev);
>>> +}
>>> +
>>> static int platform_phy_connect(struct bgmac *bgmac)
>>> {
>>> struct phy_device *phy_dev;
>>>
>>> - phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
>>> - bgmac_adjust_link);
>>> + if (bgmac->plat.nicpm_base)
>>> + phy_dev = of_phy_get_and_connect(bgmac->net_dev,
>>> + bgmac->dev->of_node,
>>> + bgmac_nicpm_speed_set);
>>> + else
>>> + phy_dev = of_phy_get_and_connect(bgmac->net_dev,
>>> + bgmac->dev->of_node,
>>> + bgmac_adjust_link);
>>> if (!phy_dev) {
>>> dev_err(bgmac->dev, "Phy connect failed\n");
>>> return -ENODEV;
>>> }
>>>
>>> + if (bgmac->feature_flags & BGMAC_FEAT_LANE_SWAP)
>>> + phy_dev->dev_flags |= PHY_BRCM_EXP_LANE_SWAP;
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -140,6 +188,9 @@ static int bgmac_probe(struct platform_device *pdev)
>>>
>>> platform_set_drvdata(pdev, bgmac);
>>>
>>> + if (of_property_read_bool(np, "brcm,enet-phy-lane-swap"))
>>> + bgmac->feature_flags |= BGMAC_FEAT_LANE_SWAP;
>>> +
>>> /* Set the features of the 4707 family */
>>> bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
>>> bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
>>> @@ -182,6 +233,14 @@ static int bgmac_probe(struct platform_device *pdev)
>>> if (IS_ERR(bgmac->plat.idm_base))
>>> return PTR_ERR(bgmac->plat.idm_base);
>>>
>>> + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
>>> + if (regs) {
>>> + bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
>>> + regs);
>>> + if (IS_ERR(bgmac->plat.nicpm_base))
>>> + return PTR_ERR(bgmac->plat.nicpm_base);
>>> + }
>>> +
>>> bgmac->read = platform_bgmac_read;
>>> bgmac->write = platform_bgmac_write;
>>> bgmac->idm_read = platform_bgmac_idm_read;
>>> @@ -213,6 +272,7 @@ static int bgmac_remove(struct platform_device *pdev)
>>> static const struct of_device_id bgmac_of_enet_match[] = {
>>> {.compatible = "brcm,amac",},
>>> {.compatible = "brcm,nsp-amac",},
>>> + {.compatible = "brcm,ns2-amac",},
>>> {},
>>> };
>>>
>>> diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
>>> index 38876ec..1796208 100644
>>> --- a/drivers/net/ethernet/broadcom/bgmac.c
>>> +++ b/drivers/net/ethernet/broadcom/bgmac.c
>>> @@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
>>> /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
>>> static void bgmac_chip_init(struct bgmac *bgmac)
>>> {
>>> + /* Clear any erroneously pending interrupts */
>>> + bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
>>> +
>>> /* 1 interrupt per received frame */
>>> bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
>>>
>>> @@ -1158,8 +1161,6 @@ static int bgmac_open(struct net_device *net_dev)
>>> struct bgmac *bgmac = netdev_priv(net_dev);
>>> int err = 0;
>>>
>>> - bgmac_chip_reset(bgmac);
>>> -
>>
>> Is this removal intentional? Maybe it should be special cased with
>> checking for a NS2 BGMAC instance and not do it in that case?
>
> The reset seems completely unnecessary. There is already 2 resets in
> the probe routine, another reset serves no purpose. I can add it
> back, as it does not seem to have the negative effect I was seeing
> before.
After repeated ifconfig down/up, does Ethernet still work with this
reset removed?
Thanks.
>
> Of course, if I remove this one I should remove the reset in the close
> too (which seems even more unnecessary, but I didn't remove it).
>
> Thanks,
> Jon
>
>> --
>> Florian
^ permalink raw reply
* [PATCH 4/5] net: ethernet: bgmac: add NS2 support
From: Ray Jui @ 2016-10-27 22:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ccbaf726-b1fc-975a-215c-17e2870328a6@broadcom.com>
On 10/27/2016 3:21 PM, Ray Jui wrote:
>
>
> On 10/27/2016 1:51 PM, Jon Mason wrote:
>> On Wed, Oct 26, 2016 at 02:50:39PM -0700, Florian Fainelli wrote:
>>> On 10/26/2016 12:36 PM, Jon Mason wrote:
>>>> Add support for the variant of amac hardware present in the Broadcom
>>>> Northstar2 based SoCs. Northstar2 requires an additional register to be
>>>> configured with the port speed/duplexity (NICPM). This can be added to
>>>> the link callback to hide it from the instances that do not use this.
>>>> Also, the bgmac_chip_reset() was intentionally removed to prevent the
>>>> resetting of the chip to the default values on open. Finally, clearing
>>>> of the pending interrupts on init is required due to observed issues on
>>>> some platforms.
>>>>
>>>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>>>> ---
>>>
>>>> +static void bgmac_nicpm_speed_set(struct net_device *net_dev)
>>>> +{
>>>> + struct bgmac *bgmac = netdev_priv(net_dev);
>>>> + u32 val;
>>>> +
>>>> + if (!bgmac->plat.nicpm_base)
>>>> + return;
>>>> +
>>>> + val = NICPM_IOMUX_CTRL_INIT_VAL;
>>>> + switch (bgmac->net_dev->phydev->speed) {
>>>> + default:
>>>> + pr_err("Unsupported speed. Defaulting to 1000Mb\n");
>>>> + case SPEED_1000:
>>>> + val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
>>>> + break;
>>>> + case SPEED_100:
>>>> + val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
>>>> + break;
>>>> + case SPEED_10:
>>>> + val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
>>>> + break;
>>>> + }
>>>> +
>>>> + writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
>>>> +
>>>> + usleep_range(10, 100);
>>>
>>> Does not seem like a good idea, do you need that sleep?
>>
>> Oops, that's not supposed to be there. Removed.
>>
>>
>>>> +
>>>> + bgmac_adjust_link(bgmac->net_dev);
>>>> +}
>>>> +
>>>> static int platform_phy_connect(struct bgmac *bgmac)
>>>> {
>>>> struct phy_device *phy_dev;
>>>>
>>>> - phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
>>>> - bgmac_adjust_link);
>>>> + if (bgmac->plat.nicpm_base)
>>>> + phy_dev = of_phy_get_and_connect(bgmac->net_dev,
>>>> + bgmac->dev->of_node,
>>>> + bgmac_nicpm_speed_set);
>>>> + else
>>>> + phy_dev = of_phy_get_and_connect(bgmac->net_dev,
>>>> + bgmac->dev->of_node,
>>>> + bgmac_adjust_link);
>>>> if (!phy_dev) {
>>>> dev_err(bgmac->dev, "Phy connect failed\n");
>>>> return -ENODEV;
>>>> }
>>>>
>>>> + if (bgmac->feature_flags & BGMAC_FEAT_LANE_SWAP)
>>>> + phy_dev->dev_flags |= PHY_BRCM_EXP_LANE_SWAP;
>>>> +
>>>> return 0;
>>>> }
>>>>
>>>> @@ -140,6 +188,9 @@ static int bgmac_probe(struct platform_device *pdev)
>>>>
>>>> platform_set_drvdata(pdev, bgmac);
>>>>
>>>> + if (of_property_read_bool(np, "brcm,enet-phy-lane-swap"))
>>>> + bgmac->feature_flags |= BGMAC_FEAT_LANE_SWAP;
>>>> +
>>>> /* Set the features of the 4707 family */
>>>> bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
>>>> bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
>>>> @@ -182,6 +233,14 @@ static int bgmac_probe(struct platform_device *pdev)
>>>> if (IS_ERR(bgmac->plat.idm_base))
>>>> return PTR_ERR(bgmac->plat.idm_base);
>>>>
>>>> + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
>>>> + if (regs) {
>>>> + bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
>>>> + regs);
>>>> + if (IS_ERR(bgmac->plat.nicpm_base))
>>>> + return PTR_ERR(bgmac->plat.nicpm_base);
>>>> + }
>>>> +
>>>> bgmac->read = platform_bgmac_read;
>>>> bgmac->write = platform_bgmac_write;
>>>> bgmac->idm_read = platform_bgmac_idm_read;
>>>> @@ -213,6 +272,7 @@ static int bgmac_remove(struct platform_device *pdev)
>>>> static const struct of_device_id bgmac_of_enet_match[] = {
>>>> {.compatible = "brcm,amac",},
>>>> {.compatible = "brcm,nsp-amac",},
>>>> + {.compatible = "brcm,ns2-amac",},
>>>> {},
>>>> };
>>>>
>>>> diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
>>>> index 38876ec..1796208 100644
>>>> --- a/drivers/net/ethernet/broadcom/bgmac.c
>>>> +++ b/drivers/net/ethernet/broadcom/bgmac.c
>>>> @@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
>>>> /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
>>>> static void bgmac_chip_init(struct bgmac *bgmac)
>>>> {
>>>> + /* Clear any erroneously pending interrupts */
>>>> + bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
>>>> +
>>>> /* 1 interrupt per received frame */
>>>> bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
>>>>
>>>> @@ -1158,8 +1161,6 @@ static int bgmac_open(struct net_device *net_dev)
>>>> struct bgmac *bgmac = netdev_priv(net_dev);
>>>> int err = 0;
>>>>
>>>> - bgmac_chip_reset(bgmac);
>>>> -
>>>
>>> Is this removal intentional? Maybe it should be special cased with
>>> checking for a NS2 BGMAC instance and not do it in that case?
>>
>> The reset seems completely unnecessary. There is already 2 resets in
>> the probe routine, another reset serves no purpose. I can add it
>> back, as it does not seem to have the negative effect I was seeing
>> before.
>
> After repeated ifconfig down/up, does Ethernet still work with this
> reset removed?
>
> Thanks.
>
Sorry, I meant to say, after removing both reset calls in the open and
close functions, does Ethernet still work after repeated ifconfig
down/up with data traffic in the background?
I would guess this reset is required, to flush out and clean up the
internal memories and state machine of the AMAC core each time before
you bring up the interface. It might also be required in the close
function, such that after the interface bring down, there's no staled
data coming out of the AMAC core. But I cannot say for sure since I do
not try this out myself.
Thanks.
>>
>> Of course, if I remove this one I should remove the reset in the close
>> too (which seems even more unnecessary, but I didn't remove it).
>>
>> Thanks,
>> Jon
>>
>>> --
>>> Florian
^ permalink raw reply
* [PATCH] [media] media: fix platform_no_drv_owner.cocci warnings
From: kbuild test robot @ 2016-10-27 22:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201610280623.yEQ4DZSc%fengguang.wu@intel.com>
drivers/media/platform/mtk-mdp/mtk_mdp_core.c:284:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
CC: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
mtk_mdp_core.c | 1 -
1 file changed, 1 deletion(-)
--- a/drivers/media/platform/mtk-mdp/mtk_mdp_core.c
+++ b/drivers/media/platform/mtk-mdp/mtk_mdp_core.c
@@ -281,7 +281,6 @@ static struct platform_driver mtk_mdp_dr
.remove = mtk_mdp_remove,
.driver = {
.name = MTK_MDP_MODULE_NAME,
- .owner = THIS_MODULE,
.pm = &mtk_mdp_pm_ops,
.of_match_table = mtk_mdp_of_ids,
}
^ permalink raw reply
* [PATCH 1/5] net: phy: broadcom: Add BCM54810 phy entry
From: Jon Mason @ 2016-10-27 22:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027091505.GB12841@lunn.ch>
On Thu, Oct 27, 2016 at 11:15:05AM +0200, Andrew Lunn wrote:
> On Wed, Oct 26, 2016 at 03:35:57PM -0400, Jon Mason wrote:
> > From: Vikas Soni <vsoni@broadcom.com>
> >
> > Add BCM54810 phy entry
>
> Hi Jon, Vikis
>
> The subject line is a bit misleading. It does more than add a PHY ID
> entry.
All of the parts are related to adding the BCM54810 Phy, but I agree it
could be more verbose about what is happening.
> > Signed-off-by: Vikas Soni <vsoni@broadcom.com>
> > Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> > ---
> > drivers/net/phy/Kconfig | 2 +-
> > drivers/net/phy/broadcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++
> > include/linux/brcmphy.h | 7 +++++
> > 3 files changed, 73 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > index 45f68ea..31967ca 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -217,7 +217,7 @@ config BROADCOM_PHY
> > select BCM_NET_PHYLIB
> > ---help---
> > Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
> > - BCM5481 and BCM5482 PHYs.
> > + BCM5481, BCM54810 and BCM5482 PHYs.
> >
> > config CICADA_PHY
> > tristate "Cicada PHYs"
> > diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
> > index 870327e..cdce761 100644
> > --- a/drivers/net/phy/broadcom.c
> > +++ b/drivers/net/phy/broadcom.c
> > @@ -35,6 +35,35 @@ static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
> > return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
> > }
> >
> > +static int bcm54810_config(struct phy_device *phydev)
> > +{
> > + int rc;
> > +
> > + /* Disable BroadR-Reach */
> > + rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL, 0);
> > + if (rc < 0)
> > + return rc;
> > +
> > + /* SKEW DISABLE */
> > + rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
> > + 0xF0E0);
> > + if (rc < 0)
> > + return rc;
> > +
> > + /* DELAY DISABLE */
> > + rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
> > + 0x7000);
>
> This driver mostly uses symbolic names, not #defines. Please can you
> use #defines here and else were in this patch.
Will do. After looking at this, this appears to be setup for a read
that doesn't follow. I'll audit this, clean it up and resend.
> > + if (rc < 0)
> > + return rc;
> > +
> > + /* DELAY DISABLE */
> > + rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, 0);
> > + if (rc < 0)
> > + return rc;
>
> Twice the same comment?
>
> > +
> > + return 0;
> > +}
> > +
> > /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
> > static int bcm50610_a0_workaround(struct phy_device *phydev)
> > {
> > @@ -207,6 +236,20 @@ static int bcm54xx_config_init(struct phy_device *phydev)
> > (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
> > bcm54xx_adjust_rxrefclk(phydev);
> >
> > + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
> > + err = bcm54810_config(phydev);
> > + if (err)
> > + return err;
> > +
> > + reg = phy_read(phydev, MII_BMCR);
> > + if (reg < 0)
> > + return reg;
> > +
> > + err = phy_write(phydev, MII_BMCR, reg & ~BMCR_PDOWN);
> > + if (err)
> > + return err;
>
> This seems a bit odd. I would expect the PHY core correctly handles
> the PHY being powered down. Can you explain this a bit more, why it is
> needed.
I believe it was needed in earlier versions of the code, but doesn't
seem to be needed anymore. Removing.
>
> Thanks
> Andrew
^ permalink raw reply
* [PATCH v7] spi: sun4i: Allow transfers larger than FIFO size
From: Mark Brown @ 2016-10-27 22:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027212727.leqg3gvwhd3u64er@lukather>
On Thu, Oct 27, 2016 at 11:27:27PM +0200, Maxime Ripard wrote:
> On Thu, Oct 27, 2016 at 12:14:19PM +0100, Mark Brown wrote:
> > but since I'm not turning up anything with this subject line I've no
> > idea what that might have been (and that's very concerning in itself
> > given that this is apparently v7...).
> v4 was here: https://patchwork.kernel.org/patch/3893371/
> v5: https://patchwork.kernel.org/patch/5455381/
> v6: https://patchwork.kernel.org/patch/6975871/
> So basically, I really have no idea why, but it really seems like it
> was just falling through the cracks, repeatedly (I'm not puting the
> blame on anyone though, it just happened). Maybe it was just because
> of the lack of comments :)
Oh, those subject lines were all starting ARM: rather than spi: -
there's a good chance I didn't look at the patches if I was busy
thinking they were changes for arch/arm rather than the SPI driver.
> > I'm also concerned that there isn't a version of this for sun6i,
> > it's going to make all the cut'n'pasting between the two drivers
> > harder if we make changes in one and not the other.
> I think I'll give reg_field a shot though, and try to merge the sun6i
> driver into this one and see the results. If it can help your
> decision.
It would definitely be nice given the level of duplication.
> > If the concern from the previous reviews to do with not using DMA is
> > there some reason it's hard to do DMA?
> I think just like Alexandru that it is orthogonal. But to really
> answer, no, it's not difficult. There's just been some fundamental
> disagreement on whether DMA was supposed to be optional or not that
> stalled everything I guess.
Oh, I seem to remember some patches adding DMA support that were doing
some strange special snowflake thing with ignoring errors now that I
think about it but that's not this one... why did nobody ever follow up
on those?
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