* [v13, 1/8] dt: bindings: update Freescale DCFG compatible
From: Yangbo Lu @ 2016-10-28 3:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477625554-46700-1-git-send-email-yangbo.lu@nxp.com>
Update Freescale DCFG compatible with 'fsl,<chip>-dcfg' instead
of 'fsl,ls1021a-dcfg' to include more chips such as ls1021a,
ls1043a, and ls2080a.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Scott Wood <oss@buserror.net>
---
Changes for v8:
- Added this patch
Changes for v9:
- Added a list for the possible compatibles
Changes for v10:
- None
Changes for v11:
- Added 'Acked-by: Rob Herring'
- Updated commit message by Scott
Changes for v12:
- None
Changes for v13:
- None
---
Documentation/devicetree/bindings/arm/fsl.txt | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index dbbc095..713c1ae 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -119,7 +119,11 @@ Freescale DCFG
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and startup.
Required properties:
- - compatible: should be "fsl,ls1021a-dcfg"
+ - compatible: should be "fsl,<chip>-dcfg"
+ Possible compatibles:
+ "fsl,ls1021a-dcfg"
+ "fsl,ls1043a-dcfg"
+ "fsl,ls2080a-dcfg"
- reg : should contain base address and length of DCFG memory-mapped registers
Example:
--
2.1.0.27.g96db324
^ permalink raw reply related
* [v13, 0/8] Fix eSDHC host version register bug
From: Yangbo Lu @ 2016-10-28 3:32 UTC (permalink / raw)
To: linux-arm-kernel
This patchset is used to fix a host version register bug in the T4240-R1.0-R2.0
eSDHC controller. To match the SoC version and revision, 10 previous version
patchsets had tried many methods but all of them were rejected by reviewers.
Such as
- dts compatible method
- syscon method
- ifdef PPC method
- GUTS driver getting SVR method
Anrd suggested a soc_device_match method in v10, and this is the only available
method left now. This v11 patchset introduces the soc_device_match interface in
soc driver.
The first six patches of Yangbo are to add the GUTS driver. This is used to
register a soc device which contain soc version and revision information.
The other two patches introduce the soc_device_match method in soc driver
and apply it on esdhc driver to fix this bug.
Arnd Bergmann (1):
base: soc: introduce soc_device_match() interface
Yangbo Lu (7):
dt: bindings: update Freescale DCFG compatible
ARM64: dts: ls2080a: add device configuration node
dt: bindings: move guts devicetree doc out of powerpc directory
powerpc/fsl: move mpc85xx.h to include/linux/fsl
soc: fsl: add GUTS driver for QorIQ platforms
MAINTAINERS: add entry for Freescale SoC drivers
mmc: sdhci-of-esdhc: fix host version for T4240-R1.0-R2.0
Documentation/devicetree/bindings/arm/fsl.txt | 6 +-
.../bindings/{powerpc => soc}/fsl/guts.txt | 3 +
MAINTAINERS | 11 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 6 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 2 +-
drivers/base/Kconfig | 1 +
drivers/base/soc.c | 66 ++++++
drivers/clk/clk-qoriq.c | 3 +-
drivers/i2c/busses/i2c-mpc.c | 2 +-
drivers/iommu/fsl_pamu.c | 3 +-
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-of-esdhc.c | 20 ++
drivers/net/ethernet/freescale/gianfar.c | 2 +-
drivers/soc/Kconfig | 3 +-
drivers/soc/fsl/Kconfig | 18 ++
drivers/soc/fsl/Makefile | 1 +
drivers/soc/fsl/guts.c | 236 +++++++++++++++++++++
include/linux/fsl/guts.h | 125 ++++++-----
.../asm/mpc85xx.h => include/linux/fsl/svr.h | 4 +-
include/linux/sys_soc.h | 3 +
21 files changed, 456 insertions(+), 62 deletions(-)
rename Documentation/devicetree/bindings/{powerpc => soc}/fsl/guts.txt (91%)
create mode 100644 drivers/soc/fsl/Kconfig
create mode 100644 drivers/soc/fsl/guts.c
rename arch/powerpc/include/asm/mpc85xx.h => include/linux/fsl/svr.h (97%)
--
2.1.0.27.g96db324
^ permalink raw reply
* [RFC PATCH v2 4/8] arm64: compat: Add a 32-bit vDSO
From: Jisheng Zhang @ 2016-10-28 3:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027163058.12156-5-kevin.brodsky@arm.com>
Dear Kevin,
On Thu, 27 Oct 2016 17:30:54 +0100 Kevin Brodsky wrote:
> Provide the files necessary for building a compat (AArch32) vDSO in
> kernel/vdso32.
>
> This is mostly an adaptation of the arm vDSO. The most significant
> change in vgettimeofday.c is the use of the arm64 vdso_data struct,
> allowing the vDSO data page to be shared between the 32 and 64-bit
> vDSOs.
>
> In addition to the time functions, sigreturn trampolines are also
> provided, aiming at replacing those in the vector page. To improve
> debugging, CFI and unwinding directives are used, based on glibc's
> implementation. Symbol offsets are made available to the kernel using
> the same method as the 64-bit vDSO.
>
> There is unfortunately an important caveat to all this: we cannot get
> away with hand-coding 32-bit instructions like in kernel/kuser32.S,
> this time we really need a 32-bit compiler. The compat vDSO Makefile
> relies on CROSS_COMPILE_ARM32 to provide a 32-bit compiler,
> appropriate logic will be added to the arm64 Makefile later on to
> ensure that an attempt to build the compat vDSO is made only if this
> variable has been set properly.
>
> Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
> ---
> arch/arm64/kernel/vdso32/Makefile | 121 +++++++++++++
> arch/arm64/kernel/vdso32/sigreturn.S | 86 +++++++++
> arch/arm64/kernel/vdso32/vdso.S | 32 ++++
> arch/arm64/kernel/vdso32/vdso.lds.S | 98 +++++++++++
> arch/arm64/kernel/vdso32/vgettimeofday.c | 294 +++++++++++++++++++++++++++++++
> 5 files changed, 631 insertions(+)
> create mode 100644 arch/arm64/kernel/vdso32/Makefile
> create mode 100644 arch/arm64/kernel/vdso32/sigreturn.S
> create mode 100644 arch/arm64/kernel/vdso32/vdso.S
> create mode 100644 arch/arm64/kernel/vdso32/vdso.lds.S
> create mode 100644 arch/arm64/kernel/vdso32/vgettimeofday.c
>
> diff --git a/arch/arm64/kernel/vdso32/Makefile b/arch/arm64/kernel/vdso32/Makefile
> new file mode 100644
> index 000000000000..38facc870f6e
> --- /dev/null
> +++ b/arch/arm64/kernel/vdso32/Makefile
> @@ -0,0 +1,121 @@
> +#
> +# Building a vDSO image for AArch32.
> +#
> +# Author: Kevin Brodsky <kevin.brodsky@arm.com>
> +# A mix between the arm64 and arm vDSO Makefiles.
> +
> +CC_ARM32 := $(CROSS_COMPILE_ARM32)gcc
> +
> +# Same as cc-ldoption, but using CC_ARM32 instead of CC
> +cc32-ldoption = $(call try-run,\
> + $(CC_ARM32) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
> +
> +# Borrow vdsomunge.c from the arm vDSO
> +munge := arch/arm/vdso/vdsomunge
> +hostprogs-y := $(srctree)/$(munge)
> +
> +c-obj-vdso := vgettimeofday.o
> +asm-obj-vdso := sigreturn.o
> +
> +# Build rules
> +targets := $(c-obj-vdso) $(asm-obj-vdso) vdso.so vdso.so.dbg vdso.so.raw
> +c-obj-vdso := $(addprefix $(obj)/, $(c-obj-vdso))
> +asm-obj-vdso := $(addprefix $(obj)/, $(asm-obj-vdso))
> +obj-vdso := $(c-obj-vdso) $(asm-obj-vdso)
> +
> +ccflags-y := -fPIC -fno-common -fno-builtin -fno-stack-protector
> +ccflags-y += -DDISABLE_BRANCH_PROFILING
> +
> +# Force -O2 to avoid libgcc dependencies
> +VDSO_CFLAGS := -march=armv8-a -O2
For completeness, bringing 32bit compiler need to check whether the 32bit
toolchain support some options. IIRC, armv8-a support isn't enabled until
gcc 4.8, so old toolchains such gcc-4.7 will complain:
error: unrecognized argument in option ?-march=armv8-a?
Thanks,
Jisheng
^ permalink raw reply
* [PATCH 1/2] of, numa: Add function to disable of_node_to_nid().
From: Leizhen (ThunderTown) @ 2016-10-28 1:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5810E112.3070908@caviumnetworks.com>
On 2016/10/27 1:00, David Daney wrote:
> On 10/26/2016 06:43 AM, Robert Richter wrote:
>> On 25.10.16 14:31:00, David Daney wrote:
>>> From: David Daney <david.daney@cavium.com>
>>>
>>> On arm64 NUMA kernels we can pass "numa=off" on the command line to
>>> disable NUMA. A side effect of this is that kmalloc_node() calls to
>>> non-zero nodes will crash the system with an OOPS:
>>>
>>> [ 0.000000] [<fffffc00081bba84>] __alloc_pages_nodemask+0xa4/0xe68
>>> [ 0.000000] [<fffffc00082163a8>] new_slab+0xd0/0x57c
>>> [ 0.000000] [<fffffc000821879c>] ___slab_alloc+0x2e4/0x514
>>> [ 0.000000] [<fffffc000823882c>] __slab_alloc+0x48/0x58
>>> [ 0.000000] [<fffffc00082195a0>] __kmalloc_node+0xd0/0x2e0
>>> [ 0.000000] [<fffffc00081119b8>] __irq_domain_add+0x7c/0x164
>>> [ 0.000000] [<fffffc0008b75d30>] its_probe+0x784/0x81c
>>> [ 0.000000] [<fffffc0008b75e10>] its_init+0x48/0x1b0
>>> .
>>> .
>>> .
>>>
>>> This is caused by code like this in kernel/irq/irqdomain.c
>>>
>>> domain = kzalloc_node(sizeof(*domain) + (sizeof(unsigned int) * size),
>>> GFP_KERNEL, of_node_to_nid(of_node));
>>>
>>> When NUMA is disabled, the concept of a node is really undefined, so
>>> of_node_to_nid() should unconditionally return NUMA_NO_NODE.
>>>
>>> Add __of_force_no_numa() to allow of_node_to_nid() to be forced to
>>> return NUMA_NO_NODE.
>>>
>>> The follow on patch will call this new function from the arm64 numa
>>> code.
>>
>> Didn't that work before?
>
> I am fairly certain that it used to work.
>
>> numa=off just maps all mem to node 0.
>
> Yes, that is the current behavior.
It just deal with the cpu nodes, but I think currently you added "numa-node-id" in the peripheral device(maybe ITS).
>
>> If mem
>> allocation is requested for another node it should just fall back to a
>> node with mem (node 0 then).
>
> This is the root of the problem. The ITS code is allocating memory. It calls of_node_to_nid() to determine which node it resides on. The answer in the failing case is node-1. Since we have mapped all the memory to node-0 the __kmalloc_node(..., 1) call fails with the OOPS shown.
>
> It could be that __kmalloc_node() used to allocate memory on a node other than the requested node if the request couldn't be met. But in v4.8 and later it produces that OOPS.
>
> If you pass a node containing free memory or NUMA_NO_NODE to __kmalloc_node(), the allocation succeeds.
>
> When we first did these patches, I advocated removing the numa=off feature, and requiring people to install usable firmware on their systems. That was rejected on the grounds that not everybody has the ability to change their firmware and we would like to allow NUMA kernels to run on systems with defective firmware by supplying this command line parameter. Now that I have seen requests from the wild for this, I think it is a good idea to allow numa=off to be used to work around this bad firmware.
>
> The change in this patch set is fairly small, and seems to get the job done. An alternative would be to change __kmalloc_node() to ignore the node parameter if the request cannot be made, but I assume that there were good reasons to have the current behavior, so that would be a much more complicated change to make.
>
>
>
>> I suspect there is something wrong with
>> the page initialization, see:
>>
>> http://www.spinics.net/lists/arm-kernel/msg535191.html
>> https://bugzilla.redhat.com/show_bug.cgi?id=1387793
>>
>> What is the complete oops?
>>
>> So I think k*alloc_node() must be able to handle requests to
>> non-existing nodes. Otherwise your fix is incomplete, assume a failed
>> of_numa_init() causing a dummy init but still some devices reporting a
>> node.
>
> .
> .
> .
> EFI stub: Booting Linux Kernel...
> EFI stub: Using DTB from configuration table
> EFI stub: Exiting boot services and installing virtual address map...
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.8.0-rc8-dd (ddaney at localhost.localdomain) (gcc version 4.8.5 20150623 (Red Hat 4.8.5-11) (GCC) ) #29 SMP Tue Sep 27 15:50:35 PDT 2016
> [ 0.000000] Boot CPU: AArch64 Processor [431f0a10]
> [ 0.000000] NUMA turned off
> [ 0.000000] earlycon: pl11 at MMIO 0x000087e024000000 (options '')
> [ 0.000000] bootconsole [pl11] enabled
> [ 0.000000] efi: Getting EFI parameters from FDT:
> [ 0.000000] efi: EFI v2.40 by Cavium Thunder cn88xx EFI jenkins_weekly_build_40-0-ga1f880f Sep 13 2016 17:05:35
> [ 0.000000] efi: ACPI=0xfffff000 ACPI 2.0=0xfffff014 SMBIOS 3.0=0x10ffafcf000
> [ 0.000000] cma: Reserved 512 MiB at 0x00000000c0000000
> [ 0.000000] NUMA disabled
> [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x0000010fffffffff]
> [ 0.000000] NUMA: Adding memblock [0x1400000 - 0xfffdffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0xfffe0000 - 0xffffffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0x100000000 - 0xfffffffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0x10000400000 - 0x10ffa38ffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0x10ffa390000 - 0x10ffa41ffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0x10ffa420000 - 0x10ffaeaffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0x10ffaeb0000 - 0x10ffaffffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0x10ffb000000 - 0x10ffffaffff] on node 0
> [ 0.000000] NUMA: Adding memblock [0x10ffffb0000 - 0x10fffffffff] on node 0
> [ 0.000000] NUMA: Initmem setup node 0 [mem 0x01400000-0x10fffffffff]
> [ 0.000000] NUMA: NODE_DATA [mem 0x10ffffae480-0x10ffffaff7f]
> [ 0.000000] Zone ranges:
> [ 0.000000] DMA [mem 0x0000000001400000-0x00000000ffffffff]
> [ 0.000000] Normal [mem 0x0000000100000000-0x0000010fffffffff]
> [ 0.000000] Movable zone start for each node
> [ 0.000000] Early memory node ranges
> [ 0.000000] node 0: [mem 0x0000000001400000-0x00000000fffdffff]
> [ 0.000000] node 0: [mem 0x00000000fffe0000-0x00000000ffffffff]
> [ 0.000000] node 0: [mem 0x0000000100000000-0x0000000fffffffff]
> [ 0.000000] node 0: [mem 0x0000010000400000-0x0000010ffa38ffff]
> [ 0.000000] node 0: [mem 0x0000010ffa390000-0x0000010ffa41ffff]
> [ 0.000000] node 0: [mem 0x0000010ffa420000-0x0000010ffaeaffff]
> [ 0.000000] node 0: [mem 0x0000010ffaeb0000-0x0000010ffaffffff]
> [ 0.000000] node 0: [mem 0x0000010ffb000000-0x0000010ffffaffff]
> [ 0.000000] node 0: [mem 0x0000010ffffb0000-0x0000010fffffffff]
> [ 0.000000] Initmem setup node 0 [mem 0x0000000001400000-0x0000010fffffffff]
> [ 0.000000] psci: probing for conduit method from DT.
> [ 0.000000] psci: PSCIv0.2 detected in firmware.
> [ 0.000000] psci: Using standard PSCI v0.2 function IDs
> [ 0.000000] psci: Trusted OS resident on physical CPU 0x0
> [ 0.000000] percpu: Embedded 3 pages/cpu @ffffff0ff6900000 s116736 r8192 d71680 u196608
> [ 0.000000] Detected VIPT I-cache on CPU0
> [ 0.000000] CPU features: enabling workaround for Cavium erratum 27456
> [ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 2094720
> [ 0.000000] Policy zone: Normal
> [ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-4.8.0-rc8-dd root=/dev/mapper/rhel-root ro crashkernel=auto rd.lvm.lv=rhel/root rd.lvm.lv=rhel/swap LANG=en_US.UTF-8 numa=off console=ttyAMA0,115200n8 earlycon=pl011,0x87e024000000
> [ 0.000000] log_buf_len individual max cpu contribution: 4096 bytes
> [ 0.000000] log_buf_len total cpu_extra contributions: 389120 bytes
> [ 0.000000] log_buf_len min size: 524288 bytes
> [ 0.000000] log_buf_len: 1048576 bytes
> [ 0.000000] early log buf free: 519176(99%)
> [ 0.000000] PID hash table entries: 4096 (order: -1, 32768 bytes)
> [ 0.000000] software IO TLB [mem 0xfbfd0000-0xfffd0000] (64MB) mapped at [fffffe00fbfd0000-fffffe00fffcffff]
> [ 0.000000] Memory: 133391936K/134193152K available (7356K kernel code, 1359K rwdata, 3392K rodata, 1216K init, 6799K bss, 276928K reserved, 524288K cma-reserved)
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] modules : 0xfffffc0000000000 - 0xfffffc0008000000 ( 128 MB)
> [ 0.000000] vmalloc : 0xfffffc0008000000 - 0xfffffdff5fff0000 ( 2045 GB)
> [ 0.000000] .text : 0xfffffc0008080000 - 0xfffffc00087b0000 ( 7360 KB)
> [ 0.000000] .rodata : 0xfffffc00087b0000 - 0xfffffc0008b10000 ( 3456 KB)
> [ 0.000000] .init : 0xfffffc0008b10000 - 0xfffffc0008c40000 ( 1216 KB)
> [ 0.000000] .data : 0xfffffc0008c40000 - 0xfffffc0008d93e00 ( 1360 KB)
> [ 0.000000] .bss : 0xfffffc0008d93e00 - 0xfffffc0009437d48 ( 6800 KB)
> [ 0.000000] fixed : 0xfffffdff7e7d0000 - 0xfffffdff7ec00000 ( 4288 KB)
> [ 0.000000] PCI I/O : 0xfffffdff7ee00000 - 0xfffffdff7fe00000 ( 16 MB)
> [ 0.000000] vmemmap : 0xfffffdff80000000 - 0xfffffe0000000000 ( 2 GB maximum)
> [ 0.000000] 0xfffffdff80005000 - 0xfffffdffc4000000 ( 1087 MB actual)
> [ 0.000000] memory : 0xfffffe0001400000 - 0xffffff1000000000 (1114092 MB)
> [ 0.000000] SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=96, Nodes=1
> [ 0.000000] Hierarchical RCU implementation.
> [ 0.000000] Build-time adjustment of leaf fanout to 64.
> [ 0.000000] RCU restricting CPUs from NR_CPUS=4096 to nr_cpu_ids=96.
> [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=96
> [ 0.000000] NR_IRQS:64 nr_irqs:64 0
> [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
> [ 0.000000] ITS: /interrupt-controller at 801000000000/gic-its at 801000020000
> [ 0.000000] ITS at 0x0000801000020000: allocated 2097152 Devices @10001000000 (flat, esz 8, psz 64K, shr 1)
> [ 0.000000] ITS: /interrupt-controller at 801000000000/gic-its at 901000020000
> [ 0.000000] ITS at 0x0000901000020000: allocated 2097152 Devices @10002000000 (flat, esz 8, psz 64K, shr 1)
> [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00001680
> [ 0.000000] pgd = fffffc0009470000
> [ 0.000000] [00001680] *pgd=0000010ffff90003, *pud=0000010ffff90003, *pmd=0000010ffff90003, *pte=0000000000000000
> [ 0.000000] Internal error: Oops: 96000006 [#1] SMP
> [ 0.000000] Modules linked in:
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.8.0-rc8-dd #29
> [ 0.000000] Hardware name: Cavium ThunderX CN88XX board (DT)
> [ 0.000000] task: fffffc0008c71c80 task.stack: fffffc0008c40000
> [ 0.000000] PC is at __alloc_pages_nodemask+0xa4/0xe68
> [ 0.000000] LR is at __alloc_pages_nodemask+0x38/0xe68
> [ 0.000000] pc : [<fffffc00081c8950>] lr : [<fffffc00081c88e4>] pstate: 600000c5
> [ 0.000000] sp : fffffc0008c43880
> [ 0.000000] x29: fffffc0008c43880 x28: ffffff000041fc00
> [ 0.000000] x27: 0000000000201200 x26: 0000000000000000
> [ 0.000000] x25: 0000000000000001 x24: 0000000000001680
> [ 0.000000] x23: 0000000000201200 x22: fffffc0008c439c8
> [ 0.000000] x21: fffffc0008c63000 x20: 0000000000201200
> [ 0.000000] x19: 0000000000000000 x18: 0000000000000070
> [ 0.000000] x17: 0000000000000008 x16: 0000000000000000
> [ 0.000000] x15: 0000000000000000 x14: 2820303030303030
> [ 0.000000] x13: 3230303031402073 x12: 6563697665442032
> [ 0.000000] x11: 0000000000000020 x10: fffffc0009334000
> [ 0.000000] x9 : 0000000001bfff3f x8 : 7f7f7f7f7f7f7f7f
> [ 0.000000] x7 : 0000000001210111 x6 : fffffdffc00010a0
> [ 0.000000] x5 : 0000000000000000 x4 : 0000000000000000
> [ 0.000000] x3 : 0000000000000000 x2 : 0000000000000000
> [ 0.000000] x1 : 0000000000000000 x0 : fffffc0008c63bb0
> [ 0.000000]
> [ 0.000000] Process swapper/0 (pid: 0, stack limit = 0xfffffc0008c40020)
> [ 0.000000] Stack: (0xfffffc0008c43880 to 0xfffffc0008c44000)
> [ 0.000000] 3880: fffffc0008c439f0 fffffc000821fa70 ffffff000041fc00 0000000000000200
> [ 0.000000] 38a0: fffffc0008115374 0000000000000000 0000000000000000 0000000000000001
> [ 0.000000] 38c0: 0000000000000000 0000000000000000 0000000000201200 ffffff000041fc00
> [ 0.000000] 38e0: fffffc0008c43960 fffffc000810bc20 fffffc0008c43960 fffffc0008c43960
> [ 0.000000] 3900: fffffc0008c43930 00000000ffffffd0 fffffc0008c43960 fffffc0008c43960
> [ 0.000000] 3920: fffffc0008c43930 00000000ffffffd0 fffffc0008c43970 fffffc0008221658
> [ 0.000000] 3940: 7f7f7f7f7f7f7f7f 0000000000000002 0101010101010101 0000000000000020
> [ 0.000000] 3960: fffffc0008c43a70 fffffc0008221c04 0000000000000001 00000000024080c0
> [ 0.000000] 3980: fffffc0008115374 fffffc0008bf8648 0000000000001000 0000000000000000
> [ 0.000000] 39a0: ffffff000041fc00 0000000000000001 ffffff0ff691e840 ffffff000041fc00
> [ 0.000000] 39c0: ffffff0ff691e840 0000000000001680 0000000000000000 0000000000000000
> [ 0.000000] 39e0: 0000000100000000 0000000000000000 fffffc0008c43a70 fffffc0008221e24
> [ 0.000000] 3a00: 0000000000000001 00000000024080c0 fffffc0008115374 fffffc0008bf8648
> [ 0.000000] 3a20: 0000000000001000 0000000000000000 0000000000000000 0000000000000001
> [ 0.000000] 3a40: ffffff0ff691e840 ffffff000041fc00 fffffc000928a1e8 024080c000000006
> [ 0.000000] 3a60: fffffc0008ca6a38 000000000000005c fffffc0008c43b90 fffffc0008239498
> [ 0.000000] 3a80: 00000000000000c0 ffffff000041fc00 ffffff0000424f00 0000000000000070
> [ 0.000000] 3aa0: 0000000000000001 fffffc0008115374 ffffff000041fc00 fffffc00093f1000
> [ 0.000000] 3ac0: ffffff0002000000 ffffff0000433000 fffffc0008c43bd0 fffffc0008a308f0
> [ 0.000000] 3ae0: 0000000000010000 0000020000000000 0000000000000000 0000000000000001
> [ 0.000000] 3b00: fffffc0008c43b30 fffffc000861f07c fffffc000941efc0 00000000000000c0
> [ 0.000000] 3b20: ffffff0ffff44e60 00000000000000c0 fffffc0008c43b70 fffffc000861f234
> [ 0.000000] 3b40: ffffff0ffff44e60 0000000000000004 ffffff0ffff44e60 fffffc0008c43c70
> [ 0.000000] 3b60: 0000000000000000 fffffc0008a74460 fffffc0008c43ba0 fffffc000861f3fc
> [ 0.000000] 3b80: fffffc0008c43ba0 fffffc00083ca55c fffffc0008c43bd0 fffffc0008222c20
> [ 0.000000] 3ba0: ffffff000041fc00 00000000024080c0 ffffff0ff691e840 fffffc0008115374
> [ 0.000000] 3bc0: 0000000000000001 00000000024080c0 fffffc0008c43c20 fffffc0008115374
> [ 0.000000] 3be0: 0000000000000070 ffffff0ffff44e80 ffffff0ffff44e60 0000000000000000
> [ 0.000000] 3c00: fffffc0008849a18 ffffffffffffffff 0000000000000000 ffffff0000433000
> [ 0.000000] 3c20: fffffc0008c43c80 fffffc0008b461dc ffffff0000424e80 2800000000000000
> [ 0.000000] 3c40: 0000000000010000 0000020000000000 0000000000000000 0000000000000400
> [ 0.000000] 3c60: 0000000000000400 ffffff00004330f8 0000000000000001 ffffff0ffffabe00
> [ 0.000000] 3c80: fffffc0008c43dc0 fffffc0008b462bc fffffc0008d33488 fffffc0008d33000
> [ 0.000000] 3ca0: ffffff0ffff44e60 fffffc0008c6c840 ffffff0000424b00 ffffff0000424880
> [ 0.000000] 3cc0: 0000000000000002 0000000000000000 0000000001bae074 0000000001f1001c
> [ 0.000000] 3ce0: 0000000000000000 fffffc0008a30890 ffffff0000424b00 fffffc0008849940
> [ 0.000000] 3d00: ffffff0000433020 fffffc0008a308f0 ffffff0000433008 ffffff0ffff44e60
> [ 0.000000] 3d20: fffffc000ac00000 0000000000000008 0000000000000001 8107000000000000
> [ 0.000000] 3d40: 00000000000000c0 0000000001000000 00000008fff44e60 0000010002000000
> [ 0.000000] 3d60: 0000000000000100 81070000000000ff fffffc0008c43dc0 0000000008b462cc
> [ 0.000000] 3d80: 0000901000020000 000090100021ffff ffffff0ffff44f08 0000000000000200
> [ 0.000000] 3da0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> [ 0.000000] 3dc0: fffffc0008c43e10 fffffc0008b4543c fffffc0008c6c828 fffffc0008d32000
> [ 0.000000] 3de0: fffffc0008c6c000 ffffff0ffff44470 fffffc0008849000 ffffff0000424880
> [ 0.000000] 3e00: fffffc0008c43e10 fffffc0008b45420 fffffc0008c43e60 fffffc0008b456bc
> [ 0.000000] 3e20: 0000000000000002 0000000000000003 0000000000000030 ffffff0000424880
> [ 0.000000] 3e40: ffffff0ffff44470 0000000000000000 0000000000000018 fffffc0008000000
> [ 0.000000] 3e60: fffffc0008c43f00 fffffc0008b5aec8 ffffff0000424700 fffffc0008c43f60
> [ 0.000000] 3e80: fffffc0008c43f60 0000000000000000 fffffc0008c43f70 fffffc0008d92000
> [ 0.000000] 3ea0: fffffc0008a734e0 fffffc0008a734b8 fffffc0008c43f00 0000000208b5ae3c
> [ 0.000000] 3ec0: 0000000000000000 00009010805fffff ffffff0ffff44518 0000000000000200
> [ 0.000000] 3ee0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> [ 0.000000] 3f00: fffffc0008c43f80 fffffc0008b43f9c fffffc0008c60000 fffffc0008b66628
> [ 0.000000] 3f20: fffffc0008b66628 fffffc0008dc0000 fffffc0008c60000 ffffff0ffffac580
> [ 0.000000] 3f40: 0000000002840000 0000000002870000 0000000000000020 0000000000000000
> [ 0.000000] 3f60: fffffc0008c43f60 fffffc0008c43f60 fffffc0008c43f70 fffffc0008c43f70
> [ 0.000000] 3f80: fffffc0008c43f90 fffffc0008b12d60 fffffc0008c43fa0 fffffc0008b10a3c
> [ 0.000000] 3fa0: 0000000000000000 fffffc0008b101c4 0000010ff7a35218 0000000000000e12
> [ 0.000000] 3fc0: 0000000021200000 0000000030d00980 0000000000000000 0000000001400000
> [ 0.000000] 3fe0: 0000000000000000 fffffc0008b66628 0000000000000000 0000000000000000
> [ 0.000000] Call trace:
> [ 0.000000] Exception stack(0xfffffc0008c436b0 to 0xfffffc0008c437e0)
> [ 0.000000] 36a0: 0000000000000000 0000040000000000
> [ 0.000000] 36c0: fffffc0008c43880 fffffc00081c8950 ffffff0ffffaf180 0000000000000003
> [ 0.000000] 36e0: fffffc0008c63000 00000000ffffffff 0000000000000001 0000000000000000
> [ 0.000000] 3700: fffffc0008c43720 fffffc00081e25cc 0000000000000000 0000000001bfff3f
> [ 0.000000] 3720: fffffc0008c43750 fffffc00081c8454 0000000000000012 0000000000000000
> [ 0.000000] 3740: fffffffffffffff8 0000000000000012 fffffc0008c63bb0 0000000000000000
> [ 0.000000] 3760: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> [ 0.000000] 3780: fffffdffc00010a0 0000000001210111 7f7f7f7f7f7f7f7f 0000000001bfff3f
> [ 0.000000] 37a0: fffffc0009334000 0000000000000020 6563697665442032 3230303031402073
> [ 0.000000] 37c0: 2820303030303030 0000000000000000 0000000000000000 0000000000000008
> [ 0.000000] [<fffffc00081c8950>] __alloc_pages_nodemask+0xa4/0xe68
> [ 0.000000] [<fffffc000821fa70>] new_slab+0xd0/0x564
> [ 0.000000] [<fffffc0008221e24>] ___slab_alloc+0x2e4/0x514
> [ 0.000000] [<fffffc0008239498>] __slab_alloc+0x48/0x58
> [ 0.000000] [<fffffc0008222c20>] __kmalloc_node+0xd0/0x2dc
> [ 0.000000] [<fffffc0008115374>] __irq_domain_add+0x7c/0x164
> [ 0.000000] [<fffffc0008b461dc>] its_probe+0x784/0x81c
> [ 0.000000] [<fffffc0008b462bc>] its_init+0x48/0x1b0
> [ 0.000000] [<fffffc0008b4543c>] gic_init_bases+0x228/0x360
> [ 0.000000] [<fffffc0008b456bc>] gic_of_init+0x148/0x1cc
> [ 0.000000] [<fffffc0008b5aec8>] of_irq_init+0x184/0x298
> [ 0.000000] [<fffffc0008b43f9c>] irqchip_init+0x14/0x38
> [ 0.000000] [<fffffc0008b12d60>] init_IRQ+0xc/0x30
> [ 0.000000] [<fffffc0008b10a3c>] start_kernel+0x240/0x3b8
> [ 0.000000] [<fffffc0008b101c4>] __primary_switched+0x30/0x6c
> [ 0.000000] Code: 912ec2a0 b9403809 0a0902fb 37b007db (f9400300)
> [ 0.000000] ---[ end trace 0000000000000000 ]---
> [ 0.000000] Kernel panic - not syncing: Fatal exception
> [ 0.000000] ---[ end Kernel panic - not syncing: Fatal exception
>
>
> Same thing on v4.8.x and v4.9-rc?
>
>
>
>
>>
>> -Robert
>>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> .
>
^ permalink raw reply
* [PATCH v2 1/2] arm64/numa: fix pcpu_cpu_distance() to get correct CPU proximity
From: Hanjun Guo @ 2016-10-28 1:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477037636-10077-1-git-send-email-guohanjun@huawei.com>
+Cc Robert, David.
On 2016/10/21 16:13, Hanjun Guo wrote:
> From: Yisheng Xie <xieyisheng1@huawei.com>
>
> The pcpu_build_alloc_info() function group CPUs according to their
> proximity, by call callback function @cpu_distance_fn from different
> ARCHs.
>
> For arm64 the callback of @cpu_distance_fn is
> pcpu_cpu_distance(from, to)
> -> node_distance(from, to)
> The @from and @to for function node_distance() should be nid.
>
> However, pcpu_cpu_distance() in arch/arm64/mm/numa.c just past the
> cpu id for @from and @to, and didn't convert to numa node id.
>
> For this incorrect cpu proximity get from ARCH, it may cause each CPU
> in one group and make group_cnt out of bound:
>
> setup_per_cpu_areas()
> pcpu_embed_first_chunk()
> pcpu_build_alloc_info()
> in pcpu_build_alloc_info, since cpu_distance_fn will return
> REMOTE_DISTANCE if we pass cpu ids (0,1,2...), so
> cpu_distance_fn(cpu, tcpu) > LOCAL_DISTANCE will wrongly be ture.
>
> This may results in triggering the BUG_ON(unit != nr_units) later:
>
> [ 0.000000] kernel BUG at mm/percpu.c:1916!
> [ 0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
> [ 0.000000] Modules linked in:
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.9.0-rc1-00003-g14155ca-dirty #26
> [ 0.000000] Hardware name: Hisilicon Hi1616 Evaluation Board (DT)
> [ 0.000000] task: ffff000008d6e900 task.stack: ffff000008d60000
> [ 0.000000] PC is at pcpu_embed_first_chunk+0x420/0x704
> [ 0.000000] LR is at pcpu_embed_first_chunk+0x3bc/0x704
> [ 0.000000] pc : [<ffff000008c754f4>] lr : [<ffff000008c75490>] pstate: 800000c5
> [ 0.000000] sp : ffff000008d63eb0
> [ 0.000000] x29: ffff000008d63eb0 [ 0.000000] x28: 0000000000000000
> [ 0.000000] x27: 0000000000000040 [ 0.000000] x26: ffff8413fbfcef00
> [ 0.000000] x25: 0000000000000042 [ 0.000000] x24: 0000000000000042
> [ 0.000000] x23: 0000000000001000 [ 0.000000] x22: 0000000000000046
> [ 0.000000] x21: 0000000000000001 [ 0.000000] x20: ffff000008cb3bc8
> [ 0.000000] x19: ffff8413fbfcf570 [ 0.000000] x18: 0000000000000000
> [ 0.000000] x17: ffff000008e49ae0 [ 0.000000] x16: 0000000000000003
> [ 0.000000] x15: 000000000000001e [ 0.000000] x14: 0000000000000004
> [ 0.000000] x13: 0000000000000000 [ 0.000000] x12: 000000000000006f
> [ 0.000000] x11: 00000413fbffff00 [ 0.000000] x10: 0000000000000004
> [ 0.000000] x9 : 0000000000000000 [ 0.000000] x8 : 0000000000000001
> [ 0.000000] x7 : ffff8413fbfcf63c [ 0.000000] x6 : ffff000008d65d28
> [ 0.000000] x5 : ffff000008d65e50 [ 0.000000] x4 : 0000000000000000
> [ 0.000000] x3 : ffff000008cb3cc8 [ 0.000000] x2 : 0000000000000040
> [ 0.000000] x1 : 0000000000000040 [ 0.000000] x0 : 0000000000000000
> [...]
> [ 0.000000] Call trace:
> [ 0.000000] Exception stack(0xffff000008d63ce0 to 0xffff000008d63e10)
> [ 0.000000] 3ce0: ffff8413fbfcf570 0001000000000000 ffff000008d63eb0 ffff000008c754f4
> [ 0.000000] 3d00: ffff000008d63d50 ffff0000081af210 00000413fbfff010 0000000000001000
> [ 0.000000] 3d20: ffff000008d63d50 ffff0000081af220 00000413fbfff010 0000000000001000
> [ 0.000000] 3d40: 00000413fbfcef00 0000000000000004 ffff000008d63db0 ffff0000081af390
> [ 0.000000] 3d60: 00000413fbfcef00 0000000000001000 0000000000000000 0000000000001000
> [ 0.000000] 3d80: 0000000000000000 0000000000000040 0000000000000040 ffff000008cb3cc8
> [ 0.000000] 3da0: 0000000000000000 ffff000008d65e50 ffff000008d65d28 ffff8413fbfcf63c
> [ 0.000000] 3dc0: 0000000000000001 0000000000000000 0000000000000004 00000413fbffff00
> [ 0.000000] 3de0: 000000000000006f 0000000000000000 0000000000000004 000000000000001e
> [ 0.000000] 3e00: 0000000000000003 ffff000008e49ae0
> [ 0.000000] [<ffff000008c754f4>] pcpu_embed_first_chunk+0x420/0x704
> [ 0.000000] [<ffff000008c6658c>] setup_per_cpu_areas+0x38/0xc8
> [ 0.000000] [<ffff000008c608d8>] start_kernel+0x10c/0x390
> [ 0.000000] [<ffff000008c601d8>] __primary_switched+0x5c/0x64
> [ 0.000000] Code: b8018660 17ffffd7 6b16037f 54000080 (d4210000)
> [ 0.000000] ---[ end trace 0000000000000000 ]---
> [ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
>
> Fix by getting cpu's node id with early_cpu_to_node() then pass it
> to node_distance() as the original intention.
>
> Fixes: 7af3a0a99252 ("arm64/numa: support HAVE_SETUP_PER_CPU_AREA")
> Signed-off-by: Yisheng Xie <xieyisheng1@huawei.com>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> arch/arm64/mm/numa.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/mm/numa.c b/arch/arm64/mm/numa.c
> index 778a985..9a71d06 100644
> --- a/arch/arm64/mm/numa.c
> +++ b/arch/arm64/mm/numa.c
> @@ -147,7 +147,7 @@ static int __init early_cpu_to_node(int cpu)
>
> static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
> {
> - return node_distance(from, to);
> + return node_distance(early_cpu_to_node(from), early_cpu_to_node(to));
> }
>
> static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size,
>
^ permalink raw reply
* [PATCH v3 2/2] clk: imx: improve precision of AV PLL to 1 Hz
From: Stephen Boyd @ 2016-10-28 1:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <66f5967187f915fe7039f4dbfb77db88a2423094.1476267249.git.emil@limesaudio.com>
On 10/12, Emil Lundmark wrote:
> The audio and video PLLs are designed to have a precision of 1 Hz if some
> conditions are met. The current implementation only allows a precision that
> depends on the rate of the parent clock. E.g., if the parent clock is 24
> MHz, the precision will be 24 Hz; or more generally the precision will be
>
> p / 10^6 Hz
>
> where p is the parent clock rate. This comes down to how the register
> values for the PLL's fractional loop divider are chosen.
>
> The clock rate calculation for the PLL is
>
> PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM)
>
> or with a shorter notation
>
> r = p * (d + a / b)
>
> In addition to all variables being integers, we also have the following
> conditions:
>
> 27 <= d <= 54
>
> -2^29 <= a <= 2^29-1
> 0 < b <= 2^30-1
> |a| < b
>
> Here, d, a and b are register values for the fractional loop divider. We
> want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate
> function. Currently, d and b are chosen as
>
> d = r / p
> b = 10^6
>
> hence we get the poor precision. And a is defined in terms of r, d, p and
> b:
>
> a = (r - d * p) * b / p
>
> I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as
>
> b = p
>
> We can do this since
>
> |a| < b
>
> |(r - d * p) * b / p| < b
>
> |r - d * p| < p
>
> Which have two solutions, one of them is when p < 0, so we can skip that
> one. The other is when p > 0 and
>
> p * (d - 1) < r < p * (d + 1)
>
> Substitute d = r / p:
>
> (r - p) < r < (r + p) <=> p > 0
>
> So, as long as p > 0, we can chose b = p. This is a good choise for b since
>
> a = (r - d * p) * b / p
> = (r - d * p) * p / p
> = r - d * p
>
> r = p * (d + a / b)
> = p * d + p * a / b
> = p * d + p * a / p
> = p * d + a
>
> and if d = r / p:
>
> a = r - d * p
> = r - r / p * p
> = 0
>
> r = p * d + a
> = p * d + 0
> = p * r / p
> = r
>
> I reckon this is the intention by the design of the clock rate formula.
>
> Signed-off-by: Emil Lundmark <emil@limesaudio.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 1/2] clk: imx: fix integer overflow in AV PLL round rate
From: Stephen Boyd @ 2016-10-28 1:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4d2e3a91dfb74209735c940b51d7efc9ba2ed69b.1476267249.git.emil@limesaudio.com>
On 10/12, Emil Lundmark wrote:
> Since 'parent_rate * mfn' may overflow 32 bits, the result should be
> stored using 64 bits.
>
> The problem was discovered when trying to set the rate of the audio PLL
> (pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but
> the actual rate returned was 192.000570 MHz. The round rate function should
> have been able to return 196.608 MHz, i.e., the desired rate.
>
> Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula")
> Cc: Anson Huang <b20788@freescale.com>
> Signed-off-by: Emil Lundmark <emil@limesaudio.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 3/3] clk: stm32f469: Add QSPI clock
From: Stephen Boyd @ 2016-10-28 1:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477041810-12313-4-git-send-email-gabriel.fernandez@st.com>
On 10/21, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> This patch adds the QSPI clock for stm32f469 discovery board.
> The gate mapping is a little bit different from stm32f429 soc.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
Applied to clk-next + added Rob's ack from v2.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 2/3] clk: stm32f4: Add RTC clock
From: Stephen Boyd @ 2016-10-28 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477041810-12313-3-git-send-email-gabriel.fernandez@st.com>
On 10/21, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> This patch introduces the support of the RTC clock.
> RTC clock can have 3 sources: lsi, lse and hse_rtc.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 1/3] clk: stm32f4: Add LSI & LSE clocks
From: Stephen Boyd @ 2016-10-28 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477041810-12313-2-git-send-email-gabriel.fernandez@st.com>
On 10/21, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> This patch introduces the support of the LSI & LSE clocks.
> The clock drivers needs to disable the power domain write protection
> using syscon/regmap to enable these clocks.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
Applied to clk-next +
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index c2661e28eeda..5eb05dbf59b8 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -224,7 +224,7 @@ static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0x0000000000000003ull,
0x0c777f33f6fec9ffull };
-const u64 *stm32f4_gate_map;
+static const u64 *stm32f4_gate_map;
static struct clk_hw **clks;
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v14 1/4] clk: mediatek: Add MT2701 clock support
From: Stephen Boyd @ 2016-10-28 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477020742-13889-2-git-send-email-erin.lo@mediatek.com>
On 10/21, Erin Lo wrote:
> diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/clk-mt2701-bdp.c
> new file mode 100644
> index 0000000..dbf6ab2
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c
> @@ -0,0 +1,148 @@
> +
> +static int mtk_bdpsys_init(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> +
> + mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> + clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + return r;
> +}
> +
> +static const struct of_device_id of_match_clk_mt2701_bdp[] = {
> + { .compatible = "mediatek,mt2701-bdpsys", },
> + {}
> +};
> +
> +static int clk_mt2701_bdp_probe(struct platform_device *pdev)
> +{
> + int r;
> +
> + r = mtk_bdpsys_init(pdev);
Why not just put the contents of that function here? I don't see
the point of this.
> + if (r) {
> + dev_err(&pdev->dev,
> + "could not register clock provider: %s: %d\n",
> + pdev->name, r);
> + }
> +
> + return r;
> +}
> +
> +static struct platform_driver clk_mt2701_bdp_drv = {
> + .probe = clk_mt2701_bdp_probe,
> + .driver = {
> + .name = "clk-mt2701-bdp",
> + .of_match_table = of_match_clk_mt2701_bdp,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt2701_bdp_drv);
> diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
> new file mode 100644
> index 0000000..b2a71a4
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt2701-eth.c
> @@ -0,0 +1,90 @@
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: Shunli Wang <shunli.wang@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt2701-clk.h>
> +
> +static const struct mtk_gate_regs eth_cg_regs = {
> + .sta_ofs = 0x0030,
> +};
> +
> +#define GATE_ETH(_id, _name, _parent, _shift) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = ð_cg_regs, \
> + .shift = _shift, \
> + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
> + }
> +
> +static const struct mtk_gate eth_clks[] = {
> + GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
> + GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
> + GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
> + GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
> + GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
> + GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
> + GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
> + GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
> +};
> +
> +static int mtk_ethsys_init(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
> +
> + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
> + clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + return r;
Just return of_clk_add_provider() please.
> +}
> +
> +static const struct of_device_id of_match_clk_mt2701_eth[] = {
> + { .compatible = "mediatek,mt2701-ethsys", },
> + {}
> +};
> +
> +static int clk_mt2701_eth_probe(struct platform_device *pdev)
> +{
> + int r;
> +
> + r = mtk_ethsys_init(pdev);
Same comment.
> + if (r) {
> + dev_err(&pdev->dev,
> + "could not register clock provider: %s: %d\n",
> + pdev->name, r);
> + }
> +
> + return r;
> +}
> +
> +static struct platform_driver clk_mt2701_eth_drv = {
> + .probe = clk_mt2701_eth_probe,
> + .driver = {
> + .name = "clk-mt2701-eth",
> + .of_match_table = of_match_clk_mt2701_eth,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt2701_eth_drv);
> diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
> new file mode 100644
> index 0000000..e2b0039
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt2701-hif.c
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: Shunli Wang <shunli.wang@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt2701-clk.h>
> +
> +static const struct mtk_gate_regs hif_cg_regs = {
> + .sta_ofs = 0x0030,
> +};
> +
> +#define GATE_HIF(_id, _name, _parent, _shift) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = &hif_cg_regs, \
> + .shift = _shift, \
> + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
> + }
> +
> +static const struct mtk_gate hif_clks[] = {
> + GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
> + GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
> + GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
> + GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
> + GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
> +};
> +
> +static int mtk_hifsys_init(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
> +
> + mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
> + clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + return r;
Just return of_clk_add_provider() please.
> +}
> +
> +static const struct of_device_id of_match_clk_mt2701_hif[] = {
> + { .compatible = "mediatek,mt2701-hifsys", },
> + {}
> +};
> +
> +static int clk_mt2701_hif_probe(struct platform_device *pdev)
> +{
> + int r;
> +
> + r = mtk_hifsys_init(pdev);
There's a pattern. Same comments apply for everything that uses
this style.
> + if (r) {
> + dev_err(&pdev->dev,
> + "could not register clock provider: %s: %d\n",
> + pdev->name, r);
> + }
> +
> + return r;
> +}
> +
> +static struct platform_driver clk_mt2701_hif_drv = {
> + .probe = clk_mt2701_hif_probe,
> + .driver = {
> + .name = "clk-mt2701-hif",
> + .of_match_table = of_match_clk_mt2701_hif,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt2701_hif_drv);
[cut a bunch of same drivers]
> diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
> new file mode 100644
> index 0000000..c225256
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt2701.c
> @@ -0,0 +1,1046 @@
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: Shunli Wang <shunli.wang@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt2701-clk.h>
> +
> +/*
> + * For some clocks, we don't care what their actual rates are. And these
> + * clocks may change their rate on different products or different scenarios.
> + * So we model these clocks' rate as 0, to denote it's not an actual rate.
> + */
> +#define DUMMY_RATE 0
> +
> +static DEFINE_SPINLOCK(lock);
Please name this something more mtk specific. mt2701_clk_lock?
> +
> +static const struct mtk_fixed_clk top_fixed_clks[] = {
> + FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
> + 108 * MHZ),
> + FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
> + 400 * MHZ),
> + FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
> + 295750000),
> + FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
> + 340 * MHZ),
> + FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
> + 340 * MHZ),
> + FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
> + 340 * MHZ),
> + FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
> + 300 * MHZ),
> + FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
> + 27 * MHZ),
> + FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
> + 416 * MHZ),
> + FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
> + 143 * MHZ),
> + FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
> + 27 * MHZ),
> + FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
> + DUMMY_RATE),
> + FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
> + DUMMY_RATE),
> + FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
> + DUMMY_RATE),
> +};
> +
> +static const struct mtk_fixed_factor top_fixed_divs[] = {
> + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
> + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
> + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
> + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
> + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
> + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
> + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
> + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
> + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
> + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
> + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
> + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
> + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
> + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
> + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
> + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
> +
> + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
> + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
> + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
> + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
> + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
> + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
> + FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
> + FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
> + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
> + FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
> + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
> + FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
> + FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
> + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
> +
> + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
> + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
> + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
> + FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
> +
> + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
> + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
> +
> + FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
> + FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
> + FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
> +
> + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
> + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
> + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
> +
> + FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
> + FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
> + FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
> +
> + FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
> + FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
> + FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
> +
> + FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
> + FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
> + FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
> +
> + FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
> +
> + FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
> + FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
> + FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
> + FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
> + FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
> +
> + FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
> + FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
> + FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
> + FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
> + FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
> + FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
> + FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
> + FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
> +};
> +
> +static const char * const axi_parents[] = {
> + "clk26m",
> + "syspll1_d2",
> + "syspll_d5",
> + "syspll1_d4",
> + "univpll_d5",
> + "univpll2_d2",
> + "mmpll_d2",
> + "dmpll_d2"
> +};
> +
> +static const char * const mem_parents[] = {
> + "clk26m",
> + "dmpll_ck"
> +};
> +
> +static const char * const ddrphycfg_parents[] = {
> + "clk26m",
> + "syspll1_d8"
> +};
> +
> +static const char * const mm_parents[] = {
> + "clk26m",
> + "vencpll_ck",
> + "syspll1_d2",
> + "syspll1_d4",
> + "univpll_d5",
> + "univpll1_d2",
> + "univpll2_d2",
> + "dmpll_ck"
> +};
> +
> +static const char * const pwm_parents[] = {
> + "clk26m",
> + "univpll2_d4",
> + "univpll3_d2",
> + "univpll1_d4",
> +};
> +
> +static const char * const vdec_parents[] = {
> + "clk26m",
> + "vdecpll_ck",
> + "syspll_d5",
> + "syspll1_d4",
> + "univpll_d5",
> + "univpll2_d2",
> + "vencpll_ck",
> + "msdcpll_d2",
> + "mmpll_d2"
> +};
> +
> +static const char * const mfg_parents[] = {
> + "clk26m",
> + "mmpll_ck",
> + "dmpll_x2_ck",
> + "msdcpll_ck",
> + "clk26m",
> + "syspll_d3",
> + "univpll_d3",
> + "univpll1_d2"
> +};
> +
> +static const char * const camtg_parents[] = {
> + "clk26m",
> + "univpll_d26",
> + "univpll2_d2",
> + "syspll3_d2",
> + "syspll3_d4",
> + "msdcpll_d2",
> + "mmpll_d2"
> +};
> +
> +static const char * const uart_parents[] = {
> + "clk26m",
> + "univpll2_d8"
> +};
> +
> +static const char * const spi_parents[] = {
> + "clk26m",
> + "syspll3_d2",
> + "syspll4_d2",
> + "univpll2_d4",
> + "univpll1_d8"
> +};
> +
> +static const char * const usb20_parents[] = {
> + "clk26m",
> + "univpll1_d8",
> + "univpll3_d4"
> +};
> +
> +static const char * const msdc30_parents[] = {
> + "clk26m",
> + "msdcpll_d2",
> + "syspll2_d2",
> + "syspll1_d4",
> + "univpll1_d4",
> + "univpll2_d4"
> +};
> +
> +static const char * const audio_parents[] = {
> + "clk26m",
> + "syspll1_d16"
> +};
> +
> +static const char * const aud_intbus_parents[] = {
> + "clk26m",
> + "syspll1_d4",
> + "syspll3_d2",
> + "syspll4_d2",
> + "univpll3_d2",
> + "univpll2_d4"
> +};
> +
> +static const char * const pmicspi_parents[] = {
> + "clk26m",
> + "syspll1_d8",
> + "syspll2_d4",
> + "syspll4_d2",
> + "syspll3_d4",
> + "syspll2_d8",
> + "syspll1_d16",
> + "univpll3_d4",
> + "univpll_d26",
> + "dmpll_d2",
> + "dmpll_d4"
> +};
> +
> +static const char * const scp_parents[] = {
> + "clk26m",
> + "syspll1_d8",
> + "dmpll_d2",
> + "dmpll_d4"
> +};
> +
> +static const char * const dpi0_parents[] = {
> + "clk26m",
> + "mipipll",
> + "mipipll_d2",
> + "mipipll_d4",
> + "clk26m",
> + "tvdpll_ck",
> + "tvdpll_d2",
> + "tvdpll_d4"
> +};
> +
> +static const char * const dpi1_parents[] = {
> + "clk26m",
> + "tvdpll_ck",
> + "tvdpll_d2",
> + "tvdpll_d4"
> +};
> +
> +static const char * const tve_parents[] = {
> + "clk26m",
> + "mipipll",
> + "mipipll_d2",
> + "mipipll_d4",
> + "clk26m",
> + "tvdpll_ck",
> + "tvdpll_d2",
> + "tvdpll_d4"
> +};
> +
> +static const char * const hdmi_parents[] = {
> + "clk26m",
> + "hdmipll_ck",
> + "hdmipll_d2",
> + "hdmipll_d3"
> +};
> +
> +static const char * const apll_parents[] = {
> + "clk26m",
> + "audpll",
> + "audpll_d4",
> + "audpll_d8",
> + "audpll_d16",
> + "audpll_d24",
> + "clk26m",
> + "clk26m"
> +};
> +
> +static const char * const rtc_parents[] = {
> + "32k_internal",
> + "32k_external",
> + "clk26m",
> + "univpll3_d8"
> +};
> +
> +static const char * const nfi2x_parents[] = {
> + "clk26m",
> + "syspll2_d2",
> + "syspll_d7",
> + "univpll3_d2",
> + "syspll2_d4",
> + "univpll3_d4",
> + "syspll4_d4",
> + "clk26m"
> +};
> +
> +static const char * const emmc_hclk_parents[] = {
> + "clk26m",
> + "syspll1_d2",
> + "syspll1_d4",
> + "syspll2_d2"
> +};
> +
> +static const char * const flash_parents[] = {
> + "clk26m_d8",
> + "clk26m",
> + "syspll2_d8",
> + "syspll3_d4",
> + "univpll3_d4",
> + "syspll4_d2",
> + "syspll2_d4",
> + "univpll2_d4"
> +};
> +
> +static const char * const di_parents[] = {
> + "clk26m",
> + "tvd2pll_ck",
> + "tvd2pll_d2",
> + "clk26m"
> +};
> +
> +static const char * const nr_osd_parents[] = {
> + "clk26m",
> + "vencpll_ck",
> + "syspll1_d2",
> + "syspll1_d4",
> + "univpll_d5",
> + "univpll1_d2",
> + "univpll2_d2",
> + "dmpll_ck"
> +};
> +
> +static const char * const hdmirx_bist_parents[] = {
> + "clk26m",
> + "syspll_d3",
> + "clk26m",
> + "syspll1_d16",
> + "syspll4_d2",
> + "syspll1_d4",
> + "vencpll_ck",
> + "clk26m"
> +};
> +
> +static const char * const intdir_parents[] = {
> + "clk26m",
> + "mmpll_ck",
> + "syspll_d2",
> + "univpll_d2"
> +};
> +
> +static const char * const asm_parents[] = {
> + "clk26m",
> + "univpll2_d4",
> + "univpll2_d2",
> + "syspll_d5"
> +};
> +
> +static const char * const ms_card_parents[] = {
> + "clk26m",
> + "univpll3_d8",
> + "syspll4_d4"
> +};
> +
> +static const char * const ethif_parents[] = {
> + "clk26m",
> + "syspll1_d2",
> + "syspll_d5",
> + "syspll1_d4",
> + "univpll_d5",
> + "univpll1_d2",
> + "dmpll_ck",
> + "dmpll_d2"
> +};
> +
> +static const char * const hdmirx_parents[] = {
> + "clk26m",
> + "univpll_d52"
> +};
> +
> +static const char * const cmsys_parents[] = {
> + "clk26m",
> + "syspll1_d2",
> + "univpll1_d2",
> + "univpll_d5",
> + "syspll_d5",
> + "syspll2_d2",
> + "syspll1_d4",
> + "syspll3_d2",
> + "syspll2_d4",
> + "syspll1_d8",
> + "clk26m",
> + "clk26m",
> + "clk26m",
> + "clk26m",
> + "clk26m"
> +};
> +
> +static const char * const clk_8bdac_parents[] = {
> + "32k_internal",
> + "8bdac_ck",
> + "clk26m",
> + "clk26m"
> +};
> +
> +static const char * const aud2dvd_parents[] = {
> + "a1sys_hp_ck",
> + "a2sys_hp_ck"
> +};
> +
> +static const char * const padmclk_parents[] = {
> + "clk26m",
> + "univpll_d26",
> + "univpll_d52",
> + "univpll_d108",
> + "univpll2_d8",
> + "univpll2_d16",
> + "univpll2_d32"
> +};
> +
> +static const char * const aud_mux_parents[] = {
> + "clk26m",
> + "aud1pll_98m_ck",
> + "aud2pll_90m_ck",
> + "hadds2pll_98m",
> + "audio_ext1_ck",
> + "audio_ext2_ck"
> +};
> +
> +static const char * const aud_src_parents[] = {
> + "aud_mux1_sel",
> + "aud_mux2_sel"
> +};
> +
> +static const char * const cpu_parents[] = {
> + "clk26m",
> + "armpll",
> + "mainpll",
> + "mmpll"
> +};
> +
> +static const struct mtk_composite top_muxes[] = {
> + MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
> + 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
> + MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
> + 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
> + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
> + ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
> + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
> + 0x0040, 24, 3, 31),
> +
> + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
> + 0x0050, 0, 2, 7),
> + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
> + 0x0050, 8, 4, 15),
> + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
> + 0x0050, 16, 3, 23),
> + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
> + 0x0050, 24, 3, 31),
> + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
> + 0x0060, 0, 1, 7),
> +
> + MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
> + 0x0060, 8, 3, 15),
> + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
> + 0x0060, 16, 2, 23),
> + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
> + 0x0060, 24, 3, 31),
> +
> + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
> + 0x0070, 0, 3, 7),
> + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
> + 0x0070, 8, 3, 15),
> + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
> + 0x0070, 16, 1, 23),
> + MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
> + 0x0070, 24, 3, 31),
> +
> + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
> + 0x0080, 0, 4, 7),
> + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
> + 0x0080, 8, 2, 15),
> + MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
> + 0x0080, 16, 3, 23),
> + MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
> + 0x0080, 24, 2, 31),
> +
> + MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
> + 0x0090, 0, 3, 7),
> + MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
> + 0x0090, 8, 2, 15),
> + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
> + 0x0090, 16, 3, 23),
> +
> + MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
> + 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
> + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
> + 0x00A0, 8, 3, 15),
> + MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
> + 0x00A0, 24, 2, 31),
> +
> + MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
> + 0x00B0, 0, 3, 7),
> + MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
> + 0x00B0, 8, 2, 15),
> + MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
> + 0x00B0, 16, 3, 23),
> + MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
> + 0x00B0, 24, 3, 31),
> +
> + MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
> + hdmirx_bist_parents, 0x00C0, 0, 3, 7),
> + MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
> + 0x00C0, 8, 2, 15),
> + MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
> + 0x00C0, 16, 2, 23),
> + MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
> + 0x00C0, 24, 3, 31),
> +
> + MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
> + 0x00D0, 0, 2, 7),
> + MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
> + 0x00D0, 16, 2, 23),
> + MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
> + 0x00D0, 24, 3, 31),
> +
> + MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
> + 0x00E0, 0, 1, 7),
> + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
> + 0x00E0, 8, 3, 15),
> + MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
> + 0x00E0, 16, 4, 23),
> +
> + MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
> + 0x00E0, 24, 3, 31),
> + MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
> + 0x00F0, 0, 3, 7),
> + MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
> + 0x00F0, 8, 2, 15),
> + MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
> + 0x00F0, 16, 1, 23),
> +
> + MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
> + 0x0100, 0, 3),
> +
> + MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
> + 0x012c, 0, 3),
> + MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
> + 0x012c, 3, 3),
> + MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
> + 0x012c, 6, 3),
> + MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
> + 0x012c, 15, 1, 23),
> + MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
> + 0x012c, 16, 1, 24),
> + MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
> + 0x012c, 17, 1, 25),
> + MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
> + 0x012c, 18, 1, 26),
> + MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
> + 0x012c, 19, 1, 27),
> + MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
> + 0x012c, 20, 1, 28),
> +};
> +
> +static const struct mtk_clk_divider top_adj_divs[] = {
> + DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
> + 0x0120, 0, 8),
> + DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
> + 0x0120, 8, 8),
> + DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
> + 0x0120, 16, 8),
> + DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
> + 0x0120, 24, 8),
> + DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
> + 0x0124, 0, 8),
> + DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
> + 0x0124, 8, 8),
> + DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
> + 0x0124, 16, 8),
> + DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
> + 0x0124, 24, 8),
> + DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
> + 0x0128, 0, 8),
> + DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
> + 0x0128, 8, 8),
> +};
> +
> +static const struct mtk_gate_regs top_aud_cg_regs = {
> + .sta_ofs = 0x012C,
> +};
> +
> +#define GATE_TOP_AUD(_id, _name, _parent, _shift) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = &top_aud_cg_regs, \
> + .shift = _shift, \
> + .ops = &mtk_clk_gate_ops_no_setclr, \
> + }
> +
> +static const struct mtk_gate top_clks[] = {
> + GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
> + 21),
> + GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
> + 22),
> + GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
> + 23),
> + GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
> + 24),
> + GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
> + 25),
> + GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
> + 26),
> + GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
> + 27),
> + GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
> + 28),
> +};
> +
> +void __iomem *devm_of_iomap(struct device *dev, int index)
Sorry what is this?
> +{
> + struct resource res;
> +
> + if (!dev)
> + return NULL;
> +
> + if (of_address_to_resource(dev->of_node, index, &res))
> + return NULL;
> +
> + return devm_ioremap(dev, res.start, resource_size(&res));
Can't we just use platform_get_resouce() and
devm_ioremap_resource() here? It looks like we always have a
platform device.
> +}
> +
> +static int mtk_topckgen_init(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + void __iomem *base;
> + int r;
> + struct device_node *node = pdev->dev.of_node;
> +
> + base = devm_of_iomap(&pdev->dev, 0);
> + if (!base)
> + return -ENOMEM;
> +
> + clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
> +
> + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
> + clk_data);
> +
> + mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
> + clk_data);
> +
> + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
> + base, &lock, clk_data);
> +
> + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
> + base, &lock, clk_data);
> +
> + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
> + clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + return r;
> +}
> +
> +static const struct mtk_gate_regs infra_cg_regs = {
> + .set_ofs = 0x0040,
> + .clr_ofs = 0x0044,
> + .sta_ofs = 0x0048,
> +};
> +
> +#define GATE_ICG(_id, _name, _parent, _shift) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = &infra_cg_regs, \
> + .shift = _shift, \
> + .ops = &mtk_clk_gate_ops_setclr, \
> + }
> +
> +static const struct mtk_gate infra_clks[] = {
> + GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
> + GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
> + GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
> + GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
> + GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
> + GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
> + GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
> + GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
> + GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
> + GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
> + GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
> + GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
> + GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
> + GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
> + GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
> + GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
> + GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
> + GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
> +};
> +
> +static const struct mtk_fixed_factor infra_fixed_divs[] = {
> + FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
> +};
> +
> +static struct clk_onecell_data *infra_clk_data;
> +
> +static void mtk_infrasys_init_early(struct device_node *node)
> +{
> + int r, i;
> +
> + if (!infra_clk_data) {
> + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> +
> + for (i = 0; i < CLK_INFRA_NR; i++)
> + infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
> + }
> +
> + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> + infra_clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> + if (r)
> + pr_err("%s(): could not register clock provider: %d\n",
> + __func__, r);
> +}
> +CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
> + mtk_infrasys_init_early);
> +
> +static int mtk_infrasys_init(struct platform_device *pdev)
> +{
> + int r, i;
> + struct device_node *node = pdev->dev.of_node;
> +
> + if (!infra_clk_data) {
> + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> + } else {
> + for (i = 0; i < CLK_INFRA_NR; i++) {
> + if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
> + infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
> + }
> + }
> +
> + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> + infra_clk_data);
> + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> + infra_clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> +
> + return r;
> +}
> +
> +static const struct mtk_gate_regs peri0_cg_regs = {
> + .set_ofs = 0x0008,
> + .clr_ofs = 0x0010,
> + .sta_ofs = 0x0018,
> +};
> +
> +static const struct mtk_gate_regs peri1_cg_regs = {
> + .set_ofs = 0x000c,
> + .clr_ofs = 0x0014,
> + .sta_ofs = 0x001c,
> +};
> +
> +#define GATE_PERI0(_id, _name, _parent, _shift) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = &peri0_cg_regs, \
> + .shift = _shift, \
> + .ops = &mtk_clk_gate_ops_setclr, \
> + }
> +
> +#define GATE_PERI1(_id, _name, _parent, _shift) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = &peri1_cg_regs, \
> + .shift = _shift, \
> + .ops = &mtk_clk_gate_ops_setclr, \
> + }
> +
> +static const struct mtk_gate peri_clks[] = {
> + GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
> + GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
> + GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
> + GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
> + GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
> + GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
> + GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
> + GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
> + GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
> + GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
> + GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
> + GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
> + GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
> + GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
> + GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
> + GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
> + GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
> + GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
> + GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
> + GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
> + GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
> + GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
> + GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
> + GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
> + GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
> + GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
> + GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
> + GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
> + GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
> + GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
> + GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
> + GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
> +
> + GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
> + GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
> + GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
> + GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
> + GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
> + GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
> + GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
> + GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
> + GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
> + GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
> + GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
> + GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
> +};
> +
> +static const char * const uart_ck_sel_parents[] = {
> + "clk26m",
> + "uart_sel",
> +};
> +
> +static const struct mtk_composite peri_muxs[] = {
> + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
> + 0x40c, 0, 1),
> + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
> + 0x40c, 1, 1),
> + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
> + 0x40c, 2, 1),
> + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
> + 0x40c, 3, 1),
> +};
> +
> +static int mtk_pericfg_init(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + void __iomem *base;
> + int r;
> + struct device_node *node = pdev->dev.of_node;
> +
> + base = devm_of_iomap(&pdev->dev, 0);
> + if (!base)
> + return -ENOMEM;
> +
> + clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
> +
> + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
> + clk_data);
> +
> + mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
> + &lock, clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + return r;
Just return of_clk_add_provider()?
> +}
[...]
> +
> +static int clk_mt2701_probe(struct platform_device *pdev)
> +{
> + int (*clk_init)(struct platform_device *);
> + int r;
> +
> + clk_init = of_device_get_match_data(&pdev->dev);
> + if (!clk_init)
> + return -EINVAL;
> +
> + r = clk_init(pdev);
> + if (r) {
> + dev_err(&pdev->dev,
> + "could not register clock provider: %s: %d\n",
> + pdev->name, r);
> + }
Braces are unnecessary.
> +
> + return r;
> +}
> +
> +static struct platform_driver clk_mt2701_drv = {
> + .probe = clk_mt2701_probe,
> + .driver = {
> + .name = "clk-mt2701",
> + .owner = THIS_MODULE,
This is unnecessary because platform_driver_register() already
does it.
> + .of_match_table = of_match_clk_mt2701,
> + },
> +};
> +
> +static int __init clk_mt2701_init(void)
> +{
> + return platform_driver_register(&clk_mt2701_drv);
> +}
> +
> +arch_initcall(clk_mt2701_init);
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index bb30f70..0541df7 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -58,6 +58,9 @@ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
> for (i = 0; i < num; i++) {
> const struct mtk_fixed_clk *rc = &clks[i];
>
> + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[rc->id]))
> + continue;
> +
> clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0,
> rc->rate);
>
> @@ -81,6 +84,9 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
> for (i = 0; i < num; i++) {
> const struct mtk_fixed_factor *ff = &clks[i];
>
> + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[ff->id]))
> + continue;
> +
> clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
> CLK_SET_RATE_PARENT, ff->mult, ff->div);
>
> @@ -116,6 +122,9 @@ int mtk_clk_register_gates(struct device_node *node,
> for (i = 0; i < num; i++) {
> const struct mtk_gate *gate = &clks[i];
>
> + if (!IS_ERR_OR_NULL(clk_data->clks[gate->id]))
> + continue;
> +
> clk = mtk_clk_register_gate(gate->name, gate->parent_name,
> regmap,
> gate->regs->set_ofs,
> @@ -232,6 +241,9 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs,
> for (i = 0; i < num; i++) {
> const struct mtk_composite *mc = &mcs[i];
>
> + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mc->id]))
> + continue;
> +
> clk = mtk_clk_register_composite(mc, base, lock);
>
> if (IS_ERR(clk)) {
> @@ -244,3 +256,31 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs,
> clk_data->clks[mc->id] = clk;
> }
> }
> +
> +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
> + int num, void __iomem *base, spinlock_t *lock,
> + struct clk_onecell_data *clk_data)
> +{
> + struct clk *clk;
> + int i;
> +
> + for (i = 0; i < num; i++) {
> + const struct mtk_clk_divider *mcd = &mcds[i];
> +
> + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
NULL is a valid clk. IS_ERR_OR_NULL is usually wrong.
> + continue;
> +
> + clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
> + mcd->flags, base + mcd->div_reg, mcd->div_shift,
> + mcd->div_width, mcd->clk_divider_flags, lock);
> +
> + if (IS_ERR(clk)) {
> + pr_err("Failed to register clk %s: %ld\n",
> + mcd->name, PTR_ERR(clk));
> + continue;
> + }
> +
> + if (clk_data)
> + clk_data->clks[mcd->id] = clk;
> + }
> +}
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 9f24fcf..f5d6b70 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -87,7 +87,8 @@ struct mtk_composite {
> * In case the rate change propagation to parent clocks is undesirable,
> * this macro allows to specify the clock flags manually.
> */
> -#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \
> +#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
> + _gate, _flags) { \
> .id = _id, \
> .name = _name, \
> .mux_reg = _reg, \
> @@ -106,7 +107,8 @@ struct mtk_composite {
> * parent clock by default.
> */
> #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
> - MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
> + MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
> + _gate, CLK_SET_RATE_PARENT)
>
> #define MUX(_id, _name, _parents, _reg, _shift, _width) { \
> .id = _id, \
> @@ -121,7 +123,8 @@ struct mtk_composite {
> .flags = CLK_SET_RATE_PARENT, \
> }
>
> -#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
> +#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
> + _div_width, _div_shift) { \
Did anything actually change? Checkpatch fix?
> .id = _id, \
> .parent = _parent, \
> .name = _name, \
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCHv4 00/15] clk: ti: add support for hwmod clocks
From: Stephen Boyd @ 2016-10-28 0:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476805568-19264-1-git-send-email-t-kristo@ti.com>
On 10/18, Tero Kristo wrote:
> Hi,
>
> As a recap, this series is part of the ongoing work to get rid of the
> hwmod database under mach-omap2 folder. This series converts the
> existing clock related functionality to a new clock type, which will
> allow removing all the .clkctrl related items from hwmod database.
> This series adds sample solution for OMAP4 only, rest of the SoCs can
> be converted automatically once the approach is acceptable.
>
> v4 has the following high level changes compared to v3:
> - Clock data is now statically built-in to the driver
> - Adds clockdomain provider support, which can be used to fetch
> clocks based on clockdomain relation. Only clockdomains need to be
> registered within DT.
> - Added some automatic clock alias generation support to the TI clock
> drivers, if this is not acceptable, I can change this to add all the
> aliases under the individual drivers/clk/ti/clk-xyz.c files
Is there a plan to get rid of the aliases entirely? Or we can't
do that because DT is not fully supported on these platforms? I'm
mostly wondering how long that sort of code is going to stick
around and if it's better to fully compartmentalize it to the
SoCs that are affected or if it should be a core feature of TI
driver.
> - As a sample, only omap4 clock data is available with this set
>
> After this series, the clock data can be dropped from the hwmod database
> for OMAP4, I have working patches for this for anybody interested. Also,
> the DT files require some modifications to add proper support for
> clockdomain providers, and drop some unnecessary clock nodes.
Can this be shared as a git tree on the web? Hopefully I can see
the resulting DTS and understand what's going on better.
>
> Boot + simple PM test seems to be working on OMAP4 with this set, and
> boot test with other boards I have access to don't seem to cause any
> issues. Applies on top of 4.9-rc1.
>
Awesome!
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCHv4 11/15] clk: ti: clockdomain: add clock provider support to clockdomains
From: Stephen Boyd @ 2016-10-28 0:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476805568-19264-12-git-send-email-t-kristo@ti.com>
On 10/18, Tero Kristo wrote:
> Clockdomains can now be used as clock providers in the system. This
> patch initializes the provider data during init, and parses the clocks
> while they are being registered. An xlate function for the provider
> is also given.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Please Cc dt reviewers on binding updates. I suppose a PRCM is
like an MFD that has clocks and resets under it? On other
platforms we've combined that all into one node and just had
#clock-cells and #reset-cells in that node. Is there any reason
we can't do that here?
> ---
> .../devicetree/bindings/arm/omap/prcm.txt | 13 ++
> .../devicetree/bindings/clock/ti/clockdomain.txt | 12 +-
> arch/arm/mach-omap2/io.c | 2 +
> drivers/clk/ti/clock.h | 1 +
> drivers/clk/ti/clockdomain.c | 147 +++++++++++++++++++++
> include/linux/clk/ti.h | 3 +
> 6 files changed, 177 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt
> index 3eb6d7a..301f576 100644
> --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
> +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
> @@ -47,6 +47,19 @@ cm: cm at 48004000 {
> };
> }
>
> +cm2: cm2 at 8000 {
> + compatible = "ti,omap4-cm2";
> + reg = <0x8000 0x3000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x8000 0x3000>;
> +
> + l4_per_clkdm: l4_per_clkdm {
> + compatible = "ti,clockdomain";
> + reg = <0x1400 0x200>;
Should there be #clock-cells = <1> here? Also node name should
have an @1400 after it?
> + };
> +};
> +
> &cm_clocks {
> omap2_32k_fck: omap_32k_fck {
> #clock-cells = <0>;
> diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
> index cb76b3f..5d8ca61 100644
> --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
> +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
> @@ -14,11 +14,21 @@ hardware hierarchy.
>
> Required properties:
> - compatible : shall be "ti,clockdomain"
> -- #clock-cells : from common clock binding; shall be set to 0.
> +- #clock-cells : from common clock binding; shall be set to 1 if this
> + clockdomain acts as a clock provider.
> +
> +Optional properties:
> - clocks : link phandles of clocks within this domain
> +- reg : address for the clockdomain
>
> Examples:
> dss_clkdm: dss_clkdm {
> compatible = "ti,clockdomain";
> clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
> };
> +
> + l4_per_clkdm: l4_per_clkdm {
add an @1400?
> + compatible = "ti,clockdomain";
> + #clock-cells = <1>;
> + reg = <0x1400 0x200>;
> + };
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 0e9acdd..c1a5cfb 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -794,6 +794,8 @@ int __init omap_clk_init(void)
> if (ret)
> return ret;
>
> + ti_dt_clockdomains_early_setup();
> +
> of_clk_init(NULL);
>
> ti_dt_clk_init_retry_clks();
> diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
> index 9b8a5f2..f6383ab 100644
> --- a/drivers/clk/ti/clock.h
> +++ b/drivers/clk/ti/clock.h
> @@ -205,6 +205,7 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
>
> int ti_clk_get_memmap_index(struct device_node *node);
> void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
> +void __iomem *ti_clk_get_reg_addr_clkdm(const char *clkdm_name, u16 offset);
> void ti_dt_clocks_register(struct ti_dt_clk *oclks);
> int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
> ti_of_clk_init_cb_t func);
> diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
> index 704157d..7b0a6c3 100644
> --- a/drivers/clk/ti/clockdomain.c
> +++ b/drivers/clk/ti/clockdomain.c
> @@ -28,6 +28,23 @@
> #define pr_fmt(fmt) "%s: " fmt, __func__
>
> /**
> + * struct ti_clkdm - TI clockdomain data structure
> + * @name: name of the clockdomain
> + * @index: index of the clk_iomap struct for this clkdm
> + * @offset: clockdomain offset from the beginning of the iomap
> + * @link: link to the list
> + */
> +struct ti_clkdm {
> + const char *name;
> + int index;
> + u32 offset;
> + struct list_head link;
> + struct list_head clocks;
> +};
> +
> +static LIST_HEAD(clkdms);
> +
> +/**
> * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
> * @hw: struct clk_hw * of the clock being enabled
> *
> @@ -116,6 +133,8 @@ void omap2_init_clk_clkdm(struct clk_hw *hw)
> struct clk_hw_omap *clk = to_clk_hw_omap(hw);
> struct clockdomain *clkdm;
> const char *clk_name;
> + struct ti_clkdm *ti_clkdm;
> + bool match = false;
>
> if (!clk->clkdm_name)
> return;
> @@ -130,7 +149,21 @@ void omap2_init_clk_clkdm(struct clk_hw *hw)
> } else {
> pr_debug("clock: could not associate clk %s to clkdm %s\n",
> clk_name, clk->clkdm_name);
> + return;
> }
> +
> + list_for_each_entry(ti_clkdm, &clkdms, link) {
> + if (!strcmp(ti_clkdm->name, clk->clkdm_name)) {
> + match = true;
> + break;
Or just goto found and then drop the match bool thing.
> + }
> + }
> +
> + if (!match)
> + return;
> +
> + /* Add clock to the list of provided clocks */
> + list_add(&clk->clkdm_link, &ti_clkdm->clocks);
> }
>
> static void __init of_ti_clockdomain_setup(struct device_node *node)
> @@ -161,11 +194,125 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
> }
> }
>
> +static struct clk_hw *clkdm_clk_xlate(struct of_phandle_args *clkspec,
> + void *data)
> +{
> + struct ti_clkdm *clkdm = data;
> + struct clk_hw_omap *clk;
> + u16 offset = clkspec->args[0];
> +
> + list_for_each_entry(clk, &clkdm->clocks, clkdm_link)
> + if (((u32)clk->enable_reg & 0xffff) - clkdm->offset == offset)
This looks scary.
> + return &clk->hw;
> +
> + return ERR_PTR(-EINVAL);
> +}
> +
> +static int ti_clk_register_clkdm(struct device_node *node)
> +{
> + u64 clkdm_addr;
> + u64 inst_addr;
> + const __be32 *reg;
> + u32 offset;
> + int idx;
> + struct ti_clkdm *clkdm;
> + int ret;
> +
> + reg = of_get_address(node, 0, NULL, NULL);
> + if (!reg)
> + return -ENOENT;
> +
> + clkdm_addr = of_translate_address(node, reg);
> +
> + reg = of_get_address(node->parent, 0, NULL, NULL);
> + if (!reg)
> + return -EINVAL;
> +
> + inst_addr = of_translate_address(node->parent, reg);
> +
> + offset = clkdm_addr - inst_addr;
> +
I guess the usual offset tricks are still going on in the TI clk
driver? Is there a plan to stop doing that at some point?
> + idx = ti_clk_get_memmap_index(node->parent);
> +
> + if (idx < 0) {
> + pr_err("bad memmap index for %s\n", node->name);
> + return idx;
> + }
> +
> + clkdm = kzalloc(sizeof(*clkdm), GFP_KERNEL);
> + if (!clkdm)
> + return -ENOMEM;
> +
> + clkdm->name = node->name;
> + clkdm->index = idx;
> + clkdm->offset = offset;
> +
> + INIT_LIST_HEAD(&clkdm->clocks);
> +
> + list_add(&clkdm->link, &clkdms);
> +
> + ret = of_clk_add_hw_provider(node, clkdm_clk_xlate, clkdm);
> + if (ret) {
> + list_del(&clkdm->link);
> + kfree(clkdm);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * ti_clk_get_reg_addr_clkdm - get register address relative to clockdomain
> + * @clkdm_name: parent clockdomain
> + * @offset: offset from the clockdomain
> + *
> + * Gets a register address relative to parent clockdomain. Searches the
> + * list of available clockdomain, and if match is found, calculates the
> + * register address from the iomap relative to the clockdomain.
> + * Returns the register address, or NULL if not found.
> + */
> +void __iomem *ti_clk_get_reg_addr_clkdm(const char *clkdm_name, u16 offset)
> +{
> + u32 reg;
> + struct clk_omap_reg *reg_setup;
> + struct ti_clkdm *clkdm;
> + bool match = false;
> +
> + reg_setup = (struct clk_omap_reg *)®
> +
> + /* XXX: get offset from clkdm, get base for instance */
> + list_for_each_entry(clkdm, &clkdms, link) {
> + if (!strcmp(clkdm->name, clkdm_name)) {
> + match = true;
> + break;
> + }
> + }
> +
> + if (!match) {
> + pr_err("%s: no entry for %s\n", __func__, clkdm_name);
> + return NULL;
> + }
> +
> + reg_setup->offset = clkdm->offset + offset;
> + reg_setup->index = clkdm->index;
> +
> + return (void __iomem *)reg;
> +}
> +
> static const struct of_device_id ti_clkdm_match_table[] __initconst = {
> { .compatible = "ti,clockdomain" },
> { }
> };
>
> +void __init ti_dt_clockdomains_early_setup(void)
> +{
> + struct device_node *np;
> +
> + for_each_matching_node(np, ti_clkdm_match_table) {
> + ti_clk_register_clkdm(np);
> + }
Nitpick: drop braces please.
> +}
> +
> /**
> * ti_dt_clockdomains_setup - setup device tree clockdomains
> *
> diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
> index 626ae94..afccb48 100644
> --- a/include/linux/clk/ti.h
> +++ b/include/linux/clk/ti.h
> @@ -125,6 +125,7 @@ struct clk_hw_omap_ops {
> /**
> * struct clk_hw_omap - OMAP struct clk
> * @node: list_head connecting this clock into the full clock list
> + * @clkdm_link: list_head connecting this clock into the clockdomain
> * @enable_reg: register to write to enable the clock (see @enable_bit)
> * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
> * @flags: see "struct clk.flags possibilities" above
> @@ -137,6 +138,7 @@ struct clk_hw_omap_ops {
> struct clk_hw_omap {
> struct clk_hw hw;
> struct list_head node;
> + struct list_head clkdm_link;
> unsigned long fixed_rate;
> u8 fixed_div;
> void __iomem *enable_reg;
> @@ -251,6 +253,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
> unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
>
> void ti_dt_clk_init_retry_clks(void);
> +void ti_dt_clockdomains_early_setup(void);
> void ti_dt_clockdomains_setup(void);
> int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
>
> --
> 1.9.1
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH RESEND 1/3] clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf
From: Stephen Boyd @ 2016-10-28 0:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5BQHKv7dxJTq2C1qdvhhRRRW8bafaXoQW77AKLNTWggAg@mail.gmail.com>
On 10/26, Fabio Estevam wrote:
> Shawn,
>
> Are you collecting the imx clk patches in this cycle?
>
> I see no response from Stephen on this series from a long time.
>
> We missed 4.9, so hopefully this can land in 4.10.
>
These patches are in the queue. If Shawn wants to pick up patches
and send pull requests that's fine too.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v2] ARM: dts: socfpga: Add Macnica sodia board
From: Olof Johansson @ 2016-10-28 0:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160924235945.32128-1-iwamatsu@nigauri.org>
Hi,
Saw this when looking at the patch when merging it.
Please fix up with incremental patch. Dinh, this goes for other
platforms under socfpga too, several have this problem:
On Sat, Sep 24, 2016 at 4:59 PM, Nobuhiro Iwamatsu <iwamatsu@nigauri.org> wrote:
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
> new file mode 100644
> index 0000000..9aaf413
> --- /dev/null
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
> @@ -0,0 +1,123 @@
> +/*
> + * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "socfpga_cyclone5.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
> + compatible = "altr,socfpga-cyclone5", "altr,socfpga";
You should add a compatible entry for your specific board. Compatible
goes from specific to generic, so something like:
compatible = "altr,macnica-sodia", "latr,socfpga-cyclone5", "altr,socfpga";
You can even add entries for the specific rev (if there are
differences). But at the very least, add one for the board.
Dinh, please follow up for other boards as well. I've still merged the
pull request you sent (email about that separately).
Regards,
-Olof
^ permalink raw reply
* [RFC][PATCH] arm64: Add support for CONFIG_DEBUG_VIRTUAL
From: Laura Abbott @ 2016-10-28 0:18 UTC (permalink / raw)
To: linux-arm-kernel
x86 has an option CONFIG_DEBUG_VIRTUAL to do additional checks
on virt_to_phys calls. The goal is to catch users who are calling
virt_to_phys on non-linear addresses immediately. As features
such as CONFIG_VMAP_STACK get enabled for arm64, this becomes
increasingly important. Add checks to catch bad virt_to_phys
usage.
Signed-off-by: Laura Abbott <labbott@redhat.com>
---
This has been on my TODO list for a while. It caught a few bugs with
CONFIG_VMAP_STACK on x86 so when that eventually gets added
for arm64 it will be useful to have. This caught one driver calling __pa on an
ioremapped address already. RFC for a couple of reasons:
1) This is basically a direct port of the x86 approach.
2) I needed some #ifndef __ASSEMBLY__ which I don't like to throw around.
3) I'm not quite sure about the bounds check for the VIRTUAL_BUG_ON with KASLR,
specifically the _end check.
4) Is it worth actually keeping this as DEBUG_VIRTUAL vs. folding it into
another option?
---
arch/arm64/include/asm/memory.h | 11 ++++++++++-
arch/arm64/mm/Makefile | 2 +-
arch/arm64/mm/physaddr.c | 17 +++++++++++++++++
lib/Kconfig.debug | 2 +-
mm/cma.c | 2 +-
5 files changed, 30 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/mm/physaddr.c
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index ba62df8..9805adc 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -106,11 +106,19 @@
* private definitions which should NOT be used outside memory.h
* files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
*/
-#define __virt_to_phys(x) ({ \
+#define __virt_to_phys_nodebug(x) ({ \
phys_addr_t __x = (phys_addr_t)(x); \
__x & BIT(VA_BITS - 1) ? (__x & ~PAGE_OFFSET) + PHYS_OFFSET : \
(__x - kimage_voffset); })
+#ifdef CONFIG_DEBUG_VIRTUAL
+#ifndef __ASSEMBLY__
+extern unsigned long __virt_to_phys(unsigned long x);
+#endif
+#else
+#define __virt_to_phys(x) __virt_to_phys_nodebug(x)
+#endif
+
#define __phys_to_virt(x) ((unsigned long)((x) - PHYS_OFFSET) | PAGE_OFFSET)
#define __phys_to_kimg(x) ((unsigned long)((x) + kimage_voffset))
@@ -202,6 +210,7 @@ static inline void *phys_to_virt(phys_addr_t x)
* Drivers should NOT use these either.
*/
#define __pa(x) __virt_to_phys((unsigned long)(x))
+#define __pa_nodebug(x) __virt_to_phys_nodebug((unsigned long)(x))
#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#define virt_to_pfn(x) __phys_to_pfn(__virt_to_phys(x))
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
index 54bb209..bcea84e 100644
--- a/arch/arm64/mm/Makefile
+++ b/arch/arm64/mm/Makefile
@@ -5,6 +5,6 @@ obj-y := dma-mapping.o extable.o fault.o init.o \
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
obj-$(CONFIG_ARM64_PTDUMP) += dump.o
obj-$(CONFIG_NUMA) += numa.o
-
+obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
obj-$(CONFIG_KASAN) += kasan_init.o
KASAN_SANITIZE_kasan_init.o := n
diff --git a/arch/arm64/mm/physaddr.c b/arch/arm64/mm/physaddr.c
new file mode 100644
index 0000000..6c271e2
--- /dev/null
+++ b/arch/arm64/mm/physaddr.c
@@ -0,0 +1,17 @@
+#include <linux/mm.h>
+
+#include <asm/memory.h>
+
+unsigned long __virt_to_phys(unsigned long x)
+{
+ phys_addr_t __x = (phys_addr_t)x;
+
+ if (__x & BIT(VA_BITS - 1)) {
+ /* The bit check ensures this is the right range */
+ return (__x & ~PAGE_OFFSET) + PHYS_OFFSET;
+ } else {
+ VIRTUAL_BUG_ON(x < kimage_vaddr || x > (unsigned long)_end);
+ return (__x - kimage_voffset);
+ }
+}
+EXPORT_SYMBOL(__virt_to_phys);
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 33bc56c..e5634bb 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -604,7 +604,7 @@ config DEBUG_VM_PGFLAGS
config DEBUG_VIRTUAL
bool "Debug VM translations"
- depends on DEBUG_KERNEL && X86
+ depends on DEBUG_KERNEL && (X86 || ARM64)
help
Enable some costly sanity checks in virtual to page code. This can
catch mistakes with virt_to_page() and friends.
diff --git a/mm/cma.c b/mm/cma.c
index 384c2cb..2345803 100644
--- a/mm/cma.c
+++ b/mm/cma.c
@@ -235,7 +235,7 @@ int __init cma_declare_contiguous(phys_addr_t base,
phys_addr_t highmem_start;
int ret = 0;
-#ifdef CONFIG_X86
+#if defined(CONFIG_X86) || defined(CONFIG_ARM64)
/*
* high_memory isn't direct mapped memory so retrieving its physical
* address isn't appropriate. But it would be useful to check the
--
2.7.4
^ permalink raw reply related
* [GIT PULL] SoCFPGA DTS updates for v4.10, part 1
From: Olof Johansson @ 2016-10-28 0:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024141654.19832-1-dinguyen@kernel.org>
On Mon, Oct 24, 2016 at 09:16:54AM -0500, Dinh Nguyen wrote:
> Hi Arnd, Kevin, Olof:
>
> Please pull in these DTS updates for SoCFPGA for v4.10.
>
> Thanks,
> Dinh
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_dts_for_v4.10_part_1
>
> for you to fetch changes up to c96f5919e6b0d132aa9afe9f1adc872fc107d5bb:
>
> ARM: dts: socfpga: socrates: enable qspi (2016-10-18 22:18:14 -0500)
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] STi DT update for v4.10 round 1
From: Olof Johansson @ 2016-10-28 0:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1a44f1ef-906a-798a-a60b-9d8212209aaa@st.com>
Hi,
On Thu, Oct 20, 2016 at 04:27:10PM +0200, Patrice Chotard wrote:
> Hi Arnd, Kevin, Olof
>
> PLease consider this first round of STi dts update for v4.10 :
>
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git
The tag specification fell off. Maybe because it hadn't been mirrored out by
the time you generated the config, since I seem to have found it there
(st-dt-for-4.10).
>
> for you to fetch changes up to 97a0b97f9e8197429eee5f87ce14373f73dbd9d3:
>
> ARM: dts: stih410-clocks: Add PROC_STFE as a critical clock (2016-10-20 16:20:26 +0200)
Merged into next/dt. Thanks!
-Olof
^ permalink raw reply
* [GIT PULL] STi defconfig updates for v4.10
From: Olof Johansson @ 2016-10-28 0:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50be6ab2-2af8-b21e-770c-d141d6396179@st.com>
On Thu, Oct 20, 2016 at 05:20:27PM +0200, Patrice Chotard wrote:
> Hi Olof, Arnd and Kevin,
>
> Please consider this first round of multi_v7_defconfig updates for v4.10 :
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git tags/sti-defconfig-for-4.10
>
> for you to fetch changes up to 620c52f4db4d47e1f33c64e641392fe575d5397f:
>
> ARM: multi_v7_defconfig: Remove stih41x phy Kconfig symbol. (2016-10-20 17:05:08 +0200)
Thanks, merged.
-Olof
^ permalink raw reply
* [PATCH] arm64: Enable HIBERNATION in defconfig
From: Olof Johansson @ 2016-10-28 0:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476896392-28106-1-git-send-email-catalin.marinas@arm.com>
On Wed, Oct 19, 2016 at 05:59:52PM +0100, Catalin Marinas wrote:
> This patch adds CONFIG_HIBERNATION to the arm64 defconfig.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>
> Re-sent post 4.9-rc1 as it was missed during the merging window.
Thanks, applied to next/arm64 for 4.10.
-Olof
^ permalink raw reply
* [PATCH] ARM: defconfig: update U8500 defconfig
From: Olof Johansson @ 2016-10-28 0:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476696229-1964-1-git-send-email-linus.walleij@linaro.org>
On Mon, Oct 17, 2016 at 11:23:49AM +0200, Linus Walleij wrote:
> Some config options like perf events and PM are now implicit,
> we have an upstream driver for the AK8974, and we really
> want the HRTIMER software triggers from configfs with some
> of the sensors.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ARM SoC folks: please apply this wherever your usual batch of
> defconfig changes go.
Thanks, applied!
-Olof
^ permalink raw reply
* [PATCH v3 1/3] PM / OPP: Expose _of_get_opp_desc_node as dev_pm_opp API
From: kbuild test robot @ 2016-10-27 23:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027214131.1725-2-d-gerlach@ti.com>
Hi Dave,
[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.9-rc2]
[cannot apply to pm/linux-next next-20161027]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Dave-Gerlach/cpufreq-Introduce-TI-CPUFreq-OPP-Driver/20161028-054633
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: xtensa-allmodconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 4.9.0
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=xtensa
All errors (new ones prefixed by >>):
drivers/base/power/opp/of.c:184:6: error: redefinition of 'dev_pm_opp_of_remove_table'
void dev_pm_opp_of_remove_table(struct device *dev)
^
In file included from drivers/base/power/opp/opp.h:21:0,
from drivers/base/power/opp/of.c:22:
include/linux/pm_opp.h:218:20: note: previous definition of 'dev_pm_opp_of_remove_table' was here
static inline void dev_pm_opp_of_remove_table(struct device *dev)
^
>> drivers/base/power/opp/of.c:191:21: error: redefinition of 'dev_pm_opp_of_get_opp_desc_node'
struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev)
^
In file included from drivers/base/power/opp/opp.h:21:0,
from drivers/base/power/opp/of.c:22:
include/linux/pm_opp.h:236:35: note: previous definition of 'dev_pm_opp_of_get_opp_desc_node' was here
static inline struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev)
^
drivers/base/power/opp/of.c:434:5: error: redefinition of 'dev_pm_opp_of_add_table'
int dev_pm_opp_of_add_table(struct device *dev)
^
In file included from drivers/base/power/opp/opp.h:21:0,
from drivers/base/power/opp/of.c:22:
include/linux/pm_opp.h:213:19: note: previous definition of 'dev_pm_opp_of_add_table' was here
static inline int dev_pm_opp_of_add_table(struct device *dev)
^
drivers/base/power/opp/of.c:474:6: error: redefinition of 'dev_pm_opp_of_cpumask_remove_table'
void dev_pm_opp_of_cpumask_remove_table(const struct cpumask *cpumask)
^
In file included from drivers/base/power/opp/opp.h:21:0,
from drivers/base/power/opp/of.c:22:
include/linux/pm_opp.h:227:20: note: previous definition of 'dev_pm_opp_of_cpumask_remove_table' was here
static inline void dev_pm_opp_of_cpumask_remove_table(const struct cpumask *cpumask)
^
drivers/base/power/opp/of.c:492:5: error: redefinition of 'dev_pm_opp_of_cpumask_add_table'
int dev_pm_opp_of_cpumask_add_table(const struct cpumask *cpumask)
^
In file included from drivers/base/power/opp/opp.h:21:0,
from drivers/base/power/opp/of.c:22:
include/linux/pm_opp.h:222:19: note: previous definition of 'dev_pm_opp_of_cpumask_add_table' was here
static inline int dev_pm_opp_of_cpumask_add_table(const struct cpumask *cpumask)
^
drivers/base/power/opp/of.c:545:5: error: redefinition of 'dev_pm_opp_of_get_sharing_cpus'
int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev,
^
In file included from drivers/base/power/opp/opp.h:21:0,
from drivers/base/power/opp/of.c:22:
include/linux/pm_opp.h:231:19: note: previous definition of 'dev_pm_opp_of_get_sharing_cpus' was here
static inline int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask)
^
vim +/dev_pm_opp_of_get_opp_desc_node +191 drivers/base/power/opp/of.c
178 * Locking: The internal opp_table and opp structures are RCU protected.
179 * Hence this function indirectly uses RCU updater strategy with mutex locks
180 * to keep the integrity of the internal data structures. Callers should ensure
181 * that this function is *NOT* called under RCU protection or in contexts where
182 * mutex cannot be locked.
183 */
> 184 void dev_pm_opp_of_remove_table(struct device *dev)
185 {
186 _dev_pm_opp_remove_table(dev, false);
187 }
188 EXPORT_SYMBOL_GPL(dev_pm_opp_of_remove_table);
189
190 /* Returns opp descriptor node for a device, caller must do of_node_put() */
> 191 struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev)
192 {
193 /*
194 * TODO: Support for multiple OPP tables.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
-------------- next part --------------
A non-text attachment was scrubbed...
Name: .config.gz
Type: application/gzip
Size: 46043 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161028/0c934d6a/attachment-0001.gz>
^ permalink raw reply
* [PATCH] ARM: dts: msm8974: Remove "unused" reserved region
From: Stephen Boyd @ 2016-10-27 23:23 UTC (permalink / raw)
To: linux-arm-kernel
>From what I can tell by looking at the android 3.10 kernel
sources for msm8974, this isn't actually a reserved region.
Instead it's marked as "unused" for reserved regions. Let's
remove it so we get back a good chunk of memory.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 561d4d136762..5f4752696171 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -58,11 +58,6 @@
reg = <0x0fd80000 0x180000>;
no-map;
};
-
- unused at 0ff00000 {
- reg = <0x0ff00000 0x10100000>;
- no-map;
- };
};
cpus {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v6] tty/serial: at91: fix hardware handshake on Atmel platforms
From: Alexandre Belloni @ 2016-10-27 23:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027180229.5faqrvxa2a4pos7i@pengutronix.de>
On 27/10/2016 at 20:02:29 +0200, Uwe Kleine-K?nig wrote :
> Hello Richard,
>
> On Thu, Oct 27, 2016 at 06:04:06PM +0200, Richard Genoud wrote:
> > diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> > index fd8aa1f4ba78..168b10cad47b 100644
> > --- a/drivers/tty/serial/atmel_serial.c
> > +++ b/drivers/tty/serial/atmel_serial.c
> > @@ -2132,11 +2132,29 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
> > mode |= ATMEL_US_USMODE_RS485;
> > } else if (termios->c_cflag & CRTSCTS) {
> > /* RS232 with hardware handshake (RTS/CTS) */
> > - if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) {
> > - dev_info(port->dev, "not enabling hardware flow control because DMA is used");
> > - termios->c_cflag &= ~CRTSCTS;
> > - } else {
> > + if (atmel_use_fifo(port) &&
> > + !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
> > + /*
> > + * with ATMEL_US_USMODE_HWHS set, the controller will
> > + * be able to drive the RTS pin high/low when the RX
> > + * FIFO is above RXFTHRES/below RXFTHRES2.
> > + * It will also disable the transmitter when the CTS
> > + * pin is high.
> > + * This mode is not activated if CTS pin is a GPIO
> > + * because in this case, the transmitter is always
> > + * disabled (there must be an internal pull-up
> > + * responsible for this behaviour).
> > + * If the RTS pin is a GPIO, the controller won't be
> > + * able to drive it according to the FIFO thresholds,
> > + * but it will be handled by the driver.
> > + */
> > mode |= ATMEL_US_USMODE_HWHS;
>
> You use
>
> !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)
>
> as indicator that the cts mode of the respective pin is used. Is this
> reliable? (It's not if there are machines that don't use CTS, neither as
> gpio nor using the hardware function.) Maybe this needs a dt property to
> indicate that there is no (hw)handshaking available?
>
We had a call today were we agreed that this should be added in a future
patch. Let's fix the regression for now.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v7] spi: sun4i: Allow transfers larger than FIFO size
From: Mark Brown @ 2016-10-27 22:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027212727.leqg3gvwhd3u64er@lukather>
On Thu, Oct 27, 2016 at 11:27:27PM +0200, Maxime Ripard wrote:
> On Thu, Oct 27, 2016 at 12:14:19PM +0100, Mark Brown wrote:
> > but since I'm not turning up anything with this subject line I've no
> > idea what that might have been (and that's very concerning in itself
> > given that this is apparently v7...).
> v4 was here: https://patchwork.kernel.org/patch/3893371/
> v5: https://patchwork.kernel.org/patch/5455381/
> v6: https://patchwork.kernel.org/patch/6975871/
> So basically, I really have no idea why, but it really seems like it
> was just falling through the cracks, repeatedly (I'm not puting the
> blame on anyone though, it just happened). Maybe it was just because
> of the lack of comments :)
Oh, those subject lines were all starting ARM: rather than spi: -
there's a good chance I didn't look at the patches if I was busy
thinking they were changes for arch/arm rather than the SPI driver.
> > I'm also concerned that there isn't a version of this for sun6i,
> > it's going to make all the cut'n'pasting between the two drivers
> > harder if we make changes in one and not the other.
> I think I'll give reg_field a shot though, and try to merge the sun6i
> driver into this one and see the results. If it can help your
> decision.
It would definitely be nice given the level of duplication.
> > If the concern from the previous reviews to do with not using DMA is
> > there some reason it's hard to do DMA?
> I think just like Alexandru that it is orthogonal. But to really
> answer, no, it's not difficult. There's just been some fundamental
> disagreement on whether DMA was supposed to be optional or not that
> stalled everything I guess.
Oh, I seem to remember some patches adding DMA support that were doing
some strange special snowflake thing with ignoring errors now that I
think about it but that's not this one... why did nobody ever follow up
on those?
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 473 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161027/f8c15ff9/attachment.sig>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox