* [PATCH] staging: vc04_services: remove vchiq_copy_from_user
From: Michael Zoran @ 2016-10-30 12:55 UTC (permalink / raw)
To: linux-arm-kernel
The vchiq_copy_from_user function is not portable
and is consider "bad practice." Replace this function
with a callback based mechanism that is passed downward
on the stack. When it is actually time to copy the data,
the callback is called to copy the data into the message.
This callback is provided internally for userland calls
through ioctls on the device.
NOTE: Internal clients will need to be modified to work
with the new internal API.
Test Run:
vchiq_test -p 1
vchiq_test -f 10
Both tests pass.
Internal API Changes:
Change vchi_msg_queue to:
int32_t
vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle,
ssize_t (*copy_callback)(void *context, void *dest,
size_t offset, size_t maxsize),
void *context,
uint32_t data_size );
Remove:
vchi_msg_queuev_ex
vchi_msg_queuev
These functions were not implemented anyway so no need to fix them. It's
easier to just remove them.
Signed-off-by: Michael Zoran <mzoran@crowfest.net>
---
.../staging/vc04_services/interface/vchi/vchi.h | 25 +-
.../interface/vchiq_arm/vchiq_2835_arm.c | 11 -
.../vc04_services/interface/vchiq_arm/vchiq_arm.c | 103 +++++++-
.../vc04_services/interface/vchiq_arm/vchiq_core.c | 269 ++++++++++++---------
.../vc04_services/interface/vchiq_arm/vchiq_core.h | 3 -
.../vc04_services/interface/vchiq_arm/vchiq_if.h | 9 +-
.../vc04_services/interface/vchiq_arm/vchiq_shim.c | 64 +----
7 files changed, 287 insertions(+), 197 deletions(-)
diff --git a/drivers/staging/vc04_services/interface/vchi/vchi.h b/drivers/staging/vc04_services/interface/vchi/vchi.h
index 1b17e98..d693728 100644
--- a/drivers/staging/vc04_services/interface/vchi/vchi.h
+++ b/drivers/staging/vc04_services/interface/vchi/vchi.h
@@ -226,25 +226,12 @@ extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle,
int value);
// Routine to send a message across a service
-extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle,
- const void *data,
- uint32_t data_size,
- VCHI_FLAGS_T flags,
- void *msg_handle );
-
-// scatter-gather (vector) and send message
-int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle,
- VCHI_MSG_VECTOR_EX_T *vector,
- uint32_t count,
- VCHI_FLAGS_T flags,
- void *msg_handle );
-
-// legacy scatter-gather (vector) and send message, only handles pointers
-int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle,
- VCHI_MSG_VECTOR_T *vector,
- uint32_t count,
- VCHI_FLAGS_T flags,
- void *msg_handle );
+extern int32_t
+ vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle,
+ ssize_t (*copy_callback)(void *context, void *dest,
+ size_t offset, size_t maxsize),
+ void *context,
+ uint32_t data_size);
// Routine to receive a msg from a service
// Dequeue is equivalent to hold, copy into client buffer, release
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
index a5afcc5..02db3a5 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
@@ -211,17 +211,6 @@ remote_event_signal(REMOTE_EVENT_T *event)
writel(0, g_regs + BELL2); /* trigger vc interrupt */
}
-int
-vchiq_copy_from_user(void *dst, const void *src, int size)
-{
- if ((uint32_t)src < TASK_SIZE) {
- return copy_from_user(dst, src, size);
- } else {
- memcpy(dst, src, size);
- return 0;
- }
-}
-
VCHIQ_STATUS_T
vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle,
void *offset, int size, int dir)
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
index ce3ba37..dbeeffe 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
@@ -402,6 +402,107 @@ static void close_delivered(USER_SERVICE_T *user_service)
}
}
+struct vchiq_io_copy_callback_context {
+ VCHIQ_ELEMENT_T *current_element;
+ size_t current_element_offset;
+ unsigned long elements_to_go;
+ size_t current_offset;
+};
+
+static ssize_t
+vchiq_ioc_copy_element_data(
+ void *context,
+ void *dest,
+ size_t offset,
+ size_t maxsize)
+{
+ long res;
+ size_t bytes_this_round;
+ struct vchiq_io_copy_callback_context *copy_context =
+ (struct vchiq_io_copy_callback_context *)context;
+
+ if (offset != copy_context->current_offset)
+ return 0;
+
+ if (!copy_context->elements_to_go)
+ return 0;
+
+ /*
+ * Complex logic here to handle the case of 0 size elements
+ * in the middle of the array of elements.
+ *
+ * Need to skip over these 0 size elements.
+ */
+ while (1) {
+ bytes_this_round = min(copy_context->current_element->size -
+ copy_context->current_element_offset,
+ maxsize);
+
+ if (bytes_this_round)
+ break;
+
+ copy_context->elements_to_go--;
+ copy_context->current_element++;
+ copy_context->current_element_offset = 0;
+
+ if (!copy_context->elements_to_go)
+ return 0;
+ }
+
+ res = copy_from_user(dest,
+ copy_context->current_element->data +
+ copy_context->current_element_offset,
+ bytes_this_round);
+
+ if (res != 0)
+ return -EFAULT;
+
+ copy_context->current_element_offset += bytes_this_round;
+ copy_context->current_offset += bytes_this_round;
+
+ /*
+ * Check if done with current element, and if so advance to the next.
+ */
+ if (copy_context->current_element_offset ==
+ copy_context->current_element->size) {
+ copy_context->elements_to_go--;
+ copy_context->current_element++;
+ copy_context->current_element_offset = 0;
+ }
+
+ return bytes_this_round;
+}
+
+/**************************************************************************
+ *
+ * vchiq_ioc_queue_message
+ *
+ **************************************************************************/
+static VCHIQ_STATUS_T
+vchiq_ioc_queue_message(VCHIQ_SERVICE_HANDLE_T handle,
+ VCHIQ_ELEMENT_T *elements,
+ unsigned long count)
+{
+ struct vchiq_io_copy_callback_context context;
+ unsigned long i;
+ size_t total_size = 0;
+
+ context.current_element = elements;
+ context.current_element_offset = 0;
+ context.elements_to_go = count;
+ context.current_offset = 0;
+
+ for (i = 0; i < count; i++) {
+ if (!elements[i].data && elements[i].size != 0)
+ return -EFAULT;
+
+ total_size += elements[i].size;
+ }
+
+ return vchiq_queue_message(handle, vchiq_ioc_copy_element_data,
+ &context, total_size);
+}
+
/****************************************************************************
*
* vchiq_ioctl
@@ -651,7 +752,7 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
VCHIQ_ELEMENT_T elements[MAX_ELEMENTS];
if (copy_from_user(elements, args.elements,
args.count * sizeof(VCHIQ_ELEMENT_T)) == 0)
- status = vchiq_queue_message
+ status = vchiq_ioc_queue_message
(args.handle,
elements, args.count);
else
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c
index f3e1000..a771062 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c
@@ -463,8 +463,8 @@ remote_event_pollall(VCHIQ_STATE_T *state)
** enough for a header. This relies on header size being a power of two, which
** has been verified earlier by a static assertion. */
-static inline unsigned int
-calc_stride(unsigned int size)
+static inline size_t
+calc_stride(size_t size)
{
/* Allow room for the header */
size += sizeof(VCHIQ_HEADER_T);
@@ -543,7 +543,7 @@ request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type)
/* Called from queue_message, by the slot handler and application threads,
** with slot_mutex held */
static VCHIQ_HEADER_T *
-reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking)
+reserve_space(VCHIQ_STATE_T *state, size_t space, int is_blocking)
{
VCHIQ_SHARED_STATE_T *local = state->local;
int tx_pos = state->local_tx_pos;
@@ -725,18 +725,66 @@ process_free_queue(VCHIQ_STATE_T *state)
}
}
+static ssize_t
+memcpy_copy_callback(
+ void *context, void *dest,
+ size_t offset, size_t maxsize)
+{
+ void *src = context;
+
+ memcpy(dest + offset, src + offset, maxsize);
+ return maxsize;
+}
+
+static ssize_t
+copy_message_data(
+ ssize_t (*copy_callback)(void *context, void *dest,
+ size_t offset, size_t maxsize),
+ void *context,
+ void *dest,
+ size_t size)
+{
+ size_t pos = 0;
+
+ while (pos < size) {
+ ssize_t callback_result;
+ size_t max_bytes = size - pos;
+
+ callback_result =
+ copy_callback(context, dest + pos,
+ pos, max_bytes);
+
+ if (callback_result < 0)
+ return callback_result;
+
+ if (!callback_result)
+ return -EIO;
+
+ if (callback_result > max_bytes)
+ return -EIO;
+
+ pos += callback_result;
+ }
+
+ return size;
+}
+
/* Called by the slot handler and application threads */
static VCHIQ_STATUS_T
queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
- int msgid, const VCHIQ_ELEMENT_T *elements,
- int count, int size, int flags)
+ int msgid,
+ ssize_t (*copy_callback)(void *context, void *dest,
+ size_t offset, size_t maxsize),
+ void *context,
+ size_t size,
+ int flags)
{
VCHIQ_SHARED_STATE_T *local;
VCHIQ_SERVICE_QUOTA_T *service_quota = NULL;
VCHIQ_HEADER_T *header;
int type = VCHIQ_MSG_TYPE(msgid);
- unsigned int stride;
+ size_t stride;
local = state->local;
@@ -842,7 +890,7 @@ queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
}
if (type == VCHIQ_MSG_DATA) {
- int i, pos;
+ ssize_t callback_result;
int tx_end_index;
int slot_use_count;
@@ -856,27 +904,23 @@ queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK |
QMFLAGS_NO_MUTEX_UNLOCK)) != 0);
- for (i = 0, pos = 0; i < (unsigned int)count;
- pos += elements[i++].size)
- if (elements[i].size) {
- if (vchiq_copy_from_user
- (header->data + pos, elements[i].data,
- (size_t) elements[i].size) !=
- VCHIQ_SUCCESS) {
- mutex_unlock(&state->slot_mutex);
- VCHIQ_SERVICE_STATS_INC(service,
+ callback_result =
+ copy_message_data(copy_callback, context,
+ header->data, size);
+
+ if (callback_result < 0) {
+ mutex_unlock(&state->slot_mutex);
+ VCHIQ_SERVICE_STATS_INC(service,
error_count);
- return VCHIQ_ERROR;
- }
- if (i == 0) {
- if (SRVTRACE_ENABLED(service,
- VCHIQ_LOG_INFO))
- vchiq_log_dump_mem("Sent", 0,
- header->data + pos,
- min(64u,
- elements[0].size));
- }
- }
+ return VCHIQ_ERROR;
+ }
+
+ if (SRVTRACE_ENABLED(service,
+ VCHIQ_LOG_INFO))
+ vchiq_log_dump_mem("Sent", 0,
+ header->data,
+ min((size_t)64,
+ (size_t)callback_result));
spin_lock("a_spinlock);
service_quota->message_use_count++;
@@ -918,9 +962,17 @@ queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
header, size, VCHIQ_MSG_SRCPORT(msgid),
VCHIQ_MSG_DSTPORT(msgid));
if (size != 0) {
- WARN_ON(!((count == 1) && (size == elements[0].size)));
- memcpy(header->data, elements[0].data,
- elements[0].size);
+ /* It is assumed for now that this code path
+ * only happens from calls inside this file.
+ *
+ * External callers are through the vchiq_queue_message
+ * path which always sets the type to be VCHIQ_MSG_DATA
+ *
+ * At first glance this appears to be correct but
+ * more review is needed.
+ */
+ copy_message_data(copy_callback, context,
+ header->data, size);
}
VCHIQ_STATS_INC(state, ctrl_tx_count);
}
@@ -966,11 +1018,16 @@ queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
/* Called by the slot handler and application threads */
static VCHIQ_STATUS_T
queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
- int msgid, const VCHIQ_ELEMENT_T *elements,
- int count, int size, int is_blocking)
+ int msgid,
+ ssize_t (*copy_callback)(void *context, void *dest,
+ size_t offset, size_t maxsize),
+ void *context,
+ int size,
+ int is_blocking)
{
VCHIQ_SHARED_STATE_T *local;
VCHIQ_HEADER_T *header;
+ ssize_t callback_result;
local = state->local;
@@ -993,50 +1050,34 @@ queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
state->id, oldmsgid);
}
- if (service) {
- int i, pos;
+ vchiq_log_info(vchiq_sync_log_level,
+ "%d: qms %s@%pK,%x (%d->%d)", state->id,
+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
+ header, size, VCHIQ_MSG_SRCPORT(msgid),
+ VCHIQ_MSG_DSTPORT(msgid));
- vchiq_log_info(vchiq_sync_log_level,
- "%d: qms %s@%pK,%x (%d->%d)", state->id,
- msg_type_str(VCHIQ_MSG_TYPE(msgid)),
- header, size, VCHIQ_MSG_SRCPORT(msgid),
- VCHIQ_MSG_DSTPORT(msgid));
+ callback_result =
+ copy_message_data(copy_callback, context,
+ header->data, size);
- for (i = 0, pos = 0; i < (unsigned int)count;
- pos += elements[i++].size)
- if (elements[i].size) {
- if (vchiq_copy_from_user
- (header->data + pos, elements[i].data,
- (size_t) elements[i].size) !=
- VCHIQ_SUCCESS) {
- mutex_unlock(&state->sync_mutex);
- VCHIQ_SERVICE_STATS_INC(service,
- error_count);
- return VCHIQ_ERROR;
- }
- if (i == 0) {
- if (vchiq_sync_log_level >=
- VCHIQ_LOG_TRACE)
- vchiq_log_dump_mem("Sent Sync",
- 0, header->data + pos,
- min(64u,
- elements[0].size));
- }
- }
+ if (callback_result < 0) {
+ mutex_unlock(&state->slot_mutex);
+ VCHIQ_SERVICE_STATS_INC(service,
+ error_count);
+ return VCHIQ_ERROR;
+ }
+
+ if (service) {
+ if (SRVTRACE_ENABLED(service,
+ VCHIQ_LOG_INFO))
+ vchiq_log_dump_mem("Sent", 0,
+ header->data,
+ min((size_t)64,
+ (size_t)callback_result));
VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count);
VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size);
} else {
- vchiq_log_info(vchiq_sync_log_level,
- "%d: qms %s@%pK,%x (%d->%d)", state->id,
- msg_type_str(VCHIQ_MSG_TYPE(msgid)),
- header, size, VCHIQ_MSG_SRCPORT(msgid),
- VCHIQ_MSG_DSTPORT(msgid));
- if (size != 0) {
- WARN_ON(!((count == 1) && (size == elements[0].size)));
- memcpy(header->data, elements[0].data,
- elements[0].size);
- }
VCHIQ_STATS_INC(state, ctrl_tx_count);
}
@@ -1149,11 +1190,16 @@ notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue,
VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE;
int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport,
service->remoteport);
- VCHIQ_ELEMENT_T element = { &bulk->actual, 4 };
/* Only reply to non-dummy bulk requests */
if (bulk->remote_data) {
- status = queue_message(service->state, NULL,
- msgid, &element, 1, 4, 0);
+ status = queue_message(
+ service->state,
+ NULL,
+ msgid,
+ memcpy_copy_callback,
+ &bulk->actual,
+ 4,
+ 0);
if (status != VCHIQ_SUCCESS)
break;
}
@@ -1513,10 +1559,6 @@ parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
struct vchiq_openack_payload ack_payload = {
service->version
};
- VCHIQ_ELEMENT_T body = {
- &ack_payload,
- sizeof(ack_payload)
- };
if (state->version_common <
VCHIQ_VERSION_SYNCHRONOUS_MODE)
@@ -1526,21 +1568,28 @@ parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
if (service->sync &&
(state->version_common >=
VCHIQ_VERSION_SYNCHRONOUS_MODE)) {
- if (queue_message_sync(state, NULL,
+ if (queue_message_sync(
+ state,
+ NULL,
VCHIQ_MAKE_MSG(
VCHIQ_MSG_OPENACK,
service->localport,
remoteport),
- &body, 1, sizeof(ack_payload),
+ memcpy_copy_callback,
+ &ack_payload,
+ sizeof(ack_payload),
0) == VCHIQ_RETRY)
goto bail_not_ready;
} else {
- if (queue_message(state, NULL,
- VCHIQ_MAKE_MSG(
+ if (queue_message(state,
+ NULL,
+ VCHIQ_MAKE_MSG(
VCHIQ_MSG_OPENACK,
service->localport,
remoteport),
- &body, 1, sizeof(ack_payload),
+ memcpy_copy_callback,
+ &ack_payload,
+ sizeof(ack_payload),
0) == VCHIQ_RETRY)
goto bail_not_ready;
}
@@ -2630,14 +2679,19 @@ vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id)
service->version,
service->version_min
};
- VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) };
VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
service->client_id = client_id;
vchiq_use_service_internal(service);
- status = queue_message(service->state, NULL,
- VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0),
- &body, 1, sizeof(payload), QMFLAGS_IS_BLOCKING);
+ status = queue_message(service->state,
+ NULL,
+ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN,
+ service->localport,
+ 0),
+ memcpy_copy_callback,
+ &payload,
+ sizeof(payload),
+ QMFLAGS_IS_BLOCKING);
if (status == VCHIQ_SUCCESS) {
/* Wait for the ACK/NAK */
if (down_interruptible(&service->remove_event) != 0) {
@@ -3305,15 +3359,18 @@ vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY);
} else {
int payload[2] = { (int)(long)bulk->data, bulk->size };
- VCHIQ_ELEMENT_T element = { payload, sizeof(payload) };
- status = queue_message(state, NULL,
- VCHIQ_MAKE_MSG(dir_msgtype,
- service->localport, service->remoteport),
- &element, 1, sizeof(payload),
- QMFLAGS_IS_BLOCKING |
- QMFLAGS_NO_MUTEX_LOCK |
- QMFLAGS_NO_MUTEX_UNLOCK);
+ status = queue_message(state,
+ NULL,
+ VCHIQ_MAKE_MSG(dir_msgtype,
+ service->localport,
+ service->remoteport),
+ memcpy_copy_callback,
+ &payload,
+ sizeof(payload),
+ QMFLAGS_IS_BLOCKING |
+ QMFLAGS_NO_MUTEX_LOCK |
+ QMFLAGS_NO_MUTEX_UNLOCK);
if (status != VCHIQ_SUCCESS) {
goto unlock_both_error_exit;
}
@@ -3359,26 +3416,22 @@ vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
VCHIQ_STATUS_T
vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle,
- const VCHIQ_ELEMENT_T *elements, unsigned int count)
+ ssize_t (*copy_callback)(void *context, void *dest,
+ size_t offset, size_t maxsize),
+ void *context,
+ size_t size)
{
VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
VCHIQ_STATUS_T status = VCHIQ_ERROR;
- unsigned int size = 0;
- unsigned int i;
-
if (!service ||
(vchiq_check_service(service) != VCHIQ_SUCCESS))
goto error_exit;
- for (i = 0; i < (unsigned int)count; i++) {
- if (elements[i].size) {
- if (elements[i].data == NULL) {
- VCHIQ_SERVICE_STATS_INC(service, error_count);
- goto error_exit;
- }
- size += elements[i].size;
- }
+ if (!size) {
+ VCHIQ_SERVICE_STATS_INC(service, error_count);
+ goto error_exit;
+
}
if (size > VCHIQ_MAX_MSG_SIZE) {
@@ -3392,14 +3445,14 @@ vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle,
VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
service->localport,
service->remoteport),
- elements, count, size, 1);
+ copy_callback, context, size, 1);
break;
case VCHIQ_SRVSTATE_OPENSYNC:
status = queue_message_sync(service->state, service,
VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
service->localport,
service->remoteport),
- elements, count, size, 1);
+ copy_callback, context, size, 1);
break;
default:
status = VCHIQ_ERROR;
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h
index 1c2b1b5..9e16465 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h
@@ -634,9 +634,6 @@ vchiq_transfer_bulk(VCHIQ_BULK_T *bulk);
extern void
vchiq_complete_bulk(VCHIQ_BULK_T *bulk);
-extern VCHIQ_STATUS_T
-vchiq_copy_from_user(void *dst, const void *src, int size);
-
extern void
remote_event_signal(REMOTE_EVENT_T *event);
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h
index 8067bbe..377e8e4 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_if.h
@@ -141,9 +141,12 @@ extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service);
extern VCHIQ_STATUS_T vchiq_use_service_no_resume(
VCHIQ_SERVICE_HANDLE_T service);
extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service);
-
-extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service,
- const VCHIQ_ELEMENT_T *elements, unsigned int count);
+extern VCHIQ_STATUS_T
+vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle,
+ ssize_t (*copy_callback)(void *context, void *dest,
+ size_t offset, size_t maxsize),
+ void *context,
+ size_t size);
extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service,
VCHIQ_HEADER_T *header);
extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service,
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c
index 7694627..d977139 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c
@@ -148,10 +148,10 @@ EXPORT_SYMBOL(vchi_msg_remove);
* Name: vchi_msg_queue
*
* Arguments: VCHI_SERVICE_HANDLE_T handle,
- * const void *data,
- * uint32_t data_size,
- * VCHI_FLAGS_T flags,
- * void *msg_handle,
+ * ssize_t (*copy_callback)(void *context, void *dest,
+ * size_t offset, size_t maxsize),
+ * void *context,
+ * uint32_t data_size
*
* Description: Thin wrapper to queue a message onto a connection
*
@@ -159,21 +159,19 @@ EXPORT_SYMBOL(vchi_msg_remove);
*
***********************************************************/
int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle,
- const void *data,
- uint32_t data_size,
- VCHI_FLAGS_T flags,
- void *msg_handle)
+ ssize_t (*copy_callback)(void *context, void *dest,
+ size_t offset, size_t maxsize),
+ void *context,
+ uint32_t data_size)
{
SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
- VCHIQ_ELEMENT_T element = {data, data_size};
VCHIQ_STATUS_T status;
- (void)msg_handle;
-
- WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
-
while (1) {
- status = vchiq_queue_message(service->handle, &element, 1);
+ status = vchiq_queue_message(service->handle,
+ copy_callback,
+ context,
+ data_size);
/*
* vchiq_queue_message() may return VCHIQ_RETRY, so we need to
@@ -356,44 +354,6 @@ int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle,
EXPORT_SYMBOL(vchi_msg_dequeue);
/***********************************************************
- * Name: vchi_msg_queuev
- *
- * Arguments: VCHI_SERVICE_HANDLE_T handle,
- * VCHI_MSG_VECTOR_T *vector,
- * uint32_t count,
- * VCHI_FLAGS_T flags,
- * void *msg_handle
- *
- * Description: Thin wrapper to queue a message onto a connection
- *
- * Returns: int32_t - success == 0
- *
- ***********************************************************/
-
-vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T));
-vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) ==
- offsetof(VCHIQ_ELEMENT_T, data));
-vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) ==
- offsetof(VCHIQ_ELEMENT_T, size));
-
-int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle,
- VCHI_MSG_VECTOR_T *vector,
- uint32_t count,
- VCHI_FLAGS_T flags,
- void *msg_handle)
-{
- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-
- (void)msg_handle;
-
- WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
-
- return vchiq_status_to_vchi(vchiq_queue_message(service->handle,
- (const VCHIQ_ELEMENT_T *)vector, count));
-}
-EXPORT_SYMBOL(vchi_msg_queuev);
-
-/***********************************************************
* Name: vchi_held_msg_release
*
* Arguments: VCHI_HELD_MSG_T *message
--
2.10.1
^ permalink raw reply related
* Build regressions/improvements in v4.9-rc3
From: Geert Uytterhoeven @ 2016-10-30 13:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477829325-4495-1-git-send-email-geert@linux-m68k.org>
On Sun, Oct 30, 2016 at 1:08 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> Below is the list of build error/warning regressions/improvements in
> v4.9-rc3[1] compared to v4.8[2].
>
> Summarized:
> - build errors: +176/-3
+ /home/kisskb/slave/src/arch/arc/include/asm/atomic.h: Error: bad
instruction `llock r2,[r0]': => 184, 185
+ /home/kisskb/slave/src/arch/arc/include/asm/atomic.h: Error: bad
instruction `scond r2,[r0]': => 186, 187
[...]
+ /home/kisskb/slave/src/include/uapi/linux/swab.h: Error: bad
instruction `swape r3,r3': => 58
+ /home/kisskb/slave/src/include/uapi/linux/swab.h: Error: bad
instruction `swape r4,r4': => 58
arcompact/axs101_defconfig
+ /home/kisskb/slave/src/drivers/pci/host/pci-rcar-gen2.c: error:
implicit declaration of function 'of_n_addr_cells'
[-Werror=implicit-function-declaration]: => 303:2
arm-randconfig
See https://patchwork.kernel.org/patch/4289161/ and
https://patchwork.kernel.org/patch/8209431/
> [1] http://kisskb.ellerman.id.au/kisskb/head/11140/ (all 262 configs)
> [3] http://kisskb.ellerman.id.au/kisskb/head/11104/ (all 262 configs)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART
From: Greg Kroah-Hartman @ 2016-10-30 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bdd495a9-fa54-9049-ed08-22e03a898323@huawei.com>
On Sun, Oct 30, 2016 at 04:49:30PM +0800, Kefeng Wang wrote:
>
>
> On 2016/10/27 23:18, Greg Kroah-Hartman wrote:
> > On Mon, Oct 24, 2016 at 11:59:20AM +0800, Kefeng Wang wrote:
> >> Hi Greg, any more comments, thanks.
> >
> > Never wait, just resend if you have comments and you know you have to
> > fix them up...
> >
>
> Hi Greg, as I mentioned in previous mail, compatible "arm,sbsa-uart" need
> be provided by adding a new OF_EARLYCON_DECLARE(), this is the patch's point.
>
> And I no further update, could this patch be acceptable and be picked up?
It's long gone from my queue, please resend it if you think it should be
applied.
thanks,
greg k-h
^ permalink raw reply
* [PATCH v3 2/4] usb: musb: core: added helper function for parsing DT
From: Kevin Hilman @ 2016-10-30 13:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477560847-8929-3-git-send-email-abailon@baylibre.com>
Alexandre Bailon <abailon@baylibre.com> writes:
> From: Petr Kulhavy <petr@barix.com>
>
> This adds the function musb_get_mode() to get the DT property "dr_mode"
>
> Signed-off-by: Petr Kulhavy <petr@barix.com>
> Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> Tested-by: David Lechner <david@lechnology.com>
> ---
> drivers/usb/musb/musb_core.c | 19 +++++++++++++++++++
> drivers/usb/musb/musb_core.h | 5 +++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
> index 27dadc0..bba07e7 100644
> --- a/drivers/usb/musb/musb_core.c
> +++ b/drivers/usb/musb/musb_core.c
> @@ -100,6 +100,7 @@
> #include <linux/io.h>
> #include <linux/dma-mapping.h>
> #include <linux/usb.h>
> +#include <linux/usb/of.h>
>
> #include "musb_core.h"
> #include "musb_trace.h"
> @@ -130,6 +131,24 @@ static inline struct musb *dev_to_musb(struct device *dev)
> return dev_get_drvdata(dev);
> }
>
> +enum musb_mode musb_get_mode(struct device *dev)
> +{
> + enum usb_dr_mode mode;
> +
> + mode = usb_get_dr_mode(dev);
> + switch (mode) {
> + case USB_DR_MODE_HOST:
> + return MUSB_HOST;
> + case USB_DR_MODE_PERIPHERAL:
> + return MUSB_PERIPHERAL;
> + case USB_DR_MODE_OTG:
> + case USB_DR_MODE_UNKNOWN:
> + default:
> + return MUSB_OTG;
> + }
> +}
> +EXPORT_SYMBOL_GPL(musb_get_mode);
> +
> /*-------------------------------------------------------------------------*/
>
> #ifndef CONFIG_BLACKFIN
> diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
> index 2cb88a49..a406468 100644
> --- a/drivers/usb/musb/musb_core.h
> +++ b/drivers/usb/musb/musb_core.h
> @@ -617,4 +617,9 @@ static inline void musb_platform_post_root_reset_end(struct musb *musb)
> musb->ops->post_root_reset_end(musb);
> }
>
> +/* gets the "dr_mode" property from DT and converts it into musb_mode
> + * if the property is not found or not recognized returns MUSB_OTG
> + */
nit: multi-line comment style
> +extern enum musb_mode musb_get_mode(struct device *dev);
> +
> #endif /* __MUSB_CORE_H__ */
Otherwise,
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Kevin
^ permalink raw reply
* [PATCH V2 6/6] arm64: Add uprobe support
From: Catalin Marinas @ 2016-10-30 14:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <41cc70043792e65cbc3b4cc4ad7fbf6379afa550.1474960629.git.panand@redhat.com>
On Tue, Sep 27, 2016 at 01:18:00PM +0530, Pratyush Anand wrote:
> --- /dev/null
> +++ b/arch/arm64/kernel/probes/uprobes.c
> @@ -0,0 +1,221 @@
> +/*
> + * Copyright (C) 2014-2016 Pratyush Anand <panand@redhat.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/highmem.h>
> +#include <linux/ptrace.h>
> +#include <linux/uprobes.h>
> +#include <asm/cacheflush.h>
> +
> +#include "decode-insn.h"
> +
> +#define UPROBE_INV_FAULT_CODE UINT_MAX
> +
> +bool is_trap_insn(uprobe_opcode_t *insn)
> +{
> + return false;
> +}
On the previous series, I had a comment left unanswered with regards to
always returning false in is_trap_insn():
Looking at handle_swbp(), if we hit a breakpoint for which we don't have
a valid uprobe, this function currently sends a SIGTRAP. But if
is_trap_insn() returns false always, is_trap_at_addr() would return 0 in
this case so the SIGTRAP is never issued.
--
Catalin
^ permalink raw reply
* [PATCH 06/10] iio: adc: stm32: add ext attrs to configure sampling time
From: Jonathan Cameron @ 2016-10-30 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477412722-24061-7-git-send-email-fabrice.gasnier@st.com>
On 25/10/16 17:25, Fabrice Gasnier wrote:
> Add per channel "smpr" IIO extended attribute, to allow sampling
> time configuration.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
First thing is that any attributes need to be documented in
Documentation/ABI/testing/sysfs-bus-iio-*
Secondly this feels rather like it should be possible to use standard ABI for
this. The documentation manages to successfully skip passed the use of
any standard ADC terminology. I'm not actually sure what its
doing when it talks about sampling time... Does this device even have an
inbuilt track and hold? Presumably but who knows... Ah, the document
'How to get the best ADC accuracy in STM32FX ... ' gives some details in the
section on how to deal with high impedance sources. Worth adding a reference
to that for this.
Arguably the 'right' value for these is dependent on the local electrical
properties, so should be described in the device tree rather than tweaked
from userspace.
If you do want to do still want to provide userspace control then it
needs to fit nicely within the IIO ABI. Now arguably it's 'sort of'
integration time but only via a nasty non linear relationship so lets
not abuse that but rather work up something ADC specific.
As such we would be looking at something like.
in_voltageX_track_time and the units should be seconds (it'll be a pain, but
we need to end up with a generic ABI so it has to be in standard units).
It might make sense to add this to the core info_mask element list and
handle it that way. I'm still dubious that this isn't really a hardware
question that should never be exposed to userspace in the first place...
You will need to convince me ;)
A few more specific comments inline.
> ---
> drivers/iio/adc/stm32/stm32-adc.c | 75 +++++++++++++++++++++++++++++++++++++
> drivers/iio/adc/stm32/stm32-adc.h | 25 +++++++++++++
> drivers/iio/adc/stm32/stm32f4-adc.c | 48 ++++++++++++++++++++++++
> 3 files changed, 148 insertions(+)
>
> diff --git a/drivers/iio/adc/stm32/stm32-adc.c b/drivers/iio/adc/stm32/stm32-adc.c
> index 9b4b459..1681f75 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.c
> +++ b/drivers/iio/adc/stm32/stm32-adc.c
> @@ -38,6 +38,61 @@
> #include "stm32-adc.h"
>
> /**
> + * stm32_adc_conf_smp() - Configure sampling time for each channel
> + * @indio_dev: IIO device
> + * @scan_mask: channels to be converted
> + */
> +static int stm32_adc_conf_smp(struct iio_dev *indio_dev,
> + const unsigned long *scan_mask)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + const struct stm32_adc_regs *smp =
> + adc->common->data->adc_reginfo->smpr_regs;
> + struct stm32_adc_chan *stm32_chan;
> + const struct iio_chan_spec *chan;
> + u32 bit, val;
> + int i;
> +
> + for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
> + chan = indio_dev->channels + bit;
> + stm32_chan = to_stm32_chan(adc, chan);
> + i = chan->channel;
> +
> + if (i >= adc->max_channels)
> + return -EINVAL;
> +
> + val = stm32_adc_readl(adc, smp[i].reg);
> + val &= ~smp[i].mask;
> + val |= (stm32_chan->smpr << smp[i].shift) & smp[i].mask;
> + stm32_adc_writel(adc, smp[i].reg, val);
> + }
> +
> + return 0;
> +}
> +
> +int stm32_adc_set_smpr(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan, unsigned int smpr)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + struct stm32_adc_chan *stm32_chan = to_stm32_chan(adc, chan);
> +
> + stm32_chan->smpr = smpr;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(stm32_adc_set_smpr);
> +
> +int stm32_adc_get_smpr(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + struct stm32_adc_chan *stm32_chan = to_stm32_chan(adc, chan);
> +
> + return stm32_chan->smpr;
> +}
> +EXPORT_SYMBOL_GPL(stm32_adc_get_smpr);
> +
> +/**
> * stm32_adc_conf_scan_seq() - Build regular or injected channels scan sequence
> * @indio_dev: IIO device
> * @scan_mask: channels to be converted
> @@ -126,6 +181,12 @@ static int stm32_adc_conf_scan(struct iio_dev *indio_dev,
> return ret;
> }
>
> + ret = stm32_adc_conf_smp(indio_dev, scan_mask);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Failed to configure samp time\n");
> + goto err_dis;
> + }
> +
> ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
> if (ret) {
> dev_err(&indio_dev->dev, "Failed to configure sequence\n");
> @@ -938,6 +999,7 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev,
> const struct stm32_adc_info *adc_info)
> {
> struct stm32_adc *adc = iio_priv(indio_dev);
> + struct stm32_adc_common *common = adc->common;
> struct device_node *node = indio_dev->dev.of_node;
> struct property *prop;
> const __be32 *cur;
> @@ -945,6 +1007,19 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev,
> int scan_index = 0, num_channels = 0;
> u32 val;
>
> + if (!common->stm32_chans[adc->id]) {
> + /* Allocate extended attributes structure for an instance */
> + struct stm32_adc_chan *stm32_chans;
> +
> + stm32_chans = devm_kcalloc(&indio_dev->dev,
> + adc_info->max_channels,
> + sizeof(*stm32_chans), GFP_KERNEL);
> + if (!stm32_chans)
> + return -ENOMEM;
> +
> + common->stm32_chans[adc->id] = stm32_chans;
> + }
> +
> of_property_for_each_u32(node, "st,adc-channels", prop, cur, val)
> num_channels++;
>
> diff --git a/drivers/iio/adc/stm32/stm32-adc.h b/drivers/iio/adc/stm32/stm32-adc.h
> index 6c9b70d..8cf1d5c 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.h
> +++ b/drivers/iio/adc/stm32/stm32-adc.h
> @@ -143,6 +143,14 @@ struct stm32_adc_chan_spec {
> };
>
> /**
> + * struct stm32_adc_chan - Extended specifications of stm32 adc channels
> + * @smpr: per channel sampling time selection
> + */
> +struct stm32_adc_chan {
> + unsigned smpr:3;
> +};
> +
> +/**
> * struct stm32_adc_trig_info - ADC trigger info
> * @extsel: trigger selection for regular or injected
> * @name: name of the trigger, corresponding to its source
> @@ -206,6 +214,7 @@ struct stm32_adc_trig_reginfo {
> * @jdr: injected data registers offsets
> * @sqr_regs: Regular sequence registers description
> * @jsqr_reg: Injected sequence register description
> + * @smpr_regs: Sampling time registers description
> * @trig_reginfo: regular trigger control registers description
> * @jtrig_reginfo: injected trigger control registers description
> */
> @@ -220,6 +229,7 @@ struct stm32_adc_reginfo {
> u32 jdr[4];
> const struct stm32_adc_regs *sqr_regs;
> const struct stm32_adc_regs *jsqr_reg;
> + const struct stm32_adc_regs *smpr_regs;
> const struct stm32_adc_trig_reginfo *trig_reginfo;
> const struct stm32_adc_trig_reginfo *jtrig_reginfo;
> };
> @@ -328,6 +338,7 @@ struct stm32_adc {
> * @aclk: common clock for the analog circuitry
> * @vref: regulator reference
> * @vref_mv: vref voltage (mv)
> + * @stm32_chans: stm32 channels extended specification data
> * @gpio_descs: gpio descriptor used to configure EXTi triggers
> * @lock: mutex
> */
> @@ -341,11 +352,21 @@ struct stm32_adc_common {
> struct clk *aclk;
> struct regulator *vref;
> int vref_mv;
> + struct stm32_adc_chan *stm32_chans[STM32_ADC_ID_MAX];
> struct gpio_descs *gpios;
> struct mutex lock; /* read_raw lock */
> };
>
> /* Helper routines */
> +static inline struct stm32_adc_chan *to_stm32_chan(struct stm32_adc *adc,
> + const struct iio_chan_spec
> + *chan)
> +{
> + struct stm32_adc_chan *stm32_chans = adc->common->stm32_chans[adc->id];
> +
> + return &stm32_chans[chan->channel];
> +}
> +
> static inline int stm32_adc_start_conv(struct stm32_adc *adc)
> {
> return adc->common->data->start_conv(adc);
> @@ -458,6 +479,10 @@ static inline void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
>
> /* STM32 common extended attributes */
> extern const struct iio_enum stm32_adc_trig_pol;
> +int stm32_adc_set_smpr(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan, unsigned int smpr);
> +int stm32_adc_get_smpr(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan);
> int stm32_adc_probe(struct platform_device *pdev);
> int stm32_adc_remove(struct platform_device *pdev);
>
> diff --git a/drivers/iio/adc/stm32/stm32f4-adc.c b/drivers/iio/adc/stm32/stm32f4-adc.c
> index e033a68..e0e6211 100644
> --- a/drivers/iio/adc/stm32/stm32f4-adc.c
> +++ b/drivers/iio/adc/stm32/stm32f4-adc.c
> @@ -330,6 +330,32 @@ enum stm32f4_adc_smpr {
> };
>
> /**
> + * stm32f4_smpr_regs[] - describe sampling time registers & bit fields
> + * Sorted so it can be indexed by channel number.
> + */
> +static const struct stm32_adc_regs stm32f4_smpr_regs[] = {
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP0_MASK, STM32F4_SMP0_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP1_MASK, STM32F4_SMP1_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP2_MASK, STM32F4_SMP2_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP3_MASK, STM32F4_SMP3_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP4_MASK, STM32F4_SMP4_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP5_MASK, STM32F4_SMP5_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP6_MASK, STM32F4_SMP6_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP7_MASK, STM32F4_SMP7_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP8_MASK, STM32F4_SMP8_SHIFT },
> + { STM32F4_ADCX_SMPR2, STM32F4_SMP9_MASK, STM32F4_SMP9_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP10_MASK, STM32F4_SMP10_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP11_MASK, STM32F4_SMP11_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP12_MASK, STM32F4_SMP12_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP13_MASK, STM32F4_SMP13_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP14_MASK, STM32F4_SMP14_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP15_MASK, STM32F4_SMP15_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP16_MASK, STM32F4_SMP16_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP17_MASK, STM32F4_SMP17_SHIFT },
> + { STM32F4_ADCX_SMPR1, STM32F4_SMP18_MASK, STM32F4_SMP18_SHIFT },
> +};
> +
> +/**
> * stm32f4_sqr_regs - describe regular sequence registers
> * - L: sequence len (register & bit field)
> * - SQ1..SQ16: sequence entries (register & bit field)
> @@ -407,6 +433,7 @@ enum stm32f4_adc_smpr {
> },
> .sqr_regs = stm32f4_sqr_regs,
> .jsqr_reg = stm32f4_jsqr_reg,
> + .smpr_regs = stm32f4_smpr_regs,
> .trig_reginfo = &stm32f4_adc_trig_reginfo,
> .jtrig_reginfo = &stm32f4_adc_jtrig_reginfo,
> };
> @@ -555,7 +582,28 @@ static int stm32f4_adc_clk_sel(struct stm32_adc *adc)
> return 0;
> }
>
> +/* stm32f4_smpr_items : Channel-wise programmable sampling time */
> +static const char * const stm32f4_smpr_items[] = {
> + [STM32F4_SMPR_3_CK_CYCLES] = "3_cycles",
> + [STM32F4_SMPR_15_CK_CYCLES] = "15_cycles",
> + [STM32F4_SMPR_28_CK_CYCLES] = "28_cycles",
> + [STM32F4_SMPR_56_CK_CYCLES] = "56_cycles",
> + [STM32F4_SMPR_84_CK_CYCLES] = "84_cycles",
> + [STM32F4_SMPR_112_CK_CYCLES] = "112_cycles",
> + [STM32F4_SMPR_144_CK_CYCLES] = "144_cycles",
> + [STM32F4_SMPR_480_CK_CYCLES] = "480_cycles",
This is a whole level of nasty magic numbers. Always take real numeric
values and either provide an _available attribute listing the options,
or if appropriate round to the next best (probably up here).
Units shouldn't be in cycles as that has no meaning without a deep and
dirty knowledge of what clocks are being fed to the device. Stuff that
is at least tricky for userspace to work out. THis is a time, so it
should be in seconds.
> +};
> +
> +static const struct iio_enum stm32f4_smpr = {
> + .items = stm32f4_smpr_items,
> + .num_items = ARRAY_SIZE(stm32f4_smpr_items),
> + .get = stm32_adc_get_smpr,
> + .set = stm32_adc_set_smpr,
> +};
> +
> static const struct iio_chan_spec_ext_info stm32f4_adc_ext_info[] = {
> + IIO_ENUM("smpr", IIO_SEPARATE, &stm32f4_smpr),
> + IIO_ENUM_AVAILABLE("smpr", &stm32f4_smpr),
> IIO_ENUM("trigger_pol", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
> {
> .name = "trigger_pol_available",
>
^ permalink raw reply
* [PATCH v7 REPOST 0/9] CPUs capacity information for heterogeneous systems
From: Catalin Marinas @ 2016-10-30 14:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017154650.18779-1-juri.lelli@arm.com>
On Mon, Oct 17, 2016 at 04:46:41PM +0100, Juri Lelli wrote:
> I'm thus now assuming that everybody is OK with the patches and that they can
> be queued for 4.10 (we certainly need this plumbing at this point). Please
> speak if my assumption is wrong (and provide feedback! :).
> Otherwise I'm going to:
>
> - use Russell's patching system for patches 2 and 8
> - ask Sudeep to pull patches 3,5,6 and 7
> - ask Catalin/Will to pull patches 1,4 and 9
I'm happy to queue patches 1, 4 and 9 for 4.10 (though it might have
been easier for the whole series to go through arm-soc).
> Do you think we might get into trouble splitting the merge process this way?
Probably not. The only minor downside is that I have to grab a new DT
for Juno from Sudeep to test the patches. Not an issue, though.
--
Catalin
^ permalink raw reply
* [PATCH] arm64/kprobes: Tidy up sign-extension usage
From: Catalin Marinas @ 2016-10-30 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f25b75bf250827113d4269614ba7936e870b0646.1476794661.git.robin.murphy@arm.com>
On Tue, Oct 18, 2016 at 01:46:27PM +0100, Robin Murphy wrote:
> Kprobes does not need its own homebrewed (and frankly inscrutable) sign
> extension macro; just use the standard kernel functions instead. Since
> the compiler actually recognises the sign-extension idiom of the latter,
> we also get the small bonus of some nicer codegen, as each displacement
> calculation helper then compiles to a single optimal SBFX instruction.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Queued for 4.10. Thanks.
--
Catalin
^ permalink raw reply
* [PATCH] arm64: Remove pointless WARN_ON in DMA teardown
From: Catalin Marinas @ 2016-10-30 14:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <74f5ae2ead8bb8fa9fabcf88b5962885b29eb2d5.1477505971.git.robin.murphy@arm.com>
On Wed, Oct 26, 2016 at 07:19:31PM +0100, Robin Murphy wrote:
> We expect arch_teardown_dma_ops() to be called very late in a device's
> life, after it has been removed from its bus, and thus after the IOMMU
> bus notifier has run. As such, even if this funny little check did make
> sense, it's unlikely to achieve what it thinks it's trying to do anyway.
> It's a residual trace of an earlier implementation which didn't belong
> here from the start; belatedly snuff it out.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Queued for 4.10. Thanks.
--
Catalin
^ permalink raw reply
* [PATCH 05/10] iio: adc: stm32: add trigger polarity ext attr
From: Jonathan Cameron @ 2016-10-30 14:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477412722-24061-6-git-send-email-fabrice.gasnier@st.com>
On 25/10/16 17:25, Fabrice Gasnier wrote:
> Add trigger polarity extended attribute.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
ABI always needs documenting. Add docs also makes it easy to review
without diving into the code.
This will also need a convincing argument for why it doesn't belong in the
device tree.
J
> ---
> drivers/iio/adc/stm32/stm32-adc.c | 41 ++++++++++++++++++++++++++++++++++++-
> drivers/iio/adc/stm32/stm32-adc.h | 4 ++++
> drivers/iio/adc/stm32/stm32f4-adc.c | 12 +++++++++++
> 3 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iio/adc/stm32/stm32-adc.c b/drivers/iio/adc/stm32/stm32-adc.c
> index 1a13450..9b4b459 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.c
> +++ b/drivers/iio/adc/stm32/stm32-adc.c
> @@ -207,7 +207,11 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev,
>
> /* trigger source */
> extsel = trig_info[ret].extsel;
> - exten = STM32_EXTEN_HWTRIG_RISING_EDGE;
> +
> + /* default to rising edge if no polarity */
> + if (adc->exten == STM32_EXTEN_SWTRIG)
> + adc->exten = STM32_EXTEN_HWTRIG_RISING_EDGE;
> + exten = adc->exten;
> }
>
> spin_lock_irqsave(&adc->lock, flags);
> @@ -221,6 +225,40 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev,
> return 0;
> }
>
> +static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + unsigned int type)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + adc->exten = type;
> +
> + return 0;
> +}
> +
> +static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + return adc->exten;
> +}
> +
> +static const char * const stm32_trig_pol_items[] = {
> + [STM32_EXTEN_SWTRIG] = "swtrig",
> + [STM32_EXTEN_HWTRIG_RISING_EDGE] = "rising-edge",
> + [STM32_EXTEN_HWTRIG_FALLING_EDGE] = "falling-edge",
> + [STM32_EXTEN_HWTRIG_BOTH_EDGES] = "both-edges",
> +};
> +
> +const struct iio_enum stm32_adc_trig_pol = {
> + .items = stm32_trig_pol_items,
> + .num_items = ARRAY_SIZE(stm32_trig_pol_items),
> + .get = stm32_adc_get_trig_pol,
> + .set = stm32_adc_set_trig_pol,
> +};
> +EXPORT_SYMBOL_GPL(stm32_adc_trig_pol);
> +
> /**
> * stm32_adc_conv_irq_enable() - Unmask end of conversion irq
> * @adc: stm32 adc instance
> @@ -893,6 +931,7 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
> chan->scan_type.realbits = adc->common->data->highres;
> chan->scan_type.storagebits = STM32_STORAGEBITS;
> chan->scan_type.shift = 0;
> + chan->ext_info = adc->common->data->ext_info;
> }
>
> static int stm32_adc_chan_of_init(struct iio_dev *indio_dev,
> diff --git a/drivers/iio/adc/stm32/stm32-adc.h b/drivers/iio/adc/stm32/stm32-adc.h
> index fe3568b..6c9b70d 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.h
> +++ b/drivers/iio/adc/stm32/stm32-adc.h
> @@ -234,6 +234,7 @@ struct stm32_adc_reginfo {
> * @ext_triggers: Reference to trigger info for regular channels
> * @jext_triggers: Reference to trigger info for injected channels
> * @adc_reginfo: stm32 ADC registers description
> + * @ext_info: Extended channel info
> * @highres: Max resolution
> * @max_clock_rate: Max input clock rate
> * @clk_sel: routine to select common clock and prescaler
> @@ -251,6 +252,7 @@ struct stm32_adc_ops {
> const struct stm32_adc_trig_info *ext_triggers;
> const struct stm32_adc_trig_info *jext_triggers;
> const struct stm32_adc_reginfo *adc_reginfo;
> + const struct iio_chan_spec_ext_info *ext_info;
> int highres;
> unsigned long max_clock_rate;
> int (*clk_sel)(struct stm32_adc *adc);
> @@ -273,6 +275,7 @@ struct stm32_adc_ops {
> * @id: ADC instance number (e.g. adc 1, 2 or 3)
> * @offset: ADC instance register offset in ADC block
> * @max_channels: Max channels number for this ADC.
> + * @exten: External trigger config (enable/polarity)
> * @extrig_list: External trigger list (for regular channel)
> * @completion: end of single conversion completion
> * @buffer: data buffer
> @@ -295,6 +298,7 @@ struct stm32_adc {
> int id;
> int offset;
> int max_channels;
> + enum stm32_adc_exten exten;
> struct list_head extrig_list;
> struct completion completion;
> u16 *buffer;
> diff --git a/drivers/iio/adc/stm32/stm32f4-adc.c b/drivers/iio/adc/stm32/stm32f4-adc.c
> index 4d7a2a8..e033a68 100644
> --- a/drivers/iio/adc/stm32/stm32f4-adc.c
> +++ b/drivers/iio/adc/stm32/stm32f4-adc.c
> @@ -555,11 +555,23 @@ static int stm32f4_adc_clk_sel(struct stm32_adc *adc)
> return 0;
> }
>
> +static const struct iio_chan_spec_ext_info stm32f4_adc_ext_info[] = {
> + IIO_ENUM("trigger_pol", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
> + {
> + .name = "trigger_pol_available",
> + .shared = IIO_SHARED_BY_ALL,
> + .read = iio_enum_available_read,
> + .private = (uintptr_t)&stm32_adc_trig_pol,
> + },
> + {},
> +};
> +
> static const struct stm32_adc_ops stm32f4_adc_ops = {
> .adc_info = stm32f4_adc_info,
> .ext_triggers = stm32f4_adc_ext_triggers,
> .jext_triggers = stm32f4_adc_jext_triggers,
> .adc_reginfo = &stm32f4_adc_reginfo,
> + .ext_info = stm32f4_adc_ext_info,
> .highres = 12,
> .max_clock_rate = 36000000,
> .clk_sel = stm32f4_adc_clk_sel,
>
^ permalink raw reply
* [PATCH 04/10] iio: adc: stm32: add optional support for exti gpios
From: Jonathan Cameron @ 2016-10-30 14:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477412722-24061-5-git-send-email-fabrice.gasnier@st.com>
On 25/10/16 17:25, Fabrice Gasnier wrote:
> STM32 ADC may use EXTi signals routed internally as trigger source
> for conversions. Configure them as interrupt to configure this path
> in HW to adc.
> Note: interrupt handler isn't required here, and corresponding interrupt
> can be kept masked at exti controller level.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> drivers/iio/adc/stm32/stm32-adc.c | 45 +++++++++++++++++++++++++++++++++++++++
> drivers/iio/adc/stm32/stm32-adc.h | 3 +++
> 2 files changed, 48 insertions(+)
>
> diff --git a/drivers/iio/adc/stm32/stm32-adc.c b/drivers/iio/adc/stm32/stm32-adc.c
> index 25d0307..1a13450 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.c
> +++ b/drivers/iio/adc/stm32/stm32-adc.c
> @@ -482,6 +482,12 @@ static irqreturn_t stm32_adc_common_isr(int irq, void *data)
> return ret;
> }
>
> +static irqreturn_t stm32_adc_exti_handler(int irq, void *data)
> +{
> + /* Exti handler should not be invoqued, and is not used */
invoked.
> + return IRQ_HANDLED;
> +}
> +
> /**
> * stm32_adc_validate_trigger() - validate trigger for stm32 adc
> * @indio_dev: IIO device
> @@ -1051,6 +1057,41 @@ static void stm32_adc_unregister(struct stm32_adc *adc)
> }
> }
>
> +static int stm32_adc_exti_probe(struct stm32_adc_common *common)
> +{
> + int i, irq, ret;
> +
> + common->gpios = devm_gpiod_get_array_optional(common->dev, NULL,
> + GPIOD_IN);
> + if (!common->gpios)
> + return 0;
> +
> + for (i = 0; i < common->gpios->ndescs; i++) {
> + irq = gpiod_to_irq(common->gpios->desc[i]);
> + if (irq < 0) {
> + dev_err(common->dev, "gpio %d to irq failed\n", i);
> + return irq;
> + }
> +
> + ret = devm_request_irq(common->dev, irq, stm32_adc_exti_handler,
> + 0, dev_name(common->dev), common);
> + if (ret) {
> + dev_err(common->dev, "request IRQ %d failed\n", irq);
> + return ret;
> + }
> +
> + /*
> + * gpios are configured as interrupts, so exti trigger path is
> + * configured in HW. But getting interrupts when starting
> + * conversions is unused here, so mask it in on exti
> + * controller by default.
> + */
> + disable_irq(irq);
> + }
> +
> + return 0;
> +}
> +
> int stm32_adc_probe(struct platform_device *pdev)
> {
> struct device_node *np = pdev->dev.of_node, *child;
> @@ -1131,6 +1172,10 @@ int stm32_adc_probe(struct platform_device *pdev)
> goto err_clk_disable;
> }
>
> + ret = stm32_adc_exti_probe(common);
> + if (ret)
> + goto err_clk_disable;
> +
> /* Parse adc child nodes to retrieve master/slave instances data */
> for_each_available_child_of_node(np, child) {
> ret = stm32_adc_register(common, child);
> diff --git a/drivers/iio/adc/stm32/stm32-adc.h b/drivers/iio/adc/stm32/stm32-adc.h
> index 01a0dda..fe3568b 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.h
> +++ b/drivers/iio/adc/stm32/stm32-adc.h
> @@ -23,6 +23,7 @@
> #define __STM32_ADC_H
>
> #include <linux/dmaengine.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/irq_work.h>
>
> /*
> @@ -323,6 +324,7 @@ struct stm32_adc {
> * @aclk: common clock for the analog circuitry
> * @vref: regulator reference
> * @vref_mv: vref voltage (mv)
> + * @gpio_descs: gpio descriptor used to configure EXTi triggers
> * @lock: mutex
> */
> struct stm32_adc_common {
> @@ -335,6 +337,7 @@ struct stm32_adc_common {
> struct clk *aclk;
> struct regulator *vref;
> int vref_mv;
> + struct gpio_descs *gpios;
> struct mutex lock; /* read_raw lock */
> };
>
>
^ permalink raw reply
* [PATCH] arm64: mm: fix __page_to_voff definition
From: Catalin Marinas @ 2016-10-30 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477040326-21260-1-git-send-email-neeraju@codeaurora.org>
On Fri, Oct 21, 2016 at 02:28:46PM +0530, Neeraj Upadhyay wrote:
> Fix parameter name for __page_to_voff, to match its definition.
> At present, we don't see any issue, as page_to_virt's caller
> declares 'page'.
>
> Fixes: 9f2875912dac ("arm64: mm: restrict virt_to_page() to the linear mapping")
> Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
I'll queue this patch for 4.10. Thanks.
--
Catalin
^ permalink raw reply
* [PATCH v4 0/3] arm64/mm: use the contiguous attribute for kernel mappings
From: Catalin Marinas @ 2016-10-30 14:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477048978-4140-1-git-send-email-ard.biesheuvel@linaro.org>
On Fri, Oct 21, 2016 at 12:22:55PM +0100, Ard Biesheuvel wrote:
> Ard Biesheuvel (3):
> arm64: mm: BUG on unsupported manipulations of live kernel mappings
> arm64: mm: replace 'block_mappings_allowed' with 'page_mappings_only'
> arm64: mm: set the contiguous bit for kernel mappings where
> appropriate
Queued for 4.10. Thanks.
--
Catalin
^ permalink raw reply
* [PATCHv4 0/4] WX checking for arm64
From: Catalin Marinas @ 2016-10-30 15:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477585654-8908-1-git-send-email-labbott@redhat.com>
On Thu, Oct 27, 2016 at 09:27:30AM -0700, Laura Abbott wrote:
> Laura Abbott (4):
> arm64: dump: Make ptdump debugfs a separate option
> arm64: dump: Make the page table dumping seq_file optional
> arm64: dump: Remove max_addr
> arm64: dump: Add checking for writable and exectuable pages
Queued for 4.10. Thanks.
--
Catalin
^ permalink raw reply
* [PATCH 1/2] DT: binding: bcm2835-mbox: fix address typo in example
From: Andreas Färber @ 2016-10-30 15:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477505640-26658-1-git-send-email-stefan.wahren@i2se.com>
Am 26.10.2016 um 20:13 schrieb Stefan Wahren:
> The address of the mailbox node in the example has a typo.
> So fix it accordingly.
>
> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
> Fixes: d4b5c782b9f4 ("dt/bindings: Add binding for the BCM2835 mailbox driver")
> ---
> .../bindings/mailbox/brcm,bcm2835-mbox.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [PATCH 02/10] iio: adc: Add stm32 support
From: Jonathan Cameron @ 2016-10-30 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477412722-24061-3-git-send-email-fabrice.gasnier@st.com>
On 25/10/16 17:25, Fabrice Gasnier wrote:
> This patch adds support for STMicroelectronics STM32 MCU's analog to
> digital converter.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Hi Fabrice,
Sometimes I hate SoC ADCs. For some reason the hardware designers seem to
try and throw everything and the kitchen sink at them. Discontinuous mode
as an example in this device. Not seen that particular piece of fun before
and glad to see you haven't 'yet' tried to support it!
Anyhow, the complexity of the hardware leads to an initially complex driver.
My first thought it that this would be easier to follow / review if we
built it up in smaller steps. Perhaps ditch the injected channel support
entirely in the first instance. I also wonder if you don't need to support
that whole thing (injected sampling) as another iio device entirely using the
same channels. That's kind of what it is from a data flow point of view
(we've had arbitary sequencers before with priorities - don't think anyone
ever decided the pain was worth supporting the complexity, but right answer
has always been multiple IIO devices).
You also have at least one layer of abstraction in here that serves no
current purpose. Please clear that out for now. It'll make the code
shorter and easier to follow. If/when other parts are introduced then
is the time to do that transistion to having the abstraction.
My first thought on the double / tripple adc handling is that you'd be better
off handling them as 3 separate devices then doing some 'unusual' trigger
handling to support the weird sequencing. Guessing you thought about that?
If so could you lay out your reasoning for the single driver instance approach.
I'm not arguing against it btw, merely want to understand your reasoning!
It would be tricky given one set of channels are selectable over 3 devices
and there are constraints to enforce (not sampling same channel on two ADCs
at the same time) but not impossible... Perhaps what you have here is
indeed simpler!
Whilst it's been a nasty job to review, I'm guessing writing it was
much worse ;) Pretty good starting point though might take a little while
to pin down the remaining questions on how best to handle this particular
monster.
Jonathan
> ---
> drivers/iio/adc/Kconfig | 2 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/stm32/Kconfig | 34 ++
> drivers/iio/adc/stm32/Makefile | 4 +
> drivers/iio/adc/stm32/stm32-adc.c | 999 ++++++++++++++++++++++++++++++++++++
> drivers/iio/adc/stm32/stm32-adc.h | 442 ++++++++++++++++
> drivers/iio/adc/stm32/stm32f4-adc.c | 574 +++++++++++++++++++++
> 7 files changed, 2056 insertions(+)
> create mode 100644 drivers/iio/adc/stm32/Kconfig
> create mode 100644 drivers/iio/adc/stm32/Makefile
> create mode 100644 drivers/iio/adc/stm32/stm32-adc.c
> create mode 100644 drivers/iio/adc/stm32/stm32-adc.h
> create mode 100644 drivers/iio/adc/stm32/stm32f4-adc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 7edcf32..5c96a55 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -583,4 +583,6 @@ config XILINX_XADC
> The driver can also be build as a module. If so, the module will be called
> xilinx-xadc.
>
> +source "drivers/iio/adc/stm32/Kconfig"
> +
> endmenu
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index 7a40c04..a9dbf3a 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_AD7791) += ad7791.o
> obj-$(CONFIG_AD7793) += ad7793.o
> obj-$(CONFIG_AD7887) += ad7887.o
> obj-$(CONFIG_AD799X) += ad799x.o
> +obj-$(CONFIG_ARCH_STM32) += stm32/
> obj-$(CONFIG_AT91_ADC) += at91_adc.o
> obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
> obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
> diff --git a/drivers/iio/adc/stm32/Kconfig b/drivers/iio/adc/stm32/Kconfig
> new file mode 100644
> index 0000000..245d037
> --- /dev/null
> +++ b/drivers/iio/adc/stm32/Kconfig
> @@ -0,0 +1,34 @@
> +#
> +# STM32 familly ADC drivers
> +#
> +
> +config STM32_ADC
> + tristate
> + select REGULATOR
> + select REGULATOR_FIXED_VOLTAGE
> + select IIO_BUFFER
> + select IIO_TRIGGERED_BUFFER
> + help
> + Say yes here to build the driver for the STMicroelectronics
> + STM32 analog-to-digital converter (ADC).
> +
> + This driver can also be built as a module. If so, the module
> + will be called stm32-adc.
> +
> +config STM32F4_ADC
> + tristate "STMicroelectronics STM32F4 adc"
> + depends on ARCH_STM32 || COMPILE_TEST
> + depends on OF
> + select STM32_ADC
> + help
> + Say yes here to build support for STMicroelectronics stm32f4 Analog
> + to Digital Converter (ADC).
> +
> + This driver can also be built as a module. If so, the module
> + will be called stm32f4-adc.
> +
> +config STM32_ADC_DEBUG
> + bool "Enable debug for stm32 ADC drivers"
> + depends on STM32_ADC
> + help
> + Say "yes" to enable debug messages, on stm32 ADC drivers.
> diff --git a/drivers/iio/adc/stm32/Makefile b/drivers/iio/adc/stm32/Makefile
> new file mode 100644
> index 0000000..83e8154
> --- /dev/null
> +++ b/drivers/iio/adc/stm32/Makefile
> @@ -0,0 +1,4 @@
> +# Core
> +subdir-ccflags-$(CONFIG_STM32_ADC_DEBUG) := -DDEBUG
> +obj-$(CONFIG_STM32_ADC) += stm32-adc.o
> +obj-$(CONFIG_STM32F4_ADC) += stm32f4-adc.o
> diff --git a/drivers/iio/adc/stm32/stm32-adc.c b/drivers/iio/adc/stm32/stm32-adc.c
> new file mode 100644
> index 0000000..1e0850d
> --- /dev/null
> +++ b/drivers/iio/adc/stm32/stm32-adc.c
> @@ -0,0 +1,999 @@
> +/*
> + * This file is part of STM32 ADC driver
> + *
> + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/debugfs.h>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/buffer.h>
> +#include <linux/iio/events.h>
> +#include <linux/iio/trigger.h>
> +#include <linux/iio/trigger_consumer.h>
> +#include <linux/iio/triggered_buffer.h>
> +#include <linux/iio/sysfs.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +#include "stm32-adc.h"
> +
> +/**
> + * stm32_adc_conf_scan_seq() - Build regular or injected channels scan sequence
> + * @indio_dev: IIO device
> + * @scan_mask: channels to be converted
> + *
> + * Conversion sequence :
> + * Configure ADC scan sequence based on selected channels in scan_mask.
> + * Add channels to SQR or JSQR registers, from scan_mask LSB to MSB, then
> + * program sequence len.
> + *
> + * Note: This can be done only when ADC enabled and no conversion is ongoing.
> + */
> +static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
> + const unsigned long *scan_mask)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + const struct stm32_adc_regs *sq;
> + const struct iio_chan_spec *chan;
> + u32 val, bit;
> + int sq_max, i = 0;
> +
> + if (!stm32_adc_is_enabled(adc))
> + return -EBUSY;
> +
> + if (adc->injected) {
> + if (stm32_adc_injected_started(adc))
> + return -EBUSY;
> +
> + sq = adc->common->data->adc_reginfo->jsqr_reg;
> + sq_max = STM32_ADC_MAX_JSQ;
> + } else {
> + if (stm32_adc_regular_started(adc))
> + return -EBUSY;
> +
> + sq = adc->common->data->adc_reginfo->sqr_regs;
> + sq_max = STM32_ADC_MAX_SQ;
> + }
> +
> + /* Build sequence for regular or injected channels */
> + for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
> + chan = indio_dev->channels + bit;
> + /*
> + * Assign one channel per SQ/JSQ entry in regular/injected
> + * sequence, starting with SQ1/JSQ1.
> + */
> + i++;
> + if (i > sq_max)
> + return -EINVAL;
> +
> + dev_dbg(adc->common->dev, "%s chan %d to %s%d\n",
> + __func__, chan->channel, adc->injected ? "JSQ" : "SQ",
> + i);
> +
> + val = stm32_adc_readl(adc, sq[i].reg);
> + val &= ~sq[i].mask;
> + val |= (chan->channel << sq[i].shift) & sq[i].mask;
> + stm32_adc_writel(adc, sq[i].reg, val);
> + }
> +
> + if (!i)
> + return -EINVAL;
> +
> + /* Sequence len */
> + val = stm32_adc_readl(adc, sq[0].reg);
> + val &= ~sq[0].mask;
> + val |= ((i - 1) << sq[0].shift) & sq[0].mask;
> + stm32_adc_writel(adc, sq[0].reg, val);
> +
> + return 0;
> +}
> +
> +static int stm32_adc_conf_scan(struct iio_dev *indio_dev,
> + const unsigned long *scan_mask)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + int ret;
> +
> + ret = stm32_adc_clk_sel(adc);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Clock sel failed\n");
> + return ret;
> + }
> +
> + ret = stm32_adc_enable(adc);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Failed to enable adc\n");
> + return ret;
> + }
> +
> + ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Failed to configure sequence\n");
> + goto err_dis;
> + }
It's horrible but to end up in the 'obvious' state I'd disable the adc
again assuming that doesn't kill the stuff that is configured.
> +
> + return 0;
> +
> +err_dis:
> + stm32_adc_disable(adc);
> +
> + return ret;
> +}
> +
> +/**
> + * stm32_adc_get_trig_index() - Get trigger index
> + * @indio_dev: IIO device
> + * @trig: trigger
> + *
> + * Returns trigger index, if trig matches one of the triggers registered by
> + * stm32 adc driver, -EINVAL otherwise.
> + */
> +static int stm32_adc_get_trig_index(struct iio_dev *indio_dev,
> + struct iio_trigger *trig)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + struct iio_trigger *tr;
> + int i = 0;
> +
> + list_for_each_entry(tr, &adc->extrig_list, alloc_list) {
> + if (tr == trig)
> + return i;
> + i++;
> + }
> +
> + return -EINVAL;
> +}
> +
> +/**
> + * stm32_adc_set_trig() - Set a regular or injected trigger
> + * @indio_dev: IIO device
> + * @trig: IIO trigger
> + *
> + * Set trigger source/polarity (e.g. SW, or HW with polarity) :
> + * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
> + * - if HW trigger enabled, set source & polarity (trigger_pol / jtrigger_pol)
> + *
> + * Note: must be called when ADC is enabled
> + */
> +static int stm32_adc_set_trig(struct iio_dev *indio_dev,
> + struct iio_trigger *trig)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + const struct stm32_adc_trig_info *trig_info;
> + const struct stm32_adc_trig_reginfo *reginfo;
> + u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
> + unsigned long flags;
> + int ret;
> +
> + if (!stm32_adc_is_enabled(adc))
> + return -EBUSY;
> +
> + if (adc->injected) {
> + if (stm32_adc_injected_started(adc))
> + return -EBUSY;
> + reginfo = adc->common->data->adc_reginfo->jtrig_reginfo;
> + trig_info = adc->common->data->jext_triggers;
> + } else {
> + if (stm32_adc_regular_started(adc))
> + return -EBUSY;
> + reginfo = adc->common->data->adc_reginfo->trig_reginfo;
> + trig_info = adc->common->data->ext_triggers;
> + }
> +
> + if (trig) {
> + ret = stm32_adc_get_trig_index(indio_dev, trig);
> + if (ret < 0)
> + return ret;
> +
> + /* trigger source */
> + extsel = trig_info[ret].extsel;
> + exten = STM32_EXTEN_HWTRIG_RISING_EDGE;
> + }
> +
> + spin_lock_irqsave(&adc->lock, flags);
> + val = stm32_adc_readl(adc, reginfo->reg);
> + val &= ~(reginfo->exten_mask | reginfo->extsel_mask);
> + val |= (exten << reginfo->exten_shift) & reginfo->exten_mask;
> + val |= (extsel << reginfo->extsel_shift) & reginfo->extsel_mask;
> + stm32_adc_writel(adc, reginfo->reg, val);
> + spin_unlock_irqrestore(&adc->lock, flags);
> +
> + return 0;
> +}
> +
> +/**
> + * stm32_adc_conv_irq_enable() - Unmask end of conversion irq
> + * @adc: stm32 adc instance
> + *
> + * Unmask either eoc or jeoc, depending on injected configuration.
> + */
> +static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
> +{
> + const struct stm32_adc_reginfo *reginfo =
> + adc->common->data->adc_reginfo;
> + u32 mask;
> +
> + if (adc->injected)
> + mask = reginfo->jeocie;
> + else
> + mask = reginfo->eocie;
> +
> + stm32_adc_set_bits(adc, reginfo->ier, mask);
> +}
> +
> +/**
> + * stm32_adc_conv_irq_disable() - Mask end of conversion irq
> + * @adc: stm32 adc instance
> + *
> + * Mask either eoc or jeoc, depending on injected configuration.
> + */
> +static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
> +{
> + const struct stm32_adc_reginfo *reginfo =
> + adc->common->data->adc_reginfo;
> + u32 mask;
> +
> + if (adc->injected)
> + mask = reginfo->jeocie;
> + else
> + mask = reginfo->eocie;
> +
> + stm32_adc_clr_bits(adc, reginfo->ier, mask);
> +}
> +
> +/**
> + * stm32_adc_single_conv() - perform a single conversion
> + * @indio_dev: IIO device
> + * @chan: IIO channel
> + * @result: conversion result
> + *
> + * The function performs a single conversion on a given channel, by
> + * by:
> + * - creating scan mask with only one channel
> + * - using SW trigger
> + * - then start single conv
> + */
> +static int stm32_adc_single_conv(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + unsigned long *scan_mask;
> + long timeout;
> + u16 result;
> + int ret;
> +
> + scan_mask = kcalloc(BITS_TO_LONGS(indio_dev->masklength), sizeof(long),
> + GFP_KERNEL);
This is known maximum length... I'd just avoid the complexity of allocating
it like this - a comment would do the job to say it is the right length.
> + if (!scan_mask)
> + return -ENOMEM;
> +
> + set_bit(chan->scan_index, scan_mask);
> +
> + reinit_completion(&adc->completion);
> +
> + adc->bufi = 0;
> + adc->num_conv = 1;
> + adc->buffer = &result;
> +
> + ret = stm32_adc_conf_scan(indio_dev, scan_mask);
> + if (ret)
> + goto free;
> +
> + /* No HW trigger: conversion can be launched in SW */
> + ret = stm32_adc_set_trig(indio_dev, NULL);
Put it back again afterwards? Otherwise some nasty race conditions look
likely to me.. (userspace sets trigger and is about to enable the buffer
when along comes this code and changes it underneath).
> + if (ret) {
> + dev_err(&indio_dev->dev, "Can't set SW trigger\n");
> + goto adc_disable;
> + }
> +
> + stm32_adc_conv_irq_enable(adc);
> +
> + ret = stm32_adc_start_conv(adc);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Failed to start single conv\n");
> + goto irq_disable;
> + }
> +
> + timeout = wait_for_completion_interruptible_timeout(
> + &adc->completion, STM32_ADC_TIMEOUT);
> + if (timeout == 0) {
> + dev_warn(&indio_dev->dev, "Conversion timed out!\n");
> + ret = -ETIMEDOUT;
> + } else if (timeout < 0) {
> + dev_warn(&indio_dev->dev, "Interrupted conversion!\n");
> + ret = -EINTR;
> + } else {
> + *val = result & STM32_RESULT_MASK;
> + ret = IIO_VAL_INT;
> + }
> +
> + if (stm32_adc_stop_conv(adc))
> + dev_err(&indio_dev->dev, "stop failed\n");
> +
> +irq_disable:
> + stm32_adc_conv_irq_disable(adc);
> +
> +adc_disable:
> + stm32_adc_disable(adc);
> +
> +free:
> + kfree(scan_mask);
> + adc->buffer = NULL;
> +
> + return ret;
> +}
> +
> +static int stm32_adc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + int ret = -EINVAL;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + ret = iio_device_claim_direct_mode(indio_dev);
> + if (ret)
> + return ret;
> + if (chan->type == IIO_VOLTAGE)
> + ret = stm32_adc_single_conv(indio_dev, chan, val);
> + iio_device_release_direct_mode(indio_dev);
> + break;
> + case IIO_CHAN_INFO_SCALE:
> + *val = adc->common->vref_mv;
> + *val2 = chan->scan_type.realbits;
> + ret = IIO_VAL_FRACTIONAL_LOG2;
> + break;
> + default:
> + break;
> + }
> +
> + return ret;
> +}
> +
> +/**
> + * stm32_adc_isr() - Treat interrupt for one ADC instance within ADC block
As this is kernel doc please document the parameter as well. Otherwise
we'll get a pile of warnings!
> + */
> +static irqreturn_t stm32_adc_isr(struct stm32_adc *adc)
> +{
> + struct iio_dev *indio_dev = iio_priv_to_dev(adc);
> + const struct stm32_adc_reginfo *reginfo =
> + adc->common->data->adc_reginfo;
> + u32 mask, clr_mask, status = stm32_adc_readl(adc, reginfo->isr);
> +
> + if (adc->injected) {
> + mask = reginfo->jeoc;
> + clr_mask = mask;
> + } else {
> + mask = reginfo->eoc;
> + /* don't clear 'eoc' as it is cleared when reading 'dr' */
> + clr_mask = 0;
> + }
> +
> + /* clear irq */
> + stm32_adc_writel(adc, reginfo->isr, status & ~clr_mask);
Want to do this in the non injected case? it's a noop isn't it?
> + status &= mask;
> +
> + /* Regular data */
> + if (status & reginfo->eoc) {
Hmm.. this is a little bit of 'missuse' of the standard trigger architecture
but as long as it's restricted to just this device I don't suppose we need
to care. Only reason we need it is to provide control of 'which' hardware
trigger is being used.
Guessing the DMA will almost always be turned on and will make this oddity
effectively disappear.
> + adc->buffer[adc->bufi] = stm32_adc_readl(adc, reginfo->dr);
> + if (iio_buffer_enabled(indio_dev)) {
> + adc->bufi++;
> + if (adc->bufi >= adc->num_conv) {
> + stm32_adc_conv_irq_disable(adc);
> + iio_trigger_poll(indio_dev->trig);
> + }
> + } else {
> + complete(&adc->completion);
> + }
> + }
> +
> + /* Injected data */
> + if (status & reginfo->jeoc) {
> + int i;
> +
> + for (i = 0; i < adc->num_conv; i++) {
> + adc->buffer[i] = stm32_adc_readl(adc, reginfo->jdr[i]);
> + adc->bufi++;
> + }
> +
> + if (iio_buffer_enabled(indio_dev)) {
> + stm32_adc_conv_irq_disable(adc);
> + iio_trigger_poll(indio_dev->trig);
> + } else {
> + complete(&adc->completion);
> + }
> + }
> +
> + /*
> + * In case end of conversion flags have been handled, this has been
> + * handled for this ADC instance
> + */
> + if (status)
> + return IRQ_HANDLED;
> +
> + /* This adc instance didn't trigger this interrupt */
> + return IRQ_NONE;
> +}
> +
> +/**
> + * stm32_adc_common_isr() - Common isr for the whole ADC block
> + *
> + * There is one IRQ for all ADCs in ADC block, check all instances.
> + */
> +static irqreturn_t stm32_adc_common_isr(int irq, void *data)
> +{
> + struct stm32_adc_common *common = data;
> + irqreturn_t ret = IRQ_NONE;
> + struct stm32_adc *adc;
> +
> + list_for_each_entry(adc, &common->adc_list, adc_list)
> + ret |= stm32_adc_isr(adc);
Hmm.. ret |= is rather fragile. Preferable to make the handling of NONE
vs IRQ_HANDLED explicit.
If you were to split the driver up as I suggested might make sense above,
then this would be done with an irq chip in a top level device (effectively
a very simple mfd).
> +
> + return ret;
> +}
> +
> +/**
> + * stm32_adc_validate_trigger() - validate trigger for stm32 adc
> + * @indio_dev: IIO device
> + * @trig: new trigger
> + *
> + * Returns: 0 if trig matches one of the triggers registered by stm32 adc
> + * driver, -EINVAL otherwise.
> + */
> +static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
> + struct iio_trigger *trig)
> +{
> + return stm32_adc_get_trig_index(indio_dev, trig) < 0 ? -EINVAL : 0;
> +}
> +
> +static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
> + const unsigned long *scan_mask)
I'm glad you kept this relatively simple compared to some of the
'fun' the hardware is capable of. Very wise!
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + int ret;
> + u32 bit;
> +
> + adc->num_conv = 0;
> + for_each_set_bit(bit, scan_mask, indio_dev->masklength)
> + adc->num_conv++;
> +
> + ret = stm32_adc_conf_scan(indio_dev, scan_mask);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
> + const struct of_phandle_args *iiospec)
> +{
> + int i;
> +
> + for (i = 0; i < indio_dev->num_channels; i++)
> + if (indio_dev->channels[i].channel == iiospec->args[0])
> + return i;
> +
> + return -EINVAL;
> +}
> +
> +/**
> + * stm32_adc_debugfs_reg_access - read or write register value
> + *
> + * To read a value from an ADC register:
> + * echo [ADC reg offset] > direct_reg_access
> + * cat direct_reg_access
> + *
> + * To write a value in a ADC register:
> + * echo [ADC_reg_offset] [value] > direct_reg_access
> + */
> +static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
> + unsigned reg, unsigned writeval,
> + unsigned *readval)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + if (!readval)
> + stm32_adc_writel(adc, reg, writeval);
> + else
> + *readval = stm32_adc_readl(adc, reg);
> +
> + return 0;
> +}
> +
> +static const struct iio_info stm32_adc_iio_info = {
> + .read_raw = stm32_adc_read_raw,
> + .validate_trigger = stm32_adc_validate_trigger,
> + .update_scan_mode = stm32_adc_update_scan_mode,
> + .debugfs_reg_access = stm32_adc_debugfs_reg_access,
> + .of_xlate = stm32_adc_of_xlate,
> + .driver_module = THIS_MODULE,
> +};
> +
> +static int stm32_adc_buffer_postdisable(struct iio_dev *indio_dev)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + stm32_adc_disable(adc);
This is a surprise as postdisbale should balance preenable...
Ah, you have update scan mode enabling the adc. If you can balance it
better by moving that to preenable please do as it is more 'obviously' correct.
> +
> + return 0;
> +}
> +
> +static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
> + .postenable = &iio_triggered_buffer_postenable,
> + .predisable = &iio_triggered_buffer_predisable,
> + .postdisable = &stm32_adc_buffer_postdisable,
> +};
> +
> +static int stm32_adc_validate_device(struct iio_trigger *trig,
> + struct iio_dev *indio_dev)
> +{
> + struct iio_dev *indio = iio_trigger_get_drvdata(trig);
> +
> + return indio != indio_dev ? -EINVAL : 0;
> +}
> +
> +static int stm32_adc_set_trigger_state(struct iio_trigger *trig,
> + bool state)
> +{
> + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + int ret;
> +
> + if (state) {
> + /* Reset adc buffer index */
> + adc->bufi = 0;
> +
> + /* Allocate adc buffer */
> + adc->buffer = kzalloc(indio_dev->scan_bytes, GFP_KERNEL);
I'd be more cynical. It's not that big a memory allocation at worst.
Just put a big enough buffer in your adc structure and don't bother doing
it dynamically.
If you didn't want to do it, it should be in the preenable callback rather
than the trigger state one (for semantic reasons rather than because it's a
bug)
> + if (!adc->buffer)
> + return -ENOMEM;
> +
> + ret = stm32_adc_set_trig(indio_dev, trig);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Can't set trigger\n");
> + goto err_buffer_free;
> + }
> +
> + stm32_adc_conv_irq_enable(adc);
> +
> + ret = stm32_adc_start_conv(adc);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Failed to start\n");
> + goto err_irq_trig_disable;
> + }
> + } else {
> + ret = stm32_adc_stop_conv(adc);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev, "Failed to stop\n");
> + return ret;
> + }
> +
> + stm32_adc_conv_irq_disable(adc);
> +
> + ret = stm32_adc_set_trig(indio_dev, NULL);
> + if (ret)
> + dev_warn(&indio_dev->dev, "Can't clear trigger\n");
> +
> + kfree(adc->buffer);
> + adc->buffer = NULL;
> + }
> +
> + return 0;
> +
> +err_irq_trig_disable:
> + stm32_adc_conv_irq_disable(adc);
> + stm32_adc_set_trig(indio_dev, NULL);
> +
> +err_buffer_free:
> + kfree(adc->buffer);
> + adc->buffer = NULL;
> +
> + return ret;
> +}
> +
> +static const struct iio_trigger_ops stm32_adc_trigger_ops = {
> + .owner = THIS_MODULE,
> + .validate_device = stm32_adc_validate_device,
> + .set_trigger_state = stm32_adc_set_trigger_state,
> +};
> +
> +static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
> +{
> + struct iio_poll_func *pf = p;
> + struct iio_dev *indio_dev = pf->indio_dev;
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
> +
> + /* reset buffer index */
> + adc->bufi = 0;
> + iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
> + pf->timestamp);
> +
> + iio_trigger_notify_done(indio_dev->trig);
> +
> + /* re-enable eoc irq */
> + stm32_adc_conv_irq_enable(adc);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void stm32_adc_trig_unregister(struct iio_dev *indio_dev)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + struct iio_trigger *trig, *_t;
> +
> + list_for_each_entry_safe(trig, _t, &adc->extrig_list, alloc_list) {
> + iio_trigger_unregister(trig);
> + list_del(&trig->alloc_list);
> + }
> +}
> +
I'd like a bit of documentation on this and a few of the other more
complex functions. Here it wasn't immediately obvious to me that it
was registering a large set of triggers. Also, silly question but
do you have any means of controlling the various timer setups from userspace?
There have been numerous discussions over the years on having a generic
timer subsystem, but if anything got written it passed me by. I have a couple
of boards where it would be handy but never had the time to do more than
talk about it ;)
> +static int stm32_adc_trig_register(struct iio_dev *indio_dev)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + struct stm32_adc_common *common = adc->common;
> + const struct stm32_adc_trig_info *ext = common->data->ext_triggers;
> + struct iio_trigger *trig;
> + int i, ret = 0;
> +
> + if (adc->injected)
> + ext = common->data->jext_triggers;
> + else
> + ext = common->data->ext_triggers;
> +
> + for (i = 0; ext && ext[i].name; i++) {
> + trig = devm_iio_trigger_alloc(common->dev, "%s_%s%d_%s",
> + indio_dev->name,
> + adc->injected ? "jext" : "ext",
> + ext[i].extsel, ext[i].name);
> + if (!trig) {
> + dev_err(common->dev, "trig %s_%s%d_%s alloc failed\n",
> + indio_dev->name,
> + adc->injected ? "jext" : "ext",
> + ext[i].extsel, ext[i].name);
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + trig->dev.parent = common->dev;
> + trig->ops = &stm32_adc_trigger_ops;
> + iio_trigger_set_drvdata(trig, indio_dev);
> +
> + ret = iio_trigger_register(trig);
> + if (ret) {
> + dev_err(common->dev,
> + "trig %s_%s%d_%s register failed\n",
> + indio_dev->name,
> + adc->injected ? "jext" : "ext",
> + ext[i].extsel, ext[i].name);
> + goto err;
> + }
> +
> + list_add_tail(&trig->alloc_list, &adc->extrig_list);
> + }
> +
> + return 0;
> +err:
> + stm32_adc_trig_unregister(indio_dev);
> +
> + return ret;
> +}
> +
> +static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
> + struct iio_chan_spec *chan,
> + const struct stm32_adc_chan_spec *channel,
> + int scan_index)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + chan->type = channel->type;
> + chan->channel = channel->channel;
> + chan->datasheet_name = channel->name;
> + chan->extend_name = channel->name;
> + chan->scan_index = scan_index;
> + chan->indexed = 1;
> + chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
> + chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
> + chan->scan_type.sign = 'u';
> + chan->scan_type.realbits = adc->common->data->highres;
> + chan->scan_type.storagebits = STM32_STORAGEBITS;
This is one of those cases where actually I'd argue just having the number
here and not under a define would be clearer! So just put 16 here.
> + chan->scan_type.shift = 0;
Should be unneeded. Shift of 0 is the obvious default so no info provided
to readers of the code either really.
> +}
> +
> +static int stm32_adc_chan_of_init(struct iio_dev *indio_dev,
> + const struct stm32_adc_info *adc_info)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + struct device_node *node = indio_dev->dev.of_node;
> + struct property *prop;
> + const __be32 *cur;
> + struct iio_chan_spec *channels;
> + int scan_index = 0, num_channels = 0;
> + u32 val;
> +
> + of_property_for_each_u32(node, "st,adc-channels", prop, cur, val)
> + num_channels++;
> +
> + channels = devm_kcalloc(&indio_dev->dev, num_channels,
> + sizeof(struct iio_chan_spec), GFP_KERNEL);
> + if (!channels)
> + return -ENOMEM;
> +
> + of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
> + stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
> + &adc_info->channels[val],
> + scan_index);
> + scan_index++;
> + }
> +
> + adc->max_channels = adc_info->max_channels;
> + indio_dev->num_channels = scan_index;
> + indio_dev->channels = channels;
> +
> + return 0;
> +}
> +
> +static int stm32_adc_register(struct stm32_adc_common *common,
> + struct device_node *child)
> +{
> + struct iio_dev *indio_dev;
> + struct stm32_adc *adc;
> + int i, ret;
> + u32 reg;
> +
> + ret = of_property_read_u32(child, "reg", ®);
> + if (ret != 0) {
> + dev_err(common->dev, "missing reg property\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; common->data->adc_info[i].channels; i++)
> + if (common->data->adc_info[i].reg == reg)
> + break;
> +
> + if (i >= STM32_ADC_ID_MAX || !common->data->adc_info[i].channels) {
> + dev_err(common->dev, "bad adc reg offset\n");
> + return -ENOENT;
> + }
> +
> + indio_dev = devm_iio_device_alloc(common->dev, sizeof(*adc));
> + if (!indio_dev) {
> + dev_err(common->dev, "iio device allocation failed\n");
> + return -ENOMEM;
> + }
> +
> + adc = iio_priv(indio_dev);
> + adc->id = i;
> + adc->offset = reg;
> + adc->common = common;
> + INIT_LIST_HEAD(&adc->extrig_list);
> + spin_lock_init(&adc->lock);
> + init_completion(&adc->completion);
> +
> + if (child->name)
> + indio_dev->name = child->name;
> + else
> + indio_dev->name = common->data->adc_info[i].name;
> + indio_dev->dev.parent = common->dev;
> + indio_dev->dev.of_node = child;
> + indio_dev->info = &stm32_adc_iio_info;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> +
> + if (of_property_read_bool(child, "st,injected")) {
> + dev_dbg(common->dev, "%s Configured to use injected\n",
> + indio_dev->name);
> + adc->injected = true;
> + }
> +
> + adc->clk = of_clk_get(child, 0);
> + if (IS_ERR(adc->clk)) {
> + adc->clk = NULL;
> + dev_dbg(common->dev, "No child clk found\n");
> + } else {
> + ret = clk_prepare_enable(adc->clk);
> + if (ret < 0)
> + goto err_clk_put;
> + }
> +
> + ret = stm32_adc_chan_of_init(indio_dev, &common->data->adc_info[i]);
> + if (ret < 0) {
> + dev_err(common->dev, "iio channels init failed\n");
> + goto err_clk_disable;
> + }
> +
> + ret = stm32_adc_trig_register(indio_dev);
> + if (ret)
> + goto err_clk_disable;
> +
> + ret = iio_triggered_buffer_setup(indio_dev,
> + &iio_pollfunc_store_time,
> + &stm32_adc_trigger_handler,
> + &iio_triggered_buffer_setup_ops);
> + if (ret) {
> + dev_err(common->dev, "buffer setup failed\n");
> + goto err_trig_unregister;
> + }
> +
> + ret = iio_device_register(indio_dev);
> + if (ret) {
> + dev_err(common->dev, "iio dev register failed\n");
> + goto err_buffer_cleanup;
> + }
> +
> + list_add_tail(&adc->adc_list, &common->adc_list);
> +
> + return 0;
> +
> +err_buffer_cleanup:
> + iio_triggered_buffer_cleanup(indio_dev);
> +
> +err_trig_unregister:
> + stm32_adc_trig_unregister(indio_dev);
> +
> +err_clk_disable:
> + if (adc->clk)
> + clk_disable_unprepare(adc->clk);
> +
> +err_clk_put:
> + if (adc->clk)
> + clk_put(adc->clk);
> +
> + return ret;
> +}
> +
> +static void stm32_adc_unregister(struct stm32_adc *adc)
> +{
> + struct iio_dev *indio_dev = iio_priv_to_dev(adc);
> +
> + iio_device_unregister(indio_dev);
> + iio_triggered_buffer_cleanup(indio_dev);
> + stm32_adc_trig_unregister(indio_dev);
> + if (adc->clk) {
> + clk_disable_unprepare(adc->clk);
> + clk_put(adc->clk);
> + }
> +}
> +
> +int stm32_adc_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node, *child;
> + struct device *dev = &pdev->dev;
> + const struct of_device_id *match;
> + struct stm32_adc_common *common;
> + struct stm32_adc *adc;
> + struct resource *res;
> + int ret;
> +
> + match = of_match_device(dev->driver->of_match_table, &pdev->dev);
> + if (!match || !match->data) {
> + dev_err(&pdev->dev, "compatible data not provided\n");
How would we have instantiated this if there was not a suitable match?
As such what does this check give us? (confused!)
> + return -EINVAL;
> + }
> +
> + common = devm_kzalloc(&pdev->dev, sizeof(*common), GFP_KERNEL);
> + if (!common)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + common->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(common->base))
> + return PTR_ERR(common->base);
> +
> + common->data = match->data;
> + common->dev = &pdev->dev;
> + platform_set_drvdata(pdev, common);
> + mutex_init(&common->lock);
> + INIT_LIST_HEAD(&common->adc_list);
> +
> + common->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(common->vref)) {
> + ret = PTR_ERR(common->vref);
> + dev_err(&pdev->dev, "vref get failed, %d\n", ret);
> + return ret;
> + }
> +
> + ret = regulator_enable(common->vref);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "vref enable failed\n");
> + return ret;
> + }
> +
> + ret = regulator_get_voltage(common->vref);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
> + goto err_regulator_disable;
> + }
> + common->vref_mv = ret / 1000;
> + dev_dbg(&pdev->dev, "vref+=%dmV\n", common->vref_mv);
> +
> + common->aclk = devm_clk_get(&pdev->dev, "adc");
> + if (IS_ERR(common->aclk)) {
> + ret = PTR_ERR(common->aclk);
> + dev_err(&pdev->dev, "Can't get 'adc' clock\n");
> + goto err_regulator_disable;
> + }
> +
> + ret = clk_prepare_enable(common->aclk);
> + if (ret < 0) {
> + dev_err(common->dev, "adc clk enable failed\n");
> + goto err_regulator_disable;
> + }
> +
> + common->irq = platform_get_irq(pdev, 0);
> + if (common->irq < 0) {
> + dev_err(&pdev->dev, "failed to get irq\n");
> + ret = common->irq;
> + goto err_clk_disable;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, common->irq, stm32_adc_common_isr,
> + 0, pdev->name, common);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to request irq\n");
> + goto err_clk_disable;
> + }
> +
> + /* Parse adc child nodes to retrieve master/slave instances data */
> + for_each_available_child_of_node(np, child) {
> + ret = stm32_adc_register(common, child);
> + if (ret)
> + goto err_unregister;
> + }
> +
> + dev_info(&pdev->dev, "registered\n");
No benefit in this info being provided (it's obvious, device just turned up
in sysfs :) So drop it.
> +
> + return 0;
> +
> +err_unregister:
> + list_for_each_entry(adc, &common->adc_list, adc_list)
> + stm32_adc_unregister(adc);
> +
> +err_clk_disable:
> + clk_disable_unprepare(common->aclk);
> +
> +err_regulator_disable:
> + regulator_disable(common->vref);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(stm32_adc_probe);
> +
> +int stm32_adc_remove(struct platform_device *pdev)
> +{
> + struct stm32_adc_common *common = platform_get_drvdata(pdev);
> + struct stm32_adc *adc;
> +
> + list_for_each_entry(adc, &common->adc_list, adc_list)
> + stm32_adc_unregister(adc);
> + clk_disable_unprepare(common->aclk);
> + regulator_disable(common->vref);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(stm32_adc_remove);
> +
> +MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 ADC driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/iio/adc/stm32/stm32-adc.h b/drivers/iio/adc/stm32/stm32-adc.h
> new file mode 100644
> index 0000000..0be603c
> --- /dev/null
> +++ b/drivers/iio/adc/stm32/stm32-adc.h
> @@ -0,0 +1,442 @@
> +/*
> + * This file is part of STM32 ADC driver
> + *
> + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __STM32_ADC_H
> +#define __STM32_ADC_H
> +
> +/*
> + * STM32 - ADC global register map
> + * ________________________________________________________
> + * | Offset | Register |
> + * --------------------------------------------------------
> + * | 0x000 | Master ADC1 |
> + * --------------------------------------------------------
> + * | 0x100 | Slave ADC2 |
> + * --------------------------------------------------------
> + * | 0x200 | Slave ADC3 |
> + * --------------------------------------------------------
> + * | 0x300 | Master & Slave common regs |
> + * --------------------------------------------------------
> + */
> +#define STM32_ADCX_COMN_OFFSET 0x300
> +#define STM32_ADC_ID_MAX 3
> +#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
> +#define STM32_ADC_MAX_JSQ 4 /* JSQ1..JSQ4 */
> +
> +/* STM32 value masks */
> +#define STM32_RESULT_MASK GENMASK(15, 0)
> +#define STM32_STORAGEBITS 16
> +
> +/* External trigger enable for regular or injected channels (exten/jexten) */
> +enum stm32_adc_exten {
> + STM32_EXTEN_SWTRIG,
> + STM32_EXTEN_HWTRIG_RISING_EDGE,
> + STM32_EXTEN_HWTRIG_FALLING_EDGE,
> + STM32_EXTEN_HWTRIG_BOTH_EDGES,
> +};
> +
> +enum stm32_adc_extsel {
> + STM32_EXT0,
> + STM32_EXT1,
> + STM32_EXT2,
> + STM32_EXT3,
> + STM32_EXT4,
> + STM32_EXT5,
> + STM32_EXT6,
> + STM32_EXT7,
> + STM32_EXT8,
> + STM32_EXT9,
> + STM32_EXT10,
> + STM32_EXT11,
> + STM32_EXT12,
> + STM32_EXT13,
> + STM32_EXT14,
> + STM32_EXT15,
> + STM32_EXT16,
> + STM32_EXT17,
> + STM32_EXT18,
> + STM32_EXT19,
> + STM32_EXT20,
> + STM32_EXT21,
> + STM32_EXT22,
> + STM32_EXT23,
> + STM32_EXT24,
> + STM32_EXT25,
> + STM32_EXT26,
> + STM32_EXT27,
> + STM32_EXT28,
> + STM32_EXT29,
> + STM32_EXT30,
> + STM32_EXT31,
> +};
> +
> +enum stm32_adc_jextsel {
> + STM32_JEXT0,
> + STM32_JEXT1,
> + STM32_JEXT2,
> + STM32_JEXT3,
> + STM32_JEXT4,
> + STM32_JEXT5,
> + STM32_JEXT6,
> + STM32_JEXT7,
> + STM32_JEXT8,
> + STM32_JEXT9,
> + STM32_JEXT10,
> + STM32_JEXT11,
> + STM32_JEXT12,
> + STM32_JEXT13,
> + STM32_JEXT14,
> + STM32_JEXT15,
> + STM32_JEXT16,
> + STM32_JEXT17,
> + STM32_JEXT18,
> + STM32_JEXT19,
> + STM32_JEXT20,
> + STM32_JEXT21,
> + STM32_JEXT22,
> + STM32_JEXT23,
> + STM32_JEXT24,
> + STM32_JEXT25,
> + STM32_JEXT26,
> + STM32_JEXT27,
> + STM32_JEXT28,
> + STM32_JEXT29,
> + STM32_JEXT30,
> + STM32_JEXT31,
> +};
> +
> +#define STM32_ADC_TIMEOUT_US 100000
> +#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
> +
> +/**
> + * struct stm32_adc_chan_spec - specification of stm32 adc channel
> + * @type: IIO channel type
> + * @channel: channel number (single ended)
> + * @name: channel name (single ended)
> + */
> +struct stm32_adc_chan_spec {
> + enum iio_chan_type type;
> + int channel;
> + const char *name;
> +};
> +
> +/**
> + * struct stm32_adc_trig_info - ADC trigger info
> + * @extsel: trigger selection for regular or injected
> + * @name: name of the trigger, corresponding to its source
> + */
> +struct stm32_adc_trig_info {
> + u32 extsel;
> + const char *name;
> +};
> +
> +/**
> + * struct stm32_adc_info - stm32 ADC, per instance config data
> + * @name: default name for this instance (like "adc1")
> + * @reg: reg offset for this instance (e.g. 0x0 for adc1...)
> + * @channels: Reference to stm32 channels spec
> + * @max_channels: Number of single ended channels
> + */
> +struct stm32_adc_info {
> + const char *name;
> + u32 reg;
> + const struct stm32_adc_chan_spec *channels;
> + int max_channels;
> +};
> +
> +/**
> + * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
> + * @reg: register offset
> + * @mask: bitfield mask
> + * @shift: left shift
> + */
> +struct stm32_adc_regs {
> + int reg;
> + int mask;
> + int shift;
> +};
> +
> +/**
> + * stm32_adc_trig_reginfo - stm32 ADC trigger control registers description
> + * @reg: trigger control register offset (exten/jexten)
> + * @exten_mask: external trigger en/polarity mask in @reg
> + * @exten_shift: external trigger en/polarity shift in @reg
> + * @extsel_mask: external trigger source mask in @reg
> + * @extsel_shift: external trigger source shift in @reg
> + */
> +struct stm32_adc_trig_reginfo {
> + u32 reg;
> + u32 exten_mask;
> + u32 exten_shift;
> + u32 extsel_mask;
> + u32 extsel_shift;
> +};
> +
> +/**
> + * struct stm32_adc_reginfo - stm32 ADC registers description
> + * @isr: interrupt status register offset
> + * @eoc: end of conversion mask in @isr
> + * @jeoc: end of injected conversion sequence mask in @isr
> + * @ier: interrupt enable register offset
> + * @eocie: end of conversion interrupt enable mask in @ier
> + * @jeocie: end of injected conversion sequence interrupt en mask
> + * @dr: data register offset
> + * @jdr: injected data registers offsets
> + * @sqr_regs: Regular sequence registers description
> + * @jsqr_reg: Injected sequence register description
> + * @trig_reginfo: regular trigger control registers description
> + * @jtrig_reginfo: injected trigger control registers description
> + */
> +struct stm32_adc_reginfo {
> + u32 isr;
> + u32 eoc;
> + u32 jeoc;
> + u32 ier;
> + u32 eocie;
> + u32 jeocie;
> + u32 dr;
> + u32 jdr[4];
> + const struct stm32_adc_regs *sqr_regs;
> + const struct stm32_adc_regs *jsqr_reg;
> + const struct stm32_adc_trig_reginfo *trig_reginfo;
> + const struct stm32_adc_trig_reginfo *jtrig_reginfo;
> +};
> +
> +struct stm32_adc;
> +
> +/**
> + * struct stm32_adc_ops - stm32 ADC, compatible dependent data
> + * - stm32 ADC may work as single ADC, or as tightly coupled master/slave ADCs.
> + *
> + * @adc_info: Array spec for stm32 adc master/slaves instances
> + * @ext_triggers: Reference to trigger info for regular channels
> + * @jext_triggers: Reference to trigger info for injected channels
> + * @adc_reginfo: stm32 ADC registers description
> + * @highres: Max resolution
> + * @max_clock_rate: Max input clock rate
> + * @clk_sel: routine to select common clock and prescaler
> + * @start_conv: routine to start conversions
> + * @stop_conv: routine to stop conversions
> + * @is_started: routine to get adc 'started' state
> + * @regular_started routine to check regular conversions status
> + * @injected_started routine to check injected conversions status
> + * @enable: optional routine to enable stm32 adc
> + * @disable: optional routine to disable stm32 adc
> + * @is_enabled reports enabled state
> + */
This is a big chunk of abstraction that seems excessive at the moment.
I'd rather see it introduced only just before it's actually used..
(I'm guessing it's intended for support of similar parts?)
Right now it just makes the driver harder to review.
> +struct stm32_adc_ops {
> + const struct stm32_adc_info *adc_info;
> + const struct stm32_adc_trig_info *ext_triggers;
> + const struct stm32_adc_trig_info *jext_triggers;
> + const struct stm32_adc_reginfo *adc_reginfo;
> + int highres;
> + unsigned long max_clock_rate;
> + int (*clk_sel)(struct stm32_adc *adc);
> + int (*start_conv)(struct stm32_adc *adc);
> + int (*stop_conv)(struct stm32_adc *adc);
> + bool (*is_started)(struct stm32_adc *adc);
> + bool (*regular_started)(struct stm32_adc *adc);
> + bool (*injected_started)(struct stm32_adc *adc);
> + int (*enable)(struct stm32_adc *adc);
> + void (*disable)(struct stm32_adc *adc);
> + bool (*is_enabled)(struct stm32_adc *adc);
> +};
> +
> +struct stm32_adc_common;
> +
> +/**
> + * struct stm32_adc - private data of each ADC IIO instance
> + * @common: reference to ADC block common data
> + * @adc_list: current ADC entry in common ADC list
> + * @id: ADC instance number (e.g. adc 1, 2 or 3)
> + * @offset: ADC instance register offset in ADC block
> + * @max_channels: Max channels number for this ADC.
> + * @extrig_list: External trigger list (for regular channel)
> + * @completion: end of single conversion completion
> + * @buffer: data buffer
> + * @bufi: data buffer index
> + * @num_conv: expected number of scan conversions
> + * @injected: use injected channels on this adc
> + * @lock: spinlock
> + * @clk: optional adc clock, for this adc instance
> + * @calib: optional calibration data
> + * @en: emulates enabled state on some stm32 adc
> + */
> +struct stm32_adc {
> + struct stm32_adc_common *common;
> + struct list_head adc_list;
> + int id;
> + int offset;
> + int max_channels;
> + struct list_head extrig_list;
> + struct completion completion;
> + u16 *buffer;
> + int bufi;
> + int num_conv;
> + bool injected;
> + spinlock_t lock; /* interrupt lock */
> + struct clk *clk;
> + void *calib;
> + bool en;
> +};
> +
> +/**
> + * struct stm32_adc_common - private data of ADC driver, common to all
> + * ADC instances (ADC block)
> + * @dev: device for this controller
> + * @base: control registers base cpu addr
> + * @irq: Common irq line for all adc instances
> + * @data: STM32 dependent data from compatible
> + * @adc_list: list of all stm32 ADC in this ADC block
> + * @aclk: common clock for the analog circuitry
> + * @vref: regulator reference
> + * @vref_mv: vref voltage (mv)
> + * @lock: mutex
> + */
> +struct stm32_adc_common {
> + struct device *dev;
> + void __iomem *base;
> + int irq;
> + const struct stm32_adc_ops *data;
> + struct list_head adc_list;
> + struct clk *aclk;
> + struct regulator *vref;
> + int vref_mv;
> + struct mutex lock; /* read_raw lock */
> +};
> +
> +/* Helper routines */
> +static inline int stm32_adc_start_conv(struct stm32_adc *adc)
> +{
> + return adc->common->data->start_conv(adc);
> +}
> +
> +static inline int stm32_adc_stop_conv(struct stm32_adc *adc)
> +{
> + return adc->common->data->stop_conv(adc);
> +}
> +
> +static inline bool stm32_adc_is_started(struct stm32_adc *adc)
> +{
> + return adc->common->data->is_started(adc);
> +}
> +
> +static inline bool stm32_adc_regular_started(struct stm32_adc *adc)
> +{
> + return adc->common->data->regular_started(adc);
> +}
> +
> +static inline bool stm32_adc_injected_started(struct stm32_adc *adc)
> +{
> + return adc->common->data->injected_started(adc);
> +}
> +
> +static inline bool stm32_adc_clk_sel(struct stm32_adc *adc)
> +{
> + return adc->common->data->clk_sel(adc);
> +}
> +
> +static inline int stm32_adc_enable(struct stm32_adc *adc)
> +{
> + if (adc->common->data->enable)
> + return adc->common->data->enable(adc);
> +
> + adc->en = true;
> +
> + return 0;
> +}
> +
> +static inline bool stm32_adc_is_enabled(struct stm32_adc *adc)
> +{
> + if (adc->common->data->is_enabled)
> + return adc->common->data->is_enabled(adc);
> + else
> + return adc->en;
> +}
> +
> +static inline void stm32_adc_disable(struct stm32_adc *adc)
> +{
> + /* Check there is no regular or injected on-going conversions */
> + if (stm32_adc_is_started(adc))
> + return;
> +
> + if (adc->common->data->disable)
> + adc->common->data->disable(adc);
> + else
> + adc->en = false;
> +}
> +
> +/* STM32 ADC registers access routines */
> +static inline u32 stm32_adc_common_readl(struct stm32_adc_common *com, u32 reg)
> +{
> + u32 val = readl_relaxed(com->base + reg);
> +
> + return val;
> +}
> +
> +static inline void stm32_adc_common_writel(struct stm32_adc_common *com,
> + u32 reg, u32 val)
> +{
> + writel_relaxed(val, com->base + reg);
> +}
> +
> +static inline u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
> +{
> + u32 val = readl_relaxed(adc->common->base + adc->offset + reg);
> +
> + return val;
> +}
> +
> +#define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
> +
> +#define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
> + readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
> + cond, sleep_us, timeout_us)
> +
> +static inline void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
> +{
> + writel_relaxed(val, adc->common->base + adc->offset + reg);
> +}
> +
> +static inline void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&adc->lock, flags);
> + stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
> + spin_unlock_irqrestore(&adc->lock, flags);
> +}
> +
> +static inline void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&adc->lock, flags);
> + stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
> + spin_unlock_irqrestore(&adc->lock, flags);
> +}
> +
> +/* STM32 common extended attributes */
> +extern const struct iio_enum stm32_adc_trig_pol;
> +int stm32_adc_probe(struct platform_device *pdev);
> +int stm32_adc_remove(struct platform_device *pdev);
> +
> +#endif
> diff --git a/drivers/iio/adc/stm32/stm32f4-adc.c b/drivers/iio/adc/stm32/stm32f4-adc.c
> new file mode 100644
> index 0000000..147fe9c
> --- /dev/null
> +++ b/drivers/iio/adc/stm32/stm32f4-adc.c
> @@ -0,0 +1,574 @@
> +/*
> + * This file is part of STM32F4 ADC driver
> + *
> + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/trigger.h>
> +#include <linux/platform_device.h>
> +#include "stm32-adc.h"
> +
> +/*
> + * STM32F4 - ADC global register map
> + * ________________________________________________________
> + * | Offset | Register |
> + * --------------------------------------------------------
> + * | 0x000 | Master ADC1 |
> + * --------------------------------------------------------
> + * | 0x100 | Slave ADC2 |
> + * --------------------------------------------------------
> + * | 0x200 | Slave ADC3 |
> + * --------------------------------------------------------
> + * | 0x300 | Master & Slave common regs |
> + * --------------------------------------------------------
> + */
> +
> +/* STM32F4 - Registers for each ADC instance */
> +#define STM32F4_ADCX_SR 0x00
> +#define STM32F4_ADCX_CR1 0x04
> +#define STM32F4_ADCX_CR2 0x08
> +#define STM32F4_ADCX_SMPR1 0x0C
> +#define STM32F4_ADCX_SMPR2 0x10
> +#define STM32F4_ADCX_HTR 0x24
> +#define STM32F4_ADCX_LTR 0x28
> +#define STM32F4_ADCX_SQR1 0x2C
> +#define STM32F4_ADCX_SQR2 0x30
> +#define STM32F4_ADCX_SQR3 0x34
> +#define STM32F4_ADCX_JSQR 0x38
> +#define STM32F4_ADCX_JDR1 0x3C
> +#define STM32F4_ADCX_JDR2 0x40
> +#define STM32F4_ADCX_JDR3 0x44
> +#define STM32F4_ADCX_JDR4 0x48
> +#define STM32F4_ADCX_DR 0x4C
> +
> +/* STM32 - Master & slave registers (common for all instances: 1, 2 & 3) */
> +#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
> +#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
> +#define STM32F4_ADC_CDR (STM32_ADCX_COMN_OFFSET + 0x08)
> +
> +/* STM32F4_ADCX_SR - bit fields */
> +#define STM32F4_OVR BIT(5)
> +#define STM32F4_STRT BIT(4)
> +#define STM32F4_JSTRT BIT(3)
> +#define STM32F4_JEOC BIT(2)
> +#define STM32F4_EOC BIT(1)
> +#define STM32F4_AWD BIT(0)
> +
> +/* STM32F4_ADCX_CR1 - bit fields */
> +#define STM32F4_OVRIE BIT(26)
> +#define STM32F4_RES_SHIFT 24
> +#define STM32F4_RES_MASK GENMASK(25, 24)
> +#define STM32F4_AWDEN BIT(23)
> +#define STM32F4_JAWDEN BIT(22)
> +#define STM32F4_DISCNUM_SHIFT 13
> +#define STM32F4_DISCNUM_MASK GENMASK(15, 13)
> +#define STM32F4_JDISCEN BIT(12)
> +#define STM32F4_DISCEN BIT(11)
> +#define STM32F4_JAUTO BIT(10)
> +#define STM32F4_AWDSGL BIT(9)
> +#define STM32F4_SCAN BIT(8)
> +#define STM32F4_JEOCIE BIT(7)
> +#define STM32F4_AWDIE BIT(6)
> +#define STM32F4_EOCIE BIT(5)
> +#define STM32F4_AWDCH_SHIFT 0
> +#define STM32F4_AWDCH_MASK GENMASK(4, 0)
> +
> +/* STM32F4_ADCX_CR2 - bit fields */
> +#define STM32F4_SWSTART BIT(30)
> +#define STM32F4_EXTEN_SHIFT 28
> +#define STM32F4_EXTEN_MASK GENMASK(29, 28)
> +#define STM32F4_EXTSEL_SHIFT 24
> +#define STM32F4_EXTSEL_MASK GENMASK(27, 24)
> +#define STM32F4_JSWSTART BIT(22)
> +#define STM32F4_JEXTEN_SHIFT 20
> +#define STM32F4_JEXTEN_MASK GENMASK(21, 20)
> +#define STM32F4_JEXTSEL_SHIFT 16
> +#define STM32F4_JEXTSEL_MASK GENMASK(19, 16)
> +#define STM32F4_ALIGN BIT(11)
> +#define STM32F4_EOCS BIT(10)
> +#define STM32F4_DDS BIT(9)
> +#define STM32F4_DMA BIT(8)
> +#define STM32F4_CONT BIT(1)
> +#define STM32F4_ADON BIT(0)
> +
> +/* STM32F4_ADCX_SMPR1 - bit fields */
> +#define STM32F4_SMP18_SHIFT 24
> +#define STM32F4_SMP18_MASK GENMASK(26, 24)
> +#define STM32F4_SMP17_SHIFT 21
> +#define STM32F4_SMP17_MASK GENMASK(23, 21)
> +#define STM32F4_SMP16_SHIFT 18
> +#define STM32F4_SMP16_MASK GENMASK(20, 18)
> +#define STM32F4_SMP15_SHIFT 15
> +#define STM32F4_SMP15_MASK GENMASK(17, 15)
> +#define STM32F4_SMP14_SHIFT 12
> +#define STM32F4_SMP14_MASK GENMASK(14, 12)
> +#define STM32F4_SMP13_SHIFT 9
> +#define STM32F4_SMP13_MASK GENMASK(11, 9)
> +#define STM32F4_SMP12_SHIFT 6
> +#define STM32F4_SMP12_MASK GENMASK(8, 6)
> +#define STM32F4_SMP11_SHIFT 3
> +#define STM32F4_SMP11_MASK GENMASK(5, 3)
> +#define STM32F4_SMP10_SHIFT 0
> +#define STM32F4_SMP10_MASK GENMASK(2, 0)
> +
> +/* STM32F4_ADCX_SMPR2 - bit fields */
> +#define STM32F4_SMP9_SHIFT 27
> +#define STM32F4_SMP9_MASK GENMASK(29, 27)
> +#define STM32F4_SMP8_SHIFT 24
> +#define STM32F4_SMP8_MASK GENMASK(26, 24)
> +#define STM32F4_SMP7_SHIFT 21
> +#define STM32F4_SMP7_MASK GENMASK(23, 21)
> +#define STM32F4_SMP6_SHIFT 18
> +#define STM32F4_SMP6_MASK GENMASK(20, 18)
> +#define STM32F4_SMP5_SHIFT 15
> +#define STM32F4_SMP5_MASK GENMASK(17, 15)
> +#define STM32F4_SMP4_SHIFT 12
> +#define STM32F4_SMP4_MASK GENMASK(14, 12)
> +#define STM32F4_SMP3_SHIFT 9
> +#define STM32F4_SMP3_MASK GENMASK(11, 9)
> +#define STM32F4_SMP2_SHIFT 6
> +#define STM32F4_SMP2_MASK GENMASK(8, 6)
> +#define STM32F4_SMP1_SHIFT 3
> +#define STM32F4_SMP1_MASK GENMASK(5, 3)
> +#define STM32F4_SMP0_SHIFT 0
> +#define STM32F4_SMP0_MASK GENMASK(2, 0)
> +enum stm32f4_adc_smpr {
> + STM32F4_SMPR_3_CK_CYCLES,
> + STM32F4_SMPR_15_CK_CYCLES,
> + STM32F4_SMPR_28_CK_CYCLES,
> + STM32F4_SMPR_56_CK_CYCLES,
> + STM32F4_SMPR_84_CK_CYCLES,
> + STM32F4_SMPR_112_CK_CYCLES,
> + STM32F4_SMPR_144_CK_CYCLES,
> + STM32F4_SMPR_480_CK_CYCLES,
> +};
> +
> +/* STM32F4_ADCX_SQR1 - bit fields */
> +#define STM32F4_L_SHIFT 20
> +#define STM32F4_L_MASK GENMASK(23, 20)
> +#define STM32F4_SQ16_SHIFT 15
> +#define STM32F4_SQ16_MASK GENMASK(19, 15)
> +#define STM32F4_SQ15_SHIFT 10
> +#define STM32F4_SQ15_MASK GENMASK(14, 10)
> +#define STM32F4_SQ14_SHIFT 5
> +#define STM32F4_SQ14_MASK GENMASK(9, 5)
> +#define STM32F4_SQ13_SHIFT 0
> +#define STM32F4_SQ13_MASK GENMASK(4, 0)
> +
> +/* STM32F4_ADCX_SQR2 - bit fields */
> +#define STM32F4_SQ12_SHIFT 25
> +#define STM32F4_SQ12_MASK GENMASK(29, 25)
> +#define STM32F4_SQ11_SHIFT 20
> +#define STM32F4_SQ11_MASK GENMASK(24, 20)
> +#define STM32F4_SQ10_SHIFT 15
> +#define STM32F4_SQ10_MASK GENMASK(19, 15)
> +#define STM32F4_SQ9_SHIFT 10
> +#define STM32F4_SQ9_MASK GENMASK(14, 10)
> +#define STM32F4_SQ8_SHIFT 5
> +#define STM32F4_SQ8_MASK GENMASK(9, 5)
> +#define STM32F4_SQ7_SHIFT 0
> +#define STM32F4_SQ7_MASK GENMASK(4, 0)
> +
> +/* STM32F4_ADCX_SQR3 - bit fields */
> +#define STM32F4_SQ6_SHIFT 25
> +#define STM32F4_SQ6_MASK GENMASK(29, 25)
> +#define STM32F4_SQ5_SHIFT 20
> +#define STM32F4_SQ5_MASK GENMASK(24, 20)
> +#define STM32F4_SQ4_SHIFT 15
> +#define STM32F4_SQ4_MASK GENMASK(19, 15)
> +#define STM32F4_SQ3_SHIFT 10
> +#define STM32F4_SQ3_MASK GENMASK(14, 10)
> +#define STM32F4_SQ2_SHIFT 5
> +#define STM32F4_SQ2_MASK GENMASK(9, 5)
> +#define STM32F4_SQ1_SHIFT 0
> +#define STM32F4_SQ1_MASK GENMASK(4, 0)
> +
> +/* STM32F4_ADCX_JSQR - bit fields */
> +#define STM32F4_JL_SHIFT 20
> +#define STM32F4_JL_MASK GENMASK(21, 20)
> +#define STM32F4_JSQ4_SHIFT 15
> +#define STM32F4_JSQ4_MASK GENMASK(19, 15)
> +#define STM32F4_JSQ3_SHIFT 10
> +#define STM32F4_JSQ3_MASK GENMASK(14, 10)
> +#define STM32F4_JSQ2_SHIFT 5
> +#define STM32F4_JSQ2_MASK GENMASK(9, 5)
> +#define STM32F4_JSQ1_SHIFT 0
> +#define STM32F4_JSQ1_MASK GENMASK(4, 0)
> +
> +/* STM32F4_ADC_CCR - bit fields */
> +#define STM32F4_ADC_ADCPRE_SHIFT 16
> +#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
> +
> +/*
> + * stm32 ADC1, ADC2 & ADC3 are tightly coupled and may be used in multi mode
> + * Define here all inputs for all ADC instances
> + */
> +static const struct stm32_adc_chan_spec stm32f4_adc1_channels[] = {
> + /* master ADC1 */
> + { IIO_VOLTAGE, 0, "in0" },
> + { IIO_VOLTAGE, 1, "in1" },
> + { IIO_VOLTAGE, 2, "in2" },
> + { IIO_VOLTAGE, 3, "in3" },
> + { IIO_VOLTAGE, 4, "in4" },
> + { IIO_VOLTAGE, 5, "in5" },
> + { IIO_VOLTAGE, 6, "in6" },
> + { IIO_VOLTAGE, 7, "in7" },
> + { IIO_VOLTAGE, 8, "in8" },
> + { IIO_VOLTAGE, 9, "in9" },
> + { IIO_VOLTAGE, 10, "in10" },
> + { IIO_VOLTAGE, 11, "in11" },
> + { IIO_VOLTAGE, 12, "in12" },
> + { IIO_VOLTAGE, 13, "in13" },
> + { IIO_VOLTAGE, 14, "in14" },
> + { IIO_VOLTAGE, 15, "in15" },
> + /* internal analog sources available on input 16 to 18 */
> + { IIO_VOLTAGE, 16, "in16" },
> + { IIO_VOLTAGE, 17, "in17" },
> + { IIO_VOLTAGE, 18, "in18" },
> +};
> +
> +static const struct stm32_adc_chan_spec stm32f4_adc23_channels[] = {
> + /* slave ADC2 / ADC3 */
> + { IIO_VOLTAGE, 0, "in0" },
> + { IIO_VOLTAGE, 1, "in1" },
> + { IIO_VOLTAGE, 2, "in2" },
> + { IIO_VOLTAGE, 3, "in3" },
> + { IIO_VOLTAGE, 4, "in4" },
> + { IIO_VOLTAGE, 5, "in5" },
> + { IIO_VOLTAGE, 6, "in6" },
> + { IIO_VOLTAGE, 7, "in7" },
> + { IIO_VOLTAGE, 8, "in8" },
> + { IIO_VOLTAGE, 9, "in9" },
> + { IIO_VOLTAGE, 10, "in10" },
> + { IIO_VOLTAGE, 11, "in11" },
> + { IIO_VOLTAGE, 12, "in12" },
> + { IIO_VOLTAGE, 13, "in13" },
> + { IIO_VOLTAGE, 14, "in14" },
> + { IIO_VOLTAGE, 15, "in15" },
> +};
> +
> +/* Triggers for regular channels */
> +static const struct stm32_adc_trig_info stm32f4_adc_ext_triggers[] = {
> + { STM32_EXT0, "TIM1_CH1" },
> + { STM32_EXT1, "TIM1_CH2" },
> + { STM32_EXT2, "TIM1_CH3" },
> + { STM32_EXT3, "TIM2_CH2" },
> + { STM32_EXT4, "TIM2_CH3" },
> + { STM32_EXT5, "TIM2_CH4" },
> + { STM32_EXT6, "TIM2_TRGO" },
> + { STM32_EXT7, "TIM3_CH1" },
> + { STM32_EXT8, "TIM3_TRGO" },
> + { STM32_EXT9, "TIM4_CH4" },
> + { STM32_EXT10, "TIM5_CH1" },
> + { STM32_EXT11, "TIM5_CH2" },
> + { STM32_EXT12, "TIM5_CH3" },
> + { STM32_EXT13, "TIM8_CH1" },
> + { STM32_EXT14, "TIM8_TRGO" },
> + { STM32_EXT15, "EXTI_11" },
> + {},
> +};
> +
> +/* Triggers for injected channels */
> +static const struct stm32_adc_trig_info stm32f4_adc_jext_triggers[] = {
> + { STM32_JEXT0, "TIM1_CH4" },
> + { STM32_JEXT1, "TIM1_TRGO" },
> + { STM32_JEXT2, "TIM2_CH1" },
> + { STM32_JEXT3, "TIM2_TRGO" },
> + { STM32_JEXT4, "TIM3_CH2" },
> + { STM32_JEXT5, "TIM3_CH4" },
> + { STM32_JEXT6, "TIM4_CH1" },
> + { STM32_JEXT7, "TIM4_CH2" },
> + { STM32_JEXT8, "TIM4_CH3" },
> + { STM32_JEXT9, "TIM4_TRGO" },
> + { STM32_JEXT10, "TIM5_CH4" },
> + { STM32_JEXT11, "TIM5_TRGO" },
> + { STM32_JEXT12, "TIM8_CH2" },
> + { STM32_JEXT13, "TIM8_CH3" },
> + { STM32_JEXT14, "TIM8_CH4" },
> + { STM32_JEXT15, "EXTI_15" },
> + {},
> +};
> +
> +static const struct stm32_adc_info stm32f4_adc_info[] = {
> + {
> + .name = "adc1-master",
> + .reg = 0x0,
> + .channels = stm32f4_adc1_channels,
> + .max_channels = ARRAY_SIZE(stm32f4_adc1_channels),
> + },
> + {
> + .name = "adc2-slave",
> + .reg = 0x100,
> + .channels = stm32f4_adc23_channels,
> + .max_channels = ARRAY_SIZE(stm32f4_adc23_channels),
> + },
> + {
> + .name = "adc3-slave",
> + .reg = 0x200,
> + .channels = stm32f4_adc23_channels,
> + .max_channels = ARRAY_SIZE(stm32f4_adc23_channels),
> + },
> + {},
> +};
> +
> +/**
> + * stm32f4_sqr_regs - describe regular sequence registers
> + * - L: sequence len (register & bit field)
> + * - SQ1..SQ16: sequence entries (register & bit field)
> + */
> +static const struct stm32_adc_regs stm32f4_sqr_regs[STM32_ADC_MAX_SQ + 1] = {
> + /* L: len bit field description to be kept as first element */
> + { STM32F4_ADCX_SQR1, STM32F4_L_MASK, STM32F4_L_SHIFT },
> + /* SQ1..SQ16 registers & bit fields */
> + { STM32F4_ADCX_SQR3, STM32F4_SQ1_MASK, STM32F4_SQ1_SHIFT },
> + { STM32F4_ADCX_SQR3, STM32F4_SQ2_MASK, STM32F4_SQ2_SHIFT },
> + { STM32F4_ADCX_SQR3, STM32F4_SQ3_MASK, STM32F4_SQ3_SHIFT },
> + { STM32F4_ADCX_SQR3, STM32F4_SQ4_MASK, STM32F4_SQ4_SHIFT },
> + { STM32F4_ADCX_SQR3, STM32F4_SQ5_MASK, STM32F4_SQ5_SHIFT },
> + { STM32F4_ADCX_SQR3, STM32F4_SQ6_MASK, STM32F4_SQ6_SHIFT },
> + { STM32F4_ADCX_SQR2, STM32F4_SQ7_MASK, STM32F4_SQ7_SHIFT },
> + { STM32F4_ADCX_SQR2, STM32F4_SQ8_MASK, STM32F4_SQ8_SHIFT },
> + { STM32F4_ADCX_SQR2, STM32F4_SQ9_MASK, STM32F4_SQ9_SHIFT },
> + { STM32F4_ADCX_SQR2, STM32F4_SQ10_MASK, STM32F4_SQ10_SHIFT },
> + { STM32F4_ADCX_SQR2, STM32F4_SQ11_MASK, STM32F4_SQ11_SHIFT },
> + { STM32F4_ADCX_SQR2, STM32F4_SQ12_MASK, STM32F4_SQ12_SHIFT },
> + { STM32F4_ADCX_SQR1, STM32F4_SQ13_MASK, STM32F4_SQ13_SHIFT },
> + { STM32F4_ADCX_SQR1, STM32F4_SQ14_MASK, STM32F4_SQ14_SHIFT },
> + { STM32F4_ADCX_SQR1, STM32F4_SQ15_MASK, STM32F4_SQ15_SHIFT },
> + { STM32F4_ADCX_SQR1, STM32F4_SQ16_MASK, STM32F4_SQ16_SHIFT },
> +};
> +
> +/**
> + * stm32f4_jsqr_reg - describe injected sequence register:
> + * - JL: injected sequence len
> + * - JSQ4..SQ1: sequence entries
> + * When JL == 3, ADC converts JSQ1, JSQ2, JSQ3, JSQ4
> + * When JL == 2, ADC converts JSQ2, JSQ3, JSQ4
> + * When JL == 1, ADC converts JSQ3, JSQ4
> + * When JL == 0, ADC converts JSQ4
> + */
> +static const struct stm32_adc_regs stm32f4_jsqr_reg[STM32_ADC_MAX_JSQ + 1] = {
> + /* JL: len bit field description to be kept as first element */
> + {STM32F4_ADCX_JSQR, STM32F4_JL_MASK, STM32F4_JL_SHIFT},
> + /* JSQ4..JSQ1 registers & bit fields */
> + {STM32F4_ADCX_JSQR, STM32F4_JSQ4_MASK, STM32F4_JSQ4_SHIFT},
> + {STM32F4_ADCX_JSQR, STM32F4_JSQ3_MASK, STM32F4_JSQ3_SHIFT},
> + {STM32F4_ADCX_JSQR, STM32F4_JSQ2_MASK, STM32F4_JSQ2_SHIFT},
> + {STM32F4_ADCX_JSQR, STM32F4_JSQ1_MASK, STM32F4_JSQ1_SHIFT},
> +};
> +
> +static const struct stm32_adc_trig_reginfo stm32f4_adc_trig_reginfo = {
> + .reg = STM32F4_ADCX_CR2,
> + .exten_mask = STM32F4_EXTEN_MASK,
> + .exten_shift = STM32F4_EXTEN_SHIFT,
> + .extsel_mask = STM32F4_EXTSEL_MASK,
> + .extsel_shift = STM32F4_EXTSEL_SHIFT,
> +};
> +
> +static const struct stm32_adc_trig_reginfo stm32f4_adc_jtrig_reginfo = {
> + .reg = STM32F4_ADCX_CR2,
> + .exten_mask = STM32F4_JEXTEN_MASK,
> + .exten_shift = STM32F4_JEXTEN_SHIFT,
> + .extsel_mask = STM32F4_JEXTSEL_MASK,
> + .extsel_shift = STM32F4_JEXTSEL_SHIFT,
> +};
> +
> +static const struct stm32_adc_reginfo stm32f4_adc_reginfo = {
> + .isr = STM32F4_ADCX_SR,
> + .eoc = STM32F4_EOC,
> + .jeoc = STM32F4_JEOC,
> + .ier = STM32F4_ADCX_CR1,
> + .eocie = STM32F4_EOCIE,
> + .jeocie = STM32F4_JEOCIE,
> + .dr = STM32F4_ADCX_DR,
> + .jdr = {
> + STM32F4_ADCX_JDR1,
> + STM32F4_ADCX_JDR2,
> + STM32F4_ADCX_JDR3,
> + STM32F4_ADCX_JDR4,
> + },
> + .sqr_regs = stm32f4_sqr_regs,
> + .jsqr_reg = stm32f4_jsqr_reg,
> + .trig_reginfo = &stm32f4_adc_trig_reginfo,
> + .jtrig_reginfo = &stm32f4_adc_jtrig_reginfo,
> +};
> +
> +static bool stm32f4_adc_is_started(struct stm32_adc *adc)
> +{
> + u32 val = stm32_adc_readl(adc, STM32F4_ADCX_CR2) & STM32F4_ADON;
> +
> + return !!val;
> +}
> +
> +static bool stm32f4_adc_regular_started(struct stm32_adc *adc)
> +{
> + u32 val = stm32_adc_readl(adc, STM32F4_ADCX_SR) & STM32F4_STRT;
> +
> + return !!val;
> +}
> +
> +static bool stm32f4_adc_injected_started(struct stm32_adc *adc)
> +{
> + u32 val = stm32_adc_readl(adc, STM32F4_ADCX_SR) & STM32F4_JSTRT;
> +
> + return !!val;
> +}
> +
> +/**
> + * stm32f4_adc_start_conv() - Start regular or injected conversions
> + * @adc: stm32 adc instance
> + *
> + * Start single conversions for regular or injected channels.
> + */
> +static int stm32f4_adc_start_conv(struct stm32_adc *adc)
> +{
> + u32 trig_msk, start_msk;
> +
> + dev_dbg(adc->common->dev, "%s %s\n", __func__,
> + adc->injected ? "injected" : "regular");
> +
> + stm32_adc_set_bits(adc, STM32F4_ADCX_CR1, STM32F4_SCAN);
> +
> + if (!stm32f4_adc_is_started(adc)) {
> + stm32_adc_set_bits(adc, STM32F4_ADCX_CR2,
> + STM32F4_EOCS | STM32F4_ADON);
> +
> + /* Wait for Power-up time (tSTAB from datasheet) */
> + usleep_range(2, 3);
> + }
> +
> + if (adc->injected) {
> + trig_msk = STM32F4_JEXTEN_MASK;
> + start_msk = STM32F4_JSWSTART;
> + } else {
> + trig_msk = STM32F4_EXTEN_MASK;
> + start_msk = STM32F4_SWSTART;
> + }
> +
> + /* Software start ? (e.g. trigger detection disabled ?) */
> + if (!(stm32_adc_readl(adc, STM32F4_ADCX_CR2) & trig_msk))
> + stm32_adc_set_bits(adc, STM32F4_ADCX_CR2, start_msk);
> +
> + return 0;
> +}
> +
> +static int stm32f4_adc_stop_conv(struct stm32_adc *adc)
> +{
> + u32 val;
> +
> + dev_dbg(adc->common->dev, "%s %s\n", __func__,
> + adc->injected ? "injected" : "regular");
> +
> + /* First disable trigger for either regular or injected channels */
> + if (adc->injected) {
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_JEXTEN_MASK);
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_SR, STM32F4_JSTRT);
> + } else {
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_EXTEN_MASK);
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_SR, STM32F4_STRT);
> + }
> +
> + /* Disable adc when all triggered conversion have been disabled */
> + val = stm32_adc_readl(adc, STM32F4_ADCX_CR2);
> + val &= STM32F4_EXTEN_MASK | STM32F4_JEXTEN_MASK;
> + if (!val) {
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR1, STM32F4_SCAN);
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_ADON);
> + }
> +
> + return 0;
> +}
> +
> +/* ADC internal common clock prescaler division ratios */
> +static int stm32f4_pclk_div[] = {2, 4, 6, 8};
> +
> +/**
> + * stm32f4_adc_clk_sel() - Select ADC common clock prescaler
> + * @adc: stm32 adc instance
> + * Select clock prescaler used for analog conversions.
> + */
> +static int stm32f4_adc_clk_sel(struct stm32_adc *adc)
> +{
> + struct stm32_adc_common *common = adc->common;
> + unsigned long rate;
> + u32 val;
> + int i;
> +
> + /* Common prescaler is set only once, when 1st ADC instance starts */
> + list_for_each_entry(adc, &common->adc_list, adc_list)
> + if (stm32f4_adc_is_started(adc))
> + return 0;
> +
> + rate = clk_get_rate(common->aclk);
> + for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
> + if ((rate / stm32f4_pclk_div[i]) <=
> + common->data->max_clock_rate)
> + break;
> + }
> + if (i >= ARRAY_SIZE(stm32f4_pclk_div))
> + return -EINVAL;
> +
> + val = stm32_adc_common_readl(common, STM32F4_ADC_CCR);
> + val &= ~STM32F4_ADC_ADCPRE_MASK;
> + val |= i << STM32F4_ADC_ADCPRE_SHIFT;
> + stm32_adc_common_writel(common, STM32F4_ADC_CCR, val);
> +
> + dev_dbg(common->dev, "Using analog clock source at %ld kHz\n",
> + rate / (stm32f4_pclk_div[i] * 1000));
> +
> + return 0;
> +}
> +
> +static const struct stm32_adc_ops stm32f4_adc_ops = {
> + .adc_info = stm32f4_adc_info,
> + .ext_triggers = stm32f4_adc_ext_triggers,
> + .jext_triggers = stm32f4_adc_jext_triggers,
> + .adc_reginfo = &stm32f4_adc_reginfo,
> + .highres = 12,
> + .max_clock_rate = 36000000,
> + .clk_sel = stm32f4_adc_clk_sel,
> + .start_conv = stm32f4_adc_start_conv,
> + .stop_conv = stm32f4_adc_stop_conv,
> + .is_started = stm32f4_adc_is_started,
> + .regular_started = stm32f4_adc_regular_started,
> + .injected_started = stm32f4_adc_injected_started,
> +};
> +
> +static const struct of_device_id stm32f4_adc_of_match[] = {
> + { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_ops},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, stm32f4_adc_of_match);
> +
> +static struct platform_driver stm32f4_adc_driver = {
> + .probe = stm32_adc_probe,
> + .remove = stm32_adc_remove,
> + .driver = {
> + .name = "stm32f4-adc",
> + .of_match_table = stm32f4_adc_of_match,
> + },
> +};
> +
> +module_platform_driver(stm32f4_adc_driver);
> +
> +MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32F4 ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply
* [PATCH 03/10] iio: adc: stm32: add optional dma support
From: Jonathan Cameron @ 2016-10-30 15:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477412722-24061-4-git-send-email-fabrice.gasnier@st.com>
On 25/10/16 17:25, Fabrice Gasnier wrote:
> Add optional DMA support to STM32 ADC.
> Use dma cyclic mode with at least two periods.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Few little bits inline, but looks superficially good (my dma knowledge isn't
really up to reviewing this.) Lars can you take a look (perhaps at the next
version)?
Also, you 'could' potentially use the dma buffer stuff to give a lower overhead
route for the data to userspace if the device goes quick enough to warrant
it.
Jonathan
> ---
> drivers/iio/adc/stm32/Kconfig | 2 +
> drivers/iio/adc/stm32/stm32-adc.c | 222 ++++++++++++++++++++++++++++++++----
> drivers/iio/adc/stm32/stm32-adc.h | 15 +++
> drivers/iio/adc/stm32/stm32f4-adc.c | 20 +++-
> 4 files changed, 235 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/iio/adc/stm32/Kconfig b/drivers/iio/adc/stm32/Kconfig
> index 245d037..5554ac8 100644
> --- a/drivers/iio/adc/stm32/Kconfig
> +++ b/drivers/iio/adc/stm32/Kconfig
> @@ -8,6 +8,7 @@ config STM32_ADC
> select REGULATOR_FIXED_VOLTAGE
> select IIO_BUFFER
> select IIO_TRIGGERED_BUFFER
> + select IRQ_WORK
> help
> Say yes here to build the driver for the STMicroelectronics
> STM32 analog-to-digital converter (ADC).
> @@ -18,6 +19,7 @@ config STM32_ADC
> config STM32F4_ADC
> tristate "STMicroelectronics STM32F4 adc"
> depends on ARCH_STM32 || COMPILE_TEST
> + depends on HAS_DMA
> depends on OF
> select STM32_ADC
> help
> diff --git a/drivers/iio/adc/stm32/stm32-adc.c b/drivers/iio/adc/stm32/stm32-adc.c
> index 1e0850d..25d0307 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.c
> +++ b/drivers/iio/adc/stm32/stm32-adc.c
> @@ -21,6 +21,7 @@
>
> #include <linux/clk.h>
> #include <linux/debugfs.h>
> +#include <linux/dma-mapping.h>
> #include <linux/iio/iio.h>
> #include <linux/iio/buffer.h>
> #include <linux/iio/events.h>
> @@ -371,6 +372,34 @@ static int stm32_adc_read_raw(struct iio_dev *indio_dev,
> return ret;
> }
>
> +static int stm32_adc_residue(struct stm32_adc *adc)
> +{
> + struct dma_tx_state state;
> + enum dma_status status;
> +
> + if (!adc->rx_buf)
> + return 0;
> +
> + status = dmaengine_tx_status(adc->dma_chan,
> + adc->dma_chan->cookie,
> + &state);
> + if (status == DMA_IN_PROGRESS) {
> + /* Residue is size in bytes from end of buffer */
> + int i = adc->rx_buf_sz - state.residue;
> + int size;
> +
> + /* Return available bytes */
> + if (i >= adc->bufi)
> + size = i - adc->bufi;
> + else
> + size = adc->rx_buf_sz - adc->bufi + i;
> +
> + return size;
> + }
> +
> + return 0;
> +}
> +
> /**
> * stm32_adc_isr() - Treat interrupt for one ADC instance within ADC block
> */
> @@ -394,8 +423,8 @@ static irqreturn_t stm32_adc_isr(struct stm32_adc *adc)
> stm32_adc_writel(adc, reginfo->isr, status & ~clr_mask);
> status &= mask;
>
> - /* Regular data */
> - if (status & reginfo->eoc) {
> + /* Regular data (when dma isn't used) */
> + if ((status & reginfo->eoc) && (!adc->rx_buf)) {
> adc->buffer[adc->bufi] = stm32_adc_readl(adc, reginfo->dr);
> if (iio_buffer_enabled(indio_dev)) {
> adc->bufi++;
> @@ -553,29 +582,154 @@ static int stm32_adc_validate_device(struct iio_trigger *trig,
> return indio != indio_dev ? -EINVAL : 0;
> }
>
> -static int stm32_adc_set_trigger_state(struct iio_trigger *trig,
> - bool state)
> +static void stm32_adc_dma_irq_work(struct irq_work *work)
> {
> - struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
> + struct stm32_adc *adc = container_of(work, struct stm32_adc, work);
> + struct iio_dev *indio_dev = iio_priv_to_dev(adc);
> +
> + /**
> + * iio_trigger_poll calls generic_handle_irq(). So, it requires hard
> + * irq context, and cannot be called directly from dma callback,
> + * dma cb has to schedule this work instead.
> + */
> + iio_trigger_poll(indio_dev->trig);
> +}
> +
> +static void stm32_adc_dma_buffer_done(void *data)
> +{
> + struct iio_dev *indio_dev = data;
> struct stm32_adc *adc = iio_priv(indio_dev);
> - int ret;
>
> - if (state) {
> - /* Reset adc buffer index */
> - adc->bufi = 0;
> + /* invoques iio_trigger_poll() from hard irq context */
invokes.
> + irq_work_queue(&adc->work);
> +}
> +
> +static int stm32_adc_buffer_alloc_dma_start(struct iio_dev *indio_dev)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + const struct stm32_adc_reginfo *reginfo =
> + adc->common->data->adc_reginfo;
> + struct dma_async_tx_descriptor *desc;
> + struct dma_slave_config config;
> + dma_cookie_t cookie;
> + int ret, size, watermark;
>
> + /* Reset adc buffer index */
> + adc->bufi = 0;
> +
> + if (!adc->dma_chan) {
> /* Allocate adc buffer */
> adc->buffer = kzalloc(indio_dev->scan_bytes, GFP_KERNEL);
> if (!adc->buffer)
> return -ENOMEM;
>
> + return 0;
> + }
> +
> + /*
> + * Allocate at least twice the buffer size for dma cyclic transfers, so
> + * we can work with at least two dma periods. There should be :
> + * - always one buffer (period) dma is working on
> + * - one buffer (period) driver can push with iio_trigger_poll().
> + */
> + size = indio_dev->buffer->bytes_per_datum * indio_dev->buffer->length;
> + size = max(indio_dev->scan_bytes * 2, size);
> +
> + adc->rx_buf = dma_alloc_coherent(adc->common->dev, PAGE_ALIGN(size),
> + &adc->rx_dma_buf,
> + GFP_KERNEL);
> + if (!adc->rx_buf)
> + return -ENOMEM;
> + adc->rx_buf_sz = size;
> + watermark = indio_dev->buffer->bytes_per_datum
> + * indio_dev->buffer->watermark;
> + watermark = max(indio_dev->scan_bytes, watermark);
> + watermark = rounddown(watermark, indio_dev->scan_bytes);
> +
> + dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, size,
> + watermark);
> +
> + /* Configure DMA channel to read data register */
> + memset(&config, 0, sizeof(config));
> + config.src_addr = (dma_addr_t)adc->common->phys_base;
> + config.src_addr += adc->offset + reginfo->dr;
> + config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> +
> + ret = dmaengine_slave_config(adc->dma_chan, &config);
> + if (ret)
> + goto config_err;
> +
> + /* Prepare a DMA cyclic transaction */
> + desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
> + adc->rx_dma_buf,
> + size, watermark,
> + DMA_DEV_TO_MEM,
> + DMA_PREP_INTERRUPT);
> + if (!desc) {
> + ret = -ENODEV;
> + goto config_err;
> + }
> +
> + desc->callback = stm32_adc_dma_buffer_done;
> + desc->callback_param = indio_dev;
> +
> + cookie = dmaengine_submit(desc);
> + if (dma_submit_error(cookie)) {
> + ret = dma_submit_error(cookie);
> + goto config_err;
> + }
> +
> + /* Issue pending DMA requests */
> + dma_async_issue_pending(adc->dma_chan);
> +
> + return 0;
> +
> +config_err:
> + dma_free_coherent(adc->common->dev, PAGE_ALIGN(size), adc->rx_buf,
> + adc->rx_dma_buf);
> +
> + return ret;
> +}
> +
> +static void stm32_adc_dma_stop_buffer_free(struct iio_dev *indio_dev)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + if (!adc->dma_chan) {
> + kfree(adc->buffer);
> + } else {
> + dmaengine_terminate_all(adc->dma_chan);
> + irq_work_sync(&adc->work);
> + dma_free_coherent(adc->common->dev, PAGE_ALIGN(adc->rx_buf_sz),
> + adc->rx_buf, adc->rx_dma_buf);
> + adc->rx_buf = NULL;
> + }
> +
> + adc->buffer = NULL;
> +}
> +
> +static int stm32_adc_set_trigger_state(struct iio_trigger *trig,
> + bool state)
> +{
> + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + int ret;
> +
> + if (state) {
> + ret = stm32_adc_buffer_alloc_dma_start(indio_dev);
> + if (ret) {
> + dev_err(&indio_dev->dev, "alloc failed\n");
> + return ret;
> + }
> +
> ret = stm32_adc_set_trig(indio_dev, trig);
> if (ret) {
> dev_err(&indio_dev->dev, "Can't set trigger\n");
> goto err_buffer_free;
> }
>
> - stm32_adc_conv_irq_enable(adc);
> + if (!adc->dma_chan)
> + stm32_adc_conv_irq_enable(adc);
>
> ret = stm32_adc_start_conv(adc);
> if (ret) {
> @@ -589,25 +743,25 @@ static int stm32_adc_set_trigger_state(struct iio_trigger *trig,
> return ret;
> }
>
> - stm32_adc_conv_irq_disable(adc);
> + if (!adc->dma_chan)
> + stm32_adc_conv_irq_disable(adc);
>
> ret = stm32_adc_set_trig(indio_dev, NULL);
> if (ret)
> dev_warn(&indio_dev->dev, "Can't clear trigger\n");
>
> - kfree(adc->buffer);
> - adc->buffer = NULL;
> + stm32_adc_dma_stop_buffer_free(indio_dev);
> }
>
> return 0;
>
> err_irq_trig_disable:
> - stm32_adc_conv_irq_disable(adc);
> + if (!adc->dma_chan)
> + stm32_adc_conv_irq_disable(adc);
> stm32_adc_set_trig(indio_dev, NULL);
>
> err_buffer_free:
> - kfree(adc->buffer);
> - adc->buffer = NULL;
> + stm32_adc_dma_stop_buffer_free(indio_dev);
>
> return ret;
> }
> @@ -624,17 +778,30 @@ static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
> struct iio_dev *indio_dev = pf->indio_dev;
> struct stm32_adc *adc = iio_priv(indio_dev);
>
> - dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
> -
> - /* reset buffer index */
> - adc->bufi = 0;
> - iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
> - pf->timestamp);
> + if (!adc->dma_chan) {
> + adc->bufi = 0;
> + iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
> + pf->timestamp);
> + } else {
> + int residue = stm32_adc_residue(adc);
> +
This bit wants some explanatory comments I think.
> + while (residue >= indio_dev->scan_bytes) {
> + adc->buffer = (u16 *)&adc->rx_buf[adc->bufi];
> + iio_push_to_buffers_with_timestamp(indio_dev,
> + adc->buffer,
> + pf->timestamp);
> + residue -= indio_dev->scan_bytes;
> + adc->bufi += indio_dev->scan_bytes;
> + if (adc->bufi >= adc->rx_buf_sz)
> + adc->bufi = 0;
> + }
> + }
>
> iio_trigger_notify_done(indio_dev->trig);
>
> /* re-enable eoc irq */
> - stm32_adc_conv_irq_enable(adc);
> + if (!adc->dma_chan)
> + stm32_adc_conv_irq_enable(adc);
>
> return IRQ_HANDLED;
> }
> @@ -827,6 +994,10 @@ static int stm32_adc_register(struct stm32_adc_common *common,
> if (ret)
> goto err_clk_disable;
>
> + adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
> + if (adc->dma_chan)
> + init_irq_work(&adc->work, stm32_adc_dma_irq_work);
> +
> ret = iio_triggered_buffer_setup(indio_dev,
> &iio_pollfunc_store_time,
> &stm32_adc_trigger_handler,
> @@ -850,6 +1021,8 @@ static int stm32_adc_register(struct stm32_adc_common *common,
> iio_triggered_buffer_cleanup(indio_dev);
>
> err_trig_unregister:
> + if (adc->dma_chan)
> + dma_release_channel(adc->dma_chan);
> stm32_adc_trig_unregister(indio_dev);
>
> err_clk_disable:
> @@ -870,6 +1043,8 @@ static void stm32_adc_unregister(struct stm32_adc *adc)
> iio_device_unregister(indio_dev);
> iio_triggered_buffer_cleanup(indio_dev);
> stm32_adc_trig_unregister(indio_dev);
> + if (adc->dma_chan)
> + dma_release_channel(adc->dma_chan);
> if (adc->clk) {
> clk_disable_unprepare(adc->clk);
> clk_put(adc->clk);
> @@ -900,6 +1075,7 @@ int stm32_adc_probe(struct platform_device *pdev)
> common->base = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(common->base))
> return PTR_ERR(common->base);
> + common->phys_base = res->start;
>
> common->data = match->data;
> common->dev = &pdev->dev;
> diff --git a/drivers/iio/adc/stm32/stm32-adc.h b/drivers/iio/adc/stm32/stm32-adc.h
> index 0be603c..01a0dda 100644
> --- a/drivers/iio/adc/stm32/stm32-adc.h
> +++ b/drivers/iio/adc/stm32/stm32-adc.h
> @@ -22,6 +22,9 @@
> #ifndef __STM32_ADC_H
> #define __STM32_ADC_H
>
> +#include <linux/dmaengine.h>
> +#include <linux/irq_work.h>
> +
> /*
> * STM32 - ADC global register map
> * ________________________________________________________
> @@ -276,6 +279,11 @@ struct stm32_adc_ops {
> * @num_conv: expected number of scan conversions
> * @injected: use injected channels on this adc
> * @lock: spinlock
> + * @work: irq work used to call trigger poll routine
> + * @dma_chan: dma channel
> + * @rx_buf: dma rx buffer cpu address
> + * @rx_dma_buf: dma rx buffer bus address
> + * @rx_buf_sz: dma rx buffer size
> * @clk: optional adc clock, for this adc instance
> * @calib: optional calibration data
> * @en: emulates enabled state on some stm32 adc
> @@ -293,6 +301,11 @@ struct stm32_adc {
> int num_conv;
> bool injected;
> spinlock_t lock; /* interrupt lock */
> + struct irq_work work;
> + struct dma_chan *dma_chan;
> + u8 *rx_buf;
> + dma_addr_t rx_dma_buf;
> + int rx_buf_sz;
> struct clk *clk;
> void *calib;
> bool en;
> @@ -302,6 +315,7 @@ struct stm32_adc {
> * struct stm32_adc_common - private data of ADC driver, common to all
> * ADC instances (ADC block)
> * @dev: device for this controller
> + * @phys_base: control registers base physical addr
> * @base: control registers base cpu addr
> * @irq: Common irq line for all adc instances
> * @data: STM32 dependent data from compatible
> @@ -313,6 +327,7 @@ struct stm32_adc {
> */
> struct stm32_adc_common {
> struct device *dev;
> + phys_addr_t phys_base;
> void __iomem *base;
> int irq;
> const struct stm32_adc_ops *data;
> diff --git a/drivers/iio/adc/stm32/stm32f4-adc.c b/drivers/iio/adc/stm32/stm32f4-adc.c
> index 147fe9c..4d7a2a8 100644
> --- a/drivers/iio/adc/stm32/stm32f4-adc.c
> +++ b/drivers/iio/adc/stm32/stm32f4-adc.c
> @@ -437,16 +437,30 @@ static bool stm32f4_adc_injected_started(struct stm32_adc *adc)
> * @adc: stm32 adc instance
> *
> * Start single conversions for regular or injected channels.
> + * Also take care of normal or DMA mode. DMA is used in circular mode for
> + * regular conversions, in IIO buffer modes. Rely on rx_buf as raw
> + * read doesn't use dma, but direct DR read.
> */
> static int stm32f4_adc_start_conv(struct stm32_adc *adc)
> {
> - u32 trig_msk, start_msk;
> + u32 val, trig_msk, start_msk;
> + unsigned long flags;
>
> dev_dbg(adc->common->dev, "%s %s\n", __func__,
> adc->injected ? "injected" : "regular");
>
> stm32_adc_set_bits(adc, STM32F4_ADCX_CR1, STM32F4_SCAN);
>
> + if (!adc->injected) {
> + spin_lock_irqsave(&adc->lock, flags);
> + val = stm32_adc_readl(adc, STM32F4_ADCX_CR2);
> + val &= ~(STM32F4_DMA | STM32F4_DDS);
> + if (adc->rx_buf)
> + val |= STM32F4_DMA | STM32F4_DDS;
> + stm32_adc_writel(adc, STM32F4_ADCX_CR2, val);
> + spin_unlock_irqrestore(&adc->lock, flags);
> + }
> +
> if (!stm32f4_adc_is_started(adc)) {
> stm32_adc_set_bits(adc, STM32F4_ADCX_CR2,
> STM32F4_EOCS | STM32F4_ADON);
> @@ -494,6 +508,10 @@ static int stm32f4_adc_stop_conv(struct stm32_adc *adc)
> stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_ADON);
> }
>
> + if (!adc->injected)
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2,
> + STM32F4_DMA | STM32F4_DDS);
> +
> return 0;
> }
>
>
^ permalink raw reply
* [PATCH 2/2] ARM: dts: bcm283x: fix typo in mailbox address
From: Andreas Färber @ 2016-10-30 15:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477505640-26658-2-git-send-email-stefan.wahren@i2se.com>
Hi,
Am 26.10.2016 um 20:14 schrieb Stefan Wahren:
> The address of the mailbox node in the bcm283x.dts has also a typo.
.dts -> .dtsi
"also has" or maybe "has the same typo as in the binding example"?
> So fix it accordingly.
>
> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
> Fixes: 05b682b7a3b2 ("ARM: bcm2835: dt: Add the mailbox to the device tree")
> ---
> arch/arm/boot/dts/bcm283x.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
> index 46d46d8..74dd21b 100644
> --- a/arch/arm/boot/dts/bcm283x.dtsi
> +++ b/arch/arm/boot/dts/bcm283x.dtsi
> @@ -104,7 +104,7 @@
> reg = <0x7e104000 0x10>;
> };
>
> - mailbox: mailbox at 7e00b800 {
> + mailbox: mailbox at 7e00b880 {
> compatible = "brcm,bcm2835-mbox";
> reg = <0x7e00b880 0x40>;
> interrupts = <0 1>;
Otherwise,
Reviewed-by: Andreas F?rber <afaerber@suse.de>
At one point in time dtc did complain about such mismatches...
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [PATCH v6 2/2] iio: adc: add support for Allwinner SoCs ADC
From: Jonathan Cameron @ 2016-10-30 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473943444-23979-3-git-send-email-quentin.schulz@free-electrons.com>
On 15/09/16 13:44, Quentin Schulz wrote:
> The Allwinner SoCs all have an ADC that can also act as a touchscreen
> controller and a thermal sensor. This patch adds the ADC driver which is
> based on the MFD for the same SoCs ADC.
>
> This also registers the thermal adc channel in the iio map array so
> iio_hwmon could use it without modifying the Device Tree. This registers
> the driver in the thermal framework.
>
> This driver probes on three different platform_device_id to take into
> account slight differences (registers bit and temperature computation)
> between Allwinner SoCs ADCs.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Acked-by: Jonathan Cameron <jic23@kernel.org>
Hi Lee,
As you applied the MFD part of this series, could you pick this up as well?
Thanks,
Jonathan
> ---
>
> v6:
> - remove useless member (regs) from sun4i_gpadc_dev structure,
> - rename sun4i_gpadc_dev structure to sun4i_gpadc_iio,
> - remove regmap_update_bits used to disable hardware interrupts, it is already
> handled by devm functions,
>
> v5:
> - correct mail address,
> - correct several typos,
> - move from const to static for sunxi_gpadc_chan_select functions,
> - rename soc_specific struct to gpadc_data,
> - rename soc_specific field to data in sun4i_gpadc_dev,
> - return error code from regmap_write in case of failure in read_raws,
> - share if condition in IIO_CHAN_INFO_RAW case,
> - add comment on why we use parent device for registering in thermal,
> - reordering remove function,
>
> v4:
> - rename files and variables from sunxi* to sun4i*,
> - shorten sunxi_gpadc_soc_specific structure to soc_specific,
> - factorize sysfs ADC and temp read_raws,
> - use cached values when read_raw times out (except before a first value
> is gotten),
> - remove mutex locks and unlocks from runtime_pm functions,
> - factorize irq initializations,
> - initialize temp_data and fifo_data values to -1 (error value),
> - "impersonate" MFD to register in thermal framework,
> - deactivate hardware interrupts one by one when probe fails or when
> removing driver instead of blindly deactivating all hardware interrupts,
> - selects THERMAL_OF in Kconfig,
>
> v3:
> - correct wrapping,
> - add comment about thermal sensor inner working,
> - move defines in mfd header,
> - use structure to define SoC specific registers or behaviour,
> - attach this structure to the device according to of_device_id of the
> platform device,
> - use new mutex instead of iio_dev mutex,
> - use atomic flags to avoid race between request_irq and disable_irq in
> probe,
> - switch from processed value to raw, offset and scale values for
> temperature ADC channel,
> - remove faulty sentinel in iio_chan_spec array,
> - add pm_runtime support,
> - register thermal sensor in thermal framework (forgotten since the
> beginning whereas it is present in current sun4i-ts driver),
> - remove useless ret variables to store return value of regmap_reads,
> - move comments on thermal sensor acquisition period in code instead of
> header,
> - adding goto label to unregister iio_map_array when failing to register
> iio_dev,
>
> v2:
> - add SUNXI_GPADC_ prefixes for defines,
> - correct typo in Kconfig,
> - reorder alphabetically includes, makefile,
> - add license header,
> - fix architecture variations not being handled in interrupt handlers or
> read raw functions,
> - fix unability to return negative values from thermal sensor,
> - add gotos to reduce code repetition,
> - fix irq variable being unsigned int instead of int,
> - remove useless dev_err and dev_info,
> - deactivate all interrupts if probe fails,
> - fix iio_device_register on NULL variable,
> - deactivate ADC in the IP when probe fails or when removing driver,
>
> drivers/iio/adc/Kconfig | 13 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/sun4i-gpadc-iio.c | 522 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 536 insertions(+)
> create mode 100644 drivers/iio/adc/sun4i-gpadc-iio.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 25378c5..ea36a4f 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -384,6 +384,19 @@ config ROCKCHIP_SARADC
> To compile this driver as a module, choose M here: the
> module will be called rockchip_saradc.
>
> +config SUN4I_GPADC
> + tristate "Support for the Allwinner SoCs GPADC"
> + depends on IIO
> + depends on MFD_SUN4I_GPADC
> + select THERMAL_OF
> + help
> + Say yes here to build support for Allwinner (A10, A13 and A31) SoCs
> + GPADC. This ADC provides 4 channels which can be used as an ADC or as
> + a touchscreen input and one channel for thermal sensor.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called sun4i-gpadc-iio.
> +
> config TI_ADC081C
> tristate "Texas Instruments ADC081C/ADC101C/ADC121C family"
> depends on I2C
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index 38638d4..204372d 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
> obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
> obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
> +obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o
> obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
> obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
> obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
> new file mode 100644
> index 0000000..e2c5ba8
> --- /dev/null
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -0,0 +1,522 @@
> +/* ADC driver for sunxi platforms' (A10, A13 and A31) GPADC
> + *
> + * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + *
> + * The Allwinner SoCs all have an ADC that can also act as a touchscreen
> + * controller and a thermal sensor.
> + * The thermal sensor works only when the ADC acts as a touchscreen controller
> + * and is configured to throw an interrupt every fixed periods of time (let say
> + * every X seconds).
> + * One would be tempted to disable the IP on the hardware side rather than
> + * disabling interrupts to save some power but that resets the internal clock of
> + * the IP, resulting in having to wait X seconds every time we want to read the
> + * value of the thermal sensor.
> + * This is also the reason of using autosuspend in pm_runtime. If there was no
> + * autosuspend, the thermal sensor would need X seconds after every
> + * pm_runtime_get_sync to get a value from the ADC. The autosuspend allows the
> + * thermal sensor to be requested again in a certain time span before it gets
> + * shutdown for not being used.
> + */
> +
> +#include <linux/completion.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/thermal.h>
> +
> +#include <linux/iio/iio.h>
> +#include <linux/iio/driver.h>
> +#include <linux/iio/machine.h>
> +#include <linux/mfd/sun4i-gpadc.h>
> +
> +static unsigned int sun4i_gpadc_chan_select(unsigned int chan)
> +{
> + return SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
> +}
> +
> +static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
> +{
> + return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
> +}
> +
> +struct gpadc_data {
> + int temp_offset;
> + int temp_scale;
> + unsigned int tp_mode_en;
> + unsigned int tp_adc_select;
> + unsigned int (*adc_chan_select)(unsigned int chan);
> +};
> +
> +static const struct gpadc_data sun4i_gpadc_data = {
> + .temp_offset = -1932,
> + .temp_scale = 133,
> + .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
> + .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> + .adc_chan_select = &sun4i_gpadc_chan_select,
> +};
> +
> +static const struct gpadc_data sun5i_gpadc_data = {
> + .temp_offset = -1447,
> + .temp_scale = 100,
> + .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
> + .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> + .adc_chan_select = &sun4i_gpadc_chan_select,
> +};
> +
> +static const struct gpadc_data sun6i_gpadc_data = {
> + .temp_offset = -1623,
> + .temp_scale = 167,
> + .tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
> + .tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
> + .adc_chan_select = &sun6i_gpadc_chan_select,
> +};
> +
> +struct sun4i_gpadc_iio {
> + struct iio_dev *indio_dev;
> + struct completion completion;
> + int temp_data;
> + u32 adc_data;
> + struct regmap *regmap;
> + unsigned int fifo_data_irq;
> + atomic_t ignore_fifo_data_irq;
> + unsigned int temp_data_irq;
> + atomic_t ignore_temp_data_irq;
> + const struct gpadc_data *data;
> + /* prevents concurrent reads of temperature and ADC */
> + struct mutex mutex;
> +};
> +
> +#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = _channel, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
> + .datasheet_name = _name, \
> +}
> +
> +static struct iio_map sun4i_gpadc_hwmon_maps[] = {
> + {
> + .adc_channel_label = "temp_adc",
> + .consumer_dev_name = "iio_hwmon.0",
> + },
> + { /* sentinel */ },
> +};
> +
> +static const struct iio_chan_spec sun4i_gpadc_channels[] = {
> + SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
> + SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
> + SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
> + SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
> + {
> + .type = IIO_TEMP,
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
> + BIT(IIO_CHAN_INFO_SCALE) |
> + BIT(IIO_CHAN_INFO_OFFSET),
> + .datasheet_name = "temp_adc",
> + },
> +};
> +
> +static int sun4i_gpadc_read(struct iio_dev *indio_dev, int channel, int *val,
> + unsigned int irq)
> +{
> + struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
> + int ret = 0;
> +
> + pm_runtime_get_sync(indio_dev->dev.parent);
> + mutex_lock(&info->mutex);
> +
> + reinit_completion(&info->completion);
> +
> + ret = regmap_write(info->regmap, SUN4I_GPADC_INT_FIFOC,
> + SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(1) |
> + SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH);
> + if (ret)
> + return ret;
> +
> + if (irq == info->fifo_data_irq) {
> + ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
> + info->data->tp_mode_en |
> + info->data->tp_adc_select |
> + info->data->adc_chan_select(channel));
> + } else {
> + /*
> + * The temperature sensor returns valid data only when the ADC
> + * operates in touchscreen mode.
> + */
> + ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
> + info->data->tp_mode_en);
> + }
> +
> + if (ret)
> + return ret;
> +
> + enable_irq(irq);
> +
> + if (!wait_for_completion_timeout(&info->completion,
> + msecs_to_jiffies(100))) {
> + if ((irq == info->fifo_data_irq && info->adc_data == -1) ||
> + (irq == info->temp_data_irq && info->temp_data == -1)) {
> + ret = -ETIMEDOUT;
> + goto out;
> + }
> + }
> +
> + if (irq == info->fifo_data_irq)
> + *val = info->adc_data;
> + else
> + *val = info->temp_data;
> +
> + ret = 0;
> +
> +out:
> + disable_irq(irq);
> + mutex_unlock(&info->mutex);
> + pm_runtime_mark_last_busy(indio_dev->dev.parent);
> + pm_runtime_put_autosuspend(indio_dev->dev.parent);
> +
> + return ret;
> +}
> +
> +static int sun4i_gpadc_adc_read(struct iio_dev *indio_dev, int channel,
> + int *val)
> +{
> + struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
> +
> + return sun4i_gpadc_read(indio_dev, channel, val, info->fifo_data_irq);
> +}
> +
> +static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
> +{
> + struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
> +
> + return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq);
> +}
> +
> +static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val)
> +{
> + struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
> +
> + *val = info->data->temp_offset;
> +
> + return 0;
> +}
> +
> +static int sun4i_gpadc_temp_scale(struct iio_dev *indio_dev, int *val)
> +{
> + struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
> +
> + *val = info->data->temp_scale;
> +
> + return 0;
> +}
> +
> +static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan, int *val,
> + int *val2, long mask)
> +{
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_OFFSET:
> + ret = sun4i_gpadc_temp_offset(indio_dev, val);
> + if (ret)
> + return ret;
> +
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_RAW:
> + if (chan->type == IIO_VOLTAGE)
> + ret = sun4i_gpadc_adc_read(indio_dev, chan->channel,
> + val);
> + else
> + ret = sun4i_gpadc_temp_read(indio_dev, val);
> +
> + if (ret)
> + return ret;
> +
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_SCALE:
> + ret = sun4i_gpadc_temp_scale(indio_dev, val);
> + if (ret)
> + return ret;
> +
> + return IIO_VAL_INT;
> + default:
> + return -EINVAL;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static const struct iio_info sun4i_gpadc_iio_info = {
> + .read_raw = sun4i_gpadc_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id)
> +{
> + struct sun4i_gpadc_iio *info = dev_id;
> +
> + if (atomic_read(&info->ignore_temp_data_irq))
> + return IRQ_HANDLED;
> +
> + if (!regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, &info->temp_data))
> + complete(&info->completion);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id)
> +{
> + struct sun4i_gpadc_iio *info = dev_id;
> +
> + if (atomic_read(&info->ignore_fifo_data_irq))
> + return IRQ_HANDLED;
> +
> + if (!regmap_read(info->regmap, SUN4I_GPADC_DATA, &info->adc_data))
> + complete(&info->completion);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int sun4i_gpadc_runtime_suspend(struct device *dev)
> +{
> + struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> +
> + /* Disable the ADC on IP */
> + regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
> + /* Disable temperature sensor on IP */
> + regmap_write(info->regmap, SUN4I_GPADC_TPR, 0);
> +
> + return 0;
> +}
> +
> +static int sun4i_gpadc_runtime_resume(struct device *dev)
> +{
> + struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> +
> + /* clkin = 6MHz */
> + regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
> + SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
> + SUN4I_GPADC_CTRL0_FS_DIV(7) |
> + SUN4I_GPADC_CTRL0_T_ACQ(63));
> + regmap_write(info->regmap, SUN4I_GPADC_CTRL1, info->data->tp_mode_en);
> + regmap_write(info->regmap, SUN4I_GPADC_CTRL3,
> + SUN4I_GPADC_CTRL3_FILTER_EN |
> + SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
> + /* period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin; ~1.3s */
> + regmap_write(info->regmap, SUN4I_GPADC_TPR,
> + SUN4I_GPADC_TPR_TEMP_ENABLE |
> + SUN4I_GPADC_TPR_TEMP_PERIOD(1953));
> +
> + return 0;
> +}
> +
> +static int sun4i_gpadc_get_temp(void *data, int *temp)
> +{
> + struct sun4i_gpadc_iio *info = (struct sun4i_gpadc_iio *)data;
> + int val, scale, offset;
> +
> + /* If reading temperature times out, take stored previous value. */
> + if (sun4i_gpadc_temp_read(info->indio_dev, &val))
> + val = info->temp_data;
> + sun4i_gpadc_temp_scale(info->indio_dev, &scale);
> + sun4i_gpadc_temp_offset(info->indio_dev, &offset);
> +
> + *temp = (val + offset) * scale;
> +
> + return 0;
> +}
> +
> +static const struct thermal_zone_of_device_ops sun4i_ts_tz_ops = {
> + .get_temp = &sun4i_gpadc_get_temp,
> +};
> +
> +static const struct dev_pm_ops sun4i_gpadc_pm_ops = {
> + .runtime_suspend = &sun4i_gpadc_runtime_suspend,
> + .runtime_resume = &sun4i_gpadc_runtime_resume,
> +};
> +
> +static int sun4i_irq_init(struct platform_device *pdev, const char *name,
> + irq_handler_t handler, const char *devname,
> + unsigned int *irq, atomic_t *atomic)
> +{
> + int ret;
> + struct sun4i_gpadc_dev *mfd_dev = dev_get_drvdata(pdev->dev.parent);
> + struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(&pdev->dev));
> +
> + /*
> + * Once the interrupt is activated, the IP continuously performs
> + * conversions thus throws interrupts. The interrupt is activated right
> + * after being requested but we want to control when these interrupts
> + * occur thus we disable it right after being requested. However, an
> + * interrupt might occur between these two instructions and we have to
> + * make sure that does not happen, by using atomic flags. We set the
> + * flag before requesting the interrupt and unset it right after
> + * disabling the interrupt. When an interrupt occurs between these two
> + * instructions, reading the atomic flag will tell us to ignore the
> + * interrupt.
> + */
> + atomic_set(atomic, 1);
> +
> + *irq = platform_get_irq_byname(pdev, name);
> + if (*irq < 0) {
> + dev_err(&pdev->dev, "no %s interrupt registered\n", name);
> + return *irq;
> + }
> +
> + *irq = regmap_irq_get_virq(mfd_dev->regmap_irqc, *irq);
> + ret = devm_request_any_context_irq(&pdev->dev, *irq, handler, 0,
> + devname, info);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "could not request %s interrupt: %d\n",
> + name, ret);
> + return ret;
> + }
> +
> + disable_irq(*irq);
> + atomic_set(atomic, 0);
> +
> + return 0;
> +}
> +
> +static int sun4i_gpadc_probe(struct platform_device *pdev)
> +{
> + struct sun4i_gpadc_iio *info;
> + struct iio_dev *indio_dev;
> + int ret;
> + struct sun4i_gpadc_dev *sun4i_gpadc_dev;
> + struct thermal_zone_device *tzd;
> +
> + sun4i_gpadc_dev = dev_get_drvdata(pdev->dev.parent);
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
> + if (!indio_dev)
> + return -ENOMEM;
> +
> + info = iio_priv(indio_dev);
> + platform_set_drvdata(pdev, indio_dev);
> +
> + mutex_init(&info->mutex);
> + info->regmap = sun4i_gpadc_dev->regmap;
> + info->indio_dev = indio_dev;
> + info->temp_data = -1;
> + info->adc_data = -1;
> + init_completion(&info->completion);
> + indio_dev->name = dev_name(&pdev->dev);
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->info = &sun4i_gpadc_iio_info;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels);
> + indio_dev->channels = sun4i_gpadc_channels;
> +
> + info->data = (struct gpadc_data *)platform_get_device_id(pdev)->driver_data;
> +
> + /*
> + * This driver is a child of an MFD which has a node in the DT but not
> + * its children. Therefore, the resulting devices of this driver do not
> + * have an of_node variable.
> + * However, its parent (the MFD driver) has an of_node variable and
> + * since devm_thermal_zone_of_sensor_register uses its first argument to
> + * match the phandle defined in the node of the thermal driver with the
> + * of_node of the device passed as first argument and the third argument
> + * to call ops from thermal_zone_of_device_ops, the solution is to use
> + * the parent device as first argument to match the phandle with its
> + * of_node, and the device from this driver as third argument to return
> + * the temperature.
> + */
> + tzd = devm_thermal_zone_of_sensor_register(pdev->dev.parent, 0, info,
> + &sun4i_ts_tz_ops);
> + if (IS_ERR(tzd)) {
> + dev_err(&pdev->dev, "could not register thermal sensor: %ld\n",
> + PTR_ERR(tzd));
> + return PTR_ERR(tzd);
> + }
> +
> + pm_runtime_set_autosuspend_delay(&pdev->dev,
> + SUN4I_GPADC_AUTOSUSPEND_DELAY);
> + pm_runtime_use_autosuspend(&pdev->dev);
> + pm_runtime_set_suspended(&pdev->dev);
> + pm_runtime_enable(&pdev->dev);
> +
> + ret = sun4i_irq_init(pdev, "TEMP_DATA_PENDING",
> + sun4i_gpadc_temp_data_irq_handler, "temp_data",
> + &info->temp_data_irq, &info->ignore_temp_data_irq);
> + if (ret < 0)
> + goto err;
> +
> + ret = sun4i_irq_init(pdev, "FIFO_DATA_PENDING",
> + sun4i_gpadc_fifo_data_irq_handler, "fifo_data",
> + &info->fifo_data_irq, &info->ignore_fifo_data_irq);
> + if (ret < 0)
> + goto err;
> +
> + ret = iio_map_array_register(indio_dev, sun4i_gpadc_hwmon_maps);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed to register iio map array\n");
> + goto err;
> + }
> +
> + ret = iio_device_register(indio_dev);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "could not register the device\n");
> + goto err_map;
> + }
> +
> + return 0;
> +
> +err_map:
> + iio_map_array_unregister(indio_dev);
> +
> +err:
> + pm_runtime_put(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> +
> + return ret;
> +}
> +
> +static int sun4i_gpadc_remove(struct platform_device *pdev)
> +{
> + struct sun4i_gpadc_iio *info;
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + pm_runtime_put(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> + info = iio_priv(indio_dev);
> + iio_map_array_unregister(indio_dev);
> + iio_device_unregister(indio_dev);
> +
> + return 0;
> +}
> +
> +static const struct platform_device_id sun4i_gpadc_id[] = {
> + { "sun4i-a10-gpadc-iio", (kernel_ulong_t)&sun4i_gpadc_data },
> + { "sun5i-a13-gpadc-iio", (kernel_ulong_t)&sun5i_gpadc_data },
> + { "sun6i-a31-gpadc-iio", (kernel_ulong_t)&sun6i_gpadc_data },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver sun4i_gpadc_driver = {
> + .driver = {
> + .name = "sun4i-gpadc-iio",
> + .pm = &sun4i_gpadc_pm_ops,
> + },
> + .id_table = sun4i_gpadc_id,
> + .probe = sun4i_gpadc_probe,
> + .remove = sun4i_gpadc_remove,
> +};
> +
> +module_platform_driver(sun4i_gpadc_driver);
> +
> +MODULE_DESCRIPTION("ADC driver for sunxi platforms");
> +MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply
* [PATCH 1/4] mfd: ti_am335x_tscadc: store physical address
From: Jonathan Cameron @ 2016-10-30 17:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161026121730.GS8574@dell>
On 26/10/16 13:17, Lee Jones wrote:
> On Fri, 30 Sep 2016, Mugunthan V N wrote:
>
>> On Wednesday 28 September 2016 01:10 AM, Lee Jones wrote:
>>> On Wed, 21 Sep 2016, Mugunthan V N wrote:
>>>
>>>> store the physical address of the device in its priv to use it
>>>> for DMA addressing in the client drivers.
>>>>
>>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>>>> ---
>>>> drivers/mfd/ti_am335x_tscadc.c | 1 +
>>>> include/linux/mfd/ti_am335x_tscadc.h | 1 +
>>>> 2 files changed, 2 insertions(+)
>>>>
>>>> diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
>>>> index c8f027b..0f3fab4 100644
>>>> --- a/drivers/mfd/ti_am335x_tscadc.c
>>>> +++ b/drivers/mfd/ti_am335x_tscadc.c
>>>> @@ -183,6 +183,7 @@ static int ti_tscadc_probe(struct platform_device *pdev)
>>>> tscadc->irq = err;
>>>>
>>>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>> + tscadc->tscadc_phys_base = res->start;
>>>
>>> This is unusual. Can't you use a virt_to_phys() variant instead?
>>>
>>
>> I tried using virt_to_phys(), but its not working for me.
>> Also saw many drivers uses like this to get physical address
>> ("git grep -n " res->start;" drivers/*").
>
> Very well:
>
> For my own reference:
> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
>
> Let me know how you wish this set to be handled.
I'm happy to pick up the whole series. There are some more mfd
header changes in patch 2 but as they only add defines, I
don't mind that much if I don't an Ack from you on those
(btw this got to V3 but as patch 1 didn't change I'll carry
your ack forwards).
Do you want an immutable branch? Seems unlikely to cause
much trouble even if there is a merge issue on all 10ish
lines of mfd code in the next merge window.
Jonathan
>
^ permalink raw reply
* [PATCH V2 2/2] ARM: dts: bcm283x: fix typo in mailbox address
From: Stefan Wahren @ 2016-10-30 17:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6b13e96d-78d1-fcab-4273-803310ae4da6@suse.de>
The address of the mailbox node in the bcm283x.dtsi also has a typo.
So fix it accordingly.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Fixes: 05b682b7a3b2 ("ARM: bcm2835: dt: Add the mailbox to the device tree")
---
Changes in V2:
* fixed commit message as reported by Andreas
arch/arm/boot/dts/bcm283x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 46d46d8..74dd21b 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -104,7 +104,7 @@
reg = <0x7e104000 0x10>;
};
- mailbox: mailbox at 7e00b800 {
+ mailbox: mailbox at 7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
--
1.7.9.5
^ permalink raw reply related
* [RFC] fpga: Pull checks for supported operations into framework
From: Moritz Fischer @ 2016-10-30 18:12 UTC (permalink / raw)
To: linux-arm-kernel
Most of the drivers only support a subset of {PARTIAL, FULL}
reconfiguration.
Pull duplicate checks in each driver into the framework.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Alan Tull <atull@opensource.altera.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: S?ren Brinkmann <soren.brinkmann@xilinx.com>
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
Hi all,
with the new drivers (ice40, altera-ps-spi) being submitted I've noticed
we're duplicating this check over and over again,
so I figured we might as well pull it into the framework.
I'm not sure if there are gonna be other 'flags' we need to support
in the short term (we talked about byte-swapping ...)
Note: This patch goes on top of greg's char-misc-testing that already
contains Alan's latest changes to support the A10 and won't apply
to master.
Cheers,
Moritz
---
drivers/fpga/fpga-mgr.c | 12 ++++++++++++
drivers/fpga/socfpga-a10.c | 4 +++-
drivers/fpga/socfpga.c | 3 ++-
drivers/fpga/zynq-fpga.c | 3 ++-
include/linux/fpga/fpga-mgr.h | 9 +++++++--
5 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index c58b4c4..85f17d8 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -49,6 +49,11 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
struct device *dev = &mgr->dev;
int ret;
+ if (!(mgr->supported_flags & info->flags)) {
+ dev_err(dev, "Unsupported flags passed\n");
+ return -ENOTSUPP;
+ }
+
/*
* Call the low level driver's write_init function. This will do the
* device-specific things to get the FPGA into the state where it is
@@ -252,6 +257,7 @@ EXPORT_SYMBOL_GPL(fpga_mgr_put);
*/
int fpga_mgr_register(struct device *dev, const char *name,
const struct fpga_manager_ops *mops,
+ u32 supported_flags,
void *priv)
{
struct fpga_manager *mgr;
@@ -268,6 +274,11 @@ int fpga_mgr_register(struct device *dev, const char *name,
return -EINVAL;
}
+ if (!supported_flags) {
+ dev_err(dev, "Attempt to register with no supported flags\n");
+ return -EINVAL;
+ }
+
mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
if (!mgr)
return -ENOMEM;
@@ -282,6 +293,7 @@ int fpga_mgr_register(struct device *dev, const char *name,
mgr->name = name;
mgr->mops = mops;
+ mgr->supported_flags = supported_flags;
mgr->priv = priv;
/*
diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c
index ccd9fb2..e7c82ff 100644
--- a/drivers/fpga/socfpga-a10.c
+++ b/drivers/fpga/socfpga-a10.c
@@ -519,7 +519,9 @@ static int socfpga_a10_fpga_probe(struct platform_device *pdev)
}
return fpga_mgr_register(dev, "SoCFPGA Arria10 FPGA Manager",
- &socfpga_a10_fpga_mgr_ops, priv);
+ &socfpga_a10_fpga_mgr_ops,
+ FPGA_MGR_PARTIAL_RECONFIG,
+ priv);
}
static int socfpga_a10_fpga_remove(struct platform_device *pdev)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index b6672e6..3285b7d 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -582,7 +582,8 @@ static int socfpga_fpga_probe(struct platform_device *pdev)
return ret;
return fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
- &socfpga_fpga_ops, priv);
+ &socfpga_fpga_ops, FPGA_MGR_FULL_RECONFIG,
+ priv);
}
static int socfpga_fpga_remove(struct platform_device *pdev)
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index 249682e..1dabd25 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -413,6 +413,7 @@ static int zynq_fpga_probe(struct platform_device *pdev)
struct zynq_fpga_priv *priv;
struct resource *res;
int err;
+ u32 flags = FPGA_MGR_FULL_RECONFIG | FPGA_MGR_PARTIAL_RECONFIG;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -465,7 +466,7 @@ static int zynq_fpga_probe(struct platform_device *pdev)
clk_disable(priv->clk);
err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",
- &zynq_fpga_ops, priv);
+ &zynq_fpga_ops, flags, priv);
if (err) {
dev_err(dev, "unable to register FPGA manager");
clk_unprepare(priv->clk);
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 040b86d..4f4bcf2 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -64,9 +64,12 @@ enum fpga_mgr_states {
/*
* FPGA Manager flags
+ * FPGA_MGR_FULL_RECONFIG: do full reconfiguration if supported
* FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
*/
-#define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
+#define FPGA_MGR_FULL_RECONFIG BIT(0)
+#define FPGA_MGR_PARTIAL_RECONFIG BIT(1)
+#define FPGA_MGR_EXTERNAL_CONFIG BIT(2)
/**
* struct fpga_image_info - information specific to a FPGA image
@@ -119,6 +122,7 @@ struct fpga_manager {
enum fpga_mgr_states state;
const struct fpga_manager_ops *mops;
void *priv;
+ u32 supported_flags;
};
#define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
@@ -135,7 +139,8 @@ struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
void fpga_mgr_put(struct fpga_manager *mgr);
int fpga_mgr_register(struct device *dev, const char *name,
- const struct fpga_manager_ops *mops, void *priv);
+ const struct fpga_manager_ops *mops, u32 supported_flags,
+ void *priv);
void fpga_mgr_unregister(struct device *dev);
--
2.4.11
^ permalink raw reply related
* [PATCH 1/2] ABI: rtc-ab8500: fix rtc_calibration documentation
From: Alexandre Belloni @ 2016-10-30 20:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <364a36215c44e0c2785911e9d9259cd866283cb9.1477735797.git.mchehab@s-opensource.com>
On 29/10/2016 at 08:10:02 -0200, Mauro Carvalho Chehab wrote :
> The "What:" field at the ABI should describe the location of
> the ABI, e. g. the position under a mounted sysfs.
>
> Fix it.
>
> Cc: Mark Godfrey <mark.godfrey@stericsson.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Alessandro Zummo <a.zummo@towertech.it>
> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: rtc-linux at googlegroups.com
> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
> ---
> .../ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Applied, thanks.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v5 1/7] drm: sunxi: Add a basic DRM driver for Allwinner DE2
From: Rob Herring @ 2016-10-30 20:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161025161441.6b248efe9229bd80e3f7a33c@free.fr>
On Tue, Oct 25, 2016 at 04:14:41PM +0200, Jean-Francois Moine wrote:
> On Mon, 24 Oct 2016 16:04:19 +0200
> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
>
> > Hi,
>
> Hi Maxime,
>
> > On Fri, Oct 21, 2016 at 09:26:18AM +0200, Jean-Francois Moine wrote:
> > > Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
> > > engine, DE2.
> > > This patch adds a DRM video driver for this device.
> > >
> > > Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> >
> > Output from checkpatch:
> > total: 0 errors, 20 warnings, 83 checks, 1799 lines checked
> >
> > > ---
> > > .../bindings/display/sunxi/sunxi-de2.txt | 83 +++
> > > drivers/gpu/drm/Kconfig | 2 +
> > > drivers/gpu/drm/Makefile | 1 +
> > > drivers/gpu/drm/sunxi/Kconfig | 21 +
> > > drivers/gpu/drm/sunxi/Makefile | 7 +
> > > drivers/gpu/drm/sunxi/de2_crtc.c | 475 +++++++++++++++++
> > > drivers/gpu/drm/sunxi/de2_crtc.h | 63 +++
> > > drivers/gpu/drm/sunxi/de2_de.c | 591 +++++++++++++++++++++
> > > drivers/gpu/drm/sunxi/de2_drm.h | 47 ++
> > > drivers/gpu/drm/sunxi/de2_drv.c | 378 +++++++++++++
> > > drivers/gpu/drm/sunxi/de2_plane.c | 119 +++++
> > > 11 files changed, 1787 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> > > create mode 100644 drivers/gpu/drm/sunxi/Kconfig
> > > create mode 100644 drivers/gpu/drm/sunxi/Makefile
> > > create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c
> > > create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h
> > > create mode 100644 drivers/gpu/drm/sunxi/de2_de.c
> > > create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h
> > > create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c
> > > create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt b/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> > > new file mode 100644
> > > index 0000000..f9cd67a
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
[...]
> > > +
> > > +- resets: phandle to the reset of the device
> > > +
> > > +- ports: phandle's to the LCD ports
> >
> > Please use the OF graph.
>
> These ports are references to the graph of nodes. See
> http://www.kernelhub.org/?msg=911825&p=2
I think what Maxime means is describe the DE to LCD connection with OF
graph, not just a phandle.
Rob
^ permalink raw reply
* [PATCH v5 1/7] drm: sunxi: Add a basic DRM driver for Allwinner DE2
From: Rob Herring @ 2016-10-30 20:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8afc5e020c5767face34fe3a9ab300ce9e67ba00.1477142934.git.moinejf@free.fr>
On Fri, Oct 21, 2016 at 09:26:18AM +0200, Jean-Francois Moine wrote:
> Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
> engine, DE2.
> This patch adds a DRM video driver for this device.
>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---
> .../bindings/display/sunxi/sunxi-de2.txt | 83 +++
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/sunxi/Kconfig | 21 +
> drivers/gpu/drm/sunxi/Makefile | 7 +
> drivers/gpu/drm/sunxi/de2_crtc.c | 475 +++++++++++++++++
> drivers/gpu/drm/sunxi/de2_crtc.h | 63 +++
> drivers/gpu/drm/sunxi/de2_de.c | 591 +++++++++++++++++++++
> drivers/gpu/drm/sunxi/de2_drm.h | 47 ++
> drivers/gpu/drm/sunxi/de2_drv.c | 378 +++++++++++++
> drivers/gpu/drm/sunxi/de2_plane.c | 119 +++++
> 11 files changed, 1787 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> create mode 100644 drivers/gpu/drm/sunxi/Kconfig
> create mode 100644 drivers/gpu/drm/sunxi/Makefile
> create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_de.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt b/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> new file mode 100644
> index 0000000..f9cd67a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> + hdmi: hdmi at 01ee0000 {
> + ...
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port {
> + type = "video";
This is proposed, but not an accepted property. Please drop.
> + hdmi_ep: endpoint {
> + remote-endpoint = <&lcd0_ep>;
> + };
> + };
> + };
^ permalink raw reply
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