* [PATCH v6 6/7] ARM: dts: sk-rzg1m: initial device tree
From: Sergei Shtylyov @ 2016-10-31 19:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1746536.qobnGdHRfV@wasted.cogentembedded.com>
Add the initial device tree for the R8A7743 SoC based SK-RZG1M board.
The board has one debug serial port (SCIF0); include support for it, so
that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 4:
- refreshed the patch.
Changes in version 3:
- added Geert's tag.
arch/arm/boot/dts/Makefile | 1
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 +++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
Index: renesas/arch/arm/boot/dts/Makefile
===================================================================
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -677,6 +677,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
+ r8a7743-sk-rzg1m.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Source for the SK-RZG1M board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743.dtsi"
+
+/ {
+ model = "SK-RZG1M";
+ compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
+
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory at 200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif0 {
+ status = "okay";
+};
^ permalink raw reply
* [PATCH v6 5/7] ARM: dts: r8a7743: add IRQC support
From: Sergei Shtylyov @ 2016-10-31 19:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1746536.qobnGdHRfV@wasted.cogentembedded.com>
Describe the IRQC interrupt controller in the R8A7743 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 4:
- refreshed the patch;
- added Geert's tag.
Changes in version 3:
- updated the "clocks" property for the CPG/MSSR driver.
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller at e61c0000 {
+ compatible = "renesas,irqc-r8a7743", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
^ permalink raw reply
* [PATCH] staging: vc04_services: setup DMA and coherent mask
From: Michael Zoran @ 2016-10-31 19:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477943593.30971.3.camel@crowfest.net>
On Mon, 2016-10-31 at 12:53 -0700, Michael Zoran wrote:
> On Mon, 2016-10-31 at 11:40 -0700, Michael Zoran wrote:
> > On Mon, 2016-10-31 at 11:36 -0700, Eric Anholt wrote:
> > > Michael Zoran <mzoran@crowfest.net> writes:
> > >
> > > > Setting the DMA mask is optional on 32 bit but
> > > > is mandatory on 64 bit.??Set the DMA mask and coherent
> > > > to force all DMA to be in the 32 bit address space.
> > > >
> > > > This is considered a "good practice" and most drivers
> > > > already do this.
> > > >
> > > > Signed-off-by: Michael Zoran <mzoran@crowfest.net>
> > > > ---
> > > > ?.../staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> > > > |
> > > > 10 ++++++++++
> > > > ?1 file changed, 10 insertions(+)
> > > >
> > > > diff --git
> > > > a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_
> > > > ar
> > > > m.
> > > > c
> > > > b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_
> > > > ar
> > > > m.
> > > > c
> > > > index a5afcc5..6fa2b5a 100644
> > > > ---
> > > > a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_
> > > > ar
> > > > m.
> > > > c
> > > > +++
> > > > b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_
> > > > ar
> > > > m.
> > > > c
> > > > @@ -97,6 +97,16 @@ int vchiq_platform_init(struct
> > > > platform_device
> > > > *pdev, VCHIQ_STATE_T *state)
> > > > ? int slot_mem_size, frag_mem_size;
> > > > ? int err, irq, i;
> > > > ?
> > > > + /*
> > > > + ?* Setting the DMA mask is necessary in the 64 bit
> > > > environment.
> > > > + ?* It isn't necessary in a 32 bit environment but is
> > > > considered
> > > > + ?* a good practice.
> > > > + ?*/
> > > > + err = dma_set_mask_and_coherent(dev,
> > > > DMA_BIT_MASK(32));
> > >
> > > I think a better comment here would be simply:
> > >
> > > /* VCHI messages between the CPU and firmware use 32-bit bus
> > > addresses. */
> > >
> > > explaining why the value is chosen (once you know that the 32 bit
> > > restriction exists, reporting it is obviously needed).??I'm
> > > curious,
> > > though: what failed when you didn't set it?
> > >
> >
> > The comment is easy to change.
> >
> > I don't have the log available ATM, but if I remember the DMA API's
> > bugcheck the first time that are used.??
> >
> > I think this was a policy decision or something because the
> > information
> > should be available in the dma-ranges.
> >
> > If it's important, I can setup a test again without the change and
> > e-
> > mail the logs.
> >
> > If you look at the DWC2 driver you will see that it also sets this
> > mask.
>
> OK, I'm begging to understand this.??It appears the architecture
> specific paths are very different.
>
> In arm the mask and coherent is set to DMA_BIT_MASK(32) in mm/dma-
> mapping.c the first time the dma APIs are used.??On arm64, it appears
> this variable is uninitialized and will contain random crude.
>
> Like I said, I don't know if this is a policy decision or if it just
> slipped through the cracks.
>
Actually, I'm getting confused here. If I need to prove this is
needed, is their anybody I can send e-mail to that has a deep
understanding of the two different architecture paths. Perhaps they
can explain exactly why arm64 is not defaulting to 32 bit DMA.
^ permalink raw reply
* [PATCH v6 4/7] ARM: dts: r8a7743: add Ether support
From: Sergei Shtylyov @ 2016-10-31 19:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1746536.qobnGdHRfV@wasted.cogentembedded.com>
Define the generic R8A7743 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 5:
- refreshed the patch.
Changes in version 4:
- refreshed the patch;
- added Geert's tag.
Changes in version 3:
- resolved a reject;
- updated the "clocks" property for the CPG/MSSR driver.
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -418,6 +418,18 @@
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ ether: ethernet at ee700000 {
+ compatible = "renesas,ether-r8a7743";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply
* [PATCH v6 3/7] ARM: dts: r8a7743: add [H]SCIF{A|B} support
From: Sergei Shtylyov @ 2016-10-31 19:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1746536.qobnGdHRfV@wasted.cogentembedded.com>
Describe [H]SCIF{|A|B} ports in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 5:
- refreshed the patch.
Changes in version 4:
- corrected RBNF in the patch description/subject;
- used the R-Car gen2 bindings instead of the RZ/G family ones;
- refreshed the patch;
- added Geert's tag.
Changes in version 3:
- resolved a reject;
- updated the "clocks" properties for the CPG/MSSR driver;
- renamed the patch.
Changes in version 2:
- used the new RZ/G family "compatible" prop values, reformatting where needed;
- fixed the size cells of the SCIFB device nodes' "reg" properties;
- changed the size cells of the "reg" properties to hexadecimal;
- indented the SCIFA1 device node's closing brace correctly
- adjusted the patch description, renamed the patch.
arch/arm/boot/dts/r8a7743.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 261 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -157,6 +157,267 @@
#dma-cells = <1>;
dma-channels = <15>;
};
+
+ scifa0: serial at e6c40000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa1: serial at e6c50000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa2: serial at e6c60000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa3: serial at e6c70000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 0x40>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa4: serial at e6c78000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa5: serial at e6c80000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb0: serial at e6c20000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb1: serial at e6c30000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb2: serial at e6ce0000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif0: serial at e6e60000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial at e6e68000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial at e6e58000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial at e6ea8000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif4: serial at e6ee0000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif5: serial at e6ee8000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial at e62c0000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial at e62c8000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif2: serial at e62d0000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 0x60>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply
* [PATCH v1 2/3] nvmem: Add the Broadcom OTP controller driver
From: Scott Branden @ 2016-10-31 19:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f51e98c8-af71-5722-ab30-a27e176ddd5f@linaro.org>
Florian,
On 16-10-31 07:23 AM, Srinivas Kandagatla wrote:
>
> On 24/10/16 20:12, Jonathan Richardson wrote:
>> From: Jonathan Richardson <jonathar@broadcom.com>
>>
>> Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
>> controller. These controllers are used on SoC's such as Cygnus and
>> Stingray.
>>
>> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
>> Tested-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
>> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
>> Signed-off-by: Oza Pawandeep <oza@broadcom.com>
>> Signed-off-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
>> ---
>> drivers/nvmem/Kconfig | 12 ++
>> drivers/nvmem/Makefile | 2 +
>> drivers/nvmem/bcm-ocotp.c | 335
>> ++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 349 insertions(+)
>> create mode 100644 drivers/nvmem/bcm-ocotp.c
>
>
> I can pick this patch along with dt bindings document, but dts patch has
> to go via arm-soc tree.
Can you pick up [PATCH v1 3/3] ARM: dts: Add node from Broadcom OTP
controller driver?
>
> Thanks,
> srini
>
>
Thanks,
Scott
^ permalink raw reply
* [PATCH v3 4/4] cpufreq: pxa: convert to clock API
From: Robert Jarzmik @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477943696-23477-1-git-send-email-robert.jarzmik@free.fr>
As the clock settings have been introduced into the clock pxa drivers,
which are now available to change the CPU clock by themselves, remove
the clock handling from this driver, and rely on pxa clock drivers.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
Since v1: added !OF Kconfig dependency
Since v2: removed !OF Kconfig dependency
---
drivers/cpufreq/pxa2xx-cpufreq.c | 191 ++++++++-------------------------------
1 file changed, 39 insertions(+), 152 deletions(-)
diff --git a/drivers/cpufreq/pxa2xx-cpufreq.c b/drivers/cpufreq/pxa2xx-cpufreq.c
index ce345bf34d5d..06b024a3e474 100644
--- a/drivers/cpufreq/pxa2xx-cpufreq.c
+++ b/drivers/cpufreq/pxa2xx-cpufreq.c
@@ -58,56 +58,40 @@ module_param(pxa27x_maxfreq, uint, 0);
MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
+struct pxa_cpufreq_data {
+ struct clk *clk_core;
+};
+static struct pxa_cpufreq_data pxa_cpufreq_data;
+
struct pxa_freqs {
unsigned int khz;
- unsigned int membus;
- unsigned int cccr;
- unsigned int div2;
- unsigned int cclkcfg;
int vmin;
int vmax;
};
-/* Define the refresh period in mSec for the SDRAM and the number of rows */
-#define SDRAM_TREF 64 /* standard 64ms SDRAM */
-static unsigned int sdram_rows;
-
-#define CCLKCFG_TURBO 0x1
-#define CCLKCFG_FCS 0x2
-#define CCLKCFG_HALFTURBO 0x4
-#define CCLKCFG_FASTBUS 0x8
-#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
-#define MDREFR_DRI_MASK 0xFFF
-
-#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
-#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
-
/*
* PXA255 definitions
*/
-/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
-#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
-
static const struct pxa_freqs pxa255_run_freqs[] =
{
- /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
- { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
- {132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
- {199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
- {265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
- {331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
- {398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
+ /* CPU MEMBUS run turbo PXbus SDRAM */
+ { 99500, -1, -1}, /* 99, 99, 50, 50 */
+ {132700, -1, -1}, /* 133, 133, 66, 66 */
+ {199100, -1, -1}, /* 199, 199, 99, 99 */
+ {265400, -1, -1}, /* 265, 265, 133, 66 */
+ {331800, -1, -1}, /* 331, 331, 166, 83 */
+ {398100, -1, -1}, /* 398, 398, 196, 99 */
};
/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
static const struct pxa_freqs pxa255_turbo_freqs[] =
{
- /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
- { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
- {199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
- {298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
- {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
- {398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
+ /* CPU run turbo PXbus SDRAM */
+ { 99500, -1, -1}, /* 99, 99, 50, 50 */
+ {199100, -1, -1}, /* 99, 199, 50, 99 */
+ {298500, -1, -1}, /* 99, 287, 50, 99 */
+ {298600, -1, -1}, /* 199, 287, 99, 99 */
+ {398100, -1, -1}, /* 199, 398, 99, 99 */
};
#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
@@ -122,47 +106,14 @@ static unsigned int pxa255_turbo_table;
module_param(pxa255_turbo_table, uint, 0);
MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
-/*
- * PXA270 definitions
- *
- * For the PXA27x:
- * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
- *
- * A = 0 => memory controller clock from table 3-7,
- * A = 1 => memory controller clock = system bus clock
- * Run mode frequency = 13 MHz * L
- * Turbo mode frequency = 13 MHz * L * N
- * System bus frequency = 13 MHz * L / (B + 1)
- *
- * In CCCR:
- * A = 1
- * L = 16 oscillator to run mode ratio
- * 2N = 6 2 * (turbo mode to run mode ratio)
- *
- * In CCLKCFG:
- * B = 1 Fast bus mode
- * HT = 0 Half-Turbo mode
- * T = 1 Turbo mode
- *
- * For now, just support some of the combinations in table 3-7 of
- * PXA27x Processor Family Developer's Manual to simplify frequency
- * change sequences.
- */
-#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
-#define CCLKCFG2(B, HT, T) \
- (CCLKCFG_FCS | \
- ((B) ? CCLKCFG_FASTBUS : 0) | \
- ((HT) ? CCLKCFG_HALFTURBO : 0) | \
- ((T) ? CCLKCFG_TURBO : 0))
-
static struct pxa_freqs pxa27x_freqs[] = {
- {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
- {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
- {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
- {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
- {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
- {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
- {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
+ {104000, 900000, 1705000 },
+ {156000, 1000000, 1705000 },
+ {208000, 1180000, 1705000 },
+ {312000, 1250000, 1705000 },
+ {416000, 1350000, 1705000 },
+ {520000, 1450000, 1705000 },
+ {624000, 1550000, 1705000 }
};
#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
@@ -241,51 +192,29 @@ static void pxa27x_guess_max_freq(void)
}
}
-static void init_sdram_rows(void)
-{
- uint32_t mdcnfg = __raw_readl(MDCNFG);
- unsigned int drac2 = 0, drac0 = 0;
-
- if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
- drac2 = MDCNFG_DRAC2(mdcnfg);
-
- if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
- drac0 = MDCNFG_DRAC0(mdcnfg);
-
- sdram_rows = 1 << (11 + max(drac0, drac2));
-}
-
-static u32 mdrefr_dri(unsigned int freq)
-{
- u32 interval = freq * SDRAM_TREF / sdram_rows;
-
- return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
-}
-
static unsigned int pxa_cpufreq_get(unsigned int cpu)
{
- return get_clk_frequency_khz(0);
+ struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
+
+ return (unsigned int) clk_get_rate(data->clk_core) / 1000;
}
static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
{
struct cpufreq_frequency_table *pxa_freqs_table;
const struct pxa_freqs *pxa_freq_settings;
- unsigned long flags;
- unsigned int new_freq_cpu, new_freq_mem;
- unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
+ struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
+ unsigned int new_freq_cpu;
int ret = 0;
/* Get the current policy */
find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
new_freq_cpu = pxa_freq_settings[idx].khz;
- new_freq_mem = pxa_freq_settings[idx].membus;
if (freq_debug)
- pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
- new_freq_cpu / 1000, (pxa_freq_settings[idx].div2) ?
- (new_freq_mem / 2000) : (new_freq_mem / 1000));
+ pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
+ policy->cur / 1000, new_freq_cpu / 1000);
if (vcc_core && new_freq_cpu > policy->cur) {
ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
@@ -293,53 +222,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
return ret;
}
- /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
- * we need to preset the smaller DRI before the change. If we're
- * speeding up we need to set the larger DRI value after the change.
- */
- preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
- if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
- preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
- preset_mdrefr |= mdrefr_dri(new_freq_mem);
- }
- postset_mdrefr =
- (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
-
- /* If we're dividing the memory clock by two for the SDRAM clock, this
- * must be set prior to the change. Clearing the divide must be done
- * after the change.
- */
- if (pxa_freq_settings[idx].div2) {
- preset_mdrefr |= MDREFR_DB2_MASK;
- postset_mdrefr |= MDREFR_DB2_MASK;
- } else {
- postset_mdrefr &= ~MDREFR_DB2_MASK;
- }
-
- local_irq_save(flags);
-
- /* Set new the CCCR and prepare CCLKCFG */
- writel(pxa_freq_settings[idx].cccr, CCCR);
- cclkcfg = pxa_freq_settings[idx].cclkcfg;
-
- asm volatile(" \n\
- ldr r4, [%1] /* load MDREFR */ \n\
- b 2f \n\
- .align 5 \n\
-1: \n\
- str %3, [%1] /* preset the MDREFR */ \n\
- mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
- str %4, [%1] /* postset the MDREFR */ \n\
- \n\
- b 3f \n\
-2: b 1b \n\
-3: nop \n\
- "
- : "=&r" (unused)
- : "r" (MDREFR), "r" (cclkcfg),
- "r" (preset_mdrefr), "r" (postset_mdrefr)
- : "r4", "r5");
- local_irq_restore(flags);
+ clk_set_rate(data->clk_core, new_freq_cpu * 1000);
/*
* Even if voltage setting fails, we don't report it, as the frequency
@@ -369,8 +252,6 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy)
pxa_cpufreq_init_voltages();
- init_sdram_rows();
-
/* set default policy and cpuinfo */
policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
@@ -429,11 +310,17 @@ static struct cpufreq_driver pxa_cpufreq_driver = {
.init = pxa_cpufreq_init,
.get = pxa_cpufreq_get,
.name = "PXA2xx",
+ .driver_data = &pxa_cpufreq_data,
};
static int __init pxa_cpu_init(void)
{
int ret = -ENODEV;
+
+ pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
+ if (IS_ERR(pxa_cpufreq_data.clk_core))
+ return PTR_ERR(pxa_cpufreq_data.clk_core);
+
if (cpu_is_pxa25x() || cpu_is_pxa27x())
ret = cpufreq_register_driver(&pxa_cpufreq_driver);
return ret;
--
2.1.4
^ permalink raw reply related
* [PATCH v3 3/4] ARM: dts: pxa: add pxa27x cpu operating points
From: Robert Jarzmik @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477943696-23477-1-git-send-email-robert.jarzmik@free.fr>
Add the relevant data taken from the PXA27x Electrical, Mechanical, and
Thermal Specfication. This will be input data for cpufreq-dt driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
Since v2: opp definition amended as per Viresh's comment
---
arch/arm/boot/dts/pxa27x.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index 9e73dc6b3ed3..e0fab48ba6fa 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -137,4 +137,44 @@
clocks = <&clks CLK_OSTIMER>;
status = "okay";
};
+
+ pxa270_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp at 104000000 {
+ opp-hz = /bits/ 64 <104000000>;
+ opp-microvolt = <900000 900000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 156000000 {
+ opp-hz = /bits/ 64 <156000000>;
+ opp-microvolt = <1000000 1000000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 208000000 {
+ opp-hz = /bits/ 64 <208000000>;
+ opp-microvolt = <1180000 1180000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <1250000 1250000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 416000000 {
+ opp-hz = /bits/ 64 <416000000>;
+ opp-microvolt = <1350000 1350000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 520000000 {
+ opp-hz = /bits/ 64 <520000000>;
+ opp-microvolt = <1450000 1450000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <1550000 1550000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ };
};
--
2.1.4
^ permalink raw reply related
* [PATCH v3 2/4] ARM: dts: pxa: add pxa25x cpu operating points
From: Robert Jarzmik @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477943696-23477-1-git-send-email-robert.jarzmik@free.fr>
Add the relevant data taken from the PXA 25x Electrical, Mechanical, and
Thermal Specfication. This will be input data for cpufreq-dt driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
Since v2: opp definition amended as per Viresh's comment
---
arch/arm/boot/dts/pxa25x.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi
index 0d1e012178c4..f9f4726396a0 100644
--- a/arch/arm/boot/dts/pxa25x.dtsi
+++ b/arch/arm/boot/dts/pxa25x.dtsi
@@ -89,4 +89,29 @@
clocks = <&clktimer>;
status = "okay";
};
+
+ pxa250_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp at 99532800 {
+ opp-hz = /bits/ 64 <99532800>;
+ opp-microvolt = <1000000 950000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 199065600 {
+ opp-hz = /bits/ 64 <199065600>;
+ opp-microvolt = <1000000 950000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 298598400 {
+ opp-hz = /bits/ 64 <298598400>;
+ opp-microvolt = <1100000 1045000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ opp at 398131200 {
+ opp-hz = /bits/ 64 <398131200>;
+ opp-microvolt = <1300000 1235000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ };
};
--
2.1.4
^ permalink raw reply related
* [PATCH v3 1/4] cpufreq: pxa: use generic platdev driver for device-tree
From: Robert Jarzmik @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477943696-23477-1-git-send-email-robert.jarzmik@free.fr>
For device-tree based pxa25x and pxa27x platforms, cpufreq-dt driver is
doing the job as well as pxa2xx-cpufreq, so add these platforms to the
compatibility list.
This won't work for legacy non device-tree platforms where
pxa2xx-cpufreq is still required.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 71267626456b..bc683d6feca8 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -34,6 +34,8 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "fsl,imx7d", },
{ .compatible = "marvell,berlin", },
+ { .compatible = "marvell,pxa250", },
+ { .compatible = "marvell,pxa270", },
{ .compatible = "samsung,exynos3250", },
{ .compatible = "samsung,exynos4210", },
--
2.1.4
^ permalink raw reply related
* [PATCH v3 0/4] PXA cpufreq conversion to clock API
From: Robert Jarzmik @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This serie is a preparation to shift the cpufreq of pxa2xx platforms to clocks
API, next iteration.
The first 3 patches are review and merge material :
- patch 1/4 for Viresh and Rafael
- patches 2/4 and 3/4 for me
The 4th on is for review but not merge, as the clock changes must be fully
reviewed and go in first as a prequisite
Since previous iteration, 2 and 3 were amended per Viresh's suggestion.
Robert Jarzmik (4):
cpufreq: pxa: use generic platdev driver for device-tree
ARM: dts: pxa: add pxa25x cpu operating points
ARM: dts: pxa: add pxa27x cpu operating points
cpufreq: pxa: convert to clock API
arch/arm/boot/dts/pxa25x.dtsi | 25 +++++
arch/arm/boot/dts/pxa27x.dtsi | 40 ++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 2 +
drivers/cpufreq/pxa2xx-cpufreq.c | 191 +++++++----------------------------
4 files changed, 106 insertions(+), 152 deletions(-)
--
2.1.4
^ permalink raw reply
* [PATCH v6 2/7] ARM: dts: r8a7743: add SYS-DMAC support
From: Sergei Shtylyov @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1746536.qobnGdHRfV@wasted.cogentembedded.com>
Describe SYS-DMAC0/1 in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 6:
- refreshed the patch.
Changes in version 5:
- refreshed the patch.
Changes in version 4:
- refreshed the patch.
Changes in version 3:
- resolved a reject;
- updated the "clocks" properties for the CPG/MSSR driver.
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7743.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -93,6 +93,70 @@
compatible = "renesas,r8a7743-rst";
reg = <0 0xe6160000 0 0x100>;
};
+
+ dmac0: dma-controller at e6700000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller at e6720000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
};
/* External root clock */
^ permalink raw reply
* [Bug] ARM: mxs: STI: console can't wake up from freeze
From: Stefan Wahren @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161031161700.GH1041@n2100.armlinux.org.uk>
> Russell King - ARM Linux <linux@armlinux.org.uk> hat am 31. Oktober 2016 um
> 17:17 geschrieben:
>
>
> On Sat, Oct 29, 2016 at 01:44:14PM +0200, Stefan Wahren wrote:
> > unfortunately not:
> >
> > Setting: no_console_suspend not in cmdline, Debug UART wakeup source enabled
> >
> > echo mem > /sys/power/state
> >
> > Result: Able to wakeup via Debug UART
> > Expected result: Able to wakeup via Debug UART
> >
> > ---
> >
> > Setting: no_console_suspend not in cmdline, Debug UART wakeup source enabled
> >
> > echo freeze > /sys/power/state
> >
> > Result: Unable to wakeup via Debug UART (no hung task warning)
> > Expected result: Able to wakeup via Debug UART
>
> Okay - I know that certain actions are bypassed when no_console_suspend
> is set, which has detrimental effects on some ARM platforms, so it was
> worth testing - iirc, working no_console_suspend is reliant on the boot
> loader re-setting up the serial port after its lost state.
>
I also made the basic PM debugging tests with the available options for pm_test:
freezer: suspend and resume as expected
devices: suspend and resume as expected
platform: suspend and resume as expected
Since these tests use a clock to wakeup, i assume my issue is related to the
debug UART and its required components.
Btw the irqchip/irq-mxs.c doesn't implement neither the irq_set_wake or the
syscore_ops. Could this be the problem?
FWIW here are the debug outputs for "echo mem > /sys/power/state" (no hang) and
"echo freeze > /sys/power/state" (hang). I need to mention that after adding
initcall_debug to the cmdline "echo mem > /sys/power/state" the system wakeups
immediately after the suspend.
echo mem > /sys/power/state
[ 62.010376] PM: Syncing filesystems ... [ 65.607842] done.
[ 65.660964] Freezing user space processes ... (elapsed 0.007 seconds) done.
[ 65.676976] Freezing remaining freezable tasks ... (elapsed 0.003 seconds)
done.
[ 65.697881] calling mmc0:0007+ @ 93, parent: mmc0
[ 65.704356] call mmc0:0007+ returned 0 after 1532 usecs
[ 65.710605] calling snd-soc-dummy+ @ 385, parent: platform
[ 65.716472] call snd-soc-dummy+ returned 0 after 16 usecs
[ 65.722356] calling duckbill:red:status+ @ 385, parent: leds
[ 65.728360] call duckbill:red:status+ returned 0 after 22 usecs
[ 65.734417] calling duckbill:green:status+ @ 385, parent: leds
[ 65.740564] call duckbill:green:status+ returned 0 after 18 usecs
[ 65.747329] calling stmp3xxx_rtc_wdt+ @ 385, parent: 80056000.rtc
[ 65.753600] call stmp3xxx_rtc_wdt+ returned 0 after 13 usecs
[ 65.759529] calling rtc0+ @ 385, parent: 80056000.rtc
[ 65.765084] call rtc0+ returned 0 after 212 usecs
[ 65.771252] calling usb1+ @ 93, parent: ci_hdrc.0
[ 65.805743] call usb1+ returned 0 after 28753 usecs
[ 65.811994] calling ci_hdrc.0+ @ 385, parent: 80080000.usb
[ 65.819188] call ci_hdrc.0+ returned 0 after 1319 usecs
[ 65.824875] calling 800f0000.etherne:00+ @ 385, parent: 800f0000.etherne
[ 65.832856] call 800f0000.etherne:00+ returned 0 after 1072 usecs
[ 65.839345] calling Fixed MDIO bus.0+ @ 385, parent: platform
[ 65.845388] call Fixed MDIO bus.0+ returned 0 after 13 usecs
[ 65.851432] calling alarmtimer+ @ 385, parent: platform
[ 65.858186] call alarmtimer+ returned 0 after 1193 usecs
[ 65.868024] calling leds+ @ 385, parent: soc0
[ 65.872567] call leds+ returned 0 after 12 usecs
[ 65.877472] calling regulators:regulator at 0+ @ 385, parent: regulators
[ 65.884088] call regulators:regulator at 0+ returned 0 after 14 usecs
[ 65.890534] calling regulators+ @ 385, parent: soc0
[ 65.895699] call regulators+ returned 0 after 14 usecs
[ 65.900971] calling iio-hwmon+ @ 385, parent: soc0
[ 65.906096] call iio-hwmon+ returned 0 after 15 usecs
[ 65.912643] calling 800f0000.ethernet+ @ 385, parent: 80080000.ahb
[ 65.920952] call 800f0000.ethernet+ returned 0 after 1743 usecs
[ 65.927181] calling 80080000.usb+ @ 385, parent: 80080000.ahb
[ 65.933350] call 80080000.usb+ returned 0 after 243 usecs
[ 65.939063] calling 80080000.ahb+ @ 385, parent: soc0
[ 65.944289] call 80080000.ahb+ returned 0 after 14 usecs
[ 65.949867] calling 8007c000.usbphy+ @ 385, parent: 80040000.apbx
[ 65.956248] call 8007c000.usbphy+ returned 0 after 15 usecs
[ 65.961960] calling 80074000.serial+ @ 385, parent: 80040000.apbx
[ 65.968832] call 80074000.serial+ returned 0 after 472 usecs
[ 65.974888] calling 80068000.timrot+ @ 385, parent: 80040000.apbx
[ 65.981162] call 80068000.timrot+ returned 0 after 13 usecs
[ 65.987008] calling 80056000.rtc+ @ 385, parent: 80040000.apbx
[ 65.993012] call 80056000.rtc+ returned 0 after 14 usecs
[ 65.998601] calling 80040000.apbx+ @ 385, parent: 80000000.apb
[ 66.004720] call 80040000.apbx+ returned 0 after 13 usecs
[ 66.010259] calling 8002c000.ocotp+ @ 385, parent: 80000000.apbh
[ 66.016565] call 8002c000.ocotp+ returned 0 after 14 usecs
[ 66.022191] calling 80028000.dcp+ @ 385, parent: 80000000.apbh
[ 66.028322] call 80028000.dcp+ returned 0 after 13 usecs
[ 66.033833] calling 80024000.dma-apbx+ @ 385, parent: 80000000.apbh
[ 66.040396] call 80024000.dma-apbx+ returned 0 after 14 usecs
[ 66.046474] calling 80018000.pinctrl:gpio at 4+ @ 385, parent: 80018000.pinctrl
[ 66.053695] call 80018000.pinctrl:gpio at 4+ returned 0 after 15 usecs
[ 66.060303] calling 80018000.pinctrl:gpio at 3+ @ 385, parent: 80018000.pinctrl
[ 66.067640] call 80018000.pinctrl:gpio at 3+ returned 0 after 14 usecs
[ 66.074124] calling 80018000.pinctrl:gpio at 2+ @ 385, parent: 80018000.pinctrl
[ 66.081478] call 80018000.pinctrl:gpio at 2+ returned 0 after 13 usecs
[ 66.088068] calling 80018000.pinctrl:gpio at 1+ @ 385, parent: 80018000.pinctrl
[ 66.095426] call 80018000.pinctrl:gpio at 1+ returned 0 after 14 usecs
[ 66.101917] calling 80018000.pinctrl:gpio at 0+ @ 385, parent: 80018000.pinctrl
[ 66.109292] call 80018000.pinctrl:gpio at 0+ returned 0 after 14 usecs
[ 66.115828] calling 80018000.pinctrl+ @ 385, parent: 80000000.apbh
[ 66.122177] call 80018000.pinctrl+ returned 0 after 13 usecs
[ 66.128103] calling 80010000.ssp+ @ 385, parent: 80000000.apbh
[ 66.134173] call 80010000.ssp+ returned 0 after 73 usecs
[ 66.139808] calling 80004000.dma-apbh+ @ 385, parent: 80000000.apbh
[ 66.146361] call 80004000.dma-apbh+ returned 0 after 14 usecs
[ 66.152266] calling 80000000.apbh+ @ 385, parent: 80000000.apb
[ 66.158402] call 80000000.apbh+ returned 0 after 14 usecs
[ 66.163947] calling 80000000.apb+ @ 385, parent: soc0
[ 66.169297] call 80000000.apb+ returned 0 after 13 usecs
[ 66.174993] calling reg-dummy+ @ 385, parent: platform
[ 66.180303] call reg-dummy+ returned 0 after 14 usecs
[ 66.185780] PM: suspend of devices complete after 491.347 msecs
[ 66.199593] PM: late suspend of devices complete after 7.795 msecs
[ 66.213823] PM: noirq suspend of devices complete after 7.810 msecs
[ 66.220384] PM: Calling sched_clock_suspend+0x0/0x30
[ 66.225386] PM: Calling timekeeping_suspend+0x0/0x248
[ 66.225386] PM: Calling irq_gc_suspend+0x0/0x6c
[ 66.225386] PM: Calling fw_suspend+0x0/0x14
[ 66.225386] PM: Calling cpu_pm_suspend+0x0/0x18
[ 66.225386] PM: Calling cpu_pm_resume+0x0/0x10
[ 66.225386] PM: Calling irq_gc_resume+0x0/0x68
[ 66.225386] PM: Calling irq_pm_syscore_resume+0x0/0x8
[ 66.225386] PM: Calling timekeeping_resume+0x0/0x388
[ 66.225386] PM: Calling sched_clock_resume+0x0/0x50
[ 66.235681] PM: noirq resume of devices complete after 9.970 msecs
[ 66.249836] PM: early resume of devices complete after 6.354 msecs
[ 66.257903] calling reg-dummy+ @ 385, parent: platform
[ 66.263393] call reg-dummy+ returned 0 after 14 usecs
[ 66.269048] calling 80000000.apb+ @ 385, parent: soc0
[ 66.274433] call 80000000.apb+ returned 0 after 14 usecs
[ 66.279854] calling 80000000.apbh+ @ 385, parent: 80000000.apb
[ 66.285986] call 80000000.apbh+ returned 0 after 13 usecs
[ 66.291488] calling 80004000.dma-apbh+ @ 385, parent: 80000000.apbh
[ 66.298050] call 80004000.dma-apbh+ returned 0 after 13 usecs
[ 66.304032] calling 80010000.ssp+ @ 385, parent: 80000000.apbh
[ 66.310100] call 80010000.ssp+ returned 0 after 71 usecs
[ 66.315901] calling mmc0:0007+ @ 390, parent: mmc0
[ 66.322084] call mmc0:0007+ returned 0 after 1186 usecs
[ 66.327863] calling 80018000.pinctrl+ @ 385, parent: 80000000.apbh
[ 66.334390] call 80018000.pinctrl+ returned 0 after 14 usecs
[ 66.340292] calling 80018000.pinctrl:gpio at 0+ @ 385, parent: 80018000.pinctrl
[ 66.347660] call 80018000.pinctrl:gpio at 0+ returned 0 after 14 usecs
[ 66.354395] calling 80018000.pinctrl:gpio at 1+ @ 385, parent: 80018000.pinctrl
[ 66.361622] call 80018000.pinctrl:gpio at 1+ returned 0 after 13 usecs
[ 66.368166] calling 80018000.pinctrl:gpio at 2+ @ 385, parent: 80018000.pinctrl
[ 66.375520] call 80018000.pinctrl:gpio at 2+ returned 0 after 13 usecs
[ 66.381932] calling 80018000.pinctrl:gpio at 3+ @ 385, parent: 80018000.pinctrl
[ 66.389309] call 80018000.pinctrl:gpio at 3+ returned 0 after 12 usecs
[ 66.399315] calling 80018000.pinctrl:gpio at 4+ @ 385, parent: 80018000.pinctrl
[ 66.406746] call 80018000.pinctrl:gpio at 4+ returned 0 after 13 usecs
[ 66.413534] calling 80024000.dma-apbx+ @ 385, parent: 80000000.apbh
[ 66.420065] call 80024000.dma-apbx+ returned 0 after 15 usecs
[ 66.426220] calling 80028000.dcp+ @ 385, parent: 80000000.apbh
[ 66.432320] call 80028000.dcp+ returned 0 after 14 usecs
[ 66.438018] calling 8002c000.ocotp+ @ 385, parent: 80000000.apbh
[ 66.444341] call 8002c000.ocotp+ returned 0 after 14 usecs
[ 66.449936] calling 80040000.apbx+ @ 385, parent: 80000000.apb
[ 66.456067] call 80040000.apbx+ returned 0 after 13 usecs
[ 66.461564] calling 80056000.rtc+ @ 385, parent: 80040000.apbx
[ 66.467729] call 80056000.rtc+ returned 0 after 23 usecs
[ 66.473447] calling 80068000.timrot+ @ 385, parent: 80040000.apbx
[ 66.479804] call 80068000.timrot+ returned 0 after 14 usecs
[ 66.485778] calling 80074000.serial+ @ 385, parent: 80040000.apbx
[ 66.492439] call 80074000.serial+ returned 0 after 303 usecs
[ 66.498644] calling 8007c000.usbphy+ @ 385, parent: 80040000.apbx
[ 66.505118] call 8007c000.usbphy+ returned 0 after 14 usecs
[ 66.511030] calling 80080000.ahb+ @ 385, parent: soc0
[ 66.516461] call 80080000.ahb+ returned 0 after 13 usecs
[ 66.522156] calling 80080000.usb+ @ 385, parent: 80080000.ahb
[ 66.528349] call 80080000.usb+ returned 0 after 72 usecs
[ 66.535063] calling 800f0000.ethernet+ @ 385, parent: 80080000.ahb
[ 66.545846] call 800f0000.ethernet+ returned 0 after 4310 usecs
[ 66.552190] calling iio-hwmon+ @ 385, parent: soc0
[ 66.557331] call iio-hwmon+ returned 0 after 13 usecs
[ 66.562680] calling regulators+ @ 385, parent: soc0
[ 66.567874] call regulators+ returned 0 after 13 usecs
[ 66.573247] calling regulators:regulator at 0+ @ 385, parent: regulators
[ 66.580022] call regulators:regulator at 0+ returned 0 after 15 usecs
[ 66.587259] calling leds+ @ 385, parent: soc0
[ 66.591800] call leds+ returned 0 after 15 usecs
[ 66.598846] calling alarmtimer+ @ 385, parent: platform
[ 66.604503] call alarmtimer+ returned 0 after 23 usecs
[ 66.610176] calling Fixed MDIO bus.0+ @ 385, parent: platform
[ 66.616252] call Fixed MDIO bus.0+ returned 0 after 12 usecs
[ 66.622674] calling 800f0000.etherne:00+ @ 385, parent: 800f0000.etherne
[ 66.630092] call 800f0000.etherne:00+ returned 0 after 387 usecs
[ 66.636354] calling ci_hdrc.0+ @ 385, parent: 80080000.usb
[ 66.647310] call ci_hdrc.0+ returned 0 after 5048 usecs
[ 66.652757] calling usb1+ @ 391, parent: ci_hdrc.0
[ 66.658084] calling rtc0+ @ 385, parent: 80056000.rtc
[ 66.664251] call usb1+ returned 0 after 6224 usecs
[ 66.670162] call rtc0+ returned 0 after 6462 usecs
[ 66.675361] calling stmp3xxx_rtc_wdt+ @ 385, parent: 80056000.rtc
[ 66.681633] call stmp3xxx_rtc_wdt+ returned 0 after 13 usecs
[ 66.687854] calling duckbill:green:status+ @ 385, parent: leds
[ 66.694074] call duckbill:green:status+ returned 0 after 22 usecs
[ 66.700951] calling duckbill:red:status+ @ 385, parent: leds
[ 66.706956] call duckbill:red:status+ returned 0 after 20 usecs
[ 66.713180] calling snd-soc-dummy+ @ 385, parent: platform
[ 66.718969] call snd-soc-dummy+ returned 0 after 13 usecs
[ 66.725823] PM: resume of devices complete after 469.549 msecs
[ 66.739348] Restarting tasks ... [ 66.783319] done.
echo freeze > /sys/power/state
[ 189.939554] PM: Syncing filesystems ... [ 191.084732] done.
[ 191.090589] Freezing user space processes ... [ 191.100074] (elapsed 0.004
seconds) done.
[ 191.104444] Freezing remaining freezable tasks ... (elapsed 0.002 seconds)
done.
[ 191.121118] calling mmc0:0007+ @ 391, parent: mmc0
[ 191.126437] calling snd-soc-dummy+ @ 385, parent: platform
[ 191.132104] call snd-soc-dummy+ returned 0 after 14 usecs
[ 191.139007] call mmc0:0007+ returned 0 after 12458 usecs
[ 191.144846] calling duckbill:red:status+ @ 385, parent: leds
[ 191.150693] call duckbill:red:status+ returned 0 after 20 usecs
[ 191.156887] calling duckbill:green:status+ @ 385, parent: leds
[ 191.163035] call duckbill:green:status+ returned 0 after 20 usecs
[ 191.169680] calling stmp3xxx_rtc_wdt+ @ 385, parent: 80056000.rtc
[ 191.176097] call stmp3xxx_rtc_wdt+ returned 0 after 14 usecs
[ 191.181889] calling rtc0+ @ 385, parent: 80056000.rtc
[ 191.187289] call rtc0+ returned 0 after 58 usecs
[ 191.193635] calling usb1+ @ 391, parent: ci_hdrc.0
[ 191.223649] call usb1+ returned 0 after 24451 usecs
[ 191.228801] calling ci_hdrc.0+ @ 385, parent: 80080000.usb
[ 191.234867] call ci_hdrc.0+ returned 0 after 249 usecs
[ 191.240183] calling 800f0000.etherne:00+ @ 385, parent: 800f0000.etherne
[ 191.247628] call 800f0000.etherne:00+ returned 0 after 428 usecs
[ 191.254012] calling Fixed MDIO bus.0+ @ 385, parent: platform
[ 191.259933] call Fixed MDIO bus.0+ returned 0 after 12 usecs
[ 191.266098] calling alarmtimer+ @ 385, parent: platform
[ 191.271513] call alarmtimer+ returned 0 after 31 usecs
[ 191.280964] calling leds+ @ 385, parent: soc0
[ 191.285646] call leds+ returned 0 after 15 usecs
[ 191.290408] calling regulators:regulator at 0+ @ 385, parent: regulators
[ 191.297152] call regulators:regulator at 0+ returned 0 after 14 usecs
[ 191.303602] calling regulators+ @ 385, parent: soc0
[ 191.308648] call regulators+ returned 0 after 13 usecs
[ 191.314044] calling iio-hwmon+ @ 385, parent: soc0
[ 191.319008] call iio-hwmon+ returned 0 after 13 usecs
[ 191.324325] calling 800f0000.ethernet+ @ 385, parent: 80080000.ahb
[ 191.330828] call 800f0000.ethernet+ returned 0 after 152 usecs
[ 191.336942] calling 80080000.usb+ @ 385, parent: 80080000.ahb
[ 191.343135] call 80080000.usb+ returned 0 after 62 usecs
[ 191.348600] calling 80080000.ahb+ @ 385, parent: soc0
[ 191.353949] call 80080000.ahb+ returned 0 after 13 usecs
[ 191.359397] calling 8007c000.usbphy+ @ 385, parent: 80040000.apbx
[ 191.365789] call 8007c000.usbphy+ returned 0 after 14 usecs
[ 191.371504] calling 80074000.serial+ @ 385, parent: 80040000.apbx
[ 191.377944] call 80074000.serial+ returned 0 after 51 usecs
[ 191.383782] calling 80068000.timrot+ @ 385, parent: 80040000.apbx
[ 191.390043] call 80068000.timrot+ returned 0 after 13 usecs
[ 191.395885] calling 80056000.rtc+ @ 385, parent: 80040000.apbx
[ 191.401889] call 80056000.rtc+ returned 0 after 14 usecs
[ 191.407472] calling 80040000.apbx+ @ 385, parent: 80000000.apb
[ 191.413607] call 80040000.apbx+ returned 0 after 12 usecs
[ 191.419146] calling 8002c000.ocotp+ @ 385, parent: 80000000.apbh
[ 191.425447] call 8002c000.ocotp+ returned 0 after 13 usecs
[ 191.431064] calling 80028000.dcp+ @ 385, parent: 80000000.apbh
[ 191.437198] call 80028000.dcp+ returned 0 after 13 usecs
[ 191.442706] calling 80024000.dma-apbx+ @ 385, parent: 80000000.apbh
[ 191.449272] call 80024000.dma-apbx+ returned 0 after 14 usecs
[ 191.455345] calling 80018000.pinctrl:gpio at 4+ @ 385, parent: 80018000.pinctrl
[ 191.462570] call 80018000.pinctrl:gpio at 4+ returned 0 after 14 usecs
[ 191.469179] calling 80018000.pinctrl:gpio at 3+ @ 385, parent: 80018000.pinctrl
[ 191.476533] call 80018000.pinctrl:gpio at 3+ returned 0 after 13 usecs
[ 191.483150] calling 80018000.pinctrl:gpio at 2+ @ 385, parent: 80018000.pinctrl
[ 191.490374] call 80018000.pinctrl:gpio at 2+ returned 0 after 15 usecs
[ 191.496983] calling 80018000.pinctrl:gpio at 1+ @ 385, parent: 80018000.pinctrl
[ 191.504340] call 80018000.pinctrl:gpio at 1+ returned 0 after 14 usecs
[ 191.510828] calling 80018000.pinctrl:gpio at 0+ @ 385, parent: 80018000.pinctrl
[ 191.518177] call 80018000.pinctrl:gpio at 0+ returned 0 after 13 usecs
[ 191.524725] calling 80018000.pinctrl+ @ 385, parent: 80000000.apbh
[ 191.531076] call 80018000.pinctrl+ returned 0 after 14 usecs
[ 191.536998] calling 80010000.ssp+ @ 385, parent: 80000000.apbh
[ 191.543197] call 80010000.ssp+ returned 0 after 72 usecs
[ 191.548705] calling 80004000.dma-apbh+ @ 385, parent: 80000000.apbh
[ 191.555270] call 80004000.dma-apbh+ returned 0 after 14 usecs
[ 191.561178] calling 80000000.apbh+ @ 385, parent: 80000000.apb
[ 191.567310] call 80000000.apbh+ returned 0 after 13 usecs
[ 191.573063] calling 80000000.apb+ @ 385, parent: soc0
[ 191.578290] call 80000000.apb+ returned 0 after 11 usecs
[ 191.583997] calling reg-dummy+ @ 385, parent: platform
[ 191.589308] call reg-dummy+ returned 0 after 12 usecs
[ 191.594782] PM: suspend of devices complete after 474.663 msecs
[ 191.608635] PM: late suspend of devices complete after 7.831 msecs
[ 191.622637] PM: noirq suspend of devices complete after 7.569 msecs
[ 366.696043] INFO: task ext4lazyinit:70 blocked for more than 120 seconds.
[ 366.703046] Not tainted 4.9.0-rc1 #7
[ 366.707188] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this
message.
[ 366.715161] ext4lazyinit D c05aa6ac 0 70 2 0x00000000
[ 366.721713] [<c05aa6ac>] (__schedule) from [<c05aafb8>] (schedule+0x3c/0xbc)
[ 366.728972] [<c05aafb8>] (schedule) from [<c05aee38>]
(schedule_timeout+0x23c/0x3d8)
[ 366.736917] [<c05aee38>] (schedule_timeout) from [<c05aa398>]
(io_schedule_timeout+0xb8/0x13c)
[ 366.745721] [<c05aa398>] (io_schedule_timeout) from [<c05ab9d8>]
(T.1434+0xac/0x12c)
[ 366.753671] [<c05ab9d8>] (T.1434) from [<c02c7668>]
(submit_bio_wait+0x50/0x68)
[ 366.761078] [<c02c7668>] (submit_bio_wait) from [<c02d9a58>]
(blkdev_issue_zeroout+0x174/0x1ec)
[ 366.769984] [<c02d9a58>] (blkdev_issue_zeroout) from [<c0196e4c>]
(ext4_init_inode_table+0x1ac/0x3b0)
[ 366.779410] [<c0196e4c>] (ext4_init_inode_table) from [<c01ba770>]
(ext4_lazyinit_thread+0x280/0x398)
[ 366.788803] [<c01ba770>] (ext4_lazyinit_thread) from [<c003bce4>]
(kthread+0xc4/0xe0)
[ 366.796828] [<c003bce4>] (kthread) from [<c000a34c>]
(ret_from_fork+0x14/0x28)
[ 366.804200]
[ 366.804200] Showing all locks held in the system:
[ 366.810465] 2 locks held by khungtaskd/10:
[ 366.814707] #0: [ 366.816500] (
rcu_read_lock[ 366.819360] ){......}
, at: [ 366.822236] [<c0093a10>] watchdog+0xb4/0x61c
[ 366.826656] #1: [ 366.828450] (
tasklist_lock[ 366.831312] ){.+.+..}
, at: [ 366.834320] [<c0051dbc>] debug_show_all_locks+0x28/0x1bc
[ 366.839701] 4 locks held by ext4lazyinit/70:
[ 366.844107] #0: [ 366.845897] (
&type->s_umount_key[ 366.849280] #22
){++++++}[ 366.851866] , at:
[ 366.854044] [<c01ba5c4>] ext4_lazyinit_thread+0xd4/0x398
[ 366.859400] #1: [ 366.861178] (
sb_writers[ 366.863897] #3
){.+.+.+}[ 366.866412] , at:
[ 366.868475] [<c01ba5dc>] ext4_lazyinit_thread+0xec/0x398
[ 366.873925] #2: [ 366.875716] (
jbd2_handle[ 366.878405] ){++++..}
, at: [ 366.881292] [<c01f661c>] start_this_handle+0xec/0x404
[ 366.886492] #3: [ 366.888284] (
&meta_group_info[i]->alloc_sem[ 366.892620] ){++++..}
, at: [ 366.895624] [<c0196d58>] ext4_init_inode_table+0xb8/0x3b0
[ 366.901093] 4 locks held by bash/385:
[ 366.904895] #0: [ 366.906686] (
sb_writers[ 366.909288] #4
){.+.+.+}[ 366.911787] , at:
[ 366.913972] [<c011f7d4>] vfs_write+0x194/0x1a4
[ 366.918456] #1: [ 366.920234] (
&of->mutex[ 366.922824] ){+.+.+.}
, at: [ 366.925940] [<c019029c>] kernfs_fop_write+0xc0/0x1d0
[ 366.930942] #2: [ 366.932714] (
s_active[ 366.935265] #43
){.+.+.+}[ 366.937864] , at:
[ 366.939927] [<c01902a4>] kernfs_fop_write+0xc8/0x1d0
[ 366.945029] #3: [ 366.946818] (
pm_mutex[ 366.949242] ){+.+.+.}
, at: [ 366.952111] [<c005b7e4>] pm_suspend+0x90/0x81c
[ 366.956697]
[ 366.958229] =============================================
^ permalink raw reply
* [PATCH v6 1/7] ARM: dts: r8a7743: initial SoC device tree
From: Sergei Shtylyov @ 2016-10-31 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1746536.qobnGdHRfV@wasted.cogentembedded.com>
The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 6:
- corrected the "reg" prop of the RST node;
- removed leading zero from the SYSC "reg" property's cell;
- fixed the typo in "overriden".
Changes in version 5:
- added the RST device node, updated the patch description accordingly.
Changes in version 4:
- removed the CPU1 node, updated the patch description accordingly;
- reformatted the "interrupts" props of the GIC/timer device nodes;
- added Geert's tag.
Changes in version 3:
- changed the R8A7743 clock header #include;
- replaced the multiple clock nodes with the single CPG node, updated the
"clocks" property in the CPU0 node, updated the patch description.
Changes in version 2:
- added the IRQC and Ether clocks.
arch/arm/boot/dts/r8a7743.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
+#include <dt-bindings/power/r8a7743-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7743";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
+ power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ L2_CA15: cache-controller at 0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7743_PD_CA15_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller at f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller at e6150000 {
+ compatible = "renesas,r8a7743-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller at e6180000 {
+ compatible = "renesas,r8a7743-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
+ rst: reset-controller at e6160000 {
+ compatible = "renesas,r8a7743-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
^ permalink raw reply
* [PATCH] staging: vc04_services: setup DMA and coherent mask
From: Michael Zoran @ 2016-10-31 19:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477939258.30971.1.camel@crowfest.net>
On Mon, 2016-10-31 at 11:40 -0700, Michael Zoran wrote:
> On Mon, 2016-10-31 at 11:36 -0700, Eric Anholt wrote:
> > Michael Zoran <mzoran@crowfest.net> writes:
> >
> > > Setting the DMA mask is optional on 32 bit but
> > > is mandatory on 64 bit.??Set the DMA mask and coherent
> > > to force all DMA to be in the 32 bit address space.
> > >
> > > This is considered a "good practice" and most drivers
> > > already do this.
> > >
> > > Signed-off-by: Michael Zoran <mzoran@crowfest.net>
> > > ---
> > > ?.../staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c |
> > > 10 ++++++++++
> > > ?1 file changed, 10 insertions(+)
> > >
> > > diff --git
> > > a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_ar
> > > m.
> > > c
> > > b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_ar
> > > m.
> > > c
> > > index a5afcc5..6fa2b5a 100644
> > > ---
> > > a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_ar
> > > m.
> > > c
> > > +++
> > > b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_ar
> > > m.
> > > c
> > > @@ -97,6 +97,16 @@ int vchiq_platform_init(struct platform_device
> > > *pdev, VCHIQ_STATE_T *state)
> > > ? int slot_mem_size, frag_mem_size;
> > > ? int err, irq, i;
> > > ?
> > > + /*
> > > + ?* Setting the DMA mask is necessary in the 64 bit
> > > environment.
> > > + ?* It isn't necessary in a 32 bit environment but is
> > > considered
> > > + ?* a good practice.
> > > + ?*/
> > > + err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
> >
> > I think a better comment here would be simply:
> >
> > /* VCHI messages between the CPU and firmware use 32-bit bus
> > addresses. */
> >
> > explaining why the value is chosen (once you know that the 32 bit
> > restriction exists, reporting it is obviously needed).??I'm
> > curious,
> > though: what failed when you didn't set it?
> >
>
> The comment is easy to change.
>
> I don't have the log available ATM, but if I remember the DMA API's
> bugcheck the first time that are used.??
>
> I think this was a policy decision or something because the
> information
> should be available in the dma-ranges.
>
> If it's important, I can setup a test again without the change and e-
> mail the logs.
>
> If you look at the DWC2 driver you will see that it also sets this
> mask.
OK, I'm begging to understand this. It appears the architecture
specific paths are very different.
In arm the mask and coherent is set to DMA_BIT_MASK(32) in mm/dma-
mapping.c the first time the dma APIs are used. On arm64, it appears
this variable is uninitialized and will contain random crude.
Like I said, I don't know if this is a policy decision or if it just
slipped through the cracks.
arch/arm/mm/dma-mapping.c(Note the call to get_coherent_dma_mask(dev))
static u64 get_coherent_dma_mask(struct device *dev)
{
u64 mask = (u64)DMA_BIT_MASK(32);
if (dev) {
mask = dev->coherent_dma_mask;
/*
?* Sanity check the DMA mask - it must be non-zero, and
?* must be able to be satisfied by a DMA allocation.
?*/
if (mask == 0) {
dev_warn(dev, "coherent DMA mask is unset\n");
return 0;
}
if (!__dma_supported(dev, mask, true))
return 0;
}
return mask;
}
static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t
*handle,
?gfp_t gfp, pgprot_t prot, bool is_coherent,
?unsigned long attrs, const void *caller)
{
u64 mask = get_coherent_dma_mask(dev);
struct page *page = NULL;
void *addr;
bool allowblock, cma;
struct arm_dma_buffer *buf;
struct arm_dma_alloc_args args = {
.dev = dev,
.size = PAGE_ALIGN(size),
.gfp = gfp,
.prot = prot,
.caller = caller,
.want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) ==
0),
.coherent_flag = is_coherent ? COHERENT : NORMAL,
};
arch/arm64/include/asm/dma-mapping.h
/* do not use this function in a driver */
static inline bool is_device_dma_coherent(struct device *dev)
{
if (!dev)
return false;
return dev->archdata.dma_coherent;
}
arch/arm64/mm/dma-mapping.c(Note no call to get_coherent_dma_mask)
static void *__dma_alloc(struct device *dev, size_t size,
?dma_addr_t *dma_handle, gfp_t flags,
?unsigned long attrs)
{
struct page *page;
void *ptr, *coherent_ptr;
bool coherent = is_device_dma_coherent(dev);
pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, false);
size = PAGE_ALIGN(size);
if (!coherent && !gfpflags_allow_blocking(flags)) {
struct page *page = NULL;
void *addr = __alloc_from_pool(size, &page, flags);
if (addr)
*dma_handle = phys_to_dma(dev,
page_to_phys(page));
return addr;
}
ptr = __dma_alloc_coherent(dev, size, dma_handle, flags,
attrs);
^ permalink raw reply
* [PATCH v6 0/7] Add R8A7743/SK-RZG1M board support
From: Sergei Shtylyov @ 2016-10-31 19:52 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
Here's the set of 7 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161031-v4.9-rc3' tag. I'm adding the device tree support for
the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board
seems identical to the R8A7791/Porter board. The device tree patches depend on
the R8A7743 CPG/MSSR driver series in order to compile and work. Already merged
patches from this series won't be re-posted.
[1/7] ARM: dts: r8a7743: initial SoC device tree
[2/7] ARM: dts: r8a7743: add SYS-DMAC support
[3/7] ARM: dts: r8a7743: add [H]SCIF{A|B} support
[4/7] ARM: dts: r8a7743: add Ether support
[5/7] ARM: dts: r8a7743: add IRQC support
[6/7] ARM: dts: sk-rzg1m: initial device tree
[7/7] ARM: dts: sk-rzg1m: add Ether support
WBR, Sergei
^ permalink raw reply
* [PATCH] arm64: errata: Check for --fix-cortex-a53-843419 and --fix-cortex-a53
From: Markus Mayer @ 2016-10-31 19:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Markus Mayer <mmayer@broadcom.com>
The new errata check leads to a warning with some older versions of the
linker that do know how to work around the errata, but still use the
original name of the command line option: --fix-cortex-a53. The commit
in question that changed the name of the option can be found at [1].
It looks like only "gold" is affected by this rename. Traditional "ld"
isn't. (There, the argument was always called --fix-cortex-a53-843419.)
To allow older versions of gold to properly handle the erratum if they
can, check whether ld supports the old name of this option in addition
to checking the new one.
[1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;h=7a2a1c793578a8468604e661dda025ecb8d0bd20;hp=cfbf0e3c5b637d66b2b1aeadecae9c187b825b2f
Signed-off-by: Markus Mayer <mmayer@broadcom.com>
---
Using the change proposed here, things work for me as expected:
$ aarch64-linux-ld -v
GNU ld (GNU Binutils) Linaro 2014.11-2 2.24.0.20141017
$ grep fix-cortex aarch64.log
/bin/bash scripts/link-vmlinux.sh aarch64-linux-ld -EL -p --no-undefined
-X --fix-cortex-a53 --build-id ; true
+ aarch64-linux-ld -EL -p --no-undefined -X --fix-cortex-a53 --build-id -o
.tmp_vmlinux1 -T ./arch/arm64/kernel/vmlinux.lds arch/arm64/kernel/head.o
init/built-in.o --start-group usr/built-in.o arch/arm64/kernel/built-in.o
arch/arm64/mm/built-in.o arch/arm64/net/built-in.o arch/arm64/kvm/built-in.o
arch/arm64/xen/built-in.o arch/arm64/crypto/built-in.o
./drivers/firmware/efi/libstub/lib.a kernel/built-in.o certs/built-in.o
mm/built-in.o fs/built-in.o ipc/built-in.o security/built-in.o
crypto/built-in.o block/built-in.o arch/arm64/lib/lib.a lib/lib.a
arch/arm64/lib/built-in.o lib/built-in.o drivers/built-in.o sound/built-in.o
firmware/built-in.o net/built-in.o virt/built-in.o --end-group
[...]
arch/arm64/Makefile | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index ab51aed..231ba69 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -20,7 +20,13 @@ endif
ifeq ($(CONFIG_ARM64_ERRATUM_843419),y)
ifeq ($(call ld-option, --fix-cortex-a53-843419),)
-$(warning ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum)
+ ifeq ($(call ld-option, --fix-cortex-a53),)
+$(warning ld does not support --fix-cortex-a53-843419 or --fix-cortex-a53; kernel may be susceptible to erratum)
+ else
+# When this option was first introduced, it was called --fix-cortex-a53 in gold.
+# So, let's use that as fall-back if the linker understands it.
+LDFLAGS_vmlinux += --fix-cortex-a53
+ endif
else
LDFLAGS_vmlinux += --fix-cortex-a53-843419
endif
--
2.7.4
^ permalink raw reply related
* [PATCH] dt-bindings: video: exynos7-decon: Remove obsolete samsung,power-domain property
From: Krzysztof Kozlowski @ 2016-10-31 19:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161030204124.wwvv2qfshj7lvggx@rob-hp-laptop>
On Sun, Oct 30, 2016 at 03:41:24PM -0500, Rob Herring wrote:
> On Fri, Oct 21, 2016 at 05:05:54PM +0300, Krzysztof Kozlowski wrote:
> > The samsung,power-domain property is obsolete since commit 0da658704136
> > ("ARM: dts: convert to generic power domain bindings for exynos DT").
> > Replace it with generic one.
> >
> > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> > ---
> > Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> You didn't send this To me, so I assume someone else is applying it.
>
> Acked-by: Rob Herring <robh@kernel.org>
Thanks for the ack. I assumed it will go through the Exynos DRM
subsystem maintainer.
Dear Inki Dae,
Could you pick it up or share your comments?
Best regards,
Krzysztof
^ permalink raw reply
* [RFC PATCH v2 2/5] net: phy: Add Meson GXL Internal PHY driver
From: Andrew Lunn @ 2016-10-31 19:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477932987-27871-3-git-send-email-narmstrong@baylibre.com>
On Mon, Oct 31, 2016 at 05:56:24PM +0100, Neil Armstrong wrote:
> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>
> This PHY seems to only implement some standard registers and need some
> workarounds to provide autoneg values from vendor registers.
>
> Some magic values are currently used to configure the PHY, and this a
> temporary setup until clarification about these registers names and
> registers fields are provided by Amlogic.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> drivers/net/phy/Kconfig | 5 +++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/meson-gxl.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 87 insertions(+)
> create mode 100644 drivers/net/phy/meson-gxl.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 2651c8d..09342b6 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -226,6 +226,11 @@ config DP83867_PHY
> ---help---
> Currently supports the DP83867 PHY.
>
> +config MESON_GXL_PHY
> + tristate "Amlogic Meson GXL Internal PHY"
> + ---help---
> + Currently has a driver for the Amlogic Meson GXL Internal PHY
> +
Hi Neil
Please keep them in alphabetic order. This goes after Marvell.
> config FIXED_PHY
> tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
> depends on PHYLIB
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index e58667d..1511b3e 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
> obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
> obj-$(CONFIG_MICREL_PHY) += micrel.o
> obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
> +obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
> obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
Again, alphabetic order.
Andrew
^ permalink raw reply
* [RFC PATCH v2 1/5] net: mdio-mux-mmioreg: Add support for 16bit and 32bit register sizes
From: Andrew Lunn @ 2016-10-31 18:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477932987-27871-2-git-send-email-narmstrong@baylibre.com>
On Mon, Oct 31, 2016 at 05:56:23PM +0100, Neil Armstrong wrote:
> In order to support PHY switching on Amlogic GXL SoCs, add support for
> 16bit and 32bit registers sizes.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Nice.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH] staging: vc04_services: setup DMA and coherent mask
From: Michael Zoran @ 2016-10-31 18:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87twbsqsb4.fsf@eliezer.anholt.net>
On Mon, 2016-10-31 at 11:36 -0700, Eric Anholt wrote:
> Michael Zoran <mzoran@crowfest.net> writes:
>
> > Setting the DMA mask is optional on 32 bit but
> > is mandatory on 64 bit.??Set the DMA mask and coherent
> > to force all DMA to be in the 32 bit address space.
> >
> > This is considered a "good practice" and most drivers
> > already do this.
> >
> > Signed-off-by: Michael Zoran <mzoran@crowfest.net>
> > ---
> > ?.../staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c |
> > 10 ++++++++++
> > ?1 file changed, 10 insertions(+)
> >
> > diff --git
> > a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.
> > c
> > b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.
> > c
> > index a5afcc5..6fa2b5a 100644
> > ---
> > a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.
> > c
> > +++
> > b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.
> > c
> > @@ -97,6 +97,16 @@ int vchiq_platform_init(struct platform_device
> > *pdev, VCHIQ_STATE_T *state)
> > ? int slot_mem_size, frag_mem_size;
> > ? int err, irq, i;
> > ?
> > + /*
> > + ?* Setting the DMA mask is necessary in the 64 bit
> > environment.
> > + ?* It isn't necessary in a 32 bit environment but is
> > considered
> > + ?* a good practice.
> > + ?*/
> > + err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
>
> I think a better comment here would be simply:
>
> /* VCHI messages between the CPU and firmware use 32-bit bus
> addresses. */
>
> explaining why the value is chosen (once you know that the 32 bit
> restriction exists, reporting it is obviously needed).??I'm curious,
> though: what failed when you didn't set it?
>
The comment is easy to change.
I don't have the log available ATM, but if I remember the DMA API's
bugcheck the first time that are used.
I think this was a policy decision or something because the information
should be available in the dma-ranges.
If it's important, I can setup a test again without the change and e-
mail the logs.
If you look at the DWC2 driver you will see that it also sets this
mask.
^ permalink raw reply
* SMR masking and PCI
From: Robin Murphy @ 2016-10-31 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <HE1PR04MB1321DED0E75BD607BB52889EFFAE0@HE1PR04MB1321.eurprd04.prod.outlook.com>
On 31/10/16 15:57, Diana Madalina Craciun wrote:
> Hi Robin,
>
> On 10/28/2016 07:16 PM, Robin Murphy wrote:
>> Hi Stuart,
>>
>> On 27/10/16 18:10, Stuart Yoder wrote:
>>> Hi Robin,
>>>
>>> A question about how the SMR masking defined in the arm,smmu binding
>>> relates to the PCI iommu-map.
>>>
>>> The #iommu-cells property defines the number of cells an "IOMMU specifier"
>>> takes and 2 is specified to be:
>>>
>>> SMMUs with stream matching support and complex masters
>>> may use a value of 2, where the second cell represents
>>> an SMR mask to combine with the ID in the first cell.
>>>
>>> An iommu-map entry is defined as:
>>>
>>> (rid-base,iommu,iommu-base,length)
>>>
>>> What seems to be currently missing in the iommu-map support is
>>> the possibility the case where #iommu-cells=<2>.
>> Indeed. The bindings have so far rather implicitly assumed the case of
>> #{msi,iommu}-cells = 1, and the code has followed suit.
>>
>>> In this case iommu-base which is an IOMMU specifier should
>>> occupy 2 cells. For example on an ls2085a we would want:
>>>
>>> iommu-map = <0x0 0x6 0x7 0x3ff 0x1
>>> 0x100 0x6 0x8 0x3ff 0x1>;
>>>
>>> ...to mask our stream IDs to 10 bits.
>>>
>>> This should work in theory and comply with the bindings, no?
>> In theory, but now consider:
>>
>> iommu-map = <0x0 0x6 0x7 0x3ff 0x2>;
>>
>> faced with ID 1. The input base is 0, the output base is the 2-cell
>> value 0x7000003ff, so the final ID value should be 0x700000400, right?
>>
>>> of_pci_map_rid() seems to have a hardcoded assumption that
>>> each field in the map is 4 bytes.
>> It does. I guess we should explicitly check that #{msi,iommu}-cells = 1
>> on the target node, and maybe clarify in the binding that that cell
>> should represent a plain linear ID value (although that's pretty obvious
>> from context IMO).
>>
>>> (Also, I guess that msi-map is not affected by this since it
>>> is not related to the IOMMU...but we do have common code
>>> handling both maps.)
>> I'd say it's definitely affected, since #msi-cells can equally be more
>> than 1, and encodes an equally opaque value.
>>
>> It seems pretty reasonable to me that we could extend the binding to
>> accommodate #cells > 1 iff length == 1. Mark?
>>
>> That said, is there a concrete need for this, i.e. do you actually have
>> one device with a single requester ID, which maps to multiple output IDs
>> (which differ only in the upper bits) in a non-predictable manner?
>>
> Actually in the example presented by Stuart, the SMR mask should be
> 0x7C00 (as 0 means that the bit is relevant for matching). So, we have
> the stream ID 7, but the SMMU 500 is appending the TBU bits which makes
> the stream ID look like 0x1407 (TBU 5). In our platform the relationship
> device-TBU is not exposed and documented.
To be fair, that's only the fault of the folks who neglected to document
it (and if this really was the anticipated use-case, possibly also the
integration folks for not simply using the 15-bit Stream ID
configuration and tying any extra bits off). The TBU IDs are still an
undeniable property of the hardware, and not exactly difficult to
discover either. For instance, an LS2085a has been running with the
following map for PCIe for quite some time:
/* Squash 8:5:3 BDF down to 2:2:3 */
iommu-map-mask = <0x031f>;
iommu-map = <0x000 &smmu 0x1400 0x20>,
<0x100 &smmu 0x1420 0x20>,
<0x200 &smmu 0x1440 0x20>,
<0x300 &smmu 0x1460 0x20>;
(with the obligatory hacks to program the PEX LUT entries to match, and
the SATA ICIDs not to alias as they apparently go through the same TBU).
> The SMMU-500 ref manual
> describes this case:
>
> "If the Stream ID presented to each TBU is already unique, and the TBU
> ID addition is not required, then you must ensure that the TBU ID field
> is masked in the SMR."
>
> This is the reason that we need the SMR mask, to mask the TBU bits in
> the SMR.
The PCIe example might be a reason to *want* masking, in order to work
around inadequate documentation, but it certainly isn't a *need*.
Fortunately, Stuart's description of the DPAA complex mastering through
multiple TBUs such that a single device's ICID may map to multiple
stream IDs *is* a compelling justification, because iommu-map isn't
designed for one-to-many mappings. You just need to be very careful the
ICIDs really are completely unique system-wide once you start masking,
or the aliasing will result in weird, and possibly impractical, group
assignment.
Anyway, from the SMMU driver perspective SMR masking does work nicely
now, so I'm happy to review patches to of_pci_map_rid() ;)
Robin.
>
> Thank you,
>
> Diana
>
>
>
^ permalink raw reply
* [PATCH] staging: vc04_services: setup DMA and coherent mask
From: Eric Anholt @ 2016-10-31 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161028171159.23973-1-mzoran@crowfest.net>
Michael Zoran <mzoran@crowfest.net> writes:
> Setting the DMA mask is optional on 32 bit but
> is mandatory on 64 bit. Set the DMA mask and coherent
> to force all DMA to be in the 32 bit address space.
>
> This is considered a "good practice" and most drivers
> already do this.
>
> Signed-off-by: Michael Zoran <mzoran@crowfest.net>
> ---
> .../staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> index a5afcc5..6fa2b5a 100644
> --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> @@ -97,6 +97,16 @@ int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state)
> int slot_mem_size, frag_mem_size;
> int err, irq, i;
>
> + /*
> + * Setting the DMA mask is necessary in the 64 bit environment.
> + * It isn't necessary in a 32 bit environment but is considered
> + * a good practice.
> + */
> + err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
I think a better comment here would be simply:
/* VCHI messages between the CPU and firmware use 32-bit bus addresses. */
explaining why the value is chosen (once you know that the 32 bit
restriction exists, reporting it is obviously needed). I'm curious,
though: what failed when you didn't set it?
> +
> + if (err < 0)
> + return err;
> +
> (void)of_property_read_u32(dev->of_node, "cache-line-size",
> &g_cache_line_size);
> g_fragments_size = 2 * g_cache_line_size;
> --
> 2.10.1
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^ permalink raw reply
* [PATCH] staging: vc04_services: call sg_init_table to init scatterlist
From: Eric Anholt @ 2016-10-31 18:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161028175813.28022-1-mzoran@crowfest.net>
Michael Zoran <mzoran@crowfest.net> writes:
> Call the sg_init_table function to correctly initialze
> the DMA scatterlist. This function is required to completely
> initialize the list and is mandatory if DMA debugging is
> enabled in the build configuration.
>
> One of the purposes of sg_init_table is to set
> the magic "cookie" on each list element and ensure
> the chain end is marked.
>
> Signed-off-by: Michael Zoran <mzoran@crowfest.net>
> ---
> drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> index 6fa2b5a..21b26e5 100644
> --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> @@ -464,6 +464,12 @@ create_pagelist(char __user *buf, size_t count, unsigned short type,
> pagelist->type = type;
> pagelist->offset = offset;
>
> + /*
> + * Initialize the scatterlist so that the magic cookie
> + * is filled if debugging is enabled
> + */
> + sg_init_table(scatterlist, num_pages);
> + /* Now set the pages for each scatterlist */
I feel like the comments don't add much, but either way:
Acked-by: Eric Anholt <eric@anholt.net>
> for (i = 0; i < num_pages; i++)
> sg_set_page(scatterlist + i, pages[i], PAGE_SIZE, 0);
>
> --
> 2.10.1
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^ permalink raw reply
* [PATCH] pinctrl: meson: Add GXL pinctrl definitions
From: Kevin Hilman @ 2016-10-31 18:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477931531-27120-1-git-send-email-narmstrong@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> Add support for the Amlogic Meson GXL SoC, this is a partially complete
> definition only based on the Amlogic Vendor tree.
>
> This definition differs a lot from the GXBB and needs a separate entry.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply
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