* [PATCH v2 07/11] ARM: dts: r8a7745: add Ether support
From: Sergei Shtylyov @ 2016-11-04 21:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2368353.xfo5beGC5E@wasted.cogentembedded.com>
Define the generic R8A7745 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -418,6 +418,18 @@
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ ether: ethernet at ee700000 {
+ compatible = "renesas,ether-r8a7745";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply
* [PATCH v2 08/11] ARM: dts: r8a7745: add IRQC support
From: Sergei Shtylyov @ 2016-11-04 21:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2368353.xfo5beGC5E@wasted.cogentembedded.com>
Describe the IRQC interrupt controller in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller at e61c0000 {
+ compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
^ permalink raw reply
* [PATCH v2 10/11] ARM: dts: sk-rzg1e: initial device tree
From: Sergei Shtylyov @ 2016-11-04 22:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2368353.xfo5beGC5E@wasted.cogentembedded.com>
Add the initial device tree for the R8A7745 SoC based SK-RZG1E board.
The board has 1 debug serial port (SCIF2); include support for it,
so that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/Makefile | 1
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 39 +++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
Index: renesas/arch/arm/boot/dts/Makefile
===================================================================
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Source for the SK-RZG1E board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7745.dtsi"
+
+/ {
+ model = "SK-RZG1E";
+ compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif2 {
+ status = "okay";
+};
^ permalink raw reply
* [PATCH v2 11/11] ARM: dts: sk-rzg1e: add Ether support
From: Sergei Shtylyov @ 2016-11-04 22:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2368353.xfo5beGC5E@wasted.cogentembedded.com>
Define the SK-RZG1E board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
+++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -37,3 +37,16 @@
&scif2 {
status = "okay";
};
+
+ðer {
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ interrupt-parent = <&irqc>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
^ permalink raw reply
* [PATCH] pinctrl: meson: Add GXL pinctrl definitions
From: Linus Walleij @ 2016-11-04 22:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477931531-27120-1-git-send-email-narmstrong@baylibre.com>
On Mon, Oct 31, 2016 at 5:32 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
> Add support for the Amlogic Meson GXL SoC, this is a partially complete
> definition only based on the Amlogic Vendor tree.
>
> This definition differs a lot from the GXBB and needs a separate entry.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Patch applied with Kevin's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 2/3] irqchip: mtk-cirq: Add mediatek mtk-cirq implement
From: Marc Zyngier @ 2016-11-04 22:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478234577.7975.29.camel@mtksdaap41>
On Fri, Nov 04 2016 at 04:42:57 AM, Youlin Pei <youlin.pei@mediatek.com> wrote:
> On Tue, 2016-11-01 at 20:49 +0000, Marc Zyngier wrote:
>> On Tue, Nov 01 2016 at 11:52:01 AM, Youlin Pei <youlin.pei@mediatek.com> wrote:
>> > In Mediatek SOCs, the CIRQ is a low power interrupt controller
>> > designed to works outside MCUSYS which comprises with Cortex-Ax
>> > cores,CCI and GIC.
>> >
>> > The CIRQ controller is integrated in between MCUSYS( include
>> > Cortex-Ax, CCI and GIC ) and interrupt sources as the second
>> > level interrupt controller. The external interrupts which outside
>> > MCUSYS will feed through CIRQ then bypass to GIC. CIRQ can monitors
>> > all edge trigger interupts. When an edge interrupt is triggered,
>> > CIRQ can record the status and generate a pulse signal to GIC when
>> > flush command executed.
>> >
>> > When system enters sleep mode, MCUSYS will be turned off to improve
>> > power consumption, also GIC is power down. The edge trigger interrupts
>> > will be lost in this scenario without CIRQ.
>> >
>> > This commit provides the CIRQ irqchip implement.
>> >
>> > Signed-off-by: Youlin Pei <youlin.pei@mediatek.com>
>> > ---
>> > drivers/irqchip/Makefile | 2 +-
>> > drivers/irqchip/irq-mtk-cirq.c | 262 ++++++++++++++++++++++++++++++++++++++++
>> > 2 files changed, 263 insertions(+), 1 deletion(-)
>> > create mode 100644 drivers/irqchip/irq-mtk-cirq.c
>> >
>> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> > index e4dbfc8..8f33580 100644
>> > --- a/drivers/irqchip/Makefile
>> > +++ b/drivers/irqchip/Makefile
>> > @@ -60,7 +60,7 @@ obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
>> > obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
>> > obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
>> > obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
>> > -obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o
>> > +obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o irq-mtk-cirq.o
>> > obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o
>> > obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o
>> > obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
>> > diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
>> > new file mode 100644
>> > index 0000000..fc43ef3
>> > --- /dev/null
>> > +++ b/drivers/irqchip/irq-mtk-cirq.c
>> > @@ -0,0 +1,262 @@
>> > +/*
>> > + * Copyright (c) 2016 MediaTek Inc.
>> > + * Author: Youlin.Pei <youlin.pei@mediatek.com>
>> > + *
>> > + * This program is free software; you can redistribute it and/or modify
>> > + * it under the terms of the GNU General Public License version 2 as
>> > + * published by the Free Software Foundation.
>> > + *
>> > + * This program is distributed in the hope that it will be useful,
>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> > + * GNU General Public License for more details.
>> > + */
>> > +
>> > +#include <linux/irq.h>
>> > +#include <linux/irqchip.h>
>> > +#include <linux/irqdomain.h>
>> > +#include <linux/of.h>
>> > +#include <linux/of_irq.h>
>> > +#include <linux/of_address.h>
>> > +#include <linux/io.h>
>> > +#include <linux/slab.h>
>> > +#include <linux/syscore_ops.h>
>> > +
>> > +#define CIRQ_ACK 0x40
>> > +#define CIRQ_MASK_SET 0xc0
>> > +#define CIRQ_MASK_CLR 0x100
>> > +#define CIRQ_SENS_SET 0x180
>> > +#define CIRQ_SENS_CLR 0x1c0
>> > +#define CIRQ_POL_SET 0x240
>> > +#define CIRQ_POL_CLR 0x280
>> > +#define CIRQ_CONTROL 0x300
>> > +
>> > +#define CIRQ_EN 0x1
>> > +#define CIRQ_EDGE 0x2
>> > +#define CIRQ_FLUSH 0x4
>> > +
>> > +#define CIRQ_IRQ_NUM 0x200
>> > +
>> > +struct mtk_cirq_chip_data {
>> > + void __iomem *base;
>> > + unsigned int ext_irq_start;
>> > +};
>> > +
>> > +static struct mtk_cirq_chip_data *cirq_data;
>>
>> Are you guaranteed that you'll only ever have a single CIRQ in any
>> system?
>
> In Mediatek's SOC, only hace a single CIRQ.
>
>>
>> > +
>> > +static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
>> > +{
>> > + struct mtk_cirq_chip_data *chip_data = data->chip_data;
>> > + unsigned int cirq_num = data->hwirq;
>> > + u32 mask = 1 << (cirq_num % 32);
>> > +
>> > + writel(mask, chip_data->base + offset + (cirq_num / 32) * 4);
>>
>> Why can't you use the relaxed accessors?
>
> It seems that i use wrong function, i will change the writel to
> writel_relaxed in next version.
>
>>
>> > +}
>> > +
>> > +static void mtk_cirq_mask(struct irq_data *data)
>> > +{
>> > + mtk_cirq_write_mask(data, CIRQ_MASK_SET);
>> > + irq_chip_mask_parent(data);
>> > +}
>> > +
>> > +static void mtk_cirq_unmask(struct irq_data *data)
>> > +{
>> > + mtk_cirq_write_mask(data, CIRQ_MASK_CLR);
>> > + irq_chip_unmask_parent(data);
>> > +}
>> > +
>> > +static void mtk_cirq_eoi(struct irq_data *data)
>> > +{
>> > + mtk_cirq_write_mask(data, CIRQ_ACK);
>>
>> EOI and ACK have very different semantics. What is this write actually
>> doing? Also, you're now doing an additional MMIO write on each interrupt
>> EOI, doubling its cost. Do you really need to do actually signal the HW
>> that we've EOIed an interrupt? I would have hoped that you'd be able to
>> put it in "bypass" mode as long as you're not suspending...
>>
>
> When external interrupt happened, CIRQ status register record the status
> even CIRQ is not enabled. when execute the flush command, CIRQ will
> resend the signals according to the status. So if don't clear the
> status, CIRQ will resend the wrong signals. the ACK write operation will
> clear the status.
But at this time, we haven't suspended yet, and there is nothing to
replay. Also, you only enable the edge capture when suspending. So what
are you ACKing here? Can't you simply clear everything right when
suspending and not do it at all on the fast path?
Thanks,
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply
* [PATCH] pinctrl: sunxi: make bool drivers explicitly non-modular
From: Linus Walleij @ 2016-11-04 22:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161030000030.9394-1-paul.gortmaker@windriver.com>
On Sun, Oct 30, 2016 at 2:00 AM, Paul Gortmaker
<paul.gortmaker@windriver.com> wrote:
> None of the Kconfigs for any of these drivers are tristate,
> meaning that they currently are not being built as a module by anyone.
>
> Lets remove the modular code that is essentially orphaned, so that
> when reading the drivers there is no doubt they are builtin-only. All
> drivers get essentially the same change, so they are handled in batch.
>
> Changes are (1) use builtin_platform_driver, (2) use init.h header
> (3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE,
> and (5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags.
>
> Since module_platform_driver() uses the same init level priority as
> builtin_platform_driver() the init ordering remains unchanged with
> this commit.
>
> Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
>
> We do delete the MODULE_LICENSE etc. tags since all that information
> is already contained at the top of each file in the comments.
>
> Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
> Cc: Chen-Yu Tsai <wens@csie.org>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
> Cc: Fabian Frederick <fabf@skynet.be>
> Cc: Maxime Coquelin <maxime.coquelin@st.com>
> Cc: Vishnu Patekar <vishnupatekar0510@gmail.com>
> Cc: Mylene Josserand <mylene.josserand@free-electrons.com>
> Cc: linux-gpio at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Low network throughput on i.MX28
From: Jörg Krause @ 2016-11-04 22:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1783642995.185945.5e54a2af-ba2c-4901-93f6-1967dd432939.open-xchange@email.1und1.de>
Hi Stefan,
sorry, I forget the link in the previous mail.
On Fri, 2016-11-04 at 20:30 +0100, Stefan Wahren wrote:
> Hi J?rg,
>
> > J?rg Krause <joerg.krause@embedded.rocks> hat am 4. November 2016
> > um 19:44
> > geschrieben:
> >
> >
> > Hi Shawn,
> >
> > On Wed, 2016-11-02 at 09:24 +0100, Stefan Wahren wrote:
> > > Am 02.11.2016 um 09:14 schrieb J?rg Krause:
> > > > On Sat, 2016-10-29 at 11:08 +0200, Stefan Wahren wrote:
> > > > > > J?rg Krause <joerg.krause@embedded.rocks> hat am 29.
> > > > > > Oktober
> > > > > > 2016
> > > > > > um 01:07
> > > > > > geschrieben:
> > > > > >
> > > > > >
> > > > > > You mentioned [1] an optimization in the Freescale vendor
> > > > > > Linux
> > > > > > kernel
> > > > > > [2]. I would really like to see this optimization in the
> > > > > > mainline
> > > > > > kernel.
> > > > > >
> > > > > > Did you ever tried to port this code from Freescale to
> > > > > > mainline?
> > > > >
> > > > > Yes, i tried once but i was frustrated soon because of the
> > > > > lot of
> > > > > required
> > > > > changes and resulting issues.
> > > >
> > > > I got the PIO mode working for the mxs-mmc driver. For this I
> > > > ported
> > > > the PIO code from the vendor kernel and removed the usage of
> > > > the
> > > > DMA
> > > > engine entirely.
> > >
> > > Good job
> > >
> > > >
> > > > Testing network bandwidth with iperf, I get about ~10Mbit/sec
> > > > with
> > > > PIO
> > > > mode compared to ~6.5Mbit/sec with DMA mode for UDP and about
> > > > ~6.5Mbit/sec compared to ~4.5Mbit/sec with DMA mode for TCP.
> > >
> > > And how about MMC / sd card performance?
> >
> > I noticed poor performance with the i.MX28 MMC and/or DMA driver
> > using
> > the mainline kernel compared to the vendor Freescale kernel 2.6.35.
> > I've seen that hou have added the drivers to mainline some years
> > ago.
> >
> > My custom i.MX28 board has a wifi chip attached to the SSP2
> > interface.
> > Comparing the bandwith with iperf I get >20Mbits/sec on the vendor
> > kernel and <5Mbits/sec on the mainline kernel.
>
> there is one thing about the clock handling. I noticed that the
> Vendor Kernel
> round up the clock frequency and the Mainline Kernel round down the
> clock
> frequency [1]. So don't trust the clock ratings from DT / board code.
> Better
> verify the register settings or check it with an osci.
>
> [1] - http://www.spinics.net/lists/linux-mmc/msg09132.html
I checked the clock rate setting by reading the register 0x80014070
(HW_SSP2_TIMING). CLOCK_DIVIDE is 0x2 and CLOCK_RATE is 0x0. As SSP CLK
is 96MHz this makes a clock rate of 48MHz.
There was a discussion on the mailing list [1] about that tasklets
might be slow.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February
/043395.html
J?rg
^ permalink raw reply
* [v17 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
From: Daniel Kurtz @ 2016-11-04 23:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e00519e2-990c-b9b2-71d4-a4c8d36f5e65@gmail.com>
On Tue, Oct 25, 2016 at 6:23 AM, Matthias Brugger
<matthias.bgg@gmail.com> wrote:
>
> On 10/18/2016 04:37 PM, Enric Balletbo Serra wrote:
> [...]
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> [...]
>>>
>>> +
>>> +/* Firmware */
>>> +#define PS_FW_NAME "ps864x_fw.bin"
>>> +
>>
>> From where I can download this firmware image?
>
> I suppose this FW bits have to be added to linux-firmware repository first, before this patch can be accepted.
All PS8640 devices should already ship with working firmware.
The firmware update procedure is only used in the unlikely event where
one wants to update the bridge to a different firmware provided by
Parade.
Why must the lack of firmware really block landing this driver?
If this is really so, can we just land the functional part of the
driver first, and add the firmware update in a follow-up patch.
>
> Regards,
> Matthias
^ permalink raw reply
* [PATCH RFC 1/7] dma: pl08x: Add support for the DMA slave map
From: Arnd Bergmann @ 2016-11-04 23:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478276094-19135-3-git-send-email-s.nawrocki@samsung.com>
On Friday 04 November 2016, Sylwester Nawrocki wrote:
> + } else {
> + pl08x->slave.filter.map = pl08x->pd->slave_map;
> + pl08x->slave.filter.mapcnt = pl08x->pd->slave_map_len;
> }
I think you miss the setup of the filter function here.
Filtering by string in this driver is a bit awkward, so I wonder if we
might want to go one step further here and pass the actual data (i.e.
struct pl08x_channel_data) rather than the string here.
Arnd
^ permalink raw reply
* [PATCH RFC 4/7] ASoC: samsung: i2s: Do not use platform_data for DMA parameters
From: Arnd Bergmann @ 2016-11-04 23:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478276094-19135-6-git-send-email-s.nawrocki@samsung.com>
On Friday 04 November 2016, Sylwester Nawrocki wrote:
> - ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
> + ret = samsung_asoc_dma_platform_register(&pdev->dev, NULL,
> NULL, NULL);
If we remove the filter argument from every caller here, maybe we should also
change the prototype to not expect those three NULL arguments any more.
Arnd
^ permalink raw reply
* [PATCH 0/3] Add memremap executable mapping and extend drivers/misc/sram.c
From: Alexandre Belloni @ 2016-11-05 2:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161027185612.22362-1-d-gerlach@ti.com>
Hi,
On 27/10/2016 at 13:56:09 -0500, Dave Gerlach wrote :
> There are several instances when one would want to execute out of on-chip
> SRAM, such as PM code on ARM platforms, so once again revisiting this
> series to allow that in a generic manner. Seems that having a solution for
> allowing SRAM to be mapped as executable will help clean up PM code on several
> ARM platforms that are using ARM internal __arm_ioremap_exec API
> and also open the door for PM support on new platforms like TI AM335x and
> AM437x. This was last sent as RFC here [1] and based on comments from Russell
> King and Arnd Bergmann has been rewritten to use memremap API rather than
> ioremap API, as executable iomem does not really make sense.
>
> I still see several platforms (at-91, imx6, socfpga) that could make use
> of this and use the generic sram driver to allocate the SRAM needed for PM.
> This series allows direct allocation of SRAM using the generic SRAM driver
> that will be already mapped as executable. Otherwise platform SRAM allocation
> code must be used or if the generic sram driver is used as-is the memory
> must be remapped as executable after it has been mapped normally by the
> SRAM driver.
>
Rockchip also actually needs that.
> I had sent omap3 series to convert from using old omap sram platform
> mapping code to using the generic sram driver instead here [2] which was
> based on previous RFC but can easily be rebased on this updated series.
> Finally, forthcoming TI am335x and am437x PM code must make use of
> it as well, as portions of PM code are moving in to drivers.
>
> Changes from the RFC include:
>
> - Rather than introduce ioremap_exec API, use memremap API, as the concept
> of executable iomem does not make sense; any memory that can used to
> run code should not have io side effects like iomem.
> - Rather than having a fallback mapping if a platform does not support
> exec mappings under the memremap API, have the mapping fail, as if you
> are mapping memory as exec, presumably you will then try to run code
> from it which will fail anyway, so it makes more sense to prevent the
> mapping in the first place.
> - Update sram driver to use memremap rather than ioremap for exec flags.
>
> Regards,
> Dave
>
> [1] http://www.spinics.net/lists/arm-kernel/msg503071.html
> [2] http://www.spinics.net/lists/linux-omap/msg128753.html
>
> Dave Gerlach (3):
> ARM: memremap: implement arch_memremap_exec/exec_nocache
> memremap: add MEMREMAP_EXEC and MEMREMAP_EXEC_NOCACHE flags
> misc: SRAM: Add option to map SRAM to allow code execution
>
> Documentation/devicetree/bindings/sram/sram.txt | 2 ++
> arch/arm/include/asm/io.h | 5 ++++
> arch/arm/mm/ioremap.c | 16 ++++++++++++
> arch/arm/mm/nommu.c | 12 +++++++++
> drivers/misc/sram.c | 7 +++++
> include/linux/io.h | 2 ++
> kernel/memremap.c | 34 ++++++++++++++++++++++++-
> 7 files changed, 77 insertions(+), 1 deletion(-)
>
To the whole series:
Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 1/2] phy: rockchip-inno-usb2: support otg-port for rk3399
From: wlf @ 2016-11-05 2:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0eeb3dd9-fc1e-f04b-4612-06367929ede6@ti.com>
Hi Kishon,
? 2016?11?04? 01:17, Kishon Vijay Abraham I ??:
>
> On Thursday 03 November 2016 07:36 AM, William Wu wrote:
>> The rk3399 SoC USB2 PHY is comprised of one Host port and
>> one OTG port. And OTG port is for USB2.0 part of USB3.0 OTG
>> controller, as a part to construct a fully feature Type-C
>> subsystem.
>>
>> With this patch, we can support OTG port with the following
>> functions:
>> - Support BC1.2 charger detect, and use extcon notifier to
>> send USB charger types to power driver.
>> - Support PHY suspend for power management.
>> - Support OTG Host only mode.
>>
>> Also, correct 480MHz output clock stable time. We found that
>> the system crashed due to 480MHz output clock of USB2 PHY was
>> unstable after clock had been enabled by gpu module.
> Can you split the clock fix into a separate patch?
OK, I will separate the clock patch in next version.
Best regards,
wulf
>
> Thanks
> Kishon
>> Theoretically, 1 millisecond is a critical value for 480 output
>> clock stable time, so we try changing the delay time to 1.2
>> millisecond to avoid this issue.
>>
>> Signed-off-by: William Wu <wulf@rock-chips.com>
>> ---
>> Changes in v2:
>> - remove wakelock
>>
>> drivers/phy/phy-rockchip-inno-usb2.c | 593 +++++++++++++++++++++++++++++++++--
>> 1 file changed, 562 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
>> index ac20310..8f2d2b6 100644
>> --- a/drivers/phy/phy-rockchip-inno-usb2.c
>> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
>> @@ -17,6 +17,7 @@
>> #include <linux/clk.h>
>> #include <linux/clk-provider.h>
>> #include <linux/delay.h>
>> +#include <linux/extcon.h>
>> #include <linux/interrupt.h>
>> #include <linux/io.h>
>> #include <linux/gpio/consumer.h>
>> @@ -30,11 +31,15 @@
>> #include <linux/of_platform.h>
>> #include <linux/phy/phy.h>
>> #include <linux/platform_device.h>
>> +#include <linux/power_supply.h>
>> #include <linux/regmap.h>
>> #include <linux/mfd/syscon.h>
>> +#include <linux/usb/of.h>
>> +#include <linux/usb/otg.h>
>>
>> #define BIT_WRITEABLE_SHIFT 16
>> -#define SCHEDULE_DELAY (60 * HZ)
>> +#define SCHEDULE_DELAY (60 * HZ)
>> +#define OTG_SCHEDULE_DELAY (2 * HZ)
>>
>> enum rockchip_usb2phy_port_id {
>> USB2PHY_PORT_OTG,
>> @@ -49,6 +54,37 @@ enum rockchip_usb2phy_host_state {
>> PHY_STATE_FS_LS_ONLINE = 4,
>> };
>>
>> +/**
>> + * Different states involved in USB charger detection.
>> + * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
>> + * process is not yet started.
>> + * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
>> + * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
>> + * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
>> + * between SDP and DCP/CDP).
>> + * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
>> + * between DCP and CDP).
>> + * USB_CHG_STATE_DETECTED USB charger type is determined.
>> + */
>> +enum usb_chg_state {
>> + USB_CHG_STATE_UNDEFINED = 0,
>> + USB_CHG_STATE_WAIT_FOR_DCD,
>> + USB_CHG_STATE_DCD_DONE,
>> + USB_CHG_STATE_PRIMARY_DONE,
>> + USB_CHG_STATE_SECONDARY_DONE,
>> + USB_CHG_STATE_DETECTED,
>> +};
>> +
>> +static const unsigned int rockchip_usb2phy_extcon_cable[] = {
>> + EXTCON_USB,
>> + EXTCON_USB_HOST,
>> + EXTCON_CHG_USB_SDP,
>> + EXTCON_CHG_USB_CDP,
>> + EXTCON_CHG_USB_DCP,
>> + EXTCON_CHG_USB_SLOW,
>> + EXTCON_NONE,
>> +};
>> +
>> struct usb2phy_reg {
>> unsigned int offset;
>> unsigned int bitend;
>> @@ -58,19 +94,55 @@ struct usb2phy_reg {
>> };
>>
>> /**
>> + * struct rockchip_chg_det_reg: usb charger detect registers
>> + * @cp_det: charging port detected successfully.
>> + * @dcp_det: dedicated charging port detected successfully.
>> + * @dp_det: assert data pin connect successfully.
>> + * @idm_sink_en: open dm sink curren.
>> + * @idp_sink_en: open dp sink current.
>> + * @idp_src_en: open dm source current.
>> + * @rdm_pdwn_en: open dm pull down resistor.
>> + * @vdm_src_en: open dm voltage source.
>> + * @vdp_src_en: open dp voltage source.
>> + * @opmode: utmi operational mode.
>> + */
>> +struct rockchip_chg_det_reg {
>> + struct usb2phy_reg cp_det;
>> + struct usb2phy_reg dcp_det;
>> + struct usb2phy_reg dp_det;
>> + struct usb2phy_reg idm_sink_en;
>> + struct usb2phy_reg idp_sink_en;
>> + struct usb2phy_reg idp_src_en;
>> + struct usb2phy_reg rdm_pdwn_en;
>> + struct usb2phy_reg vdm_src_en;
>> + struct usb2phy_reg vdp_src_en;
>> + struct usb2phy_reg opmode;
>> +};
>> +
>> +/**
>> * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
>> * @phy_sus: phy suspend register.
>> + * @bvalid_det_en: vbus valid rise detection enable register.
>> + * @bvalid_det_st: vbus valid rise detection status register.
>> + * @bvalid_det_clr: vbus valid rise detection clear register.
>> * @ls_det_en: linestate detection enable register.
>> * @ls_det_st: linestate detection state register.
>> * @ls_det_clr: linestate detection clear register.
>> + * @utmi_avalid: utmi vbus avalid status register.
>> + * @utmi_bvalid: utmi vbus bvalid status register.
>> * @utmi_ls: utmi linestate state register.
>> * @utmi_hstdet: utmi host disconnect register.
>> */
>> struct rockchip_usb2phy_port_cfg {
>> struct usb2phy_reg phy_sus;
>> + struct usb2phy_reg bvalid_det_en;
>> + struct usb2phy_reg bvalid_det_st;
>> + struct usb2phy_reg bvalid_det_clr;
>> struct usb2phy_reg ls_det_en;
>> struct usb2phy_reg ls_det_st;
>> struct usb2phy_reg ls_det_clr;
>> + struct usb2phy_reg utmi_avalid;
>> + struct usb2phy_reg utmi_bvalid;
>> struct usb2phy_reg utmi_ls;
>> struct usb2phy_reg utmi_hstdet;
>> };
>> @@ -80,31 +152,51 @@ struct rockchip_usb2phy_port_cfg {
>> * @reg: the address offset of grf for usb-phy config.
>> * @num_ports: specify how many ports that the phy has.
>> * @clkout_ctl: keep on/turn off output clk of phy.
>> + * @chg_det: charger detection registers.
>> */
>> struct rockchip_usb2phy_cfg {
>> unsigned int reg;
>> unsigned int num_ports;
>> struct usb2phy_reg clkout_ctl;
>> const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
>> + const struct rockchip_chg_det_reg chg_det;
>> };
>>
>> /**
>> * struct rockchip_usb2phy_port: usb-phy port data.
>> * @port_id: flag for otg port or host port.
>> * @suspended: phy suspended flag.
>> + * @utmi_avalid: utmi avalid status usage flag.
>> + * true - use avalid to get vbus status
>> + * flase - use bvalid to get vbus status
>> + * @vbus_attached: otg device vbus status.
>> + * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
>> * @ls_irq: IRQ number assigned for linestate detection.
>> * @mutex: for register updating in sm_work.
>> - * @sm_work: OTG state machine work.
>> + * @chg_work: charge detect work.
>> + * @otg_sm_work: OTG state machine work.
>> + * @sm_work: HOST state machine work.
>> * @phy_cfg: port register configuration, assigned by driver data.
>> + * @event_nb: hold event notification callback.
>> + * @state: define OTG enumeration states before device reset.
>> + * @mode: the dr_mode of the controller.
>> */
>> struct rockchip_usb2phy_port {
>> struct phy *phy;
>> unsigned int port_id;
>> bool suspended;
>> + bool utmi_avalid;
>> + bool vbus_attached;
>> + int bvalid_irq;
>> int ls_irq;
>> struct mutex mutex;
>> + struct delayed_work chg_work;
>> + struct delayed_work otg_sm_work;
>> struct delayed_work sm_work;
>> const struct rockchip_usb2phy_port_cfg *port_cfg;
>> + struct notifier_block event_nb;
>> + enum usb_otg_state state;
>> + enum usb_dr_mode mode;
>> };
>>
>> /**
>> @@ -113,6 +205,11 @@ struct rockchip_usb2phy_port {
>> * @clk: clock struct of phy input clk.
>> * @clk480m: clock struct of phy output clk.
>> * @clk_hw: clock struct of phy output clk management.
>> + * @chg_state: states involved in USB charger detection.
>> + * @chg_type: USB charger types.
>> + * @dcd_retries: The retry count used to track Data contact
>> + * detection process.
>> + * @edev: extcon device for notification registration
>> * @phy_cfg: phy register configuration, assigned by driver data.
>> * @ports: phy port instance.
>> */
>> @@ -122,6 +219,10 @@ struct rockchip_usb2phy {
>> struct clk *clk;
>> struct clk *clk480m;
>> struct clk_hw clk480m_hw;
>> + enum usb_chg_state chg_state;
>> + enum power_supply_type chg_type;
>> + u8 dcd_retries;
>> + struct extcon_dev *edev;
>> const struct rockchip_usb2phy_cfg *phy_cfg;
>> struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
>> };
>> @@ -166,7 +267,7 @@ static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
>> return ret;
>>
>> /* waitting for the clk become stable */
>> - mdelay(1);
>> + udelay(1200);
>> }
>>
>> return 0;
>> @@ -263,33 +364,84 @@ rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
>> return ret;
>> }
>>
>> -static int rockchip_usb2phy_init(struct phy *phy)
>> +static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
>> {
>> - struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
>> - struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
>> int ret;
>> + struct device_node *node = rphy->dev->of_node;
>> + struct extcon_dev *edev;
>> +
>> + if (of_property_read_bool(node, "extcon")) {
>> + edev = extcon_get_edev_by_phandle(rphy->dev, 0);
>> + if (IS_ERR(edev)) {
>> + if (PTR_ERR(edev) != -EPROBE_DEFER)
>> + dev_err(rphy->dev, "Invalid or missing extcon\n");
>> + return PTR_ERR(edev);
>> + }
>> + } else {
>> + /* Initialize extcon device */
>> + edev = devm_extcon_dev_allocate(rphy->dev,
>> + rockchip_usb2phy_extcon_cable);
>>
>> - if (rport->port_id == USB2PHY_PORT_HOST) {
>> - /* clear linestate and enable linestate detect irq */
>> - mutex_lock(&rport->mutex);
>> + if (IS_ERR(edev))
>> + return -ENOMEM;
>>
>> - ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
>> + ret = devm_extcon_dev_register(rphy->dev, edev);
>> if (ret) {
>> - mutex_unlock(&rport->mutex);
>> + dev_err(rphy->dev, "failed to register extcon device\n");
>> return ret;
>> }
>> + }
>>
>> - ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
>> - if (ret) {
>> - mutex_unlock(&rport->mutex);
>> - return ret;
>> + rphy->edev = edev;
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_usb2phy_init(struct phy *phy)
>> +{
>> + struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
>> + struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
>> + int ret = 0;
>> +
>> + mutex_lock(&rport->mutex);
>> +
>> + if (rport->port_id == USB2PHY_PORT_OTG) {
>> + if (rport->mode != USB_DR_MODE_HOST) {
>> + /* clear bvalid status and enable bvalid detect irq */
>> + ret = property_enable(rphy,
>> + &rport->port_cfg->bvalid_det_clr,
>> + true);
>> + if (ret)
>> + goto out;
>> +
>> + ret = property_enable(rphy,
>> + &rport->port_cfg->bvalid_det_en,
>> + true);
>> + if (ret)
>> + goto out;
>> +
>> + schedule_delayed_work(&rport->otg_sm_work,
>> + OTG_SCHEDULE_DELAY);
>> + } else {
>> + /* If OTG works in host only mode, do nothing. */
>> + dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
>> }
>> + } else if (rport->port_id == USB2PHY_PORT_HOST) {
>> + /* clear linestate and enable linestate detect irq */
>> + ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
>> + if (ret)
>> + goto out;
>> +
>> + ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
>> + if (ret)
>> + goto out;
>>
>> - mutex_unlock(&rport->mutex);
>> schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
>> }
>>
>> - return 0;
>> +out:
>> + mutex_unlock(&rport->mutex);
>> + return ret;
>> }
>>
>> static int rockchip_usb2phy_power_on(struct phy *phy)
>> @@ -340,7 +492,11 @@ static int rockchip_usb2phy_exit(struct phy *phy)
>> {
>> struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
>>
>> - if (rport->port_id == USB2PHY_PORT_HOST)
>> + if (rport->port_id == USB2PHY_PORT_OTG &&
>> + rport->mode != USB_DR_MODE_HOST) {
>> + cancel_delayed_work_sync(&rport->otg_sm_work);
>> + cancel_delayed_work_sync(&rport->chg_work);
>> + } else if (rport->port_id == USB2PHY_PORT_HOST)
>> cancel_delayed_work_sync(&rport->sm_work);
>>
>> return 0;
>> @@ -354,6 +510,249 @@ static const struct phy_ops rockchip_usb2phy_ops = {
>> .owner = THIS_MODULE,
>> };
>>
>> +static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
>> +{
>> + struct rockchip_usb2phy_port *rport =
>> + container_of(work, struct rockchip_usb2phy_port,
>> + otg_sm_work.work);
>> + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
>> + static unsigned int cable;
>> + unsigned long delay;
>> + bool vbus_attach, sch_work, notify_charger;
>> +
>> + if (rport->utmi_avalid)
>> + vbus_attach =
>> + property_enabled(rphy, &rport->port_cfg->utmi_avalid);
>> + else
>> + vbus_attach =
>> + property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
>> +
>> + sch_work = false;
>> + notify_charger = false;
>> + delay = OTG_SCHEDULE_DELAY;
>> + dev_dbg(&rport->phy->dev, "%s otg sm work\n",
>> + usb_otg_state_string(rport->state));
>> +
>> + switch (rport->state) {
>> + case OTG_STATE_UNDEFINED:
>> + rport->state = OTG_STATE_B_IDLE;
>> + if (!vbus_attach)
>> + rockchip_usb2phy_power_off(rport->phy);
>> + /* fall through */
>> + case OTG_STATE_B_IDLE:
>> + if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
>> + dev_dbg(&rport->phy->dev, "usb otg host connect\n");
>> + rport->state = OTG_STATE_A_HOST;
>> + rockchip_usb2phy_power_on(rport->phy);
>> + return;
>> + } else if (vbus_attach) {
>> + dev_dbg(&rport->phy->dev, "vbus_attach\n");
>> + switch (rphy->chg_state) {
>> + case USB_CHG_STATE_UNDEFINED:
>> + schedule_delayed_work(&rport->chg_work, 0);
>> + return;
>> + case USB_CHG_STATE_DETECTED:
>> + switch (rphy->chg_type) {
>> + case POWER_SUPPLY_TYPE_USB:
>> + dev_dbg(&rport->phy->dev,
>> + "sdp cable is connecetd\n");
>> + rockchip_usb2phy_power_on(rport->phy);
>> + rport->state = OTG_STATE_B_PERIPHERAL;
>> + notify_charger = true;
>> + sch_work = true;
>> + cable = EXTCON_CHG_USB_SDP;
>> + break;
>> + case POWER_SUPPLY_TYPE_USB_DCP:
>> + dev_dbg(&rport->phy->dev,
>> + "dcp cable is connecetd\n");
>> + rockchip_usb2phy_power_off(rport->phy);
>> + notify_charger = true;
>> + sch_work = true;
>> + cable = EXTCON_CHG_USB_DCP;
>> + break;
>> + case POWER_SUPPLY_TYPE_USB_CDP:
>> + dev_dbg(&rport->phy->dev,
>> + "cdp cable is connecetd\n");
>> + rockchip_usb2phy_power_on(rport->phy);
>> + rport->state = OTG_STATE_B_PERIPHERAL;
>> + notify_charger = true;
>> + sch_work = true;
>> + cable = EXTCON_CHG_USB_CDP;
>> + break;
>> + default:
>> + break;
>> + }
>> + break;
>> + default:
>> + break;
>> + }
>> + } else {
>> + notify_charger = true;
>> + rphy->chg_state = USB_CHG_STATE_UNDEFINED;
>> + rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
>> + }
>> +
>> + if (rport->vbus_attached != vbus_attach) {
>> + rport->vbus_attached = vbus_attach;
>> +
>> + if (notify_charger && rphy->edev)
>> + extcon_set_cable_state_(rphy->edev,
>> + cable, vbus_attach);
>> + }
>> + break;
>> + case OTG_STATE_B_PERIPHERAL:
>> + if (!vbus_attach) {
>> + dev_dbg(&rport->phy->dev, "usb disconnect\n");
>> + rphy->chg_state = USB_CHG_STATE_UNDEFINED;
>> + rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
>> + rport->state = OTG_STATE_B_IDLE;
>> + delay = 0;
>> + rockchip_usb2phy_power_off(rport->phy);
>> + }
>> + sch_work = true;
>> + break;
>> + case OTG_STATE_A_HOST:
>> + if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
>> + dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
>> + rport->state = OTG_STATE_B_IDLE;
>> + rockchip_usb2phy_power_off(rport->phy);
>> + }
>> + break;
>> + default:
>> + break;
>> + }
>> +
>> + if (sch_work)
>> + schedule_delayed_work(&rport->otg_sm_work, delay);
>> +}
>> +
>> +static const char *chg_to_string(enum power_supply_type chg_type)
>> +{
>> + switch (chg_type) {
>> + case POWER_SUPPLY_TYPE_USB:
>> + return "USB_SDP_CHARGER";
>> + case POWER_SUPPLY_TYPE_USB_DCP:
>> + return "USB_DCP_CHARGER";
>> + case POWER_SUPPLY_TYPE_USB_CDP:
>> + return "USB_CDP_CHARGER";
>> + default:
>> + return "INVALID_CHARGER";
>> + }
>> +}
>> +
>> +static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
>> + bool en)
>> +{
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
>> +}
>> +
>> +static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
>> + bool en)
>> +{
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
>> +}
>> +
>> +static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
>> + bool en)
>> +{
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
>> +}
>> +
>> +#define CHG_DCD_POLL_TIME (100 * HZ / 1000)
>> +#define CHG_DCD_MAX_RETRIES 6
>> +#define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
>> +#define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
>> +static void rockchip_chg_detect_work(struct work_struct *work)
>> +{
>> + struct rockchip_usb2phy_port *rport =
>> + container_of(work, struct rockchip_usb2phy_port, chg_work.work);
>> + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
>> + bool is_dcd, tmout, vout;
>> + unsigned long delay;
>> +
>> + dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
>> + rphy->chg_state);
>> + switch (rphy->chg_state) {
>> + case USB_CHG_STATE_UNDEFINED:
>> + if (!rport->suspended)
>> + rockchip_usb2phy_power_off(rport->phy);
>> + /* put the controller in non-driving mode */
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
>> + /* Start DCD processing stage 1 */
>> + rockchip_chg_enable_dcd(rphy, true);
>> + rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
>> + rphy->dcd_retries = 0;
>> + delay = CHG_DCD_POLL_TIME;
>> + break;
>> + case USB_CHG_STATE_WAIT_FOR_DCD:
>> + /* get data contact detection status */
>> + is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
>> + tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
>> + /* stage 2 */
>> + if (is_dcd || tmout) {
>> + /* stage 4 */
>> + /* Turn off DCD circuitry */
>> + rockchip_chg_enable_dcd(rphy, false);
>> + /* Voltage Source on DP, Probe on DM */
>> + rockchip_chg_enable_primary_det(rphy, true);
>> + delay = CHG_PRIMARY_DET_TIME;
>> + rphy->chg_state = USB_CHG_STATE_DCD_DONE;
>> + } else {
>> + /* stage 3 */
>> + delay = CHG_DCD_POLL_TIME;
>> + }
>> + break;
>> + case USB_CHG_STATE_DCD_DONE:
>> + vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
>> + rockchip_chg_enable_primary_det(rphy, false);
>> + if (vout) {
>> + /* Voltage Source on DM, Probe on DP */
>> + rockchip_chg_enable_secondary_det(rphy, true);
>> + delay = CHG_SECONDARY_DET_TIME;
>> + rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
>> + } else {
>> + if (tmout) {
>> + /* floating charger found */
>> + rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
>> + rphy->chg_state = USB_CHG_STATE_DETECTED;
>> + delay = 0;
>> + } else {
>> + rphy->chg_type = POWER_SUPPLY_TYPE_USB;
>> + rphy->chg_state = USB_CHG_STATE_DETECTED;
>> + delay = 0;
>> + }
>> + }
>> + break;
>> + case USB_CHG_STATE_PRIMARY_DONE:
>> + vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
>> + /* Turn off voltage source */
>> + rockchip_chg_enable_secondary_det(rphy, false);
>> + if (vout)
>> + rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
>> + else
>> + rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
>> + /* fall through */
>> + case USB_CHG_STATE_SECONDARY_DONE:
>> + rphy->chg_state = USB_CHG_STATE_DETECTED;
>> + delay = 0;
>> + /* fall through */
>> + case USB_CHG_STATE_DETECTED:
>> + /* put the controller in normal mode */
>> + property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
>> + rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
>> + dev_info(&rport->phy->dev, "charger = %s\n",
>> + chg_to_string(rphy->chg_type));
>> + return;
>> + default:
>> + return;
>> + }
>> +
>> + schedule_delayed_work(&rport->chg_work, delay);
>> +}
>> +
>> /*
>> * The function manage host-phy port state and suspend/resume phy port
>> * to save power.
>> @@ -485,6 +884,26 @@ static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
>> return IRQ_HANDLED;
>> }
>>
>> +static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
>> +{
>> + struct rockchip_usb2phy_port *rport = data;
>> + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
>> +
>> + if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
>> + return IRQ_NONE;
>> +
>> + mutex_lock(&rport->mutex);
>> +
>> + /* clear bvalid detect irq pending status */
>> + property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
>> +
>> + mutex_unlock(&rport->mutex);
>> +
>> + rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
>> struct rockchip_usb2phy_port *rport,
>> struct device_node *child_np)
>> @@ -509,13 +928,86 @@ static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
>> IRQF_ONESHOT,
>> "rockchip_usb2phy", rport);
>> if (ret) {
>> - dev_err(rphy->dev, "failed to request irq handle\n");
>> + dev_err(rphy->dev, "failed to request linestate irq handle\n");
>> return ret;
>> }
>>
>> return 0;
>> }
>>
>> +static int rockchip_otg_event(struct notifier_block *nb,
>> + unsigned long event, void *ptr)
>> +{
>> + struct rockchip_usb2phy_port *rport =
>> + container_of(nb, struct rockchip_usb2phy_port, event_nb);
>> +
>> + schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
>> +
>> + return NOTIFY_DONE;
>> +}
>> +
>> +static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
>> + struct rockchip_usb2phy_port *rport,
>> + struct device_node *child_np)
>> +{
>> + int ret;
>> +
>> + rport->port_id = USB2PHY_PORT_OTG;
>> + rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
>> + rport->state = OTG_STATE_UNDEFINED;
>> +
>> + /*
>> + * set suspended flag to true, but actually don't
>> + * put phy in suspend mode, it aims to enable usb
>> + * phy and clock in power_on() called by usb controller
>> + * driver during probe.
>> + */
>> + rport->suspended = true;
>> + rport->vbus_attached = false;
>> +
>> + mutex_init(&rport->mutex);
>> +
>> + rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
>> + if (rport->mode == USB_DR_MODE_HOST) {
>> + ret = 0;
>> + goto out;
>> + }
>> +
>> + INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
>> + INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
>> +
>> + rport->utmi_avalid =
>> + of_property_read_bool(child_np, "rockchip,utmi-avalid");
>> +
>> + rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
>> + if (rport->bvalid_irq < 0) {
>> + dev_err(rphy->dev, "no vbus valid irq provided\n");
>> + ret = rport->bvalid_irq;
>> + goto out;
>> + }
>> +
>> + ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
>> + rockchip_usb2phy_bvalid_irq,
>> + IRQF_ONESHOT,
>> + "rockchip_usb2phy_bvalid", rport);
>> + if (ret) {
>> + dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
>> + goto out;
>> + }
>> +
>> + if (!IS_ERR(rphy->edev)) {
>> + rport->event_nb.notifier_call = rockchip_otg_event;
>> +
>> + ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
>> + &rport->event_nb);
>> + if (ret)
>> + dev_err(rphy->dev, "register USB HOST notifier failed\n");
>> + }
>> +
>> +out:
>> + return ret;
>> +}
>> +
>> static int rockchip_usb2phy_probe(struct platform_device *pdev)
>> {
>> struct device *dev = &pdev->dev;
>> @@ -553,8 +1045,14 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
>>
>> rphy->dev = dev;
>> phy_cfgs = match->data;
>> + rphy->chg_state = USB_CHG_STATE_UNDEFINED;
>> + rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
>> platform_set_drvdata(pdev, rphy);
>>
>> + ret = rockchip_usb2phy_extcon_register(rphy);
>> + if (ret)
>> + return ret;
>> +
>> /* find out a proper config which can be matched with dt. */
>> index = 0;
>> while (phy_cfgs[index].reg) {
>> @@ -591,13 +1089,9 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
>> struct rockchip_usb2phy_port *rport = &rphy->ports[index];
>> struct phy *phy;
>>
>> - /*
>> - * This driver aim to support both otg-port and host-port,
>> - * but unfortunately, the otg part is not ready in current,
>> - * so this comments and below codes are interim, which should
>> - * be changed after otg-port is supplied soon.
>> - */
>> - if (of_node_cmp(child_np->name, "host-port"))
>> + /* This driver aims to support both otg-port and host-port */
>> + if (of_node_cmp(child_np->name, "host-port") &&
>> + of_node_cmp(child_np->name, "otg-port"))
>> goto next_child;
>>
>> phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
>> @@ -610,9 +1104,18 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
>> rport->phy = phy;
>> phy_set_drvdata(rport->phy, rport);
>>
>> - ret = rockchip_usb2phy_host_port_init(rphy, rport, child_np);
>> - if (ret)
>> - goto put_child;
>> + /* initialize otg/host port separately */
>> + if (!of_node_cmp(child_np->name, "host-port")) {
>> + ret = rockchip_usb2phy_host_port_init(rphy, rport,
>> + child_np);
>> + if (ret)
>> + goto put_child;
>> + } else {
>> + ret = rockchip_usb2phy_otg_port_init(rphy, rport,
>> + child_np);
>> + if (ret)
>> + goto put_child;
>> + }
>>
>> next_child:
>> /* to prevent out of boundary */
>> @@ -654,10 +1157,18 @@ static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
>>
>> static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
>> {
>> - .reg = 0xe450,
>> + .reg = 0xe450,
>> .num_ports = 2,
>> .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
>> .port_cfgs = {
>> + [USB2PHY_PORT_OTG] = {
>> + .phy_sus = { 0xe454, 1, 0, 2, 1 },
>> + .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
>> + .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
>> + .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
>> + .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
>> + .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
>> + },
>> [USB2PHY_PORT_HOST] = {
>> .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
>> .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
>> @@ -667,12 +1178,32 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
>> .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
>> }
>> },
>> + .chg_det = {
>> + .opmode = { 0xe454, 3, 0, 5, 1 },
>> + .cp_det = { 0xe2ac, 2, 2, 0, 1 },
>> + .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
>> + .dp_det = { 0xe2ac, 0, 0, 0, 1 },
>> + .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
>> + .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
>> + .idp_src_en = { 0xe450, 9, 9, 0, 1 },
>> + .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
>> + .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
>> + .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
>> + },
>> },
>> {
>> - .reg = 0xe460,
>> + .reg = 0xe460,
>> .num_ports = 2,
>> .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
>> .port_cfgs = {
>> + [USB2PHY_PORT_OTG] = {
>> + .phy_sus = { 0xe464, 1, 0, 2, 1 },
>> + .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
>> + .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
>> + .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
>> + .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
>> + .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
>> + },
>> [USB2PHY_PORT_HOST] = {
>> .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
>> .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
>>
>
>
^ permalink raw reply
* [PATCH 2/3] ARM: cache-uniphier: refactor jump label to follow coding style guideline
From: Masahiro Yamada @ 2016-11-05 3:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161104133221.GD1041@n2100.armlinux.org.uk>
2016-11-04 22:32 GMT+09:00 Russell King - ARM Linux <linux@armlinux.org.uk>:
> On Fri, Nov 04, 2016 at 09:50:56PM +0900, Masahiro Yamada wrote:
>> Hi Russell,
>>
>> 2016-11-04 21:23 GMT+09:00 Russell King - ARM Linux <linux@armlinux.org.uk>:
>> > On Fri, Nov 04, 2016 at 08:43:35PM +0900, Masahiro Yamada wrote:
>> >> Documentation/CodingStyle recommends to use label names which say
>> >> what the goto does or why the goto exists.
>> >>
>> >> Just in case, split it up into three labels because the CodingStyle
>> >> says "one err bugs" is a common type of bug (although, I do not
>> >> believe the current code includes such a bug).
>> >
>> > However, this has the effect of making the code unnecessarily more
>> > complicated, which is a bad thing. Avoiding unnecessary code
>> > complexity wins over style rules.
>>
>>
>> I thought this patch is stupid, but makes the code more straight-forward;
>> the failure path only calls really needed iounmap/kfree()
>> without exploiting that NULL input makes them no-op.
>
> ... while making it more fragile, because we're going back to a
> situation where the right places need to jump to the right label
> in the cleanup, so that the right functions are called.
>
> This is a backwards step.
>
> The reason that iounmap() and kfree() check for NULL pointers is to
> allow the cleanup paths to be simple, and that's very important as
> many cleanup paths are simply _not_ tested.
OK, fair enough.
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH v2 2/3] phy: da8xx-usb: rename the ohci device to ohci-da8xx
From: Kishon Vijay Abraham I @ 2016-11-05 5:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161103160308.29588-3-ahaslam@baylibre.com>
On Thursday 03 November 2016 09:33 PM, Axel Haslam wrote:
> The ohci device name has changed in the board configuraion files,
> hence, change the phy lookup table to match the new name.
>
> Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
merged, thanks.
-Kishon
> ---
> drivers/phy/phy-da8xx-usb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c
> index 32ae78c..c85fb0b 100644
> --- a/drivers/phy/phy-da8xx-usb.c
> +++ b/drivers/phy/phy-da8xx-usb.c
> @@ -198,7 +198,8 @@ static int da8xx_usb_phy_probe(struct platform_device *pdev)
> } else {
> int ret;
>
> - ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy", "ohci.0");
> + ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy",
> + "ohci-da8xx");
> if (ret)
> dev_warn(dev, "Failed to create usb11 phy lookup\n");
> ret = phy_create_lookup(d_phy->usb20_phy, "usb-phy",
> @@ -216,7 +217,7 @@ static int da8xx_usb_phy_remove(struct platform_device *pdev)
>
> if (!pdev->dev.of_node) {
> phy_remove_lookup(d_phy->usb20_phy, "usb-phy", "musb-da8xx");
> - phy_remove_lookup(d_phy->usb11_phy, "usb-phy", "ohci.0");
> + phy_remove_lookup(d_phy->usb11_phy, "usb-phy", "ohci-da8xx");
> }
>
> return 0;
>
^ permalink raw reply
* [PATCH V3 0/6] ARM64: Uprobe support added
From: Pratyush Anand @ 2016-11-05 5:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161104184652.rxllldll4qfe7qdn@localhost>
On Saturday 05 November 2016 12:16 AM, Catalin Marinas wrote:
> On Fri, Nov 04, 2016 at 11:49:51AM -0600, Catalin Marinas wrote:
>> On Wed, Nov 02, 2016 at 02:40:40PM +0530, Pratyush Anand wrote:
>>> Pratyush Anand (6):
>>> arm64: kprobe: protect/rename few definitions to be reused by uprobe
>>> arm64: kgdb_step_brk_fn: ignore other's exception
>>> arm64: Handle TRAP_TRACE for user mode as well
>>> arm64: Handle TRAP_BRKPT for user mode as well
>>> arm64: introduce mm context flag to keep 32 bit task information
>>> arm64: Add uprobe support
>>
>> I queued the patches for 4.10. I will push them into -next sometime next
>> week once I do some testing (I'm currently at the LPC).
>
> I spoke too soon. With these patches on top of 4.9-rc3, defconfig
> together with FTRACE and UPROBE_EVENT enabled I get:
>
> In file included from /work/Linux/linux-2.6-aarch64/arch/arm64/kernel/probes/decode-insn.c:20:0:
> /work/Linux/linux-2.6-aarch64/arch/arm64/include/asm/kprobes.h:52:5: error: conflicting types for 'kprobe_fault_handler'
> int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
> ^~~~~~~~~~~~~~~~~~~~
> In file included from /work/Linux/linux-2.6-aarch64/arch/arm64/kernel/probes/decode-insn.c:17:0:
> /work/Linux/linux-2.6-aarch64/include/linux/kprobes.h:398:90: note: previous definition of 'kprobe_fault_handler' was here
> static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
> ^
> /work/Linux/linux-2.6-aarch64/scripts/Makefile.build:290: recipe for target 'arch/arm64/kernel/probes/decode-insn.o' failed
>
Hummmm...CONFIG_KPROBE was defined in my setup and did not notice it :(
. We need to remove #include <asm/kprobes.h> from
/arch/arm64/kernel/probes/decode-insn.c.
<asm/kprobes.h> is already included from <linux/kprobes.h> under #ifdef
CONFIG_KPROBE.
diff --git a/arch/arm64/kernel/probes/decode-insn.c
b/arch/arm64/kernel/probes/decode-insn.c
index 8a29d29..6bf6657 100644
--- a/arch/arm64/kernel/probes/decode-insn.c
+++ b/arch/arm64/kernel/probes/decode-insn.c
@@ -17,7 +17,6 @@
#include <linux/kprobes.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-#include <asm/kprobes.h>
#include <asm/insn.h>
#include <asm/sections.h>
So, do you want me to send V4 or a separate topup fixup patch. Please
let me know, will do accordingly.
~Pratyush
^ permalink raw reply related
* [PATCH v2] phy: sun4i: check PMU presence when poking unknown bit of pmu
From: Kishon Vijay Abraham I @ 2016-11-05 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <41f43381-c1bb-2f69-5f99-ac5cebf651ea@redhat.com>
On Friday 28 October 2016 11:45 PM, Hans de Goede wrote:
> Hi,
>
> On 28-10-16 18:27, Icenowy Zheng wrote:
>> Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part.
>> The code that poke some unknown bit of PMU for H3/A64 didn't check
>> the PHY, and will cause kernel oops when PHY 0 is used.
>>
>> This patch will check whether the pmu is not NULL before poking.
>>
>> Fixes: b3e0d141ca9f (phy: sun4i: add support for A64 usb phy)
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Patch LGTM too:
>
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
merged, thanks.
-Kishon
>
> Regards,
>
> Hans
>
>
>> ---
>> drivers/phy/phy-sun4i-usb.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
>> index b9342a2..fec34f5 100644
>> --- a/drivers/phy/phy-sun4i-usb.c
>> +++ b/drivers/phy/phy-sun4i-usb.c
>> @@ -264,7 +264,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>> return ret;
>> }
>>
>> - if (data->cfg->enable_pmu_unk1) {
>> + if (phy->pmu && data->cfg->enable_pmu_unk1) {
>> val = readl(phy->pmu + REG_PMU_UNK1);
>> writel(val & ~2, phy->pmu + REG_PMU_UNK1);
>> }
>>
^ permalink raw reply
* [PATCH] drm/sun4i: Fix error handling
From: Christophe JAILLET @ 2016-11-05 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102181444.hfrh6fcr2a5oe5n4@lukather>
Le 02/11/2016 ? 19:14, Maxime Ripard a ?crit :
> Hi,
>
> On Sun, Oct 30, 2016 at 12:53:02PM +0100, Christophe JAILLET wrote:
>> BTW, memory allocation in 'sun4i_layers_init()' looks spurious, especially
>> the use of 'layer' in the for loop.
>> Just my 2 cents.
> What do you mean by it's spurious?
Hi Maxime,
what I mean is:
> struct sun4i_layer **sun4i_layers_init(struct drm_device *drm)
> {
> struct sun4i_drv *drv = drm->dev_private;
> struct sun4i_layer **layers;
> int i;
>
> layers = devm_kcalloc(drm->dev, ARRAY_SIZE(sun4i_backend_planes),
> sizeof(**layers), GFP_KERNEL);
Here, we allocate some memory for ARRAY_SIZE(sun4i_backend_planes) (i.e.
2) 'struct sun4i_layer'.
We do not allocate some space for some pointers but for some structure.
Also, these structures are zeroed and seem to never be initialized by
anything else.
> if (!layers)
> return ERR_PTR(-ENOMEM);
>
> /*
> * The hardware is a bit unusual here.
> *
> * Even though it supports 4 layers, it does the composition
> * in two separate steps.
> *
> * The first one is assigning a layer to one of its two
> * pipes. If more that 1 layer is assigned to the same pipe,
> * and if pixels overlaps, the pipe will take the pixel from
> * the layer with the highest priority.
> *
> * The second step is the actual alpha blending, that takes
> * the two pipes as input, and uses the eventual alpha
> * component to do the transparency between the two.
> *
> * This two steps scenario makes us unable to guarantee a
> * robust alpha blending between the 4 layers in all
> * situations. So we just expose two layers, one per pipe. On
> * SoCs that support it, sprites could fill the need for more
> * layers.
> */
The comment make me think that this driver (and this function) only
handles 2 layers ("So we just expose two layers"), which is consistent
with ARRAY_SIZE(sun4i_backend_planes) (i.e. 2)
So I would expect that only 2 'struct sun4i_layer' to be allcoated
> for (i = 0; i < ARRAY_SIZE(sun4i_backend_planes); i++) {
> const struct sun4i_plane_desc *plane = &sun4i_backend_planes[i];
> struct sun4i_layer *layer = layers[i];
Here, we take the address of one of the 2 structure allocated above.
This is overridden, just the line after.
>
> layer = sun4i_layer_init_one(drm, plane);
'sun4i_layer_init_one()' looks() like:
struct sun4i_layer *layer;
layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
...
return layer;
So we once more allocate some 'struct sun4i_layer'
BUT, the corresponding address is stored into the 'layer' variable, and
finally seems to get lost and no reference is kept of this. (i.e.
'layers' (with an s) is left unchanged)
> if (IS_ERR(layer)) {
> dev_err(drm->dev, "Couldn't initialize %s plane\n",
> i ? "overlay" : "primary");
> return ERR_CAST(layer);
> };
>
> DRM_DEBUG_DRIVER("Assigning %s plane to pipe %d\n",
> i ? "overlay" : "primary", plane->pipe);
> regmap_update_bits(drv->backend->regs,
SUN4I_BACKEND_ATTCTL_REG0(i),
> SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK,
> SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(plane->pipe));
>
> layer->id = i;
> };
>
> return layers;
> }
So, 4 'struct sun4i_layer' have been allocated. 2 in
'sun4i_layers_init()' and 2 in 'sun4i_layer_init_one()' (once at a time,
but called twice)
What looks spurious to me is either:
- 'struct sun4i_layer *layer = layers[i];' which should just be
'struct sun4i_layer *layer;'
or
- 'layers' (with an s) should be an array of pointers and the
addresses returned by 'sun4i_layer_init_one()' should be saved there.
I don't know at all this driver, so I'm maybe completely wrong.
What I would have expected would be something like: (un-tested, just to
give an idea)
==============8<================================================
@@ -133,9 +133,9 @@ struct sun4i_layer **sun4i_layers_init(struct
drm_device *drm)
struct sun4i_layer **layers;
int i;
layers = devm_kcalloc(drm->dev, ARRAY_SIZE(sun4i_backend_planes),
- sizeof(**layers), GFP_KERNEL);
+ sizeof(*layers), GFP_KERNEL);
if (!layers)
return ERR_PTR(-ENOMEM);
/*
@@ -160,16 +160,17 @@ struct sun4i_layer **sun4i_layers_init(struct
drm_device *drm)
* layers.
*/
for (i = 0; i < ARRAY_SIZE(sun4i_backend_planes); i++) {
const struct sun4i_plane_desc *plane = &sun4i_backend_planes[i];
- struct sun4i_layer *layer = layers[i];
+ struct sun4i_layer *layer;
layer = sun4i_layer_init_one(drm, plane);
if (IS_ERR(layer)) {
dev_err(drm->dev, "Couldn't initialize %s plane\n",
i ? "overlay" : "primary");
return ERR_CAST(layer);
};
+ layers[i] = layer;
DRM_DEBUG_DRIVER("Assigning %s plane to pipe %d\n",
i ? "overlay" : "primary", plane->pipe);
regmap_update_bits(drv->backend->regs,
SUN4I_BACKEND_ATTCTL_REG0(i),
Best regards,
CJ
^ permalink raw reply
* [PATCH] ARM: dts: imx6: Add support for Logic PD SOM and Baseboard
From: Shawn Guo @ 2016-11-05 7:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHCN7x+YopHVNxh4Vi5o1d=S3FFkoz45dNmgHMgs1sAQqaL77A@mail.gmail.com>
On Fri, Nov 04, 2016 at 12:44:21PM -0500, Adam Ford wrote:
> >> +&iomuxc {
> >> + imx6qdl-logicpd-baseboard {
> >> +
> >
> > Drop this container node and put the following pinctrl nodes directly
> > under &iomuxc.
> >
>
> Like the regulators above, if I remove this connector, the system
> won't boot. I compared both the regulator and the iomuxc containers
> in this device tree with other imx6q boards, and I seem to be
> consistent with what other boards are doing.
You might want to rebase the patch to latest mainline like v4.9-rc3 and
test first.
Shawn
^ permalink raw reply
* [PATCH v2 4/4] ARM: dts: imx28: Fix build warnings with W=1
From: Shawn Guo @ 2016-11-05 7:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5DbiHV-uR9bpdEFTfzDRXuWDao_RYxDCPJ1N=FuF4VCyQ@mail.gmail.com>
On Fri, Nov 04, 2016 at 06:51:06PM -0200, Fabio Estevam wrote:
> Hi Shawn,
>
> On Thu, Sep 8, 2016 at 11:03 AM, Shawn Guo <shawnguo@kernel.org> wrote:
> > On Mon, Sep 05, 2016 at 04:27:50PM -0300, Fabio Estevam wrote:
> >> diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
> >> index 0ebbc83..b4d4dbb 100644
> >> --- a/arch/arm/boot/dts/imx28-tx28.dts
> >> +++ b/arch/arm/boot/dts/imx28-tx28.dts
> >> @@ -35,7 +35,8 @@
> >> usbotg = &usb0;
> >> };
> >>
> >> - memory {
> >> + memory at 0 {
> >> + device_type = "memory";
> >> reg = <0 0>; /* will be filled in by U-Boot */
> >
> > I'm curious to know if the unit-address will be fixed up or not when
> > 'reg' property gets updated by U-Boot.
>
> Should I resend this series and keep imx28-tx28.dts unmodified?
Yeah, probably the best thing we can do.
Shawn
^ permalink raw reply
* [PATCH v2 1/2] ARM: imx: mmdc perf function support i.MX6QP
From: Shawn Guo @ 2016-11-05 7:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478109604-18323-1-git-send-email-Frank.Li@nxp.com>
On Wed, Nov 02, 2016 at 01:00:03PM -0500, Frank Li wrote:
> i.MX6QP added new reigster bit PROFILE_SEL in MADPCR0.
s/reigster/register
> need set it at perf start.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
We probably need a 'for' in patch subject after 'support'?
> ---
> V1 to V2: remove fsl_mmdc_devtype
>
> arch/arm/mach-imx/mmdc.c | 38 ++++++++++++++++++++++++++++++++------
> 1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
> index d82d14c..032cbe0 100644
> --- a/arch/arm/mach-imx/mmdc.c
> +++ b/arch/arm/mach-imx/mmdc.c
> @@ -44,6 +44,7 @@
> #define DBG_RST 0x2
> #define PRF_FRZ 0x4
> #define CYC_OVF 0x8
> +#define PROFILE_SEL 0x10
>
> #define MMDC_MADPCR0 0x410
> #define MMDC_MADPSR0 0x418
> @@ -55,10 +56,29 @@
>
> #define MMDC_NUM_COUNTERS 6
>
> +#define FSL_MMDC_QUIRK_PROFILE_SEL 0x1
> +
What about naming it MMDC_FLAG_PROFILE_SEL?
> #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
>
> static int ddr_type;
>
> +struct fsl_mmdc_devtype_data {
> + int driver_data;
> +};
What about the following?
struct imx_mmdc_data {
unsigned int flags;
};
> +
> +static struct fsl_mmdc_devtype_data imx6q_data = {
> +};
> +
> +static struct fsl_mmdc_devtype_data imx6qp_data = {
> + .driver_data = FSL_MMDC_QUIRK_PROFILE_SEL,
> +};
Have a const for better?
> +
> +static const struct of_device_id imx_mmdc_dt_ids[] = {
> + { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
> + { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
> + { /* sentinel */ }
> +};
> +
> #ifdef CONFIG_PERF_EVENTS
>
> static DEFINE_IDA(mmdc_ida);
> @@ -83,6 +103,7 @@ struct mmdc_pmu {
> struct device *dev;
> struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
> struct hlist_node node;
> + struct fsl_mmdc_devtype_data *devtype_data;
mmdc_data
> };
>
> /*
> @@ -307,6 +328,7 @@ static void mmdc_pmu_event_start(struct perf_event *event, int flags)
> struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
> struct hw_perf_event *hwc = &event->hw;
> void __iomem *mmdc_base, *reg;
> + int val;
Shouldn't it be u32 for better?
Shawn
>
> mmdc_base = pmu_mmdc->mmdc_base;
> reg = mmdc_base + MMDC_MADPCR0;
> @@ -321,7 +343,12 @@ static void mmdc_pmu_event_start(struct perf_event *event, int flags)
> local64_set(&hwc->prev_count, 0);
>
> writel(DBG_RST, reg);
> - writel(DBG_EN, reg);
> +
> + val = DBG_EN;
> + if (pmu_mmdc->devtype_data->driver_data & FSL_MMDC_QUIRK_PROFILE_SEL)
> + val |= PROFILE_SEL;
> +
> + writel(val, reg);
> }
>
> static int mmdc_pmu_event_add(struct perf_event *event, int flags)
> @@ -436,6 +463,8 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
> char *name;
> int mmdc_num;
> int ret;
> + const struct of_device_id *of_id =
> + of_match_device(imx_mmdc_dt_ids, &pdev->dev);
>
> pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL);
> if (!pmu_mmdc) {
> @@ -450,6 +479,8 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
> name = devm_kasprintf(&pdev->dev,
> GFP_KERNEL, "mmdc%d", mmdc_num);
>
> + pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
> +
> hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
> HRTIMER_MODE_REL);
> pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler;
> @@ -524,11 +555,6 @@ int imx_mmdc_get_ddr_type(void)
> return ddr_type;
> }
>
> -static const struct of_device_id imx_mmdc_dt_ids[] = {
> - { .compatible = "fsl,imx6q-mmdc", },
> - { /* sentinel */ }
> -};
> -
> static struct platform_driver imx_mmdc_driver = {
> .driver = {
> .name = "imx-mmdc",
> --
> 2.5.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 00/22] mtd: nand: return error code of nand_scan(_ident, _tail) on error
From: Marek Vasut @ 2016-11-05 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478256190-7452-1-git-send-email-yamada.masahiro@socionext.com>
On 11/04/2016 11:42 AM, Masahiro Yamada wrote:
>
> nand_scan(), nand_scan_ident(), nand_scan_tail() return
> an appropriate negative value on error.
>
> Most of drivers return the value from them on error,
> but some of them return the fixed error code -ENXIO
> (and a few return -ENODEV).
>
> This series make those drivers return more precise error code.
>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Nice cleanup, thanks!
--
Best regards,
Marek Vasut
^ permalink raw reply
* [PATCH V2 2/2] ARM: dts: add new compatible stream for i.MX6QP mmdc
From: Shawn Guo @ 2016-11-05 7:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478109604-18323-2-git-send-email-Frank.Li@nxp.com>
On Wed, Nov 02, 2016 at 01:00:04PM -0500, Frank Li wrote:
> mmdc of i.MX6QP are little difference with i.MX6Q.
> added new compatible stream fsl,imx6qp-mmdc
s/stream/string
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> No change for this patch.
> suspend resume code need fsl,imx6q-mmdc
You should probably add such info into commit log, e.g. although
MMDC has a slightly different programming model between imx6q and imx6qp
in terms of perf support, it's exactly same for suspend support, so we
have fsl,imx6q-mmdc here to save patching suspend driver with the new
compatible.
>
> arch/arm/boot/dts/imx6qp.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
> index 886dbf2..e0fdd0f 100644
> --- a/arch/arm/boot/dts/imx6qp.dtsi
> +++ b/arch/arm/boot/dts/imx6qp.dtsi
> @@ -85,5 +85,12 @@
> pcie: pcie at 0x01000000 {
> compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
> };
> +
> + aips-bus at 02100000 {
> + mmdc0: mmdc at 021b0000 { /* MMDC0 */
> + compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
> + reg = <0x021b0000 0x4000>;
> + };
> + };
It seems that pcie already went wrong, but please still try to add
devices in order of unit-address.
Shawn
> };
> };
> --
> 2.5.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2 1/1] ARM: dmaengine: sun6i: share the dma driver with sun50i
From: Hao Zhang @ 2016-11-05 8:05 UTC (permalink / raw)
To: linux-arm-kernel
Add soc a64 dma support.
Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
drivers/dma/sun6i-dma.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 8346199..00fcfc7 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -1028,11 +1028,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
.nr_max_vchans = 34,
};
+/*
+ * The A64 has 8 physical channels, a maximum DRQ port id of 27,
+ * and a total of 38 usable source and destination endpoints.
+ */
+
+static struct sun6i_dma_config sun50i_a64_dma_cfg = {
+ .nr_max_channels = 8,
+ .nr_max_requests = 27,
+ .nr_max_vchans = 38,
+};
+
static const struct of_device_id sun6i_dma_match[] = {
{ .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
{ .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
{ .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
+ { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun6i_dma_match);
@@ -1110,6 +1122,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)
sdc->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+
+ if (of_device_is_compatible(pdev->dev.of_node,
+ "allwinner,sun50i-a64-dma")) {
+ sdc->slave.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+ sdc->slave.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+ }
+
sdc->slave.directions = BIT(DMA_DEV_TO_MEM) |
BIT(DMA_MEM_TO_DEV);
sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
--
2.7.4
^ permalink raw reply related
* [PATCH v2] ARM: dts: imx53-qsb: Fix regulator constraints
From: Shawn Guo @ 2016-11-05 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477580804-1423-1-git-send-email-fabio.estevam@nxp.com>
On Thu, Oct 27, 2016 at 01:06:44PM -0200, Fabio Estevam wrote:
> Since commit fa93fd4ecc9c ("regulator: core: Ensure we are at least in
> bounds for our constraints") the imx53-qsb board populated with a Dialog
> DA9053 PMIC fails to boot:
>
> LDO3: Bringing 3300000uV into 1800000-1800000uV
>
> The LDO3 voltage constraints passed in the device tree do not match
> the valid range according to the datasheet, so fix this accordingly to
> allow the board booting again.
>
> While at it, fix the other voltage constraints as well.
>
> Cc: <stable@vger.kernel.org> # 4.7.x
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied, thanks.
^ permalink raw reply
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