* [crypto] [marvell-cesa] Possible regression after Linux 4.7
From: radioconfusion at gmail.com @ 2016-11-07 8:53 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
Thu, 3 Nov 2016 14:57:06 +0100, Romain Perier wrote:
>
> > Do you have any improvement for the issue?
> > Please let me know if you need any help to resolve it.
> >
> > Best Regards,
> > Jussi
> >
>
> Sorry for the delay.
> Could you try to revert locally commit
> 2786cee8e50bb4b4303dc22665f391b72318fa84 (crypto: marvell - Move SRAM
> I/O operations to step functions) ?
>
> It seems to fix most of the issues I had with curl.
> I will continue to investigate, that's just to confirm if it fixes the
> issues for you.
>
Thanks for this suggestion.
Unfortunately, I didn't get improvements using curl with this revertion.
Thanks for your investigation. Waiting for your input.
Best Regards,
Jussi
^ permalink raw reply
* [PATCH v7 2/2] ARM: EXYNOS: refactoring of mach-exynos to enable chipid driver
From: Arnd Bergmann @ 2016-11-07 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478347427-28409-3-git-send-email-pankaj.dubey@samsung.com>
On Saturday, November 5, 2016 5:33:47 PM CET Pankaj Dubey wrote:
> This patch enables chipid driver for ARCH_EXYNOS and refactors
> machine code for using chipid driver for identification of
> SoC ID and SoC rev.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> arch/arm/mach-exynos/Kconfig | 1 +
> arch/arm/mach-exynos/common.h | 92 ----------------------------
> arch/arm/mach-exynos/exynos.c | 31 ----------
> arch/arm/mach-exynos/firmware.c | 10 +--
> arch/arm/mach-exynos/include/mach/map.h | 21 -------
> arch/arm/mach-exynos/platsmp.c | 22 ++++---
> arch/arm/mach-exynos/pm.c | 41 ++++++++-----
> arch/arm/plat-samsung/cpu.c | 14 -----
> arch/arm/plat-samsung/include/plat/cpu.h | 2 -
> arch/arm/plat-samsung/include/plat/map-s5p.h | 2 -
> 10 files changed, 47 insertions(+), 189 deletions(-)
> delete mode 100644 arch/arm/mach-exynos/include/mach/map.h
Nice code removal!
> -
> static void __init exynos_init_io(void)
> {
> debug_ll_io_init();
> -
> - of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
> -
> - /* detect cpu id and rev. */
> - s5p_init_cpu(S5P_VA_CHIPID);
> }
This is now the default for .map_io, so you can remove the rest of the
function as well and do
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 757fc11de30d..808872981f45 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -234,7 +234,6 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
.l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fffff,
.smp = smp_ops(exynos_smp_ops),
- .map_io = exynos_init_io,
.init_early = exynos_firmware_init,
.init_irq = exynos_init_irq,
.init_machine = exynos_dt_machine_init,
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index fd6da54..a9f8504e 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -44,7 +44,7 @@ static int exynos_do_idle(unsigned long mode)
> writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
> sysram_ns_base_addr + 0x24);
> writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
> - if (soc_is_exynos3250()) {
> + if (of_machine_is_compatible("samsung,exynos3250")) {
> flush_cache_all();
> exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
> SMC_POWERSTATE_IDLE, 0);
I'd rather not see a proliferation of many such checks. Please try
to rework it to have fewer checks, e.g. by having a separate instance
of "struct firmware_ops" for each incompatible variant and making the
decision once.
>
> +static struct soc_device_attribute exynos4210_rev11[] = {
> + { .soc_id = "EXYNOS4210", .revision = "11", },
> + { },
> +};
> +
> static void __iomem *cpu_boot_reg_base(void)
> {
> - if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> + if (soc_device_match(exynos4210_rev11))
> return pmu_base_addr + S5P_INFORM5;
> return sysram_base_addr;
> }
> @@ -182,9 +187,10 @@ static inline void __iomem *cpu_boot_reg(int cpu)
> boot_reg = cpu_boot_reg_base();
> if (!boot_reg)
> return IOMEM_ERR_PTR(-ENODEV);
> - if (soc_is_exynos4412())
> + if (of_machine_is_compatible("samsung,exynos4412"))
> boot_reg += 4*cpu;
> - else if (soc_is_exynos5420() || soc_is_exynos5800())
> + else if (of_machine_is_compatible("samsung,exynos5420") ||
> + of_machine_is_compatible("samsung,exynos5800"))
> boot_reg += 4;
> return boot_reg;
> }
Same here, it would be nicer to rework the code to compute the address
once while called from a place where you already know this information
and then store the register address.
>
> +static struct soc_device_attribute exynos4210_rev11[] = {
> + { .soc_id = "EXYNOS4210", .revision = "11", },
> + { },
> +};
> +
> +static struct soc_device_attribute exynos4210_rev10[] = {
> + { .soc_id = "EXYNOS4210", .revision = "10", },
> + { },
> +};
Please use a single 'soc_device_attribute' table and make use
of the .data field to encode the difference.
Arnd
^ permalink raw reply related
* [PATCH 1/1] pinctrl: st: st_pinconf_dbg_show wrong format string
From: Patrice Chotard @ 2016-11-07 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161105142515.4377-1-xypron.glpk@gmx.de>
On 11/05/2016 03:25 PM, Heinrich Schuchardt wrote:
> function is defined as unsigned int.
> So we need %u to print it.
>
> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> ---
> drivers/pinctrl/pinctrl-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index b7bb371..8308f15 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -1006,7 +1006,7 @@ static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>
> function = st_pctl_get_pin_function(pc, offset);
> if (function)
> - snprintf(f, 10, "Alt Fn %d", function);
> + snprintf(f, 10, "Alt Fn %u", function);
> else
> snprintf(f, 5, "GPIO");
>
>
Hi Heinrich
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
^ permalink raw reply
* [PATCH 1/1] pinctrl: st: st_pctl_dt_parse_groups simplify expression
From: Patrice Chotard @ 2016-11-07 9:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161105143515.4668-1-xypron.glpk@gmx.de>
On 11/05/2016 03:35 PM, Heinrich Schuchardt wrote:
> for_each_property_of_node(pins, pp) checks that pp is not NULL.
> So there is no need to check it inside the loop.
>
> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> ---
> drivers/pinctrl/pinctrl-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 8308f15..676efcc 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -1181,7 +1181,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
> if (!strcmp(pp->name, "name"))
> continue;
>
> - if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
> + if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
> npins++;
> } else {
> pr_warn("Invalid st,pins in %s node\n", np->name);
>
Hi Heinrich
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
^ permalink raw reply
* [RESEND PATCH v1 0/6] Support GICv3 ITS in 32-bit mode
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series introduces GICv3 ITS to 32-bit world. Since I'm limited
with real world 32-bit platforms which uses ITS it was tested with
help of vITS on 64-bit host running 32-bit guest.
I used Andrea's its/v8 branch at [1] with following option passed to
kvmtool: --aarch32 --irqchip=gicv3-its --force-pci
[1] git://www.linux-arm.org/kvmtool.git
Changelog:
RFC -> v1
- rebased on 4.9-rc2, gits_read_typer() has been dropped
- spilt ITS and vITS in separate patch sets
Vladimir Murzin (6):
irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility
irqchip/gic-v3-its: Narrow down Entry Size when used as a divider
irqchip/gicv3-its: Specialise flush_dcache operation
irqchip/gicv3-its: Specialise readq and writeq accesses
ARM: gic-v3-its: Add 32bit support to GICv3 ITS
ARM: virt: Select ARM_GIC_V3_ITS
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch_gicv3.h | 54 +++++++++++++++++++++----
arch/arm64/include/asm/arch_gicv3.h | 17 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 75 +++++++++++++++++------------------
include/linux/irqchip/arm-gic-v3.h | 4 +-
5 files changed, 104 insertions(+), 47 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [RESEND PATCH v1 1/6] irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
Make sure that constants which are supposed to be applied on 64-bit
data is actually unsigned long long, so they won't be truncated when
used in 32-bit mode.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 28 ++++++++++++++--------------
include/linux/irqchip/arm-gic-v3.h | 4 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index c5dee30..bca125e 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -196,7 +196,7 @@ struct its_cmd_block {
static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
{
- cmd->raw_cmd[0] &= ~0xffUL;
+ cmd->raw_cmd[0] &= ~0xffULL;
cmd->raw_cmd[0] |= cmd_nr;
}
@@ -208,43 +208,43 @@ static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
{
- cmd->raw_cmd[1] &= ~0xffffffffUL;
+ cmd->raw_cmd[1] &= ~0xffffffffULL;
cmd->raw_cmd[1] |= id;
}
static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
{
- cmd->raw_cmd[1] &= 0xffffffffUL;
+ cmd->raw_cmd[1] &= 0xffffffffULL;
cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
}
static void its_encode_size(struct its_cmd_block *cmd, u8 size)
{
- cmd->raw_cmd[1] &= ~0x1fUL;
+ cmd->raw_cmd[1] &= ~0x1fULL;
cmd->raw_cmd[1] |= size & 0x1f;
}
static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
{
- cmd->raw_cmd[2] &= ~0xffffffffffffUL;
- cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
+ cmd->raw_cmd[2] &= ~0xffffffffffffULL;
+ cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL;
}
static void its_encode_valid(struct its_cmd_block *cmd, int valid)
{
- cmd->raw_cmd[2] &= ~(1UL << 63);
+ cmd->raw_cmd[2] &= ~(1ULL << 63);
cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
}
static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
{
- cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
- cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
+ cmd->raw_cmd[2] &= ~(0xffffffffULL << 16);
+ cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16));
}
static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
{
- cmd->raw_cmd[2] &= ~0xffffUL;
+ cmd->raw_cmd[2] &= ~0xffffULL;
cmd->raw_cmd[2] |= col;
}
@@ -657,8 +657,8 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
its = its_dev->its;
addr = its->phys_base + GITS_TRANSLATER;
- msg->address_lo = addr & ((1UL << 32) - 1);
- msg->address_hi = addr >> 32;
+ msg->address_lo = lower_32_bits(addr);
+ msg->address_hi = upper_32_bits(addr);
msg->data = its_get_event_id(d);
iommu_dma_map_msi_msg(d->irq, msg);
@@ -935,9 +935,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
}
if (val != tmp) {
- pr_err("ITS@%pa: %s doesn't stick: %lx %lx\n",
+ pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
&its->phys_base, its_base_type_string[type],
- (unsigned long) val, (unsigned long) tmp);
+ val, tmp);
free_pages((unsigned long)base, order);
return -ENXIO;
}
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index b7e3431..5118d3a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -239,7 +239,7 @@
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HWCOLLCNT_SHIFT 24
-#define GITS_CBASER_VALID (1UL << 63)
+#define GITS_CBASER_VALID (1ULL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT (10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
@@ -265,7 +265,7 @@
#define GITS_BASER_NR_REGS 8
-#define GITS_BASER_VALID (1UL << 63)
+#define GITS_BASER_VALID (1ULL << 63)
#define GITS_BASER_INDIRECT (1ULL << 62)
#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v1 2/6] irqchip/gic-v3-its: Narrow down Entry Size when used as a divider
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
GITS_BASER<n>'s Entry Size is much smaller than 64-bit, but when it
used as a divider it forces compiler to generate __aeabi_uldivmod if
build in 32-bit mode. So, casting it to int (like it is done in other
places) where used as a divider would give a hint to compiler that
32-bit division can be used.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index bca125e..312dd55 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -948,7 +948,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
- &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / tmp),
+ &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
its_base_type_string[type],
(unsigned long)virt_to_phys(base),
indirect ? "indirect" : "flat", (int)esz,
@@ -983,7 +983,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
* which is reported by ITS hardware times lvl1 table
* entry size.
*/
- ids -= ilog2(psz / esz);
+ ids -= ilog2(psz / (int)esz);
esz = GITS_LVL1_ENTRY_SIZE;
}
}
@@ -998,7 +998,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
new_order = max_t(u32, get_order(esz << ids), new_order);
if (new_order >= MAX_ORDER) {
new_order = MAX_ORDER - 1;
- ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / esz);
+ ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n",
&its->phys_base, its->device_ids, ids);
}
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v1 3/6] irqchip/gicv3-its: Specialise flush_dcache operation
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
It'd be better to switch to CMA... but before that done redirect
flush_dcache operation, so 32-bit implementation could be wired
latter.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm64/include/asm/arch_gicv3.h | 3 +++
drivers/irqchip/irq-gic-v3-its.c | 17 ++++++++---------
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index f8ae6d6..4f0402a 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -79,6 +79,7 @@
#include <linux/stringify.h>
#include <asm/barrier.h>
+#include <asm/cacheflush.h>
#define read_gicreg(r) \
({ \
@@ -187,5 +188,7 @@ static inline void gic_write_bpr1(u32 val)
#define gic_read_typer(c) readq_relaxed(c)
#define gic_write_irouter(v, c) writeq_relaxed(v, c)
+#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_GICV3_H */
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 312dd55..b2a6e7b 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -37,7 +37,6 @@
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic-v3.h>
-#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/exception.h>
@@ -433,7 +432,7 @@ static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
* the ITS.
*/
if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
- __flush_dcache_area(cmd, sizeof(*cmd));
+ gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
else
dsb(ishst);
}
@@ -602,7 +601,7 @@ static void lpi_set_config(struct irq_data *d, bool enable)
* Humpf...
*/
if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
- __flush_dcache_area(cfg, sizeof(*cfg));
+ gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
else
dsb(ishst);
its_send_inv(its_dev, id);
@@ -817,7 +816,7 @@ static int __init its_alloc_lpi_tables(void)
LPI_PROPBASE_SZ);
/* Make sure the GIC will observe the written configuration */
- __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
+ gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
return 0;
}
@@ -910,7 +909,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
shr = tmp & GITS_BASER_SHAREABILITY_MASK;
if (!shr) {
cache = GITS_BASER_nC;
- __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
}
goto retry_baser;
}
@@ -1102,7 +1101,7 @@ static void its_cpu_init_lpis(void)
}
/* Make sure the GIC will observe the zero-ed page */
- __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
+ gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
paddr = page_to_phys(pend_page);
pr_info("CPU%d: using LPI pending table @%pa\n",
@@ -1287,13 +1286,13 @@ static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
/* Flush Lvl2 table to PoC if hw doesn't support coherency */
if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
- __flush_dcache_area(page_address(page), baser->psz);
+ gic_flush_dcache_to_poc(page_address(page), baser->psz);
table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
/* Flush Lvl1 entry to PoC if hw doesn't support coherency */
if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
- __flush_dcache_area(table + idx, GITS_LVL1_ENTRY_SIZE);
+ gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
/* Ensure updated table contents are visible to ITS hardware */
dsb(sy);
@@ -1340,7 +1339,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
return NULL;
}
- __flush_dcache_area(itt, sz);
+ gic_flush_dcache_to_poc(itt, sz);
dev->its = its;
dev->itt = itt;
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v1 4/6] irqchip/gicv3-its: Specialise readq and writeq accesses
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
readq and writeq type of assessors are not supported in AArch32, so we
need to specialise them and glue later with series of 32-bit accesses
on AArch32 side.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm64/include/asm/arch_gicv3.h | 14 ++++++++++++++
drivers/irqchip/irq-gic-v3-its.c | 24 ++++++++++++------------
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 4f0402a..022523b 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -190,5 +190,19 @@ static inline void gic_write_bpr1(u32 val)
#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
+#define gits_read_baser(c) readq_relaxed(c)
+#define gits_write_baser(v, c) writeq_relaxed(v, c)
+
+#define gits_read_cbaser(c) readq_relaxed(c)
+#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
+
+#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
+
+#define gicr_read_propbaser(c) readq_relaxed(c)
+#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
+
+#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
+#define gicr_read_pendbaser(c) readq_relaxed(c)
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_GICV3_H */
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index b2a6e7b..69b040f 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -835,7 +835,7 @@ static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
{
u32 idx = baser - its->tables;
- return readq_relaxed(its->base + GITS_BASER + (idx << 3));
+ return gits_read_baser(its->base + GITS_BASER + (idx << 3));
}
static void its_write_baser(struct its_node *its, struct its_baser *baser,
@@ -843,7 +843,7 @@ static void its_write_baser(struct its_node *its, struct its_baser *baser,
{
u32 idx = baser - its->tables;
- writeq_relaxed(val, its->base + GITS_BASER + (idx << 3));
+ gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
baser->val = its_read_baser(its, baser);
}
@@ -1125,8 +1125,8 @@ static void its_cpu_init_lpis(void)
GICR_PROPBASER_WaWb |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
- writeq_relaxed(val, rbase + GICR_PROPBASER);
- tmp = readq_relaxed(rbase + GICR_PROPBASER);
+ gicr_write_propbaser(val, rbase + GICR_PROPBASER);
+ tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
@@ -1138,7 +1138,7 @@ static void its_cpu_init_lpis(void)
val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_nC;
- writeq_relaxed(val, rbase + GICR_PROPBASER);
+ gicr_write_propbaser(val, rbase + GICR_PROPBASER);
}
pr_info_once("GIC: using cache flushing for LPI property table\n");
gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
@@ -1149,8 +1149,8 @@ static void its_cpu_init_lpis(void)
GICR_PENDBASER_InnerShareable |
GICR_PENDBASER_WaWb);
- writeq_relaxed(val, rbase + GICR_PENDBASER);
- tmp = readq_relaxed(rbase + GICR_PENDBASER);
+ gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
+ tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
@@ -1160,7 +1160,7 @@ static void its_cpu_init_lpis(void)
val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
GICR_PENDBASER_CACHEABILITY_MASK);
val |= GICR_PENDBASER_nC;
- writeq_relaxed(val, rbase + GICR_PENDBASER);
+ gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
}
/* Enable LPIs */
@@ -1716,8 +1716,8 @@ static int __init its_probe_one(struct resource *res,
(ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
GITS_CBASER_VALID);
- writeq_relaxed(baser, its->base + GITS_CBASER);
- tmp = readq_relaxed(its->base + GITS_CBASER);
+ gits_write_cbaser(baser, its->base + GITS_CBASER);
+ tmp = gits_read_cbaser(its->base + GITS_CBASER);
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
@@ -1729,13 +1729,13 @@ static int __init its_probe_one(struct resource *res,
baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
GITS_CBASER_CACHEABILITY_MASK);
baser |= GITS_CBASER_nC;
- writeq_relaxed(baser, its->base + GITS_CBASER);
+ gits_write_cbaser(baser, its->base + GITS_CBASER);
}
pr_info("ITS: using cache flushing for cmd queue\n");
its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
}
- writeq_relaxed(0, its->base + GITS_CWRITER);
+ gits_write_cwriter(0, its->base + GITS_CWRITER);
writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
err = its_init_domain(handle, its);
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v1 5/6] ARM: gic-v3-its: Add 32bit support to GICv3 ITS
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
Wire-up flush_dcache, readq- and writeq-like gic-v3-its assessors, so
GICv3 ITS gets all it needs to be built and run.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm/include/asm/arch_gicv3.h | 54 ++++++++++++++++++++++++++++++++-----
1 file changed, 47 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index a808829..2747590 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <asm/barrier.h>
+#include <asm/cacheflush.h>
#include <asm/cp15.h>
#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
@@ -230,19 +231,14 @@ static inline void gic_write_bpr1(u32 val)
* AArch32, since the syndrome register doesn't provide any information for
* them.
* Consequently, the following IO helpers use 32bit accesses.
- *
- * There are only two registers that need 64bit accesses in this driver:
- * - GICD_IROUTERn, contain the affinity values associated to each interrupt.
- * The upper-word (aff3) will always be 0, so there is no need for a lock.
- * - GICR_TYPER is an ID register and doesn't need atomicity.
*/
-static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
+static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
{
writel_relaxed((u32)val, addr);
writel_relaxed((u32)(val >> 32), addr + 4);
}
-static inline u64 gic_read_typer(const volatile void __iomem *addr)
+static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
{
u64 val;
@@ -251,5 +247,49 @@ static inline u64 gic_read_typer(const volatile void __iomem *addr)
return val;
}
+#define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
+
+/*
+ * GICD_IROUTERn, contain the affinity values associated to each interrupt.
+ * The upper-word (aff3) will always be 0, so there is no need for a lock.
+ */
+#define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GICR_TYPER is an ID register and doesn't need atomicity.
+ */
+#define gic_read_typer(c) __gic_readq_nonatomic(c)
+
+/*
+ * GITS_BASER - hi and lo bits may be accessed independently.
+ */
+#define gits_read_baser(c) __gic_readq_nonatomic(c)
+#define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
+ * won't be being used during any updates and can be changed non-atomically
+ */
+#define gicr_read_propbaser(c) __gic_readq_nonatomic(c)
+#define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c)
+#define gicr_read_pendbaser(c) __gic_readq_nonatomic(c)
+#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GITS_TYPER is an ID register and doesn't need atomicity.
+ */
+#define gits_read_typer(c) __gic_readq_nonatomic(c)
+
+/*
+ * GITS_CBASER - hi and lo bits may be accessed independently.
+ */
+#define gits_read_cbaser(c) __gic_readq_nonatomic(c)
+#define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GITS_CWRITER - hi and lo bits may be accessed independently.
+ */
+#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
+
#endif /* !__ASSEMBLY__ */
#endif /* !__ASM_ARCH_GICV3_H */
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v1 6/6] ARM: virt: Select ARM_GIC_V3_ITS
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
This patch allows ARM guests to use GICv3 ITS on an arm64 host
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b5d529f..caef684 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -703,6 +703,7 @@ config ARCH_VIRT
select ARM_GIC
select ARM_GIC_V2M if PCI
select ARM_GIC_V3
+ select ARM_GIC_V3_ITS if PCI
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
--
1.7.9.5
^ permalink raw reply related
* [linux-sunxi] Re: [RFC PATCH] ARM: dts: add panel and tcon nodes to Allwinner A33 Q8 tablet dts
From: Hans de Goede @ 2016-11-07 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2578261478451207@web24j.yandex.ru>
Hi,
On 06-11-16 17:53, Icenowy Zheng wrote:
>
>
> 06.11.2016, 22:27, "Hans de Goede" <hdegoede@redhat.com>:
>> Hi,
>>
>> On 06-11-16 12:11, Icenowy Zheng wrote:
>>> All A33 Q8 tablets features a LCD panel, with a resolution of either
>>> 800x480 or 1024x600.
>>>
>>> Add "bone" device nodes to the device tree.
>>
>> Bone ?
>>
>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>>
>> He, as discussed in the other thread since sun8i-a33-q8-tablet.dts
>> is used for both 800x480 and 1024x600 versions we really need to
>> introduce new sun8i-a33-q8-tablet-800x600.dts and
>> sun8i-a33-q8-tablet-1024x600.dts files, which include
>> sun8i-a33-q8-tablet.dts and then add just the panel bits; and patch
>> newer u-boots to use those instead.
>>
>> This way people who stick with an old u-boot will just not get
>> the drm driver, rather then all of a sudden getting a wrong
>> resolution.
>>
>> Icenowy, can you please also submit a matching u-boot patch
>> (both the new dts file, as well as updating the defconfig you
>> use to the new dts file)?
>
> Could you choose a compatible for 1024x600 variant?
Lets just add a sun8i-a33-q8-tablet-800x600.dts now and then
I will add a sun8i-a33-q8-tablet-1024x600.dts file later.
Regards,
Hans
>
> (Since I have never such a Q8 tablet)
>
>>
>> Regards,
>>
>> Hans
>>
>>> ---
>>>
>>> Maybe it will be better to add them to sun8i-q8-reference-tablet.dtsi, as
>>> these pin configurations are part of reference design of both A23 and A33,
>>> not only restricted to Q8.
>>>
>>> The DTS file is tested by me, after cherry-picks this patch from Chen-Yu Tsai:
>>> https://github.com/wens/linux/commit/2823b887a289fbee5f97f3c6b45ed6c74a6368c6
>>>
>>> And add these commands to my U-Boot boot command:
>>>
>>> fdt addr 0x43000000
>>> fdt resize
>>> fdt set /panel compatible "urt,umsh-8596md-t"
>>> fdt set /panel status "okay"
>>> fdt set /display-engine status "okay"
>>> fdt set /soc at 01c00000/lcd-controller at 01c0c000 status "okay"
>>>
>>> arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 44 +++++++++++++++++++++++++++++++
>>> 1 file changed, 44 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>>> index b0bc236..871a20c 100644
>>> --- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>>> +++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>>> @@ -47,4 +47,48 @@
>>> / {
>>> model = "Q8 A33 Tablet";
>>> compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
>>> +
>>> + panel: panel {
>>> + /* compatible should be set according to the panel */
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&lcd_en_q8>;
>>> + backlight = <&backlight>;
>>> + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
>>> + power-supply = <®_dc1sw>;
>>> + status = "disabled";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + port at 0 {
>>> + reg = <0>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + panel_input: endpoint at 0 {
>>> + reg = <0>;
>>> + remote-endpoint = <&tcon0_out_lcd>;
>>> + };
>>> + };
>>> + };
>>> +};
>>> +
>>> +&tcon0 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&lcd_rgb666_pins>;
>>> +};
>>> +
>>> +&tcon0_out {
>>> + tcon0_out_lcd: endpoint at 0 {
>>> + reg = <0>;
>>> + remote-endpoint = <&panel_input>;
>>> + };
>>> +};
>>> +
>>> +&pio {
>>> + lcd_en_q8: lcd_en at 0 {
>>> + allwinner,pins = "PH7";
>>> + allwinner,function = "gpio_out";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> };
>
^ permalink raw reply
* [PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state
From: Geert Uytterhoeven @ 2016-11-07 9:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161104194914.GB16026@codeaurora.org>
Hi Stephen,
On Fri, Nov 4, 2016 at 8:49 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 11/02, Geert Uytterhoeven wrote:
>> On Tue, Nov 1, 2016 at 12:25 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> >
>> > Would the pull requests for clk also have dts changes at the base
>> > of the tree? Perhaps clk side can just ack the clk patches and
>>
>> Yes they would: this is moving functionality from platform code to DT.
>> Without the DT updates, it will break bisection (except for R-Car Gen2,
>> where we have fallback code to handle old DTBs).
>>
>> > then have it all routed through arm-soc? The only worry I have is
>> > if we need to make some sort of change in clk side that conflicts
>> > with these changes. I don't usually like taking dts changes
>> > through clk tree, so I'd like to avoid that if possible.
>>
>> Everything could go through arm-soc only with your Acked-by.
>> However, there are new clock drivers pending on this series.
>> Either they have to go through arm-soc, too, or this series would
>> be pulled into the clk tree with these new clock drivers.
>>
>> > Part E could happen anytime after everything else happens, so
>> > that doesn't seem like a concern.
>>
>> Part E can indeed by postponed.
>> But if parts A-D are applied together, there's no reason to postpone part E.
>>
>> > Part C could also be made to
>> > only call into the new reset drivers if the reset dts nodes are
>> > present? If that's done then we could merge clk patches anytime
>> > and remove the dead code and the node search at some later time
>> > when everything has settled?
>>
>> That would require adding more backwards compatibility code for
>> old DTBs, even for platform where we're not interested in maintaining
>> that. In addition, Part C depends on the header file for the reset driver
>> to compile the clock driver, even if you would add some DT detection,
>> and on the reset driver to link. So I'm afraid this is not feasible.
>
> TL;DR: Sounds fine, I'll be on the lookout for the PR.
Thank you very much!
> Longer version: Let me step back a bit and actually think about
> this longer than 2 minutes. From what I see
> rcar_rst_read_mode_pins() already returns -ENODEV if the nodes
> aren't present. Great.
>
> So clk tree could be given a pull for the clk patches, part C, on
> top of part A, the reset driver. If the rcar_rst_read_mode_pins()
> returns failure because the node is missing, we fall back to the
> old style of doing things. Some drivers already do that anyway,
For R-Car Gen2, we want to keep backwards compatibility for a while.
But not for the others, and I didn't want to add more code that was going
to be removed again soon.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6]
From: Linus Walleij @ 2016-11-07 9:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478097481-14895-2-git-send-email-andrew@aj.id.au>
On Wed, Nov 2, 2016 at 3:37 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> If a pin depending on bit 6 in SCU90 is requested for GPIO, the export
> will succeed but changes to the GPIO's value will not be accepted by the
> hardware. This is because the pinmux driver has misconfigured the SCU by
> writing 1 to the reserved bit.
>
> The description of SCU90[6] from the datasheet is 'Reserved, must keep
> at value ?0?'. The fix is to switch pinmux from the bit-flipping macro
> to explicitly configuring the .enable and .disable values to zero.
>
> The patch has been tested on an AST2500 EVB.
>
> Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver)
> Reported-by: Uma Yadlapati <yadlapat@us.ibm.com>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>
> This patch should be applied for 4.9.
Patch applied for fixes, adding Joel's review tag.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6]
From: Linus Walleij @ 2016-11-07 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACPK8Xcbv5VjE9deETV6zC4cPSfeBSgP96QYqV_ebAgtB9Jwtw@mail.gmail.com>
On Thu, Nov 3, 2016 at 11:59 PM, Joel Stanley <joel@jms.id.au> wrote:
> In the future I think we should send fixes separately from the rest of
> the series, so it's clear to Linus where we expect patches to end up.
>
> Perhaps Linus can share his preference with us?
Just make it clear to me where the patch is headed, if it is
a fix or a new feature.
Also mixing stuff in big series is of course problematic because
all the CC:in on MFD patches and whatnot that I don't apply
makes the picture blurry, but sometimes it is anyways needed
for context so it is a soft requirement.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 0/7] soc: renesas: Identify SoC and register with the SoC bus
From: Geert Uytterhoeven @ 2016-11-07 9:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477913455-5314-1-git-send-email-geert+renesas@glider.be>
On Mon, Oct 31, 2016 at 12:30 PM, Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> Some Renesas SoCs may exist in different revisions, providing slightly
> different functionalities (e.g. R-Car H3 ES1.x and ES2.0), and behavior
> (errate and quirks). This needs to be catered for by drivers and/or
> platform code. The recently proposed soc_device_match() API seems like
> a good fit to handle this.
>
> This patch series implements the core infrastructure to provide SoC and
> revision information through the SoC bus for Renesas ARM SoCs. It
> consists of 7 patches:
> - Patches 1-4 provide soc_device_match(), with some related fixes,
> - Patches 5-7 implement identification of Renesas SoCs and
> registration with the SoC bus,
>
> Changes compared to v1:
> - Add Acked-by,
> - New patches:
> - "[4/7] base: soc: Provide a dummy implementation of
> soc_device_match()",
> - "[5/7] ARM: shmobile: Document DT bindings for CCCR and PRR",
> - "[6/7] arm64: dts: r8a7795: Add device node for PRR"
> (more similar patches available, I'm not yet spamming you all
> with them),
> - Drop SoC families and family names; use fixed "Renesas" instead,
> - Drop EMEV2, which doesn't have a chip ID register, and doesn't share
> devices with other SoCs,
> - Drop RZ/A1H and R-CAR M1A, which don't have chip ID registers (for
> M1A: not accessible from the ARM core?),
> - On arm, move "select SOC_BUS" from ARCH_RENESAS to Kconfig symbols
> for SoCs that provide a chip ID register,
> - Build renesas-soc only if SOC_BUS is enabled,
> - Use "renesas,prr" and "renesas,cccr" device nodes in DT if
> available, else fall back to hardcoded addresses for compatibility
> with existing DTBs,
> - Remove verification of product IDs; just print the ID instead,
> - Don't register the SoC bus if the chip ID register is missing,
> - Change R-Mobile APE6 fallback to use PRR instead of CCCR (it has
> both).
>
> Merge strategy:
> - In theory, patches 1-4 should go through Greg's driver core tree.
> But it's a hard dependency for all users.
> If people agree, I can provide an immutable branch in my
> renesas-drivers repository, to be merged by all interested parties.
> So far I'm aware of Freescale/NXP, and Renesas.
And Samsung.
Shall I create the immutable branch now?
Thanks!
> - Patches 5-7 obviously have to go through Simon's Renesas tree (after
> merging the soc_device_match() core), and arm-soc.
>
> Tested on (machine, soc_id, optional revision):
> EMEV2 KZM9D Board, emev2
> Genmai, r7s72100
> APE6EVM, r8a73a4, ES1.0
> armadillo 800 eva, r8a7740, ES2.0
> bockw, r8a7778
> marzen, r8a7779, ES1.0
> Lager, r8a7790, ES1.0
> Koelsch, r8a7791, ES1.0
> Porter, r8a7791, ES3.0
> Blanche, r8a7792, ES1.1
> Gose, r8a7793, ES1.0
> Alt, r8a7794, ES1.0
> Renesas Salvator-X board based on r8a7795, r8a7795, ES1.0
> Renesas Salvator-X board based on r8a7795, r8a7795, ES1.1
> Renesas Salvator-X board based on r8a7796, r8a7796, ES1.0
> KZM-A9-GT, sh73a0, ES2.0
>
> For your convenience, this series (incl. more DT updates to add device
> nodes for CCCR and PRR to all other Renesas ARM SoCs) is also available
> in the topic/renesas-soc-id-v2 branch of my renesas-drivers git
> repository at
> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
> Its first user is support for R-Car H3 ES2.0 in branch
> topic/r8a7795-es2-v1-rebased2.
>
> Thanks for your comments!
>
> Arnd Bergmann (1):
> base: soc: Introduce soc_device_match() interface
>
> Geert Uytterhoeven (6):
> base: soc: Early register bus when needed
> base: soc: Check for NULL SoC device attributes
> base: soc: Provide a dummy implementation of soc_device_match()
> ARM: shmobile: Document DT bindings for CCCR and PRR
> arm64: dts: r8a7795: Add device node for PRR
> soc: renesas: Identify SoC and register with the SoC bus
>
> Documentation/devicetree/bindings/arm/shmobile.txt | 26 +++++
> arch/arm/mach-shmobile/Kconfig | 3 +
> arch/arm64/Kconfig.platforms | 1 +
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +
> drivers/base/Kconfig | 1 +
> drivers/base/soc.c | 79 +++++++++++++
> drivers/soc/renesas/Makefile | 2 +
> drivers/soc/renesas/renesas-soc.c | 130 +++++++++++++++++++++
> include/linux/sys_soc.h | 9 ++
> 9 files changed, 256 insertions(+)
> create mode 100644 drivers/soc/renesas/renesas-soc.c
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [BUG] pinctrl: sunxi: sunxi-pinctrl fail to load with CONFIG_DEBUG_TEST_DRIVER_REMOVE
From: Chen-Yu Tsai @ 2016-11-07 9:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161107081832.GA23580@Red>
Hi,
On Mon, Nov 7, 2016 at 4:18 PM, LABBE Corentin
<clabbe.montjoie@gmail.com> wrote:
> Hello
>
> With CONFIG_DEBUG_TEST_DRIVER_REMOVE=y pinctrl-sunxi fail to load on the second try.
>
> [ 3.900061] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver
> [ 3.916251] gpio gpiochip1: GPIO integer space overlap, cannot add chip
> [ 3.923016] gpiochip_add_data: GPIOs 0..223 (1c20800.pinctrl) failed to register
> [ 3.931099] sun8i-h3-pinctrl: probe of 1c20800.pinctrl failed with error -16
> [ 3.944709] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver
> [ 3.960796] gpio gpiochip2: GPIO integer space overlap, cannot add chip
> [ 3.967594] gpiochip_add_data: GPIOs 352..383 (1f02c00.pinctrl) failed to register
> [ 3.975633] sun8i-h3-r-pinctrl: probe of 1f02c00.pinctrl failed with error -16
>
> Without it, all subsequent drivers fail to load.
> Tested on Orange PI PC board.
I don't think the pinctrl drivers were designed to be removed.
And I thought the lack of a .remove callback in the driver blocks
the core from removing the device? Maybe I remember wrong...
ChenYu
>
> Regards
^ permalink raw reply
* [BUG] pinctrl: sunxi: sunxi-pinctrl fail to load with CONFIG_DEBUG_TEST_DRIVER_REMOVE
From: Maxime Ripard @ 2016-11-07 9:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65MHBUwWzcqwPYDtFNxgGnMECUMjHdZNOv6YPP4HVzwTw@mail.gmail.com>
On Mon, Nov 07, 2016 at 05:48:43PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Mon, Nov 7, 2016 at 4:18 PM, LABBE Corentin
> <clabbe.montjoie@gmail.com> wrote:
> > Hello
> >
> > With CONFIG_DEBUG_TEST_DRIVER_REMOVE=y pinctrl-sunxi fail to load on the second try.
> >
> > [ 3.900061] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver
> > [ 3.916251] gpio gpiochip1: GPIO integer space overlap, cannot add chip
> > [ 3.923016] gpiochip_add_data: GPIOs 0..223 (1c20800.pinctrl) failed to register
> > [ 3.931099] sun8i-h3-pinctrl: probe of 1c20800.pinctrl failed with error -16
> > [ 3.944709] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver
> > [ 3.960796] gpio gpiochip2: GPIO integer space overlap, cannot add chip
> > [ 3.967594] gpiochip_add_data: GPIOs 352..383 (1f02c00.pinctrl) failed to register
> > [ 3.975633] sun8i-h3-r-pinctrl: probe of 1f02c00.pinctrl failed with error -16
> >
> > Without it, all subsequent drivers fail to load.
> > Tested on Orange PI PC board.
>
> I don't think the pinctrl drivers were designed to be removed.
> And I thought the lack of a .remove callback in the driver blocks
> the core from removing the device? Maybe I remember wrong...
Using a builtin_platform_driver should be enough to prevent it to be
removed.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v8 0/3] ARM, arm64: renesas: Enable UHS-I SDR-104
From: Simon Horman @ 2016-11-07 9:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161105114501.GC1581@katana>
On Sat, Nov 05, 2016 at 12:45:02PM +0100, Wolfram Sang wrote:
>
> > To aid review the following git branches are provided:
> > * This patchset:
> > https:://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/sdr104-integration-v8
> > * This patch-set and above dependency
> > https:://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/sdr104-v8
>
> driver-v8 is there, but those two are not. Forgot to push out? :)
Sorry about that, they should be there now.
^ permalink raw reply
* [BUG] pinctrl: sunxi: sunxi-pinctrl fail to load with CONFIG_DEBUG_TEST_DRIVER_REMOVE
From: Chen-Yu Tsai @ 2016-11-07 9:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161107095612.ih5ns24m2qiwujy5@lukather>
On Mon, Nov 7, 2016 at 5:56 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Mon, Nov 07, 2016 at 05:48:43PM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Mon, Nov 7, 2016 at 4:18 PM, LABBE Corentin
>> <clabbe.montjoie@gmail.com> wrote:
>> > Hello
>> >
>> > With CONFIG_DEBUG_TEST_DRIVER_REMOVE=y pinctrl-sunxi fail to load on the second try.
>> >
>> > [ 3.900061] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver
>> > [ 3.916251] gpio gpiochip1: GPIO integer space overlap, cannot add chip
>> > [ 3.923016] gpiochip_add_data: GPIOs 0..223 (1c20800.pinctrl) failed to register
>> > [ 3.931099] sun8i-h3-pinctrl: probe of 1c20800.pinctrl failed with error -16
>> > [ 3.944709] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver
>> > [ 3.960796] gpio gpiochip2: GPIO integer space overlap, cannot add chip
>> > [ 3.967594] gpiochip_add_data: GPIOs 352..383 (1f02c00.pinctrl) failed to register
>> > [ 3.975633] sun8i-h3-r-pinctrl: probe of 1f02c00.pinctrl failed with error -16
>> >
>> > Without it, all subsequent drivers fail to load.
>> > Tested on Orange PI PC board.
>>
>> I don't think the pinctrl drivers were designed to be removed.
>> And I thought the lack of a .remove callback in the driver blocks
>> the core from removing the device? Maybe I remember wrong...
>
> Using a builtin_platform_driver should be enough to prevent it to be
> removed.
Labbe, can you test it again on linux-next? Or at least with this patch
0c8c6ba00cbf pinctrl: sunxi: make bool drivers explicitly non-modular
from linux-pinctrl applied. This should fix it.
ChenYu
^ permalink raw reply
* [BUG] pinctrl: sunxi: sunxi-pinctrl fail to load with CONFIG_DEBUG_TEST_DRIVER_REMOVE
From: Corentin Labbe @ 2016-11-07 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161107095612.ih5ns24m2qiwujy5@lukather>
On Mon, Nov 07, 2016 at 10:56:12AM +0100, Maxime Ripard wrote:
> On Mon, Nov 07, 2016 at 05:48:43PM +0800, Chen-Yu Tsai wrote:
> > Hi,
> >
> > On Mon, Nov 7, 2016 at 4:18 PM, LABBE Corentin
> > <clabbe.montjoie@gmail.com> wrote:
> > > Hello
> > >
> > > With CONFIG_DEBUG_TEST_DRIVER_REMOVE=y pinctrl-sunxi fail to load on the second try.
> > >
> > > [ 3.900061] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver
> > > [ 3.916251] gpio gpiochip1: GPIO integer space overlap, cannot add chip
> > > [ 3.923016] gpiochip_add_data: GPIOs 0..223 (1c20800.pinctrl) failed to register
> > > [ 3.931099] sun8i-h3-pinctrl: probe of 1c20800.pinctrl failed with error -16
> > > [ 3.944709] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver
> > > [ 3.960796] gpio gpiochip2: GPIO integer space overlap, cannot add chip
> > > [ 3.967594] gpiochip_add_data: GPIOs 352..383 (1f02c00.pinctrl) failed to register
> > > [ 3.975633] sun8i-h3-r-pinctrl: probe of 1f02c00.pinctrl failed with error -16
> > >
> > > Without it, all subsequent drivers fail to load.
> > > Tested on Orange PI PC board.
> >
> > I don't think the pinctrl drivers were designed to be removed.
> > And I thought the lack of a .remove callback in the driver blocks
> > the core from removing the device? Maybe I remember wrong...
>
> Using a builtin_platform_driver should be enough to prevent it to be
> removed.
>
The problem is that it is already builtin_platform_driver()
^ permalink raw reply
* [PATCH] staging: vc04_services: add vchiq_pagelist_info structure
From: Greg KH @ 2016-11-07 10:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161031081035.22677-1-mzoran@crowfest.net>
On Mon, Oct 31, 2016 at 01:10:35AM -0700, Michael Zoran wrote:
> The current dma_map_sg based implementation for bulk messages
> computes many offsets into a single allocation multiple times in
> both the create and free code paths. This is inefficient,
> error prone and in fact still has a few lingering issues
> with arm64.
>
> This change replaces a small portion of that inplementation with
> new code that uses a new struct vchiq_pagelist_info to store the
> needed information rather then complex offset calculations.
>
> This improved implementation should be more efficient and easier
> to understand and maintain.
>
> Tests Run(Both Pass):
> vchiq_test -p 1
> vchiq_test -f 10
>
> Signed-off-by: Michael Zoran <mzoran@crowfest.net>
> ---
> .../interface/vchiq_arm/vchiq_2835_arm.c | 223 +++++++++++----------
> 1 file changed, 113 insertions(+), 110 deletions(-)
This doesn't apply to the tree anymore because of your previous patch :(
Can you refresh it and resend?
thanks,
greg k-h
^ permalink raw reply
* [PATCH v3 0/6] ASoC: sun4i-codec: Add support for A31 Codec
From: Chen-Yu Tsai @ 2016-11-07 10:06 UTC (permalink / raw)
To: linux-arm-kernel
Hi everyone,
This is v3 of my Allwinner A31 audio codec support series. These are
the remaining driver patches not yet merged, with 1 new fix, and the
dts file patches.
The A31's internal codec is similar (in terms of DMA, interface and
control layouts) to the one found in the A10/A13/A20 SoCs. However
it has more external inputs and outputs, the mixer controls are now
stereo (left/right separated), and it also has some audio processing
features (not supported yet).
Changes since v2:
- Added patch """ASoC: sun4i-codec: Add "Right Mixer" to "Line Out
Mono Diff." route""" which fixes line out when all the sources
have their left channel muted.
- Dropped unused codec_pa_pin from A31 hummingbird dts patch.
In the past we always provided a pinmux setting for GPIOs used, to
avoid accidentally muxing a pin that was already used for GPIO, or
vice versa. The pinctrl subsystem now supports exclusive use of a
pin for GPIO, which the sunxi platform wants to migrate to. This
drops the requirement of the explicit pinmux setting for GPIOs.
- Added Maxime's Acked-by for the two existing patches from v2.
After these are merged I plan to submit patches to support the audio
codec found in Allwinner's A23 and H3 SoCs.
Regards
ChenYu
Chen-Yu Tsai (6):
ASoC: sun4i-codec: Add support for optional reset control to quirks
ASoC: sun4i-codec: Add support for A31 ADC capture path
ASoC: sun4i-codec: Add "Right Mixer" to "Line Out Mono Diff." route
ARM: dts: sun6i: Add audio codec device node
ARM: dts: sun6i: hummingbird: Enable internal audio codec
ARM: dts: sun6i: sina31s: Enable internal audio codec
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 13 ++++
arch/arm/boot/dts/sun6i-a31.dtsi | 13 ++++
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 8 +++
sound/soc/sunxi/sun4i-codec.c | 94 ++++++++++++++++++++++++++++-
4 files changed, 127 insertions(+), 1 deletion(-)
--
2.10.2
^ permalink raw reply
* [PATCH v3 1/6] ASoC: sun4i-codec: Add support for optional reset control to quirks
From: Chen-Yu Tsai @ 2016-11-07 10:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161107100703.5586-1-wens@csie.org>
The later Allwinner SoCs have a dedicated reset controller, and
peripherals have dedicated reset controls which need to be deasserted
before the associated peripheral can be used.
Add support for this to the quirks structure and probe/remove functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
sound/soc/sunxi/sun4i-codec.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index 1934db29b2b5..b28b82a5ec62 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -30,6 +30,7 @@
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/regmap.h>
+#include <linux/reset.h>
#include <linux/gpio/consumer.h>
#include <sound/core.h>
@@ -217,6 +218,7 @@ struct sun4i_codec {
struct regmap *regmap;
struct clk *clk_apb;
struct clk *clk_module;
+ struct reset_control *rst;
struct gpio_desc *gpio_pa;
/* ADC_FIFOC register is at different offset on different SoCs */
@@ -1167,6 +1169,7 @@ struct sun4i_codec_quirks {
struct reg_field reg_adc_fifoc; /* used for regmap_field */
unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
+ bool has_reset;
};
static const struct sun4i_codec_quirks sun4i_codec_quirks = {
@@ -1262,6 +1265,14 @@ static int sun4i_codec_probe(struct platform_device *pdev)
return PTR_ERR(scodec->clk_module);
}
+ if (quirks->has_reset) {
+ scodec->rst = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(scodec->rst)) {
+ dev_err(&pdev->dev, "Failed to get reset control\n");
+ return PTR_ERR(scodec->rst);
+ }
+ };
+
scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
GPIOD_OUT_LOW);
if (IS_ERR(scodec->gpio_pa)) {
@@ -1288,6 +1299,16 @@ static int sun4i_codec_probe(struct platform_device *pdev)
return -EINVAL;
}
+ /* Deassert the reset control */
+ if (scodec->rst) {
+ ret = reset_control_deassert(scodec->rst);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Failed to deassert the reset control\n");
+ goto err_clk_disable;
+ }
+ }
+
/* DMA configuration for TX FIFO */
scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
scodec->playback_dma_data.maxburst = 8;
@@ -1302,7 +1323,7 @@ static int sun4i_codec_probe(struct platform_device *pdev)
&sun4i_codec_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Failed to register our codec\n");
- goto err_clk_disable;
+ goto err_assert_reset;
}
ret = devm_snd_soc_register_component(&pdev->dev,
@@ -1339,6 +1360,9 @@ static int sun4i_codec_probe(struct platform_device *pdev)
err_unregister_codec:
snd_soc_unregister_codec(&pdev->dev);
+err_assert_reset:
+ if (scodec->rst)
+ reset_control_assert(scodec->rst);
err_clk_disable:
clk_disable_unprepare(scodec->clk_apb);
return ret;
@@ -1351,6 +1375,8 @@ static int sun4i_codec_remove(struct platform_device *pdev)
snd_soc_unregister_card(card);
snd_soc_unregister_codec(&pdev->dev);
+ if (scodec->rst)
+ reset_control_assert(scodec->rst);
clk_disable_unprepare(scodec->clk_apb);
return 0;
--
2.10.2
^ permalink raw reply related
* [PATCH v3 2/6] ASoC: sun4i-codec: Add support for A31 ADC capture path
From: Chen-Yu Tsai @ 2016-11-07 10:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161107100703.5586-1-wens@csie.org>
The A31's internal codec capture path has a mixer in front of the ADC
for each channel, capable of selecting various inputs, including
microphones, line in, phone in, and the main output mixer.
This patch adds the various controls, widgets and routes needed for
audio capture from the already supported inputs on the A31.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
sound/soc/sunxi/sun4i-codec.c | 65 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index b28b82a5ec62..6379efd21f00 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -788,6 +788,30 @@ static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = {
SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0),
};
+/* ADC mixer controls */
+static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = {
+ SOC_DAPM_DOUBLE("Mixer Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0),
+ SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0),
+ SOC_DAPM_DOUBLE("Line In Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0),
+ SOC_DAPM_DOUBLE("Mic1 Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0),
+ SOC_DAPM_DOUBLE("Mic2 Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0),
+};
+
/* headphone controls */
static const char * const sun6i_codec_hp_src_enum_text[] = {
"DAC", "Mixer",
@@ -887,6 +911,10 @@ static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = {
SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0,
sun6i_codec_mic_gain_scale),
+ SOC_DOUBLE_TLV("ADC Capture Volume",
+ SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG,
+ SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0,
+ sun6i_codec_out_mixer_pregain_scale),
};
static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
@@ -912,6 +940,23 @@ static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
/* Line In */
SND_SOC_DAPM_INPUT("LINEIN"),
+ /* Digital parts of the ADCs */
+ SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
+ SUN6I_CODEC_ADC_FIFOC_EN_AD, 0,
+ NULL, 0),
+
+ /* Analog parts of the ADCs */
+ SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_ADCLEN, 0),
+ SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_ADCREN, 0),
+
+ /* ADC Mixers */
+ SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
+ sun6i_codec_adc_mixer_controls),
+ SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
+ sun6i_codec_adc_mixer_controls),
+
/* Digital parts of the DACs */
SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
SUN4I_CODEC_DAC_DPC_EN_DA, 0,
@@ -975,6 +1020,20 @@ static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
{ "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
{ "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
+ /* Left ADC Mixer Routes */
+ { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
+ { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
+ { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
+ { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+ { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+
+ /* Right ADC Mixer Routes */
+ { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
+ { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
+ { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
+ { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+ { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+
/* Headphone Routes */
{ "Headphone Source Playback Route", "DAC", "Left DAC" },
{ "Headphone Source Playback Route", "DAC", "Right DAC" },
@@ -989,6 +1048,12 @@ static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
{ "Line Out Source Playback Route", "Stereo", "Right Mixer" },
{ "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
{ "LINEOUT", NULL, "Line Out Source Playback Route" },
+
+ /* ADC Routes */
+ { "Left ADC", NULL, "ADC Enable" },
+ { "Right ADC", NULL, "ADC Enable" },
+ { "Left ADC", NULL, "Left ADC Mixer" },
+ { "Right ADC", NULL, "Right ADC Mixer" },
};
static struct snd_soc_codec_driver sun6i_codec_codec = {
--
2.10.2
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