* [PATCH v4 2/2] pinctrl: samsung: Add GPF support for Exynos5433
From: Chanwoo Choi @ 2016-11-09 8:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478680811-24835-1-git-send-email-cw00.choi@samsung.com>
This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio at vger.kernel.org
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../devicetree/bindings/pinctrl/samsung-pinctrl.txt | 19 +++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-exynos.c | 6 ++++++
2 files changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index d49e22d2a8b5..1baf19eecabf 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -19,11 +19,30 @@ Required Properties:
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
+ - reg: Second base address of the pin controller if the specific registers
+ of the pin controller are separated into the different base address.
+
+ Eg: GPF[1-5] of Exynos5433 are separated into the two base address.
+ - First base address is for GPAx and GPF[1-5] external interrupt
+ registers.
+ - Second base address is for GPF[1-5] pinctrl registers.
+
+ pinctrl_0: pinctrl at 10580000 {
+ compatible = "samsung,exynos5433-pinctrl";
+ reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos7-wakeup-eint";
+ interrupts = <0 16 0>;
+ };
+ };
+
- Pin banks as child nodes: Pin banks of the controller are represented by child
nodes of the controller node. Bank name is taken from name of the node. Each
bank node must contain following properties:
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d657b52dfdb5..12f7d1eb65bc 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1339,6 +1339,11 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+ EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
+ EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
+ EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
+ EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
+ EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
};
/* pin banks of exynos5433 pin-controller - AUD */
@@ -1420,6 +1425,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
+ .nr_ext_resources = 1,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5433_pin_banks1,
--
1.9.1
^ permalink raw reply related
* [PATCH] arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllers
From: Gregory CLEMENT @ 2016-11-09 8:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161108174851.2cd8efb4@free-electrons.com>
Hi Marcin,
On mar., nov. 08 2016, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote:
> Hello,
>
> On Tue, 8 Nov 2016 17:31:32 +0100, Marcin Wojtas wrote:
>> Enabling SPI controllers, which are attached to different busses
>> inside an SoC, may result in overlapping enumeration and cause
>> sysfs registration failure. Example log after enabling two
>> controllers on Armada 8040 SoC with same identifiers:
>>
>> [ 3.740415] sysfs: cannot create duplicate filename
>> '/class/spi_master/spi0'
>> [ 3.747510] ------------[ cut here ]------------
>> [ 3.752145] WARNING: at fs/sysfs/dir.c:31
>> [...]
>> [ 4.002299] orion_spi: probe of f4700600.spi failed with error -17
>>
>> spi-orion driver offers dedicated DT property ('cell-index'), that
>> allow setting unique identifiers. Recently added support for CP110-slave
>> HW block introduced two new SPI controllers' nodes with same ID as
>> ones from CP110-master.
>>
>> This commit fixes the issue by assigning different 'cell-index' values
>> for CP110-slave SPI controllers.
>>
>> Fixes: 4eef78a0091b ("arm64: dts: marvell: add description for the slave
>> CP110 in Armada 8K")
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>
> It's sad that we need to hardcode those indexes in the Device Tree
> (which by no means are a description of the HW by the way), but that's
> what the SPI framework expects I believe. Therefore:
>
> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Applied on mvebu/fixes with acked-by from Thomas.
In the same time I also applied "arm64: dts: marvell: fix clocksource
for CP110 slave SPI0" which didn't find his way to mainline yet.
Thanks,
Gregory
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllers
From: Marcin Wojtas @ 2016-11-09 8:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8737j1m44b.fsf@free-electrons.com>
Thanks a lot!
Marcin
2016-11-09 9:47 GMT+01:00 Gregory CLEMENT <gregory.clement@free-electrons.com>:
> Hi Marcin,
>
> On mar., nov. 08 2016, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote:
>
>> Hello,
>>
>> On Tue, 8 Nov 2016 17:31:32 +0100, Marcin Wojtas wrote:
>>> Enabling SPI controllers, which are attached to different busses
>>> inside an SoC, may result in overlapping enumeration and cause
>>> sysfs registration failure. Example log after enabling two
>>> controllers on Armada 8040 SoC with same identifiers:
>>>
>>> [ 3.740415] sysfs: cannot create duplicate filename
>>> '/class/spi_master/spi0'
>>> [ 3.747510] ------------[ cut here ]------------
>>> [ 3.752145] WARNING: at fs/sysfs/dir.c:31
>>> [...]
>>> [ 4.002299] orion_spi: probe of f4700600.spi failed with error -17
>>>
>>> spi-orion driver offers dedicated DT property ('cell-index'), that
>>> allow setting unique identifiers. Recently added support for CP110-slave
>>> HW block introduced two new SPI controllers' nodes with same ID as
>>> ones from CP110-master.
>>>
>>> This commit fixes the issue by assigning different 'cell-index' values
>>> for CP110-slave SPI controllers.
>>>
>>> Fixes: 4eef78a0091b ("arm64: dts: marvell: add description for the slave
>>> CP110 in Armada 8K")
>>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>
>> It's sad that we need to hardcode those indexes in the Device Tree
>> (which by no means are a description of the HW by the way), but that's
>> what the SPI framework expects I believe. Therefore:
>>
>> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>
>
> Applied on mvebu/fixes with acked-by from Thomas.
> In the same time I also applied "arm64: dts: marvell: fix clocksource
> for CP110 slave SPI0" which didn't find his way to mainline yet.
>
> Thanks,
>
> Gregory
>
>
>>
>> Thomas
>> --
>> Thomas Petazzoni, CTO, Free Electrons
>> Embedded Linux and Kernel engineering
>> http://free-electrons.com
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
^ permalink raw reply
* [PATCH v2 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Baruch Siach @ 2016-11-09 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109081431.10115-2-romain.perier@free-electrons.com>
Hi Romain,
On Wed, Nov 09, 2016 at 09:14:29AM +0100, Romain Perier wrote:
> The Armada 3700 has two I2C controllers that is compliant with the I2C
> Bus Specificiation 2.1, supports multi-master and different bus speed:
> Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
> High speed mode (up to 3.4 Mhz).
>
> This IP block has a lot of similarity with the PXA, except some register
> offsets and bitfield. This commits adds a basic support for this I2C
> unit.
>
> Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
[...]
> @@ -122,7 +131,9 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
> #define ICR_SADIE (1 << 13) /* slave address detected int enable */
> #define ICR_UR (1 << 14) /* unit reset */
> #define ICR_FM (1 << 15) /* fast mode */
> +#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
> #define ICR_HS (1 << 16) /* High Speed mode */
> +#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
> #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
>
> #define ISR_RWM (1 << 0) /* read/write mode */
> @@ -193,6 +204,8 @@ struct pxa_i2c {
> unsigned char master_code;
> unsigned long rate;
> bool highmode_enter;
> + unsigned long fm_mask;
> + unsigned long hs_mask;
Do you really need 64bit for that?
baruch
> };
>
> #define _IBMR(i2c) ((i2c)->reg_ibmr)
> @@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
> writel(i2c->slave_addr, _ISAR(i2c));
>
> /* set control register values */
> - writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
> - writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
> + writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
> + writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
>
> #ifdef CONFIG_I2C_PXA_SLAVE
> dev_info(&i2c->adap.dev, "Enabling slave mode\n");
> @@ -1137,6 +1150,7 @@ static const struct of_device_id i2c_pxa_dt_ids[] = {
> { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
> { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
> { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
> + { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
> {}
> };
> MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
> @@ -1158,6 +1172,13 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
> i2c->use_pio = 1;
> if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
> i2c->fast_mode = 1;
> + if (of_device_is_compatible(np, "marvell,armada-3700-i2c")) {
> + i2c->fm_mask = ICR_BUSMODE_FM;
> + i2c->hs_mask = ICR_BUSMODE_HS;
> + } else {
> + i2c->fm_mask = ICR_FM;
> + i2c->hs_mask = ICR_HS;
> + }
>
> *i2c_types = (enum pxa_i2c_types)(of_id->data);
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply
* [PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver
From: John Garry @ 2016-11-09 9:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5821F491.1010603@gmail.com>
>>>> I'd suggest requiring #address-cells=<1> and #size-cells=<0> in the
>>>> master
>>>> node, and listing the children by reg property. If the address is not
>>>> easily expressed as a single integer, use a larger #address-cells
>>>> value.
>>> We already have something equivalent to reg in "module-id" (see patch
>>> 02/11), which is the slave device bus address; here's a sample:
>>> + /* For L3 cache PMU */
>>> + pmul3c0 {
>>> + compatible = "hisilicon,hisi-pmu-l3c-v1";
>>> + scl-id = <0x02>;
>>> + num-events = <0x16>;
>>> + num-counters = <0x08>;
>>> + module-id = <0x04>;
>>> + num-banks = <0x04>;
>>> + cfgen-map = <0x02 0x04 0x01 0x08>;
>>> + counter-reg = <0x170>;
>>> + evctrl-reg = <0x04>;
>>> + event-en = <0x1000000>;
>>> + evtype-reg = <0x140>;
>>> + };
>>>
>>> FYI, "module-id" is our own internal hw nomenclature.
>> Yes, that was my interpretation as well. Please use the standard
>> "reg" property for this then.
> Hi Arnd,
>
> Firstly my apologies for a mistake in the bindings example in ([PATCH
> 02/11 ..]).
> The module-id property is a list as defined in the PMU bindings patch
> ([PATCH v1 05/11] dt-bindings .. <https://lkml.org/lkml/2016/11/2/323>).
>
> + djtag0: djtag at 0 {
> + compatible = "hisilicon,hip05-cpu-djtag-v1";
> + pmul3c0 {
> + compatible = "hisilicon,hisi-pmu-l3c-v1";
> + scl-id = <0x02>;
> + num-events = <0x16>;
> + num-counters = <0x08>;
> + module-id = <0x04 0x04 0x04 0x04>;
> + num-banks = <0x04>;
> + cfgen-map = <0x02 0x04 0x01 0x08>;
> + counter-reg = <0x170>;
> + evctrl-reg = <0x04>;
> + event-en = <0x1000000>;
> + evtype-reg = <0x140>;
> + };
>
>
> The L3 cache in hip05/06/07 chips consist of 4 banks (each bank has PMU
> registers).
>
> In hip05/06 all L3 cache banks are identified with same module-id.
> module-id = <0x04 0x04 0x04 0x04>;
>
> But in the case hip07 chip(djtag v2), each L3 cache bank has different
> module-id
> module-id = <0x01 0x02 0x03 0x04>;
>
> So in this case Please share your opinion on how to model it.
>
My suggestion is to have a single PMU per module, whether that is 4
banks or 1 bank per module, as this makes the driver simpler.
I think you mentioned that a separate PMU per bank does not make much
sense, and you would rather treat all banks as a single bank and
aggregrate their perf statstics under a single PMU: Can you just use a
script in userspace which can do this aggregration work if you have
separate PMUs?
Maybe perf guys have a view on this also.
John
> Some more detail of L3 cache PMU.
> ------------------------------------------------
> The hip05/06/07 chips consists of a multiple Super CPU cluster (16 CPU
> cores). we call it SCCL.
> The L3 cache( 4 banks) is shared by all CPU cores in a SCCL.
> Each L3 cache bank has PMU registers. We always take the sum of the
> counters to show in perf.
> Taking individual L3 cache count is not meaningful as there is no
> mapping of CPU cores to individual
> L3 cache banks.
>
> Please share your suggestion.
>
> Thanks,
> Anurup
^ permalink raw reply
* [PATCH v2] spi: atmel: use managed resource for gpio chip select
From: Nicolas Ferre @ 2016-11-09 9:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161108174909.vnsw3zppiwpv2npo@piout.net>
Le 08/11/2016 ? 18:49, Alexandre Belloni a ?crit :
> On 08/11/2016 at 18:48:52 +0100, Nicolas Ferre wrote :
>> Use the managed gpio CS pin request so that we avoid having trouble
>> in the cleanup code.
>> In fact, if module was configured with DT, cleanup code released
>> invalid pin. Since resource wasn't freed, module cannot be reinserted.
>>
>> This require to extract the gpio request call from the "setup" function
>> and call it in the appropriate probe function.
>>
>> Reported-by: Alexander Morozov <linux@meltdown.ru>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>
> I think that's fine but I still have that item on my todo list
> (discussion in july 2014 with Mark):
>
> ---
>>> Mark: maybe it would make sense to do devm_gpio_request_one() in
>>> of_spi_register_master(), after of_get_named_gpio.
>
>> You need to transition all the drivers doing things manually but yes.
>> As I keep saying all the GPIO handling needs to be completely
>> refactored.
> ---
Would make sense indeed as we are currently doing the same node scanning
twice...
But this patch actually fixes an issue with module unloading/re-loading
and freeing of a wrong gpio. So I do think that we shouldn't hold its
adoption while thinking about this enhancement...
Regards,
>> ---
>> v2: fix devm_gpio_request location: the setup code for device was not proper
>> location. Move it to the probe function and add needed DT routines to
>> handle all CS gpio specified.
>>
>> drivers/spi/spi-atmel.c | 50 ++++++++++++++++++++++++++++++++++++++-----------
>> 1 file changed, 39 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
>> index 32683a13dd60..a60925614480 100644
>> --- a/drivers/spi/spi-atmel.c
>> +++ b/drivers/spi/spi-atmel.c
>> @@ -24,6 +24,7 @@
>>
>> #include <linux/io.h>
>> #include <linux/gpio.h>
>> +#include <linux/of_gpio.h>
>> #include <linux/pinctrl/consumer.h>
>> #include <linux/pm_runtime.h>
>>
>> @@ -1204,7 +1205,6 @@ static int atmel_spi_setup(struct spi_device *spi)
>> u32 csr;
>> unsigned int bits = spi->bits_per_word;
>> unsigned int npcs_pin;
>> - int ret;
>>
>> as = spi_master_get_devdata(spi->master);
>>
>> @@ -1247,16 +1247,9 @@ static int atmel_spi_setup(struct spi_device *spi)
>> if (!asd)
>> return -ENOMEM;
>>
>> - if (as->use_cs_gpios) {
>> - ret = gpio_request(npcs_pin, dev_name(&spi->dev));
>> - if (ret) {
>> - kfree(asd);
>> - return ret;
>> - }
>> -
>> + if (as->use_cs_gpios)
>> gpio_direction_output(npcs_pin,
>> !(spi->mode & SPI_CS_HIGH));
>> - }
>>
>> asd->npcs_pin = npcs_pin;
>> spi->controller_state = asd;
>> @@ -1471,13 +1464,11 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
>> static void atmel_spi_cleanup(struct spi_device *spi)
>> {
>> struct atmel_spi_device *asd = spi->controller_state;
>> - unsigned gpio = (unsigned long) spi->controller_data;
>>
>> if (!asd)
>> return;
>>
>> spi->controller_state = NULL;
>> - gpio_free(gpio);
>> kfree(asd);
>> }
>>
>> @@ -1499,6 +1490,39 @@ static void atmel_get_caps(struct atmel_spi *as)
>> }
>>
>> /*-------------------------------------------------------------------------*/
>> +static int atmel_spi_gpio_cs(struct platform_device *pdev)
>> +{
>> + struct spi_master *master = platform_get_drvdata(pdev);
>> + struct atmel_spi *as = spi_master_get_devdata(master);
>> + struct device_node *np = master->dev.of_node;
>> + int i;
>> + int ret = 0;
>> + int nb = 0;
>> +
>> + if (!as->use_cs_gpios)
>> + return 0;
>> +
>> + if (!np)
>> + return 0;
>> +
>> + nb = of_gpio_named_count(np, "cs-gpios");
>> + for (i = 0; i < nb; i++) {
>> + int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
>> + "cs-gpios", i);
>> +
>> + if (cs_gpio == -EPROBE_DEFER)
>> + return cs_gpio;
>> +
>> + if (gpio_is_valid(cs_gpio)) {
>> + ret = devm_gpio_request(&pdev->dev, cs_gpio,
>> + dev_name(&pdev->dev));
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>>
>> static int atmel_spi_probe(struct platform_device *pdev)
>> {
>> @@ -1577,6 +1601,10 @@ static int atmel_spi_probe(struct platform_device *pdev)
>> master->num_chipselect = 4;
>> }
>>
>> + ret = atmel_spi_gpio_cs(pdev);
>> + if (ret)
>> + goto out_unmap_regs;
>> +
>> as->use_dma = false;
>> as->use_pdc = false;
>> if (as->caps.has_dma_support) {
>> --
>> 2.9.0
>>
>
--
Nicolas Ferre
^ permalink raw reply
* [v16, 0/7] Fix eSDHC host version register bug
From: Wolfram Sang @ 2016-11-09 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478661252-42439-1-git-send-email-yangbo.lu@nxp.com>
Can you please update your CC list? There is nothing i2c related in this
patch series, so you could drop the i2c-list.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161109/022a8376/attachment.sig>
^ permalink raw reply
* [PATCH 0/6] USB support for Broadcom NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: linux-arm-kernel
This patch set contains the usb support for Broadcom NSP SoC.
The usb phy is connected through mdio interface. The mdio interface
can be used to access either internal phys or external phys using a
multiplexer.
The first patch provides the documentation details for mdio-mux and
second patch provides the documentation details for usb3 phy. The third
patch contains the mdio-mux support and fourth patch contains the
changes to the mdio bus driver.
The fifth patch provides the phy driver and sixth patch provides the
enable method for usb.
This patch series has been tested on NSP bcm958625HR board.
This patch series is based on v4.9.0-rc1 and is available from github-
repo: https://github.com/Broadcom/cygnus-linux.git
branch:nsp-usb-v1
Yendapally Reddy Dhananjaya Reddy (6):
dt-bindings: mdio-mux: Add documentation for mdio mux for NSP SoC
dt-bindings: phy: Add documentation for NSP USB3 PHY
net: mdio-mux: Add MDIO mux driver for NSP SoC
net: phy: Initialize mdio clock at probe function
phy: Add USB3 PHY support for Broadcom NSP SoC
arm: dts: nsp: Add USB nodes to device tree
.../devicetree/bindings/net/brcm,mdio-mux-nsp.txt | 57 +++++++
.../devicetree/bindings/phy/brcm,nsp-usb3-phy.txt | 39 +++++
arch/arm/boot/dts/bcm-nsp.dtsi | 57 +++++++
arch/arm/boot/dts/bcm958625k.dts | 16 ++
drivers/net/phy/Kconfig | 9 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-bcm-iproc.c | 6 +-
drivers/net/phy/mdio-mux-bcm-nsp.c | 121 ++++++++++++++
drivers/phy/Kconfig | 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-nsp-usb3.c | 176 +++++++++++++++++++++
11 files changed, 488 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
create mode 100644 Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
create mode 100644 drivers/net/phy/mdio-mux-bcm-nsp.c
create mode 100644 drivers/phy/phy-bcm-nsp-usb3.c
--
2.1.0
^ permalink raw reply
* [PATCH 1/6] dt-bindings: mdio-mux: Add documentation for mdio mux for NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Add documentation for mdio mux available in Broadcom NSP SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
.../devicetree/bindings/net/brcm,mdio-mux-nsp.txt | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
diff --git a/Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt b/Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
new file mode 100644
index 0000000..b749a2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
@@ -0,0 +1,57 @@
+Properties for an MDIO bus multiplexer available in Broadcom NSP SoC.
+
+This MDIO bus multiplexer defines buses that could access the internal
+phys as well as external to SoCs. When child bus is selected, one needs
+to select the below properties to generate desired MDIO transaction on
+appropriate bus.
+
+Required properties in addition to the generic multiplexer properties:
+
+MDIO multiplexer node:
+- compatible: brcm,mdio-mux-iproc.
+- reg: Should contain registers location and length.
+- reg-names: Should contain the resource reg names.
+ - bus-ctrl: mdio bus control register address space required to
+ select the bus master. This property is not required for SoC's
+ that doesn't provide master selection.
+ - mgmt-ctrl: mdio management control register address space
+
+Sub-nodes:
+ Each bus master should be represented as a sub-node.
+
+Sub-nodes required properties:
+- reg: Bus master number. Should be 0x10 to access the external mdio devices.
+- address-cells: should be 1
+- size-cells: should be 0
+
+Every non-ethernet PHY requires a compatible property so that it could be
+probed based on this compatible string.
+
+Additional information regarding generic multiplexer properties can be found
+at- Documentation/devicetree/bindings/net/mdio-mux.txt
+
+example:
+
+ mdio_mux: mdio-mux at 3f190 {
+ compatible = "brcm,mdio-mux-nsp";
+ reg = <0x3f190 0x4>,
+ <0x32000 0x4>;
+ reg-names = "bus-ctrl", "mgmt-ctrl";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio at 0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy at 10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
--
2.1.0
^ permalink raw reply related
* [PATCH 2/6] dt-bindings: phy: Add documentation for NSP USB3 PHY
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Add documentation for USB3 PHY available in Northstar plus SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
.../devicetree/bindings/phy/brcm,nsp-usb3-phy.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
new file mode 100644
index 0000000..30cf4b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
@@ -0,0 +1,39 @@
+Broadcom USB3 phy binding northstar plus SoC
+This is a child bus node of "brcm,mdio-mux-nsp" node.
+
+Required mdio bus properties:
+- reg: MDIO Bus number for the MDIO interface
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Required PHY properties:
+- compatible: should be "brcm,nsp-usb3-phy"
+- reg: Phy address in the MDIO interface
+- usb3-ctrl-syscon: handler of syscon node defining physical address
+ of usb3 control register.
+- #phy-cells: must be 0
+
+Required usb3 control properties:
+- compatible: should be "brcm,nsp-usb3-ctrl"
+- reg: offset and length of the control registers
+
+Example:
+
+ mdio at 0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy at 10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ }
+
+ usb3_ctrl: syscon at 104408 {
+ compatible = "brcm,nsp-usb3-ctrl", "syscon";
+ reg = <0x104408 0x3fc>;
+ };
--
2.1.0
^ permalink raw reply related
* [PATCH 3/6] net: mdio-mux: Add MDIO mux driver for NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
NSP SoC supports the mdio multiplexer which has the bus
selection logic.
This multiplexer has child buses for PCIe, USB. The bus
could be internal or external to SOC where PHYs are attached.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/net/phy/Kconfig | 9 +++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-mux-bcm-nsp.c | 121 +++++++++++++++++++++++++++++++++++++
3 files changed, 131 insertions(+)
create mode 100644 drivers/net/phy/mdio-mux-bcm-nsp.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 2651c8d..41cc583 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -63,6 +63,15 @@ config MDIO_BUS_MUX_BCM_IPROC
child MDIO bus to a parent bus. Buses could be internal as well as
external and selection logic lies inside the same multiplexer.
+config MDIO_BUS_MUX_BCM_NSP
+ tristate "Broadcom NSP MDIO bus controller"
+ depends on ARCH_BCM_NSP || COMPILE_TEST
+ depends on HAS_IOMEM && OF_MDIO
+ default ARCH_BCM_NSP
+ help
+ This module provides a driver MDIO multiplexing the busses available
+ in the Broadcom NSP SoC.
+
config MDIO_BUS_MUX_GPIO
tristate "GPIO controlled MDIO bus multiplexers"
depends on OF_GPIO && OF_MDIO
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index e58667d..d5969b2 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o
obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o
obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
+obj-$(CONFIG_MDIO_BUS_MUX_BCM_NSP) += mdio-mux-bcm-nsp.o
obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
diff --git a/drivers/net/phy/mdio-mux-bcm-nsp.c b/drivers/net/phy/mdio-mux-bcm-nsp.c
new file mode 100644
index 0000000..75dcb04
--- /dev/null
+++ b/drivers/net/phy/mdio-mux-bcm-nsp.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License version 2 (GPLv2) for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/mdio-mux.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+
+#define NSP_MDIO_EXT_BUS_START_ADDR 16
+#define NSP_MDIO_EXT_SELECT_BIT BIT(9)
+
+struct nsp_mdiomux_desc {
+ void __iomem *bus_ctrl;
+ void __iomem *mgmt_ctrl;
+ void *mux_handle;
+};
+
+static int mdio_mux_nsp_switch_fn(int current_child, int desired_child,
+ void *priv)
+{
+ struct nsp_mdiomux_desc *md = priv;
+ u32 data, bus_id;
+
+ /* select internal or external bus */
+ data = readl(md->mgmt_ctrl);
+ if (desired_child == NSP_MDIO_EXT_BUS_START_ADDR)
+ data |= NSP_MDIO_EXT_SELECT_BIT;
+ else
+ data &= ~NSP_MDIO_EXT_SELECT_BIT;
+ writel(data, md->mgmt_ctrl);
+
+ /* select bus number */
+ if (md->bus_ctrl) {
+ bus_id = desired_child & (NSP_MDIO_EXT_BUS_START_ADDR - 1);
+ writel(bus_id, md->bus_ctrl);
+ }
+
+ return 0;
+}
+
+static int mdio_mux_nsp_probe(struct platform_device *pdev)
+{
+ struct nsp_mdiomux_desc *md;
+ struct resource *res;
+ int ret;
+
+ md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL);
+ if (!md)
+ return -ENOMEM;
+
+ /* Bus control is not available in some SoC's */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus-ctrl");
+ if (res) {
+ md->bus_ctrl = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(md->bus_ctrl)) {
+ dev_err(&pdev->dev, "failed to ioremap register\n");
+ return PTR_ERR(md->bus_ctrl);
+ }
+ }
+
+ /* Get management control */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mgmt-ctrl");
+ if (!res)
+ return -EINVAL;
+
+ md->mgmt_ctrl = ioremap(res->start, resource_size(res));
+ if (!md->mgmt_ctrl)
+ return -ENOMEM;
+
+ ret = mdio_mux_init(&pdev->dev, mdio_mux_nsp_switch_fn,
+ &md->mux_handle, md, NULL);
+ if (ret != 0) {
+ iounmap(md->mgmt_ctrl);
+ return ret;
+ }
+
+ pdev->dev.platform_data = md;
+ return 0;
+}
+
+static int mdio_mux_nsp_remove(struct platform_device *pdev)
+{
+ struct nsp_mdiomux_desc *md = dev_get_platdata(&pdev->dev);
+
+ iounmap(md->mgmt_ctrl);
+ mdio_mux_uninit(md->mux_handle);
+ return 0;
+}
+
+static const struct of_device_id mdio_mux_nsp_match[] = {
+ { .compatible = "brcm,mdio-mux-nsp" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mdio_mux_nsp_match);
+
+static struct platform_driver mdio_mux_nsp_driver = {
+ .driver = {
+ .name = "mdio-mux-nsp",
+ .of_match_table = mdio_mux_nsp_match,
+ },
+ .probe = mdio_mux_nsp_probe,
+ .remove = mdio_mux_nsp_remove,
+};
+
+module_platform_driver(mdio_mux_nsp_driver);
+
+MODULE_DESCRIPTION("NSP MDIO Mux Bus Driver");
+MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com");
+MODULE_LICENSE("GPL v2");
--
2.1.0
^ permalink raw reply related
* [PATCH 4/6] net: phy: Initialize mdio clock at probe function
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Initialize mdio clock divisor in probe function. The ext bus
bit available in the same register will be used by mdio mux
to enable external mdio.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/net/phy/mdio-bcm-iproc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/mdio-bcm-iproc.c b/drivers/net/phy/mdio-bcm-iproc.c
index c0b4e65..46fe1ae 100644
--- a/drivers/net/phy/mdio-bcm-iproc.c
+++ b/drivers/net/phy/mdio-bcm-iproc.c
@@ -81,8 +81,6 @@ static int iproc_mdio_read(struct mii_bus *bus, int phy_id, int reg)
if (rc)
return rc;
- iproc_mdio_config_clk(priv->base);
-
/* Prepare the read operation */
cmd = (MII_DATA_TA_VAL << MII_DATA_TA_SHIFT) |
(reg << MII_DATA_RA_SHIFT) |
@@ -112,8 +110,6 @@ static int iproc_mdio_write(struct mii_bus *bus, int phy_id,
if (rc)
return rc;
- iproc_mdio_config_clk(priv->base);
-
/* Prepare the write operation */
cmd = (MII_DATA_TA_VAL << MII_DATA_TA_SHIFT) |
(reg << MII_DATA_RA_SHIFT) |
@@ -163,6 +159,8 @@ static int iproc_mdio_probe(struct platform_device *pdev)
bus->read = iproc_mdio_read;
bus->write = iproc_mdio_write;
+ iproc_mdio_config_clk(priv->base);
+
rc = of_mdiobus_register(bus, pdev->dev.of_node);
if (rc) {
dev_err(&pdev->dev, "MDIO bus registration failed\n");
--
2.1.0
^ permalink raw reply related
* [PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
This patch adds support for Broadcom NSP USB3 PHY
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/phy/Kconfig | 9 +++
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-nsp-usb3.c | 176 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 186 insertions(+)
create mode 100644 drivers/phy/phy-bcm-nsp-usb3.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index fe00f91..85cc556 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -489,4 +489,13 @@ config PHY_NS2_PCIE
help
Enable this to support the Broadcom Northstar2 PCIe PHY.
If unsure, say N.
+
+config PHY_NSP_USB3
+ tristate "Broadcom NorthStar plus USB3 PHY driver"
+ depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)
+ select GENERIC_PHY
+ default ARCH_BCM_NSP
+ help
+ Enable this to support the Broadcom Northstar plus USB3 PHY.
+ If unsure, say N.
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a534cf5..ba9b4c0 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
+obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.o
diff --git a/drivers/phy/phy-bcm-nsp-usb3.c b/drivers/phy/phy-bcm-nsp-usb3.c
new file mode 100644
index 0000000..0033382
--- /dev/null
+++ b/drivers/phy/phy-bcm-nsp-usb3.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mdio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+#define NSP_USB3_RST_CTRL_OFFSET 0x3f8
+
+/* mdio reg access */
+#define NSP_USB3_PHY_BASE_ADDR_REG 0x1f
+
+#define NSP_USB3_PHY_PLL30_BLOCK 0x8000
+#define NSP_USB3_PLL_CONTROL 0x01
+#define NSP_USB3_PLLA_CONTROL0 0x0a
+#define NSP_USB3_PLLA_CONTROL1 0x0b
+
+#define NSP_USB3_PHY_TX_PMD_BLOCK 0x8040
+#define NSP_USB3_TX_PMD_CONTROL1 0x01
+
+#define NSP_USB3_PHY_PIPE_BLOCK 0x8060
+#define NSP_USB3_LFPS_CMP 0x02
+#define NSP_USB3_LFPS_DEGLITCH 0x03
+
+struct nsp_usb3_phy {
+ struct regmap *usb3_ctrl;
+ struct phy *phy;
+ struct mdio_device *mdiodev;
+};
+
+static int nsp_usb3_phy_init(struct phy *phy)
+{
+ struct nsp_usb3_phy *iphy = phy_get_drvdata(phy);
+ struct mii_bus *bus = iphy->mdiodev->bus;
+ int addr = iphy->mdiodev->addr;
+ u32 data;
+ int rc;
+
+ rc = regmap_read(iphy->usb3_ctrl, 0, &data);
+ if (rc)
+ return rc;
+ data |= 1;
+ rc = regmap_write(iphy->usb3_ctrl, 0, data);
+ if (rc)
+ return rc;
+
+ rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 1);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_PLL30_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x1000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL0, 0x6400);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0xc000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0x8000);
+ if (rc)
+ return rc;
+
+ rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 0);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x9000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_PIPE_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_CMP, 0xf30d);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_DEGLITCH, 0x6302);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_TX_PMD_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_TX_PMD_CONTROL1, 0x1003);
+
+ return rc;
+}
+
+static struct phy_ops nsp_usb3_phy_ops = {
+ .init = nsp_usb3_phy_init,
+};
+
+static int nsp_usb3_phy_probe(struct mdio_device *mdiodev)
+{
+ struct device *dev = &mdiodev->dev;
+ struct phy_provider *provider;
+ struct nsp_usb3_phy *iphy;
+
+ iphy = devm_kzalloc(dev, sizeof(*iphy), GFP_KERNEL);
+ if (!iphy)
+ return -ENOMEM;
+ iphy->mdiodev = mdiodev;
+
+ iphy->usb3_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "usb3-ctrl-syscon");
+ if (IS_ERR(iphy->usb3_ctrl))
+ return PTR_ERR(iphy->usb3_ctrl);
+
+ iphy->phy = devm_phy_create(dev, dev->of_node, &nsp_usb3_phy_ops);
+ if (IS_ERR(iphy->phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(iphy->phy);
+ }
+
+ phy_set_drvdata(iphy->phy, iphy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "could not register PHY provider\n");
+ return PTR_ERR(provider);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id nsp_usb3_phy_of_match[] = {
+ {.compatible = "brcm,nsp-usb3-phy",},
+ { /* sentinel */ }
+};
+
+static struct mdio_driver nsp_usb3_phy_driver = {
+ .mdiodrv = {
+ .driver = {
+ .name = "nsp-usb3-phy",
+ .of_match_table = nsp_usb3_phy_of_match,
+ },
+ },
+ .probe = nsp_usb3_phy_probe,
+};
+
+mdio_module_driver(nsp_usb3_phy_driver);
+
+MODULE_DESCRIPTION("Broadcom NSP USB3 PHY driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com");
--
2.1.0
^ permalink raw reply related
* [PATCH 6/6] arm: dts: nsp: Add USB nodes to device tree
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Add USB nodes to the Northstar plus device tree file
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 57 ++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958625k.dts | 16 +++++++++++
2 files changed, 73 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 7c9e0fa..acdb576 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -249,6 +249,34 @@
status = "disabled";
};
+ xhci: usb at 29000 {
+ compatible = "generic-xhci";
+ reg = <0x29000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci0: usb at 2a000 {
+ compatible = "generic-ehci";
+ reg = <0x2a000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb at 2b000 {
+ compatible = "generic-ohci";
+ reg = <0x2b000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mdio: mdio at 32000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x32000 0x8>;
+ };
+
rng: rng at 33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
@@ -319,6 +347,30 @@
"sata2";
};
+ mdio_mux: mdio-mux at 3f190 {
+ compatible = "brcm,mdio-mux-nsp";
+ reg = <0x3f190 0x4>,
+ <0x32000 0x4>;
+ reg-names = "bus-ctrl", "mgmt-ctrl";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio at 0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy at 10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
pinctrl: pinctrl at 3f1c0 {
compatible = "brcm,nsp-pinmux";
reg = <0x3f1c0 0x04>,
@@ -367,6 +419,11 @@
phy-names = "sata-phy";
};
};
+
+ usb3_ctrl: syscon at 104408 {
+ compatible = "brcm,nsp-usb3-ctrl", "syscon";
+ reg = <0x104408 0x3fc>;
+ };
};
pcie0: pcie at 18012000 {
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 05c5f98..c7303fa 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -53,6 +53,22 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
--
2.1.0
^ permalink raw reply related
* [PATCH v2] spi: atmel: use managed resource for gpio chip select
From: Alexandre Belloni @ 2016-11-09 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8756e0f4-de7b-5d89-2561-ace18d157d91@atmel.com>
On 09/11/2016 at 10:16:18 +0100, Nicolas Ferre wrote :
> Le 08/11/2016 ? 18:49, Alexandre Belloni a ?crit :
> > On 08/11/2016 at 18:48:52 +0100, Nicolas Ferre wrote :
> >> Use the managed gpio CS pin request so that we avoid having trouble
> >> in the cleanup code.
> >> In fact, if module was configured with DT, cleanup code released
> >> invalid pin. Since resource wasn't freed, module cannot be reinserted.
> >>
> >> This require to extract the gpio request call from the "setup" function
> >> and call it in the appropriate probe function.
> >>
> >> Reported-by: Alexander Morozov <linux@meltdown.ru>
> >> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> >
> > I think that's fine but I still have that item on my todo list
> > (discussion in july 2014 with Mark):
> >
> > ---
> >>> Mark: maybe it would make sense to do devm_gpio_request_one() in
> >>> of_spi_register_master(), after of_get_named_gpio.
> >
> >> You need to transition all the drivers doing things manually but yes.
> >> As I keep saying all the GPIO handling needs to be completely
> >> refactored.
> > ---
>
> Would make sense indeed as we are currently doing the same node scanning
> twice...
>
> But this patch actually fixes an issue with module unloading/re-loading
> and freeing of a wrong gpio. So I do think that we shouldn't hold its
> adoption while thinking about this enhancement...
>
Yes, this patch is still useful as-is and fixes a bug.
> Regards,
>
> >> ---
> >> v2: fix devm_gpio_request location: the setup code for device was not proper
> >> location. Move it to the probe function and add needed DT routines to
> >> handle all CS gpio specified.
> >>
> >> drivers/spi/spi-atmel.c | 50 ++++++++++++++++++++++++++++++++++++++-----------
> >> 1 file changed, 39 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> >> index 32683a13dd60..a60925614480 100644
> >> --- a/drivers/spi/spi-atmel.c
> >> +++ b/drivers/spi/spi-atmel.c
> >> @@ -24,6 +24,7 @@
> >>
> >> #include <linux/io.h>
> >> #include <linux/gpio.h>
> >> +#include <linux/of_gpio.h>
> >> #include <linux/pinctrl/consumer.h>
> >> #include <linux/pm_runtime.h>
> >>
> >> @@ -1204,7 +1205,6 @@ static int atmel_spi_setup(struct spi_device *spi)
> >> u32 csr;
> >> unsigned int bits = spi->bits_per_word;
> >> unsigned int npcs_pin;
> >> - int ret;
> >>
> >> as = spi_master_get_devdata(spi->master);
> >>
> >> @@ -1247,16 +1247,9 @@ static int atmel_spi_setup(struct spi_device *spi)
> >> if (!asd)
> >> return -ENOMEM;
> >>
> >> - if (as->use_cs_gpios) {
> >> - ret = gpio_request(npcs_pin, dev_name(&spi->dev));
> >> - if (ret) {
> >> - kfree(asd);
> >> - return ret;
> >> - }
> >> -
> >> + if (as->use_cs_gpios)
> >> gpio_direction_output(npcs_pin,
> >> !(spi->mode & SPI_CS_HIGH));
> >> - }
> >>
> >> asd->npcs_pin = npcs_pin;
> >> spi->controller_state = asd;
> >> @@ -1471,13 +1464,11 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
> >> static void atmel_spi_cleanup(struct spi_device *spi)
> >> {
> >> struct atmel_spi_device *asd = spi->controller_state;
> >> - unsigned gpio = (unsigned long) spi->controller_data;
> >>
> >> if (!asd)
> >> return;
> >>
> >> spi->controller_state = NULL;
> >> - gpio_free(gpio);
> >> kfree(asd);
> >> }
> >>
> >> @@ -1499,6 +1490,39 @@ static void atmel_get_caps(struct atmel_spi *as)
> >> }
> >>
> >> /*-------------------------------------------------------------------------*/
> >> +static int atmel_spi_gpio_cs(struct platform_device *pdev)
> >> +{
> >> + struct spi_master *master = platform_get_drvdata(pdev);
> >> + struct atmel_spi *as = spi_master_get_devdata(master);
> >> + struct device_node *np = master->dev.of_node;
> >> + int i;
> >> + int ret = 0;
> >> + int nb = 0;
> >> +
> >> + if (!as->use_cs_gpios)
> >> + return 0;
> >> +
> >> + if (!np)
> >> + return 0;
> >> +
> >> + nb = of_gpio_named_count(np, "cs-gpios");
> >> + for (i = 0; i < nb; i++) {
> >> + int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
> >> + "cs-gpios", i);
> >> +
> >> + if (cs_gpio == -EPROBE_DEFER)
> >> + return cs_gpio;
> >> +
> >> + if (gpio_is_valid(cs_gpio)) {
> >> + ret = devm_gpio_request(&pdev->dev, cs_gpio,
> >> + dev_name(&pdev->dev));
> >> + if (ret)
> >> + return ret;
> >> + }
> >> + }
> >> +
> >> + return 0;
> >> +}
> >>
> >> static int atmel_spi_probe(struct platform_device *pdev)
> >> {
> >> @@ -1577,6 +1601,10 @@ static int atmel_spi_probe(struct platform_device *pdev)
> >> master->num_chipselect = 4;
> >> }
> >>
> >> + ret = atmel_spi_gpio_cs(pdev);
> >> + if (ret)
> >> + goto out_unmap_regs;
> >> +
> >> as->use_dma = false;
> >> as->use_pdc = false;
> >> if (as->caps.has_dma_support) {
> >> --
> >> 2.9.0
> >>
> >
>
>
> --
> Nicolas Ferre
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [RESPIN-PATCH v2 1/2] ARM: EXYNOS: Remove static mapping of SCU SFR
From: pankaj.dubey @ 2016-11-09 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161108190446.GA4608@kozik-lap>
Hi Krzysztof,
On Wednesday 09 November 2016 12:34 AM, Krzysztof Kozlowski wrote:
> On Tue, Nov 08, 2016 at 04:49:43PM +0530, Pankaj Dubey wrote:
>> Lets remove static mapping of SCU SFR mainly used in CORTEX-A9 SoC based boards.
>> Instead use mapping from device tree node of SCU.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>> arch/arm/mach-exynos/common.h | 1 +
>> arch/arm/mach-exynos/exynos.c | 22 ------------------
>> arch/arm/mach-exynos/include/mach/map.h | 2 --
>> arch/arm/mach-exynos/platsmp.c | 34 +++++++++++++++++++++-------
>> arch/arm/mach-exynos/pm.c | 5 ++--
>> arch/arm/mach-exynos/suspend.c | 13 ++++-------
>> arch/arm/plat-samsung/include/plat/map-s5p.h | 4 ----
>> 7 files changed, 34 insertions(+), 47 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index 9424a8a..dd5d8e8 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -161,6 +161,7 @@ extern void exynos_cpu_restore_register(void);
>> extern void exynos_pm_central_suspend(void);
>> extern int exynos_pm_central_resume(void);
>> extern void exynos_enter_aftr(void);
>> +extern int exynos_scu_enable(void);
>>
>> extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
>>
>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>> index 757fc11..fa08ef9 100644
>> --- a/arch/arm/mach-exynos/exynos.c
>> +++ b/arch/arm/mach-exynos/exynos.c
>> @@ -28,15 +28,6 @@
>>
>> #include "common.h"
>>
>> -static struct map_desc exynos4_iodesc[] __initdata = {
>> - {
>> - .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
>> - .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
>> - .length = SZ_8K,
>> - .type = MT_DEVICE,
>> - },
>> -};
>> -
>> static struct platform_device exynos_cpuidle = {
>> .name = "exynos_cpuidle",
>> #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
>> @@ -99,17 +90,6 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
>> return 1;
>> }
>>
>> -/*
>> - * exynos_map_io
>> - *
>> - * register the standard cpu IO areas
>> - */
>> -static void __init exynos_map_io(void)
>> -{
>> - if (soc_is_exynos4())
>> - iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
>> -}
>> -
>> static void __init exynos_init_io(void)
>> {
>> debug_ll_io_init();
>> @@ -118,8 +98,6 @@ static void __init exynos_init_io(void)
>>
>> /* detect cpu id and rev. */
>> s5p_init_cpu(S5P_VA_CHIPID);
>> -
>> - exynos_map_io();
>> }
>>
>> /*
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
>> index 5fb0040..0eef407 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -18,6 +18,4 @@
>>
>> #define EXYNOS_PA_CHIPID 0x10000000
>>
>> -#define EXYNOS4_PA_COREPERI 0x10500000
>> -
>> #endif /* __ASM_ARCH_MAP_H */
>> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
>> index a5d6841..94405c7 100644
>> --- a/arch/arm/mach-exynos/platsmp.c
>> +++ b/arch/arm/mach-exynos/platsmp.c
>> @@ -168,6 +168,27 @@ int exynos_cluster_power_state(int cluster)
>> S5P_CORE_LOCAL_PWR_EN);
>> }
>>
>> +/**
>> + * exynos_scu_enable : enables SCU for Cortex-A9 based system
>> + * returns 0 on success else non-zero error code
>> + */
>> +int exynos_scu_enable(void)
>> +{
>> + struct device_node *np;
>> + void __iomem *scu_base;
>> +
>> + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
>> + scu_base = of_iomap(np, 0);
>> + of_node_put(np);
>> + if (!scu_base) {
>> + pr_err("%s failed to map scu_base\n", __func__);
>> + return -ENOMEM;
>> + }
>> + scu_enable(scu_base);
>> + iounmap(scu_base);
>> + return 0;
>> +}
>> +
>> static void __iomem *cpu_boot_reg_base(void)
>> {
>> if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
>> @@ -224,11 +245,6 @@ static void write_pen_release(int val)
>> sync_cache_w(&pen_release);
>> }
>>
>> -static void __iomem *scu_base_addr(void)
>> -{
>> - return (void __iomem *)(S5P_VA_SCU);
>> -}
>> -
>> static DEFINE_SPINLOCK(boot_lock);
>>
>> static void exynos_secondary_init(unsigned int cpu)
>> @@ -393,9 +409,11 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
>>
>> exynos_set_delayed_reset_assertion(true);
>>
>> - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
>> - scu_enable(scu_base_addr());
>> -
>> + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
>> + /* if exynos_scu_enable fails, return */
>> + if (exynos_scu_enable())
>> + return;
>
> Ohhh, someone (e.g. out-of-tree DTS) might be surprised with this.
> Please mention such change of behaviour in the commit log (describe the
> possible impact of this commit).
>
OK, I will add small note, for this change of behavior in commit log.
>> + }
>> /*
>> * Write the address of secondary startup into the
>> * system-wide flags register. The boot monitor waits
>> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
>> index 487295f..23db2af 100644
>> --- a/arch/arm/mach-exynos/pm.c
>> +++ b/arch/arm/mach-exynos/pm.c
>> @@ -18,6 +18,7 @@
>> #include <linux/cpu_pm.h>
>> #include <linux/io.h>
>> #include <linux/of.h>
>> +#include <linux/of_address.h>
>
> Why do you need this include? Was it coming from mach/map.h?
>
Its not required. This is leftover of patchset v1, and can be removed.
>> #include <linux/soc/samsung/exynos-regs-pmu.h>
>> #include <linux/soc/samsung/exynos-pmu.h>
>>
>> @@ -26,8 +27,6 @@
>> #include <asm/suspend.h>
>> #include <asm/cacheflush.h>
>>
>> -#include <mach/map.h>
>> -
>> #include "common.h"
>>
>> static inline void __iomem *exynos_boot_vector_addr(void)
>> @@ -177,7 +176,7 @@ void exynos_enter_aftr(void)
>> cpu_suspend(0, exynos_aftr_finisher);
>>
>> if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
>> - scu_enable(S5P_VA_SCU);
>> + exynos_scu_enable();
>> if (call_firmware_op(resume) == -ENOSYS)
>> exynos_cpu_restore_register();
>> }
>> diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
>> index 06332f6..c73c857 100644
>> --- a/arch/arm/mach-exynos/suspend.c
>> +++ b/arch/arm/mach-exynos/suspend.c
>> @@ -34,8 +34,6 @@
>> #include <asm/smp_scu.h>
>> #include <asm/suspend.h>
>>
>> -#include <mach/map.h>
>> -
>> #include <plat/pm-common.h>
>>
>> #include "common.h"
>> @@ -461,12 +459,11 @@ static void exynos_pm_resume(void)
>> /* For release retention */
>> exynos_pm_release_retention();
>>
>> - if (cpuid == ARM_CPU_PART_CORTEX_A9)
>> - scu_enable(S5P_VA_SCU);
>> -
>> - if (call_firmware_op(resume) == -ENOSYS
>> - && cpuid == ARM_CPU_PART_CORTEX_A9)
>> - exynos_cpu_restore_register();
>> + if (cpuid == ARM_CPU_PART_CORTEX_A9) {
>> + exynos_scu_enable();
>> + if (call_firmware_op(resume) == -ENOSYS)
>> + exynos_cpu_restore_register();
>
> It does not look right. I think you changed the logic here. Previously
> if CPU != A9, then call_firmware_op() was executed. Now it won't be.
>
Yes, my bad, I understood it in different way. I will correct this and
submit V3, after addressing all your comments.
> BTW, don't respin patchset with the same version number. This is
> basically v3. To me, increasing version number is always welcomed. It
> makes dealign with patches easier.
>
OK. I will take care in future.
Thanks,
Pankaj Dubey
^ permalink raw reply
* [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards
From: Gabriel Fernandez @ 2016-11-09 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFvLkMSUg8=nYY9Zm2Q4ZW=GqUaczK_TA5b5jjb45vYyhoVLZA@mail.gmail.com>
On 11/09/2016 09:10 AM, Rados?aw Pietrzyk wrote:
> I would expect that VCO clock will force recalculation for all its
> children if I am not mistaken.
Sure
BR
Gabriel.
>
> 2016-11-08 17:19 GMT+01:00 Gabriel Fernandez <gabriel.fernandez@st.com>:
>> On 11/08/2016 09:52 AM, Rados?aw Pietrzyk wrote:
>>> 2016-11-08 9:35 GMT+01:00 Gabriel Fernandez <gabriel.fernandez@st.com>:
>>>> Hi Rados?aw
>>>>
>>>> Many thanks for reviewing.
>>>>
>>>> On 11/07/2016 03:57 PM, Rados?aw Pietrzyk wrote:
>>>>>> +static struct clk_hw *clk_register_pll_div(const char *name,
>>>>>> + const char *parent_name, unsigned long flags,
>>>>>> + void __iomem *reg, u8 shift, u8 width,
>>>>>> + u8 clk_divider_flags, const struct clk_div_table
>>>>>> *table,
>>>>>> + struct clk_hw *pll_hw, spinlock_t *lock)
>>>>>> +{
>>>>>> + struct stm32f4_pll_div *pll_div;
>>>>>> + struct clk_hw *hw;
>>>>>> + struct clk_init_data init;
>>>>>> + int ret;
>>>>>> +
>>>>>> + /* allocate the divider */
>>>>>> + pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
>>>>>> + if (!pll_div)
>>>>>> + return ERR_PTR(-ENOMEM);
>>>>>> +
>>>>>> + init.name = name;
>>>>>> + init.ops = &stm32f4_pll_div_ops;
>>>>>> + init.flags = flags;
>>>>> Maybe it's worth to have CLK_SET_RATE_PARENT here and the VCO clock
>>>>> should have CLK_SET_RATE_GATE flag and we can get rid of custom
>>>>> divider ops.
>>>> I don't want to offer the possibility to change the vco clock through the
>>>> divisor of the pll (only by a boot-loader or by DT).
>>>>
>>>> e.g. if i make a set rate on lcd-tft clock, i don't want to change the
>>>> SAI
>>>> frequencies.
>>>>
>>>> I used same structure for internal divisors of the pll (p, q, r) and for
>>>> post divisors (plli2s-q-div, pllsai-q-div & pllsai-r-div).
>>>> That why the CLK_SET_RATE_PARENT flag is transmit by parameter.
>>>>
>>>> These divisors are similar because we have to switch off the pll before
>>>> changing the rate.
>>>>
>>> But changing pll and lcd dividers only may not be enough for getting
>>> very specific pixelclocks and that might require changing the VCO
>>> frequency itself. The rest of the SAI tree should be recalculated
>>> then.
>> I agree but it seems to be too much complicated to recalculate all PLL
>> divisors if we change the vco clock.
>> You mean to use Clock notifier callback ?
^ permalink raw reply
* [PATCH v2 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Romain Perier @ 2016-11-09 9:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109085946.cmd4ltaxpiojq7il@tarshish>
Hi Baruch
Le 09/11/2016 ? 09:59, Baruch Siach a ?crit :
>> @@ -193,6 +204,8 @@ struct pxa_i2c {
>> unsigned char master_code;
>> unsigned long rate;
>> bool highmode_enter;
>> + unsigned long fm_mask;
>> + unsigned long hs_mask;
>
> Do you really need 64bit for that?
>
> baruch
Mhhh, good point. No I think that I can use an unsigned int.
I will fix it.
Thanks,
Romain
--
Romain Perier, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* ILP32 for ARM64: testing with glibc testsuite
From: Yury Norov @ 2016-11-09 9:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161107082359.GA19666@yury-N73SV>
On Mon, Nov 07, 2016 at 01:53:59PM +0530, Yury Norov wrote:
> Hi all,
>
> [add libc-alpha mail list]
>
> For libc-alpha: this is the part of LKML submission with latest
> patches for aarch64/ilp32.
> https://www.spinics.net/lists/arm-kernel/msg537846.html
>
> Glibc that I use has also included consolidation patches from Adhemerval
> Zanella and me that are still not in the glibc master. The full series is:
> https://github.com/norov/glibc/tree/ilp32-2.24-dev2
>
> Below is the results of glibc testsuite run for aarch64/lp64
> in different configurations. Column names meaning:
> kvgv: kernel is vanilla, glibc is vanilla;
> kdgv: kernel has ilp32 patches applied, but ilp32 is disabled in config;
> glibc is vanilla;
> kegv: kernel has ilp32 patches applied and ilp32 is enabled, glibc is vanilla;
> kege: kernel patches are applied and enabled, glibc patches are applied.
>
> Only different lines are shown. Full results are in attached archive.
The same, plus ILP32 regressions:
Test kvgv kdgv kegv kege ilp32
conform/ISO/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
conform/ISO11/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
conform/ISO99/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
conform/POSIX/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
conform/POSIX/sys/stat.h/linknamespace PASS PASS PASS FAIL FAIL
conform/UNIX98/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
conform/XOPEN2K/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
conform/XPG3/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
conform/XPG4/stdio.h/linknamespace PASS PASS PASS FAIL FAIL
csu/tst-atomic PASS PASS PASS FAIL PASS
elf/check-localplt PASS PASS PASS FAIL FAIL
iconvdata/mtrace-tst-loading PASS FAIL PASS PASS FAIL
iconvdata/tst-loading PASS FAIL PASS PASS PASS
io/check-installed-headers-c PASS PASS PASS FAIL FAIL
io/check-installed-headers-cxx PASS PASS PASS FAIL FAIL
malloc/tst-malloc-backtrace FAIL PASS PASS PASS PASS
malloc/tst-malloc-thread-exit FAIL PASS PASS PASS PASS
malloc/tst-malloc-usable FAIL PASS PASS PASS PASS
malloc/tst-mallocfork FAIL PASS PASS PASS PASS
malloc/tst-mallocstate FAIL PASS PASS PASS PASS
malloc/tst-mallopt FAIL PASS PASS PASS PASS
malloc/tst-mcheck FAIL PASS PASS PASS PASS
malloc/tst-memalign FAIL PASS PASS PASS PASS
malloc/tst-obstack FAIL PASS PASS PASS PASS
malloc/tst-posix_memalign FAIL PASS PASS PASS PASS
malloc/tst-pvalloc FAIL PASS PASS PASS PASS
malloc/tst-realloc FAIL PASS PASS PASS PASS
malloc/tst-scratch_buffer FAIL PASS PASS PASS PASS
malloc/tst-trim1 FAIL PASS PASS PASS PASS
nptl/tst-eintr4 PASS PASS PASS NA NA
posix/tst-regex2 PASS FAIL FAIL FAIL FAIL
posix/tst-getaddrinfo4 PASS PASS FAIL FAIL PASS
posix/tst-getaddrinfo5 PASS PASS FAIL FAIL PASS
sysvipc/test-sysvmsg NA NA NA FAIL PASS
sysvipc/test-sysvsem NA NA NA FAIL PASS
sysvipc/test-sysvshm NA NA NA FAIL PASS
c++-types-check PASS PASS PASS PASS FAIL
debug/tst-backtrace4 PASS PASS PASS PASS FAIL
elf/check-abi-libc PASS PASS PASS PASS FAIL
elf/tst-tls1 PASS PASS PASS PASS FAIL
elf/tst-tls1-static PASS PASS PASS PASS FAIL
elf/tst-tls2 PASS PASS PASS PASS FAIL
elf/tst-tls2-static PASS PASS PASS PASS FAIL
elf/tst-tls3 PASS PASS PASS PASS FAIL
math/check-abi-libm PASS PASS PASS PASS FAIL
misc/tst-writev PASS PASS PASS PASS NA
nptl/tst-cancel-self-canceltype PASS PASS PASS PASS FAIL
nptl/tst-cancel1 PASS PASS PASS PASS FAIL
nptl/tst-cancel10 PASS PASS PASS PASS FAIL
nptl/tst-cancel11 PASS PASS PASS PASS FAIL
nptl/tst-cancel13 PASS PASS PASS PASS FAIL
nptl/tst-cancel15 PASS PASS PASS PASS FAIL
nptl/tst-cancel16 PASS PASS PASS PASS FAIL
nptl/tst-cancel17 PASS PASS PASS PASS FAIL
nptl/tst-cancel18 PASS PASS PASS PASS FAIL
nptl/tst-cancel2 PASS PASS PASS PASS FAIL
nptl/tst-cancel20 PASS PASS PASS PASS FAIL
nptl/tst-cancel21 PASS PASS PASS PASS FAIL
nptl/tst-cancel24 PASS PASS PASS PASS FAIL
nptl/tst-cancel25 PASS PASS PASS PASS FAIL
nptl/tst-cancel26 PASS PASS PASS PASS FAIL
nptl/tst-cancel27 PASS PASS PASS PASS FAIL
nptl/tst-cancel3 PASS PASS PASS PASS FAIL
nptl/tst-cancel4 PASS PASS PASS PASS FAIL
nptl/tst-cancel5 PASS PASS PASS PASS FAIL
nptl/tst-cancel6 PASS PASS PASS PASS FAIL
nptl/tst-cancel7 PASS PASS PASS PASS FAIL
nptl/tst-cancelx10 PASS PASS PASS PASS FAIL
nptl/tst-cancelx11 PASS PASS PASS PASS FAIL
nptl/tst-cancelx13 PASS PASS PASS PASS FAIL
nptl/tst-cancelx15 PASS PASS PASS PASS FAIL
nptl/tst-cancelx16 PASS PASS PASS PASS FAIL
nptl/tst-cancelx17 PASS PASS PASS PASS FAIL
nptl/tst-cancelx18 PASS PASS PASS PASS FAIL
nptl/tst-cancelx2 PASS PASS PASS PASS FAIL
nptl/tst-cancelx20 PASS PASS PASS PASS FAIL
nptl/tst-cancelx21 PASS PASS PASS PASS FAIL
nptl/tst-cancelx3 PASS PASS PASS PASS FAIL
nptl/tst-cancelx4 PASS PASS PASS PASS FAIL
nptl/tst-cancelx5 PASS PASS PASS PASS FAIL
nptl/tst-cancelx6 PASS PASS PASS PASS FAIL
nptl/tst-cancelx7 PASS PASS PASS PASS FAIL
nptl/tst-cleanup4 PASS PASS PASS PASS FAIL
nptl/tst-cleanupx4 PASS PASS PASS PASS FAIL
nptl/tst-cond-except PASS PASS PASS PASS FAIL
nptl/tst-cond7 PASS PASS PASS PASS FAIL
nptl/tst-cond8 PASS PASS PASS PASS FAIL
nptl/tst-fini1 PASS PASS PASS PASS FAIL
nptl/tst-initializers1 PASS PASS PASS PASS FAIL
nptl/tst-initializers1-c11 PASS PASS PASS PASS FAIL
nptl/tst-initializers1-c89 PASS PASS PASS PASS FAIL
nptl/tst-initializers1-c99 PASS PASS PASS PASS FAIL
nptl/tst-initializers1-gnu11 PASS PASS PASS PASS FAIL
nptl/tst-initializers1-gnu89 PASS PASS PASS PASS FAIL
nptl/tst-initializers1-gnu99 PASS PASS PASS PASS FAIL
nptl/tst-join5 PASS PASS PASS PASS FAIL
nptl/tst-key3 PASS PASS PASS PASS FAIL
nptl/tst-mutex8 PASS PASS PASS PASS FAIL
nptl/tst-mutexpi8 PASS PASS PASS PASS FAIL
nptl/tst-once3 PASS PASS PASS PASS FAIL
nptl/tst-once4 PASS PASS PASS PASS FAIL
nptl/tst-oncex3 PASS PASS PASS PASS FAIL
nptl/tst-oncex4 PASS PASS PASS PASS FAIL
nptl/tst-rwlock15 PASS PASS PASS PASS FAIL
nptl/tst-rwlock8 PASS PASS PASS PASS FAIL
nptl/tst-rwlock9 PASS PASS PASS PASS FAIL
nptl/tst-sem11 PASS PASS PASS PASS FAIL
nptl/tst-sem12 PASS PASS PASS PASS FAIL
posix/bug-regex24 PASS PASS PASS PASS FAIL
rt/tst-mqueue1 PASS PASS PASS PASS FAIL
rt/tst-mqueue2 PASS PASS PASS PASS FAIL
rt/tst-mqueue4 PASS PASS PASS PASS FAIL
rt/tst-mqueue7 PASS PASS PASS PASS FAIL
rt/tst-mqueue8 PASS PASS PASS PASS FAIL
rt/tst-mqueue8x PASS PASS PASS PASS FAIL
stdlib/tst-makecontext3 PASS PASS PASS PASS FAIL
^ permalink raw reply
* [PATCH v3 0/3] Add basic support for the I2C units of the Armada 3700
From: Romain Perier @ 2016-11-09 10:13 UTC (permalink / raw)
To: linux-arm-kernel
This series add basic support for the I2C bus interface units present
in the Armada 3700 to the pxa-i2c driver. It also add the definitions of
the device nodes to the devicetree at the SoC level and for its official
development board: the Armada 3720 DB.
Romain Perier (3):
i2c: pxa: Add support for the I2C units found in Armada 3700
arm64: dts: marvell: Add I2C definitions for the Armada 3700
dt-bindings: i2c: pxa: Update the documentation for the Armada 3700
Documentation/devicetree/bindings/i2c/i2c-pxa.txt | 1 +
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 ++++++++++++++++
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++--
5 files changed, 47 insertions(+), 3 deletions(-)
--
2.9.3
^ permalink raw reply
* [PATCH v3 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Romain Perier @ 2016-11-09 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109101349.18722-1-romain.perier@free-electrons.com>
The Armada 3700 has two I2C controllers that is compliant with the I2C
Bus Specificiation 2.1, supports multi-master and different bus speed:
Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
High speed mode (up to 3.4 Mhz).
This IP block has a lot of similarity with the PXA, except some register
offsets and bitfield. This commits adds a basic support for this I2C
unit.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
Changes in v3:
- Replaced the type of hm_mask and fm_mask by unsigned int,
instead of unsigned long.
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++++--
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d252276..2f56a26 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -763,7 +763,7 @@ config I2C_PUV3
config I2C_PXA
tristate "Intel PXA2XX I2C adapter"
- depends on ARCH_PXA || ARCH_MMP || (X86_32 && PCI && OF)
+ depends on ARCH_PXA || ARCH_MMP || ARCH_MVEBU || (X86_32 && PCI && OF)
help
If you have devices in the PXA I2C bus, say yes to this option.
This driver can also be built as a module. If so, the module
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index e28b825..09619db 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -55,6 +55,7 @@ enum pxa_i2c_types {
REGS_PXA3XX,
REGS_CE4100,
REGS_PXA910,
+ REGS_A3700,
};
/*
@@ -91,6 +92,13 @@ static struct pxa_reg_layout pxa_reg_layout[] = {
.ilcr = 0x28,
.iwcr = 0x30,
},
+ [REGS_A3700] = {
+ .ibmr = 0x00,
+ .idbr = 0x04,
+ .icr = 0x08,
+ .isr = 0x0c,
+ .isar = 0x10,
+ },
};
static const struct platform_device_id i2c_pxa_id_table[] = {
@@ -98,6 +106,7 @@ static const struct platform_device_id i2c_pxa_id_table[] = {
{ "pxa3xx-pwri2c", REGS_PXA3XX },
{ "ce4100-i2c", REGS_CE4100 },
{ "pxa910-i2c", REGS_PXA910 },
+ { "armada-3700-i2c", REGS_A3700 },
{ },
};
MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
@@ -122,7 +131,9 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
#define ICR_FM (1 << 15) /* fast mode */
+#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
#define ICR_HS (1 << 16) /* High Speed mode */
+#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
#define ISR_RWM (1 << 0) /* read/write mode */
@@ -193,6 +204,8 @@ struct pxa_i2c {
unsigned char master_code;
unsigned long rate;
bool highmode_enter;
+ unsigned int fm_mask;
+ unsigned int hs_mask;
};
#define _IBMR(i2c) ((i2c)->reg_ibmr)
@@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
writel(i2c->slave_addr, _ISAR(i2c));
/* set control register values */
- writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
- writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
+ writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
+ writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, "Enabling slave mode\n");
@@ -1137,6 +1150,7 @@ static const struct of_device_id i2c_pxa_dt_ids[] = {
{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
+ { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
{}
};
MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
@@ -1158,6 +1172,13 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
i2c->use_pio = 1;
if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
i2c->fast_mode = 1;
+ if (of_device_is_compatible(np, "marvell,armada-3700-i2c")) {
+ i2c->fm_mask = ICR_BUSMODE_FM;
+ i2c->hs_mask = ICR_BUSMODE_HS;
+ } else {
+ i2c->fm_mask = ICR_FM;
+ i2c->hs_mask = ICR_HS;
+ }
*i2c_types = (enum pxa_i2c_types)(of_id->data);
--
2.9.3
^ permalink raw reply related
* [PATCH v3 2/3] arm64: dts: marvell: Add I2C definitions for the Armada 3700
From: Romain Perier @ 2016-11-09 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109101349.18722-1-romain.perier@free-electrons.com>
The Armada 3700 has two i2c bus interface units, this commit adds the
definitions of the corresponding device nodes. It also enables the node
on the development board for this SoC.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6..16d84af 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -62,6 +62,10 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
/* CON3 */
&sata {
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c476253..bf2d73d 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -98,6 +98,24 @@
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
+ i2c0: i2c at 11000 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11000 0x24>;
+ clocks = <&nb_perih_clk 10>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 11080 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11080 0x24>;
+ clocks = <&nb_perih_clk 9>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
uart0: serial at 12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
--
2.9.3
^ permalink raw reply related
* [PATCH v3 3/3] dt-bindings: i2c: pxa: Update the documentation for the Armada 3700
From: Romain Perier @ 2016-11-09 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109101349.18722-1-romain.perier@free-electrons.com>
This commit documents the compatible string to have the compatibility for
the I2C unit found in the Armada 3700.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
---
Changes in v2:
- Fixed wrong compatible string, it should be "marvell,armada-3700-i2c"
and not "marvell,armada-3700".
Documentation/devicetree/bindings/i2c/i2c-pxa.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
index 12b78ac..d30f0b1 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
@@ -7,6 +7,7 @@ Required properties :
compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
as shown in the example below.
+ For the Armada 3700, the compatible should be "marvell,armada-3700-i2c".
Recommended properties :
--
2.9.3
^ permalink raw reply related
* [PATCH v3 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Gregory CLEMENT @ 2016-11-09 10:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109101349.18722-2-romain.perier@free-electrons.com>
Hi Romain,
You was too fast I didn't have time to commnent about Baruch suggestion.
On mer., nov. 09 2016, Romain Perier <romain.perier@free-electrons.com> wrote:
> The Armada 3700 has two I2C controllers that is compliant with the I2C
> Bus Specificiation 2.1, supports multi-master and different bus speed:
> Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
> High speed mode (up to 3.4 Mhz).
>
> This IP block has a lot of similarity with the PXA, except some register
> offsets and bitfield. This commits adds a basic support for this I2C
> unit.
>
> Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>
> Changes in v3:
> - Replaced the type of hm_mask and fm_mask by unsigned int,
> instead of unsigned long.
[...]
> #define ISR_RWM (1 << 0) /* read/write mode */
> @@ -193,6 +204,8 @@ struct pxa_i2c {
> unsigned char master_code;
> unsigned long rate;
> bool highmode_enter;
> + unsigned int fm_mask;
> + unsigned int hs_mask;
These masks are used with writel and readl which use an u32. So the
better is to use this type.
Gregory
> };
>
> #define _IBMR(i2c) ((i2c)->reg_ibmr)
> @@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
> writel(i2c->slave_addr, _ISAR(i2c));
>
> /* set control register values */
> - writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
> - writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
> + writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
> + writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver
From: Anurup M @ 2016-11-09 10:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1609380.NN50qvVsP7@wuerfel>
On Tuesday 08 November 2016 08:40 PM, Arnd Bergmann wrote:
> On Tuesday, November 8, 2016 1:49:43 PM CET John Garry wrote:
>> Hi Arnd,
>>
>> Thanks for the reference.
>>
>> I think the i2c interface doesn't fully satisfy our requirements as we
>> need more than just a slave bus address when accessing the slave device
>> (which I think is what i2c uses). We also need to pass "offset" and
>> "mod_mask" arguments to the djtag adapter to access specific registers
>> in the slave device.
> Ok. Are those values constant per device, or maybe a range? We may want to
> include those in the reg property as well then.
>
> Arnd
>
Hi Arnd,
The "mod_mask" is to select the sub-module within a module. This
parameter is
used for djtag write operation.
In the case of L3 cache, this will select the L3 cache bank. 0xFFFF
select all banks.
This value will change based on the L3 cache bank to be written to. I
think this value
can be in the driver itself.
For djtag read operation, the "mod_mask" is ignored. instead the input
parameter
"chain_id" is used. this will identify the sub-module or bank.
For djtag-v1, the "chain_id" is different for each L3 cache bank, But in
the case of
djtag-v2 the "chain_id" is fixed and the value is 0 as In djtag-v2 there
is separate
"module-id" for each sub-module.
The "offset" is the register offset and this value is a range for a module.
Thanks,
Anurup
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox