* [PATCH 1/2] ARM: dts: rockchip: add the sdmmc pinctrl for rk1108
From: Jacob Chen @ 2016-11-13 8:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
---
arch/arm/boot/dts/rk1108.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
index 9dccfea..6a06ad7 100644
--- a/arch/arm/boot/dts/rk1108.dtsi
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -321,6 +321,31 @@
input-enable;
};
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_cd: sdmmc-cd {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+ };
+
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
--
2.7.4
^ permalink raw reply related
* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: Andy Yan @ 2016-11-13 7:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2910206.ioRrj8ivkn@diego>
Hi Heiko, Jacob:
On 2016?11?13? 05:44, Heiko St?bner wrote:
> Hi Jacob,
>
> Am Sonntag, 13. November 2016, 01:41:21 schrieb ??:
>> 2016-11-03 20:34 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
>>> Add basic support for rk1108 soc
>>>
>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>>> ---
>>>
>>> drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
>>> 1 file changed, 26 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pinctrl/pinctrl-rockchip.c
>>> b/drivers/pinctrl/pinctrl-rockchip.c index 49bf7dc..9f324b1 100644
>>> --- a/drivers/pinctrl/pinctrl-rockchip.c
>>> +++ b/drivers/pinctrl/pinctrl-rockchip.c
>>> @@ -59,6 +59,7 @@
>>>
>>> #define GPIO_LS_SYNC 0x60
>>>
>>> enum rockchip_pinctrl_type {
>>>
>>> + RK1108,
>>>
>>> RK2928,
>>> RK3066B,
>>> RK3188,
>>>
>>> @@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct
>>> rockchip_pin_bank *bank, int pin_num)>
>>> return !(data & BIT(bit))
>>>
>>> ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
>>>
>>> : PIN_CONFIG_BIAS_DISABLE;
>>>
>>> + case RK1108:
>>> case RK3188:
>>> case RK3288:
>>>
>>> case RK3368:
>>> @@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct
>>> rockchip_pin_bank *bank,>
>>> spin_unlock_irqrestore(&bank->slock, flags);
>>> break;
>>>
>>> + case RK1108:
>>> case RK3188:
>>> case RK3288:
>>>
>>> case RK3368:
>>> @@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct
>>> rockchip_pin_ctrl *ctrl,>
>>> pull == PIN_CONFIG_BIAS_DISABLE);
>>>
>>> case RK3066B:
>>> return pull ? false : true;
>>>
>>> + case RK1108:
>>> case RK3188:
>>> case RK3288:
>>>
>>> case RK3368:
>>> @@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev
>>> *pctldev, unsigned int pin,>
>>> for (i = 0; i < num_configs; i++) {
>>>
>>> param = pinconf_to_config_param(configs[i]);
>>> arg = pinconf_to_config_argument(configs[i]);
>>>
>>> -
>>>
>>> switch (param) {
>>>
>>> case PIN_CONFIG_BIAS_DISABLE:
>>> rc = rockchip_set_pull(bank, pin -
>>> bank->pin_base,
>>>
>>> @@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct
>>> platform_device *pdev)>
>>> return 0;
>>>
>>> }
>>>
>>> +static struct rockchip_pin_bank rk1108_pin_banks[] = {
>>> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
>>> + IOMUX_SOURCE_PMU,
>>> + IOMUX_SOURCE_PMU,
>>> + IOMUX_SOURCE_PMU),
>>> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>>> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
>>> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
>>> +};
>>> +
>>> +static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
>>> + .pin_banks = rk1108_pin_banks,
>>> + .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
>>> + .label = "RK1108-GPIO",
>>> + .type = RK1108,
>>> + .grf_mux_offset = 0x10,
>>> + .pmu_mux_offset = 0x0,
>>> + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
>>> +};
>>> +com
>>>
>>> static struct rockchip_pin_bank rk2928_pin_banks[] = {
>>>
>>> PIN_BANK(0, 32, "gpio0"),
>>> PIN_BANK(1, 32, "gpio1"),
>>>
>>> @@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
>>>
>>> };
>>>
>>> static const struct of_device_id rockchip_pinctrl_dt_match[] = {
>>>
>>> + { .compatible = "rockchip,rk1108-pinctrl",
>>> + .data = (void *)&rk1108_pin_ctrl },
>>>
>>> { .compatible = "rockchip,rk2928-pinctrl",
>>>
>>> .data = (void *)&rk2928_pin_ctrl },
>>>
>>> { .compatible = "rockchip,rk3036-pinctrl",
>>>
>>> --
>>> 2.7.4
>> rk3288_calc_pull_reg_and_bit can't be used directly in rk1108.
>> rk1108 have a different PULL_PMU_OFFSET and PULL_OFFSET.
> yes, you're right, the offsets are different, so need a new function.
>
> Andy, when at it, you might also want to include drive-strength functionality?
> It is missing here but from looking at the TRM, it should be pretty easy to
> add, as everything looks similar to what other rockchip socs do.
I had already found it, it will be fixed in next version.
Thank you!
>
> Heiko
>
>
>
^ permalink raw reply
* [GIT PULL] Qualcomm SoC Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-soc-for-4.10
for you to fetch changes up to e19811a89d0f566bb781959e151f244bd3bcde8a:
arm64: qcom: enable GPIOLIB in Kconfig (2016-11-12 23:24:26 -0600)
----------------------------------------------------------------
Qualcomm ARM Based SoC Updates for v4.10
* Enable GPIOLIB for QCOM ARM64 platforms
----------------------------------------------------------------
Michael Scott (1):
arm64: qcom: enable GPIOLIB in Kconfig
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
^ permalink raw reply
* [GIT PULL] Qualcomm Device Tree Changes for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-dts-for-4.10
for you to fetch changes up to 52a1a5f773110f687c34a828ef42fdb882b6b908:
ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard (2016-10-25 08:42:37 -0500)
----------------------------------------------------------------
Qualcomm Device Tree Changes for v4.10
* Add EBI2 support to MSM8660
* Add SMSC ethernet support to APQ8060
* Add support for display, pstore, iommu, and hdmi to APQ8064
* Add SDHCI node to MSM8974 Hammerhead
* Add WP8548 MangOH board support (MDM9615)
----------------------------------------------------------------
Archit Taneja (2):
arm: dts: qcom: apq8064: Add display DT nodes
arm: dts: qcom: apq8064-ifc6410: Add HDMI support
Bhushan Shah (1):
ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node
John Stultz (3):
arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes
arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7
Linus Walleij (2):
ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI
ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
Neil Armstrong (5):
ARM: dts: Add MDM9615 dtsi
dt-bindings: qcom: Add MDM9615 bindings
ARM: dts: Add Sierra Wireless WP8548 dtsi
ARM: dts: Add WP8548 based MangOH Green board DTS
dt-bindings: arm: Add Sierra Wireless modules bindings
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
Documentation/devicetree/bindings/arm/swir.txt | 12 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 119 +++++
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 77 ++-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 74 +++
arch/arm/boot/dts/qcom-apq8064.dtsi | 321 ++++++++++++
arch/arm/boot/dts/qcom-mdm9615.dtsi | 557 +++++++++++++++++++++
arch/arm/boot/dts/qcom-msm8660.dtsi | 17 +
.../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 29 ++
arch/arm/boot/dts/swir-wp8548-mangoh-green.dts | 281 +++++++++++
arch/arm/boot/dts/swir-wp8548.dtsi | 170 +++++++
12 files changed, 1658 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/swir.txt
create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi
create mode 100644 arch/arm/boot/dts/swir-wp8548-mangoh-green.dts
create mode 100644 arch/arm/boot/dts/swir-wp8548.dtsi
^ permalink raw reply
* [GIT PULL] Qualcomm Driver Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-drivers-for-4.10
for you to fetch changes up to bd4760ca03156731674a570e44490986189d8228:
firmware: qcom: scm: Use devm_reset_controller_register() (2016-11-12 23:24:51 -0600)
----------------------------------------------------------------
Qualcomm ARM Based Driver Updates for v4.10
* Fixup QCOM SCM to use devm_reset_controller_register
* Add QCOM pinctrl to Qualcomm MAINTAINERS entry
* Add PM8994 regulator definitions
* Add stub for WCNSS_CTRL API
----------------------------------------------------------------
Bjorn Andersson (1):
soc: qcom: wcnss_ctrl: Stub wcnss_ctrl API
Michael Scott (1):
MAINTAINERS: add drivers/pinctrl/qcom to ARM/QUALCOMM SUPPORT
Srinivas Kandagatla (1):
pinctrl: pm8994: add pad voltage regulator defines
Wei Yongjun (1):
firmware: qcom: scm: Use devm_reset_controller_register()
MAINTAINERS | 1 +
drivers/firmware/qcom_scm.c | 4 +++-
include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 4 ++++
include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 6 ++++++
include/linux/soc/qcom/wcnss_ctrl.h | 13 +++++++++++++
5 files changed, 27 insertions(+), 1 deletion(-)
^ permalink raw reply
* [GIT PULL] Qualcomm Defconfig Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-defconfig-for-4.10
for you to fetch changes up to 206787737e308bb447d18adef7da7749188212f5:
ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config (2016-10-24 16:04:32 -0500)
----------------------------------------------------------------
Qualcomm ARM Based defconfig Updates for v4.10
* Fixup MDM9615 option names
----------------------------------------------------------------
Neil Armstrong (1):
ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config
arch/arm/configs/qcom_defconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 DT Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-for-4.10
for you to fetch changes up to feeaf56ac78d283efe65ea60ec999d4bf3cf395e:
arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support (2016-11-12 22:57:56 -0600)
----------------------------------------------------------------
Qualcomm ARM64 Updates for v4.10
* Add Hexagon SMD/PIL nodes
* Add DB820c PMIC pins
* Fixup APQ8016 voltage ranges
* Add various MSM8996 nodes to support SMD/SMEM/SMP2P
* Add support for Huawei Nexus 6P (Angler)
* Add support for LG Nexus 5x (Bullhead)
----------------------------------------------------------------
Archit Taneja (1):
arm64: dts: apq8016-sbc: Set up LDO2, LDO6 and LDO17 regulator voltage ranges
Bastian K?cher (1):
arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
Bjorn Andersson (3):
arm64: dts: qcom: msm8916: Add Hexagon SMD edge
arm64: dts: qcom: msm8916: Add Hexagon PIL node
arm64: dts: msm8996: Add SMEM DT nodes
Jeremy McNicoll (2):
arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
dt-bindings: qcom: Add msm899(2/4) bindings
Rajendra Nayak (1):
arm64: dts: qcom: Add missing interrupt entry for pm8994 gpios
Srinivas Kandagatla (2):
dts: arm64: db820c: add pmic pins specific dts file
arm64: dts: apq8016-sbc: add analog audio support with multicodec
spjoshi at codeaurora.org (3):
arm64: dts: msm8996: Add SMEM reserve-memory node
arm64: dts: msm8996: Add reserve-memory nodes
arm64: dts: msm8996: Add SMP2P and APCS nodes
Documentation/devicetree/bindings/arm/qcom.txt | 2 +
arch/arm64/boot/dts/qcom/Makefile | 7 +-
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 73 ++++++-
.../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi | 15 ++
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 2 +
arch/arm64/boot/dts/qcom/msm8916.dtsi | 62 +++++-
.../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 41 ++++
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 ++++
arch/arm64/boot/dts/qcom/msm8992.dtsi | 184 ++++++++++++++++++
.../arm64/boot/dts/qcom/msm8994-angler-rev-101.dts | 40 ++++
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++++
arch/arm64/boot/dts/qcom/msm8994.dtsi | 216 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 82 ++++++++
arch/arm64/boot/dts/qcom/pm8916.dtsi | 45 ++++-
arch/arm64/boot/dts/qcom/pm8994.dtsi | 1 +
15 files changed, 836 insertions(+), 10 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 Defconfig Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-defconfig-for-4.10
for you to fetch changes up to a77a713395392a7f79d89e634fe3e018c4f83898:
arm64: configs: enable configs for msm899(2/4) basic support (2016-11-12 22:44:09 -0600)
----------------------------------------------------------------
Qualcomm ARM64 Based defconfig Updates for v4.10
* Enable defconfig options for MSM8992/8994
----------------------------------------------------------------
Jeremy McNicoll (1):
arm64: configs: enable configs for msm899(2/4) basic support
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
^ permalink raw reply
* [PATCH 5/10] clk: sunxi-ng: Implement multiplier maximum
From: Chen-Yu Tsai @ 2016-11-13 4:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1d12cf2cb0a7364f17691705f3bd018eddc51202.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu_mult.h | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> index 84839641dfdf..524acddfcb2e 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.h
> +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> @@ -10,24 +10,26 @@ struct ccu_mult_internal {
> u8 shift;
> u8 width;
> u8 min;
> + u8 max;
> };
>
> -#define _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, _min) \
> +#define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \
> { \
> .min = _min, \
> + .max = _max, \
> .offset = _offset, \
> .shift = _shift, \
> .width = _width, \
> }
>
> #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> - _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, _min)
> + _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
>
> #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \
> - _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, 1)
> + _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
>
> #define _SUNXI_CCU_MULT(_shift, _width) \
> - _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, 1)
> + _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
>
> struct ccu_mult {
> u32 enable;
> --
> git-series 0.8.11
You're missing the code that actually uses the maximum value.
ChenYu
^ permalink raw reply
* [PATCH 4/10] clk: sunxi-ng: Add clocks and resets indices for sun5i
From: Chen-Yu Tsai @ 2016-11-13 4:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8fbb8e05d73282fb5e7d33f8faffbeaccf63aeae.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The SoCs part of the sun5i family share the DTs, so we need consistant
> indices in order to still share the DTs.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> include/dt-bindings/clock/sun5i-ccu.h | 126 +++++++++++++++++++++++++++-
> include/dt-bindings/reset/sun5i-ccu.h | 32 +++++++-
> 2 files changed, 158 insertions(+), 0 deletions(-)
> create mode 100644 include/dt-bindings/clock/sun5i-ccu.h
> create mode 100644 include/dt-bindings/reset/sun5i-ccu.h
>
> diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h
> new file mode 100644
> index 000000000000..32735b2cf29c
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun5i-ccu.h
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright 2016 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _CCU_SUN5I_H_
> +#define _CCU_SUN5I_H_
> +
> +#define CLK_HOSC 1
> +#define CLK_OSC3M 2
We don't need this one. The clock diagram shows the video PLLs' input
as OSC24M. This means there's a fixed /8 pre-divider at the input.
> +#define CLK_PLL_CORE 3
> +#define CLK_PLL_AUDIO_BASE 4
> +#define CLK_PLL_AUDIO 5
> +#define CLK_PLL_AUDIO_2X 6
> +#define CLK_PLL_AUDIO_4X 7
> +#define CLK_PLL_AUDIO_8X 8
> +#define CLK_PLL_VIDEO0 9
> +#define CLK_PLL_VIDEO0_2X 10
> +#define CLK_PLL_VE 11
> +#define CLK_PLL_DDR_BASE 12
> +#define CLK_PLL_DDR 13
> +#define CLK_PLL_DDR_OTHER 14
> +#define CLK_PLL_PERIPH 15
> +#define CLK_PLL_VIDEO1 16
> +#define CLK_PLL_VIDEO1_2X 17
> +#define CLK_OSC24M 18
> +#define CLK_CPU 19
> +#define CLK_AXI 20
> +#define CLK_AHB 21
> +#define CLK_APB0 22
> +#define CLK_APB1 23
> +#define CLK_DRAM_AXI 24
> +#define CLK_AHB_OTG 25
> +#define CLK_AHB_EHCI 26
> +#define CLK_AHB_OHCI 27
> +#define CLK_AHB_SS 28
> +#define CLK_AHB_DMA 29
> +#define CLK_AHB_BIST 30
> +#define CLK_AHB_MMC0 31
> +#define CLK_AHB_MMC1 32
> +#define CLK_AHB_MMC2 33
> +#define CLK_AHB_NAND 34
> +#define CLK_AHB_SDRAM 35
> +#define CLK_AHB_EMAC 36
> +#define CLK_AHB_TS 37
> +#define CLK_AHB_SPI0 38
> +#define CLK_AHB_SPI1 39
> +#define CLK_AHB_SPI2 40
> +#define CLK_AHB_GPS 41
> +#define CLK_AHB_HSTIMER 42
> +#define CLK_AHB_VE 43
> +#define CLK_AHB_TVE 44
> +#define CLK_AHB_LCD 45
> +#define CLK_AHB_CSI 46
> +#define CLK_AHB_HDMI 47
> +#define CLK_AHB_DE_BE 48
> +#define CLK_AHB_DE_FE 49
> +#define CLK_AHB_IEP 50
> +#define CLK_AHB_GPU 51
> +#define CLK_APB0_CODEC 52
> +#define CLK_APB0_SPDIF 53
> +#define CLK_APB0_I2S 54
> +#define CLK_APB0_PIO 55
> +#define CLK_APB0_IR 56
> +#define CLK_APB0_KEYPAD 57
> +#define CLK_APB1_I2C0 58
> +#define CLK_APB1_I2C1 59
> +#define CLK_APB1_I2C2 60
> +#define CLK_APB1_UART0 61
> +#define CLK_APB1_UART1 62
> +#define CLK_APB1_UART2 63
> +#define CLK_APB1_UART3 64
> +#define CLK_NAND 65
> +#define CLK_MMC0 66
> +#define CLK_MMC1 67
> +#define CLK_MMC2 68
> +#define CLK_TS 69
> +#define CLK_SS 70
> +#define CLK_CE 71
You use 'SS' for the AHB gate. Since the manual uses 'SS',
can we stick to that.
> +#define CLK_SPI0 72
> +#define CLK_SPI1 73
> +#define CLK_SPI2 74
> +#define CLK_IR 75
> +#define CLK_I2S 76
> +#define CLK_SPDIF 77
> +#define CLK_KEYPAD 78
> +#define CLK_USB_OHCI 79
> +#define CLK_USB_PHY0 80
> +#define CLK_USB_PHY1 81
> +#define CLK_GPS 82
> +#define CLK_DRAM_VE 83
> +#define CLK_DRAM_CSI 84
> +#define CLK_DRAM_TS 85
> +#define CLK_DRAM_TVE 86
> +#define CLK_DRAM_DE_FE 87
> +#define CLK_DRAM_DE_BE 88
> +#define CLK_DRAM_ACE 89
> +#define CLK_DRAM_IEP 90
> +#define CLK_DE_BE 91
> +#define CLK_DE_FE 92
> +#define CLK_TCON_CH0 93
> +#define CLK_TCON_CH1_SCLK 94
> +#define CLK_TCON_CH1 95
> +#define CLK_CSI 96
> +#define CLK_VE 97
> +#define CLK_CODEC 98
> +#define CLK_AVS 99
> +#define CLK_HDMI 100
> +#define CLK_GPU 101
> +#define CLK_MBUS 102
> +#define CLK_IEP 103
> +
> +#define CLK_NUMBER (CLK_IEP + 1)
> +
> +#endif /* _CCU_SUN5I_H_ */
> diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h
> new file mode 100644
> index 000000000000..c2b9726b5026
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun5i-ccu.h
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright 2016 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _RST_SUN5I_H_
> +#define _RST_SUN5I_H_
> +
> +#define RST_USB_PHY0 0
> +#define RST_USB_PHY1 1
> +#define RST_GPS 2
> +#define RST_DE_BE 3
> +#define RST_DE_FE 4
> +#define RST_TVE 5
> +#define RST_LCD 6
> +#define RST_CSI 7
> +#define RST_VE 8
> +#define RST_GPU 9
> +#define RST_IEP 10
> +
> +#endif /* _RST_SUN5I_H_ */
> --
> git-series 0.8.11
The rest looks good.
ChenYu
^ permalink raw reply
* [PATCH 3/10] clk: sunxi-ng: Implement multiplier offsets
From: Chen-Yu Tsai @ 2016-11-13 4:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <434b49180c2b5f8668f9fd92f5cba6d8b64a7de8.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The multipliers we've seen so far all had an offset of one. However, on the
Explaining that the offset refers to the difference between the register value
and the actual multiplier/divider applied to the clock rate would be nice.
> earlier Allwinner SoCs, the multipliers could have no offset at all.
>
> Implement an additional field for the multipliers to specify that offset.
You are also doing this for dividers. Please mention that.
And you should mention that you're only doing this for "linear" factors,
not power-of-two ones.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu_div.h | 10 +++++++++-
> drivers/clk/sunxi-ng/ccu_mp.c | 10 +++++++---
> drivers/clk/sunxi-ng/ccu_mult.c | 4 ++--
> drivers/clk/sunxi-ng/ccu_mult.h | 20 ++++++++++++++------
> drivers/clk/sunxi-ng/ccu_nk.c | 14 ++++++++++----
> drivers/clk/sunxi-ng/ccu_nkm.c | 18 +++++++++++++-----
> drivers/clk/sunxi-ng/ccu_nkmp.c | 17 +++++++++++++----
> drivers/clk/sunxi-ng/ccu_nm.c | 13 ++++++++++---
> 8 files changed, 78 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
> index 06540f7cf41c..08d074451204 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.h
> +++ b/drivers/clk/sunxi-ng/ccu_div.h
> @@ -41,6 +41,7 @@ struct ccu_div_internal {
> u8 width;
>
> u32 max;
> + u32 offset;
>
> u32 flags;
>
> @@ -58,20 +59,27 @@ struct ccu_div_internal {
> #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
> _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
>
> -#define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
> +#define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \
> { \
> .shift = _shift, \
> .width = _width, \
> .flags = _flags, \
> .max = _max, \
> + .offset = _off, \
> }
>
> +#define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
> + _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
> +
> #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
> _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
>
> #define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \
> _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0)
>
> +#define _SUNXI_CCU_DIV_OFFSET(_shift, _width, _offset) \
> + _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _offset, 0, 0)
> +
With this macro, you can have a divider offset of anything but 1, but
no specified maximum. You should handle this in the callbacks somehow.
Same goes for the multiplier. Otherwise with max = (1 << width), you'll
overflow the register field when offset = 0.
Also, if specified, does the maximum apply before or after the offset
is applied? Some clarification is required.
> #define _SUNXI_CCU_DIV(_shift, _width) \
> _SUNXI_CCU_DIV_FLAGS(_shift, _width, 0)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
> index ebb1b31568a5..22c2ca7a2a22 100644
> --- a/drivers/clk/sunxi-ng/ccu_mp.c
> +++ b/drivers/clk/sunxi-ng/ccu_mp.c
> @@ -89,11 +89,14 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
>
> m = reg >> cmp->m.shift;
> m &= (1 << cmp->m.width) - 1;
> + m += cmp->m.offset;
> + if (!m)
> + m++;
>
> p = reg >> cmp->p.shift;
> p &= (1 << cmp->p.width) - 1;
>
> - return (parent_rate >> p) / (m + 1);
> + return (parent_rate >> p) / m;
> }
>
> static int ccu_mp_determine_rate(struct clk_hw *hw,
> @@ -124,9 +127,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
> reg = readl(cmp->common.base + cmp->common.reg);
> reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
> reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
> + reg |= (m - cmp->m.offset) << cmp->m.shift;
> + reg |= ilog2(p) << cmp->p.shift;
>
> - writel(reg | (ilog2(p) << cmp->p.shift) | ((m - 1) << cmp->m.shift),
> - cmp->common.base + cmp->common.reg);
> + writel(reg, cmp->common.base + cmp->common.reg);
>
> spin_unlock_irqrestore(cmp->common.lock, flags);
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> index 826302464650..bf5e11c803f9 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.c
> +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> @@ -85,7 +85,7 @@ static unsigned long ccu_mult_recalc_rate(struct clk_hw *hw,
> ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
> &parent_rate);
>
> - return parent_rate * (val + 1);
> + return parent_rate * (val + cm->mult.offset);
> }
>
> static int ccu_mult_determine_rate(struct clk_hw *hw,
> @@ -122,7 +122,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
> reg = readl(cm->common.base + cm->common.reg);
> reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);
>
> - writel(reg | ((_cm.mult - 1) << cm->mult.shift),
> + writel(reg | ((_cm.mult - cm->mult.offset) << cm->mult.shift),
> cm->common.base + cm->common.reg);
>
> spin_unlock_irqrestore(cm->common.lock, flags);
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> index bd2e38b5a32a..84839641dfdf 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.h
> +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> @@ -6,20 +6,28 @@
> #include "ccu_mux.h"
>
> struct ccu_mult_internal {
> + u8 offset;
> u8 shift;
> u8 width;
> u8 min;
> };
>
> -#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> - { \
> - .shift = _shift, \
> - .width = _width, \
> - .min = _min, \
> +#define _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, _min) \
> + { \
> + .min = _min, \
> + .offset = _offset, \
> + .shift = _shift, \
> + .width = _width, \
> }
>
> +#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> + _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, _min)
> +
> +#define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \
> + _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, 1)
> +
> #define _SUNXI_CCU_MULT(_shift, _width) \
> - _SUNXI_CCU_MULT_MIN(_shift, _width, 1)
> + _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, 1)
>
> struct ccu_mult {
> u32 enable;
> diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> index eaf0fdf78d2b..90117d3ead8c 100644
> --- a/drivers/clk/sunxi-ng/ccu_nk.c
> +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> @@ -76,12 +76,17 @@ static unsigned long ccu_nk_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nk->n.shift;
> n &= (1 << nk->n.width) - 1;
> + n += nk->n.offset;
> + if (!n)
> + n++;
>
> k = reg >> nk->k.shift;
> k &= (1 << nk->k.width) - 1;
> + k += nk->k.offset;
> + if (!k)
> + k++;
>
> - rate = parent_rate * (n + 1) * (k + 1);
> -
> + rate = parent_rate * n * k;
> if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> rate /= nk->fixed_post_div;
>
> @@ -135,8 +140,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);
> reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
>
> - writel(reg | ((_nk.k - 1) << nk->k.shift) | ((_nk.n - 1) << nk->n.shift),
> - nk->common.base + nk->common.reg);
> + reg |= (_nk.k - nk->k.offset) << nk->k.shift;
> + reg |= (_nk.n - nk->n.offset) << nk->n.shift;
> + writel(reg, nk->common.base + nk->common.reg);
>
> spin_unlock_irqrestore(nk->common.lock, flags);
>
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index fd3c6a9d987c..e0b4c914d7ac 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -82,14 +82,23 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nkm->n.shift;
> n &= (1 << nkm->n.width) - 1;
> + n += nkm->n.offset;
> + if (!n)
> + n++;
>
> k = reg >> nkm->k.shift;
> k &= (1 << nkm->k.width) - 1;
> + k += nkm->k.offset;
> + if (!k)
> + k++;
>
> m = reg >> nkm->m.shift;
> m &= (1 << nkm->m.width) - 1;
> + m += nkm->m.offset;
> + if (!m)
> + m++;
>
> - rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
> + rate = parent_rate * n * k / m;
> if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> rate /= nkm->fixed_post_div;
>
> @@ -156,10 +165,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);
> reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift);
>
> - reg |= (_nkm.n - 1) << nkm->n.shift;
> - reg |= (_nkm.k - 1) << nkm->k.shift;
> - reg |= (_nkm.m - 1) << nkm->m.shift;
> -
> + reg |= (_nkm.n - nkm->n.offset) << nkm->n.shift;
> + reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift;
> + reg |= (_nkm.m - nkm->m.offset) << nkm->m.shift;
> writel(reg, nkm->common.base + nkm->common.reg);
>
> spin_unlock_irqrestore(nkm->common.lock, flags);
> diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> index 684c42da3ebb..da2bba02b845 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> @@ -88,17 +88,26 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nkmp->n.shift;
> n &= (1 << nkmp->n.width) - 1;
> + n += nkmp->n.offset;
> + if (!n)
> + n++;
>
> k = reg >> nkmp->k.shift;
> k &= (1 << nkmp->k.width) - 1;
> + k += nkmp->k.offset;
> + if (!k)
> + k++;
>
> m = reg >> nkmp->m.shift;
> m &= (1 << nkmp->m.width) - 1;
> + m += nkmp->m.offset;
> + if (!m)
> + m++;
>
> p = reg >> nkmp->p.shift;
> p &= (1 << nkmp->p.width) - 1;
>
> - return (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
> + return parent_rate * n * k >> p / m;
> }
>
> static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
> @@ -148,9 +157,9 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift);
> reg &= ~GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift);
>
> - reg |= (_nkmp.n - 1) << nkmp->n.shift;
> - reg |= (_nkmp.k - 1) << nkmp->k.shift;
> - reg |= (_nkmp.m - 1) << nkmp->m.shift;
> + reg |= (_nkmp.n - nkmp->n.offset) << nkmp->n.shift;
> + reg |= (_nkmp.k - nkmp->k.offset) << nkmp->k.shift;
> + reg |= (_nkmp.m - nkmp->m.offset) << nkmp->m.shift;
> reg |= ilog2(_nkmp.p) << nkmp->p.shift;
>
> writel(reg, nkmp->common.base + nkmp->common.reg);
> diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> index c9f3b6c982f0..158d74e0215f 100644
> --- a/drivers/clk/sunxi-ng/ccu_nm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> @@ -80,11 +80,17 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nm->n.shift;
> n &= (1 << nm->n.width) - 1;
> + n += nm->n.offset;
> + if (!n)
> + n++;
>
> m = reg >> nm->m.shift;
> m &= (1 << nm->m.width) - 1;
> + m += nm->m.offset;
> + if (!m)
> + m++;
>
> - return parent_rate * (n + 1) / (m + 1);
> + return parent_rate * n / m;
> }
>
> static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
> @@ -129,8 +135,9 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);
> reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
>
> - writel(reg | ((_nm.m - 1) << nm->m.shift) | ((_nm.n - 1) << nm->n.shift),
> - nm->common.base + nm->common.reg);
> + reg |= (_nm.n - nm->n.offset) << nm->n.shift;
> + reg |= (_nm.m - nm->m.offset) << nm->m.shift;
> + writel(reg, nm->common.base + nm->common.reg);
>
> spin_unlock_irqrestore(nm->common.lock, flags);
>
> --
> git-series 0.8.11
The existing bits in this patch look good.
Regards
ChenYu
^ permalink raw reply
* [PATCH 2/10] clk: sunxi-ng: nkm: Deal with fixed post dividers
From: Chen-Yu Tsai @ 2016-11-13 3:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v64YW+7Grr4NvjuhsDNM2bF_fuhTkdW6Hs1=MXK2LFne0g@mail.gmail.com>
On Sun, Nov 13, 2016 at 11:48 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>
> It'd be better if you mentioned what clock needs this.
>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> drivers/clk/sunxi-ng/ccu_nkm.c | 17 ++++++++++++++---
>> drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
>> 2 files changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
>> index 9b840a47a94d..fd3c6a9d987c 100644
>> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
>> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
>> @@ -75,7 +75,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
>> - unsigned long n, m, k;
>> + unsigned long rate, n, m, k;
>> u32 reg;
>>
>> reg = readl(nkm->common.base + nkm->common.reg);
>> @@ -89,7 +89,11 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
>> m = reg >> nkm->m.shift;
>> m &= (1 << nkm->m.width) - 1;
>>
>> - return parent_rate * (n + 1) * (k + 1) / (m + 1);
>> + rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
>> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>> + rate /= nkm->fixed_post_div;
>> +
>> + return rate;
>> }
>>
>> static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>> @@ -100,6 +104,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>> struct ccu_nkm *nkm = data;
>> struct _ccu_nkm _nkm;
>>
>> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>> + rate *= nkm->fixed_post_div;
>> +
>> _nkm.min_n = nkm->n.min;
>> _nkm.max_n = 1 << nkm->n.width;
>> _nkm.min_k = nkm->k.min;
>> @@ -109,7 +116,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>>
>> ccu_nkm_find_best(parent_rate, rate, &_nkm);
>>
>> - return parent_rate * _nkm.n * _nkm.k / _nkm.m;
>> + rate = parent_rate * _nkm.n * _nkm.k / _nkm.m;
>> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>> + rate = rate / nkm->fixed_post_div;
>> +
>> + return rate;
>> }
>>
>
> You also need to handle this in the set_rate callback. You might need
> to read back
> the parent index value to determine if the post divider applies, as
> this clock supports
> a mux. Or don't support mux + post-div, and leave a TODO note.
Was thinking pre-dividers... sorry. Please ignore the second parent
index part.
ChenYu
>
> ChenYu
>
>> static int ccu_nkm_determine_rate(struct clk_hw *hw,
>> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
>> index 34580894f4d1..0f1dbca25719 100644
>> --- a/drivers/clk/sunxi-ng/ccu_nkm.h
>> +++ b/drivers/clk/sunxi-ng/ccu_nkm.h
>> @@ -32,6 +32,8 @@ struct ccu_nkm {
>> struct ccu_mult_internal n;
>> struct ccu_mult_internal k;
>> struct ccu_div_internal m;
>> +
>> + unsigned int fixed_post_div;
>> struct ccu_mux_internal mux;
>>
>> struct ccu_common common;
>> --
>> git-series 0.8.11
^ permalink raw reply
* [PATCH 2/10] clk: sunxi-ng: nkm: Deal with fixed post dividers
From: Chen-Yu Tsai @ 2016-11-13 3:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f8333c3a1f3308fcebd87bfc3710ce605f9bb595.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
It'd be better if you mentioned what clock needs this.
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu_nkm.c | 17 ++++++++++++++---
> drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
> 2 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index 9b840a47a94d..fd3c6a9d987c 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -75,7 +75,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
> - unsigned long n, m, k;
> + unsigned long rate, n, m, k;
> u32 reg;
>
> reg = readl(nkm->common.base + nkm->common.reg);
> @@ -89,7 +89,11 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
> m = reg >> nkm->m.shift;
> m &= (1 << nkm->m.width) - 1;
>
> - return parent_rate * (n + 1) * (k + 1) / (m + 1);
> + rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate /= nkm->fixed_post_div;
> +
> + return rate;
> }
>
> static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> @@ -100,6 +104,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> struct ccu_nkm *nkm = data;
> struct _ccu_nkm _nkm;
>
> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate *= nkm->fixed_post_div;
> +
> _nkm.min_n = nkm->n.min;
> _nkm.max_n = 1 << nkm->n.width;
> _nkm.min_k = nkm->k.min;
> @@ -109,7 +116,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>
> ccu_nkm_find_best(parent_rate, rate, &_nkm);
>
> - return parent_rate * _nkm.n * _nkm.k / _nkm.m;
> + rate = parent_rate * _nkm.n * _nkm.k / _nkm.m;
> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate = rate / nkm->fixed_post_div;
> +
> + return rate;
> }
>
You also need to handle this in the set_rate callback. You might need
to read back
the parent index value to determine if the post divider applies, as
this clock supports
a mux. Or don't support mux + post-div, and leave a TODO note.
ChenYu
> static int ccu_nkm_determine_rate(struct clk_hw *hw,
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
> index 34580894f4d1..0f1dbca25719 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.h
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.h
> @@ -32,6 +32,8 @@ struct ccu_nkm {
> struct ccu_mult_internal n;
> struct ccu_mult_internal k;
> struct ccu_div_internal m;
> +
> + unsigned int fixed_post_div;
> struct ccu_mux_internal mux;
>
> struct ccu_common common;
> --
> git-series 0.8.11
^ permalink raw reply
* [PATCH 10/10] ARM: gr8: Convert to CCU
From: kbuild test robot @ 2016-11-12 23:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <14a9d0306074ca0276831dc42104929a65f3b666.1478625788.git-series.maxime.ripard@free-electrons.com>
Hi Maxime,
[auto build test ERROR on ]
url: https://github.com/0day-ci/linux/commits/Maxime-Ripard/ARM-sun5i-Convert-sun5i-SoCs-to-sunxi-ng/20161109-014935
base:
config: arm-pxa168_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
>> ERROR: Input tree has errors, aborting (use -f to force output)
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v3] crypto: arm64/sha2: integrate OpenSSL implementations of SHA256/SHA512
From: Will Deacon @ 2016-11-12 22:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478953953-11523-1-git-send-email-ard.biesheuvel@linaro.org>
Hi Ard,
On Sat, Nov 12, 2016 at 01:32:33PM +0100, Ard Biesheuvel wrote:
> This integrates both the accelerated scalar and the NEON implementations
> of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.
>
> Relative performance compared to the respective generic C versions:
>
> | SHA256-scalar | SHA256-NEON* | SHA512 |
> ------------+-----------------+--------------+----------+
> Cortex-A53 | 1.63x | 1.63x | 2.34x |
> Cortex-A57 | 1.43x | 1.59x | 1.95x |
> Cortex-A73 | 1.26x | 1.56x | ? |
>
> The core crypto code was authored by Andy Polyakov of the OpenSSL
> project, in collaboration with whom the upstream code was adapted so
> that this module can be built from the same version of sha512-armv8.pl.
>
> The version in this patch was taken from OpenSSL commit
>
> 866e505e0d66 sha/asm/sha512-armv8.pl: add NEON version of SHA256.
>
> * The core SHA algorithm is fundamentally sequential, but there is a
> secondary transformation involved, called the schedule update, which
> can be performed independently. The NEON version of SHA-224/SHA-256
> only implements this part of the algorithm using NEON instructions,
> the sequential part is always done using scalar instructions.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> v3: at Will's request, the generated assembly files are now included
> as .S_shipped files, for which generic build rules are defined
> already. Note that this has caused issues in the past with
> patchwork, so for Herbert's convenience, the patch can be pulled
> from http://git.kernel.org/cgit/linux/kernel/git/ardb/linux.git,
> branch arm64-sha256 (based on today's cryptodev)
Thanks.
Looking at the generated code, I see references to __ARMEB__ and __ILP32__.
The former is probably a bug, whilst the second is not required. There are
also some commented out instructions, which is weird.
Will
^ permalink raw reply
* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: Heiko Stübner @ 2016-11-12 21:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFLEztRW8P4kiPZzVX2jM5UZMZun=TBBCij4B7j2TiesCuJYWA@mail.gmail.com>
Hi Jacob,
Am Sonntag, 13. November 2016, 01:41:21 schrieb ??:
> 2016-11-03 20:34 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> > Add basic support for rk1108 soc
> >
> > Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> > ---
> >
> > drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
> > 1 file changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pinctrl/pinctrl-rockchip.c
> > b/drivers/pinctrl/pinctrl-rockchip.c index 49bf7dc..9f324b1 100644
> > --- a/drivers/pinctrl/pinctrl-rockchip.c
> > +++ b/drivers/pinctrl/pinctrl-rockchip.c
> > @@ -59,6 +59,7 @@
> >
> > #define GPIO_LS_SYNC 0x60
> >
> > enum rockchip_pinctrl_type {
> >
> > + RK1108,
> >
> > RK2928,
> > RK3066B,
> > RK3188,
> >
> > @@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct
> > rockchip_pin_bank *bank, int pin_num)>
> > return !(data & BIT(bit))
> >
> > ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
> >
> > : PIN_CONFIG_BIAS_DISABLE;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct
> > rockchip_pin_bank *bank,>
> > spin_unlock_irqrestore(&bank->slock, flags);
> > break;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct
> > rockchip_pin_ctrl *ctrl,>
> > pull == PIN_CONFIG_BIAS_DISABLE);
> >
> > case RK3066B:
> > return pull ? false : true;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev
> > *pctldev, unsigned int pin,>
> > for (i = 0; i < num_configs; i++) {
> >
> > param = pinconf_to_config_param(configs[i]);
> > arg = pinconf_to_config_argument(configs[i]);
> >
> > -
> >
> > switch (param) {
> >
> > case PIN_CONFIG_BIAS_DISABLE:
> > rc = rockchip_set_pull(bank, pin -
> > bank->pin_base,
> >
> > @@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct
> > platform_device *pdev)>
> > return 0;
> >
> > }
> >
> > +static struct rockchip_pin_bank rk1108_pin_banks[] = {
> > + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU),
> > + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> > + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
> > + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
> > +};
> > +
> > +static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
> > + .pin_banks = rk1108_pin_banks,
> > + .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
> > + .label = "RK1108-GPIO",
> > + .type = RK1108,
> > + .grf_mux_offset = 0x10,
> > + .pmu_mux_offset = 0x0,
> > + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
> > +};
> > +
> >
> > static struct rockchip_pin_bank rk2928_pin_banks[] = {
> >
> > PIN_BANK(0, 32, "gpio0"),
> > PIN_BANK(1, 32, "gpio1"),
> >
> > @@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
> >
> > };
> >
> > static const struct of_device_id rockchip_pinctrl_dt_match[] = {
> >
> > + { .compatible = "rockchip,rk1108-pinctrl",
> > + .data = (void *)&rk1108_pin_ctrl },
> >
> > { .compatible = "rockchip,rk2928-pinctrl",
> >
> > .data = (void *)&rk2928_pin_ctrl },
> >
> > { .compatible = "rockchip,rk3036-pinctrl",
> >
> > --
> > 2.7.4
>
> rk3288_calc_pull_reg_and_bit can't be used directly in rk1108.
> rk1108 have a different PULL_PMU_OFFSET and PULL_OFFSET.
yes, you're right, the offsets are different, so need a new function.
Andy, when at it, you might also want to include drive-strength functionality?
It is missing here but from looking at the TRM, it should be pretty easy to
add, as everything looks similar to what other rockchip socs do.
Heiko
^ permalink raw reply
* PM regression with LED changes in next-20161109
From: Hans de Goede @ 2016-11-12 21:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c01cac8b-a921-56d1-7e57-8071d4b9faf6@gmail.com>
Hi,
On 12-11-16 20:14, Jacek Anaszewski wrote:
<snip>
>>>> Why a dedicated file? Are we going to mirror brightness here
>>>> wrt r/w (show/store) behavior ? If not userspace now needs
>>>> 2 open fds which is not really nice. If we are and we are
>>>> not going to use poll for something else on brightness itself
>>>> then why not just poll directly on brightness ?
>>>
>>> My main concern is that reporting only hw brightness changes
>>> wouldn't be consistent with general brightness file purpose.
>>> One could expect that brightness changes made by triggers
>>> should be also reported.
>>
>> Ok, I agree that not notifying poll() while an actual
>> read() would result in a different value is not really good
>> semantics.
>>
>> I don't like to call it hw_brightness_change though, as
>> mentioned before I believe that if we were to start with
>> a clean slate we would make the brightness file's read/write
>> behavior more a mirror of itself.
>>
>> So I would like to propose creating a new read-write
>> user_brightness file.
>>
>> The write behavior would be 100% identical to the brightness
>> file (in code terms it will call the same store function).
>>
>> The the read behavior otoh will be different: it will shows
>> the last brightness as set by the user, this would show the
>> read behavior we really want of brightness: show the real
>> brightness when not blinking / triggers are active and show
>> the brightness used when on when blinking / triggers are active.
>>
>> We could then add poll support on this new user_brightness
>> file, thus avoiding the problem with the extra cpu-load on
>> notifications on blinking / triggers.
>
> I agree that user_brightness allows to solve the issues you raised
> about inconsistent write and read brightness' semantics
> (which is not that painful IMHO).
>
> Reporting non-user brightness changes on user_brightness file
> doesn't sound reasonable though.
The changes I'm interested in are user brightness changes they
are just not done through sysfs, but through a hardwired hotkey,
they are however very much done by the user.
> Also, how would we read the
> brightness set by the firmware? We'd have to read brightness
> file, so still two files would have to be opened which is
> a second drawback of this approach.
No, look carefully at the definition of the read behavior
I plan to put in the ABI doc:
"Reading this file will return the actual led brightness
when not blinking and no triggers are active; reading this
file will return the brightness used when the led is on
when blinking or triggers are active."
So for e.g. the backlit keyboard case reading this single
file will return the actual brightness of the backlight,
since this does not involve blinking or triggers.
Basically the idea is that the user_brightness file
will have the semantics which IMHO the brightness file
itself should have had from the beginning, but which
we can't change now due to ABI reasons.
> Having no difference in this area between the two approaches
> I'm still in favour of the read-only file for notifying
> brightness changes procured by hardware.
That brings back the needing 2 fds problem; and does
not solve userspace not being able to reliably read
the led on brightness when blinking or using triggers.
And this also has the issue that one is doing poll() on
one fd to detect changes on another fd, which is completely
unheard of in any kernel API, so I still vote NACK for the
entire idea of having a different file purely for notifying
changes. The way unix defines poll to work means that the
poll() and read() must be on the same fd, anything else
does not make sense.
Regards,
Hans
^ permalink raw reply
* [PATCH RFC] mm: Add debug_virt_to_phys()
From: Florian Fainelli @ 2016-11-12 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161112054318.GB24127@arm.com>
Le 11/11/2016 ? 21:43, Will Deacon a ?crit :
> On Fri, Nov 11, 2016 at 04:44:43PM -0800, Florian Fainelli wrote:
>> When CONFIG_DEBUG_VM is turned on, virt_to_phys() maps to
>> debug_virt_to_phys() which helps catch vmalloc space addresses being
>> passed. This is helpful in debugging bogus drivers that just assume
>> linear mappings all over the place.
>>
>> For ARM, ARM64, Unicore32 and Microblaze, the architectures define
>> __virt_to_phys() as being the functional implementation of the address
>> translation, so we special case the debug stub to call into
>> __virt_to_phys directly.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>> arch/arm/include/asm/memory.h | 4 ++++
>> arch/arm64/include/asm/memory.h | 4 ++++
>> include/asm-generic/memory_model.h | 4 ++++
>> mm/debug.c | 15 +++++++++++++++
>> 4 files changed, 27 insertions(+)
>
> What's the interaction between this and the DEBUG_VIRTUAL patches from Laura?
>
> http://lkml.kernel.org/r/20161102210054.16621-7-labbott at redhat.com
>
> They seem to be tackling the exact same problem afaict.
Indeed thanks for pointing that out, I guess I could piggy back on this
patchset and try to cover ARM.
Thanks!
--
Florian
^ permalink raw reply
* [PATCH RFT] irqchip: mxs: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND
From: Oleksij Rempel @ 2016-11-12 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478885208-18821-1-git-send-email-stefan.wahren@i2se.com>
Am 11.11.2016 um 18:26 schrieb Stefan Wahren:
> The ICOLL controller doesn't provide any facility to configure the
> wakeup sources. That's the reason why this implementation lacks
> the irq_set_wake implementation. But this prevent us from properly
> entering power management states like "suspend to idle".
>
> So enable the flags IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND
> to let the irqchip core allows and handles the power management.
>
> This patch has been tested with a MX23 and a MX28 board. Any further
> tests especially with ASM9260 would be appreciated.
Hi, I wont be able to test this patch on ASM9260 until March.
Please roll it out, so far it looks ok for me.
> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
> ---
> drivers/irqchip/irq-mxs.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c
> index 1730470..05fa9f7 100644
> --- a/drivers/irqchip/irq-mxs.c
> +++ b/drivers/irqchip/irq-mxs.c
> @@ -131,12 +131,16 @@ static void asm9260_unmask_irq(struct irq_data *d)
> .irq_ack = icoll_ack_irq,
> .irq_mask = icoll_mask_irq,
> .irq_unmask = icoll_unmask_irq,
> + .flags = IRQCHIP_MASK_ON_SUSPEND |
> + IRQCHIP_SKIP_SET_WAKE,
> };
>
> static struct irq_chip asm9260_icoll_chip = {
> .irq_ack = icoll_ack_irq,
> .irq_mask = asm9260_mask_irq,
> .irq_unmask = asm9260_unmask_irq,
> + .flags = IRQCHIP_MASK_ON_SUSPEND |
> + IRQCHIP_SKIP_SET_WAKE,
> };
>
> asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
>
--
Regards,
Oleksij
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^ permalink raw reply
* PM regression with LED changes in next-20161109
From: Jacek Anaszewski @ 2016-11-12 19:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3eb60c78-d891-27e5-6b7b-a54a5b547a1c@redhat.com>
Hi,
On 11/12/2016 11:33 AM, Hans de Goede wrote:
> Hi,
>
> On 12-11-16 11:24, Jacek Anaszewski wrote:
>> Hi,
>>
>> On 11/11/2016 08:28 PM, Hans de Goede wrote:
>>> Hi,
>>>
>>> On 11-11-16 18:03, Jacek Anaszewski wrote:
>>>> On 11/11/2016 01:01 PM, Pavel Machek wrote:
>>>>> On Thu 2016-11-10 22:34:07, Jacek Anaszewski wrote:
>>>>>> Hi,
>>>>>>
>>>>>> On 11/10/2016 09:29 PM, Pavel Machek wrote:
>>>>>>> On Thu 2016-11-10 10:55:37, Tony Lindgren wrote:
>>>>>>>> * Pavel Machek <pavel@ucw.cz> [161110 09:29]:
>>>>>>>>> Hi!
>>>>>>>>>
>>>>>>>>>>>>> Looks like commit 883d32ce3385 ("leds: core: Add support for
>>>>>>>>>>>>> poll()ing
>>>>>>>>>>>>> the sysfs brightness attr for changes.") breaks runtime PM
>>>>>>>>>>>>> for me.
>>>>>>>>>>>>>
>>>>>>>>>>>>> On my omap dm3730 based test system, idle power consumption
>>>>>>>>>>>>> is over 70
>>>>>>>>>>>>> times higher now with this patch! It goes from about 6mW for
>>>>>>>>>>>>> the core
>>>>>>>>>>>>> system to over 440mW during idle meaning there's some busy
>>>>>>>>>>>>> timer now
>>>>>>>>>>>>> active.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Reverting this patch fixes the issue. Any ideas?
>>>>>>>>>
>>>>>>>>> Are you using any LED that toggles with high frequency? Like
>>>>>>>>> perhaps
>>>>>>>>> LED that is lit when CPU is active?
>>>>>>>>
>>>>>>>> Yeah one of them seems to have cpu0 as the default trigger.
>>>>>>>
>>>>>>> Aha. Its quite obvious we don't want to notify sysfs each time that
>>>>>>> one is toggled, right?
>>>>>>>
>>>>>>> IMO brightness should display max brightness for the trigger, as
>>>>>>> Hans
>>>>>>> suggested, anything else is madness for trigger such as cpu
>>>>>>> activity.
>>>>>>
>>>>>> Are you suggesting that we should revert changes introduced
>>>>>> by below patch?
>>>>>>
>>>>>> commit 29d76dfa29fe22583aefddccda0bc56aa81035dc
>>>>>> Author: Henrique de Moraes Holschuh <hmh@hmh.eng.br>
>>>>>> Date: Tue Mar 18 09:47:48 2008 +0000
>>>>>>
>>>>>> leds: Add support to leds with readable status
>>>>>>
>>>>>> Some led hardware allows drivers to query the led state, and
>>>>>> this patch
>>>>>> adds a hook to let the led class take advantage of that
>>>>>> information when
>>>>>> available.
>>>>>>
>>>>>> Without this functionality, when access to the led hardware is
>>>>>> not
>>>>>> exclusive (i.e. firmware or hardware might change its state
>>>>>> behind the
>>>>>> kernel's back), reality goes out of sync with the led class'
>>>>>> idea of
>>>>>> what
>>>>>> the led is doing, which is annoying at best.
>>>>>
>>>>> Hmm. So userland can read the LED state, and it can get _some_ value
>>>>> back, but it can not know if it is current state or not.
>>>>>
>>>>> I don't think that's a good interface. I see it is from 2008... is
>>>>> someone using it? Maybe it is too late for revert.
>>>>
>>>> I can imagine it being used in flash LED use case. E.g. one
>>>> could use oneshot trigger to trigger flash strobe, and then
>>>> he could periodically read brightness file to check, for whatever
>>>> reason, whether the flash is strobing.
>>>>
>>>>> But I'd certainly not extend it with poll.
>>>>
>>>> We could add a dedicated file e.g. hw_brightness_change for that
>>>> (maybe someone will have a better candidate for the file name).
>>>
>>> Why a dedicated file? Are we going to mirror brightness here
>>> wrt r/w (show/store) behavior ? If not userspace now needs
>>> 2 open fds which is not really nice. If we are and we are
>>> not going to use poll for something else on brightness itself
>>> then why not just poll directly on brightness ?
>>
>> My main concern is that reporting only hw brightness changes
>> wouldn't be consistent with general brightness file purpose.
>> One could expect that brightness changes made by triggers
>> should be also reported.
>
> Ok, I agree that not notifying poll() while an actual
> read() would result in a different value is not really good
> semantics.
>
> I don't like to call it hw_brightness_change though, as
> mentioned before I believe that if we were to start with
> a clean slate we would make the brightness file's read/write
> behavior more a mirror of itself.
>
> So I would like to propose creating a new read-write
> user_brightness file.
>
> The write behavior would be 100% identical to the brightness
> file (in code terms it will call the same store function).
>
> The the read behavior otoh will be different: it will shows
> the last brightness as set by the user, this would show the
> read behavior we really want of brightness: show the real
> brightness when not blinking / triggers are active and show
> the brightness used when on when blinking / triggers are active.
>
> We could then add poll support on this new user_brightness
> file, thus avoiding the problem with the extra cpu-load on
> notifications on blinking / triggers.
I agree that user_brightness allows to solve the issues you raised
about inconsistent write and read brightness' semantics
(which is not that painful IMHO).
Reporting non-user brightness changes on user_brightness file
doesn't sound reasonable though. Also, how would we read the
brightness set by the firmware? We'd have to read brightness
file, so still two files would have to be opened which is
a second drawback of this approach.
Having no difference in this area between the two approaches
I'm still in favour of the read-only file for notifying
brightness changes procured by hardware.
>> I'd make it only readable, so it wouldn't mirror brightness
>> file behavior.
>
> Then userspace which wants to be able to read + write + poll
> the brightness again needs to open 2 fds, as suggested
> above for the new user_brightness file it will be easy
> to just make it mimic the brightness file write behavior
> and then userspace only needs to open one fd.
>
> Regards,
>
> Hans
>
>
>
>
>>
>> Its purpose would be clear: notify hw brightness changes
>> and provide the brightness value that was set by the hardware
>> last time. It implies that this value could be different from
>> the one the brightness file reports. E.g. hw could have changed
>> brightness, which could be later updated through brightness
>> file, but hw_brightness_change would still report brightness level
>> that was set by the hardware last time. It could be useful
>> e.g. in case of showing the difference between the desired
>> value and the currently allowed configuration (e.g. if the
>> firmware automatically adjusted the value set by the user).
>>
>
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* [PATCH v2 1/2] arm64: dts: Add level for cpu dt node for exynos7
From: Krzysztof Kozlowski @ 2016-11-12 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGOxZ50Ttd1hP0x+Z527wc7mLLpz+Dom0TXFk08+mL0vnaxWwA@mail.gmail.com>
On Sat, Nov 12, 2016 at 6:00 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Javier,
>
> On Sat, Nov 12, 2016 at 7:54 PM, Javier Martinez Canillas
> <javier@osg.samsung.com> wrote:
>> Hello Alim,
>>
>> On 11/12/2016 07:17 AM, Alim Akhtar wrote:
>>> This patch adds level for cpu dt node, so that these levels can be used
>>
>> Do you mean s/level/label here? I'm asking because you are using level
>> consistently in the subject line and commit message but I'm not sure
>> what it means in this context.
>>
>
> Ah!! my bad. Its __label__. If required, will respin.
> Thanks for review.
I think there is no need of respin because this should be squashed
with previous patch. This is quite small and there are no functional
changes here (labels are transparent, except of course conflict
cases). Without the 2/2, this patch does not have much sense yet.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 1/4] ARM: dts: mxs: Add new M28EVK manufacturer compat
From: Marek Vasut @ 2016-11-12 18:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024065002.GX30578@tiger>
On 10/24/2016 08:50 AM, Shawn Guo wrote:
> On Sun, Oct 23, 2016 at 03:30:32PM +0200, Marek Vasut wrote:
>> On 10/23/2016 03:01 PM, Shawn Guo wrote:
>>> On Mon, Sep 19, 2016 at 11:40:41PM +0200, Marek Vasut wrote:
>>>> The board is now manufactured by Aries Embedded GmbH, update compat string.
>>>>
>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>> Cc: Shawn Guo <shawnguo@kernel.org>
>>>> ---
>>>> arch/arm/boot/dts/imx28-m28.dtsi | 4 ++--
>>>> arch/arm/boot/dts/imx28-m28evk.dts | 4 ++--
>>>> 2 files changed, 4 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
>>>> index 214bb15..a69856e 100644
>>>> --- a/arch/arm/boot/dts/imx28-m28.dtsi
>>>> +++ b/arch/arm/boot/dts/imx28-m28.dtsi
>>>> @@ -12,8 +12,8 @@
>>>> #include "imx28.dtsi"
>>>>
>>>> / {
>>>> - model = "DENX M28";
>>>> - compatible = "denx,m28", "fsl,imx28";
>>>> + model = "Aries/DENX M28";
>>>> + compatible = "aries,m28", "denx,m28", "fsl,imx28";
>>>
>>> Do we have an entry for Aries Embedded GmbH in vendor-prefixes.txt?
>>
>> The patch was submitted, not yet applied though:
>> http://www.spinics.net/lists/arm-kernel/msg533000.html
>
> Okay. Ping me when it gets applied.
Ping, it's in.
http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings/vendor-prefixes.txt?id=553a8bcd6a103f518d1f6a021b8442d8dfec5e6d
--
Best regards,
Marek Vasut
^ permalink raw reply
* [PATCH v2] staging: vc04_services: rework ioctl code path
From: Stefan Wahren @ 2016-11-12 17:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111061531.23507-1-mzoran@crowfest.net>
Hi Michael,
> Michael Zoran <mzoran@crowfest.net> hat am 11. November 2016 um 07:15
> geschrieben:
>
>
> VCHIQ/vc04_services has a userland device interface
> that includes ioctls. The current ioctl implementation
> is a single monolithic function over 1,000+ lines
> that handles 17 different ioctls through a complex
> maze of switch and if statements.
>
> The change reimplements that code path by breaking
> up the code into smaller, easier to maintain functions
> and uses a dispatch table to invoke the correct function.
nice. But please always use scripts/checkpatch.pl before submitting your
patches.
And yes it is not necessary to fix all "line over 80 chars" warnings.
^ permalink raw reply
* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: 陈豪 @ 2016-11-12 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478176470-11956-1-git-send-email-andy.yan@rock-chips.com>
2016-11-03 20:34 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> Add basic support for rk1108 soc
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 49bf7dc..9f324b1 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -59,6 +59,7 @@
> #define GPIO_LS_SYNC 0x60
>
> enum rockchip_pinctrl_type {
> + RK1108,
> RK2928,
> RK3066B,
> RK3188,
> @@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
> return !(data & BIT(bit))
> ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
> : PIN_CONFIG_BIAS_DISABLE;
> + case RK1108:
> case RK3188:
> case RK3288:
> case RK3368:
> @@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
>
> spin_unlock_irqrestore(&bank->slock, flags);
> break;
> + case RK1108:
> case RK3188:
> case RK3288:
> case RK3368:
> @@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
> pull == PIN_CONFIG_BIAS_DISABLE);
> case RK3066B:
> return pull ? false : true;
> + case RK1108:
> case RK3188:
> case RK3288:
> case RK3368:
> @@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
> for (i = 0; i < num_configs; i++) {
> param = pinconf_to_config_param(configs[i]);
> arg = pinconf_to_config_argument(configs[i]);
> -
> switch (param) {
> case PIN_CONFIG_BIAS_DISABLE:
> rc = rockchip_set_pull(bank, pin - bank->pin_base,
> @@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
> return 0;
> }
>
> +static struct rockchip_pin_bank rk1108_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
> +};
> +
> +static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
> + .pin_banks = rk1108_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
> + .label = "RK1108-GPIO",
> + .type = RK1108,
> + .grf_mux_offset = 0x10,
> + .pmu_mux_offset = 0x0,
> + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
> +};
> +
> static struct rockchip_pin_bank rk2928_pin_banks[] = {
> PIN_BANK(0, 32, "gpio0"),
> PIN_BANK(1, 32, "gpio1"),
> @@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
> };
>
> static const struct of_device_id rockchip_pinctrl_dt_match[] = {
> + { .compatible = "rockchip,rk1108-pinctrl",
> + .data = (void *)&rk1108_pin_ctrl },
> { .compatible = "rockchip,rk2928-pinctrl",
> .data = (void *)&rk2928_pin_ctrl },
> { .compatible = "rockchip,rk3036-pinctrl",
> --
> 2.7.4
>
>
rk3288_calc_pull_reg_and_bit can't be used directly in rk1108.
rk1108 have a different PULL_PMU_OFFSET and PULL_OFFSET.
^ permalink raw reply
* [PATCH] drm/sun4i: constify component_ops structures
From: Julia Lawall @ 2016-11-12 17:19 UTC (permalink / raw)
To: linux-arm-kernel
These component_ops structures are only used as the second argument to
component_add and component_del, which are declared as const, so the
structures can be declared as const as well.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct component_ops i at p = { ... };
@ok1@
identifier r.i;
expression e1;
position p;
@@
component_add(e1,&i at p)
@ok2@
identifier r.i;
expression e1;
position p;
@@
component_del(e1, &i at p)
@bad@
position p != {r.p,ok1.p,ok2.p};
identifier r.i;
struct component_ops e;
@@
e at i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct component_ops i = { ... };
// </smpl>
The result of the size command before the change is (arm):
text data bss dec hex filename
5266 236 8 5510 1586 sun4i_backend.o
6393 236 8 6637 19ed sun4i_tcon.o
3700 368 8 4076 fec sun4i_tv.o
1668 108 0 1776 6f0 sun6i_drc.o
and after the change:
text data bss dec hex filename
5274 228 8 5510 1586 sun4i_backend.o
6401 228 8 6637 19ed sun4i_tcon.o
3708 360 8 4076 fec sun4i_tv.o
1676 100 0 1776 6f0 sun6i_drc.o
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_tv.c | 2 +-
drivers/gpu/drm/sun4i/sun6i_drc.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 7eb2a96..2e08f96 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -409,7 +409,7 @@ static void sun4i_backend_unbind(struct device *dev, struct device *master,
reset_control_assert(backend->reset);
}
-static struct component_ops sun4i_backend_ops = {
+static const struct component_ops sun4i_backend_ops = {
.bind = sun4i_backend_bind,
.unbind = sun4i_backend_unbind,
};
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c6afb24..ea2906f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -545,7 +545,7 @@ static void sun4i_tcon_unbind(struct device *dev, struct device *master,
sun4i_tcon_free_clocks(tcon);
}
-static struct component_ops sun4i_tcon_ops = {
+static const struct component_ops sun4i_tcon_ops = {
.bind = sun4i_tcon_bind,
.unbind = sun4i_tcon_unbind,
};
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 1dd3d9e..d430b331 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -667,7 +667,7 @@ static void sun4i_tv_unbind(struct device *dev, struct device *master,
clk_disable_unprepare(tv->clk);
}
-static struct component_ops sun4i_tv_ops = {
+static const struct component_ops sun4i_tv_ops = {
.bind = sun4i_tv_bind,
.unbind = sun4i_tv_unbind,
};
diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c
index 6ef707c..09bba85 100644
--- a/drivers/gpu/drm/sun4i/sun6i_drc.c
+++ b/drivers/gpu/drm/sun4i/sun6i_drc.c
@@ -80,7 +80,7 @@ static void sun6i_drc_unbind(struct device *dev, struct device *master,
reset_control_assert(drc->reset);
}
-static struct component_ops sun6i_drc_ops = {
+static const struct component_ops sun6i_drc_ops = {
.bind = sun6i_drc_bind,
.unbind = sun6i_drc_unbind,
};
^ permalink raw reply related
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