* [PATCH 15/16] ARM: mvebu: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Jason Cooper <jason@lakedaemon.net>
CC: Andrew Lunn <andrew@lunn.ch>
CC: Gregory Clement <gregory.clement@free-electrons.com>
CC: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-mvebu/board-v7.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index ccca951..d7014a3 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -41,13 +41,9 @@ static void __iomem *scu_base;
*/
static void __init mvebu_scu_enable(void)
{
- struct device_node *np =
- of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
- if (np) {
- scu_base = of_iomap(np, 0);
+ scu_base = of_scu_get_base();
+ if (!IS_ERR(scu_base))
scu_enable(scu_base);
- of_node_put(np);
- }
}
void __iomem *mvebu_get_scu_base(void)
--
2.7.4
^ permalink raw reply related
* [PATCH 14/16] ARM: hisi: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-hisi/platsmp.c | 24 +++++-------------------
1 file changed, 5 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index e1d6764..425a291 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -39,29 +39,14 @@ int hi3xxx_get_cpu_jump(int cpu)
return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
}
-static void __init hisi_enable_scu_a9(void)
-{
- unsigned long base = 0;
- void __iomem *scu_base = NULL;
-
- if (scu_a9_has_base()) {
- base = scu_a9_get_base();
- scu_base = ioremap(base, SZ_4K);
- if (!scu_base) {
- pr_err("ioremap(scu_base) failed\n");
- return;
- }
- scu_enable(scu_base);
- iounmap(scu_base);
- }
-}
-
static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np = NULL;
u32 offset = 0;
- hisi_enable_scu_a9();
+ if (scu_a9_has_base())
+ of_scu_enable();
+
if (!ctrl_base) {
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
@@ -100,7 +85,8 @@ static const struct smp_operations hi3xxx_smp_ops __initconst = {
static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
{
- hisi_enable_scu_a9();
+ if (scu_a9_has_base())
+ of_scu_enable();
}
static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
--
2.7.4
^ permalink raw reply related
* [PATCH 13/16] ARM: zynq: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
At the same time this patch cleans up mach-zynq platform files by
removing static mapping of SCU and dropping zynq_scu_map_io and zynq_map_io
functions.
CC: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-zynq/common.c | 32 +-------------------------------
arch/arm/mach-zynq/common.h | 2 --
arch/arm/mach-zynq/platsmp.c | 2 ++
3 files changed, 3 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index d12002c..3986b2b 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -38,7 +38,6 @@
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
-#include <asm/smp_scu.h>
#include <asm/system_info.h>
#include <asm/hardware/cache-l2x0.h>
@@ -48,8 +47,6 @@
#define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28
#define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF
-void __iomem *zynq_scu_base;
-
/**
* zynq_memory_init - Initialize special memory
*
@@ -153,33 +150,6 @@ static void __init zynq_timer_init(void)
clocksource_probe();
}
-static struct map_desc zynq_cortex_a9_scu_map __initdata = {
- .length = SZ_256,
- .type = MT_DEVICE,
-};
-
-static void __init zynq_scu_map_io(void)
-{
- unsigned long base;
-
- base = scu_a9_get_base();
- zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base);
- /* Expected address is in vmalloc area that's why simple assign here */
- zynq_cortex_a9_scu_map.virtual = base;
- iotable_init(&zynq_cortex_a9_scu_map, 1);
- zynq_scu_base = (void __iomem *)base;
- BUG_ON(!zynq_scu_base);
-}
-
-/**
- * zynq_map_io - Create memory mappings needed for early I/O.
- */
-static void __init zynq_map_io(void)
-{
- debug_ll_io_init();
- zynq_scu_map_io();
-}
-
static void __init zynq_irq_init(void)
{
zynq_early_slcr_init();
@@ -196,7 +166,7 @@ DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
.l2c_aux_val = 0x00400000,
.l2c_aux_mask = 0xffbfffff,
.smp = smp_ops(zynq_smp_ops),
- .map_io = zynq_map_io,
+ .map_io = debug_ll_io_init,
.init_irq = zynq_irq_init,
.init_machine = zynq_init_machine,
.init_late = zynq_init_late,
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index e771933..7c2f008 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -33,8 +33,6 @@ extern int zynq_cpun_start(u32 address, int cpu);
extern const struct smp_operations zynq_smp_ops;
#endif
-extern void __iomem *zynq_scu_base;
-
void zynq_pm_late_init(void);
static inline void zynq_core_pm_init(void)
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 7cd9865..2d09119 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -33,6 +33,7 @@
* be called from zynq_cpun_start() because it is not in __init section.
*/
static int ncores;
+static void __iomem *zynq_scu_base;
int zynq_cpun_start(u32 address, int cpu)
{
@@ -108,6 +109,7 @@ static void __init zynq_smp_init_cpus(void)
static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
{
+ zynq_scu_base = of_scu_get_base();
scu_enable(zynq_scu_base);
}
--
2.7.4
^ permalink raw reply related
* [PATCH 12/16] ARM: imx: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
At the same time this patch cleans up mach-imx platform files by
removing static mapping of SCU and dropping imx_scu_map_io function.
CC: Shawn Guo <shawnguo@kernel.org>
CC: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-imx/common.h | 5 -----
arch/arm/mach-imx/mach-imx6q.c | 8 +-------
arch/arm/mach-imx/platsmp.c | 32 +++++---------------------------
arch/arm/mach-imx/pm-imx6.c | 3 ++-
4 files changed, 8 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c4436d9..9787d5f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -87,11 +87,6 @@ u32 imx_get_cpu_arg(int cpu);
void imx_set_cpu_arg(int cpu, u32 arg);
#ifdef CONFIG_SMP
void v7_secondary_startup(void);
-void imx_scu_map_io(void);
-void imx_smp_prepare(void);
-#else
-static inline void imx_scu_map_io(void) {}
-static inline void imx_smp_prepare(void) {}
#endif
void imx_src_init(void);
void imx_gpc_pre_suspend(bool arm_power_off);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 45801b2..1c6cc9f 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -383,12 +383,6 @@ static void __init imx6q_init_late(void)
}
}
-static void __init imx6q_map_io(void)
-{
- debug_ll_io_init();
- imx_scu_map_io();
-}
-
static void __init imx6q_init_irq(void)
{
imx_gpc_check_dt();
@@ -410,7 +404,7 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.smp = smp_ops(imx_smp_ops),
- .map_io = imx6q_map_io,
+ .map_io = debug_ll_io_init,
.init_irq = imx6q_init_irq,
.init_machine = imx6q_init_machine,
.init_late = imx6q_init_late,
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 711dbbd..c032369 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -26,26 +26,6 @@
u32 g_diag_reg;
static void __iomem *scu_base;
-static struct map_desc scu_io_desc __initdata = {
- /* .virtual and .pfn are run-time assigned */
- .length = SZ_4K,
- .type = MT_DEVICE,
-};
-
-void __init imx_scu_map_io(void)
-{
- unsigned long base;
-
- /* Get SCU base */
- asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
-
- scu_io_desc.virtual = IMX_IO_P2V(base);
- scu_io_desc.pfn = __phys_to_pfn(base);
- iotable_init(&scu_io_desc, 1);
-
- scu_base = IMX_IO_ADDRESS(base);
-}
-
static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
imx_set_cpu_jump(cpu, v7_secondary_startup);
@@ -61,20 +41,18 @@ static void __init imx_smp_init_cpus(void)
{
int i, ncores;
- ncores = scu_get_core_count(scu_base);
+ if (!IS_ERR(scu_base))
+ ncores = scu_get_core_count(scu_base);
for (i = ncores; i < NR_CPUS; i++)
set_cpu_possible(i, false);
}
-void imx_smp_prepare(void)
-{
- scu_enable(scu_base);
-}
-
static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
{
- imx_smp_prepare();
+ scu_base = of_scu_get_base();
+ if (!IS_ERR(scu_base))
+ scu_enable(scu_base);
/*
* The diagnostic register holds the errata bits. Mostly bootloader
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 1515e49..859aacb 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -26,6 +26,7 @@
#include <asm/fncpy.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
+#include <asm/smp_scu.h>
#include <asm/tlb.h>
#include "common.h"
@@ -393,7 +394,7 @@ static int imx6q_pm_enter(suspend_state_t state)
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
if (cpu_is_imx6q() || cpu_is_imx6dl())
- imx_smp_prepare();
+ of_scu_enable();
imx_anatop_post_resume();
imx_gpc_post_resume();
imx6_enable_rbc(false);
--
2.7.4
^ permalink raw reply related
* [PATCH 11/16] ARM: rockchip: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Heiko Stuebner <heiko@sntech.de>
CC: linux-rockchip at lists.infradead.org
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-rockchip/platsmp.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 4d827a0..31169cf 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -282,21 +282,15 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
if (has_pmu && rockchip_smp_prepare_pmu())
return;
- if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+ if (scu_a9_has_base()) {
if (rockchip_smp_prepare_sram(node))
return;
/* enable the SCU power domain */
pmu_set_power_domain(PMU_PWRDN_SCU, true);
- node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
- if (!node) {
- pr_err("%s: missing scu\n", __func__);
- return;
- }
-
- scu_base_addr = of_iomap(node, 0);
- if (!scu_base_addr) {
+ scu_base_addr = of_scu_get_base();
+ if (IS_ERR(scu_base_addr)) {
pr_err("%s: could not map scu registers\n", __func__);
return;
}
--
2.7.4
^ permalink raw reply related
* [PATCH 10/16] ARM: tegra: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: linux-tegra at vger.kernel.org
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-tegra/platsmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 75620ae..3467617 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -179,7 +179,7 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
cpumask_set_cpu(0, &tegra_cpu_init_mask);
if (scu_a9_has_base())
- scu_enable(IO_ADDRESS(scu_a9_get_base()));
+ of_scu_enable();
}
const struct smp_operations tegra_smp_ops __initconst = {
--
2.7.4
^ permalink raw reply related
* [PATCH 09/16] ARM: BCM: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Florian Fainelli <f.fainelli@gmail.com>
CC: Ray Jui <rjui@broadcom.com>
CC: Scott Branden <sbranden@broadcom.com>
CC: bcm-kernel-feedback-list at broadcom.com
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-bcm/bcm63xx_smp.c | 18 ++--------------
arch/arm/mach-bcm/platsmp.c | 46 +----------------------------------------
2 files changed, 3 insertions(+), 61 deletions(-)
diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c
index 9b6727e..a4c6ecd 100644
--- a/arch/arm/mach-bcm/bcm63xx_smp.c
+++ b/arch/arm/mach-bcm/bcm63xx_smp.c
@@ -20,9 +20,6 @@
#include "bcm63xx_smp.h"
-/* Size of mapped Cortex A9 SCU address space */
-#define CORTEX_A9_SCU_SIZE 0x58
-
/*
* Enable the Cortex A9 Snoop Control Unit
*
@@ -35,7 +32,6 @@
*/
static int __init scu_a9_enable(void)
{
- unsigned long config_base;
void __iomem *scu_base;
unsigned int i, ncores;
@@ -44,19 +40,9 @@ static int __init scu_a9_enable(void)
return -ENXIO;
}
- /* Config base address register value is zero for uniprocessor */
- config_base = scu_a9_get_base();
- if (!config_base) {
- pr_err("hardware reports only one core\n");
- return -ENOENT;
- }
-
- scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
- if (!scu_base) {
- pr_err("failed to remap config base (%lu/%u) for SCU\n",
- config_base, CORTEX_A9_SCU_SIZE);
+ scu_base = of_scu_get_base();
+ if (IS_ERR(scu_base))
return -ENOMEM;
- }
scu_enable(scu_base);
diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
index 3ac3a9b..743599a 100644
--- a/arch/arm/mach-bcm/platsmp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -28,9 +28,6 @@
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
-/* Size of mapped Cortex A9 SCU address space */
-#define CORTEX_A9_SCU_SIZE 0x58
-
#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
#define BOOT_ADDR_CPUID_MASK 0x3
@@ -38,47 +35,6 @@
#define OF_SECONDARY_BOOT "secondary-boot-reg"
#define MPIDR_CPUID_BITMASK 0x3
-/*
- * Enable the Cortex A9 Snoop Control Unit
- *
- * By the time this is called we already know there are multiple
- * cores present. We assume we're running on a Cortex A9 processor,
- * so any trouble getting the base address register or getting the
- * SCU base is a problem.
- *
- * Return 0 if successful or an error code otherwise.
- */
-static int __init scu_a9_enable(void)
-{
- unsigned long config_base;
- void __iomem *scu_base;
-
- if (!scu_a9_has_base()) {
- pr_err("no configuration base address register!\n");
- return -ENXIO;
- }
-
- /* Config base address register value is zero for uniprocessor */
- config_base = scu_a9_get_base();
- if (!config_base) {
- pr_err("hardware reports only one core\n");
- return -ENOENT;
- }
-
- scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
- if (!scu_base) {
- pr_err("failed to remap config base (%lu/%u) for SCU\n",
- config_base, CORTEX_A9_SCU_SIZE);
- return -ENOMEM;
- }
-
- scu_enable(scu_base);
-
- iounmap(scu_base); /* That's the last we'll need of this */
-
- return 0;
-}
-
static u32 secondary_boot_addr_for(unsigned int cpu)
{
u32 secondary_boot_addr = 0;
@@ -134,7 +90,7 @@ static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
/* Enable the SCU on Cortex A9 based SoCs */
- if (scu_a9_enable()) {
+ if (of_scu_enable()) {
/* Update the CPU present map to reflect uniprocessor mode */
pr_warn("failed to enable A9 SCU - disabling SMP\n");
init_cpu_present(&only_cpu_0);
--
2.7.4
^ permalink raw reply related
* [PATCH 08/16] ARM: vexpress: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Sudeep Holla <sudeep.holla@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-vexpress/platsmp.c | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 8b8d072..17dee2b 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -41,20 +41,9 @@ bool __init vexpress_smp_init_ops(void)
return false;
}
-static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = {
- { .compatible = "arm,cortex-a5-scu", },
- { .compatible = "arm,cortex-a9-scu", },
- {}
-};
-
static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus)
{
- struct device_node *scu = of_find_matching_node(NULL,
- vexpress_smp_dt_scu_match);
-
- if (scu)
- scu_enable(of_iomap(scu, 0));
-
+ of_scu_enable();
/*
* Write the address of secondary startup into the
* system-wide flags register. The boot monitor waits
--
2.7.4
^ permalink raw reply related
* [PATCH 07/16] ARM: ux500: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-ux500/platsmp.c | 20 +-------------------
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 8f2f615..e1927ae 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -66,28 +66,10 @@ static void wakeup_secondary(void)
static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
{
- struct device_node *np;
- static void __iomem *scu_base;
- unsigned int ncores;
- int i;
-
- np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
- if (!np) {
- pr_err("No SCU base address\n");
- return;
- }
- scu_base = of_iomap(np, 0);
- of_node_put(np);
- if (!scu_base) {
+ if (of_scu_enable()) {
pr_err("No SCU remap\n");
return;
}
-
- scu_enable(scu_base);
- ncores = scu_get_core_count(scu_base);
- for (i = 0; i < ncores; i++)
- set_cpu_possible(i, true);
- iounmap(scu_base);
}
static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
--
2.7.4
^ permalink raw reply related
* [PATCH 06/16] ARM: STi: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-sti/platsmp.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
index ea5a227..0bc7ff8 100644
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -99,19 +99,12 @@ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
- void __iomem *scu_base;
u32 __iomem *cpu_strt_ptr;
u32 release_phys;
int cpu;
unsigned long entry_pa = virt_to_phys(sti_secondary_startup);
- np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
-
- if (np) {
- scu_base = of_iomap(np, 0);
- scu_enable(scu_base);
- of_node_put(np);
- }
+ of_scu_enable();
if (max_cpus <= 1)
return;
--
2.7.4
^ permalink raw reply related
* [PATCH 05/16] ARM: socfpga: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-socfpga/platsmp.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 0794574..d3f0a07 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -79,19 +79,10 @@ static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle
static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
{
- struct device_node *np;
- void __iomem *socfpga_scu_base_addr;
-
- np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
- if (!np) {
+ if (of_scu_enable()) {
pr_err("%s: missing scu\n", __func__);
return;
}
-
- socfpga_scu_base_addr = of_iomap(np, 0);
- if (!socfpga_scu_base_addr)
- return;
- scu_enable(socfpga_scu_base_addr);
}
#ifdef CONFIG_HOTPLUG_CPU
--
2.7.4
^ permalink raw reply related
* [PATCH 04/16] ARM: realview: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
Also this patch removes computation of number of cores
from SCU, as for DT platform it will be taken care from
DT CPU device nodes.
CC: Russell King <linux@armlinux.org.uk>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-realview/platsmp-dt.c | 29 +++++++++--------------------
1 file changed, 9 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-realview/platsmp-dt.c
index 70ca99e..b2dbf77 100644
--- a/arch/arm/mach-realview/platsmp-dt.c
+++ b/arch/arm/mach-realview/platsmp-dt.c
@@ -23,8 +23,6 @@
static const struct of_device_id realview_scu_match[] = {
{ .compatible = "arm,arm11mp-scu", },
- { .compatible = "arm,cortex-a9-scu", },
- { .compatible = "arm,cortex-a5-scu", },
{ }
};
@@ -41,27 +39,18 @@ static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
struct device_node *np;
void __iomem *scu_base;
struct regmap *map;
- unsigned int ncores;
int i;
- np = of_find_matching_node(NULL, realview_scu_match);
- if (!np) {
- pr_err("PLATSMP: No SCU base address\n");
- return;
+ if (of_scu_enable()) {
+ np = of_find_matching_node(NULL, realview_scu_match);
+ scu_base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!scu_base) {
+ pr_err("PLATSMP: No SCU remap\n");
+ return;
+ }
+ scu_enable(scu_base);
}
- scu_base = of_iomap(np, 0);
- of_node_put(np);
- if (!scu_base) {
- pr_err("PLATSMP: No SCU remap\n");
- return;
- }
-
- scu_enable(scu_base);
- ncores = scu_get_core_count(scu_base);
- pr_info("SCU: %d cores detected\n", ncores);
- for (i = 0; i < ncores; i++)
- set_cpu_possible(i, true);
- iounmap(scu_base);
/* The syscon contains the magic SMP start address registers */
np = of_find_matching_node(NULL, realview_syscon_match);
--
2.7.4
^ permalink raw reply related
* [PATCH 03/16] ARM: berlin: use generic API for enabling SCU
From: Pankaj Dubey @ 2016-11-14 5:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
CC: Jisheng Zhang <jszhang@marvell.com>
CC: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-berlin/platsmp.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
index 93f9068..25a6ca5 100644
--- a/arch/arm/mach-berlin/platsmp.c
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -60,26 +60,21 @@ static int berlin_boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
- void __iomem *scu_base;
void __iomem *vectors_base;
- np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
- scu_base = of_iomap(np, 0);
- of_node_put(np);
- if (!scu_base)
- return;
-
np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl");
cpu_ctrl = of_iomap(np, 0);
of_node_put(np);
if (!cpu_ctrl)
- goto unmap_scu;
+ return;
vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
if (!vectors_base)
- goto unmap_scu;
+ return;
+
+ if (of_scu_enable())
+ return;
- scu_enable(scu_base);
flush_cache_all();
/*
@@ -95,8 +90,6 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
iounmap(vectors_base);
-unmap_scu:
- iounmap(scu_base);
}
#ifdef CONFIG_HOTPLUG_CPU
--
2.7.4
^ permalink raw reply related
* [PATCH 02/16] ARM: EXYNOS: use generic API to enable SCU
From: Pankaj Dubey @ 2016-11-14 5:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Now as we have of_scu_enable which takes care of mapping
scu base from DT, lets use it.
This patch also fixes build failure in case !SMP caused
by commit SHA ID: 94210b1abb2 which is already merged in
krzk/for-next branch
CC: Krzysztof Kozlowski <krzk@kernel.org>
CC: linux-samsung-soc at vger.kernel.org
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/mach-exynos/common.h | 1 -
arch/arm/mach-exynos/platsmp.c | 30 ++++--------------------------
arch/arm/mach-exynos/pm.c | 4 ++--
arch/arm/mach-exynos/suspend.c | 14 ++++----------
4 files changed, 10 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index fb12d11..d19064b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -156,7 +156,6 @@ extern void exynos_cpu_restore_register(void);
extern void exynos_pm_central_suspend(void);
extern int exynos_pm_central_resume(void);
extern void exynos_enter_aftr(void);
-extern int exynos_scu_enable(void);
extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 94405c7..2e5ecc1 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -168,27 +168,6 @@ int exynos_cluster_power_state(int cluster)
S5P_CORE_LOCAL_PWR_EN);
}
-/**
- * exynos_scu_enable : enables SCU for Cortex-A9 based system
- * returns 0 on success else non-zero error code
- */
-int exynos_scu_enable(void)
-{
- struct device_node *np;
- void __iomem *scu_base;
-
- np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
- scu_base = of_iomap(np, 0);
- of_node_put(np);
- if (!scu_base) {
- pr_err("%s failed to map scu_base\n", __func__);
- return -ENOMEM;
- }
- scu_enable(scu_base);
- iounmap(scu_base);
- return 0;
-}
-
static void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
@@ -409,11 +388,10 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
exynos_set_delayed_reset_assertion(true);
- if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
- /* if exynos_scu_enable fails, return */
- if (exynos_scu_enable())
- return;
- }
+ /* if of_scu_enable fails, return */
+ if (scu_a9_has_base() && of_scu_enable())
+ return;
+
/*
* Write the address of secondary startup into the
* system-wide flags register. The boot monitor waits
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c0b46c3..9678438 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -174,8 +174,8 @@ void exynos_enter_aftr(void)
cpu_suspend(0, exynos_aftr_finisher);
- if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
- exynos_scu_enable();
+ if (scu_a9_has_base()) {
+ of_scu_enable();
if (call_firmware_op(resume) == -ENOSYS)
exynos_cpu_restore_register();
}
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 73df9f3..5414282 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -451,19 +451,16 @@ static void exynos_pm_release_retention(void)
static void exynos_pm_resume(void)
{
- u32 cpuid = read_cpuid_part();
-
if (exynos_pm_central_resume())
goto early_wakeup;
/* For release retention */
exynos_pm_release_retention();
- if (cpuid == ARM_CPU_PART_CORTEX_A9)
- exynos_scu_enable();
+ if (scu_a9_has_base())
+ of_scu_enable();
- if (call_firmware_op(resume) == -ENOSYS
- && cpuid == ARM_CPU_PART_CORTEX_A9)
+ if (call_firmware_op(resume) == -ENOSYS && scu_a9_has_base())
exynos_cpu_restore_register();
early_wakeup:
@@ -475,8 +472,6 @@ static void exynos_pm_resume(void)
static void exynos3250_pm_resume(void)
{
- u32 cpuid = read_cpuid_part();
-
if (exynos_pm_central_resume())
goto early_wakeup;
@@ -485,8 +480,7 @@ static void exynos3250_pm_resume(void)
pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
- if (call_firmware_op(resume) == -ENOSYS
- && cpuid == ARM_CPU_PART_CORTEX_A9)
+ if (call_firmware_op(resume) == -ENOSYS && scu_a9_has_base())
exynos_cpu_restore_register();
early_wakeup:
--
2.7.4
^ permalink raw reply related
* [PATCH 01/16] ARM: scu: Provide support for parsing SCU device node to enable SCU
From: Pankaj Dubey @ 2016-11-14 5:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-1-git-send-email-pankaj.dubey@samsung.com>
Many platforms are duplicating code for enabling SCU, lets add
common code to enable SCU by parsing SCU device node so the duplication
in each platform can be avoided.
CC: Krzysztof Kozlowski <krzk@kernel.org>
CC: Jisheng Zhang <jszhang@marvell.com>
CC: Russell King <linux@armlinux.org.uk>
CC: Dinh Nguyen <dinguyen@opensource.altera.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Ray Jui <rjui@broadcom.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Heiko Stuebner <heiko@sntech.de>
CC: Shawn Guo <shawnguo@kernel.org>
CC: Michal Simek <michal.simek@xilinx.com>
CC: Wei Xu <xuwei5@hisilicon.com>
CC: Andrew Lunn <andrew@lunn.ch>
CC: Jun Nie <jun.nie@linaro.org>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/include/asm/smp_scu.h | 4 +++
arch/arm/kernel/smp_scu.c | 56 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index bfe163c..fdeec07 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -39,8 +39,12 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
#if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
void scu_enable(void __iomem *scu_base);
+void __iomem *of_scu_get_base(void);
+int of_scu_enable(void);
#else
static inline void scu_enable(void __iomem *scu_base) {}
+static inline void __iomem *of_scu_get_base(void) {return NULL; }
+static inline int of_scu_enable(void) {return 0; }
#endif
#endif
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 72f9241..d0ac3ed 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -10,6 +10,7 @@
*/
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/of_address.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
@@ -70,6 +71,61 @@ void scu_enable(void __iomem *scu_base)
*/
flush_cache_all();
}
+
+static const struct of_device_id scu_match[] = {
+ { .compatible = "arm,cortex-a9-scu", },
+ { .compatible = "arm,cortex-a5-scu", },
+ { }
+};
+
+/*
+ * Helper API to get SCU base address
+ * In case platform DT do not have SCU node, or iomap fails
+ * this call will fallback and will try to map via call to
+ * scu_a9_get_base.
+ * This will return ownership of scu_base to the caller
+ */
+void __iomem *of_scu_get_base(void)
+{
+ unsigned long base = 0;
+ struct device_node *np;
+ void __iomem *scu_base;
+
+ np = of_find_matching_node(NULL, scu_match);
+ scu_base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!scu_base) {
+ pr_err("%s failed to map scu_base via DT\n", __func__);
+ if (scu_a9_has_base()) {
+ base = scu_a9_get_base();
+ scu_base = ioremap(base, SZ_4K);
+ }
+ if (!scu_base) {
+ pr_err("%s failed to map scu_base\n", __func__);
+ return IOMEM_ERR_PTR(-ENOMEM);
+ }
+ }
+ return scu_base;
+}
+
+/*
+ * Enable SCU via mapping scu_base DT
+ * If scu_base mapped successfully scu will be enabled and in case of
+ * failure if will return non-zero error code
+ */
+int of_scu_enable(void)
+{
+ void __iomem *scu_base;
+
+ scu_base = of_scu_get_base();
+ if (!IS_ERR(scu_base)) {
+ scu_enable(scu_base);
+ iounmap(scu_base);
+ return 0;
+ }
+ return PTR_ERR(scu_base);
+}
+
#endif
/*
--
2.7.4
^ permalink raw reply related
* [PATCH 00/16] Provide support of generic function for SCU enable
From: Pankaj Dubey @ 2016-11-14 5:01 UTC (permalink / raw)
To: linux-arm-kernel
During consolidation work on Exynos platform for SCU, it has been found
that across many ARM platforms Cortex-A9 boards, SCU enabling code is
duplicated.
Subsequently it felt that [1] by introducing generic API support in arm/smp_scu.c
file will help in removing all these duplicate work from all such platforms.
This patch series introduces support for parsting SCU device node to enable SCU
and get SCU base address. If a platform does not support SCU device node in DT, the
API will fallback to scu_a9_get_base to obtain SCU base address.
[1]: https://www.spinics.net/lists/arm-kernel/msg541830.html
Arnd helped in consolidating various ARM platforms duplicating SCU code as below:
a) of_iomap: berlin, exynos, mvebu, realview, rockchip, socfpga, sti, ux500, vexpress
b) ioremap(scu_a9_get_base()): bcm63xx, bcm, hisi, zx
c) iotable_init, scu_a9_get_base(): imx, omap4, tegra, zynq
d) ioremap(constant): shmobile, spear13xx
Based on his suggestion on how to move all these platform to use generic API
I have modified EXYNOS, berlin, realview, socfpga, STi, ux500, vexpress, BCM,
tegra, rockchip, imx, zynq, hisi, mvebu and ZX platform files to adopt generic API for
SCU enabling to obtaining SCU base address.
Only fourth case shmobile and spear13xx will be left to adopt to this new API after this,
which I felt some details information about these platforms and I leave it to the maintainers
of these platforms.
NOTE: This patch series has been tested on EXYNOS platform using Exynos4210 based Origen board
for SMP boot.
Rest platforms are *ONLY* Compiled Tested.
I request maintainers/developers having h/w of these platforms to test this series on their
platforms.
Pankaj Dubey (16):
ARM: scu: Provide support for parsing SCU device node to enable SCU
ARM: EXYNOS: use generic API to enable SCU
ARM: berlin: use generic API for enabling SCU
ARM: realview: use generic API for enabling SCU
ARM: socfpga: use generic API for enabling SCU
ARM: STi: use generic API for enabling SCU
ARM: ux500: use generic API for enabling SCU
ARM: vexpress: use generic API for enabling SCU
ARM: BCM: use generic API for enabling SCU
ARM: tegra: use generic API for enabling SCU
ARM: rockchip: use generic API for enabling SCU
ARM: imx: use generic API for enabling SCU
ARM: zynq: use generic API for enabling SCU
ARM: hisi: use generic API for enabling SCU
ARM: mvebu: use generic API for enabling SCU
ARM: zx: use generic API for enabling SCU
arch/arm/include/asm/smp_scu.h | 4 +++
arch/arm/kernel/smp_scu.c | 56 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-bcm/bcm63xx_smp.c | 18 ++----------
arch/arm/mach-bcm/platsmp.c | 46 +-----------------------------
arch/arm/mach-berlin/platsmp.c | 17 ++++-------
arch/arm/mach-exynos/common.h | 1 -
arch/arm/mach-exynos/platsmp.c | 30 +++-----------------
arch/arm/mach-exynos/pm.c | 4 +--
arch/arm/mach-exynos/suspend.c | 14 +++-------
arch/arm/mach-hisi/platsmp.c | 24 ++++------------
arch/arm/mach-imx/common.h | 5 ----
arch/arm/mach-imx/mach-imx6q.c | 8 +-----
arch/arm/mach-imx/platsmp.c | 32 ++++-----------------
arch/arm/mach-imx/pm-imx6.c | 3 +-
arch/arm/mach-mvebu/board-v7.c | 8 ++----
arch/arm/mach-realview/platsmp-dt.c | 29 ++++++-------------
arch/arm/mach-rockchip/platsmp.c | 12 ++------
arch/arm/mach-socfpga/platsmp.c | 11 +-------
arch/arm/mach-sti/platsmp.c | 9 +-----
arch/arm/mach-tegra/platsmp.c | 2 +-
arch/arm/mach-ux500/platsmp.c | 20 +------------
arch/arm/mach-vexpress/platsmp.c | 13 +--------
arch/arm/mach-zx/platsmp.c | 6 ++--
arch/arm/mach-zynq/common.c | 32 +--------------------
arch/arm/mach-zynq/common.h | 2 --
arch/arm/mach-zynq/platsmp.c | 2 ++
26 files changed, 115 insertions(+), 293 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH 01/14] dma: sun6i-dma: Add burst case of 4
From: Vinod Koul @ 2016-11-14 4:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65yR9NOff+VDA0cBj3UenGpdYUfnYfesnmzP8AN4uw4Tw@mail.gmail.com>
On Tue, Nov 01, 2016 at 10:55:13PM +0800, Chen-Yu Tsai wrote:
> >> * @src_maxburst: the maximum number of words (note: words, as in
> >> * units of the src_addr_width member, not bytes) that can be sent
> >> * in one burst to the device. Typically something like half the
> >> * FIFO depth on I/O peripherals so you don't overflow it. This
> >> * may or may not be applicable on memory sources.
> >> * @dst_maxburst: same as src_maxburst but for destination target
> >> * mutatis mutandis.
> >>
> >> The DMA engine driver should be free to select whatever burst size
> >> that doesn't exceed this. So for max_burst = 4, the driver can select
> >> burst = 4 for controllers that do support it, or burst = 1 for those
> >> that don't, and do more bursts.
> >
> > Nope, the client configures these parameters and dmaengine driver
> > validates and programs
>
> Shouldn't we just name it "burst_size" then if it's meant to be what
> the client specifically asks for?
Well if for some reason we program lesser than than max it would work
technically. But a larger burst wont work at all, so thats why maxburst is
significant.
> My understanding is that the client configures its own parameters,
> such as the trigger level for the DRQ, like raise DRQ when level < 1/4
> FIFO depth, request maxburst = 1/4 or 1/2 FIFO depth, so as not to
> overrun the FIFO. When the DRQ is raised, the DMA engine will do a
> burst, and after the burst the DRQ would be low again, so the DMA
> engine will wait. So the DMA engine driver should be free to
> program the actual burst size to something less than maxburst, shouldn't
> it?
Yup but not more that max..
> >> This also means we can increase max_burst for the audio codec, as
> >> the FIFO is 64 samples deep for stereo, or 128 samples for mono.
> >
> > Beware that higher bursts means chance of underrun of FIFO. This value
> > is selected with consideration of power and performance required. Lazy
> > allocation would be half of FIFO size..
>
> You mean underrun if its the source right? So the client setting maxburst
> should take the DRQ trigger level into account for this.
Yes
--
~Vinod
^ permalink raw reply
* [PATCH] arm64: dts: rockchip: add gmac needed clk for rk3399 pd
From: Caesar Wang @ 2016-11-14 4:36 UTC (permalink / raw)
To: linux-arm-kernel
From: Jeffy Chen <jeffy.chen@rock-chips.com>
This patch fixes that sometimes hang at start-up time of the system.
As the below log:
...
[ 11.136543] calling pm_genpd_debug_init+0x0/0x60 @ 1
[ 11.141602] initcall pm_genpd_debug_init+0x0/0x60 returned 0 after 11 usecs
[ 11.148558] calling genpd_poweroff_unused+0x0/0x84 @ 1
<hang>
In some cases, the rk3399 should turn off the gmac power domain to save
power if some boards didn't register the gmac device node for rk3399.
Then, rk3399 need to make sure the gmac's pclk enabled if we need
operate the gmac power domain. (Due to the NOC had enabled always)
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 172e7ed..e8b9df9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -825,7 +825,8 @@
/* These power domains are grouped by VD_LOGIC */
pd_gmac at RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
- clocks = <&cru ACLK_GMAC>;
+ clocks = <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
pm_qos = <&qos_gmac>;
};
pd_vio at RK3399_PD_VIO {
--
2.7.4
^ permalink raw reply related
* [PATCH v16 0/5] Mediatek MT8173 CMDQ support
From: Jassi Brar @ 2016-11-14 4:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478856898.8781.6.camel@mtksdaap41>
On 11 November 2016 at 15:04, Horng-Shyang Liao <hs.liao@mediatek.com> wrote:
> On Fri, 2016-11-11 at 11:15 +0530, Jassi Brar wrote:
>> On Thu, Nov 10, 2016 at 4:45 PM, Horng-Shyang Liao <hs.liao@mediatek.com> wrote:
>> > On Tue, 2016-11-01 at 19:28 +0800, HS Liao wrote:
>> >> Hi,
>> >>
>> >> This is Mediatek MT8173 Command Queue(CMDQ) driver. The CMDQ is used
>> >> to help write registers with critical time limitation, such as
>> >> updating display configuration during the vblank. It controls Global
>> >> Command Engine (GCE) hardware to achieve this requirement.
>> >>
>> >> These patches have a build dependency on top of v4.9-rc1.
>> >>
>> >> Changes since v15:
>> >> - separate "suspend and resume" patch from "save energy" patch
>> >> - don't stop running tasks in cmdq_suspend()
>> >> (i.e. leave no running tasks guarantee to clients)
>> >>
>> >> Best regards,
>> >> HS Liao
>> >>
>> >> HS Liao (5):
>> >> dt-bindings: soc: Add documentation for the MediaTek GCE unit
>> >> CMDQ: Mediatek CMDQ driver
>> >> arm64: dts: mt8173: Add GCE node
>> >> CMDQ: suspend and resume
>> >> CMDQ: save energy
>> >>
>> >> .../devicetree/bindings/mailbox/mtk-gce.txt | 43 ++
>> >> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 +
>> >> drivers/mailbox/Kconfig | 10 +
>> >> drivers/mailbox/Makefile | 2 +
>> >> drivers/mailbox/mtk-cmdq-mailbox.c | 632 +++++++++++++++++++++
>> >> drivers/soc/mediatek/Kconfig | 11 +
>> >> drivers/soc/mediatek/Makefile | 1 +
>> >> drivers/soc/mediatek/mtk-cmdq-helper.c | 310 ++++++++++
>> >> include/linux/mailbox/mtk-cmdq-mailbox.h | 67 +++
>> >> include/linux/soc/mediatek/mtk-cmdq.h | 182 ++++++
>> >> 10 files changed, 1268 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/mailbox/mtk-gce.txt
>> >> create mode 100644 drivers/mailbox/mtk-cmdq-mailbox.c
>> >> create mode 100644 drivers/soc/mediatek/mtk-cmdq-helper.c
>> >> create mode 100644 include/linux/mailbox/mtk-cmdq-mailbox.h
>> >> create mode 100644 include/linux/soc/mediatek/mtk-cmdq.h
>> >>
>> >
>> >
>> > Hi Jassi, Matthias,
>> >
>> > Sorry to disturb you.
>> >
>> No, you don't disturb, but the controller driver and protocol driver,
>> introduced in the same patch, does :) So does the suspend/resume
>> support (patch 4&5) added separately as a patch on top. Please
>> reorganise the patchset.
>>
>> Thanks.
>
> Hi Jassi,
>
> Do you mean
> 1. split controller driver and protocol driver as two patches,
> 2. merge patch 4&5 into one patch, and
> 3. reorganize the patchset as "(1) binding doc (2) controller driver
> (3) protocol driver (4) devicetree (5) energy patch" ?
>
Merge any patch to controller driver, in the patch that adds the
controller driver. Protocol driver patch should be the last in the
series.
^ permalink raw reply
* [PATCH fpga 8/9] fpga socfpga: Use the scatterlist interface
From: atull @ 2016-11-14 4:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114001854.GA27248@obsidianresearch.com>
On Mon, 14 Nov 2016, Jason Gunthorpe wrote:
> On Sun, Nov 13, 2016 at 05:19:34PM -0600, atull wrote:
>
> > Currently or soon we have 3 drivers that don't really use the sg
> > interface natively. So this workaround ends up in each of them?
>
> Thinking of the SG list as a workaround is not really right - the SG
> list is a way to pass memory stored in non-contiguous pages around,
> and the miter is a way to access them from the CPU.
No, I ment the other way. The changes to socfpga.c are a workaround
to the sg-centric interface. And other drivers will need the same
workaround. But below I see you understand...
>
> socfpga *does* use sg natively because it is happy to process the data
> from the CPU page-at-time. It just doesn't use DMA.
>
> > That's a lot of duplicated code. Why can't this code be in the
> > fpga-mgr.c core for drivers that aren't using sg (to minimizing
> > duplication).
>
> Sure, if it is a common pattern it is a good idea to lift it.
>
> I'd add a newop 'write_fragment' and a driver must define write_sg
> write_fragment, if write_fragment is used then the core supplies
> that loop.
Sure, but isn't that just the old op? :)
There may also be common code that you added to configure_init
that should go in the core unless it's fpga-specific.
>
> Is there a tree with these new drivers someplace?
The arria10 driver is on linux-next master branch. There are two
others on the mailing list now. linux-next also contains other
changes to the FPGA mgr API that will affect your patches in minor
ways, so you should rebase you patches.
>
> > I will test this when I get time, may not be this week. I just
> > moved to a new building and lab and am in a course all week and
> > so forth.
>
> Sure, I don't expect any problems, Zynq uses the same loop and it
> seems fine.
>
> Jason
>
^ permalink raw reply
* [PATCH V3 0/8] IOMMU probe deferral support
From: Sricharan @ 2016-11-14 3:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9f36244f-62d4-08e3-d64a-2b04ad4dc2e0@arm.com>
Hi Robin,
>Hi Robin,
>
>>On 04/11/16 15:16, Sricharan wrote:
>>> Hi Robin,
>>>
>>>>>> Yikes, on second look, that definitely shouldn't be happening.
>>>>>> Everything below is probably the resulting fallout.
>>>>>
>>>>> [ 40.206703] vfio-pci 0000:08:00.0: Failed to setup iommu ops
>>>>>
>>>>> I think the above print which says "failed to setup iommu_ops"
>>>>> because the call ops->add_device failed in of_pci_iommu_configure
>>>>> is the reason for the failure, in my case i simply do not get this even with
>>>>> your scripts. ops->add_device succeeds in the rebind as well. So still
>>>>> checking what could be happening in your case.
>>>>
>>>> I was looking at your code base from [1].The ops->add_device
>>>> callback from of_pci_iommu_configure on the rebind is the
>>>> one which is causing the failure. But not able to spot out
>>>>from code which point is causing the failure. It would be very helpful
>>>> if i can know which is the return value from the add_device callback
>>>> or point inside add_device callback which fails in your setup.
>>>>
>>>>
>>>> [1] git://linux-arm.org/linux-rm iommu/misc
>>>
>>> With little more try, i saw an issue where i had an failure
>>> similar to what you reported. The issue happens when multiple
>>> devices fall in to same group due to matching sids. I ended up
>>> doing a fix like below and it would be nice to verify if it is the same
>>> that we are seeing in your setup and if the fix makes a difference ?
>>>
>>> From: Sricharan R <sricharan@codeaurora.org>
>>> Date: Fri, 4 Nov 2016 20:28:49 +0530
>>> Subject: [PATCH] iommu/arm-smmu: Fix group's reference counting
>>>
>>> iommu_group_get_for_dev which gets called in the add_device
>>> callback, increases the reference count of the iommu_group,
>>> so we do an iommu_group_put after that. iommu_group_get_for_dev
>>> inturn calls device_group callback and in the case of arm-smmu
>>> we call generic_device_group/pci_device_group which takes
>>> care of increasing the group's reference. But when we return
>>> an already existing group(when multiple devices have same group)
>>> the reference is not incremented, resulting in issues when the
>>> remove_device callback for the devices is invoked.
>>> Fixing the same here.
>>
>>Bah, yes, this does look like my fault - after flip-flopping between
>>about 3 different ways to keep refcounts for the S2CR entries, none of
>>which would quite work, I ripped it all out but apparently still got
>>things wrong, oh well. Thanks for figuring it out.
> >
>>On the probe-deferral angle, whilst it's useful to have uncovered this
>>bug, I don't think we should actually be calling remove_device() from
>>DMA teardown. I think it's preferable from a user perspective if group
>>numbering remains stable, rather than changing depending on the order in
>>which they unbind/rebind VFIO drivers. I'm really keen to try and get
>>this in shape for 4.10, so I've taken the liberty of hacking up my own
>>branch (iommu/defer) based on v3 - would you mind taking a look at the
>>two "iommu/of:" commits to see what you think? (Ignore the PCI changes
>>to your later patches - that was an experiment which didn't really work out)
>
>Ok, will take a look at this now and respond more on this.
>
Sorry for the delayed response on this. I was OOO for the last few days.
So i tested this branch and it worked fine. I tested it with a pci device
for both normal and deferred probe cases. The of/iommu patches
are the cleanup/preparation patches and it looks fine. One thing is without
calling the remove_device callback, the resources like (smes for exmaple)
and the group association of the device all remain allocated. That does not
feel correct, given that the associated device does not exist. So to
understand that, what happens with VFIO in this case which makes the
group renumbering/rebinding a problem ?
Regards,
Sricharan
^ permalink raw reply
* [PATCH V2] dmaengine: qcom_hidma: cleanup sysfs entries during remove
From: Sinan Kaya @ 2016-11-14 3:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114030452.GH3000@localhost>
On 11/13/2016 10:04 PM, Vinod Koul wrote:
> On Wed, Oct 19, 2016 at 02:42:46PM -0400, Sinan Kaya wrote:
>> The 4.8-rc8 kernel is printing duplicate file entry warnings while removing
>> the HIDMA object. This is caused by stale sysfs entries remaining from the
>> previous execution.
>>
>> _sysfs_warn_dup+0x5c/0x78
>> sysfs_add_file_mode_ns+0x13c/0x1c0
>> sysfs_create_file_ns+0x2c/0x40
>> device_create_file+0x54/0xa0
>> hidma_probe+0x7c8/0x808
>>
>> Create hidma_sysfs_init and hidma_sysfs_uninit functions and call them from
>> the probe and remove path. To do proper clean up, adding the attrs object
>> to the device data structure to keep it around until remove call is made.
>
> This doesnt apply for me, I think due to other patches applied..
>
OK. Let me rebase.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH V2] dmaengine: qcom_hidma: cleanup sysfs entries during remove
From: Vinod Koul @ 2016-11-14 3:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476902566-26676-1-git-send-email-okaya@codeaurora.org>
On Wed, Oct 19, 2016 at 02:42:46PM -0400, Sinan Kaya wrote:
> The 4.8-rc8 kernel is printing duplicate file entry warnings while removing
> the HIDMA object. This is caused by stale sysfs entries remaining from the
> previous execution.
>
> _sysfs_warn_dup+0x5c/0x78
> sysfs_add_file_mode_ns+0x13c/0x1c0
> sysfs_create_file_ns+0x2c/0x40
> device_create_file+0x54/0xa0
> hidma_probe+0x7c8/0x808
>
> Create hidma_sysfs_init and hidma_sysfs_uninit functions and call them from
> the probe and remove path. To do proper clean up, adding the attrs object
> to the device data structure to keep it around until remove call is made.
This doesnt apply for me, I think due to other patches applied..
--
~Vinod
^ permalink raw reply
* [PATCH] ARM: dts: imx6sx-udoo: Add board specific compatible strings
From: Shawn Guo @ 2016-11-14 2:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478021892-18344-1-git-send-email-fabio.estevam@nxp.com>
On Tue, Nov 01, 2016 at 03:38:12PM -0200, Fabio Estevam wrote:
> Add a compatible entry for the specific board versions.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied, thanks.
^ permalink raw reply
* [PATCH V7 1/3] tracing: add a possibility of exporting function trace to other places instead of ring buffer only
From: Chunyan Zhang @ 2016-11-14 2:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAG2=9p_SKF4TAbbqF6L4u=y9-_m73vZJ3tOAbRKHCT0MOsLwGQ@mail.gmail.com>
Hi Steve,
Resend this since the subject was lost in the prior one due to unknown reason.
On 21 October 2016 at 20:13, Chunyan Zhang <zhang.chunyan@linaro.org> wrote:
> On 18 October 2016 at 23:44, Steven Rostedt <rostedt@goodmis.org> wrote:
>> On Tue, 18 Oct 2016 16:08:58 +0800
>> Chunyan Zhang <zhang.chunyan@linaro.org> wrote:
>>
>>> Currently Function traces can be only exported to ring buffer, this
>>> patch added trace_export concept which can process traces and export
>>> them to a registered destination as an addition to the current only
>>> one output of Ftrace - i.e. ring buffer.
>>>
>>> In this way, if we want Function traces to be sent to other destination
>>> rather than ring buffer only, we just need to register a new trace_export
>>> and implement its own .write() function for writing traces to storage.
>>>
>>> With this patch, only Function trace (trace type is TRACE_FN)
>>> is supported.
>>
>> This is getting better, but I still have some nits.
>>
>
> Thanks.
>
>>>
>>> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
>>> ---
>>> include/linux/trace.h | 28 +++++++++++
>>> kernel/trace/trace.c | 132 +++++++++++++++++++++++++++++++++++++++++++++++++-
>>> 2 files changed, 159 insertions(+), 1 deletion(-)
>>> create mode 100644 include/linux/trace.h
>>>
>>> diff --git a/include/linux/trace.h b/include/linux/trace.h
>>> new file mode 100644
>>> index 0000000..eb1c5b8
>>> --- /dev/null
>>> +++ b/include/linux/trace.h
>>> @@ -0,0 +1,28 @@
>>> +#ifndef _LINUX_TRACE_H
>>> +#define _LINUX_TRACE_H
>>> +
>>> +#ifdef CONFIG_TRACING
>>> +/*
>>> + * The trace export - an export of Ftrace output. The trace_export
>>> + * can process traces and export them to a registered destination as
>>> + * an addition to the current only output of Ftrace - i.e. ring buffer.
>>> + *
>>> + * If you want traces to be sent to some other place rather than ring
>>> + * buffer only, just need to register a new trace_export and implement
>>> + * its own .write() function for writing traces to the storage.
>>> + *
>>> + * next - pointer to the next trace_export
>>> + * write - copy traces which have been delt with ->commit() to
>>> + * the destination
>>> + */
>>> +struct trace_export {
>>> + struct trace_export __rcu *next;
>>> + void (*write)(const char *, unsigned int);
>>
>> Why const char*? Why not const void *? This will never be a string.
>>
>
> Will revise this.
>
>>
>>> +};
>>> +
>>> +int register_ftrace_export(struct trace_export *export);
>>> +int unregister_ftrace_export(struct trace_export *export);
>>> +
>>> +#endif /* CONFIG_TRACING */
>>> +
>>> +#endif /* _LINUX_TRACE_H */
>>> diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
>>> index 8696ce6..db94ec1 100644
>>> --- a/kernel/trace/trace.c
>>> +++ b/kernel/trace/trace.c
>>> @@ -40,6 +40,7 @@
>>> #include <linux/poll.h>
>>> #include <linux/nmi.h>
>>> #include <linux/fs.h>
>>> +#include <linux/trace.h>
>>> #include <linux/sched/rt.h>
>>>
>>> #include "trace.h"
>>> @@ -2128,6 +2129,132 @@ void trace_buffer_unlock_commit_regs(struct trace_array *tr,
>>> ftrace_trace_userstack(buffer, flags, pc);
>>> }
>>>
>>> +static void
>>> +trace_process_export(struct trace_export *export,
>>> + struct ring_buffer_event *event)
>>> +{
>>> + struct trace_entry *entry;
>>> + unsigned int size = 0;
>>> +
>>> + entry = ring_buffer_event_data(event);
>>> +
>>> + size = ring_buffer_event_length(event);
>>> +
>>> + if (export->write)
>>> + export->write((char *)entry, size);
>>
>> Is there ever going to be a time where export->write wont be set?
>
> There hasn't been since only one trace_export (i.e. stm_ftrace) was
> added in this patch-set , I just wanted to make sure the write() has
> been set before registering trace_export like what I added in 2/3 of
> this series.
>
>>
>> And if there is, this can be racy. As in
>>
>>
>> CPU 0: CPU 1:
>> ------ ------
>> if (export->write)
>>
>> export->write = NULL;
>
> Is there going to be this kind of use case? Why some one needs to
> change export->write() rather than register a new trace_export?
>
> I probably haven't understood your point thoroughly, please correct me
> if my guess was wrong.
>
Any further comments? :)
Thanks,
Chunyan
>
> Thanks for the review,
> Chunyan
>
>>
>> export->write(entry, size);
>>
>> BOOM!
>>
>>
>> -- Steve
>>
>>> +}
>>> +
>>> +static DEFINE_MUTEX(ftrace_export_lock);
>>> +
>>> +static struct trace_export __rcu *ftrace_exports_list __read_mostly;
>>> +
>>> +static DEFINE_STATIC_KEY_FALSE(ftrace_exports_enabled);
>>> +
>>> +static inline void ftrace_exports_enable(void)
>>> +{
>>> + static_branch_enable(&ftrace_exports_enabled);
>>> +}
>>> +
>>> +static inline void ftrace_exports_disable(void)
>>> +{
>>> + static_branch_disable(&ftrace_exports_enabled);
>>> +}
>>> +
>>> +void ftrace_exports(struct ring_buffer_event *event)
>>> +{
>>> + struct trace_export *export;
>>> +
>>> + preempt_disable_notrace();
>>> +
>>> + export = rcu_dereference_raw_notrace(ftrace_exports_list);
>>> + while (export) {
>>> + trace_process_export(export, event);
>>> + export = rcu_dereference_raw_notrace(export->next);
>>> + }
>>> +
>>> + preempt_enable_notrace();
>>> +}
>>> +
>>> +static inline void
>>> +add_trace_export(struct trace_export **list, struct trace_export *export)
>>> +{
>>> + rcu_assign_pointer(export->next, *list);
>>> + /*
>>> + * We are entering export into the list but another
>>> + * CPU might be walking that list. We need to make sure
>>> + * the export->next pointer is valid before another CPU sees
>>> + * the export pointer included into the list.
>>> + */
>>> + rcu_assign_pointer(*list, export);
>>> +}
>>> +
>>> +static inline int
>>> +rm_trace_export(struct trace_export **list, struct trace_export *export)
>>> +{
>>> + struct trace_export **p;
>>> +
>>> + for (p = list; *p != NULL; p = &(*p)->next)
>>> + if (*p == export)
>>> + break;
>>> +
>>> + if (*p != export)
>>> + return -1;
>>> +
>>> + rcu_assign_pointer(*p, (*p)->next);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static inline void
>>> +add_ftrace_export(struct trace_export **list, struct trace_export *export)
>>> +{
>>> + if (*list == NULL)
>>> + ftrace_exports_enable();
>>> +
>>> + add_trace_export(list, export);
>>> +}
>>> +
>>> +static inline int
>>> +rm_ftrace_export(struct trace_export **list, struct trace_export *export)
>>> +{
>>> + int ret;
>>> +
>>> + ret = rm_trace_export(list, export);
>>> + if (*list == NULL)
>>> + ftrace_exports_disable();
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +int register_ftrace_export(struct trace_export *export)
>>> +{
>>> + if (WARN_ON_ONCE(!export->write))
>>> + return -1;
>>> +
>>> + mutex_lock(&ftrace_export_lock);
>>> +
>>> + add_ftrace_export(&ftrace_exports_list, export);
>>> +
>>> + mutex_unlock(&ftrace_export_lock);
>>> +
>>> + return 0;
>>> +}
>>> +EXPORT_SYMBOL_GPL(register_ftrace_export);
>>> +
>>> +int unregister_ftrace_export(struct trace_export *export)
>>> +{
>>> + int ret;
>>> +
>>> + mutex_lock(&ftrace_export_lock);
>>> +
>>> + ret = rm_ftrace_export(&ftrace_exports_list, export);
>>> +
>>> + mutex_unlock(&ftrace_export_lock);
>>> +
>>> + return ret;
>>> +}
>>> +EXPORT_SYMBOL_GPL(unregister_ftrace_export);
>>> +
>>> void
>>> trace_function(struct trace_array *tr,
>>> unsigned long ip, unsigned long parent_ip, unsigned long flags,
>>> @@ -2146,8 +2273,11 @@ trace_function(struct trace_array *tr,
>>> entry->ip = ip;
>>> entry->parent_ip = parent_ip;
>>>
>>> - if (!call_filter_check_discard(call, entry, buffer, event))
>>> + if (!call_filter_check_discard(call, entry, buffer, event)) {
>>> + if (static_branch_unlikely(&ftrace_exports_enabled))
>>> + ftrace_exports(event);
>>> __buffer_unlock_commit(buffer, event);
>>> + }
>>> }
>>>
>>> #ifdef CONFIG_STACKTRACE
>>
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