* [PATCH 2/2] ARM: dts: sun8i: reference-design-tablet: ldo_io1 is vcc-touchscreen
From: Maxime Ripard @ 2016-11-14 20:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161113192203.7101-2-hdegoede@redhat.com>
On Sun, Nov 13, 2016 at 08:22:03PM +0100, Hans de Goede wrote:
> On some Q8 and other tablets ldo_io1 is used as vcc-touchscreen,
> config at as such in sun8i-reference-design-tablet.dtsi.
>
> Note that it will only be enabled when it us actually referenced by
> a foo-supply property in the touchscreen node, so for tablets which
> do not use ldo_io1 as vcc-touchscreen, it will be disabled.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 801 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161114/4197396f/attachment.sig>
^ permalink raw reply
* [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Uwe Kleine-König @ 2016-11-14 20:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479126185.15557.5@smtp.gmail.com>
Hello Tomas,
On Mon, Nov 14, 2016 at 01:23:05PM +0100, tomas.hlavacek at nic.cz wrote:
> On Sat, Nov 5, 2016 at 9:38 PM, Uwe Kleine-K?nig <uwe@kleine-koenig.org>
> wrote:
> > This machine is an open hardware router by cz.nic driven by a
> > Marvell Armada 385.
> >
> > Signed-off-by: Uwe Kleine-K?nig <uwe@kleine-koenig.org>
> > ---
> >
> > Hello,
> >
> > the following components are working:
> >
> > - WAN port
> > - eMMC
>
> But I not not sure about DDR50 mode. At least with kernel 4.4, that we use
> in production, we had to limit to SDR50 to overcome I/O errors and
> communication instability, if I can remember it correctly. So it might need
> more testing with the current kernel.
I didn't test that extensively, but the eMMC serves my rootfs and I
didn't had any problems so far.
> > Still missing is support for the switch. Wireless fails to probe, didn't
> > debug this up to now. SFP is untested as is UART1.
>
> Actually SFP is connected to SGMII interface of eth1, which is routed
> through SERDES 5. The SGMII line is shared between the SFP and metallic PHY
> 88E1514. There is a autonomous high-speed switch connected to the SFPDET
> signal from SFP cage. It disconnects the metallic SFP and connects SGMII to
> SFP once the module is connected.
>
> The SFP is also connected to the I2C mux port 4 and to GPIO expander for
> reading/driving SFPDET, LOS, TXFLT, TXDIS signals:
>
> &i2c0 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c0_pins>;
> status = "okay";
> clock-frequency = <100000>;
>
> i2cmux at 70 {
> compatible = "nxp,pca9547";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x70>;
> status = "okay";
>
> ...
>
> i2c at 7 {
> /* SFP+ GPIO expander */
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <7>;
>
> sfpgpio: gpio at 71 {
> compatible = "nxp,pca9538";
> reg = <0x71>;
> interrupt-parent = <&gpio1>;
> interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
> gpio-controller;
> #gpio-cells = <2>;
> };
I have authored a nearly identical snippet, mine looks as follows:
+ i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+
+ pcawan: gpio at 71 {
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcawan_pins>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
The interrupt-controller part doesn't seem to work though, at least
+ interrupt-parent = <&pcawan>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
in the phy node gives an error.
> };
> };
> };
>
> We have our proprietary support hacked onto mvneta driver for disconnecting
> PHY on the fly. It is a bit nasty, so I suggest to ignore SFP in this DTS
> altogether and let's wait till "phylink based SFP module support" or
> something alike hits upstream, so we can base the SFP support on solid code;
> unless somebody has a better idea, of course.
>
> >
> >
> > diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts
> > b/arch/arm/boot/dts/armada-385-turris-omnia.dts
> > new file mode 100644
> > index 000000000000..d3cd8a4d713d
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
> > @@ -0,0 +1,246 @@
> ...
> > +
> > + /* USB part of the eSATA/USB 2.0 port */
>
> This comment is perhaps some error inherited from my development DTS. We do
> not have any eSATA, perhaps PCIe/USB 2.0 slot.
oh right. I changed it for v3.
> >
> > + usb at 58000 {
> > + status = "okay";
> > + };
> > +
> > +
> > +ð0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&ge0_rgmii_pins>;
> > + status = "okay";
> > + phy-mode = "rgmii-id";
> > +
> > + fixed-link {
> > + speed = <1000>;
> > + full-duplex;
> > + };
> > +};
> > +
> > +ð1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&ge1_rgmii_pins>;
> > + status = "okay";
> > + phy-mode = "rgmii-id";
> > +
> > + fixed-link {
> > + speed = <1000>;
> > + full-duplex;
> > + };
> > +};
> > +
>
> Actually eth0 and eth1 (both are RGMII) are connected to the 88E6176 switch.
> The problem is that from what I have read so far the switch can not operate
> in DSA mode with two CPU ports. We currently operate the switch in "normal
> mode" with the eth0 and eth1 set to fixed-link 1000/full and with
> proprietary driver (derived from OpenWRT switch drivers). I would say that
> these records for eth0 and eth1 are therefore redundant, because it does
> nothing without the switch support and it would most likely change once we
> have DSA driver (using only eth0).
Right. They do nothing currently. In my local tree I have a
specification for the switch which allows to read the phy registers of
the lan ports, but communication isn't possible yet. For this AFAIK I
need at least one of these. I mailed a few iterations with Andrew here,
but no success so far. Also dropping one cpu port from the definition
didn't help.
Best regards
Uwe
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 455 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161114/a783ea53/attachment.sig>
^ permalink raw reply
* [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Andrew Lunn @ 2016-11-14 20:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114201640.rr32iyjf5a53v33t@perseus.defre.kleine-koenig.org>
>
> + i2c at 7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> +
> + pcawan: gpio at 71 {
> + compatible = "nxp,pca9538";
> + reg = <0x71>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcawan_pins>;
> +
> + interrupt-parent = <&gpio1>;
> + interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
>
> The interrupt-controller part doesn't seem to work though, at least
>
> + interrupt-parent = <&pcawan>;
> + interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
>
> in the phy node gives an error.
Interrupts don't seem to work very well with the nxp,pca9538. Which
is probably why it is disabled by default.
Andrew
^ permalink raw reply
* [PATCH] ARM: sun8i: sina33: Enable USB gadget
From: Maxime Ripard @ 2016-11-14 20:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161104144439.4469-1-maxime.ripard@free-electrons.com>
On Fri, Nov 04, 2016 at 03:44:39PM +0100, Maxime Ripard wrote:
> The micro-USB on the SinA33 has a somewhat interesting design in the sense
> that it has a micro USB connector, but the VBUS is (supposed to be)
> controlled through an (unpopulated) jumper.
>
> Obviously, that doesn't work really well, and only the peripheral mode
> really works. Still enable it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Applied.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 801 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161114/9b9d417b/attachment-0001.sig>
^ permalink raw reply
* [linux-sunxi] [PATCH v5 4/7] ASoC: sunxi: Add sun8i I2S driver
From: Maxime Ripard @ 2016-11-14 21:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161108115129.f315ca5feefd22614859bbe3@free.fr>
On Tue, Nov 08, 2016 at 11:51:29AM +0100, Jean-Francois Moine wrote:
> On Mon, 7 Nov 2016 21:05:05 +0100
> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
>
> > Hi,
> >
> > On Sun, Nov 06, 2016 at 07:02:48PM +0100, Jean-Francois Moine wrote:
> > > On Sun, 23 Oct 2016 09:33:16 +0800
> > > Chen-Yu Tsai <wens@csie.org> wrote:
> > >
> > > > On Fri, Oct 21, 2016 at 4:36 PM, Jean-Francois Moine <moinejf@free.fr> wrote:
> > > > > This patch adds I2S support to sun8i SoCs as the A83T and H3.
> > > > >
> > > > > Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> > > > > ---
> > > > > Note: This driver is closed to the sun4i-i2s except that:
> > > > > - it handles the H3
> > > >
> > > > If it's close to sun4i-i2s, you should probably rework that one to support
> > > > the newer SoCs.
> > >
> > > I started to add the H3 into the sun4i-i2s, but I am blocked with
> > > regmap.
> > > Many H3 registers are common with the A10, but some of them have more
> > > or less fields, the fields may be at different offsets. And, finally,
> > > some registers are completely different.
> > > This would not raise any problem, except with regmap which is really
> > > painful.
> >
> > That's weird, because regmap's regmap_field should make that much
> > easier.
>
> #define field_relaxed(addr, mask, val) \
> writel_relaxed((readl_relaxed(addr) & mask) | val, addr)
I'm not sure what you mean here.
> > > As I may understood, regmap is used to simplify suspend/resume, but, is
> > > it useful to save the I2S register on suspend?
> > > Practically, I am streaming some tune on my device. I suspend it for
> > > any reason. The next morning, I resume it. Are you sure I want to
> > > continue to hear the end of the tune?
> > >
> > > I better think that streaming should be simply stopped on suspend.
> >
> > You're mistaken. The code in there is for *runtime* suspend, ie when
> > the device is no longer used, so that case shouldn't even happen at
> > all.
> >
> > (And real suspend isn't supported anyway)
>
> Is it time to remove this useless code?
Which useless code?
> > > Then, there is no need to save the playing registers, and, here I am,
> > > there is no need to use regmap.
> > >
> > > May I go this way?
> >
> > No, please don't. regmap is also providing very useful features, such
> > as access to all the registers through debugfs, or tracing. What
> > exactly feels painful to you?
>
> When the I/O registers are in memory (that's the case), you may access
> them (read and write) thru /dev/mem.
For all the registers if you want to dump all of them. It needs
scripting, it needs root access, and it needs some tool (either devmem
or a custom one) to dump the values. And this is if you have the right
kernel configuration options (devmem enabled, with the protection
against mapped devices disabled).
It just works with debugfs.
> Also, is a register access trace really needed in this driver?
Yes.
> The pain is to define the regmap_config (which registers can be
> read/write/volatile and which can be the values the u-boot let us in
> the registers at startup time), and the lot of code which is run instead
> of simple load/store machine instructions.
This is only needed if you want to use caching, and caching is
optional.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 801 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161114/5cda6589/attachment.sig>
^ permalink raw reply
* [PATCH v2 0/6] mm: fix the "counter.sh" failure for libhugetlbfs
From: Andrew Morton @ 2016-11-14 22:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479107259-2011-1-git-send-email-shijie.huang@arm.com>
On Mon, 14 Nov 2016 15:07:33 +0800 Huang Shijie <shijie.huang@arm.com> wrote:
> (1) Background
> For the arm64, the hugetlb page size can be 32M (PMD + Contiguous bit).
> In the 4K page environment, the max page order is 10 (max_order - 1),
> so 32M page is the gigantic page.
>
> The arm64 MMU supports a Contiguous bit which is a hint that the TTE
> is one of a set of contiguous entries which can be cached in a single
> TLB entry. Please refer to the arm64v8 mannul :
> DDI0487A_f_armv8_arm.pdf (in page D4-1811)
>
> (2) The bug
> After I tested the libhugetlbfs, I found the test case "counter.sh"
> will fail with the gigantic page (32M page in arm64 board).
>
> This patch set adds support for gigantic surplus hugetlb pages,
> allowing the counter.sh unit test to pass.
I'm not really seeing a description of the actual bug. I don't know
what counter.sh is, there is no copy of counter.sh included in the
changelogs and there is no description of the kernel error which
counter.sh demonstrates.
So can you pleaser send to me a copy of counter.sh as well as a
suitable description of the kernel error which counter.sh triggers?
^ permalink raw reply
* [PATCH] ARM: socfpga: fix spelling mistake in error message
From: Colin King @ 2016-11-14 23:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Colin Ian King <colin.king@canonical.com>
Trivial fix to spelling mistake "Mananger" to "Manager"
in error message
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
arch/arm/mach-socfpga/l2_cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
index 4267c95f..bb359d7 100644
--- a/arch/arm/mach-socfpga/l2_cache.c
+++ b/arch/arm/mach-socfpga/l2_cache.c
@@ -74,7 +74,7 @@ void socfpga_init_arria10_l2_ecc(void)
}
if (!sys_manager_base_addr) {
- pr_err("System Mananger not mapped for L2 ECC\n");
+ pr_err("System Manager not mapped for L2 ECC\n");
goto exit;
}
/* Clear any pending IRQs */
--
2.10.2
^ permalink raw reply related
* [PATCH fpga 5/9] fpga zynq: Remove priv->dev
From: Jason Gunthorpe @ 2016-11-14 23:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAAtXAHe60QjyitDxkEzc9+Zr99mj0SeWFUOW0SOexGnBvuqGjw@mail.gmail.com>
On Mon, Nov 14, 2016 at 09:20:38AM -0800, Moritz Fischer wrote:
> this one could be independent of the other patches, this is cleanup and
> could be merged before the rest (that's still in discussion) if you pull it out.
As I said in the cover letter, several of the patches are just fixes
and can be applied, but they are all linked by patch context so are
presented as a series.
Lets get as many reviewed as possible and then I can repost them in a
different order if necessary.
The first 5 are all straigtfoward and should be no problem to get
ackd. We've talked about the sanity check patch enough, lets just go
ahead with it now.
Jason
^ permalink raw reply
* [PATCH 0/2] ARM: davinci: cleanup and rework PM initializaion
From: Kevin Hilman @ 2016-11-14 23:04 UTC (permalink / raw)
To: linux-arm-kernel
This series removes the fake platform_device used to initialize PM on
legacy davinci platforms, and adds PM support for DT platforms.
Sekhar: the 2nd patch should probably be squashed into the first upon
approval, but was kept separated in order to make the functional
changes in the first patch more readable.
Tested with legacy boot on da850-evm, and DT boot on da850-lcdk. Used
RTC to wake from suspend-to-RAM: e.g. rtcwake -m mem -s 4 -d /dev/rtc0
Kevin Hilman (2):
ARM: davinci: PM: rework init, support DT platforms
ARM: davinci: PM: rework init: cleanup
arch/arm/mach-davinci/board-da850-evm.c | 17 +----
arch/arm/mach-davinci/board-mityomapl138.c | 16 +----
arch/arm/mach-davinci/common.c | 1 -
arch/arm/mach-davinci/da850.c | 38 ------------
arch/arm/mach-davinci/da8xx-dt.c | 1 +
arch/arm/mach-davinci/include/mach/da8xx.h | 1 -
arch/arm/mach-davinci/pm.c | 99 +++++++++++++++++-------------
7 files changed, 58 insertions(+), 115 deletions(-)
--
2.9.3
^ permalink raw reply
* [PATCH 1/2] ARM: davinci: PM: rework init, support DT platforms
From: Kevin Hilman @ 2016-11-14 23:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114230441.356-1-khilman@baylibre.com>
Remove fake platform device used for PM init. Move pdata values which
are common across all current platforms into pm.c.
Also add PM support for DT platforms (vi da8xx-dt.c)
Suggested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
---
arch/arm/mach-davinci/board-da850-evm.c | 17 +-------
arch/arm/mach-davinci/board-mityomapl138.c | 16 +-------
arch/arm/mach-davinci/common.c | 1 -
arch/arm/mach-davinci/da850.c | 38 ------------------
arch/arm/mach-davinci/da8xx-dt.c | 1 +
arch/arm/mach-davinci/include/mach/da8xx.h | 1 -
arch/arm/mach-davinci/pm.c | 64 ++++++++++++++++++------------
7 files changed, 41 insertions(+), 97 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 8e4539f69fdc..4e88723c23c7 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -196,18 +196,6 @@ static struct platform_device da850_evm_norflash_device = {
.resource = da850_evm_norflash_resource,
};
-static struct davinci_pm_config da850_pm_pdata = {
- .sleepcount = 128,
-};
-
-static struct platform_device da850_pm_device = {
- .name = "pm-davinci",
- .dev = {
- .platform_data = &da850_pm_pdata,
- },
- .id = -1,
-};
-
/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
* (128K blocks). It may be used instead of the (default) SPI flash
* to boot, using TI's tools to install the secondary boot loader
@@ -1453,10 +1441,7 @@ static __init void da850_evm_init(void)
if (ret)
pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
- ret = da850_register_pm(&da850_pm_device);
- if (ret)
- pr_warn("%s: suspend registration failed: %d\n", __func__, ret);
-
+ davinci_pm_init();
da850_vpif_init();
ret = spi_register_board_info(da850evm_spi_info,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index bc4e63fa9808..9e7388ba413c 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -498,18 +498,6 @@ static void __init mityomapl138_config_emac(void)
pr_warn("emac registration failed: %d\n", ret);
}
-static struct davinci_pm_config da850_pm_pdata = {
- .sleepcount = 128,
-};
-
-static struct platform_device da850_pm_device = {
- .name = "pm-davinci",
- .dev = {
- .platform_data = &da850_pm_pdata,
- },
- .id = -1,
-};
-
static void __init mityomapl138_init(void)
{
int ret;
@@ -555,9 +543,7 @@ static void __init mityomapl138_init(void)
if (ret)
pr_warn("cpuidle registration failed: %d\n", ret);
- ret = da850_register_pm(&da850_pm_device);
- if (ret)
- pr_warn("suspend registration failed: %d\n", ret);
+ davinci_pm_init();
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 049025f6d531..9f9fbfa6da0d 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -118,6 +118,5 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
void __init davinci_init_late(void)
{
davinci_cpufreq_init();
- davinci_pm_init();
davinci_clk_disable_unused();
}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index ed3d0e9f72ac..28771923199f 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1172,44 +1172,6 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
}
#endif
-int __init da850_register_pm(struct platform_device *pdev)
-{
- int ret;
- struct davinci_pm_config *pdata = pdev->dev.platform_data;
-
- ret = davinci_cfg_reg(DA850_RTC_ALARM);
- if (ret)
- return ret;
-
- pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
- pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
- pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
-
- pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
- if (!pdata->cpupll_reg_base)
- return -ENOMEM;
-
- pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
- if (!pdata->ddrpll_reg_base) {
- ret = -ENOMEM;
- goto no_ddrpll_mem;
- }
-
- pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
- if (!pdata->ddrpsc_reg_base) {
- ret = -ENOMEM;
- goto no_ddrpsc_mem;
- }
-
- return platform_device_register(pdev);
-
-no_ddrpsc_mem:
- iounmap(pdata->ddrpll_reg_base);
-no_ddrpll_mem:
- iounmap(pdata->cpupll_reg_base);
- return ret;
-}
-
/* VPIF resource, platform data */
static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index c9f7e9274aa8..aed44dcdfd30 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -46,6 +46,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
static void __init da850_init_machine(void)
{
of_platform_default_populate(NULL, da850_auxdata_lookup, NULL);
+ davinci_pm_init();
}
static const char *const da850_boards_compat[] __initconst = {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index f9f9713aacdd..3d7a13789661 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -101,7 +101,6 @@ int da8xx_register_gpio(void *pdata);
int da850_register_cpufreq(char *async_clk);
int da8xx_register_cpuidle(void);
void __iomem *da8xx_get_mem_ctlr(void);
-int da850_register_pm(struct platform_device *pdev);
int da850_register_sata(unsigned long refclkpn);
int da850_register_vpif(void);
int da850_register_vpif_display
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index 8929569b1f8a..fc6a5710b3fa 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -23,13 +23,18 @@
#include <mach/da8xx.h>
#include "sram.h"
#include <mach/pm.h>
+#include <mach/mux.h>
#include "clock.h"
+#include "psc.h"
+#define DA850_PLL1_BASE 0x01e1a000
#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
+#define DEEPSLEEP_SLEEPCOUNT 128
static void (*davinci_sram_suspend) (struct davinci_pm_config *);
-static struct davinci_pm_config *pdata;
+static struct davinci_pm_config pm_config;
+static struct davinci_pm_config *pdata = &pm_config;
static void davinci_sram_push(void *dest, void *src, unsigned int size)
{
@@ -117,17 +122,38 @@ static const struct platform_suspend_ops davinci_pm_ops = {
.valid = suspend_valid_only_mem,
};
-static int __init davinci_pm_probe(struct platform_device *pdev)
+int __init davinci_pm_init(void)
{
- pdata = pdev->dev.platform_data;
- if (!pdata) {
- dev_err(&pdev->dev, "cannot get platform data\n");
- return -ENOENT;
+ int ret;
+
+ ret = davinci_cfg_reg(DA850_RTC_ALARM);
+ if (ret)
+ return ret;
+
+ pdata->sleepcount = DEEPSLEEP_SLEEPCOUNT;
+ pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
+ pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
+ pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
+
+ pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
+ if (!pdata->cpupll_reg_base)
+ return -ENOMEM;
+
+ pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
+ if (!pdata->ddrpll_reg_base) {
+ ret = -ENOMEM;
+ goto no_ddrpll_mem;
+ }
+
+ pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
+ if (!pdata->ddrpsc_reg_base) {
+ ret = -ENOMEM;
+ goto no_ddrpsc_mem;
}
davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
if (!davinci_sram_suspend) {
- dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
+ pr_err("PM: cannot allocate SRAM memory\n");
return -ENOMEM;
}
@@ -136,23 +162,9 @@ static int __init davinci_pm_probe(struct platform_device *pdev)
suspend_set_ops(&davinci_pm_ops);
- return 0;
-}
-
-static int __exit davinci_pm_remove(struct platform_device *pdev)
-{
- sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
- return 0;
-}
-
-static struct platform_driver davinci_pm_driver = {
- .driver = {
- .name = "pm-davinci",
- },
- .remove = __exit_p(davinci_pm_remove),
-};
-
-int __init davinci_pm_init(void)
-{
- return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
+no_ddrpsc_mem:
+ iounmap(pdata->ddrpll_reg_base);
+no_ddrpll_mem:
+ iounmap(pdata->cpupll_reg_base);
+ return ret;
}
--
2.9.3
^ permalink raw reply related
* [PATCH 2/2] ARM: davinci: PM: rework init: cleanup
From: Kevin Hilman @ 2016-11-14 23:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114230441.356-1-khilman@baylibre.com>
A follow-on cleanup renaming 'pdata' since it is no longer
platform_data.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
---
arch/arm/mach-davinci/pm.c | 61 +++++++++++++++++++++++-----------------------
1 file changed, 30 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index fc6a5710b3fa..1f2ac36efe11 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -34,7 +34,6 @@
static void (*davinci_sram_suspend) (struct davinci_pm_config *);
static struct davinci_pm_config pm_config;
-static struct davinci_pm_config *pdata = &pm_config;
static void davinci_sram_push(void *dest, void *src, unsigned int size)
{
@@ -46,58 +45,58 @@ static void davinci_pm_suspend(void)
{
unsigned val;
- if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
+ if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
/* Switch CPU PLL to bypass mode */
- val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+ val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
- __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+ __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
udelay(PLL_BYPASS_TIME);
/* Powerdown CPU PLL */
- val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+ val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val |= PLLCTL_PLLPWRDN;
- __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+ __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
}
/* Configure sleep count in deep sleep register */
- val = __raw_readl(pdata->deepsleep_reg);
+ val = __raw_readl(pm_config.deepsleep_reg);
val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
- val |= pdata->sleepcount;
- __raw_writel(val, pdata->deepsleep_reg);
+ val |= pm_config.sleepcount;
+ __raw_writel(val, pm_config.deepsleep_reg);
/* System goes to sleep in this call */
- davinci_sram_suspend(pdata);
+ davinci_sram_suspend(&pm_config);
- if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
+ if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
/* put CPU PLL in reset */
- val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+ val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLRST;
- __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+ __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* put CPU PLL in power down */
- val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+ val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLPWRDN;
- __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+ __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* wait for CPU PLL reset */
udelay(PLL_RESET_TIME);
/* bring CPU PLL out of reset */
- val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+ val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val |= PLLCTL_PLLRST;
- __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+ __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* Wait for CPU PLL to lock */
udelay(PLL_LOCK_TIME);
/* Remove CPU PLL from bypass mode */
- val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+ val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLENSRC;
val |= PLLCTL_PLLEN;
- __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+ __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
}
}
@@ -130,23 +129,23 @@ int __init davinci_pm_init(void)
if (ret)
return ret;
- pdata->sleepcount = DEEPSLEEP_SLEEPCOUNT;
- pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
- pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
- pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
+ pm_config.sleepcount = DEEPSLEEP_SLEEPCOUNT;
+ pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
+ pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
+ pm_config.ddrpsc_num = DA8XX_LPSC1_EMIF3C;
- pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
- if (!pdata->cpupll_reg_base)
+ pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
+ if (!pm_config.cpupll_reg_base)
return -ENOMEM;
- pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
- if (!pdata->ddrpll_reg_base) {
+ pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
+ if (!pm_config.ddrpll_reg_base) {
ret = -ENOMEM;
goto no_ddrpll_mem;
}
- pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
- if (!pdata->ddrpsc_reg_base) {
+ pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
+ if (!pm_config.ddrpsc_reg_base) {
ret = -ENOMEM;
goto no_ddrpsc_mem;
}
@@ -163,8 +162,8 @@ int __init davinci_pm_init(void)
suspend_set_ops(&davinci_pm_ops);
no_ddrpsc_mem:
- iounmap(pdata->ddrpll_reg_base);
+ iounmap(pm_config.ddrpll_reg_base);
no_ddrpll_mem:
- iounmap(pdata->cpupll_reg_base);
+ iounmap(pm_config.cpupll_reg_base);
return ret;
}
--
2.9.3
^ permalink raw reply related
* [PATCH 1/4] fpga mgr: Introduce FPGA capabilities
From: atull @ 2016-11-14 23:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAAtXAHeX08ZxGceXvqkdNwsVHdOpczxx5fvFapLy74n1_4R-CA@mail.gmail.com>
On Mon, 14 Nov 2016, Moritz Fischer wrote:
Hi Moritz,
> Hi Alan,
>
> On Mon, Nov 14, 2016 at 6:06 AM, atull <atull@opensource.altera.com> wrote:
> > On Mon, 7 Nov 2016, Moritz Fischer wrote:
> >
> >> Add FPGA capabilities as a way to express the capabilities
> >> of a given FPGA manager.
> >>
> >> Removes code duplication by comparing the low-level driver's
> >> capabilities at the framework level rather than having each driver
> >> check for supported operations in the write_init() callback.
> >>
> >> This allows for extending with additional capabilities, similar
> >> to the the dmaengine framework's implementation.
> >>
> >> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
> >> Cc: Alan Tull <atull@opensource.altera.com>
> >> Cc: Michal Simek <michal.simek@xilinx.com>
> >> Cc: S?ren Brinkmann <soren.brinkmann@xilinx.com>
> >> Cc: linux-kernel at vger.kernel.org
> >> Cc: linux-arm-kernel at lists.infradead.org
> >> ---
> >>
> >> Changes from RFC:
> >> * in the RFC the caps weren't actually stored into the struct fpga_mgr
> >>
> >> Note:
> >>
> >> If people disagree on the typedef being a 'false positive' I can fix
> >> that in a future rev of the patchset.
> >>
> >> Thanks,
> >>
> >> Moritz
> >>
> >> ---
> >> drivers/fpga/fpga-mgr.c | 15 ++++++++++++++
> >> drivers/fpga/socfpga.c | 10 +++++-----
> >> drivers/fpga/zynq-fpga.c | 7 ++++++-
> >> include/linux/fpga/fpga-mgr.h | 46 ++++++++++++++++++++++++++++++++++++++++++-
> >> 4 files changed, 71 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
> >> index 953dc91..ed57c17 100644
> >> --- a/drivers/fpga/fpga-mgr.c
> >> +++ b/drivers/fpga/fpga-mgr.c
> >> @@ -49,6 +49,18 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf,
> >> struct device *dev = &mgr->dev;
> >> int ret;
> >>
> >> + if (flags & FPGA_MGR_PARTIAL_RECONFIG &&
> >> + !fpga_mgr_has_cap(FPGA_MGR_CAP_PARTIAL_RECONF, mgr->caps)) {
> >> + dev_err(dev, "Partial reconfiguration not supported\n");
> >> + return -ENOTSUPP;
> >> + }
> >> +
> >> + if (flags & FPGA_MGR_FULL_RECONFIG &&
> >> + !fpga_mgr_has_cap(FPGA_MGR_CAP_FULL_RECONF, mgr->caps)) {
> >> + dev_err(dev, "Full reconfiguration not supported\n");
> >> + return -ENOTSUPP;
> >> + }
> >> +
> >
> > Could you move the checks to their own function like
> > 'fpga_mgr_check_caps()' or something? I really like it if we can keep
> > the functions short, like a screen or so where it's practicle to do
> > so and I could see the number of caps growing here.
>
> Absolutely. Great suggestion.
>
> > The only counter argument I could think of is if a cap affects the sequence
> > in this function. Hmmm...
>
> Oh you mean the cap being there affecting the sequence in *this* function?
> I'd suggest we address that when we run into a cap that requires this.
Yes, I agree.
Alan
>
> Cheers,
>
> Moritz
>
^ permalink raw reply
* [RFC v2 3/8] iommu/dma: Allow MSI-only cookies
From: Auger Eric @ 2016-11-14 23:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5f93ebfd-edf4-0b5a-b54a-b96937a588b8@arm.com>
Hi Robin,
On 14/11/2016 13:36, Robin Murphy wrote:
> On 04/11/16 11:24, Eric Auger wrote:
>> From: Robin Murphy <robin.murphy@arm.com>
>>
>> IOMMU domain users such as VFIO face a similar problem to DMA API ops
>> with regard to mapping MSI messages in systems where the MSI write is
>> subject to IOMMU translation. With the relevant infrastructure now in
>> place for managed DMA domains, it's actually really simple for other
>> users to piggyback off that and reap the benefits without giving up
>> their own IOVA management, and without having to reinvent their own
>> wheel in the MSI layer.
>>
>> Allow such users to opt into automatic MSI remapping by dedicating a
>> region of their IOVA space to a managed cookie.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> OK, following the discussion elsewhere I've had a go at the less stupid,
> but more involved, version. Thoughts?
Conceptually I don't have any major objection with the minimalist
allocation scheme all the more so it follows Joerg's guidance. Maybe the
only thing is we do not check we don't overshoot the reserved msi-region.
Besides there are 2 issues reported below.
>
> Robin.
>
> ----->8-----
> From: Robin Murphy <robin.murphy@arm.com>
> Subject: [RFC PATCH] iommu/dma: Allow MSI-only cookies
>
> IOMMU domain users such as VFIO face a similar problem to DMA API ops
> with regard to mapping MSI messages in systems where the MSI write is
> subject to IOMMU translation. With the relevant infrastructure now in
> place for managed DMA domains, it's actually really simple for other
> users to piggyback off that and reap the benefits without giving up
> their own IOVA management, and without having to reinvent their own
> wheel in the MSI layer.
>
> Allow such users to opt into automatic MSI remapping by dedicating a
> region of their IOVA space to a managed cookie, and extend the mapping
> routine to implement a trivial linear allocator in such cases, to avoid
> the needless overhead of a full-blown IOVA domain.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> drivers/iommu/dma-iommu.c | 118 ++++++++++++++++++++++++++++++++++++----------
> include/linux/dma-iommu.h | 6 +++
> 2 files changed, 100 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
> index c5ab8667e6f2..33d66a8273c6 100644
> --- a/drivers/iommu/dma-iommu.c
> +++ b/drivers/iommu/dma-iommu.c
> @@ -37,10 +37,19 @@ struct iommu_dma_msi_page {
> phys_addr_t phys;
> };
>
> +enum iommu_dma_cookie_type {
> + IOMMU_DMA_IOVA_COOKIE,
> + IOMMU_DMA_MSI_COOKIE,
> +};
> +
> struct iommu_dma_cookie {
> - struct iova_domain iovad;
> - struct list_head msi_page_list;
> - spinlock_t msi_lock;
> + union {
> + struct iova_domain iovad;
> + dma_addr_t msi_iova;
> + };
> + struct list_head msi_page_list;
> + spinlock_t msi_lock;
> + enum iommu_dma_cookie_type type;
> };
>
> static inline struct iova_domain *cookie_iovad(struct iommu_domain *domain)
> @@ -53,6 +62,19 @@ int iommu_dma_init(void)
> return iova_cache_get();
> }
>
> +static struct iommu_dma_cookie *__cookie_alloc(enum iommu_dma_cookie_type type)
> +{
> + struct iommu_dma_cookie *cookie;
> +
> + cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
> + if (cookie) {
> + spin_lock_init(&cookie->msi_lock);
> + INIT_LIST_HEAD(&cookie->msi_page_list);
> + cookie->type = type;
> + }
> + return cookie;
> +}
> +
> /**
> * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
> * @domain: IOMMU domain to prepare for DMA-API usage
> @@ -62,25 +84,53 @@ int iommu_dma_init(void)
> */
> int iommu_get_dma_cookie(struct iommu_domain *domain)
> {
> - struct iommu_dma_cookie *cookie;
> -
> if (domain->iova_cookie)
> return -EEXIST;
>
> - cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
> - if (!cookie)
> + domain->iova_cookie = __cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
> + if (!domain->iova_cookie)
> return -ENOMEM;
>
> - spin_lock_init(&cookie->msi_lock);
> - INIT_LIST_HEAD(&cookie->msi_page_list);
> - domain->iova_cookie = cookie;
> return 0;
> }
> EXPORT_SYMBOL(iommu_get_dma_cookie);
>
> /**
> + * iommu_get_msi_cookie - Acquire just MSI remapping resources
> + * @domain: IOMMU domain to prepare
> + * @base: Start address of IOVA region for MSI mappings
> + *
> + * Users who manage their own IOVA allocation and do not want DMA API support,
> + * but would still like to take advantage of automatic MSI remapping, can use
> + * this to initialise their own domain appropriately. Users should reserve a
> + * contiguous IOVA region, starting at @base, large enough to accommodate the
> + * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
> + * used by the devices attached to @domain.
> + */
> +int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
> +{
> + struct iommu_dma_cookie *cookie;
> +
> + if (domain->type != IOMMU_DOMAIN_UNMANAGED)
> + return -EINVAL;
> +
> + if (domain->iova_cookie)
> + return -EEXIST;
> +
> + cookie = __cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
must be IOMMU_DMA_MSI_COOKIE else it has bad consequences.
> + if (!cookie)
> + return -ENOMEM;
> +
> + cookie->msi_iova = base;
> + domain->iova_cookie = cookie;
> + return 0;
> +}
> +EXPORT_SYMBOL(iommu_get_msi_cookie);
> +
> +/**
> * iommu_put_dma_cookie - Release a domain's DMA mapping resources
> - * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
> + * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
> + * iommu_get_msi_cookie()
> *
> * IOMMU drivers should normally call this from their domain_free callback.
> */
> @@ -92,7 +142,7 @@ void iommu_put_dma_cookie(struct iommu_domain *domain)
> if (!cookie)
> return;
>
> - if (cookie->iovad.granule)
> + if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
> put_iova_domain(&cookie->iovad);
>
> list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
> @@ -137,11 +187,12 @@ static void iova_reserve_pci_windows(struct pci_dev *dev,
> int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
> u64 size, struct device *dev)
> {
> - struct iova_domain *iovad = cookie_iovad(domain);
> + struct iommu_dma_cookie *cookie = domain->iova_cookie;
> + struct iova_domain *iovad = &cookie->iovad;
> unsigned long order, base_pfn, end_pfn;
>
> - if (!iovad)
> - return -ENODEV;
> + if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
> + return -EINVAL;
>
> /* Use the smallest supported page size for IOVA granularity */
> order = __ffs(domain->pgsize_bitmap);
> @@ -644,11 +695,21 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
> {
> struct iommu_dma_cookie *cookie = domain->iova_cookie;
> struct iommu_dma_msi_page *msi_page;
> - struct iova_domain *iovad = &cookie->iovad;
> + struct iova_domain *iovad;
> struct iova *iova;
> int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
> + size_t size;
> +
> + if (cookie->type == IOMMU_DMA_IOVA_COOKIE) {
> + iovad = &cookie->iovad;
> + size = iovad->granule;
> + } else {
> + iovad = NULL;
> + size = PAGE_SIZE;
> + }
> +
> + msi_addr &= ~(phys_addr_t)(size - 1);
>
> - msi_addr &= ~(phys_addr_t)iova_mask(iovad);
> list_for_each_entry(msi_page, &cookie->msi_page_list, list)
> if (msi_page->phys == msi_addr)
> return msi_page;
> @@ -657,13 +718,18 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
> if (!msi_page)
> return NULL;
>
> - iova = __alloc_iova(domain, iovad->granule, dma_get_mask(dev));
> - if (!iova)
> - goto out_free_page;
> -
> msi_page->phys = msi_addr;
> - msi_page->iova = iova_dma_addr(iovad, iova);
> - if (iommu_map(domain, msi_page->iova, msi_addr, iovad->granule, prot))
> + if (iovad) {
> + iova = __alloc_iova(domain, size, dma_get_mask(dev));
> + if (!iova)
> + goto out_free_page;
> + msi_page->iova = iova_dma_addr(iovad, iova);
> + } else {
> + msi_page->iova = cookie->msi_iova;
> + cookie->msi_iova += size;
> + }
> +
> + if (iommu_map(domain, msi_page->iova, msi_addr, size, prot))
> goto out_free_iova;
>
> INIT_LIST_HEAD(&msi_page->list);
> @@ -671,7 +737,10 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
> return msi_page;
>
> out_free_iova:
> - __free_iova(iovad, iova);
> + if (iovad)
> + __free_iova(iovad, iova);
> + else
> + cookie->msi_iova -= size;
> out_free_page:
> kfree(msi_page);
> return NULL;
> @@ -716,3 +785,4 @@ void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg)
> msg->address_lo += lower_32_bits(msi_page->iova);
> }
> }
in iommu_dma_map_msi_msg there is another issue at:
msg->address_lo &= iova_mask(&cookie->iovad);
iovad might not exist
Thanks
Eric
> +
> diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h
> index 32c589062bd9..d69932474576 100644
> --- a/include/linux/dma-iommu.h
> +++ b/include/linux/dma-iommu.h
> @@ -27,6 +27,7 @@ int iommu_dma_init(void);
>
> /* Domain management interface for IOMMU drivers */
> int iommu_get_dma_cookie(struct iommu_domain *domain);
> +int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base);
> void iommu_put_dma_cookie(struct iommu_domain *domain);
>
> /* Setup call for arch DMA mapping code */
> @@ -82,6 +83,11 @@ static inline int iommu_get_dma_cookie(struct iommu_domain *domain)
> return -ENODEV;
> }
>
> +static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
> +{
> + return -ENODEV;
> +}
> +
> static inline void iommu_put_dma_cookie(struct iommu_domain *domain)
> {
> }
>
^ permalink raw reply
* [PATCH 1/3] Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boards
From: Rob Herring @ 2016-11-14 23:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478714651-12679-1-git-send-email-harninder.rai@nxp.com>
On Wed, Nov 09, 2016 at 11:34:11PM +0530, Harninder Rai wrote:
> Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH] ARM: socfpga: fix spelling mistake in error message
From: Dinh Nguyen @ 2016-11-14 23:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114230400.5352-1-colin.king@canonical.com>
On Mon, Nov 14, 2016 at 5:04 PM, Colin King <colin.king@canonical.com> wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> Trivial fix to spelling mistake "Mananger" to "Manager"
> in error message
>
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> ---
> arch/arm/mach-socfpga/l2_cache.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied!
Thanks,
DInh
^ permalink raw reply
* [PATCH 2/3] Documentation: DT: add LS1012A compatible for SCFG and DCFG
From: Rob Herring @ 2016-11-15 0:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478714679-12724-1-git-send-email-harninder.rai@nxp.com>
On Wed, Nov 09, 2016 at 11:34:39PM +0530, Harninder Rai wrote:
> Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH 3/3] dt-bindings: clockgen: Add compatible string for LS1012A
From: Rob Herring @ 2016-11-15 0:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478715053-12790-1-git-send-email-harninder.rai@nxp.com>
On Wed, Nov 09, 2016 at 11:40:53PM +0530, Harninder Rai wrote:
> Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v2 01/30] usb: dwc2: Deprecate g-use-dma binding
From: Rob Herring @ 2016-11-15 0:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <966d342a5a7fee9ac3ef8140b60c228c4a87c7d3.1478748145.git.johnyoun@synopsys.com>
On Wed, Nov 09, 2016 at 07:27:40PM -0800, John Youn wrote:
> This is not needed as the gadget now fully supports DMA and it can
> autodetect it. This was initially added because gadget DMA mode was only
> partially implemented so could not be automatically enabled.
>
> Signed-off-by: John Youn <johnyoun@synopsys.com>
> ---
> Documentation/devicetree/bindings/usb/dwc2.txt | 4 +++-
> arch/arm/boot/dts/rk3036.dtsi | 1 -
> arch/arm/boot/dts/rk3288.dtsi | 1 -
> arch/arm/boot/dts/rk3xxx.dtsi | 1 -
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 -
> arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1 -
> drivers/usb/dwc2/core.h | 4 +---
> drivers/usb/dwc2/params.c | 17 ++++++++++++++---
> drivers/usb/dwc2/pci.c | 1 -
> 9 files changed, 18 insertions(+), 13 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH] ARM: dts: imx6q: replace gpio-key,wakeup with wakeup-source for Utilite Pro
From: Shawn Guo @ 2016-11-15 0:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479138250-17780-3-git-send-email-sudeep.holla@arm.com>
On Mon, Nov 14, 2016 at 03:44:09PM +0000, Sudeep Holla wrote:
> Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
> check for/support the legacy "gpio-key,wakeup" boolean property to
> enable gpio buttons as wakeup source, "wakeup-source" is the new
> standard binding.
>
> This patch replaces the legacy "gpio-key,wakeup" with the unified
> "wakeup-source" property in order to avoid any further copy-paste
> duplication.
>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Applied, thanks.
^ permalink raw reply
* [GIT PULL] omap fixes for v4.9-rc cycle
From: Tony Lindgren @ 2016-11-15 0:33 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.9/fixes-for-rc-cycle
for you to fetch changes up to 1bc2f5fac34535aeb3878ce32a762a221be7a851:
ARM: dts: omap5: board-common: fix wrong SMPS6 (VDD-DDR3) voltage (2016-11-14 13:03:21 -0800)
----------------------------------------------------------------
Fixes for omaps for v4.9-rc cycle. Except for the omap3 fix for the SoC
features printed, all these are quite trivial and tiny. The omap5 jack
detection and gpadc patches are not strictly fixes, but I wanted to get
binding document typo fixed before it pops up on other boards. The
gpadc one liner was in the same series and I applied and pushed it out
already before noticing it could have waited. The list of changes is:
- Fix omap3 SoC features printed
- Make sure OMAP_INTERCONNECT is selected for am43xx only configurations
- Add missing memory node for torpedo
- Initialize uart4_mask properly to avoid writing garbage to PRM registers
- Fix NULL pointer dereference for omap4 volt_data
- Add alias for omap5 gpadc needed by iio drivers
- Enable omap5 jack headset jack detection and fix it's binding typo
- Add missing memory node for logicpd-som-lv
- Fix wrong SMPS6 voltage for VDD-DDR3 for omap5
----------------------------------------------------------------
Adam Ford (2):
ARM: dts: omap3: Fix memory node in Torpedo board
ARM: omap3: Add missing memory node in SOM-LV
Colin Ian King (1):
ARM: OMAP2+: PRM: initialize en_uart4_mask and grpsel_uart4_mask
Dave Gerlach (1):
ARM: AM43XX: Select OMAP_INTERCONNECT in Kconfig
H. Nikolaus Schaller (4):
dts: omap5: board-common: add phandle to reference Palmas gpadc
dts: omap5: board-common: enable twl6040 headset jack detection
ASoC: omap-abe-twl6040: fix typo in bindings documentation
ARM: dts: omap5: board-common: fix wrong SMPS6 (VDD-DDR3) voltage
Nicolae Rosia (1):
ARM: OMAP2+: avoid NULL pointer dereference
Tony Lindgren (1):
ARM: OMAP3: Fix formatting of features printed
.../devicetree/bindings/sound/omap-abe-twl6040.txt | 2 +-
arch/arm/boot/dts/logicpd-som-lv.dtsi | 5 +++++
arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 4 ++--
arch/arm/boot/dts/omap5-board-common.dtsi | 7 ++++---
arch/arm/mach-omap2/Kconfig | 1 +
arch/arm/mach-omap2/id.c | 16 +++++++++++-----
arch/arm/mach-omap2/prm3xxx.c | 3 +++
arch/arm/mach-omap2/voltage.c | 6 ++++++
8 files changed, 33 insertions(+), 11 deletions(-)
^ permalink raw reply
* [GIT PULL] add #pinctrl-cells for v4.10
From: Tony Lindgren @ 2016-11-15 0:34 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.10/pinctrl-cells-signed
for you to fetch changes up to be76fd3197df608e1b010bf5ab90377205f54344:
ARM: dts: Add #pinctrl-cells for pinctrl-single instances (2016-11-07 08:27:49 -0700)
----------------------------------------------------------------
Add #pinctrl-cells for pinctrl-single using dts files. This allows
us to use generic parser later on. Note that the driver supports
handling the legacy binding also with no #pinctrl-cells so these
changes can be queued separately from the driver changes.
----------------------------------------------------------------
Tony Lindgren (1):
ARM: dts: Add #pinctrl-cells for pinctrl-single instances
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt | 3 +++
arch/arm/boot/dts/am33xx.dtsi | 2 ++
arch/arm/boot/dts/am3517.dtsi | 1 +
arch/arm/boot/dts/am4372.dtsi | 1 +
arch/arm/boot/dts/da850.dtsi | 1 +
arch/arm/boot/dts/dm814x.dtsi | 1 +
arch/arm/boot/dts/dm816x.dtsi | 2 ++
arch/arm/boot/dts/dra7.dtsi | 1 +
arch/arm/boot/dts/hi3620.dtsi | 2 ++
arch/arm/boot/dts/keystone-k2g.dtsi | 1 +
arch/arm/boot/dts/keystone-k2l.dtsi | 1 +
arch/arm/boot/dts/omap2420.dtsi | 2 ++
arch/arm/boot/dts/omap2430.dtsi | 2 ++
arch/arm/boot/dts/omap3.dtsi | 2 ++
arch/arm/boot/dts/omap34xx.dtsi | 1 +
arch/arm/boot/dts/omap36xx.dtsi | 1 +
arch/arm/boot/dts/omap4.dtsi | 2 ++
arch/arm/boot/dts/omap5.dtsi | 2 ++
arch/arm/boot/dts/pxa3xx.dtsi | 1 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 3 +++
20 files changed, 32 insertions(+)
^ permalink raw reply
* [PATCH] ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED
From: Eric Anholt @ 2016-11-15 0:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <741880731.428971.a2c5fd60-1b30-481e-b728-fc62c8d1c81a.open-xchange@email.1und1.de>
Stefan Wahren <stefan.wahren@i2se.com> writes:
> Hi Eric,
>
> [add Gerd to CC]
>
>> Eric Anholt <eric@anholt.net> hat am 11. November 2016 um 18:38 geschrieben:
>>
>>
>> From: Andrea Merello <andrea.merello@gmail.com>
>>
>> We are incorrectly defining the pwr LED, attaching it to a gpio line
>> that is wired to the Wi-Fi SDIO module (which fails due to this).
>
> i agree with the intention of this patch, but is the upstream kernel really
> affected? I can't see any compatible for the Wifi interface.
The wifi isn't in the DT yet because the driver isn't merged. Some
progress was made on that a while ago, but people asked for more
cleanups so it's still living out of tree.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 800 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161114/aeaf51d8/attachment.sig>
^ permalink raw reply
* [PATCH v3 1/3] ARM: imx6ull: add imx6ull support
From: Shawn Guo @ 2016-11-15 0:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479107062-15365-2-git-send-email-peter.chen@nxp.com>
On Mon, Nov 14, 2016 at 03:04:20PM +0800, Peter Chen wrote:
> diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
> new file mode 100644
> index 0000000..580b5c3
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __DTS_IMX6ULL_PINFUNC_H
> +#define __DTS_IMX6ULL_PINFUNC_H
> +
> +#include "imx6ul-pinfunc.h"
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
> +#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
> +#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
> +#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0
> +#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0
> +#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0
> +#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0
> +#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
> +#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
Not sure why the indentation goes bad from here. I fixed it up and
applied all 3 patches.
Shawn
> +#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
> +#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
> +
> +#endif /* __DTS_IMX6ULL_PINFUNC_H */
^ permalink raw reply
* [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
From: Shawn Guo @ 2016-11-15 1:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114071308.GL3310@dragon>
On Mon, Nov 14, 2016 at 03:13:10PM +0800, Shawn Guo wrote:
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> > index 6602718..39db645 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -1,3 +1,6 @@
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
>
> It seems that the patch is not generated against mainline kernel. We do
> not have fsl-ls1046a-qds.dtb target in mainline kernel.
Sorry, forgot that we just added it in this development cycle.
Shawn
^ permalink raw reply
* [PATCH v2] [media] mtk-mdp: allocate video_device dynamically
From: Minghsiu Tsai @ 2016-11-15 1:34 UTC (permalink / raw)
To: linux-arm-kernel
It can fix known problems with embedded video_device structs.
Signed-off-by: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
---
Changes in v2:
. Call video_device_release() instead of video_unregister_device()
in mtk_mdp_register_m2m_device()
---
drivers/media/platform/mtk-mdp/mtk_mdp_core.h | 2 +-
drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c | 33 ++++++++++++++++-----------
2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp/mtk_mdp_core.h b/drivers/media/platform/mtk-mdp/mtk_mdp_core.h
index 848569d..ad1cff3 100644
--- a/drivers/media/platform/mtk-mdp/mtk_mdp_core.h
+++ b/drivers/media/platform/mtk-mdp/mtk_mdp_core.h
@@ -167,7 +167,7 @@ struct mtk_mdp_dev {
struct mtk_mdp_comp *comp[MTK_MDP_COMP_ID_MAX];
struct v4l2_m2m_dev *m2m_dev;
struct list_head ctx_list;
- struct video_device vdev;
+ struct video_device *vdev;
struct v4l2_device v4l2_dev;
struct workqueue_struct *job_wq;
struct platform_device *vpu_dev;
diff --git a/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c b/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c
index 9a747e7..13afe48 100644
--- a/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c
+++ b/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c
@@ -1236,16 +1236,22 @@ int mtk_mdp_register_m2m_device(struct mtk_mdp_dev *mdp)
int ret;
mdp->variant = &mtk_mdp_default_variant;
- mdp->vdev.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
- mdp->vdev.fops = &mtk_mdp_m2m_fops;
- mdp->vdev.ioctl_ops = &mtk_mdp_m2m_ioctl_ops;
- mdp->vdev.release = video_device_release_empty;
- mdp->vdev.lock = &mdp->lock;
- mdp->vdev.vfl_dir = VFL_DIR_M2M;
- mdp->vdev.v4l2_dev = &mdp->v4l2_dev;
- snprintf(mdp->vdev.name, sizeof(mdp->vdev.name), "%s:m2m",
+ mdp->vdev = video_device_alloc();
+ if (!mdp->vdev) {
+ dev_err(dev, "failed to allocate video device\n");
+ ret = -ENOMEM;
+ goto err_video_alloc;
+ }
+ mdp->vdev->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
+ mdp->vdev->fops = &mtk_mdp_m2m_fops;
+ mdp->vdev->ioctl_ops = &mtk_mdp_m2m_ioctl_ops;
+ mdp->vdev->release = video_device_release;
+ mdp->vdev->lock = &mdp->lock;
+ mdp->vdev->vfl_dir = VFL_DIR_M2M;
+ mdp->vdev->v4l2_dev = &mdp->v4l2_dev;
+ snprintf(mdp->vdev->name, sizeof(mdp->vdev->name), "%s:m2m",
MTK_MDP_MODULE_NAME);
- video_set_drvdata(&mdp->vdev, mdp);
+ video_set_drvdata(mdp->vdev, mdp);
mdp->m2m_dev = v4l2_m2m_init(&mtk_mdp_m2m_ops);
if (IS_ERR(mdp->m2m_dev)) {
@@ -1254,26 +1260,27 @@ int mtk_mdp_register_m2m_device(struct mtk_mdp_dev *mdp)
goto err_m2m_init;
}
- ret = video_register_device(&mdp->vdev, VFL_TYPE_GRABBER, 2);
+ ret = video_register_device(mdp->vdev, VFL_TYPE_GRABBER, 2);
if (ret) {
dev_err(dev, "failed to register video device\n");
goto err_vdev_register;
}
v4l2_info(&mdp->v4l2_dev, "driver registered as /dev/video%d",
- mdp->vdev.num);
+ mdp->vdev->num);
return 0;
err_vdev_register:
v4l2_m2m_release(mdp->m2m_dev);
err_m2m_init:
- video_device_release(&mdp->vdev);
+ video_device_release(mdp->vdev);
+err_video_alloc:
return ret;
}
void mtk_mdp_unregister_m2m_device(struct mtk_mdp_dev *mdp)
{
- video_device_release(&mdp->vdev);
+ video_unregister_device(mdp->vdev);
v4l2_m2m_release(mdp->m2m_dev);
}
--
1.9.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox