* [PATCH v2] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168
From: Geetha sowjanya @ 2016-11-15 7:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
This patch implements Cavium ThunderX erratum 28168.
PCI requires stores complete in order. Due to erratum #28168
PCI-inbound MSI-X store to the interrupt controller are delivered
to the interrupt controller before older PCI-inbound memory stores
are committed.
Doing a sync on SMMU will make sure all prior data transfers are
completed before invoking ISR.
Signed-off-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>
---
arch/arm64/Kconfig | 11 +++++++++++
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/include/asm/cpufeature.h | 3 ++-
arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++
drivers/iommu/arm-smmu.c | 24 ++++++++++++++++++++++++
drivers/irqchip/irq-gic-common.h | 1 +
drivers/irqchip/irq-gic-v3.c | 19 +++++++++++++++++++
7 files changed, 74 insertions(+), 1 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 30398db..751972c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -474,6 +474,17 @@ config CAVIUM_ERRATUM_27456
If unsure, say Y.
+config CAVIUM_ERRATUM_28168
+ bool "Cavium erratum 28168: Make sure DMA data transfer is done before MSIX"
+ depends on ARCH_THUNDER && ARM64
+ default y
+ help
+ Due to erratum #28168 PCI-inbound MSI-X store to the interrupt
+ controller are delivered to the interrupt controller before older
+ PCI-inbound memory stores are committed. Doing a sync on SMMU
+ will make sure all prior data transfers are done before invoking ISR.
+
+ If unsure, say Y.
endmenu
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index cfbdf02..2ac4ac6 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -185,6 +185,7 @@ config ARCH_SPRD
config ARCH_THUNDER
bool "Cavium Inc. Thunder SoC Family"
+ select IRQ_PREFLOW_FASTEOI
help
This enables support for Cavium's Thunder Family of SoCs.
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 758d74f..821fc3c 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -40,8 +40,9 @@
#define ARM64_HAS_32BIT_EL0 13
#define ARM64_HYP_OFFSET_LOW 14
#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
+#define ARM64_WORKAROUND_CAVIUM_28168 16
-#define ARM64_NCAPS 16
+#define ARM64_NCAPS 17
#ifndef __ASSEMBLY__
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 0150394..0841a12 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -122,6 +122,22 @@ static void cpu_enable_trap_ctr_access(void *__unused)
MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
},
#endif
+#ifdef CONFIG_CAVIUM_ERRATUM_28168
+ {
+ /* Cavium ThunderX, T88 pass 1.x - 2.1 */
+ .desc = "Cavium erratum 28168",
+ .capability = ARM64_WORKAROUND_CAVIUM_28168,
+ MIDR_RANGE(MIDR_THUNDERX, 0x00,
+ (1 << MIDR_VARIANT_SHIFT) | 1),
+ },
+ {
+ /* Cavium ThunderX, T81 pass 1.0 */
+ .desc = "Cavium erratum 28168",
+ .capability = ARM64_WORKAROUND_CAVIUM_28168,
+ MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
+ },
+#endif
+
{
.desc = "Mismatched cache line size",
.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index c841eb7..1b4555c 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -570,6 +570,30 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
}
}
+/*
+ * Cavium ThunderX erratum 28168
+ *
+ * Due to erratum #28168 PCI-inbound MSI-X store to the interrupt
+ * controller are delivered to the interrupt controller before older
+ * PCI-inbound memory stores are committed. Doing a sync on SMMU
+ * will make sure all prior data transfers are completed before
+ * invoking ISR.
+ *
+ */
+void cavium_arm_smmu_tlb_sync(struct device *dev)
+{
+ struct iommu_fwspec *fwspec = dev->iommu_fwspec;
+ struct arm_smmu_device *smmu;
+
+ smmu = fwspec_smmu(fwspec);
+ if (!smmu)
+ return;
+ __arm_smmu_tlb_sync(smmu);
+
+}
+EXPORT_SYMBOL(cavium_arm_smmu_tlb_sync);
+
+
static void arm_smmu_tlb_sync(void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h
index 205e5fd..4e88f55 100644
--- a/drivers/irqchip/irq-gic-common.h
+++ b/drivers/irqchip/irq-gic-common.h
@@ -38,4 +38,5 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
void gic_set_kvm_info(const struct gic_kvm_info *info);
+void cavium_arm_smmu_tlb_sync(struct device *dev);
#endif /* _IRQ_GIC_COMMON_H */
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 19d642e..723cebe 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -28,6 +28,8 @@
#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/slab.h>
+#include <linux/msi.h>
+#include <linux/pci.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic-common.h>
@@ -736,6 +738,20 @@ static inline void gic_cpu_pm_init(void) { }
#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
+/*
+ * Due to #28168 erratum in ThunderX,
+ * we need to make sure DMA data transfer is done before MSIX.
+ */
+static void cavium_irq_perflow_handler(struct irq_data *data)
+{
+ struct pci_dev *pdev;
+
+ pdev = msi_desc_to_pci_dev(irq_data_get_msi_desc(data));
+ if ((pdev->vendor != 0x177d) &&
+ ((pdev->device & 0xA000) != 0xA000))
+ cavium_arm_smmu_tlb_sync(&pdev->dev);
+}
+
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
@@ -773,6 +789,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
return -EPERM;
irq_domain_set_info(d, irq, hw, chip, d->host_data,
handle_fasteoi_irq, NULL, NULL);
+ if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_28168))
+ __irq_set_preflow_handler(irq,
+ cavium_irq_perflow_handler);
}
return 0;
--
1.7.1
^ permalink raw reply related
* [PATCH] reset: hisilicon: add a polarity cell for reset line specifier
From: Jiancheng Xue @ 2016-11-15 7:09 UTC (permalink / raw)
To: linux-arm-kernel
Add a polarity cell for reset line specifier. If the reset line
is asserted when the register bit is 1, the polarity is
normal. Otherwise, it is inverted.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
.../devicetree/bindings/clock/hisi-crg.txt | 11 ++++---
arch/arm/boot/dts/hi3519.dtsi | 2 +-
drivers/clk/hisilicon/reset.c | 36 ++++++++++++++++------
3 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt
index e3919b6..fcbb4f3 100644
--- a/Documentation/devicetree/bindings/clock/hisi-crg.txt
+++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt
@@ -25,19 +25,20 @@ to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
-- #reset-cells: should be 2.
+- #reset-cells: should be 3.
A reset signal can be controlled by writing a bit register in the CRG module.
-The reset specifier consists of two cells. The first cell represents the
+The reset specifier consists of three cells. The first cell represents the
register offset relative to the base address. The second cell represents the
-bit index in the register.
+bit index in the register. The third cell represents the polarity of the reset
+line (0 for normal, 1 for inverted).
Example: CRG nodes
CRG: clock-reset-controller at 12010000 {
compatible = "hisilicon,hi3519-crg";
reg = <0x12010000 0x10000>;
#clock-cells = <1>;
- #reset-cells = <2>;
+ #reset-cells = <3>;
};
Example: consumer nodes
@@ -45,5 +46,5 @@ i2c0: i2c at 12110000 {
compatible = "hisilicon,hi3519-i2c";
reg = <0x12110000 0x1000>;
clocks = <&CRG HI3519_I2C0_RST>;
- resets = <&CRG 0xe4 0>;
+ resets = <&CRG 0xe4 0 0>;
};
diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
index 5729ecf..b7cb182 100644
--- a/arch/arm/boot/dts/hi3519.dtsi
+++ b/arch/arm/boot/dts/hi3519.dtsi
@@ -50,7 +50,7 @@
crg: clock-reset-controller at 12010000 {
compatible = "hisilicon,hi3519-crg";
#clock-cells = <1>;
- #reset-cells = <2>;
+ #reset-cells = <3>;
reg = <0x12010000 0x10000>;
};
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
index 2a5015c..c0ab0b6 100644
--- a/drivers/clk/hisilicon/reset.c
+++ b/drivers/clk/hisilicon/reset.c
@@ -17,6 +17,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
@@ -25,9 +26,11 @@
#include <linux/spinlock.h>
#include "reset.h"
-#define HISI_RESET_BIT_MASK 0x1f
-#define HISI_RESET_OFFSET_SHIFT 8
-#define HISI_RESET_OFFSET_MASK 0xffff00
+#define HISI_RESET_POLARITY_MASK BIT(0)
+#define HISI_RESET_BIT_SHIFT 1
+#define HISI_RESET_BIT_MASK GENMASK(6, 1)
+#define HISI_RESET_OFFSET_SHIFT 8
+#define HISI_RESET_OFFSET_MASK GENMASK(23, 8)
struct hisi_reset_controller {
spinlock_t lock;
@@ -44,12 +47,15 @@ static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
{
u32 offset;
u8 bit;
+ bool polarity;
offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT)
& HISI_RESET_OFFSET_MASK;
- bit = reset_spec->args[1] & HISI_RESET_BIT_MASK;
+ bit = (reset_spec->args[1] << HISI_RESET_BIT_SHIFT)
+ & HISI_RESET_BIT_MASK;
+ polarity = reset_spec->args[2] & HISI_RESET_POLARITY_MASK;
- return (offset | bit);
+ return (offset | bit | polarity);
}
static int hisi_reset_assert(struct reset_controller_dev *rcdev,
@@ -59,14 +65,19 @@ static int hisi_reset_assert(struct reset_controller_dev *rcdev,
unsigned long flags;
u32 offset, reg;
u8 bit;
+ bool polarity;
offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
- bit = id & HISI_RESET_BIT_MASK;
+ bit = (id & HISI_RESET_BIT_MASK) >> HISI_RESET_BIT_SHIFT;
+ polarity = id & HISI_RESET_POLARITY_MASK;
spin_lock_irqsave(&rstc->lock, flags);
reg = readl(rstc->membase + offset);
- writel(reg | BIT(bit), rstc->membase + offset);
+ if (polarity)
+ writel(reg & ~BIT(bit), rstc->membase + offset);
+ else
+ writel(reg | BIT(bit), rstc->membase + offset);
spin_unlock_irqrestore(&rstc->lock, flags);
@@ -80,14 +91,19 @@ static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long flags;
u32 offset, reg;
u8 bit;
+ bool polarity;
offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
- bit = id & HISI_RESET_BIT_MASK;
+ bit = (id & HISI_RESET_BIT_MASK) >> HISI_RESET_BIT_SHIFT;
+ polarity = id & HISI_RESET_POLARITY_MASK;
spin_lock_irqsave(&rstc->lock, flags);
reg = readl(rstc->membase + offset);
- writel(reg & ~BIT(bit), rstc->membase + offset);
+ if (polarity)
+ writel(reg | BIT(bit), rstc->membase + offset);
+ else
+ writel(reg & ~BIT(bit), rstc->membase + offset);
spin_unlock_irqrestore(&rstc->lock, flags);
@@ -118,7 +134,7 @@ struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev)
rstc->rcdev.owner = THIS_MODULE;
rstc->rcdev.ops = &hisi_reset_ops;
rstc->rcdev.of_node = pdev->dev.of_node;
- rstc->rcdev.of_reset_n_cells = 2;
+ rstc->rcdev.of_reset_n_cells = 3;
rstc->rcdev.of_xlate = hisi_reset_of_xlate;
reset_controller_register(&rstc->rcdev);
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] devicetree: bindings: nvmem: Add compatible string for imx6ul
From: Jacky Bai @ 2016-11-15 7:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114161423.fs7dlt5firmj4q3s@rob-hp-laptop>
> > Add new compatible string for i.MX6UL SOC.
> >
> > Signed-off-by: Bai Ping <ping.bai@nxp.com>
> > ---
> > Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > index 383d588..a7ff65d 100644
> > --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > @@ -1,13 +1,14 @@
> > Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
> >
> > This binding represents the on-chip eFuse OTP controller found on
> > -i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
> > +i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
> >
> > Required properties:
> > - compatible: should be one of
> > "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
> > - "fsl,imx6sl-ocotp" (i.MX6SL), or
> > - "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
> > + "fsl,imx6sl-ocotp" (i.MX6SL),
> > + "fsl,imx6sx-ocotp" (i.MX6SX), or
> > + "fsl,imx6ul-ocotp" (i.MX6UL), followed by "syscon".
>
> This should be reformatted such that it's not a 5 line change to add a
> compatible. "one of" defines this is an OR relationship, so drop that.
> Move 'followed by "syscon"' to below the list of compatibles.
>
Thanks for review, I will adopt in V2.
Jacky Bai
> > - reg: Should contain the register base and length.
> > - clocks: Should contain a phandle pointing to the gated peripheral clock.
> >
> > --
> > 2.8.2
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
From: Y.T. Tang @ 2016-11-15 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478715118-12848-1-git-send-email-harninder.rai@nxp.com>
Hi Harninder,
Please add compatible string "fsl,ls1043a-ahci" to sata node because they are compatible.
In this way, sata can be enabled.
Regards,
Yuantian
> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> bounces at lists.infradead.org] On Behalf Of Harninder Rai
> Sent: Thursday, November 10, 2016 2:12 AM
> To: devicetree at vger.kernel.org; shawnguo at kernel.org;
> robh+dt at kernel.org; mark.rutland at arm.com
> Cc: oss at buserror.net; Harninder Rai <harninder.rai@nxp.com>; Bhaskar U
> <bhaskar.upadhaya@nxp.com>; linux-arm-kernel at lists.infradead.org
> Subject: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
>
> Add the device tree support for FSL LS1012A SoC.
> Following levels of DTSI/DTS files have been created for the LS1012A
> SoC family:
>
> - fsl-ls1012a.dtsi:
> DTS-Include file for FSL LS1012A SoC.
>
> - fsl-ls1012a-frdm.dts:
> DTS file for FSL LS1012A FRDM board.
>
> - fsl-ls1012a-qds.dts:
> DTS file for FSL LS1012A QDS board.
>
> - fsl-ls1012a-rdb.dts:
> DTS file for FSL LS1012A RDB board.
>
> Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 3 +
> arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 115 ++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 128 +++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 59 +++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 248
> +++++++++++++++++++++
> 5 files changed, 553 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile
> b/arch/arm64/boot/dts/freescale/Makefile
> index 6602718..39db645 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -1,3 +1,6 @@
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb diff --git
> a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> new file mode 100644
> index 0000000..1f2da79
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> @@ -0,0 +1,115 @@
> +/*
> + * Device Tree file for Freescale LS1012A Freedom Board.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +/dts-v1/;
> +
> +#include "fsl-ls1012a.dtsi"
> +
> +/ {
> + model = "LS1012A Freedom Board";
> + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
> +
> + sys_mclk: clock-mclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + reg_1p8v: regulator at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,widgets =
> + "Microphone", "Microphone Jack",
> + "Headphone", "Headphone Jack",
> + "Speaker", "Speaker Ext",
> + "Line", "Line In Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Microphone Jack",
> + "Microphone Jack", "Mic Bias",
> + "LINE_IN", "Line In Jack",
> + "Headphone Jack", "HP_OUT",
> + "Speaker Ext", "LINE_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + frame-master;
> + bitclock-master;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&codec>;
> + frame-master;
> + bitclock-master;
> + system-clock-frequency = <25000000>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + codec: sgtl5000 at a {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,sgtl5000";
> + reg = <0xa>;
> + VDDA-supply = <®_1p8v>;
> + VDDIO-supply = <®_1p8v>;
> + clocks = <&sys_mclk>;
> + };
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> +
> +&sai2 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> new file mode 100644
> index 0000000..ca680a7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> @@ -0,0 +1,128 @@
> +/*
> + * Device Tree file for Freescale LS1012A QDS Board.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +/dts-v1/;
> +
> +#include "fsl-ls1012a.dtsi"
> +
> +/ {
> + model = "LS1012A QDS Board";
> + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
> +
> + sys_mclk: clock-mclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + };
> +
> + reg_3p3v: regulator at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,widgets =
> + "Microphone", "Microphone Jack",
> + "Headphone", "Headphone Jack",
> + "Speaker", "Speaker Ext",
> + "Line", "Line In Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Microphone Jack",
> + "Microphone Jack", "Mic Bias",
> + "LINE_IN", "Line In Jack",
> + "Headphone Jack", "HP_OUT",
> + "Speaker Ext", "LINE_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + frame-master;
> + bitclock-master;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&codec>;
> + frame-master;
> + bitclock-master;
> + system-clock-frequency = <24576000>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + pca9547 at 77 {
> + compatible = "nxp,pca9547";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c at 4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4>;
> +
> + codec: sgtl5000 at a {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,sgtl5000";
> + reg = <0xa>;
> + VDDA-supply = <®_3p3v>;
> + VDDIO-supply = <®_3p3v>;
> + clocks = <&sys_mclk>;
> + };
> + };
> + };
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> +
> +&sai2 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> new file mode 100644
> index 0000000..924dad6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> @@ -0,0 +1,59 @@
> +/*
> + * Device Tree file for Freescale LS1012A RDB Board.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +/dts-v1/;
> +
> +#include "fsl-ls1012a.dtsi"
> +
> +/ {
> + model = "LS1012A RDB Board";
> + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; };
> +
> +&i2c0 {
> + status = "okay";
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> new file mode 100644
> index 0000000..0bf5b64
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> @@ -0,0 +1,248 @@
> +/*
> + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "fsl,ls1012a";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + clocks = <&clockgen 1 0>;
> + #cooling-cells = <2>;
> + };
> + };
> +
> + sysclk: sysclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + /* Physical Secure PPI */
> + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,
> + /* Physical Non-Secure PPI */
> + <1 14 IRQ_TYPE_LEVEL_LOW>,
> + /* Virtual PPI */
> + <1 11 IRQ_TYPE_LEVEL_LOW>,
> + /* Hypervisor PPI */
> + <1 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <0 106 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + gic: interrupt-controller at 1400000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> + <0x0 0x1402000 0 0x2000>, /* GICC */
> + <0x0 0x1404000 0 0x2000>, /* GICH */
> + <0x0 0x1406000 0 0x2000>; /* GICV */
> + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + reboot {
> + compatible = "syscon-reboot";
> + regmap = <&dcfg>;
> + offset = <0xb0>;
> + mask = <0x02>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clockgen: clocking at 1ee1000 {
> + compatible = "fsl,ls1012a-clockgen";
> + reg = <0x0 0x1ee1000 0x0 0x1000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + };
> +
> + scfg: scfg at 1570000 {
> + compatible = "fsl,ls1012a-scfg", "syscon";
> + reg = <0x0 0x1570000 0x0 0x10000>;
> + big-endian;
> + };
> +
> + dcfg: dcfg at 1ee0000 {
> + compatible = "fsl,ls1012a-dcfg",
> + "syscon";
> + reg = <0x0 0x1ee0000 0x0 0x10000>;
> + big-endian;
> + };
> +
> + i2c0: i2c at 2180000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2180000 0x0 0x10000>;
> + interrupts = <0 56 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c at 2190000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2190000 0x0 0x10000>;
> + interrupts = <0 57 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + status = "disabled";
> + };
> +
> + duart0: serial at 21c0500 {
> + compatible = "fsl,ns16550", "ns16550a";
> + reg = <0x00 0x21c0500 0x0 0x100>;
> + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 0>;
> + };
> +
> + duart1: serial at 21c0600 {
> + compatible = "fsl,ns16550", "ns16550a";
> + reg = <0x00 0x21c0600 0x0 0x100>;
> + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 0>;
> + };
> +
> + gpio0: gpio at 2300000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2300000 0x0 0x10000>;
> + interrupts = <0 66 IRQ_TYPE_LEVEL_LOW>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio1: gpio at 2310000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2310000 0x0 0x10000>;
> + interrupts = <0 67 IRQ_TYPE_LEVEL_LOW>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + wdog0: wdog at 2ad0000 {
> + compatible = "fsl,ls1012a-wdt",
> + "fsl,imx21-wdt";
> + reg = <0x0 0x2ad0000 0x0 0x10000>;
> + interrupts = <0 83 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + big-endian;
> + };
> +
> + sai1: sai at 2b50000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,vf610-sai";
> + reg = <0x0 0x2b50000 0x0 0x10000>;
> + interrupts = <0 148 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> + <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dma-names = "tx", "rx";
> + dmas = <&edma0 1 47>,
> + <&edma0 1 46>;
> + status = "disabled";
> + };
> +
> + sai2: sai at 2b60000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,vf610-sai";
> + reg = <0x0 0x2b60000 0x0 0x10000>;
> + interrupts = <0 149 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> + <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dma-names = "tx", "rx";
> + dmas = <&edma0 1 45>,
> + <&edma0 1 44>;
> + status = "disabled";
> + };
> +
> + edma0: edma at 2c00000 {
> + #dma-cells = <2>;
> + compatible = "fsl,vf610-edma";
> + reg = <0x0 0x2c00000 0x0 0x10000>,
> + <0x0 0x2c10000 0x0 0x10000>,
> + <0x0 0x2c20000 0x0 0x10000>;
> + interrupts = <0 103 IRQ_TYPE_LEVEL_LOW>,
> + <0 103 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "edma-tx", "edma-err";
> + dma-channels = <32>;
> + big-endian;
> + clock-names = "dmamux0", "dmamux1";
> + clocks = <&clockgen 4 3>,
> + <&clockgen 4 3>;
> + };
> +
> + sata: sata at 3200000 {
> + compatible = "fsl,ls1012a-ahci";
> + reg = <0x0 0x3200000 0x0 0x10000>;
> + interrupts = <0 69 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + };
> + };
> +};
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH V7 1/3] tracing: add a possibility of exporting function trace to other places instead of ring buffer only
From: Chunyan Zhang @ 2016-11-15 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114105926.7bc7844b@gandalf.local.home>
On 14 November 2016 at 23:59, Steven Rostedt <rostedt@goodmis.org> wrote:
> On Fri, 21 Oct 2016 20:13:13 +0800
> Chunyan Zhang <zhang.chunyan@linaro.org> wrote:
>
>> On 18 October 2016 at 23:44, Steven Rostedt <rostedt@goodmis.org> wrote:
>> > On Tue, 18 Oct 2016 16:08:58 +0800
>> > Chunyan Zhang <zhang.chunyan@linaro.org> wrote:
>> >
>> >> Currently Function traces can be only exported to ring buffer, this
>> >> patch added trace_export concept which can process traces and export
>> >> them to a registered destination as an addition to the current only
>> >> one output of Ftrace - i.e. ring buffer.
>> >>
>> >> In this way, if we want Function traces to be sent to other destination
>> >> rather than ring buffer only, we just need to register a new trace_export
>> >> and implement its own .write() function for writing traces to storage.
>> >>
>> >> With this patch, only Function trace (trace type is TRACE_FN)
>> >> is supported.
>> >
>> > This is getting better, but I still have some nits.
>> >
>>
>> Thanks.
>>
>> >>
>> >> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
>> >> ---
>> >> include/linux/trace.h | 28 +++++++++++
>> >> kernel/trace/trace.c | 132 +++++++++++++++++++++++++++++++++++++++++++++++++-
>> >> 2 files changed, 159 insertions(+), 1 deletion(-)
>> >> create mode 100644 include/linux/trace.h
>> >>
>> >> diff --git a/include/linux/trace.h b/include/linux/trace.h
>> >> new file mode 100644
>> >> index 0000000..eb1c5b8
>> >> --- /dev/null
>> >> +++ b/include/linux/trace.h
>> >> @@ -0,0 +1,28 @@
>> >> +#ifndef _LINUX_TRACE_H
>> >> +#define _LINUX_TRACE_H
>> >> +
>> >> +#ifdef CONFIG_TRACING
>> >> +/*
>> >> + * The trace export - an export of Ftrace output. The trace_export
>> >> + * can process traces and export them to a registered destination as
>> >> + * an addition to the current only output of Ftrace - i.e. ring buffer.
>> >> + *
>> >> + * If you want traces to be sent to some other place rather than ring
>> >> + * buffer only, just need to register a new trace_export and implement
>> >> + * its own .write() function for writing traces to the storage.
>> >> + *
>> >> + * next - pointer to the next trace_export
>> >> + * write - copy traces which have been delt with ->commit() to
>> >> + * the destination
>> >> + */
>> >> +struct trace_export {
>> >> + struct trace_export __rcu *next;
>> >> + void (*write)(const char *, unsigned int);
>> >
>> > Why const char*? Why not const void *? This will never be a string.
>> >
>>
>> Will revise this.
>>
>> >
>> >> +};
>> >> +
>> >> +int register_ftrace_export(struct trace_export *export);
>> >> +int unregister_ftrace_export(struct trace_export *export);
>> >> +
>> >> +#endif /* CONFIG_TRACING */
>> >> +
>> >> +#endif /* _LINUX_TRACE_H */
>> >> diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
>> >> index 8696ce6..db94ec1 100644
>> >> --- a/kernel/trace/trace.c
>> >> +++ b/kernel/trace/trace.c
>> >> @@ -40,6 +40,7 @@
>> >> #include <linux/poll.h>
>> >> #include <linux/nmi.h>
>> >> #include <linux/fs.h>
>> >> +#include <linux/trace.h>
>> >> #include <linux/sched/rt.h>
>> >>
>> >> #include "trace.h"
>> >> @@ -2128,6 +2129,132 @@ void trace_buffer_unlock_commit_regs(struct trace_array *tr,
>> >> ftrace_trace_userstack(buffer, flags, pc);
>> >> }
>> >>
>> >> +static void
>> >> +trace_process_export(struct trace_export *export,
>> >> + struct ring_buffer_event *event)
>> >> +{
>> >> + struct trace_entry *entry;
>> >> + unsigned int size = 0;
>> >> +
>> >> + entry = ring_buffer_event_data(event);
>> >> +
>> >> + size = ring_buffer_event_length(event);
>> >> +
>> >> + if (export->write)
>> >> + export->write((char *)entry, size);
>> >
>> > Is there ever going to be a time where export->write wont be set?
>>
>> There hasn't been since only one trace_export (i.e. stm_ftrace) was
>> added in this patch-set , I just wanted to make sure the write() has
>> been set before registering trace_export like what I added in 2/3 of
>> this series.
>>
>> >
>> > And if there is, this can be racy. As in
>> >
>> >
>> > CPU 0: CPU 1:
>> > ------ ------
>> > if (export->write)
>> >
>> > export->write = NULL;
>>
>> Is there going to be this kind of use case? Why some one needs to
>> change export->write() rather than register a new trace_export?
>
> Then why have a
>
> if (export->write)
>
>
> Is there every going to be a case where export will not have a write
> function?
There shouldn't be.
I can move this if statement to the register_ftrace_export() to ensure
users won't wrongly use it, that's saying the write() of trace_export
has been set before being registered to 'ftrace_exports_list'.
Thanks,
Chunyan
>
> -- Steve
>
>>
>> I probably haven't understood your point thoroughly, please correct me
>> if my guess was wrong.
>>
>>
>> Thanks for the review,
>> Chunyan
>>
>> >
>> > export->write(entry, size);
>> >
>> > BOOM!
>> >
>> >
>> > -- Steve
^ permalink raw reply
* [PATCH v2 4/6] mm: mempolicy: intruduce a helper huge_nodemask()
From: Huang Shijie @ 2016-11-15 8:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87oa1hb7tp.fsf@linux.vnet.ibm.com>
On Tue, Nov 15, 2016 at 11:31:06AM +0530, Aneesh Kumar K.V wrote:
> Huang Shijie <shijie.huang@arm.com> writes:
> > #ifdef CONFIG_HUGETLBFS
> > /*
> > + * huge_nodemask(@vma, @addr)
> > + * @vma: virtual memory area whose policy is sought
> > + * @addr: address in @vma for shared policy lookup and interleave policy
> > + *
> > + * If the effective policy is BIND, returns a pointer to the mempolicy's
> > + * @nodemask.
> > + */
> > +nodemask_t *huge_nodemask(struct vm_area_struct *vma, unsigned long addr)
> > +{
> > + nodemask_t *nodes_mask = NULL;
> > + struct mempolicy *mpol = get_vma_policy(vma, addr);
> > +
> > + if (mpol->mode == MPOL_BIND)
> > + nodes_mask = &mpol->v.nodes;
> > + mpol_cond_put(mpol);
>
> What if it is MPOL_PREFERED or MPOL_INTERLEAVE ? we don't honor node
> mask in that case ?
I wrote this code by following the logic in the huge_zonelist().
So I ignored the support for MPOL_PREFERED/MPOL_INTERLEAVE.
IMHO, it is okay to allocate a gigantic page with MPOL_PREFERED/MPOL_BIND.
But I am not sure if we can allocate a gigantic page with MPOL_INTERLEAVE, since
since the gigantic page's order is bigger then MAX_ORDER.
Could you give me some advice about this?
Thanks
Huang Shijie
^ permalink raw reply
* [PATCH v4 1/2] pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank
From: Linus Walleij @ 2016-11-15 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478680811-24835-2-git-send-email-cw00.choi@samsung.com>
On Wed, Nov 9, 2016 at 9:40 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
> In the pre-existing Exynos series, the registers of the gpio bank are included
> in the one memory map. But, some gpio bank need to support the one more memory
> map (IORESOURCE_MEM) because the registers of gpio bank are separated into
> the different memory map.
>
> For example,
> The both ALIVE and IMEM domain have the different memory base address.
> The GFP[1-5] of exynos5433 are composed as following:
> - ALIVE domain : WEINT_* registers
> - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: linux-gpio at vger.kernel.org
> Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v4 2/2] pinctrl: samsung: Add GPF support for Exynos5433
From: Linus Walleij @ 2016-11-15 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478680811-24835-3-git-send-email-cw00.choi@samsung.com>
On Wed, Nov 9, 2016 at 9:40 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
> to support the multiple memory map because the registers of GPFx are located
> in the different domain.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: linux-gpio at vger.kernel.org
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 4/6] mm: mempolicy: intruduce a helper huge_nodemask()
From: Huang Shijie @ 2016-11-15 8:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87oa1hb7tp.fsf@linux.vnet.ibm.com>
On Tue, Nov 15, 2016 at 11:31:06AM +0530, Aneesh Kumar K.V wrote:
> Huang Shijie <shijie.huang@arm.com> writes:
> > #ifdef CONFIG_HUGETLBFS
> > /*
> > + * huge_nodemask(@vma, @addr)
> > + * @vma: virtual memory area whose policy is sought
> > + * @addr: address in @vma for shared policy lookup and interleave policy
> > + *
> > + * If the effective policy is BIND, returns a pointer to the mempolicy's
> > + * @nodemask.
> > + */
> > +nodemask_t *huge_nodemask(struct vm_area_struct *vma, unsigned long addr)
> > +{
> > + nodemask_t *nodes_mask = NULL;
> > + struct mempolicy *mpol = get_vma_policy(vma, addr);
> > +
> > + if (mpol->mode == MPOL_BIND)
> > + nodes_mask = &mpol->v.nodes;
> > + mpol_cond_put(mpol);
>
> What if it is MPOL_PREFERED or MPOL_INTERLEAVE ? we don't honor node
> mask in that case ?
>
I suddenly find maybe I should follow init_nodemask_of_mempolicy(), not the
huge_zonelist(). Is it okay?
Thanks
Huang Shijie
^ permalink raw reply
* [GIT PULL 1/5] i.MX non-critical fixes for 4.10
From: Shawn Guo @ 2016-11-15 9:00 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-fix-nc-4.10
for you to fetch changes up to 72649a46067903d00f46e2ebef6543768224f1a0:
ARM: dts: imx6q-cm-fx6: fix fec pinctrl (2016-11-14 15:31:01 +0800)
----------------------------------------------------------------
i.MX non-critical fixes for 4.10:
- A series from Vladimir to fix broken i.MX31 DT clock initialization.
As i.MX31 DT support is still not quite complete, the changes are
tested on qemu kzm target and mx31lite board with simple written DTS
files.
- A fix for CompuLab's sbc-fx6 baseboard to remove wrong fec pinctrl
setting.
- A DTS correction for i.MX6QP to reflect the change that the gate of
LDB clock has been moved before the divider.
- An imx7d-pinfunc fix for UART pinmux defines
----------------------------------------------------------------
Christopher Spinrath (1):
ARM: dts: imx6q-cm-fx6: fix fec pinctrl
Lucas Stach (1):
ARM: dts: imx6qp: correct LDB clock inputs
Stefan Agner (1):
ARM: dts: imx7d-pinfunc: fix UART pinmux defines
Vladimir Zapolskiy (4):
ARM: dts: imx31: fix clock control module interrupts description
ARM: dts: imx31: move CCM device node to AIPS2 bus devices
clk: imx31: fix rewritten input argument of mx31_clocks_init()
ARM: clk: imx31: properly init clocks for machines with DT
.../devicetree/bindings/clock/imx31-clock.txt | 2 +-
arch/arm/boot/dts/imx31.dtsi | 14 +++---
arch/arm/boot/dts/imx6q-cm-fx6.dts | 1 -
arch/arm/boot/dts/imx6qp.dtsi | 10 +++++
arch/arm/boot/dts/imx7d-pinfunc.h | 12 +++--
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/imx31-dt.c | 6 ---
drivers/clk/imx/clk-imx31.c | 52 +++++++++++-----------
8 files changed, 52 insertions(+), 46 deletions(-)
^ permalink raw reply
* [GIT PULL 2/5] i.MX soc updates for 4.10
From: Shawn Guo @ 2016-11-15 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-soc-4.10
for you to fetch changes up to 75b832fea2564c547dfd0a2377a5893f41aefec6:
ARM: imx: mach-imx6ul: add imx6ull support (2016-11-15 08:58:43 +0800)
----------------------------------------------------------------
i.MX SoC changes for 4.10:
- Drop PL310_ERRATA_769419 for Vybrid, as it turns out that the SoC
integrates revision r3p2 of the L2C-310, which is not affected by
errata 769419.
- Support perf for i.MX6 Multi-Mode DDR Controller (MMDC), so that we
can profile memory access performance.
- Support i.MX6ULL SoC using i.MX6UL base, since it's a derivative of
i.MX6UL and pin-to-pin compatible with i.MX6UL.
----------------------------------------------------------------
Andrey Smirnov (1):
ARM: imx: Drop errata 769419 for Vybrid
Frank Li (1):
ARM: imx: mmdc perf function support i.MX6QP
Peter Chen (1):
ARM: imx: mach-imx6ul: add imx6ull support
Zhengyu Shen (1):
ARM: imx: Added perf functionality to mmdc driver
arch/arm/mach-imx/Kconfig | 1 -
arch/arm/mach-imx/mach-imx6ul.c | 1 +
arch/arm/mach-imx/mmdc.c | 495 +++++++++++++++++++++++++++++++++++++++-
3 files changed, 489 insertions(+), 8 deletions(-)
^ permalink raw reply
* [GIT PULL 3/5] i.MX device tree updates for 4.10
From: Shawn Guo @ 2016-11-15 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt-4.10
for you to fetch changes up to c201369d4aa5f05b8a37d6d1eeabf248c7086454:
ARM: dts: imx6ull: add imx6ull support (2016-11-15 08:54:27 +0800)
----------------------------------------------------------------
i.MX device tree updates for 4.10:
- New boards support: i.MX6SX UDOO Neo, Boundary Devices Nitrogen6_SOM2,
Engicam i.CoreM6, Grinn i.MX6UL liteSOM/liteBoard, Toradex Colibri
iMX6 module, i.MX6ULL and EVK board.
- Remove skeleton.dtsi inclusion from all i.MX SoC dts files, as it's
been deprecated, since commit 9c0da3cc61f1233c ("ARM: dts: explicitly
mark skeleton.dtsi as deprecated").
- Misc device addition and enabling: OCOTP for Vybrid, MMDC for i.MX6QP,
TMU for LS1021A, FEC for imx6qdl-icore, DMA for Vybrid DSPI.
- A few cleanups: use hyphens for node names, fix white spaces, move
imx-weim parameters into SoC dtsi, replace gpio-key,wakeup with
wakeup-source, remove pwm-leds from imx6q-apalis-ixora, remove I2C3
from vf610-zii-dev-rev-b.
- Other small random changes: calibrate USB PHY for b650v3 board,
update TX D_CAL for USBPHY, use enable-gpios for backlight on
imx6qdl-apalis, etc.
----------------------------------------------------------------
Andreas F?rber (1):
ARM: dts: imx6sx: Add UDOO Neo support
Andrey Smirnov (2):
ARM: dts: vf610-zii-dev-rev-b: Remove I2C3
ARM: dts: vfxxx: Add node corresponding to OCOTP
Christopher Spinrath (1):
ARM: dts: imx6q-utilite-pro: i2c1 is muxed
Fabio Estevam (2):
ARM: dts: imx6sx-udoo: Add board specific compatible strings
ARM: dts: imx: Remove skeleton.dtsi
Frank Li (1):
ARM: dts: add new compatible string for i.MX6QP mmdc
Gary Bisson (5):
ARM: dts: imx: add Boundary Devices Nitrogen6_SOM2 support
ARM: dts: imx6qdl-sabrelite: use hyphens for nodes name
ARM: dts: imx6qdl-nitrogen6x: use hyphens for nodes name
ARM: dts: imx6qdl-nit6xlite: use hyphens for nodes name
ARM: dts: imx6qdl-nitrogen6_max: use hyphens for nodes name
Hongtao Jia (1):
ARM: dts: ls1021a: Add TMU device tree support for LS1021A
Jagan Teki (7):
ARM: dts: imx6qdl: Fix "WARNING: please, no space before tabs"
ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible"
ARM: dts: imx6qdl-wandboard-revb: Fix "ERROR: trailing whitespace"
ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support
ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support
ARM: dts: imx6qdl-icore: Add FEC support
ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible"
Jaret Cantu (1):
ARM: dts: imx: b650v3: Calibrate USB PHY to pass eye diagram test
Joshua Clayton (1):
ARM: dts: imx6: Add imx-weim parameters to dtsi's
Marcin Niestroj (2):
ARM: dts: imx6ul: Add DTS for liteSOM module
ARM: dts: imx6ul: Add DTS for liteBoard
Marek Vasut (4):
ARM: dts: imx6sx: Fix LCDIF interrupt type
ARM: dts: novena: Enable PWM1
ARM: dts: mxs: Add new M28EVK manufacturer compat
ARM: dts: mx5: Add new M53EVK manufacturer compat
Peter Chen (4):
ARM: dts: imx6ul-14x14-evk: add USB dual-role support
ARM: dts: imx6sx-sdb: update TX D_CAL for USBPHY
ARM: dts: imx6ul-14x14-evk: update TX D_CAL for USBPHY
ARM: dts: imx6ull: add imx6ull support
Sanchayan Maity (5):
ARM: dts: imx6: Add support for Toradex Colibri iMX6 module
ARM: dts: imx6q-apalis-ixora: Remove use of pwm-leds
ARM: dts: imx6qdl-apalis: Use enable-gpios property for backlight
ARM: dts: vfxxx: Enable DMA for DSPI on Vybrid
ARM: dts: vfxxx: Enable DMA for DSPI2 and DSPI3
Sudeep Holla (1):
ARM: dts: imx6q: replace gpio-key,wakeup with wakeup-source for Utilite Pro
arch/arm/boot/dts/Makefile | 13 +-
arch/arm/boot/dts/imx1.dtsi | 4 +-
arch/arm/boot/dts/imx23.dtsi | 6 +-
arch/arm/boot/dts/imx25.dtsi | 4 +-
arch/arm/boot/dts/imx27.dtsi | 4 +-
arch/arm/boot/dts/imx28-m28.dtsi | 4 +-
arch/arm/boot/dts/imx28-m28evk.dts | 4 +-
arch/arm/boot/dts/imx28.dtsi | 4 +-
arch/arm/boot/dts/imx31.dtsi | 5 +-
arch/arm/boot/dts/imx35.dtsi | 4 +-
arch/arm/boot/dts/imx50.dtsi | 48 +-
arch/arm/boot/dts/imx51.dtsi | 48 +-
arch/arm/boot/dts/imx53-m53.dtsi | 4 +-
arch/arm/boot/dts/imx53-m53evk.dts | 4 +-
arch/arm/boot/dts/imx53.dtsi | 72 +-
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 253 +++++++
arch/arm/boot/dts/imx6dl-icore.dts | 59 ++
arch/arm/boot/dts/imx6dl-riotboard.dts | 2 +-
arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts | 2 +-
arch/arm/boot/dts/imx6dl-tx6u-801x.dts | 2 +-
arch/arm/boot/dts/imx6q-apalis-ixora.dts | 22 -
arch/arm/boot/dts/imx6q-b650v3.dts | 6 +
arch/arm/boot/dts/imx6q-evi.dts | 3 -
arch/arm/boot/dts/imx6q-icore.dts | 59 ++
arch/arm/boot/dts/imx6q-nitrogen6_som2.dts | 53 ++
arch/arm/boot/dts/imx6q-novena.dts | 4 +
arch/arm/boot/dts/imx6q-phytec-pbab01.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1010.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1020.dts | 2 +-
arch/arm/boot/dts/imx6q-utilite-pro.dts | 53 +-
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 9 +
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 14 +-
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 890 +++++++++++++++++++++++++
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-icore.dtsi | 265 ++++++++
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 32 +-
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 18 +-
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 770 +++++++++++++++++++++
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 12 +-
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 6 +-
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 10 +-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl-tx6.dtsi | 32 +-
arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl.dtsi | 14 +-
arch/arm/boot/dts/imx6qp.dtsi | 7 +
arch/arm/boot/dts/imx6sl.dtsi | 7 +-
arch/arm/boot/dts/imx6sx-sdb.dtsi | 16 +-
arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts | 69 ++
arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts | 54 ++
arch/arm/boot/dts/imx6sx-udoo-neo-full.dts | 69 ++
arch/arm/boot/dts/imx6sx-udoo-neo.dtsi | 293 ++++++++
arch/arm/boot/dts/imx6sx.dtsi | 17 +-
arch/arm/boot/dts/imx6ul-14x14-evk.dts | 10 +-
arch/arm/boot/dts/imx6ul-liteboard.dts | 147 ++++
arch/arm/boot/dts/imx6ul-litesom.dtsi | 82 +++
arch/arm/boot/dts/imx6ul.dtsi | 4 +-
arch/arm/boot/dts/imx6ull-14x14-evk.dts | 52 ++
arch/arm/boot/dts/imx6ull-pinfunc.h | 56 ++
arch/arm/boot/dts/imx6ull.dtsi | 43 ++
arch/arm/boot/dts/imx7s.dtsi | 4 +-
arch/arm/boot/dts/ls1021a.dtsi | 84 ++-
arch/arm/boot/dts/vf-colibri.dtsi | 4 +
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 14 -
arch/arm/boot/dts/vfxxx.dtsi | 18 +
72 files changed, 3638 insertions(+), 268 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
create mode 100644 arch/arm/boot/dts/imx6dl-icore.dts
create mode 100644 arch/arm/boot/dts/imx6q-icore.dts
create mode 100644 arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-colibri.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-icore.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-liteboard.dts
create mode 100644 arch/arm/boot/dts/imx6ul-litesom.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts
create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h
create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
^ permalink raw reply
* [GIT PULL 4/5] Freescale arm64 device tree updates for 4.10
From: Shawn Guo @ 2016-11-15 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt64-4.10
for you to fetch changes up to 236f794e4463a6b53139702c1b609091f61a17ab:
arm64: dts: ls2080a: Add TMU device tree support for LS2080A (2016-11-15 15:05:36 +0800)
----------------------------------------------------------------
Freescale arm64 device tree updates for 4.10:
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
----------------------------------------------------------------
Hongtao Jia (2):
arm64: dts: ls1043a: Add TMU device tree support for LS1043A
arm64: dts: ls2080a: Add TMU device tree support for LS2080A
Mingkai Hu (2):
arm64: dts: add QorIQ LS1046A SoC support
arm64: dts: add LS1046A-RDB board support
Shaohui Xie (8):
dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings
dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG
dt-bindings: i2c: adds two more nxp devices
dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen
dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a
Documentation: DT: Add entry for QorIQ LS1046A-RDB board
Documentation: DT: Add entry for QorIQ LS1046A-QDS board
arm64: dts: add LS1046A-QDS board support
Documentation/devicetree/bindings/arm/fsl.txt | 34 +-
.../devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +-
.../devicetree/bindings/clock/qoriq-clock.txt | 3 +
.../devicetree/bindings/i2c/trivial-devices.txt | 2 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 78 ++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 212 +++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 150 ++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 515 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 ++++-
15 files changed, 1107 insertions(+), 17 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
^ permalink raw reply
* [GIT PULL 5/5] i.MX defconfig updates for 4.10
From: Shawn Guo @ 2016-11-15 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-defconfig-4.10
for you to fetch changes up to 3252e255371ad22c02d5c9d1740d408ce1b10f35:
ARM: imx_v6_v7_defconfig: Select the es8328 codec driver (2016-10-24 19:54:38 +0800)
----------------------------------------------------------------
i.MX defconfig updates for 4.10:
- Increase CMA size to 64 MiB, so that we can use etnaviv driver with
1920x1080 display devices.
- Enable ES8328 codec driver support, which is required by Kosagi
Novena boards.
----------------------------------------------------------------
Marek Vasut (2):
ARM: imx_v6_v7_defconfig: Increase CMA size
ARM: imx_v6_v7_defconfig: Select the es8328 codec driver
arch/arm/configs/imx_v6_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
^ permalink raw reply
* [PATCH v3 0/3] modversions: Fix CRC mangling under CONFIG_RELOCATABLE=y
From: Ard Biesheuvel @ 2016-11-15 9:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87eg2kj757.fsf@concordia.ellerman.id.au>
On 10 November 2016 at 05:22, Michael Ellerman <mpe@ellerman.id.au> wrote:
> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes:
>
>> On 27 October 2016 at 17:27, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>>> This series is a followup to the single patch 'modversions: treat symbol
>>> CRCs as 32 bit quantities on 64 bit archs', of which two versions have
>>> been sent out so far [0][1]
>>>
>>> As pointed out by Michael, GNU ld behaves a bit differently between arm64
>>> and PowerPC64, and where the former gets rid of all runtime relocations
>>> related to CRCs, the latter is not as easily convinced.
>>>
>>> Patch #1 fixes the issue where CRCs are corrupted by the runtime relocation
>>> routines for 32-bit PowerPC, for which the original fix was effectively
>>> reverted by commit 0e0ed6406e61 ("powerpc/modules: Module CRC relocation fix
>>> causes perf issues")
>>>
>>> Patch #2 adds handling of R_PPC64_ADDR32 relocations against the NULL .dynsym
>>> symbol entry to the PPC64 runtime relocation routines, so it is prepared to
>>> deal with CRCs being emitted as 32-bit quantities.
>>>
>>> Patch #3 is the original patch from the v1 and v2 submissions.
>>>
>>> Changes since v2:
>>> - added #1 and #2
>>> - updated #3 to deal with CRC entries being emitted from assembler
>>> - added Rusty's ack (#3)
>>>
>>> Branch can be found here:
>>> https://git.kernel.org/cgit/linux/kernel/git/ardb/linux.git/log/?h=kcrctab-reloc
>>>
>>> [0] http://marc.info/?l=linux-kernel&m=147652300207369&w=2
>>> [1] http://marc.info/?l=linux-kernel&m=147695629614409&w=2
>>
>> Ping?
>
> Sorry, you didn't cc linuxppc-dev, so it's not in my patchwork list
> which tends to mean I miss it.
>
Ah, my mistake. Apologies.
> Will try and test and get back to you.
>
Thanks!
^ permalink raw reply
* [PATCH V1 0/2] Add support for ThunderX SoCs ACPI Host Controllers
From: Tomasz Nowicki @ 2016-11-15 9:14 UTC (permalink / raw)
To: linux-arm-kernel
These patches were part of https://lkml.org/lkml/2016/9/9/666 series,
however, only core part (first two patches) was approved. ThunderX quirk
example had some comments which are address in this series (resetting version
numbering).
Add ACPI PCI host controler support for ThunderX SoCs pass1.x & pass2.x using
ACPI quirk mechanism [1]. Patches rework ThunderX ECAM and PEM driver to work
with ACPI & DT boot method.
Patch set can be found here:
git at github.com:semihalf-nowicki-tomasz/linux.git (pci-quirks-thunderx-v1)
It is based on branch pci/ecam-v6 which can be found here:
[1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git (pci/ecam-v6)
Tomasz Nowicki (2):
PCI: thunder: Enable ACPI PCI controller for ThunderX pass2.x silicon
version
PCI: thunder: Enable ACPI PCI controller for ThunderX pass1.x silicon
version
drivers/acpi/pci_mcfg.c | 35 ++++++++++++
drivers/pci/host/pci-thunder-ecam.c | 2 +-
drivers/pci/host/pci-thunder-pem.c | 107 +++++++++++++++++++++++++++++++-----
include/linux/pci-ecam.h | 7 +++
4 files changed, 136 insertions(+), 15 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH V1 1/2] PCI: thunder: Enable ACPI PCI controller for ThunderX pass2.x silicon version
From: Tomasz Nowicki @ 2016-11-15 9:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479201298-25494-1-git-send-email-tn@semihalf.com>
ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully
compliant with ECAM standard. It uses non-standard configuration space
accessors (see pci_thunder_pem_ops) and custom configuration space granulation
(see bus_shift = 24). In order to access configuration space and
probe PEM as ACPI based PCI host controller we need to add MCFG quirk
infrastructure. This involves:
1. thunder_pem_init() ACPI extension so that we can probe PEM-specific
register ranges analogously to DT
2. Export PEM pci_thunder_pem_ops structure so it is visible to MCFG quirk
code.
3. New quirk entries for each PEM segment. Each contains platform IDs,
mentioned pci_thunder_pem_ops and CFG resources.
Quirk is considered for ThunderX silicon pass2.x only which is identified
via MCFG revision 1.
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
---
drivers/acpi/pci_mcfg.c | 20 +++++++
drivers/pci/host/pci-thunder-pem.c | 107 ++++++++++++++++++++++++++++++++-----
include/linux/pci-ecam.h | 4 ++
3 files changed, 117 insertions(+), 14 deletions(-)
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..e4e2b9b 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,26 @@ static struct mcfg_fixup mcfg_quirks[] = {
{ "QCOM ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, &pci_32b_ops },
{ "QCOM ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, &pci_32b_ops },
{ "QCOM ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, &pci_32b_ops },
+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
+#define THUNDER_MCFG_RES(addr, node) \
+ DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M)
+#define THUNDER_MCFG_QUIRK(rev, node) \
+ { "CAVIUM", "THUNDERX", rev, 4 + (10 * node), MCFG_BUS_ANY, \
+ &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x88001f000000UL, node) }, \
+ { "CAVIUM", "THUNDERX", rev, 5 + (10 * node), MCFG_BUS_ANY, \
+ &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x884057000000UL, node) }, \
+ { "CAVIUM", "THUNDERX", rev, 6 + (10 * node), MCFG_BUS_ANY, \
+ &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x88808f000000UL, node) }, \
+ { "CAVIUM", "THUNDERX", rev, 7 + (10 * node), MCFG_BUS_ANY, \
+ &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x89001f000000UL, node) }, \
+ { "CAVIUM", "THUNDERX", rev, 8 + (10 * node), MCFG_BUS_ANY, \
+ &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x894057000000UL, node) }, \
+ { "CAVIUM", "THUNDERX", rev, 9 + (10 * node), MCFG_BUS_ANY, \
+ &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x89808f000000UL, node) }
+ /* SoC pass2.x */
+ THUNDER_MCFG_QUIRK(1, 0UL),
+ THUNDER_MCFG_QUIRK(1, 1UL),
+#endif
};
static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/pci-thunder-pem.c b/drivers/pci/host/pci-thunder-pem.c
index 6abaf80..7bdc4cd 100644
--- a/drivers/pci/host/pci-thunder-pem.c
+++ b/drivers/pci/host/pci-thunder-pem.c
@@ -18,6 +18,7 @@
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
+#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>
#include <linux/platform_device.h>
@@ -284,6 +285,84 @@ static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
return pci_generic_config_write(bus, devfn, where, size, val);
}
+#ifdef CONFIG_ACPI
+
+/*
+ * Retrieve PEM bridge register base and size from PNP0C02 sub-device under
+ * the RC.
+ *
+ * Device (RES0)
+ * {
+ * Name (_HID, "THRX0002")
+ * Name (_CID, "PNP0C02")
+ * Name (_CRS, ResourceTemplate () {
+ * // Device specific registers range
+ * QWordMemory(ResourceConsumer, PosDecode, MinFixed,
+ * MaxFixed, Cacheable, ReadWrite, 0,
+ * 0x87e0c2000000, 0x87E0C2FFFFFF, 0, 0x1000000)
+ * })
+ * }
+ */
+
+static const struct acpi_device_id thunder_pem_reg_ids[] = {
+ {"THRX0002", 0},
+ {"", 0},
+};
+
+static struct resource *thunder_pem_acpi_res(struct pci_config_window *cfg)
+{
+ struct device *dev = cfg->parent;
+ struct acpi_device *adev = to_acpi_device(dev);
+ struct acpi_device *child_adev;
+ struct resource *res_pem;
+
+ res_pem = devm_kzalloc(dev, sizeof(*res_pem), GFP_KERNEL);
+ if (!res_pem) {
+ dev_err(dev, "failed to allocate PEM resource\n");
+ return NULL;
+ }
+
+ list_for_each_entry(child_adev, &adev->children, node) {
+ struct resource_entry *entry;
+ struct list_head list;
+ unsigned long flags;
+ int ret;
+
+ ret = acpi_match_device_ids(child_adev, thunder_pem_reg_ids);
+ if (ret)
+ continue;
+
+ INIT_LIST_HEAD(&list);
+ flags = IORESOURCE_MEM;
+ ret = acpi_dev_get_resources(child_adev, &list,
+ acpi_dev_filter_resource_type_cb,
+ (void *)flags);
+ if (ret < 0) {
+ dev_err(&child_adev->dev,
+ "failed to parse _CRS method, error code %d\n",
+ ret);
+ return NULL;
+ } else if (ret == 0) {
+ dev_err(&child_adev->dev,
+ "no memory resources present in _CRS\n");
+ return NULL;
+ }
+
+ entry = list_first_entry(&list, struct resource_entry, node);
+ *res_pem = *entry->res;
+ acpi_dev_free_resource_list(&list);
+ return res_pem;
+ }
+
+ return NULL;
+}
+#else
+static struct resource *thunder_pem_acpi_res(struct pci_config_window *cfg)
+{
+ return NULL;
+}
+#endif
+
static int thunder_pem_init(struct pci_config_window *cfg)
{
struct device *dev = cfg->parent;
@@ -292,24 +371,24 @@ static int thunder_pem_init(struct pci_config_window *cfg)
struct thunder_pem_pci *pem_pci;
struct platform_device *pdev;
- /* Only OF support for now */
- if (!dev->of_node)
- return -EINVAL;
-
pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
if (!pem_pci)
return -ENOMEM;
- pdev = to_platform_device(dev);
-
- /*
- * The second register range is the PEM bridge to the PCIe
- * bus. It has a different config access method than those
- * devices behind the bridge.
- */
- res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (acpi_disabled) {
+ pdev = to_platform_device(dev);
+
+ /*
+ * The second register range is the PEM bridge to the PCIe
+ * bus. It has a different config access method than those
+ * devices behind the bridge.
+ */
+ res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ } else {
+ res_pem = thunder_pem_acpi_res(cfg);
+ }
if (!res_pem) {
- dev_err(dev, "missing \"reg[1]\"property\n");
+ dev_err(dev, "missing configuration region\n");
return -EINVAL;
}
@@ -332,7 +411,7 @@ static int thunder_pem_init(struct pci_config_window *cfg)
return 0;
}
-static struct pci_ecam_ops pci_thunder_pem_ops = {
+struct pci_ecam_ops pci_thunder_pem_ops = {
.bus_shift = 24,
.init = thunder_pem_init,
.pci_ops = {
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index f5740b7..3f2a98f 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -58,6 +58,10 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
int where);
/* default ECAM ops */
extern struct pci_ecam_ops pci_generic_ecam_ops;
+/* ECAM ops for known quirks */
+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
+extern struct pci_ecam_ops pci_thunder_pem_ops;
+#endif
/* ops for buggy ECAM that supports only 32-bit accesses */
extern struct pci_ecam_ops pci_32b_ops;
--
2.7.4
^ permalink raw reply related
* [PATCH V1 2/2] PCI: thunder: Enable ACPI PCI controller for ThunderX pass1.x silicon version
From: Tomasz Nowicki @ 2016-11-15 9:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479201298-25494-1-git-send-email-tn@semihalf.com>
ThunderX pass1.x requires to emulate the EA headers for on-chip devices
hence it has to use custom pci_thunder_ecam_ops for accessing PCI config
space (pci-thuner-ecam.c). Add new entries to MCFG quirk array where it
can be applied while probing ACPI based PCI host controller.
ThunderX pass1.x is using the same way for accessing off-chip devices
(so-called PEM) as silicon pass-2.x so we need to add PEM quirk
entries too.
Quirk is considered for ThunderX silicon pass1.x only which is identified
via MCFG revision 2.
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
---
drivers/acpi/pci_mcfg.c | 15 +++++++++++++++
drivers/pci/host/pci-thunder-ecam.c | 2 +-
include/linux/pci-ecam.h | 3 +++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index e4e2b9b..5e16211 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -76,6 +76,21 @@ static struct mcfg_fixup mcfg_quirks[] = {
/* SoC pass2.x */
THUNDER_MCFG_QUIRK(1, 0UL),
THUNDER_MCFG_QUIRK(1, 1UL),
+
+ /* SoC pass1.x */
+ THUNDER_MCFG_QUIRK(2, 0UL),
+ THUNDER_MCFG_QUIRK(2, 1UL),
+#endif
+#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
+ /* SoC pass1.x */
+ { "CAVIUM", "THUNDERX", 2, 0, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
+ { "CAVIUM", "THUNDERX", 2, 1, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
+ { "CAVIUM", "THUNDERX", 2, 2, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
+ { "CAVIUM", "THUNDERX", 2, 3, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
+ { "CAVIUM", "THUNDERX", 2, 10, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
+ { "CAVIUM", "THUNDERX", 2, 11, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
+ { "CAVIUM", "THUNDERX", 2, 12, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
+ { "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, &pci_thunder_ecam_ops },
#endif
};
diff --git a/drivers/pci/host/pci-thunder-ecam.c b/drivers/pci/host/pci-thunder-ecam.c
index d50a3dc..b6c17e2 100644
--- a/drivers/pci/host/pci-thunder-ecam.c
+++ b/drivers/pci/host/pci-thunder-ecam.c
@@ -346,7 +346,7 @@ static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
return pci_generic_config_write(bus, devfn, where, size, val);
}
-static struct pci_ecam_ops pci_thunder_ecam_ops = {
+struct pci_ecam_ops pci_thunder_ecam_ops = {
.bus_shift = 20,
.pci_ops = {
.map_bus = pci_ecam_map_bus,
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index 3f2a98f..5a1f291 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -62,6 +62,9 @@ extern struct pci_ecam_ops pci_generic_ecam_ops;
#ifdef CONFIG_PCI_HOST_THUNDER_PEM
extern struct pci_ecam_ops pci_thunder_pem_ops;
#endif
+#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
+extern struct pci_ecam_ops pci_thunder_ecam_ops;
+#endif
/* ops for buggy ECAM that supports only 32-bit accesses */
extern struct pci_ecam_ops pci_32b_ops;
--
2.7.4
^ permalink raw reply related
* [PATCH] pinctrl: sunxi: Free configs in pinctrl_map only if it is a config map
From: Linus Walleij @ 2016-11-15 9:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111023510.14146-1-wens@csie.org>
On Fri, Nov 11, 2016 at 3:35 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> In the recently refactored sunxi pinctrl library, we are only allocating
> one set of pin configs for each pinmux setting node. When the pinctrl_map
> structure is freed, the pin configs should also be freed. However the
> code assumed the first map would contain the configs, which actually
> never happens, as the mux function map gets added first.
>
> The proper way to do this is to look through all the maps and free the
> first one whose type is actually PIN_MAP_TYPE_CONFIGS_GROUP.
>
> Also slightly expand the comment explaining this.
>
> Fixes: f233dbca6227 ("pinctrl: sunxi: Rework the pin config building code")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 1/3] pinctrl: sunxi: Fix PIN_CONFIG_BIAS_PULL_{DOWN, UP} argument
From: Linus Walleij @ 2016-11-15 9:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111024455.16883-2-wens@csie.org>
On Fri, Nov 11, 2016 at 3:44 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> According to pinconf-generic.h, the argument for
> PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled
> with a pull up/down resistor, zero if it is directly connected
> to VDD or ground.
>
> Since Allwinner hardware uses a weak pull resistor internally,
> the argument should be 1.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v3 1/3] pinctrl: sunxi: Fix PIN_CONFIG_BIAS_PULL_{DOWN, UP} argument
From: Linus Walleij @ 2016-11-15 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111095036.11803-2-wens@csie.org>
On Fri, Nov 11, 2016 at 10:50 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> According to pinconf-generic.h, the argument for
> PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled
> with a pull up/down resistor, zero if it is directly connected
> to VDD or ground.
>
> Since Allwinner hardware uses a weak pull resistor internally,
> the argument should be 1.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Applied this v3 rather than the v2.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v3 2/3] pinctrl: sunxi: Add support for fetching pinconf settings from hardware
From: Linus Walleij @ 2016-11-15 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111095036.11803-3-wens@csie.org>
On Fri, Nov 11, 2016 at 10:50 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> The sunxi pinctrl driver only caches whatever pinconf setting was last
> set on a given pingroup. This is not particularly helpful, nor is it
> correct.
>
> Fix this by actually reading the hardware registers and returning
> the correct results or error codes. Also filter out unsupported
> pinconf settings. Since this driver has a peculiar setup of 1 pin
> per group, we can support both pin and pingroup pinconf setting
> read back with the same code. The sunxi_pconf_reg helper and code
> structure is inspired by pinctrl-msm.
>
> With this done we can also claim to support generic pinconf, by
> setting .is_generic = true in pinconf_ops.
>
> Also remove the cached config value. The behavior of this was never
> correct, as it only cached 1 setting instead of all of them. Since
> we can now read back settings directly from the hardware, it is no
> longer required.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v3 3/3] pinctrl: sunxi: Make sunxi_pconf_group_set use sunxi_pconf_reg helper
From: Linus Walleij @ 2016-11-15 9:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111095036.11803-4-wens@csie.org>
On Fri, Nov 11, 2016 at 10:50 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> The sunxi_pconf_reg helper introduced in the last patch gives us the
> chance to rework sunxi_pconf_group_set to have it match the structure
> of sunxi_pconf_(group_)get and make it easier to understand.
>
> For each config to set, it:
>
> 1. checks if the parameter is supported.
> 2. checks if the argument is within limits.
> 3. converts argument to the register value.
> 4. writes to the register with spinlock held.
>
> As a result the function now blocks unsupported config parameters,
> instead of silently ignoring them.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168
From: Marc Zyngier @ 2016-11-15 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479193220-6693-1-git-send-email-gakula@caviumnetworks.com>
On 15/11/16 07:00, Geetha sowjanya wrote:
> From: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
>
> This patch implements Cavium ThunderX erratum 28168.
>
> PCI requires stores complete in order. Due to erratum #28168
> PCI-inbound MSI-X store to the interrupt controller are delivered
> to the interrupt controller before older PCI-inbound memory stores
> are committed.
> Doing a sync on SMMU will make sure all prior data transfers are
> completed before invoking ISR.
>
> Signed-off-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>
> ---
> arch/arm64/Kconfig | 11 +++++++++++
> arch/arm64/Kconfig.platforms | 1 +
> arch/arm64/include/asm/cpufeature.h | 3 ++-
> arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++
> drivers/iommu/arm-smmu.c | 24 ++++++++++++++++++++++++
> drivers/irqchip/irq-gic-common.h | 1 +
> drivers/irqchip/irq-gic-v3.c | 19 +++++++++++++++++++
> 7 files changed, 74 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 30398db..751972c 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -474,6 +474,17 @@ config CAVIUM_ERRATUM_27456
>
> If unsure, say Y.
>
> +config CAVIUM_ERRATUM_28168
> + bool "Cavium erratum 28168: Make sure DMA data transfer is done before MSIX"
> + depends on ARCH_THUNDER && ARM64
> + default y
> + help
> + Due to erratum #28168 PCI-inbound MSI-X store to the interrupt
> + controller are delivered to the interrupt controller before older
> + PCI-inbound memory stores are committed. Doing a sync on SMMU
> + will make sure all prior data transfers are done before invoking ISR.
> +
> + If unsure, say Y.
Where is the entry in Documentation/arm64/silicon-errata.txt?
> endmenu
>
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index cfbdf02..2ac4ac6 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -185,6 +185,7 @@ config ARCH_SPRD
>
> config ARCH_THUNDER
> bool "Cavium Inc. Thunder SoC Family"
> + select IRQ_PREFLOW_FASTEOI
> help
> This enables support for Cavium's Thunder Family of SoCs.
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index 758d74f..821fc3c 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -40,8 +40,9 @@
> #define ARM64_HAS_32BIT_EL0 13
> #define ARM64_HYP_OFFSET_LOW 14
> #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
> +#define ARM64_WORKAROUND_CAVIUM_28168 16
>
> -#define ARM64_NCAPS 16
> +#define ARM64_NCAPS 17
>
> #ifndef __ASSEMBLY__
>
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 0150394..0841a12 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -122,6 +122,22 @@ static void cpu_enable_trap_ctr_access(void *__unused)
> MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
> },
> #endif
> +#ifdef CONFIG_CAVIUM_ERRATUM_28168
> + {
> + /* Cavium ThunderX, T88 pass 1.x - 2.1 */
> + .desc = "Cavium erratum 28168",
> + .capability = ARM64_WORKAROUND_CAVIUM_28168,
> + MIDR_RANGE(MIDR_THUNDERX, 0x00,
> + (1 << MIDR_VARIANT_SHIFT) | 1),
> + },
> + {
> + /* Cavium ThunderX, T81 pass 1.0 */
> + .desc = "Cavium erratum 28168",
> + .capability = ARM64_WORKAROUND_CAVIUM_28168,
> + MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
> + },
> +#endif
How is that a CPU bug? Shouldn't that be keyed on the SMMU version or
the ITs version?
> +
> {
> .desc = "Mismatched cache line size",
> .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index c841eb7..1b4555c 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -570,6 +570,30 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
> }
> }
>
> +/*
> + * Cavium ThunderX erratum 28168
> + *
> + * Due to erratum #28168 PCI-inbound MSI-X store to the interrupt
> + * controller are delivered to the interrupt controller before older
> + * PCI-inbound memory stores are committed. Doing a sync on SMMU
> + * will make sure all prior data transfers are completed before
> + * invoking ISR.
> + *
> + */
> +void cavium_arm_smmu_tlb_sync(struct device *dev)
> +{
> + struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> + struct arm_smmu_device *smmu;
> +
> + smmu = fwspec_smmu(fwspec);
> + if (!smmu)
> + return;
> + __arm_smmu_tlb_sync(smmu);
> +
> +}
> +EXPORT_SYMBOL(cavium_arm_smmu_tlb_sync);
Why does this need to be exported? The only user can only be built-in.
> +
> +
> static void arm_smmu_tlb_sync(void *cookie)
> {
> struct arm_smmu_domain *smmu_domain = cookie;
> diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h
> index 205e5fd..4e88f55 100644
> --- a/drivers/irqchip/irq-gic-common.h
> +++ b/drivers/irqchip/irq-gic-common.h
> @@ -38,4 +38,5 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
>
> void gic_set_kvm_info(const struct gic_kvm_info *info);
>
> +void cavium_arm_smmu_tlb_sync(struct device *dev);
Why should this be visible to GICv2 as well? I have the ugly feeling
this should stay private to the SMMU code and that a more standard
mechanism should be used... Robin, is there anything else we could
piggy-back on?
> #endif /* _IRQ_GIC_COMMON_H */
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index 19d642e..723cebe 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -28,6 +28,8 @@
> #include <linux/of_irq.h>
> #include <linux/percpu.h>
> #include <linux/slab.h>
> +#include <linux/msi.h>
> +#include <linux/pci.h>
>
> #include <linux/irqchip.h>
> #include <linux/irqchip/arm-gic-common.h>
> @@ -736,6 +738,20 @@ static inline void gic_cpu_pm_init(void) { }
>
> #define GIC_ID_NR (1U << gic_data.rdists.id_bits)
>
> +/*
> + * Due to #28168 erratum in ThunderX,
> + * we need to make sure DMA data transfer is done before MSIX.
> + */
> +static void cavium_irq_perflow_handler(struct irq_data *data)
> +{
> + struct pci_dev *pdev;
> +
> + pdev = msi_desc_to_pci_dev(irq_data_get_msi_desc(data));
What happens if this is not a PCI device?
> + if ((pdev->vendor != 0x177d) &&
> + ((pdev->device & 0xA000) != 0xA000))
> + cavium_arm_smmu_tlb_sync(&pdev->dev);
I've asked that before. What makes Cavium devices so special that they
are not sensitive to this bug?
> +}
> +
> static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
> irq_hw_number_t hw)
> {
> @@ -773,6 +789,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
> return -EPERM;
> irq_domain_set_info(d, irq, hw, chip, d->host_data,
> handle_fasteoi_irq, NULL, NULL);
> + if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_28168))
> + __irq_set_preflow_handler(irq,
> + cavium_irq_perflow_handler);
What happens if SMMUv2 is not compiled in? Also, since this only affects
LPI signaling, why is this in the core GICv3 code and not in the ITS.
And more specifically, in the PCI part of the ITS, since you seem to
exclusively consider PCI?
> }
>
> return 0;
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH 1/2] ARM: davinci: PM: rework init, support DT platforms
From: Sekhar Nori @ 2016-11-15 9:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114230441.356-2-khilman@baylibre.com>
Hi Kevin,
Looks good to me overall, I have some minor comments.
On Tuesday 15 November 2016 04:34 AM, Kevin Hilman wrote:
> Remove fake platform device used for PM init. Move pdata values which
> are common across all current platforms into pm.c.
>
> Also add PM support for DT platforms (vi da8xx-dt.c)
Can you please separate out PM enabling on DT platform to a separate
patch? Its a small change, but it will be nice to separate it from rest
of the cleanup.
> diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
> index f9f9713aacdd..3d7a13789661 100644
> --- a/arch/arm/mach-davinci/include/mach/da8xx.h
> +++ b/arch/arm/mach-davinci/include/mach/da8xx.h
> @@ -101,7 +101,6 @@ int da8xx_register_gpio(void *pdata);
> int da850_register_cpufreq(char *async_clk);
> int da8xx_register_cpuidle(void);
> void __iomem *da8xx_get_mem_ctlr(void);
> -int da850_register_pm(struct platform_device *pdev);
> int da850_register_sata(unsigned long refclkpn);
> int da850_register_vpif(void);
> int da850_register_vpif_display
> diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
> index 8929569b1f8a..fc6a5710b3fa 100644
> --- a/arch/arm/mach-davinci/pm.c
> +++ b/arch/arm/mach-davinci/pm.c
> @@ -23,13 +23,18 @@
> #include <mach/da8xx.h>
> #include "sram.h"
> #include <mach/pm.h>
> +#include <mach/mux.h>
Can you please add the mux.h inclusion above pm.h? Looks like the sram.h
inclusion is out of place already, but since you are touching this part,
can you please move it below along with rest of the local includes.
I see that linux/ includes are not sorted as well, but lets keep that
aside until someone needs to touch them.
> #include "clock.h"
> +#include "psc.h"
>
> +#define DA850_PLL1_BASE 0x01e1a000
> #define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
> +#define DEEPSLEEP_SLEEPCOUNT 128
>
> static void (*davinci_sram_suspend) (struct davinci_pm_config *);
> -static struct davinci_pm_config *pdata;
> +static struct davinci_pm_config pm_config;
> +static struct davinci_pm_config *pdata = &pm_config;
>
> static void davinci_sram_push(void *dest, void *src, unsigned int size)
> {
> @@ -117,17 +122,38 @@ static const struct platform_suspend_ops davinci_pm_ops = {
> .valid = suspend_valid_only_mem,
> };
>
> -static int __init davinci_pm_probe(struct platform_device *pdev)
> +int __init davinci_pm_init(void)
> {
> - pdata = pdev->dev.platform_data;
> - if (!pdata) {
> - dev_err(&pdev->dev, "cannot get platform data\n");
> - return -ENOENT;
> + int ret;
> +
> + ret = davinci_cfg_reg(DA850_RTC_ALARM);
> + if (ret)
> + return ret;
> +
> + pdata->sleepcount = DEEPSLEEP_SLEEPCOUNT;
> + pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
> + pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
> + pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
Some of these could be statically initialized in pm_config. Can you
please move the constants to static initialization.
Thanks,
Sekhar
^ permalink raw reply
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