* ILP32 for ARM64 - testing with lmbench
From: Zhangjian (Bamvor) @ 2016-11-17 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <266952F2-53F5-4D5E-83F0-6C8203092F67@linaro.org>
Hi, Maxim
On 2016/11/17 13:02, Maxim Kuvyrkov wrote:
> Hi Bamvor,
>
> I'm surprised that you see this much difference from ILP32 patches on SPEC CPU2006int at all. The SPEC CPU2006 benchmarks spend almost no time in the kernel syscalls. I can imagine memory, TLB, and cache handling in the kernel could affect CPU2006 benchmarks. Do ILP32 patches touch code in those areas?
>
> Other than that, it would be interesting to check what the variance is between the 3 iterations of benchmark runs. Could you check what relative standard deviation is between the 3 iterations -- (STDEV(RUN1, RUN2, RUN3) / RUNselected)?
>
> For reference, in my [non-ILP32] benchmarking I see 1.1% for 401.bzip2, 0.8% for 429.mcf, 0.2% for 456.hmmer, and 0.1% for 462.libquantum.
Here is my result:
ILP32_merged ILP32_unmerged
401.bzip2 0.31% 0.26%
429.mcf 1.61% 1.36%
456.hmmer 1.37% 1.57%
462.libquantum 0.29% 0.28%
Regards
Bamvor
>
> --
> Maxim Kuvyrkov
> www.linaro.org
>
>
>
>> On Nov 17, 2016, at 7:28 AM, Zhangjian (Bamvor) <bamvor.zhangjian@huawei.com> wrote:
>>
>> Hi, all
>>
>> I test specint of aarch64 LP64 when aarch32 el0 disable/enabled respectively
>> and compare with ILP32 unmerged kernel(4.8-rc6) in our arm64 board. I found
>> that difference(ILP32 disabled/ILP32 unmerged) is bigger when aarch32 el0 is
>> enabled, compare with aarch32 el0 disabled kernel. And bzip2, mcg, hmmer,
>> libquantum are the top four differences[1]. Note that bigger is better in
>> specint test.
>>
>> In order to make sure the above results, I retest these four testcases in
>> reportable way(reference the command in the end). The result[2] show that
>> libquantum decrease -2.09% after ILP32 enabled and aarch32 on. I think it is in
>> significant.
>>
>> The result of lmbench is not stable in my board. I plan to dig it later.
>>
>> [1] The following test result is tested through --size=ref --iterations=3.
>> 1.1 Test when aarch32_el0 is enabled.
>> ILP32 disabled base line
>> 400.perlbench 100.00% 100%
>> 401.bzip2 99.35% 100%
>> 403.gcc 100.26% 100%
>> 429.mcf 102.75% 100%
>> 445.gobmk 100.00% 100%
>> 456.hmmer 95.66% 100%
>> 458.sjeng 100.00% 100%
>> 462.libquantum 100.00% 100%
>> 471.omnetpp 100.59% 100%
>> 473.astar 99.66% 100%
>> 483.xalancbmk 99.10% 100%
>>
>> 1.2 Test when aarch32_el0 is disabled
>> ILP32 disabled base line
>> 400.perlbench 100.22% 100%
>> 401.bzip2 100.95% 100%
>> 403.gcc 100.20% 100%
>> 429.mcf 100.76% 100%
>> 445.gobmk 100.36% 100%
>> 456.hmmer 97.94% 100%
>> 458.sjeng 99.73% 100%
>> 462.libquantum 98.72% 100%
>> 471.omnetpp 100.86% 100%
>> 473.astar 99.15% 100%
>> 483.xalancbmk 100.08% 100%
>>
>> [2] The following test result is tested through: runspec --config=my.cfg --size=test,train,ref --noreportable --tune=base,peak --iterations=3 bzip2 mcf hmmer libquantum
>> 2.1 Test when aarch32_el0 is enabled.
>> ILP32_enabled base line
>> 401.bzip2 100.82% 100%
>> 429.mcf 100.18% 100%
>> 456.hmmer 99.64% 100%
>> 462.libquantum 97.91% 100%
>>
>> Regards
>>
>> Bamvor
>>
>> On 2016/10/28 20:46, Yury Norov wrote:
>>> [Add Steve Ellcey, thanks for testing on ThunderX]
>>>
>>> Lmbench-3.0-a9 testing is performed on ThunderX machine to check that
>>> ILP32 series does not add performance regressions for LP64. Test
>>> summary is in the table below. Our measurements doesn't show
>>> significant performance regression of LP64 if ILP32 code is merged,
>>> both enabled or disabled.
>>>
>>> ILP32 enabled ILP32 disabled Standard Kernel
>>> null syscall 0.1066 0.1121 0.1121
>>> 95.09% 100.00%
>>>
>>> stat 1.3947 1.3814 1.3864
>>> 100.60% 99.64%
>>>
>>> fstat 0.4459 0.4344 0.4524
>>> 98.56% 96.02%
>>>
>>> open/close 4.0606 4.0411 4.0453
>>> 100.38% 99.90%
>>>
>>> read 0.4819 0.5014 0.5014
>>> 96.11% 100.00%
>>>
>>> Tested with linux 4.8 because 4.9-rc1 is not fixed yet for ThunderX.
>>> Other system details below.
>>>
>>> Yury.
>>>
>>> ubuntu at crb6:~$ uname -a
>>> Linux crb6 4.8.0+ #3 SMP Thu Oct 27 11:01:32 PDT 2016 aarch64 aarch64 aarch64 GNU/Linux
>>>
>>> ubuntu at crb6:~$ cat /proc/meminfo
>>> MemTotal: 132011948 kB
>>> MemFree: 131442672 kB
>>> MemAvailable: 130695764 kB
>>> Buffers: 15696 kB
>>> Cached: 88088 kB
>>> SwapCached: 0 kB
>>> Active: 82760 kB
>>> Inactive: 41336 kB
>>> Active(anon): 20880 kB
>>> Inactive(anon): 8576 kB
>>> Active(file): 61880 kB
>>> Inactive(file): 32760 kB
>>> Unevictable: 0 kB
>>> Mlocked: 0 kB
>>> SwapTotal: 128920572 kB
>>> SwapFree: 128920572 kB
>>> Dirty: 0 kB
>>> Writeback: 0 kB
>>> AnonPages: 20544 kB
>>> Mapped: 19780 kB
>>> Shmem: 9060 kB
>>> Slab: 78804 kB
>>> SReclaimable: 27372 kB
>>> SUnreclaim: 51432 kB
>>> KernelStack: 8336 kB
>>> PageTables: 820 kB
>>> NFS_Unstable: 0 kB
>>> Bounce: 0 kB
>>> WritebackTmp: 0 kB
>>> CommitLimit: 194926544 kB
>>> Committed_AS: 256324 kB
>>> VmallocTotal: 135290290112 kB
>>> VmallocUsed: 0 kB
>>> VmallocChunk: 0 kB
>>> AnonHugePages: 0 kB
>>> ShmemHugePages: 0 kB
>>> ShmemPmdMapped: 0 kB
>>> CmaTotal: 0 kB
>>> CmaFree: 0 kB
>>> HugePages_Total: 0
>>> HugePages_Free: 0
>>> HugePages_Rsvd: 0
>>> HugePages_Surp: 0
>>> Hugepagesize: 2048 kB
>>>
>>> ubuntu at crb6:~$ cat /proc/cpuinfo
>>> processor : 0
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 1
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 2
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 3
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 4
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 5
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 6
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 7
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 8
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 9
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 10
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 11
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 12
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 13
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 14
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 15
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 16
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 17
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 18
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 19
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 20
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 21
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 22
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 23
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 24
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 25
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 26
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 27
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 28
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 29
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 30
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 31
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 32
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 33
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 34
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 35
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 36
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 37
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 38
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 39
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 40
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 41
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 42
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 43
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 44
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 45
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 46
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>> processor : 47
>>> BogoMIPS : 200.00
>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
>>> CPU implementer : 0x43
>>> CPU architecture: 8
>>> CPU variant : 0x1
>>> CPU part : 0x0a1
>>> CPU revision : 0
>>>
>>
>
^ permalink raw reply
* [PATCH v4 1/2] drm/bridge: dumb-vga-dac: Support a VDD regulator supply
From: Archit Taneja @ 2016-11-17 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116154232.872-2-wens@csie.org>
Hi,
Thanks for the patch.
On 11/16/2016 09:12 PM, Chen-Yu Tsai wrote:
> Some dumb VGA DACs are active components which require external power.
> Add support for specifying a regulator as its power supply.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/display/bridge/dumb-vga-dac.txt | 2 ++
> drivers/gpu/drm/bridge/dumb-vga-dac.c | 35 ++++++++++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
> index 003bc246a270..164cbb15f04c 100644
> --- a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
> +++ b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
> @@ -16,6 +16,8 @@ graph bindings specified in Documentation/devicetree/bindings/graph.txt.
> - Video port 0 for RGB input
> - Video port 1 for VGA output
>
> +Optional properties:
> +- vdd-supply: Power supply for DAC
>
> Example
> -------
> diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c b/drivers/gpu/drm/bridge/dumb-vga-dac.c
> index afec232185a7..15b549f94307 100644
> --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
> +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
> @@ -12,6 +12,7 @@
>
> #include <linux/module.h>
> #include <linux/of_graph.h>
> +#include <linux/regulator/consumer.h>
>
> #include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> @@ -23,6 +24,7 @@ struct dumb_vga {
> struct drm_connector connector;
>
> struct i2c_adapter *ddc;
> + struct regulator *vdd;
> };
>
> static inline struct dumb_vga *
> @@ -124,8 +126,32 @@ static int dumb_vga_attach(struct drm_bridge *bridge)
> return 0;
> }
>
> +static void dumb_vga_enable(struct drm_bridge *bridge)
> +{
> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
> + int ret = 0;
> +
> + if (vga->vdd)
> + ret = regulator_enable(vga->vdd);
> +
> + if (ret) {
> + DRM_ERROR("Failed to enable vdd regulator: %d\n", ret);
> + return;
We don't need this return for now. If you're okay with it, can I fix this
and queue to misc?
Thanks,
Archit
> + }
> +}
> +
> +static void dumb_vga_disable(struct drm_bridge *bridge)
> +{
> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
> +
> + if (vga->vdd)
> + regulator_disable(vga->vdd);
> +}
> +
> static const struct drm_bridge_funcs dumb_vga_bridge_funcs = {
> .attach = dumb_vga_attach,
> + .enable = dumb_vga_enable,
> + .disable = dumb_vga_disable,
> };
>
> static struct i2c_adapter *dumb_vga_retrieve_ddc(struct device *dev)
> @@ -169,6 +195,15 @@ static int dumb_vga_probe(struct platform_device *pdev)
> return -ENOMEM;
> platform_set_drvdata(pdev, vga);
>
> + vga->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
> + if (IS_ERR(vga->vdd)) {
> + ret = PTR_ERR(vga->vdd);
> + if (ret == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> + vga->vdd = NULL;
> + dev_dbg(&pdev->dev, "No vdd regulator found: %d\n", ret);
> + }
> +
> vga->ddc = dumb_vga_retrieve_ddc(&pdev->dev);
> if (IS_ERR(vga->ddc)) {
> if (PTR_ERR(vga->ddc) == -ENODEV) {
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v4 1/2] drm/bridge: dumb-vga-dac: Support a VDD regulator supply
From: Chen-Yu Tsai @ 2016-11-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <31b8b5b9-9621-286a-7649-cc999ab020da@codeaurora.org>
On Thu, Nov 17, 2016 at 3:48 PM, Archit Taneja <architt@codeaurora.org> wrote:
> Hi,
>
> Thanks for the patch.
>
>
> On 11/16/2016 09:12 PM, Chen-Yu Tsai wrote:
>>
>> Some dumb VGA DACs are active components which require external power.
>> Add support for specifying a regulator as its power supply.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> Acked-by: Rob Herring <robh@kernel.org>
>> ---
>> .../bindings/display/bridge/dumb-vga-dac.txt | 2 ++
>> drivers/gpu/drm/bridge/dumb-vga-dac.c | 35
>> ++++++++++++++++++++++
>> 2 files changed, 37 insertions(+)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>> b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>> index 003bc246a270..164cbb15f04c 100644
>> --- a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>> +++ b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>> @@ -16,6 +16,8 @@ graph bindings specified in
>> Documentation/devicetree/bindings/graph.txt.
>> - Video port 0 for RGB input
>> - Video port 1 for VGA output
>>
>> +Optional properties:
>> +- vdd-supply: Power supply for DAC
>>
>> Example
>> -------
>> diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c
>> b/drivers/gpu/drm/bridge/dumb-vga-dac.c
>> index afec232185a7..15b549f94307 100644
>> --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
>> +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
>> @@ -12,6 +12,7 @@
>>
>> #include <linux/module.h>
>> #include <linux/of_graph.h>
>> +#include <linux/regulator/consumer.h>
>>
>> #include <drm/drmP.h>
>> #include <drm/drm_atomic_helper.h>
>> @@ -23,6 +24,7 @@ struct dumb_vga {
>> struct drm_connector connector;
>>
>> struct i2c_adapter *ddc;
>> + struct regulator *vdd;
>> };
>>
>> static inline struct dumb_vga *
>> @@ -124,8 +126,32 @@ static int dumb_vga_attach(struct drm_bridge *bridge)
>> return 0;
>> }
>>
>> +static void dumb_vga_enable(struct drm_bridge *bridge)
>> +{
>> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
>> + int ret = 0;
>> +
>> + if (vga->vdd)
>> + ret = regulator_enable(vga->vdd);
>> +
>> + if (ret) {
>> + DRM_ERROR("Failed to enable vdd regulator: %d\n", ret);
>> + return;
>
>
> We don't need this return for now. If you're okay with it, can I fix this
> and queue to misc?
Yes, please!
Thanks
ChenYu
>
> Thanks,
> Archit
>
>
>> + }
>> +}
>> +
>> +static void dumb_vga_disable(struct drm_bridge *bridge)
>> +{
>> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
>> +
>> + if (vga->vdd)
>> + regulator_disable(vga->vdd);
>> +}
>> +
>> static const struct drm_bridge_funcs dumb_vga_bridge_funcs = {
>> .attach = dumb_vga_attach,
>> + .enable = dumb_vga_enable,
>> + .disable = dumb_vga_disable,
>> };
>>
>> static struct i2c_adapter *dumb_vga_retrieve_ddc(struct device *dev)
>> @@ -169,6 +195,15 @@ static int dumb_vga_probe(struct platform_device
>> *pdev)
>> return -ENOMEM;
>> platform_set_drvdata(pdev, vga);
>>
>> + vga->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
>> + if (IS_ERR(vga->vdd)) {
>> + ret = PTR_ERR(vga->vdd);
>> + if (ret == -EPROBE_DEFER)
>> + return -EPROBE_DEFER;
>> + vga->vdd = NULL;
>> + dev_dbg(&pdev->dev, "No vdd regulator found: %d\n", ret);
>> + }
>> +
>> vga->ddc = dumb_vga_retrieve_ddc(&pdev->dev);
>> if (IS_ERR(vga->ddc)) {
>> if (PTR_ERR(vga->ddc) == -ENODEV) {
>>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 1/2] dt-bindings: ahci-fsl-qoriq: added explanation for reg-names
From: yuantian.tang at nxp.com @ 2016-11-17 7:59 UTC (permalink / raw)
To: linux-arm-kernel
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Added explanation for reg-names to make it more clear.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
index fc33ca0..80cf10c 100644
--- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -10,6 +10,8 @@ Required properties:
Optional properties:
- dma-coherent: Enable AHCI coherent DMA operation.
- reg-names: register area names when there are more than 1 register area.
+ example: 'ahci' is for sata controller register.
+ 'sata-ecc' is for sata ecc register.
Examples:
sata at 3200000 {
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: updated sata node on ls1046a dts
From: yuantian.tang at nxp.com @ 2016-11-17 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479369560-9188-1-git-send-email-yuantian.tang@nxp.com>
From: Tang Yuantian <Yuantian.Tang@nxp.com>
On ls1046a soc, sata ecc should be disabled. So added sata ecc
register address so that driver can get this information.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..88aaaf1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -507,7 +507,9 @@
sata: sata at 3200000 {
compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH] crypto: sun4i-ss: support the Security System PRNG
From: Corentin Labbe @ 2016-11-17 8:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANc+2y63p1b5ATDY0oU4nLckk9CJhSs3CXGHy=NwoXn_awP9aA@mail.gmail.com>
On Tue, Oct 18, 2016 at 09:39:17PM +0530, PrasannaKumar Muralidharan wrote:
> Hi Corentin,
>
> I have a few minor comments.
>
> On 18 October 2016 at 18:04, Corentin Labbe <clabbe.montjoie@gmail.com> wrote:
> > From: LABBE Corentin <clabbe.montjoie@gmail.com>
> >
> > The Security System have a PRNG.
> > This patch add support for it as an hwrng.
> >
> > Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> > ---
> > drivers/crypto/Kconfig | 8 ++++
> > drivers/crypto/sunxi-ss/Makefile | 1 +
> > drivers/crypto/sunxi-ss/sun4i-ss-core.c | 14 +++++++
> > drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c | 70 ++++++++++++++++++++++++++++++++
> > drivers/crypto/sunxi-ss/sun4i-ss.h | 8 ++++
> > 5 files changed, 101 insertions(+)
> > create mode 100644 drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c
> >
> > diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> > index 4d2b81f..38f7aca 100644
> > --- a/drivers/crypto/Kconfig
> > +++ b/drivers/crypto/Kconfig
> > @@ -538,6 +538,14 @@ config CRYPTO_DEV_SUN4I_SS
> > To compile this driver as a module, choose M here: the module
> > will be called sun4i-ss.
> >
> > +config CRYPTO_DEV_SUN4I_SS_PRNG
> > + bool "Support for Allwinner Security System PRNG"
> > + depends on CRYPTO_DEV_SUN4I_SS
> > + select HW_RANDOM
> > + help
> > + This driver provides kernel-side support for the Pseudo-Random
> > + Number Generator found in the Security System.
> > +
> > config CRYPTO_DEV_ROCKCHIP
> > tristate "Rockchip's Cryptographic Engine driver"
> > depends on OF && ARCH_ROCKCHIP
> > diff --git a/drivers/crypto/sunxi-ss/Makefile b/drivers/crypto/sunxi-ss/Makefile
> > index 8f4c7a2..ca049ee 100644
> > --- a/drivers/crypto/sunxi-ss/Makefile
> > +++ b/drivers/crypto/sunxi-ss/Makefile
> > @@ -1,2 +1,3 @@
> > obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sun4i-ss.o
> > sun4i-ss-y += sun4i-ss-core.o sun4i-ss-hash.o sun4i-ss-cipher.o
> > +sun4i-ss-$(CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG) += sun4i-ss-hwrng.o
> > diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> > index 3ac6c6c..fa739de 100644
> > --- a/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> > +++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> > @@ -359,6 +359,16 @@ static int sun4i_ss_probe(struct platform_device *pdev)
> > }
> > }
> > platform_set_drvdata(pdev, ss);
> > +
> > +#ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG
> > + /* Voluntarily made the PRNG optional */
> > + err = sun4i_ss_hwrng_register(&ss->hwrng);
> > + if (!err)
> > + dev_info(ss->dev, "sun4i-ss PRNG loaded");
> > + else
> > + dev_err(ss->dev, "sun4i-ss PRNG failed");
> > +#endif
> > +
> > return 0;
> > error_alg:
> > i--;
> > @@ -386,6 +396,10 @@ static int sun4i_ss_remove(struct platform_device *pdev)
> > int i;
> > struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
> >
> > +#ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG
> > + sun4i_ss_hwrng_remove(&ss->hwrng);
> > +#endif
> > +
> > for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
> > switch (ss_algs[i].type) {
> > case CRYPTO_ALG_TYPE_ABLKCIPHER:
> > diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c b/drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c
> > new file mode 100644
> > index 0000000..95fadb7
> > --- /dev/null
> > +++ b/drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c
> > @@ -0,0 +1,70 @@
> > +#include "sun4i-ss.h"
> > +
> > +static int sun4i_ss_hwrng_init(struct hwrng *hwrng)
> > +{
> > + struct sun4i_ss_ctx *ss;
> > +
> > + ss = container_of(hwrng, struct sun4i_ss_ctx, hwrng);
> > + get_random_bytes(ss->seed, SS_SEED_LEN);
> > +
> > + return 0;
> > +}
> > +
> > +static int sun4i_ss_hwrng_read(struct hwrng *hwrng, void *buf,
> > + size_t max, bool wait)
> > +{
> > + int i;
> > + u32 v;
> > + u32 *data = buf;
> > + const u32 mode = SS_OP_PRNG | SS_PRNG_CONTINUE | SS_ENABLED;
> > + size_t len;
> > + struct sun4i_ss_ctx *ss;
> > +
> > + ss = container_of(hwrng, struct sun4i_ss_ctx, hwrng);
> > + len = min_t(size_t, SS_DATA_LEN, max);
> > +
> > + spin_lock_bh(&ss->slock);
>
> Is spin_lock_bh really required here? I could see it is being used in
> sun4i-ss-hash.c but could not find any comment/info about the need.
>
No for sun4i-ss-hwrng it seems not required and work perfecly without _bh
> > + writel(mode, ss->base + SS_CTL);
> > +
> > + /* write the seed */
> > + for (i = 0; i < SS_SEED_LEN / 4; i++)
> > + writel(ss->seed[i], ss->base + SS_KEY0 + i * 4);
> > + writel(mode | SS_PRNG_START, ss->base + SS_CTL);
> > +
> > + /* Read the random data */
> > + readsl(ss->base + SS_TXFIFO, data, len / 4);
> > +
> > + if (len % 4 > 0) {
> > + v = readl(ss->base + SS_TXFIFO);
> > + memcpy(data + len / 4, &v, len % 4);
> > + }
>
> hwrng core asks for "rng_buffer_size()" of data which is a multiple of
> 4. So len % 4 will be 0. I think the above check is not required. Feel
> free to correct if I am wrong.
>
Agree, I removed that in v2
Thanks
Corentin Labbe
^ permalink raw reply
* [PATCH] crypto: sun4i-ss: support the Security System PRNG
From: Corentin Labbe @ 2016-11-17 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1722218.eZlGktOxfL@tauon.atsec.com>
On Tue, Oct 18, 2016 at 04:24:22PM +0200, Stephan Mueller wrote:
> Am Dienstag, 18. Oktober 2016, 14:34:27 CEST schrieb Corentin Labbe:
>
> Hi Corentin,
>
> > diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c
> > b/drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c new file mode 100644
> > index 0000000..95fadb7
> > --- /dev/null
> > +++ b/drivers/crypto/sunxi-ss/sun4i-ss-hwrng.c
> > @@ -0,0 +1,70 @@
> > +#include "sun4i-ss.h"
> > +
> > +static int sun4i_ss_hwrng_init(struct hwrng *hwrng)
> > +{
> > + struct sun4i_ss_ctx *ss;
> > +
> > + ss = container_of(hwrng, struct sun4i_ss_ctx, hwrng);
> > + get_random_bytes(ss->seed, SS_SEED_LEN);
>
> Is it wise to call get_random_bytes once in the init function and never
> thereafter?
>
> This init function may be called during boot time of the kernel at which the
> input_pool may not yet have received sufficient amounts of entropy.
>
> What about registering a callback with add_random_ready_callback and seed
> again when sufficient entropy was collected?
>
Seed again, or just do not seed (and so return -EAGAIN for read() function) until ready_callback ?
Thanks
Corentin Labbe
^ permalink raw reply
* [PATCH] crypto: sun4i-ss: support the Security System PRNG
From: Stephan Mueller @ 2016-11-17 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117080748.GB25394@Red>
Am Donnerstag, 17. November 2016, 09:07:48 CET schrieb Corentin Labbe:
Hi Corentin,
>
> Seed again, or just do not seed (and so return -EAGAIN for read() function)
> until ready_callback ?
This is your choice. But for the start sequence, you should not simply rely on
get_random_bytes.
For the DRBG in crypto/drbg.c we seed with get_random_bytes and the Jitter RNG
in case the input_pool is not fully seeded. The reseed trigger is reduced to
50 DRBG requests, i.e. after 50 requests, the DRBG again reseeds from
get_random_bytes / Jitter RNG. This is continued until the input_pool has been
sufficiently seeded (i.e. the registered callback is triggered). At that
point, another get_random_bytes call is made, the Jitter RNG is deactivated
and the reseed threshold is set to the common value.
Ciao
Stephan
^ permalink raw reply
* [PATCH] pinctrl: nomadik: split up and comments MC0 pins
From: Linus Walleij @ 2016-11-17 8:47 UTC (permalink / raw)
To: linux-arm-kernel
When debugging it helps to see exactly which pin goes where,
so make it very detailed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
index 8392083514fb..af4814479eb0 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
@@ -379,13 +379,24 @@ static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
/* Basic pins of the MMC/SD card 0 interface */
-static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
- DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
- DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
+static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, /* MC0_CMDDIR */
+ DB8500_PIN_AC1, /* MC0_DAT0DIR */
+ DB8500_PIN_AB4, /* MC0_DAT2DIR */
+ DB8500_PIN_AA3, /* MC0_FBCLK */
+ DB8500_PIN_AA4, /* MC0_CLK */
+ DB8500_PIN_AB2, /* MC0_CMD */
+ DB8500_PIN_Y4, /* MC0_DAT0 */
+ DB8500_PIN_Y2, /* MC0_DAT1 */
+ DB8500_PIN_AA2, /* MC0_DAT2 */
+ DB8500_PIN_AA1 /* MC0_DAT3 */
+};
/* Often only 4 bits are used, then these are not needed (only used for MMC) */
-static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
- DB8500_PIN_V3, DB8500_PIN_V2};
-static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 };
+static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, /* MC0_DAT4 */
+ DB8500_PIN_W3, /* MC0_DAT5 */
+ DB8500_PIN_V3, /* MC0_DAT6 */
+ DB8500_PIN_V2 /* MC0_DAT7 */
+};
+static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 }; /* MC0_DAT31DIR */
/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
--
2.7.4
^ permalink raw reply related
* [PATCH] pinctrl: sunxi: fix theoretical uninitialized variable access
From: Linus Walleij @ 2016-11-17 9:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116203358.midi7vmaqirpywtt@lukather>
On Wed, Nov 16, 2016 at 9:33 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Wed, Nov 16, 2016 at 03:18:18PM +0100, Arnd Bergmann wrote:
>> gcc warns about a way that it could use an uninitialized variable:
>>
>> drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init':
>> drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized]
>>
>> This cannot really happen except if 'freq' is UINT_MAX and 'clock' is
>> zero, and both of these are forbidden. To shut up the warning anyway,
>> this changes the logic to initialize the return code to the first
>> divider value before looking at the others.
>>
>> Fixes: 7c926492d38a ("pinctrl: sunxi: Add support for interrupt debouncing")
>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> Thanks for that patch.
>
> Just out of curiosity, which gcc gives those warnings? I have 6.2 and
> it didn't output anything..
Context: Arnd re-enabled -Werror=maybe-uninitialized
in the kernel build and this kind of stuff started to appear so
it needs to be fixed up.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 2/3] soc: rockchip: add driver handling grf setup
From: Heiko Stuebner @ 2016-11-17 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a01a1a8c-b01b-4335-b69c-bb99dec9d6d6@rock-chips.com>
Am Donnerstag, 17. November 2016, 09:38:11 CET schrieb Shawn Lin:
> Hi Heiko,
>
> ? 2016/11/16 17:58, Heiko Stuebner ??:
> > Hi Shawn,
> >
> > Am Mittwoch, 16. November 2016, 17:33:21 CET schrieb Shawn Lin:
> >> ? 2016/11/16 6:38, Heiko Stuebner ??:
> >>> The General Register Files are an area of registers containing a lot
> >>> of single-bit settings for numerous components as well full components
> >>> like usbphy control. Therefore all used components are accessed
> >>> via the syscon provided by the grf nodes or from the sub-devices
> >>> created through the simple-mfd created from the grf node.
>
> ----8<----------------
> [...]
>
> >>> + for (i = 0; i < grf_info->num_values; i++) {
> >>> + const struct rockchip_grf_value *val = &grf_info->values[i];
> >>> +
> >>> + pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
> >>> + val->desc, val->reg, val->val);
> >>> + ret = regmap_write(grf, val->reg, val->val);
> >>> + if (ret < 0)
> >>> + pr_err("%s: write to %#6x failed with %d\n",
> >>> + __func__, val->reg, ret);
> >>
> >> So, when failing to do one of the settings, should we still let it goes?
> >> Sometimes the log of postcore_initcall is easy to be neglected when
> >> people finally find problems later but the very earlier log was missing
> >> due to whatever reason like buffer limitation, etc.
> >
> > I expect errors here to be very rare. I.e. Doug thought that regmap might
> > return errors if we write outside the mapped region, which would mean
> > someone really messed up in this core component or a core-element of the
> > dts. But in general the GRF is always a mmio-regmap, so there won't be
> > any i2c/spi/ whatever errors possible.
>
> I was just thinking about the scalability that in the future some of the
> GRF settings may depend on genpd or clock even if they are only a
> mmio-regmap but they don't belong to the general pd/clock for GRF, for
> instance, some of the PHYs' or controller's cap(like emmc) settings.
>
> But, IIRC, you suggested this driver shouldn't be a catchall, and we
> now ask the drivers of controllers and phys to take over this, so I
> guess we won't put those settings here ever. :)
>
> Thanks for explaining this.
correct, it should never become a catchall as things like those phy-subdevices
that need runtime handling should definitly be handled in their respective
drivers.
So far we're also always starting with all clocks and power-domains being on,
so settings should always succeed as we're only active during early boot here.
We'll simply have to reevaluate if some new soc begins to boot with some
needed clocks/power-domains being off.
Heiko
^ permalink raw reply
* [PATCH v3 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash
From: Yao Yuan @ 2016-11-17 9:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM4PR0701MB2130273C90BE0EE615382718FEB10@AM4PR0701MB2130.eurprd07.prod.outlook.com>
On Thu, Nov 17, 2016 at 06:50:55AM +0000, Krzeminski, Marcin (Nokia - PL/Wroclaw) wrote:
> > > > On Thu, Aug 18, 2016 at 2:38 AM, Yunhui Cui <B56489@freescale.com>
> > > > wrote:
> > > > > From: Yunhui Cui <yunhui.cui@nxp.com>
> > > > >
> > > > > With the physical sectors combination, S25FS-S family flash
> > > > > requires some special operations for read/write functions.
> > > > >
> > > > > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> > > > > ---
> > > > > drivers/mtd/spi-nor/spi-nor.c | 56
> > > > > +++++++++++++++++++++++++++++++++++++++++++
> > > > > 1 file changed, 56 insertions(+)
> > > > >
> > > > > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > > > > b/drivers/mtd/spi-nor/spi-nor.c index d0fc165..495d0bb 100644
> > > > > --- a/drivers/mtd/spi-nor/spi-nor.c
> > > > > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > > > > @@ -39,6 +39,10 @@
> > > > >
> > > > > #define SPI_NOR_MAX_ID_LEN 6
> > > > > #define SPI_NOR_MAX_ADDR_WIDTH 4
> > > > > +/* Added for S25FS-S family flash */
> > > > > +#define SPINOR_CONFIG_REG3_OFFSET 0x800004
> > > > > +#define CR3V_4KB_ERASE_UNABLE 0x8 #define
> > > > > +SPINOR_S25FS_FAMILY_EXT_JEDEC 0x81
> > > > >
> > > > > struct flash_info {
> > > > > char *name;
> > > > > @@ -78,6 +82,7 @@ struct flash_info { };
> > > > >
> > > > > #define JEDEC_MFR(info) ((info)->id[0])
> > > > > +#define EXT_JEDEC(info) ((info)->id[5])
> > > > >
> > > > > static const struct flash_info *spi_nor_match_id(const char
> > > > > *name);
> > > > >
> > > > > @@ -899,6 +904,7 @@ static const struct flash_info spi_nor_ids[] = {
> > > > > */
> > > > > { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64,
> > > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > > > > { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128,
> > > > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > > > > + { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024,
> > > > > + 512, 0)},
> > > > > { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
> > > > > { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512,
> > > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > > > > { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256,
> > > > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, @@ -1036,6
> > +1042,50
> > > > @@ static const struct flash_info *spi_nor_read_id(struct spi_nor
> > > > *nor)
> > > > > return ERR_PTR(-ENODEV); }
> > > > >
> > > > > +/*
> > > > > + * The S25FS-S family physical sectors may be configured as a
> > > > > + * hybrid combination of eight 4-kB parameter sectors
> > > > > + * at the top or bottom of the address space with all
> > > > > + * but one of the remaining sectors being uniform size.
> > > > > + * The Parameter Sector Erase commands (20h or 21h) must
> > > > > + * be used to erase the 4-kB parameter sectors individually.
> > > > > + * The Sector (uniform sector) Erase commands (D8h or DCh)
> > > > > + * must be used to erase any of the remaining
> > > > > + * sectors, including the portion of highest or lowest address
> > > > > + * sector that is not overlaid by the parameter sectors.
> > > > > + * The uniform sector erase command has no effect on parameter
> > > > sectors.
> > > > > + */
> > > > > +static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor) {
> > > > > + u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
> > > > > + u8 cr3v = 0x0;
> > > > > + int ret = 0x0;
> > > > > +
> > > > > + nor->cmd_buf[2] = cr3v_addr >> 16;
> > > > > + nor->cmd_buf[1] = cr3v_addr >> 8;
> > > > > + nor->cmd_buf[0] = cr3v_addr >> 0;
> > > > > +
> > > > > + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + if (cr3v & CR3V_4KB_ERASE_UNABLE)
> > > > > + return 0;
> > > > > + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + cr3v = CR3V_4KB_ERASE_UNABLE;
> > > > > + nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
> > > > > + nor->write(nor, cr3v_addr, 1, &cr3v);
> > > > > +
> > > > > + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
> > > > > + return -EPERM;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
> > > > > size_t *retlen, u_char *buf) { @@
> > > > > -1361,6
> > > > > +1411,12 @@ int spi_nor_scan(struct spi_nor *nor, const char
> > > > > +*name,
> > > > enum read_mode mode)
> > > > > spi_nor_wait_till_ready(nor);
> > > > > }
> > > > >
> > > > > + if (EXT_JEDEC(info) == SPINOR_S25FS_FAMILY_EXT_JEDEC) {
> > > > > + ret = spansion_s25fs_disable_4kb_erase(nor);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > if (!mtd->name)
> > > > > mtd->name = dev_name(dev);
> > > > > mtd->priv = nor;
> > > > > --
> > > > > 2.1.0.27.g96db324
> > > > >
> > > > >
> > > > Hi Brian, I will ack this change but still feel it's kind of hacking code.
> > > >
> > > > Acked-by: Han xu <han.xu@nxp.com>
> > >
> > > I am new on the list so I am not sure if this topic has been discussed.
> > > Generally our product functionality relay on those 4KiB sectors.
> > > I know that this hack is already in u-boot, but if you mainstream
> > > this you will force users of those 4KiB sectors to do hack the hack...
> > > I believe the proper solution here is to use erase regions
> > > functionality, I send and RFS about that some time ago.
> >
> > Do you mind to send me a link for reference?
> >
> Han,
>
> Sorry, It seem I have not posted erase region changes (only those regarding
> DUAL/QUAD I/O).
> Generally, in this flash you need to create 3 erase regions (because in FS-S
> family support only 4KiB erase on parameters sector - eg. 1.2.2.4 in S25FS512S).
> In my case regions are:
> 1. 0-32KiB (8*4KiB) - 4K_ERASE (0x20/0x21) 2. 32 - 256 - SE_CMD (0xd8/0xdc) 3.
> Rest of the flash SE_CMD (0xd8/0xdc)
>
> To erase whole flash you can also use CHIP_ERASE_CMD (0x60/0xC7) command,
> you just need to add one more mtd partition that will cover whole flash.
>
Hi Krzeminski,
Do you think is there any great advantages for enable 4KB?
Because for NXP(Freescale) QSPI controller, there is only support max to 16 groups command.
So It's hard to give 3 groups command just for erase (0x21,0xdc and 0xc7).
So we have to disable the 4kb erase and only use 256kbytes in this patch.
^ permalink raw reply
* [RFC PATCH] mfd: dt: Add Aspeed LPC binding
From: Arnd Bergmann @ 2016-11-17 9:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117060633.3837-1-andrew@aj.id.au>
On Thursday, November 17, 2016 4:36:33 PM CET Andrew Jeffery wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>
> I'd like to start a discussion about how to handle the LPC register space in
> the Aspeed SoC. There are a number of issues, largely concerned with the layout
> of the registers but also with the fact that LPC register state is used by the
> pinmux to determine some pin functionality.
...
>
> What is the recommended approach to managing such hardware?
Can you clarify which side of the LPC bus this is? We are currently having
a discussion for how to integrate the LPC master on an ARM64 server that
uses LPC to access an Aspeed LPC slave. For this one we want to use the
traditional ISA DT binding.
I'm guessing that you are interesting in the other side here, for mapping
the registers of the LPC slave on the Aspeed BMC, but that's not clear from
your email, as I'm assuming that the same chip has both master and slave
interfaces.
Arnd
^ permalink raw reply
* [PATCH v4 1/2] drm/bridge: dumb-vga-dac: Support a VDD regulator supply
From: Archit Taneja @ 2016-11-17 9:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v668A-hFnWy22_DarSSZ6TkvH5=WH-UvaXOFQJBqyKzPXw@mail.gmail.com>
On 11/17/2016 01:25 PM, Chen-Yu Tsai wrote:
> On Thu, Nov 17, 2016 at 3:48 PM, Archit Taneja <architt@codeaurora.org> wrote:
>> Hi,
>>
>> Thanks for the patch.
>>
>>
>> On 11/16/2016 09:12 PM, Chen-Yu Tsai wrote:
>>>
>>> Some dumb VGA DACs are active components which require external power.
>>> Add support for specifying a regulator as its power supply.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> Acked-by: Rob Herring <robh@kernel.org>
>>> ---
>>> .../bindings/display/bridge/dumb-vga-dac.txt | 2 ++
>>> drivers/gpu/drm/bridge/dumb-vga-dac.c | 35
>>> ++++++++++++++++++++++
>>> 2 files changed, 37 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>>> b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>>> index 003bc246a270..164cbb15f04c 100644
>>> --- a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>>> +++ b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
>>> @@ -16,6 +16,8 @@ graph bindings specified in
>>> Documentation/devicetree/bindings/graph.txt.
>>> - Video port 0 for RGB input
>>> - Video port 1 for VGA output
>>>
>>> +Optional properties:
>>> +- vdd-supply: Power supply for DAC
>>>
>>> Example
>>> -------
>>> diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c
>>> b/drivers/gpu/drm/bridge/dumb-vga-dac.c
>>> index afec232185a7..15b549f94307 100644
>>> --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
>>> +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
>>> @@ -12,6 +12,7 @@
>>>
>>> #include <linux/module.h>
>>> #include <linux/of_graph.h>
>>> +#include <linux/regulator/consumer.h>
>>>
>>> #include <drm/drmP.h>
>>> #include <drm/drm_atomic_helper.h>
>>> @@ -23,6 +24,7 @@ struct dumb_vga {
>>> struct drm_connector connector;
>>>
>>> struct i2c_adapter *ddc;
>>> + struct regulator *vdd;
>>> };
>>>
>>> static inline struct dumb_vga *
>>> @@ -124,8 +126,32 @@ static int dumb_vga_attach(struct drm_bridge *bridge)
>>> return 0;
>>> }
>>>
>>> +static void dumb_vga_enable(struct drm_bridge *bridge)
>>> +{
>>> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
>>> + int ret = 0;
>>> +
>>> + if (vga->vdd)
>>> + ret = regulator_enable(vga->vdd);
>>> +
>>> + if (ret) {
>>> + DRM_ERROR("Failed to enable vdd regulator: %d\n", ret);
>>> + return;
>>
>>
>> We don't need this return for now. If you're okay with it, can I fix this
>> and queue to misc?
>
> Yes, please!
pushed to drm-misc.
Thanks,
Archit
>
> Thanks
> ChenYu
>
>>
>> Thanks,
>> Archit
>>
>>
>>> + }
>>> +}
>>> +
>>> +static void dumb_vga_disable(struct drm_bridge *bridge)
>>> +{
>>> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
>>> +
>>> + if (vga->vdd)
>>> + regulator_disable(vga->vdd);
>>> +}
>>> +
>>> static const struct drm_bridge_funcs dumb_vga_bridge_funcs = {
>>> .attach = dumb_vga_attach,
>>> + .enable = dumb_vga_enable,
>>> + .disable = dumb_vga_disable,
>>> };
>>>
>>> static struct i2c_adapter *dumb_vga_retrieve_ddc(struct device *dev)
>>> @@ -169,6 +195,15 @@ static int dumb_vga_probe(struct platform_device
>>> *pdev)
>>> return -ENOMEM;
>>> platform_set_drvdata(pdev, vga);
>>>
>>> + vga->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
>>> + if (IS_ERR(vga->vdd)) {
>>> + ret = PTR_ERR(vga->vdd);
>>> + if (ret == -EPROBE_DEFER)
>>> + return -EPROBE_DEFER;
>>> + vga->vdd = NULL;
>>> + dev_dbg(&pdev->dev, "No vdd regulator found: %d\n", ret);
>>> + }
>>> +
>>> vga->ddc = dumb_vga_retrieve_ddc(&pdev->dev);
>>> if (IS_ERR(vga->ddc)) {
>>> if (PTR_ERR(vga->ddc) == -ENODEV) {
>>>
>>
>> --
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> a Linux Foundation Collaborative Project
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash
From: Krzeminski, Marcin (Nokia - PL/Wroclaw) @ 2016-11-17 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR0401MB24077A46D3FC5147DC4C69D989B10@DB6PR0401MB2407.eurprd04.prod.outlook.com>
> -----Original Message-----
> From: Yao Yuan [mailto:yao.yuan at nxp.com]
> Sent: Thursday, November 17, 2016 10:14 AM
> To: Krzeminski, Marcin (Nokia - PL/Wroclaw)
> <marcin.krzeminski@nokia.com>; Han Xu <xhnjupt@gmail.com>
> Cc: David Woodhouse <dwmw2@infradead.org>; linux-
> kernel at vger.kernel.org; linux-mtd at lists.infradead.org;
> han.xu at freescale.com; Brian Norris <computersforpeace@gmail.com>;
> jagannadh.teki at gmail.com; linux-arm-kernel at lists.infradead.org
> Subject: RE: [PATCH v3 6/9] mtd: spi-nor: Support R/W for S25FS-S family
> flash
>
> On Thu, Nov 17, 2016 at 06:50:55AM +0000, Krzeminski, Marcin (Nokia -
> PL/Wroclaw) wrote:
> > > > > On Thu, Aug 18, 2016 at 2:38 AM, Yunhui Cui
> > > > > <B56489@freescale.com>
> > > > > wrote:
> > > > > > From: Yunhui Cui <yunhui.cui@nxp.com>
> > > > > >
> > > > > > With the physical sectors combination, S25FS-S family flash
> > > > > > requires some special operations for read/write functions.
> > > > > >
> > > > > > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> > > > > > ---
> > > > > > drivers/mtd/spi-nor/spi-nor.c | 56
> > > > > > +++++++++++++++++++++++++++++++++++++++++++
> > > > > > 1 file changed, 56 insertions(+)
> > > > > >
> > > > > > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > > > > > b/drivers/mtd/spi-nor/spi-nor.c index d0fc165..495d0bb 100644
> > > > > > --- a/drivers/mtd/spi-nor/spi-nor.c
> > > > > > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > > > > > @@ -39,6 +39,10 @@
> > > > > >
> > > > > > #define SPI_NOR_MAX_ID_LEN 6
> > > > > > #define SPI_NOR_MAX_ADDR_WIDTH 4
> > > > > > +/* Added for S25FS-S family flash */
> > > > > > +#define SPINOR_CONFIG_REG3_OFFSET 0x800004
> > > > > > +#define CR3V_4KB_ERASE_UNABLE 0x8 #define
> > > > > > +SPINOR_S25FS_FAMILY_EXT_JEDEC 0x81
> > > > > >
> > > > > > struct flash_info {
> > > > > > char *name;
> > > > > > @@ -78,6 +82,7 @@ struct flash_info { };
> > > > > >
> > > > > > #define JEDEC_MFR(info) ((info)->id[0])
> > > > > > +#define EXT_JEDEC(info) ((info)->id[5])
> > > > > >
> > > > > > static const struct flash_info *spi_nor_match_id(const char
> > > > > > *name);
> > > > > >
> > > > > > @@ -899,6 +904,7 @@ static const struct flash_info spi_nor_ids[] = {
> > > > > > */
> > > > > > { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024,
> > > > > > 64,
> > > > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > > > > > { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024,
> > > > > > 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > > > > > + { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024,
> > > > > > + 512, 0)},
> > > > > > { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
> > > > > > { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024,
> > > > > > 512,
> > > > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > > > > > { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024,
> > > > > > 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, @@ -1036,6
> > > +1042,50
> > > > > @@ static const struct flash_info *spi_nor_read_id(struct
> > > > > spi_nor
> > > > > *nor)
> > > > > > return ERR_PTR(-ENODEV); }
> > > > > >
> > > > > > +/*
> > > > > > + * The S25FS-S family physical sectors may be configured as a
> > > > > > + * hybrid combination of eight 4-kB parameter sectors
> > > > > > + * at the top or bottom of the address space with all
> > > > > > + * but one of the remaining sectors being uniform size.
> > > > > > + * The Parameter Sector Erase commands (20h or 21h) must
> > > > > > + * be used to erase the 4-kB parameter sectors individually.
> > > > > > + * The Sector (uniform sector) Erase commands (D8h or DCh)
> > > > > > + * must be used to erase any of the remaining
> > > > > > + * sectors, including the portion of highest or lowest
> > > > > > +address
> > > > > > + * sector that is not overlaid by the parameter sectors.
> > > > > > + * The uniform sector erase command has no effect on
> > > > > > +parameter
> > > > > sectors.
> > > > > > + */
> > > > > > +static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor) {
> > > > > > + u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
> > > > > > + u8 cr3v = 0x0;
> > > > > > + int ret = 0x0;
> > > > > > +
> > > > > > + nor->cmd_buf[2] = cr3v_addr >> 16;
> > > > > > + nor->cmd_buf[1] = cr3v_addr >> 8;
> > > > > > + nor->cmd_buf[0] = cr3v_addr >> 0;
> > > > > > +
> > > > > > + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR,
> &cr3v, 1);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > + if (cr3v & CR3V_4KB_ERASE_UNABLE)
> > > > > > + return 0;
> > > > > > + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > + cr3v = CR3V_4KB_ERASE_UNABLE;
> > > > > > + nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
> > > > > > + nor->write(nor, cr3v_addr, 1, &cr3v);
> > > > > > +
> > > > > > + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR,
> &cr3v, 1);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > + if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
> > > > > > + return -EPERM;
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t
> len,
> > > > > > size_t *retlen, u_char *buf) { @@
> > > > > > -1361,6
> > > > > > +1411,12 @@ int spi_nor_scan(struct spi_nor *nor, const char
> > > > > > +*name,
> > > > > enum read_mode mode)
> > > > > > spi_nor_wait_till_ready(nor);
> > > > > > }
> > > > > >
> > > > > > + if (EXT_JEDEC(info) == SPINOR_S25FS_FAMILY_EXT_JEDEC) {
> > > > > > + ret = spansion_s25fs_disable_4kb_erase(nor);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > + }
> > > > > > +
> > > > > > if (!mtd->name)
> > > > > > mtd->name = dev_name(dev);
> > > > > > mtd->priv = nor;
> > > > > > --
> > > > > > 2.1.0.27.g96db324
> > > > > >
> > > > > >
> > > > > Hi Brian, I will ack this change but still feel it's kind of hacking code.
> > > > >
> > > > > Acked-by: Han xu <han.xu@nxp.com>
> > > >
> > > > I am new on the list so I am not sure if this topic has been discussed.
> > > > Generally our product functionality relay on those 4KiB sectors.
> > > > I know that this hack is already in u-boot, but if you mainstream
> > > > this you will force users of those 4KiB sectors to do hack the hack...
> > > > I believe the proper solution here is to use erase regions
> > > > functionality, I send and RFS about that some time ago.
> > >
> > > Do you mind to send me a link for reference?
> > >
> > Han,
> >
> > Sorry, It seem I have not posted erase region changes (only those
> > regarding DUAL/QUAD I/O).
> > Generally, in this flash you need to create 3 erase regions (because
> > in FS-S family support only 4KiB erase on parameters sector - eg. 1.2.2.4 in
> S25FS512S).
> > In my case regions are:
> > 1. 0-32KiB (8*4KiB) - 4K_ERASE (0x20/0x21) 2. 32 - 256 - SE_CMD
> (0xd8/0xdc) 3.
> > Rest of the flash SE_CMD (0xd8/0xdc)
> >
> > To erase whole flash you can also use CHIP_ERASE_CMD (0x60/0xC7)
> > command, you just need to add one more mtd partition that will cover
> whole flash.
> >
>
> Hi Krzeminski,
>
> Do you think is there any great advantages for enable 4KB?
> Because for NXP(Freescale) QSPI controller, there is only support max to 16
> groups command.
>
> So It's hard to give 3 groups command just for erase (0x21,0xdc and 0xc7).
> So we have to disable the 4kb erase and only use 256kbytes in this patch.
>
Yes, if you disable parameters sector in spi-nor framework you will disable it
for all spi-nor clients not only for NXP QSPI controller. There are users (at
least me) that relay on parameters sector functionality. This patch will brake it.
Thanks,
Marcin
^ permalink raw reply
* [PATCH] pinctrl: sunxi: fix theoretical uninitialized variable access
From: Arnd Bergmann @ 2016-11-17 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYk25q9P5sErnfHcH49BT43vCCDihsZNEsf-6Gvpq+Pww@mail.gmail.com>
On Thursday, November 17, 2016 10:08:28 AM CET Linus Walleij wrote:
> On Wed, Nov 16, 2016 at 9:33 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>
> > On Wed, Nov 16, 2016 at 03:18:18PM +0100, Arnd Bergmann wrote:
> >> gcc warns about a way that it could use an uninitialized variable:
> >>
> >> drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init':
> >> drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized]
> >>
> >> This cannot really happen except if 'freq' is UINT_MAX and 'clock' is
> >> zero, and both of these are forbidden. To shut up the warning anyway,
> >> this changes the logic to initialize the return code to the first
> >> divider value before looking at the others.
> >>
> >> Fixes: 7c926492d38a ("pinctrl: sunxi: Add support for interrupt debouncing")
> >> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> >
> > Thanks for that patch.
> >
> > Just out of curiosity, which gcc gives those warnings? I have 6.2 and
> > it didn't output anything..
>
> Context: Arnd re-enabled -Werror=maybe-uninitialized
> in the kernel build and this kind of stuff started to appear so
> it needs to be fixed up.
Right, it was disabled from linux-4.8-rc1 to linux-4.9-rc4 and is now back
in the default builds when using gcc-4.9 or higher. You should get the
warning if you test with linux-next or -rc4.
Arnd
^ permalink raw reply
* [PATCH v16 00/15] acpi, clocksource: add GTDT driver and GTDT support in arm_arch_timer
From: Xiongfeng Wang @ 2016-11-17 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <944d11ac-3c0d-72c0-6888-df8e474e21bb@huawei.com>
Sorry for not describing specifically in the last mail.
I have applied all the patches of this patchset on Linux 4.9, and tested
the per-cpu timer and sbsa watchdog part, which function well on D05 board.
On 2016/11/17 11:34, Xiongfeng Wang wrote:
> Tested-by: wangxiongfeng2 at huawei.com on D05 board.
>
>
> On 2016/11/16 21:48, fu.wei at linaro.org wrote:
>> From: Fu Wei <fu.wei@linaro.org>
>>
>> This patchset:
>> (1)Preparation for adding GTDT support in arm_arch_timer:
>> 1. Move some enums and marcos to header file;
>> 2. Add a new enum for spi type;
>> 3. Improve printk relevant code.
>> 4. rename some enums and defines, and some cleanups.
>> 5. separate out arch_timer_uses_ppi init code and fix a potential bug
>> 6. Refactor arch_timer_detect_rate to keep dt code only in *_of_init
>> 7. Refactor arch_timer_needs_probing, and call it only if acpi disabled.
>> 8. Introduce some new structs and refactor the timer init code
>>
>> (2)Introduce ACPI GTDT parser: drivers/acpi/arm64/acpi_gtdt.c
>> Parse all kinds of timer in GTDT table of ACPI:arch timer,
>> memory-mapped timer and SBSA Generic Watchdog timer.
>> This driver can help to simplify all the relevant timer drivers,
>> and separate all the ACPI GTDT knowledge from them.
>>
>> (3)Simplify ACPI code for arm_arch_timer
>>
>> (4)Add GTDT support for ARM memory-mapped timer, also refactor
>> original memory-mapped timer dt support for reusing some common
>> code.
>>
>> This patchset has been tested on the following platforms with ACPI enabled:
>> (1)ARM Foundation v8 model
>>
>> Changelog:
>> v16: https://lkml.org/lkml/2016/
>> Fix patchset problem about static enum ppi_nr of 01/13 in v15.
>> Refactor arch_timer_detect_rate.
>> Refactor arch_timer_needs_probing.
>>
>> v15: https://lkml.org/lkml/2016/11/15/366
>> Re-order patches
>> Add arm_arch_timer refactoring patches to prepare for GTDT:
>> 1. rename some enums and defines, and some cleanups
>> 2. separate out arch_timer_uses_ppi init code and fix a potential bug
>> 3. Improve some new structs, refactor the timer init code.
>> Since the some structs have been changed, GTDT parser for memory-mapped
>> timer and SBSA Generic Watchdog timer have been update.
>>
>> v14: https://lkml.org/lkml/2016/9/28/573
>> Separate memory-mapped timer GTDT support into two patches
>> 1. Refactor the timer init code to prepare for GTDT
>> 2. Add GTDT support for memory-mapped timer
>>
>> v13: http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg1231717.html
>> Improve arm_arch_timer code for memory-mapped
>> timer GTDT support, refactor original memory-mapped timer
>> dt support for reusing some common code.
>>
>> v12: https://lkml.org/lkml/2016/9/13/250
>> Rebase to latest Linux 4.8-rc6
>> Delete the confusing "skipping" in the error message.
>>
>> V11: https://lkml.org/lkml/2016/9/6/354
>> Rebase to latest Linux 4.8-rc5
>> Delete typedef (suggested by checkpatch.pl)
>>
>> V10: https://lkml.org/lkml/2016/7/26/215
>> Drop the "readq" patch.
>> Rebase to latest Linux 4.7.
>>
>> V9: https://lkml.org/lkml/2016/7/25/345
>> Improve pr_err message in acpi gtdt driver.
>> Update Commit message for 7/9
>> shorten the irq mapping function name
>> Improve GTDT driver for memory-mapped timer
>>
>> v8: https://lkml.org/lkml/2016/7/19/660
>> Improve "pr_fmt(fmt)" definition: add "ACPI" in front of "GTDT",
>> and also improve printk message.
>> Simplify is_timer_block and is_watchdog.
>> Merge acpi_gtdt_desc_init and gtdt_arch_timer_init into acpi_gtdt_init();
>> Delete __init in include/linux/acpi.h for GTDT API
>> Make ARM64 select GTDT.
>> Delete "#include <linux/module.h>" from acpi_gtdt.c
>> Simplify GT block parse code.
>>
>> v7: https://lkml.org/lkml/2016/7/13/769
>> Move the GTDT driver to drivers/acpi/arm64
>> Add add the ARM64-specific ACPI Support maintainers in MAINTAINERS
>> Merge 3 patches of GTDT parser driver.
>> Fix the for_each_platform_timer bug.
>>
>> v6: https://lkml.org/lkml/2016/6/29/580
>> split the GTDT driver to 4 parts: basic, arch_timer, memory-mapped timer,
>> and SBSA Generic Watchdog timer
>> Improve driver by suggestions and example code from Daniel Lezcano
>>
>> v5: https://lkml.org/lkml/2016/5/24/356
>> Sorting out all patches, simplify the API of GTDT driver:
>> GTDT driver just fills the data struct for arm_arch_timer driver.
>>
>> v4: https://lists.linaro.org/pipermail/linaro-acpi/2016-March/006667.html
>> Delete the kvm relevant patches
>> Separate two patches for sorting out the code for arm_arch_timer.
>> Improve irq info export code to allow missing irq info in GTDT table.
>>
>> v3: https://lkml.org/lkml/2016/2/1/658
>> Improve GTDT driver code:
>> (1)improve pr_* by defining pr_fmt(fmt)
>> (2)simplify gtdt_sbsa_gwdt_init
>> (3)improve gtdt_arch_timer_data_init, if table is NULL, it will try
>> to get GTDT table.
>> Move enum ppi_nr to arm_arch_timer.h, and add enum spi_nr.
>> Add arm_arch_timer get ppi from DT and GTDT support for kvm.
>>
>> v2: https://lkml.org/lkml/2015/12/2/10
>> Rebase to latest kernel version(4.4-rc3).
>> Fix the bug about the config problem,
>> use CONFIG_ACPI_GTDT instead of CONFIG_ACPI in arm_arch_timer.c
>>
>> v1: The first upstreaming version: https://lkml.org/lkml/2015/10/28/553
>>
>> Fu Wei (15):
>> clocksource/drivers/arm_arch_timer: Move enums and defines to header
>> file
>> clocksource/drivers/arm_arch_timer: Add a new enum for spi type
>> clocksource/drivers/arm_arch_timer: Improve printk relevant code
>> clocksource/drivers/arm_arch_timer: rename some enums and defines, and
>> some cleanups.
>> clocksource/drivers/arm_arch_timer: fix a bug in arch_timer_register
>> about arch_timer_uses_ppi
>> clocksource/drivers/arm_arch_timer: separate out arch_timer_uses_ppi
>> init code to prepare for GTDT.
>> clocksource/drivers/arm_arch_timer: Refactor arch_timer_detect_rate to
>> keep dt code in *_of_init
>> clocksource/drivers/arm_arch_timer: Refactor arch_timer_needs_probing,
>> and call it only if acpi disabled.
>> clocksource/drivers/arm_arch_timer: Introduce some new structs to
>> prepare for GTDT
>> clocksource/drivers/arm_arch_timer: Refactor the timer init code to
>> prepare for GTDT
>> acpi/arm64: Add GTDT table parse driver
>> clocksource/drivers/arm_arch_timer: Simplify ACPI support code.
>> acpi/arm64: Add memory-mapped timer support in GTDT driver
>> clocksource/drivers/arm_arch_timer: Add GTDT support for memory-mapped
>> timer
>> acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver
>>
>> arch/arm64/Kconfig | 1 +
>> drivers/acpi/arm64/Kconfig | 3 +
>> drivers/acpi/arm64/Makefile | 1 +
>> drivers/acpi/arm64/gtdt.c | 411 +++++++++++++++++++++++++++++
>> drivers/clocksource/arm_arch_timer.c | 484 ++++++++++++++++++++---------------
>> drivers/watchdog/Kconfig | 1 +
>> include/clocksource/arm_arch_timer.h | 61 ++++-
>> include/linux/acpi.h | 8 +
>> virt/kvm/arm/hyp/timer-sr.c | 6 +-
>> 9 files changed, 759 insertions(+), 217 deletions(-)
>> create mode 100644 drivers/acpi/arm64/gtdt.c
>>
>
>
> .
>
^ permalink raw reply
* [PATCH] pinctrl: sunxi: fix theoretical uninitialized variable access
From: Maxime Ripard @ 2016-11-17 9:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYk25q9P5sErnfHcH49BT43vCCDihsZNEsf-6Gvpq+Pww@mail.gmail.com>
On Thu, Nov 17, 2016 at 10:08:28AM +0100, Linus Walleij wrote:
> On Wed, Nov 16, 2016 at 9:33 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>
> > On Wed, Nov 16, 2016 at 03:18:18PM +0100, Arnd Bergmann wrote:
> >> gcc warns about a way that it could use an uninitialized variable:
> >>
> >> drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init':
> >> drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized]
> >>
> >> This cannot really happen except if 'freq' is UINT_MAX and 'clock' is
> >> zero, and both of these are forbidden. To shut up the warning anyway,
> >> this changes the logic to initialize the return code to the first
> >> divider value before looking at the others.
> >>
> >> Fixes: 7c926492d38a ("pinctrl: sunxi: Add support for interrupt debouncing")
> >> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> >
> > Thanks for that patch.
> >
> > Just out of curiosity, which gcc gives those warnings? I have 6.2 and
> > it didn't output anything..
>
> Context: Arnd re-enabled -Werror=maybe-uninitialized
> in the kernel build and this kind of stuff started to appear so
> it needs to be fixed up.
Ah, that makes sense. Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [RFC PATCH] mfd: dt: Add Aspeed LPC binding
From: Linus Walleij @ 2016-11-17 9:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117060633.3837-1-andrew@aj.id.au>
On Thu, Nov 17, 2016 at 7:06 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> +* Device tree bindings for the Aspeed LPC Controller
We are going overboard with the lingo sometimes, to the point that we do not
understand how terse things become.
LPC = Low Pin Count, right?
Explain that right here: it is a slow external bus, right?
> +The Aspeed LPC controller contains registers for a variety of functions. Not
> +all registers for a function are contiguous, and some registers are referenced
> +by functions outside the LPC controller.
> +
> +Note that this is separate from the H8S/2168 compatible register set occupying
> +the start of the LPC controller address space.
> +
> +Some significant functions in the LPC controller:
> +
> +* LPC Host Controller
> +* Host Interface Controller
Host interface to what?
> +* iBT Controller
What is iBT?
> +* SuperIO Scratch registers
Again more context please.
With standards documents, either explain everything or provide
pointers for the information.
Yours,
Linus Walleij
^ permalink raw reply
* wdt, gpio: move arch_initcall into subsys_initcall ?
From: Vladimir Zapolskiy @ 2016-11-17 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <582D5750.4000408@denx.de>
Hello Heiko,
On 11/17/2016 09:08 AM, Heiko Schocher wrote:
> Hello Guenter, Vladimir,
>
> Sorry for the late response, but I was "on the road" ...
>
> Am 15.11.2016 um 14:46 schrieb Guenter Roeck:
>> On 11/15/2016 03:32 AM, Vladimir Zapolskiy wrote:
>>> On 11/15/2016 01:10 PM, Vladimir Zapolskiy wrote:
>>>> Hello Heiko,
>>>>
>>>> On 11/15/2016 12:20 PM, Heiko Schocher wrote:
>>>>> Hello,
>>>>>
>>>>> commit e188cbf7564f: "gpio: mxc: shift gpio_mxc_init() to
>>>>> subsys_initcall level"
>>>>> moves the gpio initialization of the mxc gpio driver
>>>>> from the arch_initcall level into subsys_initcall level.
>>>>>
>>>>> This leads now on mxc boards, which use a gpio wdt driver
>>>>> and the CONFIG_GPIO_WATCHDOG_ARCH_INITCALL option enabled,
>>>>> to unwanted driver probe deferrals during kernel boot.
>>>>>
>>>>> I see this currently on an imx6 based board (which has unfortunately
>>>>> 3 WDT: imx6 internal (disabled), gpio wdt and da9063 WDT ...).
>>>>>
>>>>> Also a side effect from above commit is, that the da9063 WDT driver
>>>>> is now probed before the gpio WDT driver ... so /dev/watchdog now
>>>>> does not point to the gpio_wdt, instead it points to the da9063 WDT.
>>>>>
>>>>> So there are 2 solutions possible:
>>>>>
>>>>> - add a CONFIG_GPIO_MCX_ARCH_INITCALL option
>>>>> in drivers/gpio/gpio-mxc.c like for the gpio_wdt.c driver?
>>>>
>>>> in my opinion this is overly heavy solution and it might be
>>>> better to avoid it if possible.
>>>>
>>>> I would rather prefer to reconsider GPIO_WATCHDOG_ARCH_INITCALL
>>>> usage in the watchdog driver.
>>>>
>>>> Moreover adding this proposed GPIO_MCX_ARCH_INITCALL to call
>>>> the driver on arch level will result in deferring the GPIO driver.
>>>>
>>>>> But how can we guarantee, that first the gpio driver and then
>>>>> the gpio_wdt driver gets probed?
>>>>>
>>>>> - move the arch_initcall in gpio_wdt.c into a subsys_initcall
>>>>> (Tested this, and the probe dereferral messages are gone ...)
>>>>>
>>>>> But this may results in problems on boards, which needs an early
>>>>> trigger on an gpio wdt ...
>>>>
>>>> The level of "earliness" can not be defined in absolute time value
>>>> in any case, why decreasing the init level of the watchdog driver
>>>> to subsys level can cause problems? For that there should exist
>>>> some kind of a dependency on IC or PCB hardware level, can you
>>>> name it please?
>
> On the current problem, there is no dependency on PCB, but I know
> of watchdogs triggered through a gpio pin, which must triggered < 1 second
> and subsys_initcall is too late for this. I think, this was the reason
This is not a valid reason, nobody guarantees that arch_initcall()
code is run in < 1 second time interval.
> for introducing the CONFIG_GPIO_WATCHDOG_ARCH_INITCALL option ...
>
Putting GPIO driver on arch_initcall() level results in deferring
of the GPIO driver. Because you desire to avoid probe deferring, you
should not consider putting GPIO driver on arch_initcall() level.
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH] ARM: dts: sunxi: Explicitly enable pull-ups for MMC pins
From: Chen-Yu Tsai @ 2016-11-17 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In the past, all the MMC pins had
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
which was actually a no-op. We were relying on U-boot to set the bias
pull up for us. These properties were removed as part of the fix up to
actually support no bias on the pins. During the transition some boards
experienced regular MMC time-outs during normal operation, while others
completely failed to initialize the SD card.
Given that MMC starts in open-drain mode and the pull-ups are required,
it's best to enable it for all the pin settings.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
arch/arm/boot/dts/sun5i.dtsi | 1 +
arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++++
arch/arm/boot/dts/sun7i-a20.dtsi | 2 ++
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 3 +++
arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
arch/arm/boot/dts/sun8i-h3.dtsi | 3 +++
arch/arm/boot/dts/sun9i-a80.dtsi | 3 +++
8 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index dae838e4dd9e..ba20b48c0702 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -1023,6 +1023,7 @@
"PF3", "PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 7ab6b336533e..54170147040f 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -582,6 +582,7 @@
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
mmc2_pins_a: mmc2 at 0 {
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 7ea1116c7c88..20a0331ddfb5 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -547,6 +547,7 @@
"PF3", "PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
mmc1_pins_a: mmc1 at 0 {
@@ -554,6 +555,7 @@
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
+ bias-pull-up;
};
mmc2_pins_a: mmc2 at 0 {
@@ -571,6 +573,7 @@
"PC24";
function = "mmc2";
drive-strength = <30>;
+ bias-pull-up;
};
mmc3_8bit_emmc_pins: mmc3 at 1 {
@@ -580,6 +583,7 @@
"PC24";
function = "mmc3";
drive-strength = <40>;
+ bias-pull-up;
};
uart0_pins_a: uart0 at 0 {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 34d613b0dd73..a1ee4197129a 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1179,6 +1179,7 @@
"PF3", "PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
@@ -1200,6 +1201,7 @@
"PI7", "PI8", "PI9";
function = "mmc3";
drive-strength = <30>;
+ bias-pull-up;
};
ps20_pins_a: ps20 at 0 {
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index ecb49a5a7615..bc3e936edfcf 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -293,6 +293,7 @@
"PF3", "PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
mmc1_pins_a: mmc1 at 0 {
@@ -300,6 +301,7 @@
"PG3", "PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
+ bias-pull-up;
};
mmc2_8bit_pins: mmc2_8bit {
@@ -309,6 +311,7 @@
"PC15", "PC16";
function = "mmc2";
drive-strength = <30>;
+ bias-pull-up;
};
pwm0_pins: pwm0 {
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 656cdb5f7a88..79eaa7139f43 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -171,6 +171,7 @@
"PF3", "PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
uart0_pins_a: uart0 at 0 {
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 416b825ddb9f..fca66bf2dec5 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -348,6 +348,7 @@
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
mmc0_cd_pin: mmc0_cd_pin at 0 {
@@ -361,6 +362,7 @@
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
+ bias-pull-up;
};
mmc2_8bit_pins: mmc2_8bit {
@@ -370,6 +372,7 @@
"PC15", "PC16";
function = "mmc2";
drive-strength = <30>;
+ bias-pull-up;
};
spi0_pins: spi0 {
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index b97db1df0803..7231d2c90dde 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -696,6 +696,7 @@
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
+ bias-pull-up;
};
mmc1_pins: mmc1 {
@@ -703,6 +704,7 @@
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
+ bias-pull-up;
};
mmc2_8bit_pins: mmc2_8bit {
@@ -712,6 +714,7 @@
"PC16";
function = "mmc2";
drive-strength = <30>;
+ bias-pull-up;
};
uart0_pins_a: uart0 at 0 {
--
2.10.2
^ permalink raw reply related
* [PATCH v16 00/15] acpi, clocksource: add GTDT driver and GTDT support in arm_arch_timer
From: Daniel Lezcano @ 2016-11-17 9:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479304148-2965-1-git-send-email-fu.wei@linaro.org>
On Wed, Nov 16, 2016 at 09:48:53PM +0800, fu.wei at linaro.org wrote:
> From: Fu Wei <fu.wei@linaro.org>
>
> This patchset:
> (1)Preparation for adding GTDT support in arm_arch_timer:
> 1. Move some enums and marcos to header file;
> 2. Add a new enum for spi type;
> 3. Improve printk relevant code.
> 4. rename some enums and defines, and some cleanups.
> 5. separate out arch_timer_uses_ppi init code and fix a potential bug
> 6. Refactor arch_timer_detect_rate to keep dt code only in *_of_init
> 7. Refactor arch_timer_needs_probing, and call it only if acpi disabled.
> 8. Introduce some new structs and refactor the timer init code
>
> (2)Introduce ACPI GTDT parser: drivers/acpi/arm64/acpi_gtdt.c
> Parse all kinds of timer in GTDT table of ACPI:arch timer,
> memory-mapped timer and SBSA Generic Watchdog timer.
> This driver can help to simplify all the relevant timer drivers,
> and separate all the ACPI GTDT knowledge from them.
>
> (3)Simplify ACPI code for arm_arch_timer
>
> (4)Add GTDT support for ARM memory-mapped timer, also refactor
> original memory-mapped timer dt support for reusing some common
> code.
>
> This patchset has been tested on the following platforms with ACPI enabled:
> (1)ARM Foundation v8 model
>
> Changelog:
> v16: https://lkml.org/lkml/2016/
> Fix patchset problem about static enum ppi_nr of 01/13 in v15.
> Refactor arch_timer_detect_rate.
> Refactor arch_timer_needs_probing.
Most of the patches are touching drivers/clocksource and others acpi.
Through which tree this patchset should go ?
^ permalink raw reply
* [PATCH V8 2/6] thermal: bcm2835: add thermal driver for bcm2835 soc
From: Martin Sperl @ 2016-11-17 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117021107.GA2647@localhost.localdomain>
On 17.11.2016 03:11, Eduardo Valentin wrote:
> Hey Martin,
>
> Very sorry for the late feedback. Not so sure if this one got queued
> already or not. Anyways, just minor questions as follows:
>
> On Wed, Nov 02, 2016 at 10:18:22AM +0000, kernel at martin.sperl.org wrote:
>> From: Martin Sperl <kernel@martin.sperl.org>
>>
>> Add basic thermal driver for bcm2835 SOC.
>>
>> This driver currently relies on the firmware setting up the
>> tsense HW block and does not set it up itself.
>>
>> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
>> Acked-by: Eric Anholt <eric@anholt.net>
>> Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
>>
...
>> +static int bcm2835_thermal_adc2temp(
>> + const struct bcm2835_thermal_info *info, u32 adc)
>> +{
>> + return info->offset + (adc * info->slope);
>
> Any specific reason we cannot use thermal_zone_params->slope and
> thermal_zone_params->offset?
You could - the patch was just rebased to 4.9 and those slope and
offset just got merged during this cycle.
Do we really need to modify it - the patch has been around since 4.6.
>> +
>> +static int bcm2835_thermal_get_trip_temp(
>> + struct thermal_zone_device *tz, int trip, int *temp)
>> +{
>> + struct bcm2835_thermal_data *data = tz->devdata;
>> + u32 val = readl(data->regs + BCM2835_TS_TSENSCTL);
>> +
>> + /* get the THOLD bits */
>> + val &= BCM2835_TS_TSENSCTL_THOLD_MASK;
>> + val >>= BCM2835_TS_TSENSCTL_THOLD_SHIFT;
>> +
>> + /* if it is zero then use the info value */
>> + if (val)
>
> Is this a read only register or is this driver supposed to program it?
> In which scenario it would be 0? Can this be added as comments?
It is RW, but the Firmware typically sets up the thermal device with the
correct values already - this is just a fallback.
>> +static int bcm2835_thermal_get_temp(struct thermal_zone_device *tz,
>> + int *temp)
>> +{
>> + struct bcm2835_thermal_data *data = tz->devdata;
>> + u32 val = readl(data->regs + BCM2835_TS_TSENSSTAT);
>> +
>> + if (!(val & BCM2835_TS_TSENSSTAT_VALID))
>
> What cases you would get the valid bit not set? Do you need to wait for
> the conversion to finish?
I guess: if you have just enabled the HW-block (which the FW does much
in advance) and start to read the value immediately (before the first
sample period has finished), then this will not be valid.
So do you need another version of the patchset that uses that new API?
Thanks,
Martin
^ permalink raw reply
* [PATCH v10 01/11] remoteproc: st_slim_rproc: add a slimcore rproc driver
From: Vinod Koul @ 2016-11-17 9:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117063646.GE28340@tuxbot>
On Wed, Nov 16, 2016 at 10:36:46PM -0800, Bjorn Andersson wrote:
> On Sun 13 Nov 21:18 PST 2016, Vinod Koul wrote:
>
> > On Mon, Nov 07, 2016 at 01:57:35PM +0000, Peter Griffin wrote:
> > > >
> > > > As you now make changes to the entire remoteproc Kconfig file, rather
> > > > than simply add a Kconfig symbol we can't bring this in via Vinod's tree
> > > > without providing Linus with a messy merge conflict.
> > > >
> > > > So the remoteproc parts now has to go through my tree.
> > >
> > > OK, I think the best approach is for Vinod to create an immutable
> > > branch with the entire fdma series on, and then both of you merge that branch into
> > > your respective trees.
> >
> > my topic/st_fdma is immutable branch. You cna merge it, if you need a signed
> > tag, please do let me know
> >
>
> Hi Vinod,
>
> It looks like you reverted the wrong Kconfig fix, the one I objected to
> was the change in drivers/remoteproc, not the one in drivers/dma.
>
> The ST_FMDA depends on functions exposed by REMOTEPROC and
> ST_SLIM_REMOTEPROC, the latter in turn depends on REMOTEPROC, which you
> guys made user selectable - and as such should not be selected - but I
> think we should move forward and get everything merged and then we can
> go back and figure out how this should be addressed (or left alone?).
>
> I have merged "topic/st_fdma" into rproc-next, so that I can fix up the
> now broken drivers/remoteproc/Kconfig.
>
> We do however both need to revert the revert or there will be link
> errors if you build the dma driver with remoteproc=n. If you do this I
> can merge the topic once more and we'll keep the set of changes in sync.
Oops my bad, thanks for letting me know. I have reverted this now and
pushing out. Please do let me know if this was fine
Thanks
--
~Vinod
^ permalink raw reply
* [RFC PATCH] mfd: dt: Add Aspeed LPC binding
From: Joel Stanley @ 2016-11-17 10:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4751029.AudB7s5avo@wuerfel>
On Thu, Nov 17, 2016 at 7:46 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday, November 17, 2016 4:36:33 PM CET Andrew Jeffery wrote:
>> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
>> ---
>>
>> I'd like to start a discussion about how to handle the LPC register space in
>> the Aspeed SoC. There are a number of issues, largely concerned with the layout
>> of the registers but also with the fact that LPC register state is used by the
>> pinmux to determine some pin functionality.
> ...
>>
>> What is the recommended approach to managing such hardware?
>
> Can you clarify which side of the LPC bus this is? We are currently having
> a discussion for how to integrate the LPC master on an ARM64 server that
> uses LPC to access an Aspeed LPC slave. For this one we want to use the
> traditional ISA DT binding.
This is from the perspective of the BMC.
On the machines we are talking to, most (all?) access is performed
through the system firmware (skiboot).
> I'm guessing that you are interesting in the other side here, for mapping
> the registers of the LPC slave on the Aspeed BMC, but that's not clear from
> your email, as I'm assuming that the same chip has both master and slave
> interfaces.
Yep, we come from the "other side".
The BMC itself can operate the bus in Master or Slave mode. We are
interested in the slave case, for when the host is requesting access
to its system firmware at boot time. This happens by mapping a region
of the BMC's AHB memory space into the LPC address space. After we
deal with pinmux, Andrew or I will be hacking on a driver to configure
that space, as the BMC needs to configure the window before the host
can boot. It's a pile of bits spread out over different parts of the
chip, and doesn't map nicely into any existing driver model we have in
the kernel.
Other functions include IPMI communication between the BMC and the
host via the LPC bus via the iBT interface. We have a driver for that
staged for 4.10. Then there's a mailbox, some "scratch" registers that
can be used by the firmware for whatever they see fit, and all kinds
of crazy legacy x86 stuff like POST code registers.
Cheers,
Joel
^ permalink raw reply
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