* [GIT PULL] Qualcomm Device Tree Changes for v4.10
From: Olof Johansson @ 2016-11-18 7:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-5-git-send-email-andy.gross@linaro.org>
Hi,
On Sun, Nov 13, 2016 at 12:15:35AM -0600, Andy Gross wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-dts-for-4.10
>
> for you to fetch changes up to 52a1a5f773110f687c34a828ef42fdb882b6b908:
>
> ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard (2016-10-25 08:42:37 -0500)
>
> ----------------------------------------------------------------
> Qualcomm Device Tree Changes for v4.10
>
> * Add EBI2 support to MSM8660
> * Add SMSC ethernet support to APQ8060
> * Add support for display, pstore, iommu, and hdmi to APQ8064
> * Add SDHCI node to MSM8974 Hammerhead
> * Add WP8548 MangOH board support (MDM9615)
>
> ----------------------------------------------------------------
> Archit Taneja (2):
> arm: dts: qcom: apq8064: Add display DT nodes
> arm: dts: qcom: apq8064-ifc6410: Add HDMI support
>
> Bhushan Shah (1):
> ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node
>
> John Stultz (3):
> arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
> arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes
> arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7
>
> Linus Walleij (2):
> ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI
> ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
>
> Neil Armstrong (5):
> ARM: dts: Add MDM9615 dtsi
> dt-bindings: qcom: Add MDM9615 bindings
> ARM: dts: Add Sierra Wireless WP8548 dtsi
> ARM: dts: Add WP8548 based MangOH Green board DTS
We tend to keep the SoC manufacturer as the topmost prefix here, to keep
things in common.
While the Sierra Wireless products are modules, they are based on QCOM SoCs.
So the expected names would be qcom-<soc>-module. Something like
qcom-mdm9615-wp8548.dtsi and qcom-mdm9615-wp8548-mangoh-green.dts.
Can you respin with this addressed? Thanks!
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm Driver Updates for v4.10
From: Olof Johansson @ 2016-11-18 7:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-4-git-send-email-andy.gross@linaro.org>
On Sun, Nov 13, 2016 at 12:15:34AM -0600, Andy Gross wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-drivers-for-4.10
>
> for you to fetch changes up to bd4760ca03156731674a570e44490986189d8228:
>
> firmware: qcom: scm: Use devm_reset_controller_register() (2016-11-12 23:24:51 -0600)
>
> ----------------------------------------------------------------
> Qualcomm ARM Based Driver Updates for v4.10
>
> * Fixup QCOM SCM to use devm_reset_controller_register
> * Add QCOM pinctrl to Qualcomm MAINTAINERS entry
> * Add PM8994 regulator definitions
> * Add stub for WCNSS_CTRL API
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm Defconfig Updates for v4.10
From: Olof Johansson @ 2016-11-18 7:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-3-git-send-email-andy.gross@linaro.org>
On Sun, Nov 13, 2016 at 12:15:33AM -0600, Andy Gross wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-defconfig-for-4.10
>
> for you to fetch changes up to 206787737e308bb447d18adef7da7749188212f5:
>
> ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config (2016-10-24 16:04:32 -0500)
>
> ----------------------------------------------------------------
> Qualcomm ARM Based defconfig Updates for v4.10
>
> * Fixup MDM9615 option names
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 DT Updates for v4.10
From: Olof Johansson @ 2016-11-18 7:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-2-git-send-email-andy.gross@linaro.org>
On Sun, Nov 13, 2016 at 12:15:32AM -0600, Andy Gross wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-for-4.10
>
> for you to fetch changes up to feeaf56ac78d283efe65ea60ec999d4bf3cf395e:
>
> arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support (2016-11-12 22:57:56 -0600)
>
> ----------------------------------------------------------------
> Qualcomm ARM64 Updates for v4.10
>
> * Add Hexagon SMD/PIL nodes
> * Add DB820c PMIC pins
> * Fixup APQ8016 voltage ranges
> * Add various MSM8996 nodes to support SMD/SMEM/SMP2P
> * Add support for Huawei Nexus 6P (Angler)
> * Add support for LG Nexus 5x (Bullhead)
Merged, thanks. Great to start seeing (almost) current phone support, even if
it's very basic hardware descriptions so far.
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 Defconfig Updates for v4.10
From: Olof Johansson @ 2016-11-18 7:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
On Sun, Nov 13, 2016 at 12:15:31AM -0600, Andy Gross wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-defconfig-for-4.10
>
> for you to fetch changes up to a77a713395392a7f79d89e634fe3e018c4f83898:
>
> arm64: configs: enable configs for msm899(2/4) basic support (2016-11-12 22:44:09 -0600)
>
> ----------------------------------------------------------------
> Qualcomm ARM64 Based defconfig Updates for v4.10
>
> * Enable defconfig options for MSM8992/8994
>
> ----------------------------------------------------------------
> Jeremy McNicoll (1):
> arm64: configs: enable configs for msm899(2/4) basic support
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 3/3] Rockchip dts64 changes for 4.10
From: Olof Johansson @ 2016-11-18 7:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4932547.OPNQihgQS9@phil>
On Sat, Nov 12, 2016 at 04:36:25PM +0100, Heiko Stuebner wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.10-rockchip-dts64-1
>
> for you to fetch changes up to c49590691f3819bb6be3f77938ef39038eb76643:
>
> arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" (2016-11-09 15:08:55 +0100)
>
> ----------------------------------------------------------------
> 64bit devicetree changes including the px5 evaluation board
> a fix for wrong i2c registers on rk3368 a new nvmem cell and
> power-domain on rk3399 as well as moving mmc frequency
> properties to the more generic max-frequency one.
>
> ----------------------------------------------------------------
> Andy Yan (2):
> arm64: dts: rockchip: fix i2c resource error of rk3368
> arm64: dts: rockchip: Add PX5 Evaluation board
>
> Chris Zhong (1):
> arm64: dts: rockchip: add powerdomain for typec on rk3399
>
> Jaehoon Chung (1):
> arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
>
> Shawn Lin (2):
> arm64: dts: rockchip: Add more properties for emmc on px5-evb
> arm64: dts: rockchip: add sdmmc support for px5-evb
>
> Ziyuan Xu (1):
> arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 2/3] Rockchip dts32 changes for 4.10
From: Olof Johansson @ 2016-11-18 7:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2517910.T56YgEDzxC@phil>
On Sat, Nov 12, 2016 at 04:35:49PM +0100, Heiko Stuebner wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.10-rockchip-dts32-1
>
> for you to fetch changes up to 6a8883d614c7bede1075a4850139daa9723c291e:
>
> ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" (2016-11-09 14:46:04 +0100)
>
> ----------------------------------------------------------------
> 32bit devicetree changes for Rockchip including removal of skeleton.dtsi
> inclusion, missing unit names for memory nodes, various frequency
> optimizations allowing for better performance on rk3066, the usage of
> pin constants to bridge between the two numbering schemes used (gpio
> controllers using 0-31 and pins being labeled A0-A7,..., D0-D7)
> and UHS/HS modes for the mmc controllers on the popmetal board.
>
> Two new boards, the PX3-based evaluation board, with the PX3 being an
> industrial variant of the rk3188 soc and the Rikomagic MK808 board
> based around the rk3066 are also added.
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 1/3] Rockchip driver changes for 4.10
From: Olof Johansson @ 2016-11-18 7:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1698724.ZQnZMjf8xY@phil>
On Sat, Nov 12, 2016 at 04:34:17PM +0100, Heiko Stuebner wrote:
> Hi Arnd, Kevin, Olof,
>
> please find below and in the following two mails, Rockchip power-domain as
> well as dts32 and dts64 changes for 4.10.
>
> I don't think anything big stands out, just the usual mix of incremental
> improvements, so if stuff looks ok please pull.
>
>
> Thanks
> Heiko
>
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.10-rockchip-drivers1
>
> for you to fetch changes up to dabc0259db63338f0e64107cc92b2241f98a3284:
>
> soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell (2016-11-11 02:14:59 +0100)
>
> ----------------------------------------------------------------
> Changes to the power-domain driver including counter presets now being set
> by firmware on the rk3399, avoiding infite loops when powering on/off a
> domain and actually returning an error if power-domain addition fails.
> The last part requires usage of the (new in 4.9-rc1) pm_genpd_remove
> functionality as well.
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 2/2] SoCFPGA defconfig updates for v4.10
From: Olof Johansson @ 2016-11-18 7:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111205915.22173-2-dinguyen@kernel.org>
On Fri, Nov 11, 2016 at 02:59:15PM -0600, Dinh Nguyen wrote:
> Hi Arnd, Kevin, and Olof:
>
> Please pull these defconfig updates for v4.10.
>
> Thanks,
> Dinh
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_defconfig_updates_for_v4.10
>
> for you to fetch changes up to cab004fa972f06b236ba6b592bbb0512d5c6c158:
>
> ARM: socfpga_defconfig: enable FS configs to support Angstrom filesystem (2016-11-09 08:11:31 -0600)
>
> ----------------------------------------------------------------
> SoCFPGA defconfig updates for v4.10
> - enable QSPI, HIGHMEM, FPGA bridge and device-tree overlays
> - enable AUTOFS4 and NFS file system support
>
> ----------------------------------------------------------------
> Alan Tull (1):
> ARM: socfpga: updates for socfpga_defconfig
>
> Dinh Nguyen (2):
> ARM: socfpga_defconfig: Enable HIGHMEM
> ARM: socfpga_defconfig: enable FS configs to support Angstrom filesystem
>
> Steffen Trumtrar (1):
> ARM: socfpga: defconfig: enable qspi
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 1/2] SoCFPGA DTS updates for v4.10
From: Olof Johansson @ 2016-11-18 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111205915.22173-1-dinguyen@kernel.org>
On Fri, Nov 11, 2016 at 02:59:14PM -0600, Dinh Nguyen wrote:
> Hi Arnd, Kevin, and Olof:
>
> Please pull in part 2 of these DTS updates for v4.10.
>
> Thanks,
> Dinh
>
> The following changes since commit c96f5919e6b0d132aa9afe9f1adc872fc107d5bb:
>
> ARM: dts: socfpga: socrates: enable qspi (2016-10-18 22:18:14 -0500)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_dts_for_v4.10_part_2
>
> for you to fetch changes up to d837a80d19505d74ee5941eebf9dd53fed6f36a6:
>
> ARM: dts: socfpga: add nand controller nodes (2016-11-09 12:40:52 -0600)
>
> ----------------------------------------------------------------
> SoCFPGA DTS update for v4.10, part 2
> - Add specific compatible strings for variants of Cyclone5 boards
> - Add QSPI node on Arria10
> - Enable QSPI on Arria5 and Arria10 devkit, and Cyclone5 SoCKit
> - Add NAND controller node on Cyclone5
>
> ----------------------------------------------------------------
> Dinh Nguyen (6):
> ARM: dts: socfpga: add specific compatible strings for boards
> ARM: dts: socfpga: enable qspi on the Cyclone5 devkit
> ARM: dts: socfpga: Add QSPI node for the Arria10
> ARM: dts: socfpga: Enable QSPI in Arria10 devkit
> ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit
> ARM: dts: socfpga: Enable QSPI on the Arria5 devkit
>
> Steffen Trumtrar (1):
> ARM: dts: socfpga: add nand controller nodes
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/socfpga.dtsi | 13 ++++++
> arch/arm/boot/dts/socfpga_arria10.dtsi | 14 +++++++
> arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 49 ++++++++++++++++++++++
> arch/arm/boot/dts/socfpga_arria5_socdk.dts | 33 +++++++++++++++
> arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 35 +++++++++++++++-
> arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 23 +++++++++-
> arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 2 +-
> 11 files changed, 170 insertions(+), 6 deletions(-)
> create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL] STi DT update for v4.10 round 2
From: Olof Johansson @ 2016-11-18 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <828ebfb1-7ed0-8e6b-116d-9ef74d804db6@st.com>
On Thu, Nov 10, 2016 at 10:00:48AM +0100, Patrice Chotard wrote:
> Hi Arnd, Kevin, Olof
>
> PLease consider this second round of STi dts update for v4.10 :
>
> The following changes since commit 97a0b97f9e8197429eee5f87ce14373f73dbd9d3:
>
> ARM: dts: stih410-clocks: Add PROC_STFE as a critical clock (2016-10-20 16:20:26 +0200)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git tags/sti-dt-for-4.10-round2
>
> for you to fetch changes up to 64783ea7de0bff3de77cfdff1ed76428c288faac:
>
> ARM: dts: STiHxxx-b2120: change sound card name (2016-11-10 09:52:49 +0100)
>
> ----------------------------------------------------------------
> STi dts update:
>
> Change sound card name for B2120
> Enable sound card for B2260
> Remove stih415-clks.h
> Identify critical clocks for STiH407
> Fix typo in stih407-pinctrl.dtsi
>
> ----------------------------------------------------------------
> Arnaud Pouliquen (2):
> ARM: dts: STiH410-B2260: enable sound card
> ARM: dts: STiHxxx-b2120: change sound card name
>
> Geert Uytterhoeven (1):
> ARM: dts: STiH407: DT fix s/interrupts-names/interrupt-names/
>
> Patrice Chotard (1):
> ARM: dts: remove stih415-clks.h
>
> Peter Griffin (1):
> ARM: dts: stih407-clocks: Identify critical clocks
>
> arch/arm/boot/dts/stih407-clock.dtsi | 10 ++++++++++
> arch/arm/boot/dts/stih407-pinctrl.dtsi | 2 +-
> arch/arm/boot/dts/stih410-b2260.dts | 22 ++++++++++++++++++++++
> arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +-
> include/dt-bindings/clock/stih415-clks.h | 16 ----------------
> 5 files changed, 34 insertions(+), 18 deletions(-)
> delete mode 100644 include/dt-bindings/clock/stih415-clks.h
>
>
>
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL] STi defconfig updates for v4.10 round 2
From: Olof Johansson @ 2016-11-18 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <919f7b55-a2cd-fc20-a1cd-4d3f309fd60d@st.com>
On Thu, Nov 10, 2016 at 10:00:32AM +0100, Patrice Chotard wrote:
> Hi Olof, Arnd and Kevin,
>
> Please consider the second round of multi_v7_defconfig updates for v4.10 :
>
>
> The following changes since commit 620c52f4db4d47e1f33c64e641392fe575d5397f:
>
> ARM: multi_v7_defconfig: Remove stih41x phy Kconfig symbol. (2016-10-20 17:05:08 +0200)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git sti-defconfig-for-4.10-round2
>
> for you to fetch changes up to 57dae748959d0abae2b382ccee68621a82f827c8:
>
> ARM: multi_v7_defconfig: Remove ST_THERMAL_SYSCFG Kconfig symbol (2016-10-21 17:05:54 +0200)
>
> ----------------------------------------------------------------
>
> Remove STiH415/416 specific IPs
>
> As STiH415/416 have been removed from kernel, remove IPs only
> found on these socs, remove ST_THERMAL_SYSCFG.
Merged, thanks.
-Olof
^ permalink raw reply
* [PATCH] ARM: integrator: drop EBI access use syscon
From: Olof Johansson @ 2016-11-18 7:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478679126-5460-1-git-send-email-linus.walleij@linaro.org>
On Wed, Nov 09, 2016 at 09:12:06AM +0100, Linus Walleij wrote:
> The EBI lookup is not longer in use: this has been moved to the
> NAND chip driver. The syscon node is better accessed indirectly
> using the regmap like the NAND chip driver does, so let's use
> the syscon to set the modem control signals RTS/CTS through the
> dedicated syscon register.
>
> We also migrate the decoder status "SC_DEC" register that
> enumerate the logic modules using syscon.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ARM SoC folks: please apply this patch directly to the tree
> wherever it fits. I do not plan to send more Integrator patches
> this merge window.
Thanks, applied!
-Olof
^ permalink raw reply
* [GIT PULL] Integrator DTS and defconfig changes
From: Olof Johansson @ 2016-11-18 7:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdara5D=kvGVYu-WRh_JYK6Z9NKmQ-eniXsauxdzx-QJbA@mail.gmail.com>
Hi Linus,
On Wed, Nov 09, 2016 at 09:10:35AM +0100, Linus Walleij wrote:
> Hi ARM SoC folks,
>
> this adds DT-based cpufreq to the Integrator family.
>
> The corresponding cpufreq changes are merged by Rafael to the
> cpufreq tree, and can go in orthogonally.
>
> However I have included the defconfig change turning on the feature
> here as it makes all kind of logic sense to have these three patches
> in succession: addin the DTS nodes and then turning on the DT
> cpufreq.
>
> If you insist, of course I can send the defconfig patch separately.
> I just think it makes more sense like this.
>
> Please pull it in so we get some rotation in linux-next for this!
Hmm.
I understand that it makes sense for your platform do turn on the option
at the same time as adding the DT entries, but there's nothing that should
require them to go in together (they just won't be used until both branches are
in).
We try to keep our categories of patches separate in the arm-soc tree;
keeping SoC changes, driver changes, DT changes and defconfig changes
is from a general code hygiene point of view beneficial and we encourage all
platform maintainers to follow those guidelines.
I also sympathize that it's extra annoying having to split just three
patches across two branches. So, if it's easier we can just cherry-pick
apart the patches here across the branches (your comment about next
coverage makes me suspect you have no direct downstream users of this
branch). If that's OK, let me know and I'll do that tomorrow.
Cheers,
-Olof
^ permalink raw reply
* [GIT PULL] pxa-dt for v4.10
From: Olof Johansson @ 2016-11-18 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8760nxwqs0.fsf@belgarion.home>
Hi,
On Tue, Nov 08, 2016 at 11:27:59PM +0100, Robert Jarzmik wrote:
> Hi Arnd, Kevin, and Olof,
>
> This is the pxa pull request for 4.10 device-tree, can you please consider
> pulling ?
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> https://github.com/rjarzmik/linux.git tags/pxa-dt-4.10
>
> for you to fetch changes up to f409d2f134d499354dca0613693f27d8efd75c74:
>
> ARM: dts: pxa: add pxa27x cpu operating points (2016-11-02 22:52:45 +0100)
>
> ----------------------------------------------------------------
> This device-tree pxa update brings :
> - pxa25x support
> - cpu operating points in preparation for cpufreq-dt
> - small fixes
>
> ----------------------------------------------------------------
> Robert Jarzmik (4):
> ARM: dts: add pxa25x .dtsi file
> ARM: dts: pxa: fix gpio0 and gpio1 interrupts
> ARM: dts: pxa: add pxa25x cpu operating points
> ARM: dts: pxa: add pxa27x cpu operating points
>
> Vijay Kumar (1):
> Fix no. of gpio cells in the pxa gpio binding doucmentation
This isn't the right patch subject. Please use standard prefix format
here (ARM: dts: pxa: ...).
Please respin this branch and post a fresh pull request. Thanks!
-Olof
^ permalink raw reply
* [GIT PULL] pxa for v4.10
From: Olof Johansson @ 2016-11-18 7:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87a8d9wr6d.fsf@belgarion.home>
On Tue, Nov 08, 2016 at 11:19:22PM +0100, Robert Jarzmik wrote:
> Hello Arnd, Kevin, Olof,
>
> Please consider this pull request for pxa 4.10 cycle. This pull request strides
> off from my usual ones as its spans more than just mach-pxa.
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> https://github.com/rjarzmik/linux.git tags/pxa-for-4.10
>
> for you to fetch changes up to e413bd33ac44b6d0bebc0ef2ac19cbe7558a7303:
>
> ARM: pxa: fix pxa25x interrupt init (2016-11-05 21:48:18 +0100)
>
> ----------------------------------------------------------------
> This is the pxa changes for v4.10 cycle.
>
> This cycle is covering :
> - some clock fixes common with sa1100 architecture
> - the consequence of the pxa_camera conversion to v4l2
> - a small irq related fix for pxa25x device-tree only
Thanks, merged.
-Olof
^ permalink raw reply
* [PATCH v2] ARM: Drop fixed 200 Hz timer requirement from Samsung platforms
From: Krzysztof Kozlowski @ 2016-11-18 7:16 UTC (permalink / raw)
To: linux-arm-kernel
All Samsung platforms, including the Exynos, are selecting HZ_FIXED with
200 Hz. Unfortunately in case of multiplatform image this affects also
other platforms when Exynos is enabled.
This looks like an very old legacy code, dating back to initial
upstreaming of S3C24xx. Probably it was required for s3c24xx timer
driver, which was removed in commit ad38bdd15d5b ("ARM: SAMSUNG: Remove
unused plat-samsung/time.c").
Since then, this fixed 200 Hz spread everywhere, including out-of-tree
Samsung kernels (SoC vendor's and Tizen's). I believe this choice
was rather an effect of coincidence instead of conscious choice.
Exynos uses its own MCT or arch timer and can work with all HZ values.
Older platforms use newer Samsung PWM timer driver which should handle
down to 100 Hz.
Few perf mem and sched tests on Odroid XU3 board (Exynos5422, 4x Cortex
A7, 4x Cortex A15) show no regressions when switching from 200 Hz to
other values.
Reported-by: Lee Jones <lee.jones@linaro.org>
[Dropping 200_HZ from S3C/S5P suggested by Arnd]
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Kukjin Kim <kgene@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Tested on Exynos5422 and Exynos5800 (by Javier). It would be
appreciated if anyone could test it on S3C24xx or S5PV210.
Changes since v1:
1. Add Javier's tested-by.
2. Drop HZ_FIXED also from ARCH_S5PV210 and ARCH_S3C24XX after Arnd
suggestions and analysis.
---
arch/arm/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b5d529fdffab..ced2e08a9d08 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1496,8 +1496,7 @@ source kernel/Kconfig.preempt
config HZ_FIXED
int
- default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
- ARCH_S5PV210 || ARCH_EXYNOS4
+ default 200 if ARCH_EBSA110
default 128 if SOC_AT91RM9200
default 0
--
2.7.4
^ permalink raw reply related
* [PATCH] clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it
From: Chen-Yu Tsai @ 2016-11-18 7:15 UTC (permalink / raw)
To: linux-arm-kernel
The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.
Add the 2 LDO enable bits to the gate bits. This fixes issues with
the TCON not sending vblank interrupts when the tcon and dot clock are
indirectly clocked from the PLL-MIPI clock.
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
This can be queued for either 4.9 or 4.10.
The clock driver was introduced in 4.9,
but the users won't appear until 4.10.
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 4a82a49cff5e..fc75a335a7ce 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -143,7 +143,7 @@ static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
4, 2, /* K */
0, 4, /* M */
21, 0, /* mux */
- BIT(31), /* gate */
+ BIT(31) | BIT(23) | BIT(22), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
--
2.10.2
^ permalink raw reply related
* [PATCH] ARM: Drop fixed 200 Hz timer requirement from Exynos platforms
From: Krzysztof Kozlowski @ 2016-11-18 6:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3145378.USf2WOPoV2@wuerfel>
On Thu, Nov 17, 2016 at 01:35:45PM +0100, Arnd Bergmann wrote:
> On Monday, November 14, 2016 8:27:05 PM CET Krzysztof Kozlowski wrote:
> > @@ -1497,7 +1497,7 @@ source kernel/Kconfig.preempt
> > config HZ_FIXED
> > int
> > default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
> > - ARCH_S5PV210 || ARCH_EXYNOS4
> > + ARCH_S5PV210
> > default 128 if SOC_AT91RM9200
> > default 0
>
> After further research, I've concluded that we should also drop the
> settings for ARCH_S5PV210 and ARCH_S3C24XX here.
>
> ARCH_S5PV210 behaves exactly like EXYNOS here, it has 32-bit timers
> so there won't be any overflow with 100Hz.
>
> For ARCH_S3C24XX, it the requirement was that HZ_100 could not
> be used with the old arch/arm/plat-samsung/time.c code that would
> overflow its 16-bit counter.
> However, the new drivers/clocksource/samsung_pwm_timer.c configures
> the clock divider to '50' instead of '6', so there is no longer
> a 16-bit overflow before the 100Hz tick, it now overflows every
> 3.7ms for the typical 12MHz clock.
I can send an updated version however testing would be nice... I know
Sylwester has a S3C6410 platform running, maybe S3C24xx as well.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 1/3] arm: hisi: add ARCH_MULTI_V5 support
From: Jiancheng Xue @ 2016-11-18 6:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <114569cb-79ab-a46d-8582-6169f182a32c@hisilicon.com>
Hi Marty,
On 2016/11/17 11:03, Jiancheng Xue wrote:
> Hi Wei?
>
> On 2016/11/16 17:31, Wei Xu wrote:
>> Hi Pan,
>>
>> On 2016/11/16 8:56, wenpan wrote:
>>> Hi Marty?
>>> Does this confict with your patch? If not?I hope this could be merged first. Besides could you tell me the link to your related patch?
>>
>> This is the link: https://patchwork.kernel.org/patch/9334743/
>>
Could you give your comments on this patch?
If you have any objections to it, please let us know.
>
> Thank you for offering this.If I want to give some comments on Marty's patch,
> what should I do?
>
> For Marty's patch, I think there's no need to add specific config item ARCH_HIxxxx
> for every chipset. Some existing chipsets depend on ARCH_HISI directly like Hi3519
> and Hi3798CV200. If some options like ARM_GIC is removed from ARCH_HISI, this kind
> of chipsets will must choose other place to select it. I suggest we should keep selecting
> ARM_GIC under ARCH_HISI as Pan's patch do.
>
> The code may be like this:
>
> config ARCH_HISI
> bool "Hisilicon SoC Support"
> - depends on ARCH_MULTI_V7
> + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7
> select ARM_AMBA
> - select ARM_GIC
> + select ARM_GIC if ARCH_MULTI_V7
> + select ARM_VIC if ARCH_MULTI_V5 || depends on ARCH_MULTI_V6
> select ARM_TIMER_SP804
> select POWER_RESET
> select POWER_RESET_HISI
> select POWER_SUPPLY
>
What's your opinion about this?
Best Regards,
Jiancheng
>>> On 2016/10/17 21:48, Arnd Bergmann wrote:
>>>> On Monday, October 17, 2016 8:07:03 PM CEST Pan Wen wrote:
>>>>> Add support for some HiSilicon SoCs which depend on ARCH_MULTI_V5.
>>>>>
>>>>> Signed-off-by: Pan Wen <wenpan@hisilicon.com>
>>>>>
>>>>
>>>> Looks ok. I've added Marty Plummer to Cc, he was recently proposing
>>>> patches for Hi3520, which I think is closely related to this one.
>>>> Please try to work together so the patches don't conflict. It should
>>>> be fairly straightforward since you are basically doing the same
>>>> change here.
>>>>
>
>
>
> .
>
^ permalink raw reply
* [PATCH] kirkwood: fix spelling mistake
From: p.wassi at gmx.at @ 2016-11-18 6:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117210227.GL5574@lunn.ch>
Hi Andrew,
> You should also send the patch to the Marvell MVEBU
> maintainers.
how do I find Marvell mvebu maintainers?
The list in
https://www.kernel.org/doc/linux/MAINTAINERS
(line 1429) references mvebu/kirkwood and gave me the
mailing list's address. Should the other two maintainers
be addressed directly?
Best regards,
P. Wassi
^ permalink raw reply
* [RFC v3 00/10] KVM PCIe/MSI passthrough on ARM/ARM64 and IOVA reserved regions
From: Bharat Bhushan @ 2016-11-18 5:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479215363-2898-1-git-send-email-eric.auger@redhat.com>
Hi Eric,
Have you sent out QEMU side patches based on this new approach? In case I missed please point me the patches?
Thanks
-Bharat
> -----Original Message-----
> From: iommu-bounces at lists.linux-foundation.org [mailto:iommu-
> bounces at lists.linux-foundation.org] On Behalf Of Eric Auger
> Sent: Tuesday, November 15, 2016 6:39 PM
> To: eric.auger at redhat.com; eric.auger.pro at gmail.com;
> christoffer.dall at linaro.org; marc.zyngier at arm.com;
> robin.murphy at arm.com; alex.williamson at redhat.com;
> will.deacon at arm.com; joro at 8bytes.org; tglx at linutronix.de;
> jason at lakedaemon.net; linux-arm-kernel at lists.infradead.org
> Cc: drjones at redhat.com; kvm at vger.kernel.org; punit.agrawal at arm.com;
> linux-kernel at vger.kernel.org; iommu at lists.linux-foundation.org;
> pranav.sawargaonkar at gmail.com
> Subject: [RFC v3 00/10] KVM PCIe/MSI passthrough on ARM/ARM64 and
> IOVA reserved regions
>
> Following LPC discussions, we now report reserved regions through iommu-
> group sysfs reserved_regions attribute file.
>
> Reserved regions are populated through the IOMMU get_resv_region
> callback (former get_dm_regions), now implemented by amd-iommu, intel-
> iommu and arm-smmu.
>
> The intel-iommu reports the [FEE0_0000h - FEF0_000h] MSI window as an
> IOMMU_RESV_NOMAP reserved region.
>
> arm-smmu reports the MSI window (arbitrarily located at 0x8000000 and 1MB
> large) and the PCI host bridge windows.
>
> The series integrates a not officially posted patch from Robin:
> "iommu/dma: Allow MSI-only cookies".
>
> This series currently does not address IRQ safety assessment.
>
> Best Regards
>
> Eric
>
> Git: complete series available at
> https://github.com/eauger/linux/tree/v4.9-rc5-reserved-rfc-v3
>
> History:
> RFC v2 -> v3:
> - switch to an iommu-group sysfs API
> - use new dummy allocator provided by Robin
> - dummy allocator initialized by vfio-iommu-type1 after enumerating
> the reserved regions
> - at the moment ARM MSI base address/size is left unchanged compared
> to v2
> - we currently report reserved regions and not usable IOVA regions as
> requested by Alex
>
> RFC v1 -> v2:
> - fix intel_add_reserved_regions
> - add mutex lock/unlock in vfio_iommu_type1
>
>
> Eric Auger (10):
> iommu/dma: Allow MSI-only cookies
> iommu: Rename iommu_dm_regions into iommu_resv_regions
> iommu: Add new reserved IOMMU attributes
> iommu: iommu_alloc_resv_region
> iommu: Do not map reserved regions
> iommu: iommu_get_group_resv_regions
> iommu: Implement reserved_regions iommu-group sysfs file
> iommu/vt-d: Implement reserved region get/put callbacks
> iommu/arm-smmu: Implement reserved region get/put callbacks
> vfio/type1: Get MSI cookie
>
> drivers/iommu/amd_iommu.c | 20 +++---
> drivers/iommu/arm-smmu.c | 52 +++++++++++++++
> drivers/iommu/dma-iommu.c | 116 ++++++++++++++++++++++++++----
> ---
> drivers/iommu/intel-iommu.c | 50 ++++++++++----
> drivers/iommu/iommu.c | 141
> ++++++++++++++++++++++++++++++++++++----
> drivers/vfio/vfio_iommu_type1.c | 26 ++++++++
> include/linux/dma-iommu.h | 7 ++
> include/linux/iommu.h | 49 ++++++++++----
> 8 files changed, 391 insertions(+), 70 deletions(-)
>
> --
> 1.9.1
>
> _______________________________________________
> iommu mailing list
> iommu at lists.linux-foundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* [PATCH v5] drm/mediatek: fixed the calc method of data rate per lane
From: CK Hu @ 2016-11-18 5:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGS+omBpdRH5ZnvcApX_pevwSBHwUon77DhhjX0p9aQXuOy4DA@mail.gmail.com>
Hi, Daniel:
On Fri, 2016-11-18 at 11:22 +0800, Daniel Kurtz wrote:
> Hi CK,
>
> On Thu, Nov 17, 2016 at 1:36 PM, CK Hu <ck.hu@mediatek.com> wrote:
> > Hi, Jitao:
> >
> >
> > On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote:
> >> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e.
> >> Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP
> >> mode, those signals will cause h-time larger than normal and reduce FPS.
> >> So need to multiply a coefficient to offset the extra signal's effect.
> >> coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+
> >> Ths_trail+Ths_exit)/(htotal*bpp/lane_number)
> >>
> >> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> >
> > It looks good to me.
> > But this patch conflict with [1] which is one patch of MT2701 series. I
> > want to apply MT2701 patches first, so please help to refine this patch
> > based on MT2701 patches.
>
> I don't think the MT2701 DSI patches are quite ready yet (I just
> reviewed the one below).
> Can we instead land Jitao's small targeted change first, and then
> rebase the MT2701 series on top.
>
> Thanks,
> -Dan
MT2701 series looks still have some defect to be fixed.
Therefore, I would apply this patch first.
Thanks for your help.
Regards,
CK
> >
> > [1] https://patchwork.kernel.org/patch/9422821/
> >
> > Regards,
> > CK
> >
> >> ---
> >> Change since v4:
> >> - tune the calc comment more clear.
> >> - define the phy timings as constants.
> >>
> >> Chnage since v3:
> >> - wrapp the commit msg.
> >> - fix alignment of some lines.
> >>
> >> Change since v2:
> >> - move phy timing back to dsi_phy_timconfig.
> >>
> >> Change since v1:
> >> - phy_timing2 and phy_timing3 refer clock cycle time.
> >> - define values of LPX HS_PRPR HS_ZERO HS_TRAIL TA_GO TA_SURE TA_GET DA_HS_EXIT.
> >> ---
> >>
> >
^ permalink raw reply
* [PATCH v9 02/10] drm/mediatek: add *driver_data for different hardware settings
From: Daniel Kurtz @ 2016-11-18 4:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478865346-19043-3-git-send-email-yt.shen@mediatek.com>
Hi YT,
I don't see a reason to handle device_data in such a generic way at
the generic mtk_ddp_comp layer.
The device data is very component specific, so just define different
structs for different comp types, ie:
struct mtk_disp_ovl_driver_data {
unsigned int reg_ovl_addr;
unsigned int fmt_rgb565;
unsigned int fmt_rgb888;
};
struct mtk_disp_rdma_driver_data {
unsigned int fifo_pseudo_size;
};
struct mtk_disp_color_driver_data {
unsigned int color_offset;
};
Then add typed pointers to the local structs that use them, for example:
struct mtk_disp_ovl {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_ovl_driver_data *data;
};
And fetch the device specific driver data directly in .probe, as you
are already doing:
static int mtk_disp_ovl_probe(struct platform_device *pdev) {
...
priv->data = of_device_get_match_data(dev);
...
}
More comments in-line...
On Fri, Nov 11, 2016 at 7:55 PM, YT Shen <yt.shen@mediatek.com> wrote:
> There are some hardware settings changed, between MT8173 & MT2701:
> DISP_OVL address offset changed, color format definition changed.
> DISP_RDMA fifo size changed.
> DISP_COLOR offset changed.
> MIPI_TX pll setting changed.
> And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod.
Nit: I think it would make sense to combine this patch with
drm/mediatek: rename macros, add chip prefix
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 27 ++++++++++++++++-----------
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 11 +++++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 11 +++++++----
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 27 +++++++++++++++++++++------
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 13 +++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 25 ++++++++++++++++++-------
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 ++++++++
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 24 +++++++++++++++++++++++-
> 8 files changed, 115 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 019b7ca..1139834 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -35,13 +35,10 @@
> #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
> -#define DISP_REG_OVL_ADDR(n) (0x0f40 + 0x20 * (n))
Also, I would still use the "#define macros", for example
"DISP_REG_OVL_ADDR offsets, and use the named constant in the
driver_data:
#define DISP_REG_OVL_ADDR_MT8173 0x0f40
(and in a later patch:
#define DISP_REG_OVL_ADDR_MT2701 0x0040
)
Also, I would still use the macro rather than open coding the "0x20 *
(n)", and just pass 'ovl' to the overlay macros that depend on
hardware type.
Something like the following:
#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->ovl_addr + 0x20 * (n))
>
> #define OVL_RDMA_MEM_GMC 0x40402020
>
> #define OVL_CON_BYTE_SWAP BIT(24)
> -#define OVL_CON_CLRFMT_RGB565 (0 << 12)
> -#define OVL_CON_CLRFMT_RGB888 (1 << 12)
This seems like a really random and unnecessary hardware change.
Why chip designers, why!!?!?
For this one, it seems the polarity is either one way or the other, so
we can just use a bool to distinguish:
bool fmt_rgb565_is_0;
> +static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = {
> + .ovl = { DISP_REG_OVL_ADDR_MT8173, .fmt_rgb565_is_0 = true }
> +};
For use at runtime, the defines could become:
#define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? 0
: OVL_CON_CLRFMT_RGB888)
#define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ?
OVL_CON_CLRFMT_RGB888 : 0)
> #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
> #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
> #define OVL_CON_AEN BIT(8)
> @@ -137,18 +134,18 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
> writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
> }
>
> -static unsigned int ovl_fmt_convert(unsigned int fmt)
> +static unsigned int ovl_fmt_convert(struct mtk_ddp_comp *comp, unsigned int fmt)
> {
> switch (fmt) {
> default:
> case DRM_FORMAT_RGB565:
> - return OVL_CON_CLRFMT_RGB565;
> + return comp->data->ovl.fmt_rgb565;
It will be nice to define a helper function for converting from the
generic 'mtk_ddp_comp' to the specific 'mtk_disp_ovl':
static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp) {
return container_of(comp, struct mtk_disp_ovl, ddp_comp);
}
Then these could become:
return OVL_CON_CLRFMT_RGB565(comp_to_ovl(comp));
Or maybe cleaner, do the conversion once at the top of the function:
struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
And then just:
return OVL_CON_CLRFMT_RGB565(ovl);
> case DRM_FORMAT_BGR565:
> - return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
> + return comp->data->ovl.fmt_rgb565 | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_RGB888:
> - return OVL_CON_CLRFMT_RGB888;
> + return comp->data->ovl.fmt_rgb888;
> case DRM_FORMAT_BGR888:
> - return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
> + return comp->data->ovl.fmt_rgb888 | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_RGBX8888:
> case DRM_FORMAT_RGBA8888:
> return OVL_CON_CLRFMT_ARGB8888;
[snip]
> diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> index 1c366f8..935a8ef 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> @@ -16,6 +16,7 @@
> #include <linux/delay.h>
> #include <linux/io.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
>
> @@ -87,6 +88,9 @@
>
> #define MIPITX_DSI_PLL_CON2 0x58
>
> +#define MIPITX_DSI_PLL_TOP 0x64
> +#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
> +
> #define MIPITX_DSI_PLL_PWR 0x68
> #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
> #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
> @@ -123,10 +127,15 @@
> #define SW_LNT2_HSTX_PRE_OE BIT(24)
> #define SW_LNT2_HSTX_OE BIT(25)
>
> +struct mtk_mipitx_data {
> + const u32 data;
Use a better name, like "mppll_preserve".
Ok, that's it for now.
Actually, the patch set in general looks pretty good.
-Dan
^ permalink raw reply
* [RFC 6/6] ARM: dts: am57xx-beagle-x15-common: enable etnaviv
From: Nishanth Menon @ 2016-11-18 4:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOCHtYh8QebrYA2ioaXgURdc47QY4x+EwZLBXLLGP1-k7eAMmw@mail.gmail.com>
On 11/17/2016 10:26 PM, Robert Nelson wrote:
[...]
> Oh yeah, defintely, we can move gpu-subsystem to the base dra7.dtsi,
> as the whole dra.dtsi family has a gc320 and then the board device
> tree can enable it via:
>
> &bb2d {
> status = "okay";
> };
Yep, thanks.
--
Regards,
Nishanth Menon
^ permalink raw reply
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