* [GIT PULL 2/5] i.MX soc updates for 4.10
From: Olof Johansson @ 2016-11-18 17:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-2-git-send-email-shawnguo@kernel.org>
On Tue, Nov 15, 2016 at 05:00:28PM +0800, Shawn Guo wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-soc-4.10
>
> for you to fetch changes up to 75b832fea2564c547dfd0a2377a5893f41aefec6:
>
> ARM: imx: mach-imx6ul: add imx6ull support (2016-11-15 08:58:43 +0800)
>
> ----------------------------------------------------------------
> i.MX SoC changes for 4.10:
> - Drop PL310_ERRATA_769419 for Vybrid, as it turns out that the SoC
> integrates revision r3p2 of the L2C-310, which is not affected by
> errata 769419.
> - Support perf for i.MX6 Multi-Mode DDR Controller (MMDC), so that we
> can profile memory access performance.
> - Support i.MX6ULL SoC using i.MX6UL base, since it's a derivative of
> i.MX6UL and pin-to-pin compatible with i.MX6UL.
Merged, thanks.
-Olof
^ permalink raw reply
* [PATCH 1/3] dt-bindings: Add Macnica Americas vendor prefix
From: Rob Herring @ 2016-11-18 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CADhT+wcesJRSf0q+_BDEmtsMTAO2LcAPkqjsRW2mNc1znMp4qg@mail.gmail.com>
On Fri, Nov 18, 2016 at 10:25 AM, Dinh Nguyen <dinh.linux@gmail.com> wrote:
> Hi Rob,
>
> On Tue, Nov 1, 2016 at 10:36 AM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>> Add a vendor prefix for the Macnica company.
>> http://http://www.macnica.com
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> index f0a48ea..81674f2 100644
>> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
>> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> @@ -158,6 +158,7 @@ lg LG Corporation
>> linux Linux-specific binding
>> lltc Linear Technology Corporation
>> lsi LSI Corp. (LSI Logic)
>> +macnica Macnica Americas
>> marvell Marvell Technology Group Ltd.
>> maxim Maxim Integrated Products
>> meas Measurement Specialties
>> --
>> 2.8.3
>
> Just a gentle ping.
Sorry, didn't send anything out, but the series is already applied if
you look at -next or PW.
Rob
^ permalink raw reply
* [PATCH v8 13/16] drivers: iommu: arm-smmu: add IORT configuration
From: Lorenzo Pieralisi @ 2016-11-18 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <83df7dba-8d04-96ae-f59b-b0d484085e12@arm.com>
On Fri, Nov 18, 2016 at 05:36:46PM +0000, Robin Murphy wrote:
> On 16/11/16 15:29, Lorenzo Pieralisi wrote:
> > In ACPI bases systems, in order to be able to create platform
>
> based?
Ok.
> > devices and initialize them for ARM SMMU components, the IORT
> > kernel implementation requires a set of static functions to be
> > used by the IORT kernel layer to configure platform devices for
> > ARM SMMU components.
> >
> > Add static configuration functions to the IORT kernel layer for
> > the ARM SMMU components, so that the ARM SMMU driver can
> > initialize its respective platform device by relying on the IORT
> > kernel infrastructure and by adding a corresponding ACPI device
> > early probe section entry.
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Reviewed-by: Tomasz Nowicki <tn@semihalf.com>
> > Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
> > Tested-by: Tomasz Nowicki <tn@semihalf.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: Robin Murphy <robin.murphy@arm.com>
> > Cc: Joerg Roedel <joro@8bytes.org>
> > ---
> > drivers/acpi/arm64/iort.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
> > drivers/iommu/arm-smmu.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++-
> > include/linux/acpi_iort.h | 3 ++
> > 3 files changed, 166 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> > index fd52e4c..4708806 100644
> > --- a/drivers/acpi/arm64/iort.c
> > +++ b/drivers/acpi/arm64/iort.c
> > @@ -548,6 +548,78 @@ static bool __init arm_smmu_v3_is_coherent(struct acpi_iort_node *node)
> > return smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE;
> > }
> >
> > +static int __init arm_smmu_count_resources(struct acpi_iort_node *node)
> > +{
> > + struct acpi_iort_smmu *smmu;
> > + int num_irqs;
> > + u64 *glb_irq;
> > +
> > + /* Retrieve SMMU specific data */
> > + smmu = (struct acpi_iort_smmu *)node->node_data;
> > +
> > + glb_irq = ACPI_ADD_PTR(u64, node, smmu->global_interrupt_offset);
> > + if (!IORT_IRQ_MASK(glb_irq[1])) /* 0 means not implemented */
> > + num_irqs = 1;
> > + else
> > + num_irqs = 2;
>
> Do we actually need this - I mean, the configuration access interrupt is
> of somewhat limited utility, implementation-defined, and we don't have
> any handling for it. Nor should it, if present, ever happen anyway,
> since it's not like anyone else should be randomly poking our SMMU in
> invalid ways. Can we simply ignore it?
I added its parsing to bring the same capabilities present in DT to
ACPI, from what you are saying I think that we'd better ignore it
and add its parsing later if we _ever_ need to handle it.
> > +
> > + num_irqs += smmu->context_interrupt_count;
> > +
> > + return num_irqs + 1;
> > +}
> > +
> > +static void __init arm_smmu_init_resources(struct resource *res,
> > + struct acpi_iort_node *node)
> > +{
> > + struct acpi_iort_smmu *smmu;
> > + int i, hw_irq, trigger, num_res = 0;
> > + u64 *ctx_irq, *glb_irq;
> > +
> > + /* Retrieve SMMU specific data */
> > + smmu = (struct acpi_iort_smmu *)node->node_data;
> > +
> > + res[num_res].start = smmu->base_address;
> > + res[num_res].end = smmu->base_address + smmu->span - 1;
> > + res[num_res].flags = IORESOURCE_MEM;
> > + num_res++;
> > +
> > + glb_irq = ACPI_ADD_PTR(u64, node, smmu->global_interrupt_offset);
> > + /* Global IRQs */
> > + hw_irq = IORT_IRQ_MASK(glb_irq[0]);
> > + trigger = IORT_IRQ_TRIGGER_MASK(glb_irq[0]);
> > +
> > + acpi_iort_register_irq(hw_irq, "arm-smmu-global", trigger,
> > + &res[num_res++]);
> > +
> > + /* Global IRQs */
> > + hw_irq = IORT_IRQ_MASK(glb_irq[1]);
> > + if (hw_irq) {
> > + trigger = IORT_IRQ_TRIGGER_MASK(glb_irq[1]);
> > + acpi_iort_register_irq(hw_irq, "arm-smmu-global", trigger,
> > + &res[num_res++]);
> > + }
>
> Related to the above, I think the driver generally assumes these to be
> the global fault interrupt. If we *are* going to claim the config
> interrupt as well, we should probably disambiguate them, although
> admittedly we can't really do that retrospectively on the DT side.
I do not think we are missing functionality if for the time being
we just ignore the configuration access interrupt so that's what
I will do for this first version.
Thanks !
Lorenzo
> > +
> > + /* Context IRQs */
> > + ctx_irq = ACPI_ADD_PTR(u64, node, smmu->context_interrupt_offset);
> > + for (i = 0; i < smmu->context_interrupt_count; i++) {
> > + hw_irq = IORT_IRQ_MASK(ctx_irq[i]);
> > + trigger = IORT_IRQ_TRIGGER_MASK(ctx_irq[i]);
> > +
> > + acpi_iort_register_irq(hw_irq, "arm-smmu-context", trigger,
> > + &res[num_res++]);
> > + }
> > +}
> > +
> > +static bool __init arm_smmu_is_coherent(struct acpi_iort_node *node)
> > +{
> > + struct acpi_iort_smmu *smmu;
> > +
> > + /* Retrieve SMMU specific data */
> > + smmu = (struct acpi_iort_smmu *)node->node_data;
> > +
> > + return smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK;
> > +}
> > +
> > struct iort_iommu_config {
> > const char *name;
> > int (*iommu_init)(struct acpi_iort_node *node);
> > @@ -564,12 +636,21 @@ static const struct iort_iommu_config iort_arm_smmu_v3_cfg __initconst = {
> > .iommu_init_resources = arm_smmu_v3_init_resources
> > };
> >
> > +static const struct iort_iommu_config iort_arm_smmu_cfg __initconst = {
> > + .name = "arm-smmu",
> > + .iommu_is_coherent = arm_smmu_is_coherent,
> > + .iommu_count_resources = arm_smmu_count_resources,
> > + .iommu_init_resources = arm_smmu_init_resources
> > +};
> > +
> > static __init
> > const struct iort_iommu_config *iort_get_iommu_cfg(struct acpi_iort_node *node)
> > {
> > switch (node->type) {
> > case ACPI_IORT_NODE_SMMU_V3:
> > return &iort_arm_smmu_v3_cfg;
> > + case ACPI_IORT_NODE_SMMU:
> > + return &iort_arm_smmu_cfg;
> > default:
> > return NULL;
> > }
> > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> > index 573b2b6..21d1892 100644
> > --- a/drivers/iommu/arm-smmu.c
> > +++ b/drivers/iommu/arm-smmu.c
> > @@ -28,6 +28,8 @@
> >
> > #define pr_fmt(fmt) "arm-smmu: " fmt
> >
> > +#include <linux/acpi.h>
> > +#include <linux/acpi_iort.h>
> > #include <linux/atomic.h>
> > #include <linux/delay.h>
> > #include <linux/dma-iommu.h>
> > @@ -1904,6 +1906,70 @@ static const struct of_device_id arm_smmu_of_match[] = {
> > };
> > MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
> >
> > +#ifdef CONFIG_ACPI
> > +static int acpi_smmu_get_data(u32 model, u32 *version, u32 *impl)
> > +{
> > + int ret = 0;
> > +
> > + switch (model) {
> > + case ACPI_IORT_SMMU_V1:
> > + case ACPI_IORT_SMMU_CORELINK_MMU400:
> > + *version = ARM_SMMU_V1;
> > + *impl = GENERIC_SMMU;
>
> Further to Will's comment, I'd say just pass the smmu pointer in and set
> the fields explicitly here.
>
> Robin.
>
> > + break;
> > + case ACPI_IORT_SMMU_V2:
> > + *version = ARM_SMMU_V2;
> > + *impl = GENERIC_SMMU;
> > + break;
> > + case ACPI_IORT_SMMU_CORELINK_MMU500:
> > + *version = ARM_SMMU_V2;
> > + *impl = ARM_MMU500;
> > + break;
> > + default:
> > + ret = -ENODEV;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
> > + struct arm_smmu_device *smmu)
> > +{
> > + struct device *dev = smmu->dev;
> > + struct acpi_iort_node *node =
> > + *(struct acpi_iort_node **)dev_get_platdata(dev);
> > + struct acpi_iort_smmu *iort_smmu;
> > + u64 *glb_irq;
> > + int ret;
> > +
> > + /* Retrieve SMMU1/2 specific data */
> > + iort_smmu = (struct acpi_iort_smmu *)node->node_data;
> > +
> > + ret = acpi_smmu_get_data(iort_smmu->model, &smmu->version,
> > + &smmu->model);
> > + if (ret < 0)
> > + return ret;
> > +
> > + glb_irq = ACPI_ADD_PTR(u64, node, iort_smmu->global_interrupt_offset);
> > +
> > + if (!IORT_IRQ_MASK(glb_irq[1])) /* 0 means not implemented */
> > + smmu->num_global_irqs = 1;
> > + else
> > + smmu->num_global_irqs = 2;
> > +
> > + if (iort_smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK)
> > + smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
> > +
> > + return 0;
> > +}
> > +#else
> > +static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
> > + struct arm_smmu_device *smmu)
> > +{
> > + return -ENODEV;
> > +}
> > +#endif
> > +
> > static int arm_smmu_device_dt_probe(struct platform_device *pdev,
> > struct arm_smmu_device *smmu)
> > {
> > @@ -1955,7 +2021,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
> > }
> > smmu->dev = dev;
> >
> > - err = arm_smmu_device_dt_probe(pdev, smmu);
> > + if (dev->of_node)
> > + err = arm_smmu_device_dt_probe(pdev, smmu);
> > + else
> > + err = arm_smmu_device_acpi_probe(pdev, smmu);
> > +
> > if (err)
> > return err;
> >
> > @@ -2103,6 +2173,17 @@ IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", arm_smmu_of_init);
> > IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", arm_smmu_of_init);
> > IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", arm_smmu_of_init);
> >
> > +#ifdef CONFIG_ACPI
> > +static int __init arm_smmu_acpi_init(struct acpi_table_header *table)
> > +{
> > + if (iort_node_match(ACPI_IORT_NODE_SMMU))
> > + return arm_smmu_init();
> > +
> > + return 0;
> > +}
> > +IORT_ACPI_DECLARE(arm_smmu, ACPI_SIG_IORT, arm_smmu_acpi_init);
> > +#endif
> > +
> > MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
> > MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
> > MODULE_LICENSE("GPL v2");
> > diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h
> > index 17bb078..79ba1bb 100644
> > --- a/include/linux/acpi_iort.h
> > +++ b/include/linux/acpi_iort.h
> > @@ -23,6 +23,9 @@
> > #include <linux/fwnode.h>
> > #include <linux/irqdomain.h>
> >
> > +#define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
> > +#define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
> > +
> > int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node);
> > void iort_deregister_domain_token(int trans_id);
> > struct fwnode_handle *iort_find_domain_token(int trans_id);
> >
>
^ permalink raw reply
* [PATCH] drm/sun4i: Fix a return value in case of error
From: Christophe JAILLET @ 2016-11-18 18:18 UTC (permalink / raw)
To: linux-arm-kernel
If 'sun4i_backend_drm_format_to_layer()' does not return 0, then 'val' is
left unmodified.
As it is not initialized either, the return value can be anything.
It is likely that returning the error code was expected here.
As the only caller of 'sun4i_backend_update_layer_formats()' does not check
the return value, this fix is purely theorical.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 7eb2a965f83d..f724b8047bae 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -192,7 +192,7 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
ret = sun4i_backend_drm_format_to_layer(plane, fb->pixel_format, &val);
if (ret) {
DRM_DEBUG_DRIVER("Invalid format\n");
- return val;
+ return ret;
}
regmap_update_bits(backend->regs, SUN4I_BACKEND_ATTCTL_REG1(layer),
--
2.9.3
^ permalink raw reply related
* [PATCHv3 6/6] arm64: Add support for CONFIG_DEBUG_VIRTUAL
From: Mark Rutland @ 2016-11-18 18:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479431816-5028-7-git-send-email-labbott@redhat.com>
On Thu, Nov 17, 2016 at 05:16:56PM -0800, Laura Abbott wrote:
> diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
> index 54bb209..0d37c19 100644
> --- a/arch/arm64/mm/Makefile
> +++ b/arch/arm64/mm/Makefile
> @@ -5,6 +5,7 @@ obj-y := dma-mapping.o extable.o fault.o init.o \
> obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
> obj-$(CONFIG_ARM64_PTDUMP) += dump.o
> obj-$(CONFIG_NUMA) += numa.o
> +obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
We'll also need:
KASAN_SANITIZE_physaddr.o := n
... or code prior to KASAN init will cause the kernel to die if
__virt_to_phys() or __phys_addr_symbol() are called.
> obj-$(CONFIG_KASAN) += kasan_init.o
> KASAN_SANITIZE_kasan_init.o := n
Thanks,
Mark,
^ permalink raw reply
* [GIT PULL 3/5] i.MX device tree updates for 4.10
From: Olof Johansson @ 2016-11-18 18:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-3-git-send-email-shawnguo@kernel.org>
On Tue, Nov 15, 2016 at 05:00:29PM +0800, Shawn Guo wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt-4.10
>
> for you to fetch changes up to c201369d4aa5f05b8a37d6d1eeabf248c7086454:
>
> ARM: dts: imx6ull: add imx6ull support (2016-11-15 08:54:27 +0800)
>
> ----------------------------------------------------------------
> i.MX device tree updates for 4.10:
> - New boards support: i.MX6SX UDOO Neo, Boundary Devices Nitrogen6_SOM2,
> Engicam i.CoreM6, Grinn i.MX6UL liteSOM/liteBoard, Toradex Colibri
> iMX6 module, i.MX6ULL and EVK board.
> - Remove skeleton.dtsi inclusion from all i.MX SoC dts files, as it's
> been deprecated, since commit 9c0da3cc61f1233c ("ARM: dts: explicitly
> mark skeleton.dtsi as deprecated").
> - Misc device addition and enabling: OCOTP for Vybrid, MMDC for i.MX6QP,
> TMU for LS1021A, FEC for imx6qdl-icore, DMA for Vybrid DSPI.
> - A few cleanups: use hyphens for node names, fix white spaces, move
> imx-weim parameters into SoC dtsi, replace gpio-key,wakeup with
> wakeup-source, remove pwm-leds from imx6q-apalis-ixora, remove I2C3
> from vf610-zii-dev-rev-b.
> - Other small random changes: calibrate USB PHY for b650v3 board,
> update TX D_CAL for USBPHY, use enable-gpios for backlight on
> imx6qdl-apalis, etc.
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 4/5] Freescale arm64 device tree updates for 4.10
From: Olof Johansson @ 2016-11-18 18:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-4-git-send-email-shawnguo@kernel.org>
On Tue, Nov 15, 2016 at 05:00:30PM +0800, Shawn Guo wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt64-4.10
>
> for you to fetch changes up to 236f794e4463a6b53139702c1b609091f61a17ab:
>
> arm64: dts: ls2080a: Add TMU device tree support for LS2080A (2016-11-15 15:05:36 +0800)
>
> ----------------------------------------------------------------
> Freescale arm64 device tree updates for 4.10:
> - Enable Thermal Monitoring Unit (TMU) for thermal management on
> LS1043A and LS2080A.
> - Add support for LS1046A SoC, which has similar peripherals as
> LS1043A but integrates 4 A72 cores.
> - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 5/5] i.MX defconfig updates for 4.10
From: Olof Johansson @ 2016-11-18 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479200431-1765-5-git-send-email-shawnguo@kernel.org>
On Tue, Nov 15, 2016 at 05:00:31PM +0800, Shawn Guo wrote:
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-defconfig-4.10
>
> for you to fetch changes up to 3252e255371ad22c02d5c9d1740d408ce1b10f35:
>
> ARM: imx_v6_v7_defconfig: Select the es8328 codec driver (2016-10-24 19:54:38 +0800)
>
> ----------------------------------------------------------------
> i.MX defconfig updates for 4.10:
> - Increase CMA size to 64 MiB, so that we can use etnaviv driver with
> 1920x1080 display devices.
> - Enable ES8328 codec driver support, which is required by Kosagi
> Novena boards.
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] STM32 SOC changes for v4.10 #1
From: Olof Johansson @ 2016-11-18 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7e258e38-5ac9-60e8-4bc7-03acedd5e11d@st.com>
Hi,
On Tue, Nov 15, 2016 at 03:22:30PM +0100, Alexandre Torgue wrote:
> Hi Olof, Arnd and Kevin,
>
> Please consider this first round of STM32 SOC updates for v4.10:
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git
> tags/soc-for-4.10-1
>
> for you to fetch changes up to 6bc18b83c0c3b5d56137a31ce98ca2802036e7a9:
>
> ARM: Kconfig: Introduce MACH_STM32F746 flag (2016-11-15 12:02:59 +0100)
>
> ----------------------------------------------------------------
> STM32 SOC updates for v4.10, round 1.
>
> Highlights:
> ----------
> - Add new MCU SOC STM32F746
>
> ----------------------------------------------------------------
> Alexandre TORGUE (2):
> ARM: mach-stm32: Add a new SOC - STM32F746
> ARM: Kconfig: Introduce MACH_STM32F746 flag
Merged. For future patches, please use the same format as other platforms,
in your case it would be:
ARM: stm32: <..>
I.e. others are leaving out the mach- part.
Also, on the Kconfig change, please consider adding a Kconfig under your
mach directory and include it. We ask most platforms that have suboptions
to do this to avoid conflicts and provide a bit more structure. Feel
free to send a new pull request build on top of this one for that,
since we're merging this one now.
Thanks!
-Olof
^ permalink raw reply
* [GIT PULL] STM32 DT changes for v4.10 #2
From: Olof Johansson @ 2016-11-18 18:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2f793efd-01c6-fa28-0332-9e292341c064@st.com>
On Tue, Nov 15, 2016 at 03:40:24PM +0100, Alexandre Torgue wrote:
> Hi Olof, Arnd and Kevin,
>
> Please consider this second round of STM32 DT updates for v4.10:
>
> The following changes since commit f6dbbff4f0af1a5c0d6eaf414572b5eff7a73a8b:
>
> ARM: dts: stm32f429: add LSI and LSE clocks (2016-11-04 15:08:08 +0100)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git
> tags/stm32-dt-for-v4.10-2
>
> for you to fetch changes up to 2ecaa477b404d707bac93c56f09a0a6162e04ed7:
>
> ARM: dts: stm32f429: Add QSPI clock (2016-11-15 13:59:11 +0100)
>
> ----------------------------------------------------------------
> STM32 DT updates for v4.10, round 2.
>
> Highlights:
> ----------
> - Add support of STM32F746 MCU and STM32746G-Eval board
> - Add QSPI support for STM32F469-Disco board
>
> ----------------------------------------------------------------
> Alexandre TORGUE (1):
> ARM: dts: Add STM32F746 MCU and STM32746g-EVAL board
>
> Gabriel Fernandez (1):
> ARM: dts: stm32f429: Add QSPI clock
Hi, merged. But here too, please use common prefixes in the future,
please. I'd recommend 'ARM: dts: stm32: <...>'.
Thanks!
-Olof
^ permalink raw reply
* [GIT PULL] arm64: dts: hisilicon dts updates for v4.10
From: Olof Johansson @ 2016-11-18 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <582B320F.7030206@hisilicon.com>
On Tue, Nov 15, 2016 at 04:04:31PM +0000, Wei Xu wrote:
> Hi Arnd, Hi Olof, Hi Kevin,
>
> Please help to pull the following changes.
> Thanks!
>
> Best Regards,
> Wei
>
> ---
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://github.com/hisilicon/linux-hisi.git tags/hisi-arm64-dt-4.10
>
> for you to fetch changes up to 85f5bd9e771349833602ccdd39b65613ecd11fd1:
>
> arm64: dts: hisi: add refclk node to hip06 dts files for SAS (2016-11-15 10:58:41 +0000)
>
> ----------------------------------------------------------------
> ARM64: DT: Hisilicon SoC DT updates for 4.10
>
> - Correct the hardware pin number of the usb node on the Hip06
> - Add the Hisilicon Hip07 D05 board dts binding
> - Add the initial dts for the Hip07 D05 board
> - Fix the warning for the node without reg propery on the Hip06
> - Fix the sas am max transmissions quirk property on the Hip06
> - Disable the sas0 and sas2 on D03 board
> - Add refclk node for SAS on the Hip06
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] arm: dts: hisilicon dts updates for v4.10
From: Olof Johansson @ 2016-11-18 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <582B333E.2060205@hisilicon.com>
On Tue, Nov 15, 2016 at 04:09:34PM +0000, Wei Xu wrote:
> Hi Arnd, Hi Olof, Hi Kevin,
>
> Please help to pull the following changes.
> Thanks!
>
> Best Regards,
> Wei
>
> ---
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://github.com/hisilicon/linux-hisi.git tags/hisi-armv7-soc-dt-for-4.10
>
> for you to fetch changes up to 3b23aabfcd48988179f7c6c2dde01f3356f68213:
>
> ARM: dts: hisi-x5hd2: Remove skeleton.dtsi inclusion (2016-11-15 11:30:55 +0000)
>
> ----------------------------------------------------------------
> ARM: DT: Hisilicon ARMv7 SoC DT updates for 4.10
>
> - Remove skeleton.dtsi inclusion for the Hip01, Hi3620 and Hix5hd2
Merged, thanks.
-Olof
^ permalink raw reply
* [PATCHv3 6/6] arm64: Add support for CONFIG_DEBUG_VIRTUAL
From: Laura Abbott @ 2016-11-18 18:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118175327.GE1197@leverpostej>
On 11/18/2016 09:53 AM, Mark Rutland wrote:
> Hi,
>
> On Thu, Nov 17, 2016 at 05:16:56PM -0800, Laura Abbott wrote:
>>
>> x86 has an option CONFIG_DEBUG_VIRTUAL to do additional checks
>> on virt_to_phys calls. The goal is to catch users who are calling
>> virt_to_phys on non-linear addresses immediately. This inclues callers
>> using virt_to_phys on image addresses instead of __pa_symbol. As features
>> such as CONFIG_VMAP_STACK get enabled for arm64, this becomes increasingly
>> important. Add checks to catch bad virt_to_phys usage.
>>
>> Signed-off-by: Laura Abbott <labbott@redhat.com>
>> ---
>> v3: Make use of __pa_symbol required via debug checks. It's a WARN for now but
>> it can become a BUG after wider testing. __virt_to_phys is
>> now for linear addresses only. Dropped the VM_BUG_ON from Catalin's suggested
>> version from the nodebug version since having that in the nodebug version
>> essentially made them the debug version. Changed to KERNEL_START/KERNEL_END
>> for bounds checking. More comments.
>
> I gave this a go with DEBUG_VIRTUAL && KASAN_INLINE selected, and the
> kernel dies somewhere before bringing up earlycon. :(
>
> I mentioned some possible reasons in a reply to pastch 5, and I have
> some more comments below.
>
> [...]
>
>> -#define __virt_to_phys(x) ({ \
>> +
>> +
>> +/*
>> + * This is for translation from the standard linear map to physical addresses.
>> + * It is not to be used for kernel symbols.
>> + */
>> +#define __virt_to_phys_nodebug(x) ({ \
>> phys_addr_t __x = (phys_addr_t)(x); \
>> - __x & BIT(VA_BITS - 1) ? (__x & ~PAGE_OFFSET) + PHYS_OFFSET : \
>> - (__x - kimage_voffset); })
>> + ((__x & ~PAGE_OFFSET) + PHYS_OFFSET); \
>> +})
>
> Given the KASAN failure, and the strong possibility that there's even
> more stuff lurking in common code, I think we should retain the logic to
> handle kernel image addresses for the timebeing (as x86 does). Once
> we've merged DEBUG_VIRTUAL, it will be easier to track those down.
>
Agreed. I might see about adding another option DEBUG_STRICT_VIRTUAL
for catching bad __pa vs __pa_symbol usage and keep DEBUG_VIRTUAL for
catching addresses that will work in neither case.
> Catalin, I think you suggested removing that logic; are you happy for it
> to be restored?
>
> See below for a refactoring that retains this logic.
>
> [...]
>
>> +/*
>> + * This is for translation from a kernel image/symbol address to a
>> + * physical address.
>> + */
>> +#define __pa_symbol_nodebug(x) ({ \
>> + phys_addr_t __x = (phys_addr_t)(x); \
>> + (__x - kimage_voffset); \
>> +})
>
> We can avoid duplication here (and in physaddr.c) if we factor the logic
> into helpers, e.g.
>
> /*
> * The linear kernel range starts in the middle of the virtual adddress
> * space. Testing the top bit for the start of the region is a
> * sufficient check.
> */
> #define __is_lm_address(addr) (!!((addr) & BIT(VA_BITS - 1)))
>
> #define __lm_to_phys(addr) (((addr) & ~PAGE_OFFSET) + PHYS_OFFSET)
> #define __kimg_to_phys(addr) ((addr) - kimage_voffset)
>
> #define __virt_to_phys_nodebug(x) ({ \
> phys_addr_t __x = (phys_addr_t)(x); \
> __is_lm_address(__x) ? __lm_to_phys(__x) : \
> __kimg_to_phys(__x); \
> })
>
> #define __pa_symbol_nodebug(x) __kimg_to_phys((phys_addr_t)(x))
>
Yes, this is much cleaner
>> +#ifdef CONFIG_DEBUG_VIRTUAL
>> +extern unsigned long __virt_to_phys(unsigned long x);
>> +extern unsigned long __phys_addr_symbol(unsigned long x);
>
> It would be better for both of these to return phys_addr_t.
>
> [...]
>
I was worried this would turn into another warning project but
at first pass this works fine and the type will hopefully catch
some bad uses elsewhere.
>> diff --git a/arch/arm64/mm/physaddr.c b/arch/arm64/mm/physaddr.c
>> new file mode 100644
>> index 0000000..f8eb781
>> --- /dev/null
>> +++ b/arch/arm64/mm/physaddr.c
>> @@ -0,0 +1,39 @@
>> +#include <linux/mm.h>
>> +
>> +#include <asm/memory.h>
>
> We also need:
>
> #include <linux/bug.h>
> #include <linux/export.h>
> #include <linux/types.h>
> #include <linux/mmdebug.h>
>
>> +unsigned long __virt_to_phys(unsigned long x)
>> +{
>> + phys_addr_t __x = (phys_addr_t)x;
>> +
>> + if (__x & BIT(VA_BITS - 1)) {
>> + /*
>> + * The linear kernel range starts in the middle of the virtual
>> + * adddress space. Testing the top bit for the start of the
>> + * region is a sufficient check.
>> + */
>> + return (__x & ~PAGE_OFFSET) + PHYS_OFFSET;
>> + } else {
>> + /*
>> + * __virt_to_phys should not be used on symbol addresses.
>> + * This should be changed to a BUG once all basic bad uses have
>> + * been cleaned up.
>> + */
>> + WARN(1, "Do not use virt_to_phys on symbol addresses");
>> + return __phys_addr_symbol(x);
>> + }
>> +}
>> +EXPORT_SYMBOL(__virt_to_phys);
>
> I think this would be better something like:
>
> phys_addr_t __virt_to_phys(unsigned long x)
> {
> WARN(!__is_lm_address(x),
> "virt_to_phys() used for non-linear address: %pK\n",
> (void*)x);
>
> return __virt_to_phys_nodebug(x);
> }
> EXPORT_SYMBOL(__virt_to_phys);
>
>> +
>> +unsigned long __phys_addr_symbol(unsigned long x)
>> +{
>> + phys_addr_t __x = (phys_addr_t)x;
>> +
>> + /*
>> + * This is bounds checking against the kernel image only.
>> + * __pa_symbol should only be used on kernel symbol addresses.
>> + */
>> + VIRTUAL_BUG_ON(x < (unsigned long) KERNEL_START || x > (unsigned long) KERNEL_END);
>> + return (__x - kimage_voffset);
>> +}
>> +EXPORT_SYMBOL(__phys_addr_symbol);
>
> Similarly:
>
> phys_addr_t __phys_addr_symbol(unsigned long x)
> {
> /*
> * This is bounds checking against the kernel image only.
> * __pa_symbol should only be used on kernel symbol addresses.
> */
> VIRTUAL_BUG_ON(x < (unsigned long) KERNEL_START ||
> x > (unsigned long) KERNEL_END);
>
> return __pa_symbol_nodebug(x);
> }
> EXPORT_SYMBOL(__phys_addr_symbol);
>
> Thanks,
> Mark.
>
Thanks,
Laura
^ permalink raw reply
* [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
From: Lee Jones @ 2016-11-18 18:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478097481-14895-4-git-send-email-andrew@aj.id.au>
Arnd,
Do you have a preference?
> The Aspeed LPC Host Controller is presented as a syscon device to
> arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on
> fifth generation SoCs depends on bits in both the System Control Unit
> and the LPC Host Controller.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++
Create a new directory in bindings/mfd called 'syscon'.
Or perhaps 'bindings/syscon'.
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> new file mode 100644
> index 000000000000..792651488c3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> @@ -0,0 +1,17 @@
> +* Device tree bindings for the Aspeed LPC Host Controller (LPCHC)
> +
> +The LPCHC registers configure LPC behaviour between the BMC and the host
> +system. The LPCHC also participates in pinmux requests on g5 SoCs and is
> +therefore considered a syscon device.
> +
> +Required properties:
> +- compatible: "aspeed,ast2500-lpchc", "syscon"
> +- reg: contains offset/length value of the LPCHC memory
> + region.
Why not just use a single tab, then you don't have to linewrap?
> +Example:
> +
> +lpchc: lpchc at 1e7890a0 {
> + compatible = "aspeed,ast2500-lpchc", "syscon";
> + reg = <0x1e7890a0 0xc4>;
> +};
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
From: Lee Jones @ 2016-11-18 18:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118184437.GD19884@dell.home>
[Sending Arnd this time!]
> Arnd,
>
> Do you have a preference?
>
> > The Aspeed LPC Host Controller is presented as a syscon device to
> > arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on
> > fifth generation SoCs depends on bits in both the System Control Unit
> > and the LPC Host Controller.
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++
>
> Create a new directory in bindings/mfd called 'syscon'.
>
> Or perhaps 'bindings/syscon'.
>
> > 1 file changed, 17 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> > new file mode 100644
> > index 000000000000..792651488c3d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> > @@ -0,0 +1,17 @@
> > +* Device tree bindings for the Aspeed LPC Host Controller (LPCHC)
> > +
> > +The LPCHC registers configure LPC behaviour between the BMC and the host
> > +system. The LPCHC also participates in pinmux requests on g5 SoCs and is
> > +therefore considered a syscon device.
> > +
> > +Required properties:
> > +- compatible: "aspeed,ast2500-lpchc", "syscon"
> > +- reg: contains offset/length value of the LPCHC memory
> > + region.
>
> Why not just use a single tab, then you don't have to linewrap?
>
> > +Example:
> > +
> > +lpchc: lpchc at 1e7890a0 {
> > + compatible = "aspeed,ast2500-lpchc", "syscon";
> > + reg = <0x1e7890a0 0xc4>;
> > +};
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
From: Lee Jones @ 2016-11-18 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478097481-14895-3-git-send-email-andrew@aj.id.au>
On Thu, 03 Nov 2016, Andrew Jeffery wrote:
> The Aspeed SoC Display Controller is presented as a syscon device to
> arbitrate access by display and pinmux drivers. Video pinmux
> configuration on fifth generation SoCs depends on bits in both the
> System Control Unit and the Display Controller.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
Same here.
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
> new file mode 100644
> index 000000000000..aea5370efd97
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
> @@ -0,0 +1,17 @@
> +* Device tree bindings for Aspeed SoC Display Controller (GFX)
> +
> +The Aspeed SoC Display Controller primarily does as its name suggests, but also
> +participates in pinmux requests on the g5 SoCs. It is therefore considered a
> +syscon device.
> +
> +Required properties:
> +- compatible: "aspeed,ast2500-gfx", "syscon"
> +- reg: contains offset/length value of the GFX memory
> + region.
> +
> +Example:
> +
> +gfx: display at 1e6e6000 {
> + compatible = "aspeed,ast2500-gfx", "syscon";
> + reg = <0x1e6e6000 0x1000>;
> +};
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 1/2] mfd: axp20x: Add address extension registers for AXP806 regmap
From: Lee Jones @ 2016-11-18 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111032953.20849-2-wens@csie.org>
On Fri, 11 Nov 2016, Chen-Yu Tsai wrote:
> The AXP806 supports either master/standalone or slave mode.
> Slave mode allows sharing the serial bus, even with multiple
> AXP806 which all have the same hardware address.
>
> This is done with extra "serial interface address extension",
> or AXP806_BUS_ADDR_EXT, and "register address extension", or
> AXP806_REG_ADDR_EXT, registers. The former is read-only, with
> 1 bit customizable at the factory, and 1 bit depending on the
> state of an external pin. The latter is writable. Only when
> the these device addressing bits (in the upper 4 bits of the
> registers) match, will the device respond to operations on
> its other registers.
>
> Add these 2 registers to the regmap so we can access them.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> drivers/mfd/axp20x.c | 3 ++-
> include/linux/mfd/axp20x.h | 2 ++
> 2 files changed, 4 insertions(+), 1 deletion(-)
Applied, thanks.
> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> index ba130be32e61..cdaeb34a9a38 100644
> --- a/drivers/mfd/axp20x.c
> +++ b/drivers/mfd/axp20x.c
> @@ -135,6 +135,7 @@ static const struct regmap_range axp806_writeable_ranges[] = {
> regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
> regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
> regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
> + regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
> };
>
> static const struct regmap_range axp806_volatile_ranges[] = {
> @@ -305,7 +306,7 @@ static const struct regmap_config axp806_regmap_config = {
> .val_bits = 8,
> .wr_table = &axp806_writeable_table,
> .volatile_table = &axp806_volatile_table,
> - .max_register = AXP806_VREF_TEMP_WARN_L,
> + .max_register = AXP806_REG_ADDR_EXT,
> .cache_type = REGCACHE_RBTREE,
> };
>
> diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
> index fec597fb34cb..7e85ececcedf 100644
> --- a/include/linux/mfd/axp20x.h
> +++ b/include/linux/mfd/axp20x.h
> @@ -115,6 +115,8 @@ enum {
> #define AXP806_CLDO2_V_CTRL 0x25
> #define AXP806_CLDO3_V_CTRL 0x26
> #define AXP806_VREF_TEMP_WARN_L 0xf3
> +#define AXP806_BUS_ADDR_EXT 0xfe
> +#define AXP806_REG_ADDR_EXT 0xff
>
> /* Interrupt */
> #define AXP152_IRQ1_EN 0x40
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v8 6/7] arm/arm64: vgic: Implement VGICv3 CPU interface access
From: Vijay Kilari @ 2016-11-18 18:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117160951.GB23588@cbox>
On Thu, Nov 17, 2016 at 9:39 PM, Christoffer Dall
<christoffer.dall@linaro.org> wrote:
> On Thu, Nov 17, 2016 at 09:25:59PM +0530, Vijay Kilari wrote:
>> On Thu, Nov 17, 2016 at 12:22 AM, Christoffer Dall
>> <christoffer.dall@linaro.org> wrote:
>> > On Fri, Nov 04, 2016 at 04:43:32PM +0530, vijay.kilari at gmail.com wrote:
>> >> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>> >>
>> >> VGICv3 CPU interface registers are accessed using
>> >> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> >> as 64-bit. The cpu MPIDR value is passed along with register id.
>> >> is used to identify the cpu for registers access.
>> >>
>> >> The version of VGIC v3 specification is define here
>> >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
>> >>
>> >> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
>> >> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>> >> ---
>> >> arch/arm64/include/uapi/asm/kvm.h | 3 +
>> >> arch/arm64/kvm/Makefile | 1 +
>> >> include/kvm/arm_vgic.h | 9 +
>> >> virt/kvm/arm/vgic/vgic-kvm-device.c | 27 +++
>> >> virt/kvm/arm/vgic/vgic-mmio-v3.c | 19 +++
>> >> virt/kvm/arm/vgic/vgic-sys-reg-v3.c | 324 ++++++++++++++++++++++++++++++++++++
>> >> virt/kvm/arm/vgic/vgic-v3.c | 8 +
>> >> virt/kvm/arm/vgic/vgic.h | 4 +
>> >> 8 files changed, 395 insertions(+)
>> >>
>> >> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
>> >> index 56dc08d..91c7137 100644
>> >> --- a/arch/arm64/include/uapi/asm/kvm.h
>> >> +++ b/arch/arm64/include/uapi/asm/kvm.h
>> >> @@ -206,9 +206,12 @@ struct kvm_arch_memory_slot {
>> >> (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
>> >> #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
>> >> #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
>> >> +#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
>> >> #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
>> >> #define KVM_DEV_ARM_VGIC_GRP_CTRL 4
>> >> #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
>> >> +#define KVM_DEV_ARM_VGIC_CPU_SYSREGS 6
>> >> +
>> >> #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
>> >>
>> >> /* Device Control API on vcpu fd */
>> >> diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
>> >> index d50a82a..1a14e29 100644
>> >> --- a/arch/arm64/kvm/Makefile
>> >> +++ b/arch/arm64/kvm/Makefile
>> >> @@ -32,5 +32,6 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-mmio-v3.o
>> >> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-kvm-device.o
>> >> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-its.o
>> >> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o
>> >> +kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-sys-reg-v3.o
>> >
>> > Thi is making me wonder: Are we properly handling GICv3 save/restore
>> > for AArch32 now that we have GICv3 support for AArch32? By properly I
>> > mean that either it is clearly only supported on AArch64 systems or it's
>> > supported on both AArch64 and AArch32, but it shouldn't break randomly
>> > on AArch32.
>>
>> It supports both AArch64 and AArch64 in handling of system registers
>> save/restore.
>> All system registers that we save/restore are 32-bit for both aarch64
>> and aarch32.
>> Though opcode op0 should be zero for aarch32, the remaining Op and CRn codes
>> are same. However the codes sent by qemu is matched and register
>> are handled properly irrespective of AArch32 or AArch64.
>>
>> I don't have platform which support AArch32 guests to verify.
>
> Actually this is not about the guest, it's about an ARMv8 AArch32 host
> that has a GICv3.
>
> I just tried to do a v7 compile with your patches, and it results in an
> epic failure, so there's something for you to look at.
>
Could you please share you config file?. I tried with multi_v7 defconfig with
CONFIG KVM and CONFIG_KVM_ARM_HOST enabled. it compiled for me.
^ permalink raw reply
* [PATCH v16 04/15] clocksource/drivers/arm_arch_timer: rename some enums and defines, and some cleanups.
From: Mark Rutland @ 2016-11-18 18:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479304148-2965-5-git-send-email-fu.wei@linaro.org>
On Wed, Nov 16, 2016 at 09:48:57PM +0800, fu.wei at linaro.org wrote:
> From: Fu Wei <fu.wei@linaro.org>
>
> Rename some enums and defines, to unify the format of enums and defines
> in arm_arch_timer.h, also update all the users of these enums and defines:
> drivers/clocksource/arm_arch_timer.c
> virt/kvm/arm/hyp/timer-sr.c
I'm happy with making definitions use a consistent ARCH_TIMER_ prefix,
given they're exposed in headers...
> And do some cleanups, according to the suggestion from checkpatch.pl:
> (1) using BIT(nr) instead of (1 << nr)
> (2) using 'unsigned int' instead of 'unsigned'
... but these changes are pointless churn. They make the patch larger,
hardwer to review, and more painful to merge.
Please leave these as they are unless there is a functional problem. If
there will be a functional problem unless these are changed, describe
that in the commit message.
Thanks,
Mark.
>
> No functional change.
>
> Signed-off-by: Fu Wei <fu.wei@linaro.org>
> ---
> drivers/clocksource/arm_arch_timer.c | 111 ++++++++++++++++++-----------------
> include/clocksource/arm_arch_timer.h | 40 ++++++-------
> virt/kvm/arm/hyp/timer-sr.c | 6 +-
> 3 files changed, 81 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 15341cf..dd1040d 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -66,11 +66,11 @@ struct arch_timer {
> #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
>
> static u32 arch_timer_rate;
> -static int arch_timer_ppi[MAX_TIMER_PPI];
> +static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
>
> static struct clock_event_device __percpu *arch_timer_evt;
>
> -static enum arch_timer_ppi_nr arch_timer_uses_ppi = VIRT_PPI;
> +static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
> static bool arch_timer_c3stop;
> static bool arch_timer_mem_use_virtual;
>
> @@ -340,7 +340,7 @@ static void fsl_a008585_set_sne(struct clock_event_device *clk)
> if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
> return;
>
> - if (arch_timer_uses_ppi == VIRT_PPI)
> + if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
> clk->set_next_event = fsl_a008585_set_next_event_virt;
> else
> clk->set_next_event = fsl_a008585_set_next_event_phys;
> @@ -352,7 +352,7 @@ static void __arch_timer_setup(unsigned type,
> {
> clk->features = CLOCK_EVT_FEAT_ONESHOT;
>
> - if (type == ARCH_CP15_TIMER) {
> + if (type == ARCH_TIMER_TYPE_CP15) {
> if (arch_timer_c3stop)
> clk->features |= CLOCK_EVT_FEAT_C3STOP;
> clk->name = "arch_sys_timer";
> @@ -360,14 +360,14 @@ static void __arch_timer_setup(unsigned type,
> clk->cpumask = cpumask_of(smp_processor_id());
> clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
> switch (arch_timer_uses_ppi) {
> - case VIRT_PPI:
> + case ARCH_TIMER_VIRT_PPI:
> clk->set_state_shutdown = arch_timer_shutdown_virt;
> clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
> clk->set_next_event = arch_timer_set_next_event_virt;
> break;
> - case PHYS_SECURE_PPI:
> - case PHYS_NONSECURE_PPI:
> - case HYP_PPI:
> + case ARCH_TIMER_PHYS_SECURE_PPI:
> + case ARCH_TIMER_PHYS_NONSECURE_PPI:
> + case ARCH_TIMER_HYP_PPI:
> clk->set_state_shutdown = arch_timer_shutdown_phys;
> clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
> clk->set_next_event = arch_timer_set_next_event_phys;
> @@ -447,8 +447,8 @@ static void arch_counter_set_user_access(void)
>
> static bool arch_timer_has_nonsecure_ppi(void)
> {
> - return (arch_timer_uses_ppi == PHYS_SECURE_PPI &&
> - arch_timer_ppi[PHYS_NONSECURE_PPI]);
> + return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
> + arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
> }
>
> static u32 check_ppi_trigger(int irq)
> @@ -469,14 +469,15 @@ static int arch_timer_starting_cpu(unsigned int cpu)
> struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
> u32 flags;
>
> - __arch_timer_setup(ARCH_CP15_TIMER, clk);
> + __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
>
> flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
> enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
>
> if (arch_timer_has_nonsecure_ppi()) {
> - flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]);
> - enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags);
> + flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
> + enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
> + flags);
> }
>
> arch_counter_set_user_access();
> @@ -513,16 +514,17 @@ arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
> static void arch_timer_banner(unsigned type)
> {
> pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
> - type & ARCH_CP15_TIMER ? "cp15" : "",
> - type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
> - type & ARCH_MEM_TIMER ? "mmio" : "",
> + type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
> + type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
> + " and " : "",
> + type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
> (unsigned long)arch_timer_rate / 1000000,
> (unsigned long)(arch_timer_rate / 10000) % 100,
> - type & ARCH_CP15_TIMER ?
> - (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
> + type & ARCH_TIMER_TYPE_CP15 ?
> + (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
> "",
> - type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
> - type & ARCH_MEM_TIMER ?
> + type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
> + type & ARCH_TIMER_TYPE_MEM ?
> arch_timer_mem_use_virtual ? "virt" : "phys" :
> "");
> }
> @@ -588,8 +590,9 @@ static void __init arch_counter_register(unsigned type)
> u64 start_count;
>
> /* Register the CP15 based counter if we have one */
> - if (type & ARCH_CP15_TIMER) {
> - if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI)
> + if (type & ARCH_TIMER_TYPE_CP15) {
> + if (IS_ENABLED(CONFIG_ARM64) ||
> + arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
> arch_timer_read_counter = arch_counter_get_cntvct;
> else
> arch_timer_read_counter = arch_counter_get_cntpct;
> @@ -625,7 +628,7 @@ static void arch_timer_stop(struct clock_event_device *clk)
>
> disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
> if (arch_timer_has_nonsecure_ppi())
> - disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
> + disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
>
> clk->set_state_shutdown(clk);
> }
> @@ -688,24 +691,24 @@ static int __init arch_timer_register(void)
>
> ppi = arch_timer_ppi[arch_timer_uses_ppi];
> switch (arch_timer_uses_ppi) {
> - case VIRT_PPI:
> + case ARCH_TIMER_VIRT_PPI:
> err = request_percpu_irq(ppi, arch_timer_handler_virt,
> "arch_timer", arch_timer_evt);
> break;
> - case PHYS_SECURE_PPI:
> - case PHYS_NONSECURE_PPI:
> + case ARCH_TIMER_PHYS_SECURE_PPI:
> + case ARCH_TIMER_PHYS_NONSECURE_PPI:
> err = request_percpu_irq(ppi, arch_timer_handler_phys,
> "arch_timer", arch_timer_evt);
> - if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
> - ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
> + if (!err && arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]) {
> + ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
> err = request_percpu_irq(ppi, arch_timer_handler_phys,
> "arch_timer", arch_timer_evt);
> if (err)
> - free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
> + free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
> arch_timer_evt);
> }
> break;
> - case HYP_PPI:
> + case ARCH_TIMER_HYP_PPI:
> err = request_percpu_irq(ppi, arch_timer_handler_phys,
> "arch_timer", arch_timer_evt);
> break;
> @@ -737,7 +740,7 @@ static int __init arch_timer_register(void)
> out_unreg_notify:
> free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
> if (arch_timer_has_nonsecure_ppi())
> - free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
> + free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
> arch_timer_evt);
>
> out_free:
> @@ -758,7 +761,7 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
>
> t->base = base;
> t->evt.irq = irq;
> - __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
> + __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
>
> if (arch_timer_mem_use_virtual)
> func = arch_timer_handler_virt_mem;
> @@ -801,13 +804,15 @@ arch_timer_needs_probing(int type, const struct of_device_id *matches)
>
> static int __init arch_timer_common_init(void)
> {
> - unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
> + unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
>
> /* Wait until both nodes are probed if we have two timers */
> if ((arch_timers_present & mask) != mask) {
> - if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match))
> + if (arch_timer_needs_probing(ARCH_TIMER_TYPE_MEM,
> + arch_timer_mem_of_match))
> return 0;
> - if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match))
> + if (arch_timer_needs_probing(ARCH_TIMER_TYPE_CP15,
> + arch_timer_of_match))
> return 0;
> }
>
> @@ -832,16 +837,16 @@ static int __init arch_timer_init(void)
> * their CNTHP_*_EL2 counterparts, and use a different PPI
> * number.
> */
> - if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
> + if (is_hyp_mode_available() || !arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) {
> bool has_ppi;
>
> if (is_kernel_in_hyp_mode()) {
> - arch_timer_uses_ppi = HYP_PPI;
> - has_ppi = !!arch_timer_ppi[HYP_PPI];
> + arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI;
> + has_ppi = !!arch_timer_ppi[ARCH_TIMER_HYP_PPI];
> } else {
> - arch_timer_uses_ppi = PHYS_SECURE_PPI;
> - has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] ||
> - !!arch_timer_ppi[PHYS_NONSECURE_PPI]);
> + arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
> + has_ppi = (!!arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] ||
> + !!arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
> }
>
> if (!has_ppi) {
> @@ -858,7 +863,7 @@ static int __init arch_timer_init(void)
> if (ret)
> return ret;
>
> - arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
> + arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
>
> return 0;
> }
> @@ -867,13 +872,13 @@ static int __init arch_timer_of_init(struct device_node *np)
> {
> int i;
>
> - if (arch_timers_present & ARCH_CP15_TIMER) {
> + if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
> pr_warn("multiple nodes in dt, skipping\n");
> return 0;
> }
>
> - arch_timers_present |= ARCH_CP15_TIMER;
> - for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
> + arch_timers_present |= ARCH_TIMER_TYPE_CP15;
> + for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
> arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
>
> arch_timer_detect_rate(NULL, np);
> @@ -895,7 +900,7 @@ static int __init arch_timer_of_init(struct device_node *np)
> */
> if (IS_ENABLED(CONFIG_ARM) &&
> of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
> - arch_timer_uses_ppi = PHYS_SECURE_PPI;
> + arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
>
> return arch_timer_init();
> }
> @@ -909,7 +914,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
> unsigned int irq, ret = -EINVAL;
> u32 cnttidr;
>
> - arch_timers_present |= ARCH_MEM_TIMER;
> + arch_timers_present |= ARCH_TIMER_TYPE_MEM;
> cntctlbase = of_iomap(np, 0);
> if (!cntctlbase) {
> pr_err("Can't find CNTCTLBase\n");
> @@ -1008,28 +1013,28 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
> {
> struct acpi_table_gtdt *gtdt;
>
> - if (arch_timers_present & ARCH_CP15_TIMER) {
> + if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
> pr_warn("already initialized, skipping\n");
> return -EINVAL;
> }
>
> gtdt = container_of(table, struct acpi_table_gtdt, header);
>
> - arch_timers_present |= ARCH_CP15_TIMER;
> + arch_timers_present |= ARCH_TIMER_TYPE_CP15;
>
> - arch_timer_ppi[PHYS_SECURE_PPI] =
> + arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] =
> map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
> gtdt->secure_el1_flags);
>
> - arch_timer_ppi[PHYS_NONSECURE_PPI] =
> + arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
> map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
> gtdt->non_secure_el1_flags);
>
> - arch_timer_ppi[VIRT_PPI] =
> + arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
> map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
> gtdt->virtual_timer_flags);
>
> - arch_timer_ppi[HYP_PPI] =
> + arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
> map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
> gtdt->non_secure_el2_flags);
>
> diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
> index d23c381..2625ff1 100644
> --- a/include/clocksource/arm_arch_timer.h
> +++ b/include/clocksource/arm_arch_timer.h
> @@ -20,18 +20,18 @@
> #include <linux/timecounter.h>
> #include <linux/types.h>
>
> -#define ARCH_CP15_TIMER BIT(0)
> -#define ARCH_MEM_TIMER BIT(1)
> +#define ARCH_TIMER_TYPE_CP15 BIT(0)
> +#define ARCH_TIMER_TYPE_MEM BIT(1)
>
> -#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
> -#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
> -#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
> +#define ARCH_TIMER_CTRL_ENABLE BIT(0)
> +#define ARCH_TIMER_CTRL_IT_MASK BIT(1)
> +#define ARCH_TIMER_CTRL_IT_STAT BIT(2)
>
> -#define CNTHCTL_EL1PCTEN (1 << 0)
> -#define CNTHCTL_EL1PCEN (1 << 1)
> -#define CNTHCTL_EVNTEN (1 << 2)
> -#define CNTHCTL_EVNTDIR (1 << 3)
> -#define CNTHCTL_EVNTI (0xF << 4)
> +#define ARCH_TIMER_CNTHCTL_EL1PCTEN BIT(0)
> +#define ARCH_TIMER_CNTHCTL_EL1PCEN BIT(1)
> +#define ARCH_TIMER_CNTHCTL_EVNTEN BIT(2)
> +#define ARCH_TIMER_CNTHCTL_EVNTDIR BIT(3)
> +#define ARCH_TIMER_CNTHCTL_EVNTI (0xF << 4)
>
> enum arch_timer_reg {
> ARCH_TIMER_REG_CTRL,
> @@ -39,11 +39,11 @@ enum arch_timer_reg {
> };
>
> enum arch_timer_ppi_nr {
> - PHYS_SECURE_PPI,
> - PHYS_NONSECURE_PPI,
> - VIRT_PPI,
> - HYP_PPI,
> - MAX_TIMER_PPI
> + ARCH_TIMER_PHYS_SECURE_PPI,
> + ARCH_TIMER_PHYS_NONSECURE_PPI,
> + ARCH_TIMER_VIRT_PPI,
> + ARCH_TIMER_HYP_PPI,
> + ARCH_TIMER_MAX_TIMER_PPI
> };
>
> enum arch_timer_spi_nr {
> @@ -57,13 +57,13 @@ enum arch_timer_spi_nr {
> #define ARCH_TIMER_MEM_PHYS_ACCESS 2
> #define ARCH_TIMER_MEM_VIRT_ACCESS 3
>
> -#define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */
> -#define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */
> -#define ARCH_TIMER_VIRT_EVT_EN (1 << 2)
> +#define ARCH_TIMER_USR_PCT_ACCESS_EN BIT(0) /* physical counter */
> +#define ARCH_TIMER_USR_VCT_ACCESS_EN BIT(1) /* virtual counter */
> +#define ARCH_TIMER_VIRT_EVT_EN BIT(2)
> #define ARCH_TIMER_EVT_TRIGGER_SHIFT (4)
> #define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
> -#define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */
> -#define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */
> +#define ARCH_TIMER_USR_VT_ACCESS_EN BIT(8) /* virtual timer registers */
> +#define ARCH_TIMER_USR_PT_ACCESS_EN BIT(9) /* physical timer registers */
>
> #define ARCH_TIMER_EVT_STREAM_FREQ 10000 /* 100us */
>
> diff --git a/virt/kvm/arm/hyp/timer-sr.c b/virt/kvm/arm/hyp/timer-sr.c
> index 798866a..695b9d9 100644
> --- a/virt/kvm/arm/hyp/timer-sr.c
> +++ b/virt/kvm/arm/hyp/timer-sr.c
> @@ -37,7 +37,7 @@ void __hyp_text __timer_save_state(struct kvm_vcpu *vcpu)
>
> /* Allow physical timer/counter access for the host */
> val = read_sysreg(cnthctl_el2);
> - val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
> + val |= ARCH_TIMER_CNTHCTL_EL1PCTEN | ARCH_TIMER_CNTHCTL_EL1PCEN;
> write_sysreg(val, cnthctl_el2);
>
> /* Clear cntvoff for the host */
> @@ -55,8 +55,8 @@ void __hyp_text __timer_restore_state(struct kvm_vcpu *vcpu)
> * Physical counter access is allowed
> */
> val = read_sysreg(cnthctl_el2);
> - val &= ~CNTHCTL_EL1PCEN;
> - val |= CNTHCTL_EL1PCTEN;
> + val &= ~ARCH_TIMER_CNTHCTL_EL1PCEN;
> + val |= ARCH_TIMER_CNTHCTL_EL1PCTEN;
> write_sysreg(val, cnthctl_el2);
>
> if (timer->enabled) {
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 2/2] mfd: axp20x: Fix AXP806 access errors on cold boot
From: Lee Jones @ 2016-11-18 18:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111032953.20849-3-wens@csie.org>
On Fri, 11 Nov 2016, Chen-Yu Tsai wrote:
> The AXP806 supports either master/standalone or slave mode.
> Slave mode allows sharing the serial bus, even with multiple
> AXP806 which all have the same hardware address.
>
> This is done with extra "serial interface address extension",
> or AXP806_BUS_ADDR_EXT, and "register address extension", or
> AXP806_REG_ADDR_EXT, registers. The former is read-only, with
> 1 bit customizable at the factory, and 1 bit depending on the
> state of an external pin. The latter is writable. Only when
> the these device addressing bits (in the upper 4 bits of the
> registers) match, will the device respond to operations on
> its other registers.
>
> The AXP806_REG_ADDR_EXT was previously configured by Allwinner's
> bootloader. Work on U-boot SPL support now allows us to switch
> to mainline U-boot, which doesn't do this for us. There might
> be other bare minimum bootloaders out there which don't to this
> either. It's best to handle this in the kernel.
>
> This patch sets AXP806_REG_ADDR_EXT to 0x10, which is what we
> know to be the proper value for a standard AXP806 in slave mode.
> Afterwards it will reinitialize the regmap cache, to purge any
> invalid stale values.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> drivers/mfd/axp20x.c | 35 +++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> index cdaeb34a9a38..2f5d46f28511 100644
> --- a/drivers/mfd/axp20x.c
> +++ b/drivers/mfd/axp20x.c
> @@ -829,6 +829,41 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
> {
> int ret;
>
> + /*
> + * The AXP806 supports either master/standalone or slave mode.
> + * Slave mode allows sharing the serial bus, even with multiple
> + * AXP806 which all have the same hardware address.
> + *
> + * This is done with extra "serial interface address extension",
> + * or AXP806_BUS_ADDR_EXT, and "register address extension", or
> + * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
> + * 1 bit customizable at the factory, and 1 bit depending on the
> + * state of an external pin. The latter is writable. Only when
> + * the these device addressing bits (in the upper 4 bits of the
> + * registers) match, will the device respond to operations on its
> + * other registers.
> + *
> + * Since we only support an AXP806 chained to an AXP809 in slave
> + * mode, and there isn't any existing hardware which uses AXP806
> + * in master mode, or has 2 AXP806s in the same system, we can
> + * just program the register address extension to the slave mode
> + * address.
> + */
> + if (axp20x->variant == AXP806_ID) {
> + /* Write to the register address extension register */
> + regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT, 0x10);
Please define 0x10.
> + /* Make sure the write hits the device */
> + regcache_sync_region(axp20x->regmap, AXP806_REG_ADDR_EXT,
> + AXP806_REG_ADDR_EXT);
> +
> + /*
> + * Reinitialize the regmap cache in case the device didn't
> + * properly respond to our reads before.
> + */
> + regmap_reinit_cache(axp20x->regmap, axp20x->regmap_cfg);
> + }
> +
> ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
> IRQF_ONESHOT | IRQF_SHARED, -1,
> axp20x->regmap_irq_chip,
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH] ARM: dts: socfpga: fine-tune L2 cache configuration
From: Marek Vasut @ 2016-11-18 18:52 UTC (permalink / raw)
To: linux-arm-kernel
Enable double-linefill and increase prefetch offset, which gives
considerable read performance boost. The following numbers were
obtained using lmbench 3.0 bw_mem tool, for easier comparison, the
numbers are pasted in two columns. The test machine has Cyclone V
SoC running at 800MHz MPU clock and 512MiB 333MHz 16bit DDR3 DRAM.
Without patch | With patch
$ for i in rd wr rdwr cp fwr frd fcp bzero bcopy ; do echo $i ; bw_mem 64M $i ; done
rd | rd
64.00 526.46 | 64.00 1151.06
wr | wr
64.00 329.95 | 64.00 346.14
rdwr | rdwr
64.00 342.07 | 64.00 367.24
cp | cp
64.00 239.79 | 64.00 322.47
fwr | fwr
64.00 1027.90 | 64.00 1025.38
frd | frd
64.00 322.36 | 64.00 641.89
fcp | fcp
64.00 256.99 | 64.00 408.41
bzero | bzero
64.00 1028.43 | 64.00 1025.07
bcopy | bcopy
64.00 294.73 | 64.00 357.19
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f2f74b5..d645bef 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -694,6 +694,11 @@
prefetch-data = <1>;
prefetch-instr = <1>;
arm,shared-override;
+ arm,double-linefill = <1>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <1>;
+ arm,prefetch-drop = <0>;
+ arm,prefetch-offset = <7>;
};
mmc: dwmmc0 at ff704000 {
--
2.10.2
^ permalink raw reply related
* [PATCH v16 05/15] clocksource/drivers/arm_arch_timer: fix a bug in arch_timer_register about arch_timer_uses_ppi
From: Mark Rutland @ 2016-11-18 18:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479304148-2965-6-git-send-email-fu.wei@linaro.org>
On Wed, Nov 16, 2016 at 09:48:58PM +0800, fu.wei at linaro.org wrote:
> From: Fu Wei <fu.wei@linaro.org>
>
> The patch fix a potential bug about arch_timer_uses_ppi in
> arch_timer_register.
> On ARM64, we don't use ARCH_TIMER_PHYS_SECURE_PPI in Linux, so we will
> just igorne it in init code.
That's not currently the case. I assume you mean we will in later
patches? If so, please make that clear in the commit message.
> If arch_timer_uses_ppi is ARCH_TIMER_PHYS_NONSECURE_PPI, the orignal
> code of arch_timer_uses_ppi may go wrong.
How? What specifically happens?
We don't currently assign ARCH_TIMER_PHYS_NONSECURE_PPI to
arch_timer_uses_ppi, so I assume a later patch changes this. This change
should be folded into said patch; it doesn't make sense in isolation.
Thanks,
Mark.
> Signed-off-by: Fu Wei <fu.wei@linaro.org>
> ---
> drivers/clocksource/arm_arch_timer.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index dd1040d..6de164f 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -699,7 +699,7 @@ static int __init arch_timer_register(void)
> case ARCH_TIMER_PHYS_NONSECURE_PPI:
> err = request_percpu_irq(ppi, arch_timer_handler_phys,
> "arch_timer", arch_timer_evt);
> - if (!err && arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]) {
> + if (!err && arch_timer_has_nonsecure_ppi()) {
> ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
> err = request_percpu_irq(ppi, arch_timer_handler_phys,
> "arch_timer", arch_timer_evt);
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH] mfd: twl-core: export twl_get_regmap
From: Lee Jones @ 2016-11-18 18:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478950693-13959-1-git-send-email-Nicolae_Rosia@mentor.com>
On Sat, 12 Nov 2016, Nicolae Rosia wrote:
> We want to get rid of global twl_i2c_{write/read}.
> As a first step, allow clients to get the regmap and write directly
What's stopping you from passing it through device data?
> Signed-off-by: Nicolae Rosia <Nicolae_Rosia@mentor.com>
> ---
> drivers/mfd/twl-core.c | 3 ++-
> include/linux/i2c/twl.h | 2 ++
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
> index c64615d..49e6a4b 100644
> --- a/drivers/mfd/twl-core.c
> +++ b/drivers/mfd/twl-core.c
> @@ -421,7 +421,7 @@ EXPORT_SYMBOL(twl_rev);
> *
> * Returns the regmap pointer or NULL in case of failure.
> */
> -static struct regmap *twl_get_regmap(u8 mod_no)
> +struct regmap *twl_get_regmap(u8 mod_no)
> {
> int sid;
> struct twl_client *twl;
> @@ -440,6 +440,7 @@ static struct regmap *twl_get_regmap(u8 mod_no)
>
> return twl->regmap;
> }
> +EXPORT_SYMBOL(twl_get_regmap);
>
> /**
> * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
> diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
> index 9ad7828..4c43cdb3 100644
> --- a/include/linux/i2c/twl.h
> +++ b/include/linux/i2c/twl.h
> @@ -174,6 +174,8 @@ static inline int twl_class_is_ ##class(void) \
> TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
> TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
>
> +struct regmap *twl_get_regmap(u8 mod_no);
> +
> /* Set the regcache bypass for the regmap associated with the nodule */
> int twl_set_regcache_bypass(u8 mod_no, bool enable);
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [GIT PULL] add #pinctrl-cells for v4.10
From: Tony Lindgren @ 2016-11-18 18:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118175629.GC8882@localhost>
* Olof Johansson <olof@lixom.net> [161118 10:49]:
> Hi,
>
> On Mon, Nov 14, 2016 at 04:34:19PM -0800, Tony Lindgren wrote:
> > The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
> >
> > Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
> >
> > are available in the git repository at:
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.10/pinctrl-cells-signed
> >
> > for you to fetch changes up to be76fd3197df608e1b010bf5ab90377205f54344:
> >
> > ARM: dts: Add #pinctrl-cells for pinctrl-single instances (2016-11-07 08:27:49 -0700)
> >
> > ----------------------------------------------------------------
> > Add #pinctrl-cells for pinctrl-single using dts files. This allows
> > us to use generic parser later on. Note that the driver supports
> > handling the legacy binding also with no #pinctrl-cells so these
> > changes can be queued separately from the driver changes.
>
> You forgot to make one commit per file to maximize your patch contribution
> count! :-)
Heh I've got plenty of churn commits already :)
> Merged, but note that we normally keep arm64 and arm DT updates
> separate. I'm gambling on not seeing any conflicts on the hi6220 dtsi
> this time around though, and took it in as-is.
Oh right, sorry about that. I'll split n * arch ways next time.
Regards,
Tony
^ permalink raw reply
* [GIT PULL 1/4] bcm2835-dt-next-2016-11-18
From: Eric Anholt @ 2016-11-18 18:58 UTC (permalink / raw)
To: linux-arm-kernel
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
https://github.com/anholt/linux tags/bcm2835-dt-next-2016-11-18
for you to fetch changes up to 3a1689ea752436917c5ce4487527ed6c444630ee:
ARM: bcm2835: Add names for the RPi Zero GPIO lines (2016-11-16 13:54:36 -0800)
----------------------------------------------------------------
This pull request brings in DT changes for BCM2835: pinctrl setup
cleanups, GPIO line naming, and the node for the new thermal driver.
----------------------------------------------------------------
Eric Anholt (1):
ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
Gerd Hoffmann (6):
pinctrl: bcm2835: add pull defines to dt bindings
ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
ARM: dts: bcm283x: drop alt3 from &gpio
Linus Walleij (1):
ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
Martin Sperl (2):
dt: bindings: add thermal device driver for bcm2835
ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
Stefan Wahren (4):
DT: binding: bcm2835-mbox: fix address typo in example
ARM: dts: bcm283x: fix typo in mailbox address
ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines
ARM: bcm2835: Add names for the RPi Zero GPIO lines
.../bindings/mailbox/brcm,bcm2835-mbox.txt | 2 +-
.../bindings/thermal/brcm,bcm2835-thermal.txt | 17 ++
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 67 ++++++-
arch/arm/boot/dts/bcm2835-rpi-a.dts | 69 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 68 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 68 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b.dts | 69 ++++++-
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 67 ++++++-
arch/arm/boot/dts/bcm2835-rpi.dtsi | 15 +-
arch/arm/boot/dts/bcm2835.dtsi | 6 +
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +-
arch/arm/boot/dts/bcm2836.dtsi | 6 +
arch/arm/boot/dts/bcm283x.dtsi | 212 ++++++++++++++++++++-
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 6 -
include/dt-bindings/pinctrl/bcm2835.h | 5 +
15 files changed, 658 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt
^ permalink raw reply
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