* [GIT PULL 5/10] soc: tegra: Core SoC changes for v4.10-rc1
From: Olof Johansson @ 2016-11-19 2:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118161719.24153-5-thierry.reding@gmail.com>
On Fri, Nov 18, 2016 at 05:17:14PM +0100, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.10-soc
>
> for you to fetch changes up to 4522112069a976908e32e5dd3231c9272d19794a:
>
> soc/tegra: pmc: Use consistent naming for PM domains (2016-11-15 15:51:56 +0100)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> soc: tegra: Core SoC changes for v4.10-rc1
>
> This contains mostly cleanup and new feature work on the power
> management controller as well as the addition of a Kconfig symbol for
> the new Tegra186 (Parker) SoC generation.
>
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 6/10] dt-bindings: Cleanups and additions for v4.10-rc1
From: Olof Johansson @ 2016-11-19 2:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118161719.24153-6-thierry.reding@gmail.com>
On Fri, Nov 18, 2016 at 05:17:15PM +0100, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.10-dt-bindings
>
> for you to fetch changes up to 2e002bdedcdcbd6a708f5698a09eb32df568efb8:
>
> dt-bindings: Add documentation for Tegra186 Denver (2016-11-17 18:09:05 +0100)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> dt-bindings: Cleanups and additions for v4.10-rc1
>
> Contains two small patches, one fixing a typo and the other adding the
> compatible string for the Denver CPUs found on the new Tegra186 SoCs.
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 7/10] ARM: tegra: Device tree changes for v4.10-rc1
From: Olof Johansson @ 2016-11-19 2:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118161719.24153-7-thierry.reding@gmail.com>
On Fri, Nov 18, 2016 at 05:17:16PM +0100, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.10-arm-dt
>
> for you to fetch changes up to 5e8a724d143308f3195375951b0c8f01b2ca59fe:
>
> ARM: tegra: apalis-tk1: Drop leading 0 from unit-address (2016-11-08 11:14:02 +0100)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> ARM: tegra: Device tree changes for v4.10-rc1
>
> Adds support for GMI on Tegra20 and Tegra30 and enables the GPU on Nyan
> Chromebooks. It also enables sound support on various Toradex devices.
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 8/10] ARM: tegra: Default configuration updates for v4.10-rc1
From: Olof Johansson @ 2016-11-19 2:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118161719.24153-8-thierry.reding@gmail.com>
On Fri, Nov 18, 2016 at 05:17:17PM +0100, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.10-arm-defconfig
>
> for you to fetch changes up to dafba3f6fb8614a114f939e5626447d71db864af:
>
> ARM: tegra: Enable GMI driver in default configuration (2016-11-08 11:49:41 +0100)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> ARM: tegra: Default configuration updates for v4.10-rc1
>
> Enable audio support for various Toradex devices as well as the GMI.
>
> ----------------------------------------------------------------
> Marcel Ziswiler (1):
> ARM: tegra: Enable SGTL5000 audio
>
> Thierry Reding (2):
> ARM: tegra: Update default configuration for v4.9-rc1
> ARM: tegra: Enable GMI driver in default configuration
>
> arch/arm/configs/tegra_defconfig | 27 +++++++++++++--------------
> 1 file changed, 13 insertions(+), 14 deletions(-)
> --
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 9/10] arm64: tegra: Device tree changes for v4.10-rc1
From: Olof Johansson @ 2016-11-19 2:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118161719.24153-9-thierry.reding@gmail.com>
On Fri, Nov 18, 2016 at 05:17:18PM +0100, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.10-arm64-dt
>
> for you to fetch changes up to cc13b4fa4ac780cec6c21b64a39ab2950e95e8f6:
>
> arm64: tegra: Add NVIDIA P2771 board support (2016-11-18 14:35:53 +0100)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> arm64: tegra: Device tree changes for v4.10-rc1
>
> This adds initial support for Tegra186, the P3310 processor module as
> well as the P2771 development board. Not much is functional, but there
> is enough to boot to an initial ramdisk with debug serial output.
>
> ----------------------------------------------------------------
> Dan Carpenter (1):
> mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells()
>
> Joseph Lo (6):
> soc/tegra: Add Tegra186 support
> dt-bindings: mailbox: Add Tegra HSP binding
> dt-bindings: firmware: Add bindings for Tegra BPMP
> arm64: tegra: Add Tegra186 support
> arm64: tegra: Add NVIDIA P3310 processor module support
> arm64: tegra: Add NVIDIA P2771 board support
>
> Stephen Warren (2):
> dt-bindings: Add power domains to Tegra BPMP firmware
> dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
>
> Thierry Reding (12):
> Merge branch 'for-4.10/soc' into for-4.10/mailbox
> mailbox: Add Tegra HSP driver
> Merge branch 'for-4.10/mailbox' into for-4.10/firmware
> firmware: tegra: Add IVC library
> firmware: tegra: Add BPMP support
> Merge branch 'for-4.10/firmware' into for-4.10/arm64/dt
> arm64: tegra: Add CPU nodes for Tegra186
> arm64: tegra: Add serial ports on Tegra186
> arm64: tegra: Add I2C controllers on Tegra186
> arm64: tegra: Add SDHCI controllers on Tegra186
> arm64: tegra: Add GPIO controllers on Tegra186
> arm64: tegra: Enable PSCI on P3310
The drivers->dt dependency here is annoying. Any chance you can respin without
it?
We've been encouraging people to consider using numerical clock/gpio/reset
numbers on initial submission to avoid these dependencies on dt-bindings
includes, and then follow up with a move to the symbolic names between -rc1 and
-rc2. Mind doing the same here?
Thanks!
-Olof
^ permalink raw reply
* [kvm-unit-tests PATCH v9 0/3] ARM PMU tests
From: Wei Huang @ 2016-11-19 4:15 UTC (permalink / raw)
To: linux-arm-kernel
Changes from v8:
* Probe PMU version based on ID_DFR0
* pmccntr_read() now returns 64bit and can handle both 32bit and 64bit
PMCCNTR based on PMU version.
* Add pmccntr_write() support
* Use a common printf format PRId64 to support 64bit variable smoothly in
test functions
* Add barriers to several PMU write functions
* Verfied on different execution modes
Note:
1) Current KVM code has bugs in handling PMCCFILTR write. A fix (see
below) is required for this unit testing code to work correctly under
KVM mode.
https://lists.cs.columbia.edu/pipermail/kvmarm/2016-November/022134.html.
Thanks,
-Wei
Wei Huang (3):
arm: Add PMU test
arm: pmu: Check cycle count increases
arm: pmu: Add CPI checking
arm/Makefile.common | 3 +-
arm/pmu.c | 339 ++++++++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 19 +++
3 files changed, 360 insertions(+), 1 deletion(-)
create mode 100644 arm/pmu.c
--
1.8.3.1
^ permalink raw reply
* [kvm-unit-tests PATCH v9 1/3] arm: Add PMU test
From: Wei Huang @ 2016-11-19 4:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479528942-21866-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
arm/Makefile.common | 3 ++-
arm/pmu.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 5 ++++
3 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 arm/pmu.c
diff --git a/arm/Makefile.common b/arm/Makefile.common
index ccb554d..f98f422 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -11,7 +11,8 @@ endif
tests-common = \
$(TEST_DIR)/selftest.flat \
- $(TEST_DIR)/spinlock-test.flat
+ $(TEST_DIR)/spinlock-test.flat \
+ $(TEST_DIR)/pmu.flat
all: test_cases
diff --git a/arm/pmu.c b/arm/pmu.c
new file mode 100644
index 0000000..9d9c53b
--- /dev/null
+++ b/arm/pmu.c
@@ -0,0 +1,74 @@
+/*
+ * Test the ARM Performance Monitors Unit (PMU).
+ *
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License version 2.1 and
+ * only version 2.1 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+ * for more details.
+ */
+#include "libcflat.h"
+#include "asm/barrier.h"
+
+#define PMU_PMCR_N_SHIFT 11
+#define PMU_PMCR_N_MASK 0x1f
+#define PMU_PMCR_ID_SHIFT 16
+#define PMU_PMCR_ID_MASK 0xff
+#define PMU_PMCR_IMP_SHIFT 24
+#define PMU_PMCR_IMP_MASK 0xff
+
+#if defined(__arm__)
+static inline uint32_t pmcr_read(void)
+{
+ uint32_t ret;
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret));
+ return ret;
+}
+#elif defined(__aarch64__)
+static inline uint32_t pmcr_read(void)
+{
+ uint32_t ret;
+
+ asm volatile("mrs %0, pmcr_el0" : "=r" (ret));
+ return ret;
+}
+#endif
+
+/*
+ * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't
+ * null. Also print out a couple other interesting fields for diagnostic
+ * purposes. For example, as of fall 2016, QEMU TCG mode doesn't implement
+ * event counters and therefore reports zero event counters, but hopefully
+ * support for at least the instructions event will be added in the future and
+ * the reported number of event counters will become nonzero.
+ */
+static bool check_pmcr(void)
+{
+ uint32_t pmcr;
+
+ pmcr = pmcr_read();
+
+ printf("PMU implementer: %c\n",
+ (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK);
+ printf("Identification code: 0x%x\n",
+ (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK);
+ printf("Event counters: %d\n",
+ (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK);
+
+ return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0;
+}
+
+int main(void)
+{
+ report_prefix_push("pmu");
+
+ report("Control register", check_pmcr());
+
+ return report_summary();
+}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 3f6fa45..7645180 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -54,3 +54,8 @@ file = selftest.flat
smp = $MAX_SMP
extra_params = -append 'smp'
groups = selftest
+
+# Test PMU support
+[pmu]
+file = pmu.flat
+groups = pmu
--
1.8.3.1
^ permalink raw reply related
* [kvm-unit-tests PATCH v9 2/3] arm: pmu: Check cycle count increases
From: Wei Huang @ 2016-11-19 4:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479528942-21866-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
---
arm/pmu.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 156 insertions(+)
diff --git a/arm/pmu.c b/arm/pmu.c
index 9d9c53b..fa87de4 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -15,6 +15,9 @@
#include "libcflat.h"
#include "asm/barrier.h"
+#define PMU_PMCR_E (1 << 0)
+#define PMU_PMCR_C (1 << 2)
+#define PMU_PMCR_LC (1 << 6)
#define PMU_PMCR_N_SHIFT 11
#define PMU_PMCR_N_MASK 0x1f
#define PMU_PMCR_ID_SHIFT 16
@@ -22,6 +25,14 @@
#define PMU_PMCR_IMP_SHIFT 24
#define PMU_PMCR_IMP_MASK 0xff
+#define ID_DFR0_PERFMON_SHIFT 24
+#define ID_DFR0_PERFMON_MASK 0xf
+
+#define PMU_CYCLE_IDX 31
+
+#define NR_SAMPLES 10
+
+static unsigned int pmu_version;
#if defined(__arm__)
static inline uint32_t pmcr_read(void)
{
@@ -30,6 +41,69 @@ static inline uint32_t pmcr_read(void)
asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret));
return ret;
}
+
+static inline void pmcr_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (value));
+ isb();
+}
+
+static inline void pmselr_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (value));
+ isb();
+}
+
+static inline void pmxevtyper_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (value));
+}
+
+static inline uint64_t pmccntr_read(void)
+{
+ uint32_t lo, hi = 0;
+
+ if (pmu_version == 0x3)
+ asm volatile("mrrc p15, 0, %0, %1, c9" : "=r" (lo), "=r" (hi));
+ else
+ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (lo));
+
+ return ((uint64_t)hi << 32) | lo;
+}
+
+static inline void pmccntr_write(uint64_t value)
+{
+ uint32_t lo, hi;
+
+ lo = value & 0xffffffff;
+ hi = (value >> 32) & 0xffffffff;
+
+ if (pmu_version == 0x3)
+ asm volatile("mcrr p15, 0, %0, %1, c9" : : "r" (lo), "r" (hi));
+ else
+ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (lo));
+}
+
+static inline void pmcntenset_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (value));
+}
+
+/* PMCCFILTR is an obsolete name for PMXEVTYPER31 in ARMv7 */
+static inline void pmccfiltr_write(uint32_t value)
+{
+ pmselr_write(PMU_CYCLE_IDX);
+ pmxevtyper_write(value);
+ isb();
+}
+
+static inline uint32_t id_dfr0_read(void)
+{
+ uint32_t val;
+
+ asm volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (val));
+ return val;
+}
#elif defined(__aarch64__)
static inline uint32_t pmcr_read(void)
{
@@ -38,6 +112,44 @@ static inline uint32_t pmcr_read(void)
asm volatile("mrs %0, pmcr_el0" : "=r" (ret));
return ret;
}
+
+static inline void pmcr_write(uint32_t value)
+{
+ asm volatile("msr pmcr_el0, %0" : : "r" (value));
+ isb();
+}
+
+static inline uint64_t pmccntr_read(void)
+{
+ uint64_t cycles;
+
+ asm volatile("mrs %0, pmccntr_el0" : "=r" (cycles));
+ return cycles;
+}
+
+static inline void pmccntr_write(uint64_t value)
+{
+ asm volatile("msr pmccntr_el0, %0" : : "r" (value));
+}
+
+static inline void pmcntenset_write(uint32_t value)
+{
+ asm volatile("msr pmcntenset_el0, %0" : : "r" (value));
+}
+
+static inline void pmccfiltr_write(uint32_t value)
+{
+ asm volatile("msr pmccfiltr_el0, %0" : : "r" (value));
+ isb();
+}
+
+static inline uint32_t id_dfr0_read(void)
+{
+ uint32_t id;
+
+ asm volatile("mrs %0, id_dfr0_el1" : "=r" (id));
+ return id;
+}
#endif
/*
@@ -64,11 +176,55 @@ static bool check_pmcr(void)
return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0;
}
+/*
+ * Ensure that the cycle counter progresses between back-to-back reads.
+ */
+static bool check_cycles_increase(void)
+{
+ bool success = true;
+
+ pmccntr_write(0);
+ pmcr_write(pmcr_read() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E);
+
+ for (int i = 0; i < NR_SAMPLES; i++) {
+ uint64_t a, b;
+
+ a = pmccntr_read();
+ b = pmccntr_read();
+
+ if (a >= b) {
+ printf("Read %"PRId64" then %"PRId64".\n", a, b);
+ success = false;
+ break;
+ }
+ }
+
+ pmcr_write(pmcr_read() & ~PMU_PMCR_E);
+
+ return success;
+}
+
+void pmu_init(void)
+{
+ uint32_t dfr0;
+
+ /* probe pmu version */
+ dfr0 = id_dfr0_read();
+ pmu_version = (dfr0 >> ID_DFR0_PERFMON_SHIFT) & ID_DFR0_PERFMON_MASK;
+ printf("PMU version: %d\n", pmu_version);
+
+ /* init for PMU event access, right now only care about cycle count */
+ pmcntenset_write(1 << PMU_CYCLE_IDX);
+ pmccfiltr_write(0); /* count cycles in EL0, EL1, but not EL2 */
+}
+
int main(void)
{
report_prefix_push("pmu");
+ pmu_init();
report("Control register", check_pmcr());
+ report("Monotonically increasing cycle count", check_cycles_increase());
return report_summary();
}
--
1.8.3.1
^ permalink raw reply related
* [kvm-unit-tests PATCH v9 3/3] arm: pmu: Add CPI checking
From: Wei Huang @ 2016-11-19 4:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479528942-21866-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
---
arm/pmu.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
arm/unittests.cfg | 14 +++++++
2 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index fa87de4..b36c4fb 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -104,6 +104,25 @@ static inline uint32_t id_dfr0_read(void)
asm volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (val));
return val;
}
+
+/*
+ * Extra instructions inserted by the compiler would be difficult to compensate
+ * for, so hand assemble everything between, and including, the PMCR accesses
+ * to start and stop counting.
+ */
+static inline void loop(int i, uint32_t pmcr)
+{
+ asm volatile(
+ " mcr p15, 0, %[pmcr], c9, c12, 0\n"
+ " isb\n"
+ "1: subs %[i], %[i], #1\n"
+ " bgt 1b\n"
+ " mcr p15, 0, %[z], c9, c12, 0\n"
+ " isb\n"
+ : [i] "+r" (i)
+ : [pmcr] "r" (pmcr), [z] "r" (0)
+ : "cc");
+}
#elif defined(__aarch64__)
static inline uint32_t pmcr_read(void)
{
@@ -150,6 +169,25 @@ static inline uint32_t id_dfr0_read(void)
asm volatile("mrs %0, id_dfr0_el1" : "=r" (id));
return id;
}
+
+/*
+ * Extra instructions inserted by the compiler would be difficult to compensate
+ * for, so hand assemble everything between, and including, the PMCR accesses
+ * to start and stop counting.
+ */
+static inline void loop(int i, uint32_t pmcr)
+{
+ asm volatile(
+ " msr pmcr_el0, %[pmcr]\n"
+ " isb\n"
+ "1: subs %[i], %[i], #1\n"
+ " b.gt 1b\n"
+ " msr pmcr_el0, xzr\n"
+ " isb\n"
+ : [i] "+r" (i)
+ : [pmcr] "r" (pmcr)
+ : "cc");
+}
#endif
/*
@@ -204,6 +242,71 @@ static bool check_cycles_increase(void)
return success;
}
+/*
+ * Execute a known number of guest instructions. Only odd instruction counts
+ * greater than or equal to 3 are supported by the in-line assembly code. The
+ * control register (PMCR_EL0) is initialized with the provided value (allowing
+ * for example for the cycle counter or event counters to be reset). At the end
+ * of the exact instruction loop, zero is written to PMCR_EL0 to disable
+ * counting, allowing the cycle counter or event counters to be read at the
+ * leisure of the calling code.
+ */
+static void measure_instrs(int num, uint32_t pmcr)
+{
+ int i = (num - 1) / 2;
+
+ assert(num >= 3 && ((num - 1) % 2 == 0));
+ loop(i, pmcr);
+}
+
+/*
+ * Measure cycle counts for various known instruction counts. Ensure that the
+ * cycle counter progresses (similar to check_cycles_increase() but with more
+ * instructions and using reset and stop controls). If supplied a positive,
+ * nonzero CPI parameter, also strictly check that every measurement matches
+ * it. Strict CPI checking is used to test -icount mode.
+ */
+static bool check_cpi(int cpi)
+{
+ uint32_t pmcr = pmcr_read() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E;
+
+ if (cpi > 0)
+ printf("Checking for CPI=%d.\n", cpi);
+ printf("instrs : cycles0 cycles1 ...\n");
+
+ for (unsigned int i = 3; i < 300; i += 32) {
+ uint64_t avg, sum = 0;
+
+ printf("%d :", i);
+ for (int j = 0; j < NR_SAMPLES; j++) {
+ uint64_t cycles;
+
+ pmccntr_write(0);
+ measure_instrs(i, pmcr);
+ cycles = pmccntr_read();
+ printf(" %"PRId64"", cycles);
+
+ /*
+ * The cycles taken by the loop above should fit in
+ * 32 bits easily. We check the upper 32 bits of the
+ * cycle counter to make sure there is no supprise.
+ */
+ if (!cycles || (cpi > 0 && cycles != i * cpi) ||
+ (cycles & 0xffffffff00000000)) {
+ printf("\n");
+ return false;
+ }
+
+ sum += cycles;
+ }
+ avg = sum / NR_SAMPLES;
+ printf(" sum=%"PRId64" avg=%"PRId64" avg_ipc=%"PRId64" "
+ "avg_cpi=%"PRId64"\n", sum, avg, i / avg, avg / i);
+ }
+
+ return true;
+}
+
void pmu_init(void)
{
uint32_t dfr0;
@@ -218,13 +321,19 @@ void pmu_init(void)
pmccfiltr_write(0); /* count cycles in EL0, EL1, but not EL2 */
}
-int main(void)
+int main(int argc, char *argv[])
{
+ int cpi = 0;
+
+ if (argc >= 1)
+ cpi = atol(argv[0]);
+
report_prefix_push("pmu");
pmu_init();
report("Control register", check_pmcr());
report("Monotonically increasing cycle count", check_cycles_increase());
+ report("Cycle/instruction ratio", check_cpi(cpi));
return report_summary();
}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 7645180..2050dc8 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -59,3 +59,17 @@ groups = selftest
[pmu]
file = pmu.flat
groups = pmu
+
+# Test PMU support (TCG) with -icount IPC=1
+[pmu-tcg-icount-1]
+file = pmu.flat
+extra_params = -icount 0 -append '1'
+groups = pmu
+accel = tcg
+
+# Test PMU support (TCG) with -icount IPC=256
+[pmu-tcg-icount-256]
+file = pmu.flat
+extra_params = -icount 8 -append '256'
+groups = pmu
+accel = tcg
--
1.8.3.1
^ permalink raw reply related
* [PATCH V8 2/6] thermal: bcm2835: add thermal driver for bcm2835 soc
From: Eduardo Valentin @ 2016-11-19 4:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7957B3CC-0E18-4B27-82EB-EF88B7695E28@martin.sperl.org>
Hello Martin,
Thanks for your patience to take the time to explain to me how the
firmware/linux split is done in your platform. Still, one thing is not
clear to me.
On Fri, Nov 18, 2016 at 09:32:47AM +0100, kernel at martin.sperl.org wrote:
>
> The way that firmware works on the RPI is quite different from most others I guess.
> in principle you got 2 different CPUs on the bcm2835:
> * ARM, which runs the linux instance
> * VideoCore 4, which runs the firmware (loading from SD initially) and
> then booting the ARM.
>
> So this Firmware on VC4 is the one that I am talking about.
> Without the working firmware linux can not boot on arm.
Given that "without the working firmware linux can not boot on arm",
(...)
> As far as I understand the conversion is continuous (as soon as the HW is
> configured). This case is there primarily to handle the situation where
> we initialize the HW ourselves (see line 226 and below), and we immediately
and around line 226 we have the comment:
+ /*
+ * right now the FW does set up the HW-block, so we are not
+ * touching the configuration registers.
+ * But if the HW is not enabled, then set it up
+ * using "sane" values used by the firmware right now.
+ */
> want to read the ADC value before the first conversion is finished.
>
then, does the firmware initializes the device or not?
What are the cases you would load this driver but still get an
uninitialized device? That looks like some bug workaround hidden
somewhere. Do system integrators/engineers need to be aware of this w/a?
Would the driver work right aways when the subsystem is loaded during
boot? How about module insertion?
Who has the ownership of this device?
> The above mentioned ?configuration if not running? reflect the values that
> the FW is currently setting. We should not change those values as long as the
> Firmware is also reading the temperature on its own.
hmm.. that looks like racy to me. Again, How do you synchronize accesses to
this device? What if you configure the device and right after the
firmware updates the configs? How do you make sure the configs you are
writing here are the same used by the firmware? What if the firmware
version changes? What versions of the firmware does this driver support?
Would it make sense to simply always initialize the device? Do you have
a way to tell the firmware that it should not use the device?
Or, if you want to keep the device driver simply being a dummy reader,
would it make sense to simply avoid writing configurations to the
device, and simply retry to check if the firmware gets the device
initialized?
>
> >
> >> So do you need another version of the patchset that uses that new API?
> >
> > I think the API usage is change that can be done together with
> > clarification for the above questions too: on hardware state,
> > firmware loading, maybe a master driver dependency, and the ADC
> > conversion sequence, which are not well clear to me on this driver. As long as
> > this is clarified and documented in the code (can be simple comments so
> > it is clear to whoever reads in the future), then I would be OK with
> > this driver.
>
> So how do you want this to get ?documented? in the driver?
> The setup and Firmware is a generic feature of the SOC, so if we would put
> some clarifications in this driver, then we would need to put it in every
> bcm283X driver (which seems unreasonable).
>
I think a simple comment explaining the firmware dependency and the
expected pre-conditions to get this driver working in a sane state would
do it.
A better device initialization would also be appreciated. Based on my
limited understanding of this platform, and your explanations, this
device seams to have a serious race condition with firmware while
accessing this device.
> Thanks,
> Martin
^ permalink raw reply
* [PATCH] spi: davinci: Allow device tree devices to use DMA
From: David Lechner @ 2016-11-19 4:41 UTC (permalink / raw)
To: linux-arm-kernel
This makes SPI devices specified in a device tree use DMA when the master
controller has DMA configured.
Since device tree is supposed to only describe the hardware, adding a
configuration option to device tree to enable DMA per-device would not be
acceptable. So, this is the best we can do for now to get SPI devices
working with DMA when using device tree.
Unfortunately, this excludes the possibility of using one SPI device with
DMA and one without on the same master.
I have tested this on LEGO MINDSTORMS EV3 using the NOR flash. Reading the
flash memory would fail with -EIO when DMA is not enabled for the device.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/spi/spi-davinci.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index d36c11b..c6cf73a 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -388,6 +388,7 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
static int davinci_spi_of_setup(struct spi_device *spi)
{
struct davinci_spi_config *spicfg = spi->controller_data;
+ struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
struct device_node *np = spi->dev.of_node;
u32 prop;
@@ -400,6 +401,9 @@ static int davinci_spi_of_setup(struct spi_device *spi)
if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
spicfg->wdelay = (u8)prop;
spi->controller_data = spicfg;
+ /* Use DMA for device if master supports it */
+ if (dspi->dma_rx)
+ spicfg->io_type = SPI_IO_TYPE_DMA;
}
return 0;
--
2.7.4
^ permalink raw reply related
* [GIT PULL v2] Qualcomm Device Tree Changes for v4.10
From: Andy Gross @ 2016-11-19 5:57 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-dts-for-4.10-1
for you to fetch changes up to 4c52ffc708c90b2985f941db5490145530e4df69:
ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard (2016-11-18 23:30:32 -0600)
----------------------------------------------------------------
Qualcomm Device Tree Changes for v4.10 - v2
* Add EBI2 support to MSM8660
* Add SMSC ethernet support to APQ8060
* Add support for display, pstore, iommu, and hdmi to APQ8064
* Add SDHCI node to MSM8974 Hammerhead
* Add WP8548 MangOH board support (MDM9615)
----------------------------------------------------------------
Archit Taneja (2):
arm: dts: qcom: apq8064: Add display DT nodes
arm: dts: qcom: apq8064-ifc6410: Add HDMI support
Bhushan Shah (1):
ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node
John Stultz (3):
arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes
arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7
Linus Walleij (2):
ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI
ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
Neil Armstrong (5):
ARM: dts: Add MDM9615 dtsi
dt-bindings: qcom: Add MDM9615 bindings
ARM: dts: Add Sierra Wireless WP8548 dtsi
ARM: dts: Add WP8548 based MangOH Green board DTS
dt-bindings: arm: Add Sierra Wireless modules bindings
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
Documentation/devicetree/bindings/arm/swir.txt | 12 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 119 +++++
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 77 ++-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 74 +++
arch/arm/boot/dts/qcom-apq8064.dtsi | 321 ++++++++++++
.../boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts | 281 +++++++++++
arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 170 +++++++
arch/arm/boot/dts/qcom-mdm9615.dtsi | 557 +++++++++++++++++++++
arch/arm/boot/dts/qcom-msm8660.dtsi | 17 +
.../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 29 ++
12 files changed, 1658 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/swir.txt
create mode 100644 arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
create mode 100644 arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi
^ permalink raw reply
* [PATCH] ARM: dts: msm8916: Add and enable wcnss node
From: Bjorn Andersson @ 2016-11-19 6:42 UTC (permalink / raw)
To: linux-arm-kernel
Add the wcnss remoteproc node the SMD edge and the wcnss ctrl, bluetooth
and wifi nodes specified and enable this on db410c.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
This still require the last wcn36xx and scm-interrupted patches to land, but as
those won't affect the dts I'm posting this anyway.
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 4 ++
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 13 ++++++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 73 +++++++++++++++++++++++++++++-
3 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 08bd5ebafb4e..716d3ccbc309 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -306,6 +306,10 @@
};
};
};
+
+ wcnss at a21b000 {
+ status = "okay";
+ };
};
usb2513 {
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 10c83e11c272..4cb0b5834143 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -720,4 +720,17 @@
};
};
};
+
+ wcnss_pin_a: wcnss-active {
+ pinmux {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "wcss_wlan";
+ };
+
+ pinconf {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 4221b7d2c0ce..2c692650ae43 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8916";
@@ -82,7 +83,7 @@
no-map;
};
- wcnss at 89300000 {
+ wcnss_mem: wcnss at 89300000 {
reg = <0x0 0x89300000 0x0 0x600000>;
no-map;
};
@@ -853,6 +854,76 @@
memory-region = <&mpss_mem>;
};
};
+
+ pronto: wcnss at a21b000 {
+ compatible = "qcom,pronto-v2-pil", "qcom,pronto";
+ reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ memory-region = <&wcnss_mem>;
+
+ interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ vddmx-supply = <&pm8916_l3>;
+ vddpx-supply = <&pm8916_l7>;
+
+ qcom,state = <&wcnss_smp2p_out 0>;
+ qcom,state-names = "stop";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcnss_pin_a>;
+
+ status = "disabled";
+
+ iris {
+ compatible = "qcom,wcn3620";
+
+ clocks = <&rpmcc RPM_SMD_RF_CLK2>;
+ clock-names = "xo";
+
+ vddxo-supply = <&pm8916_l7>;
+ vddrfa-supply = <&pm8916_s3>;
+ vddpa-supply = <&pm8916_l9>;
+ vdddig-supply = <&pm8916_l5>;
+ };
+
+ smd-edge {
+ interrupts = <0 142 1>;
+
+ qcom,ipc = <&apcs 8 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+
+ label = "pronto";
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&pronto>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
+ <0 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
+ };
};
smd {
--
2.5.0
^ permalink raw reply related
* [PATCH] arm: spin one more cycle in timer-based delays
From: Afzal Mohammed @ 2016-11-19 7:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <582F0DD2.3030805@free.fr>
Hi Mason,
On Fri, Nov 18, 2016 at 03:18:58PM +0100, Mason wrote:
> On 18/11/2016 13:54, Russell King - ARM Linux wrote:
> > So, NAK on this change. udelay is not super-accurate.
>
> usleep_range() fixed this issue recently.
> 6c5e9059692567740a4ee51530dffe51a4b9584d
> https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/commit/?h=timers/core&id=6c5e9059692567740a4ee51530dffe51a4b9584d
But the above "timers: Fix usleep_range() in the context of
wake_up_process()" is to avoid wakeup causing premature return than
about being precise, no ?
With conflicting opinion on delay/sleep fn's from the players, the one
in gallery would get confused.
But Linus has mentioned udelay as not meant to be precise, okay ?
Regards
afzal
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt for v4.10 (#1)
From: Gregory CLEMENT @ 2016-11-19 8:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161119015838.GG2543@localhost>
Hi Olof,
On sam., nov. 19 2016, Olof Johansson <olof@lixom.net> wrote:
> Hi,
>
> On Thu, Nov 17, 2016 at 10:50:33PM +0100, Gregory CLEMENT wrote:
>> Hi,
>>
>> Here is the first pull request for dt for mvebu for v4.10.
>>
>> I hope being able to send a second part very soon with the series
>> removing all the DT warning.
>>
>> Gregory
>>
>> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>>
>> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>>
>> are available in the git repository at:
>>
>> git://git.infradead.org/linux-mvebu.git tags/mvebu-dt-4.10-1
>>
>> for you to fetch changes up to cf20c489de6fcef88405d4febef7a078d2053b9e:
>>
>> ARM: dt: orion5x: convert ls-chl to FDT (2016-11-07 17:23:34 +0100)
>>
>> ----------------------------------------------------------------
>> mvebu fixes for 4.10 (part 1)
>>
>> Most of the commit are pinmux and i2c fix for netgear NASes
>> Fix on a wrong comment about PLL frequency
>> Bigger commit: conversion of on otion5x based board to the device tree
>>
>> ----------------------------------------------------------------
>> Ashley Hughes (1):
>> ARM: dt: orion5x: convert ls-chl to FDT
>
> This is a great conversion, but I'd like to see the code handled a
> little differently.
>
> First of all, there's no longer a need to have a config option for
> MACH_LINKSTATION_LSCHL, as long as ARCH_ORION5X_DT is enabled you'll
> be fine. So you can remove that Kconfig entry alltogether.
>
> Also, there's no need to make the DT addition and the legacy platform
> removal in one commit. It's common that we build up the DT support to the point
> that it's at parity, and then remove the legacy board. That way we also don't
> entangle DT commits with non-DT commits, which can sometimes be a bit of a pain
> (in particular for those who maintain a copy of the DT subdir in another git
> repo).
>
> So, mind respinning with this fixed? Thanks!
OK I am doing it.
Gregory
>
>
> -Olof
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt for v4.10 (#1)
From: Gregory CLEMENT @ 2016-11-19 8:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for dt for mvebu for v4.10. It repalces
the previous one sent 2 days ago as requested by Olof.
I take the opportunity to add new commits:
"ARM: dts: kirkwood: fix spelling mistake" which as applied recently but
which is harmless and trivial.
I also add all the non controversial patches removing the DTC
warning. They wre posted two weeks ago and was in linux-next since this
day. As there is still some discussions about MBUS_ID and ranges, I will
prepare a new series for them which I still hope mnage to be part of
4.10.
Gregory
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-dt-4.10-1
for you to fetch changes up to 2f7132852038deb8e364bee155f51cb477c8d2f4:
ARM: dts: armada-375: Fixup ethernet child DT warning (2016-11-19 09:16:52 +0100)
----------------------------------------------------------------
mvebu dt for 4.10 (part 1)
Add missing pinmux declaration for netgear NASes
Fix i2c compatible string for netgear NASes
Fix on a wrong comment about PLL frequency
Fix spelling mistake of the manufacturer's name of the Topkick
Add dt support for the orion5x ls-chl Linkstation device
First step of fixing DTC warning for Armada 370, 375 and XP
----------------------------------------------------------------
Ashley Hughes (1):
ARM: dts: orion5x: convert ls-chl to FDT
Chris Packham (1):
ARM: dts: mvebu: Update comment for main PLL frequency
Gregory CLEMENT (21):
ARM: dts: armada-xp-matrix: Fix the location of the pcie-controller node
ARM: dts: armada-370-xp: move the cpurst node in the common file
ARM: dts: armada-370-xp: add node labels
ARM: dts: armada-370-xp: Use the node labels
ARM: dts: armada-370-xp: Fixup mdio DT warning
ARM: dts: armada-xp: Fixup pcie DT warnings
ARM: dts: armada-370: Fixup pcie DT warnings
ARM: dts: armada-370-xp: Remove skeleton.dtsi
ARM: dts: armada-370-xp: Fixup l2-cache DT warning
ARM: dts: armada-370-xp: Fixup memory DT warning
ARM: dts: armada-370-xp: Remove address from dsa unit name
ARM: dts: armada-370-xp: Remove button address and fixup names
ARM: dts: armada-370-xp: Fixup regulator DT warning
ARM: dts: armada-375: Add node labels
ARM: dts: armada-375: Use the node labels
ARM: dts: armada-375: Fixup mdio DT warning
ARM: dts: armada-375: Fixup pcie DT warnings
ARM: dts: armada-375: Fixup pinctrl DT warnings
ARM: dts: armada-375: Remove skeleton.dtsi
ARM: dts: armada-375: Fixup memory DT warning
ARM: dts: armada-375: Fixup ethernet child DT warning
Paul Wassi (1):
ARM: dts: kirkwood: fix spelling mistake
Uwe Kleine-K?nig (6):
ARM: dts: armada-370-rn104: add pinmuxing for i2c0
ARM: dts: armada-370-rn104: drop specification of compatible for i2c0
ARM: dts: armada-xp-rn2120: drop wrong compatible for i2c0
ARM: dts: armada-xp-rn2120: add pinmuxing for ethernet
ARM: dts: armada-370-rn102: drop specification of compatible for i2c0
ARM: dts: armada-370-rn102: add pinmuxing for i2c0
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-370-db.dts | 63 ++---
arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 30 +--
arch/arm/boot/dts/armada-370-mirabox.dts | 57 ++---
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 55 +++--
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 63 ++---
arch/arm/boot/dts/armada-370-rd.dts | 57 ++---
arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts | 27 +-
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 45 ++--
.../dts/armada-370-seagate-personal-cloud.dtsi | 44 ++--
arch/arm/boot/dts/armada-370-synology-ds213j.dts | 18 +-
arch/arm/boot/dts/armada-370-xp.dtsi | 39 +--
arch/arm/boot/dts/armada-370.dtsi | 136 +++++------
arch/arm/boot/dts/armada-375-db.dts | 271 +++++++++++----------
arch/arm/boot/dts/armada-375.dtsi | 72 +++---
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
arch/arm/boot/dts/armada-39x.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-axpwifiap.dts | 68 +++---
arch/arm/boot/dts/armada-xp-db.dts | 104 ++++----
arch/arm/boot/dts/armada-xp-gp.dts | 80 +++---
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 53 ++--
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 52 ++--
arch/arm/boot/dts/armada-xp-matrix.dts | 20 +-
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 12 +-
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 20 +-
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 22 +-
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 74 +++---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 58 ++---
arch/arm/boot/dts/armada-xp-synology-ds414.dts | 75 +++---
arch/arm/boot/dts/armada-xp.dtsi | 94 +++----
arch/arm/boot/dts/kirkwood-topkick.dts | 2 +-
arch/arm/boot/dts/orion5x-lschl.dts | 171 +++++++++++++
32 files changed, 1042 insertions(+), 845 deletions(-)
create mode 100644 arch/arm/boot/dts/orion5x-lschl.dts
^ permalink raw reply
* [GIT PULL] ARM: mvebu: soc for v4.10 (#1)
From: Gregory CLEMENT @ 2016-11-19 8:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for soc for mvebu for v4.10.
On this PR there is only the removal part of the orion5x platform whcih
was initially part of the "ARM: dt: orion5x: convert ls-chl to FDT"
patch.
Gregory
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-soc-4.10-1
for you to fetch changes up to ecfe69639157b6f70f53a7bc250efb4614c0eb31:
ARM: orion5x: remove legacy support of ls-chl (2016-11-19 09:14:28 +0100)
----------------------------------------------------------------
mvebu soc for 4.10 (part 1)
remove legacy support of orion5x ls-chl
----------------------------------------------------------------
Ashley Hughes (1):
ARM: orion5x: remove legacy support of ls-chl
arch/arm/mach-orion5x/Kconfig | 7 -
arch/arm/mach-orion5x/Makefile | 1 -
arch/arm/mach-orion5x/ls-chl-setup.c | 331 -----------------------------------
3 files changed, 339 deletions(-)
delete mode 100644 arch/arm/mach-orion5x/ls-chl-setup.c
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt64 for v4.10 (#2)
From: Gregory CLEMENT @ 2016-11-19 8:45 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the second pull request for dt64 for mvebu for v4.10.
This series was posted 2 weeks ago and actually should have been part
of the first PR.
Gregory
The following changes since commit e735aaf8fc4ac84dbdb3642a135da8dcdb84587b:
arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board (2016-10-17 17:19:56 +0200)
are available in the git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-dt64-4.10-2
for you to fetch changes up to 3684534548d4cbba7d3724b3d79152eff38dc82f:
ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx (2016-11-19 09:39:07 +0100)
----------------------------------------------------------------
mvebu dt64 for 4.10 (part 2)
Fix DTC warning on Armada 37xx and 7K/8K
----------------------------------------------------------------
Gregory CLEMENT (3):
arm64: dts: marvell: Fixup internal-regs DT warning for Armada 37xx
arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K
ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 2 +-
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 +-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
^ permalink raw reply
* [GIT PULL v2] pxa-dt for v4.10
From: Robert Jarzmik @ 2016-11-19 9:51 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Kevin, and Olof,
This is the second iteration of the pxa pull request for 4.10 device-tree, with
the patch subjects fixed.
Can you please consider pulling ?
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
https://github.com/rjarzmik/linux.git tags/pxa-dt-4.10
for you to fetch changes up to 74e382b870caf297f4e1a727010c9a26cce6b6af:
ARM: dts: pxa: add pxa27x cpu operating points (2016-11-18 17:09:45 +0100)
----------------------------------------------------------------
This device-tree pxa update brings :
- pxa25x support
- cpu operating points in preparation for cpufreq-dt
- small fixes
----------------------------------------------------------------
Robert Jarzmik (4):
ARM: dts: pxa: add pxa25x .dtsi file
ARM: dts: pxa: fix gpio0 and gpio1 interrupts
ARM: dts: pxa: add pxa25x cpu operating points
ARM: dts: pxa: add pxa27x cpu operating points
Vijay Kumar (1):
ARM: dts: pxa: fix no. of gpio cells in the pxa gpio binding documentation
.../devicetree/bindings/gpio/mrvl-gpio.txt | 6 +-
arch/arm/boot/dts/pxa25x.dtsi | 117 +++++++++++++++++++++
arch/arm/boot/dts/pxa27x.dtsi | 40 +++++++
arch/arm/boot/dts/pxa2xx.dtsi | 4 +-
4 files changed, 163 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/pxa25x.dtsi
--
Robert
^ permalink raw reply
* [PATCH] ASoC: mioa701_wm9713: add missing white space in dev_err message
From: Robert Jarzmik @ 2016-11-19 9:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161112163025.4801-1-colin.king@canonical.com>
Colin King <colin.king@canonical.com> writes:
> From: Colin Ian King <colin.king@canonical.com>
>
> There is a missing whitespace in the dev_err message between
> "will" and "lead". Add the whitespace.
>
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Cheers.
--
Robert
^ permalink raw reply
* [PATCH] arm: spin one more cycle in timer-based delays
From: Russell King - ARM Linux @ 2016-11-19 11:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161119071702.GA25647@afzalpc>
Linus, please see the comment and patch at the bottom of this mail.
Thanks.
On Sat, Nov 19, 2016 at 12:47:02PM +0530, Afzal Mohammed wrote:
> Hi Mason,
>
> On Fri, Nov 18, 2016 at 03:18:58PM +0100, Mason wrote:
> > On 18/11/2016 13:54, Russell King - ARM Linux wrote:
>
> > > So, NAK on this change. udelay is not super-accurate.
> >
> > usleep_range() fixed this issue recently.
> > 6c5e9059692567740a4ee51530dffe51a4b9584d
> > https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/commit/?h=timers/core&id=6c5e9059692567740a4ee51530dffe51a4b9584d
>
> But the above "timers: Fix usleep_range() in the context of
> wake_up_process()" is to avoid wakeup causing premature return than
> about being precise, no ?
usleep*() is different from udelay(). usleep*() is not based on looping
a certain number of times, and doesn't involve calibration of such a
loop. usleep*() is based on the scheduler, which has tighter
requirements laid down in POSIX amongst other standards, such as "not
timing out before this specified time" (due to things like select(),
poll(), etc.) udelay() is purely a kernel thing, unspecified by any
standard.
> With conflicting opinion on delay/sleep fn's from the players, the one
> in gallery would get confused.
>
> But Linus has mentioned udelay as not meant to be precise, okay ?
Exactly - and the reason for that (as I've explained several times in
the past) the "standard" software delay loop calibrated against the
timer interrupt is _always_ going to be short.
I explain why this is in the message to which Linus replied:
http://lists.openwall.net/linux-kernel/2011/01/09/56
A consequence of the formula that I give in (2) in that mail is that
the higher the HZ value, the more error in the resulting value of
loops_per_jiffy, and the shorter udelay(1) than 1us will be, since
"timer_interrupt_usec" is a constant but "usec_per_jiffy" reduces.
So folk need to put the idea that "udelay(1) will always be at least
1us" out of their minds - that's simply not guaranteed by the kernel.
Linus' reply also indicates that we don't care if it's out by 5%,
and probably more than that too.
If someone can show that our timer-based udelay() produces an error
more than 5%, then I'll apply the patch. What I don't want to do is
to apply the patch because someone thinks that udelay() should not
return early. Applying it in that case has the effect of re-inforcing
what is an incorrect assumption, leading to people writing buggy drivers
that have delays which are too finely "tuned" - which may work with a
timer-based udelay() but cause failures with a loop-based udelay().
This is all about ensuring that driver authors do the right thing.
Linus, how about we add something like this to linux/delay.h to document
this fact?
include/linux/delay.h | 12 +++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/linux/delay.h b/include/linux/delay.h
index a6ecb34cf547..2ecb3c46b20a 100644
--- a/include/linux/delay.h
+++ b/include/linux/delay.h
@@ -5,6 +5,18 @@
* Copyright (C) 1993 Linus Torvalds
*
* Delay routines, using a pre-computed "loops_per_jiffy" value.
+ *
+ * Please note that ndelay(), udelay() and mdelay() may return early for
+ * several reasons:
+ * 1. computed loops_per_jiffy too low (due to the time taken to
+ * execute the timer interrupt.)
+ * 2. cache behaviour affecting the time it takes to execute the
+ * loop function.
+ * 3. CPU clock rate changes.
+ * As a result, delays should always be over-stated.
+ *
+ * Please see this thread:
+ * http://lists.openwall.net/linux-kernel/2011/01/09/56
*/
#include <linux/kernel.h>
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply related
* [PATCH next] arm64: remove "SMP: Total of %d processors activated." message
From: Russell King - ARM Linux @ 2016-11-19 11:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118101826.GC13470@arm.com>
On Fri, Nov 18, 2016 at 10:18:26AM +0000, Will Deacon wrote:
> On Fri, Nov 18, 2016 at 11:37:10AM +0800, Kefeng Wang wrote:
> > The message provides no further information than the generic code, so kill it.
> > Or show BogoMIPS like arm32?
>
> Ha! No, I don't think printing the BogoMIPS is the right solution. I just
> think that, if you insist on removing the harmless print, then you should
> also consider doing the same thing for all the other architectures that
> print the same message.
Note that I'd removed the redundant message from ARM a long time ago,
until Linus reverted the patch due to the /proc/cpuinfo part.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* Low network throughput on i.MX28
From: Stefan Wahren @ 2016-11-19 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479512941.5577.1.camel@embedded.rocks>
Hi J?rg,
> J?rg Krause <joerg.krause@embedded.rocks> hat am 19. November 2016 um 00:49
> geschrieben:
>
>
> Hi all,
>
> [snip]
>
> I did some time measurements on the wifi, mmc and dma driver to compare
> the performance between the vendor and the mainline kernel. For this I
> toggled some GPIOs and measured the time difference with an osci. I
> started measuring the time before calling sdio_readsb() in the wifi
> driver [1] and stopped the time when the call returns. Note that the
> time was only measured for a packet length of 1536 bytes.
>
> The vendor kernel took about 250 us to return whereas the mainline
> kernel took about 325 us. To investigate where this additional time
> comes from I divided the whole procedure into seperate parts and
> compared their time consumed.
>
> I noticed that the mainline kernel does took much longer to return
> after the DMA request is done, signalled in this case by calling
> mxs_mmc_dma_irq_callback() [2] in the mxs-mmc driver. From here it
> takes about 150 us to get back to sdio_readsb().
>
> An example for consuming much more time is the mainline mmc driver
> where it hangs in?mmc_wait_done() [2] about 50 us just calling
> complete(), whereas the vendor mmc driver almost immediately returns
> here.
>
> I wonder why this call to complete consumes so much time? Any ideas?
i don't know why, but how about putting the SDIO clk signal parallel to the
GPIOs at your osci? So could get a better view of the runtime behavior.
Btw you should also verify the necessary time between to 2 packets.
Stefan
>
> [1] http://lxr.free-electrons.com/source/drivers/net/wireless/broadcom/
> brcm80211/brcmfmac/bcmsdh.c#L488
>
> [2] http://lxr.free-electrons.com/source/drivers/mmc/host/mxs-mmc.c#L17
> 9
>
> [3] http://lxr.free-electrons.com/source/drivers/mmc/core/core.c#L386
>
> Best regards,
> J?rg Krause
^ permalink raw reply
* [PATCH 8/9] mfd: wm97xx-core: core support for wm97xx Codec
From: Robert Jarzmik @ 2016-11-19 11:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118165040.GB19884@dell.home>
Lee Jones <lee.jones@linaro.org> writes:
> On Wed, 26 Oct 2016, Robert Jarzmik wrote:
>> +config MFD_WM97xx
>> + tristate "Wolfson Microelectronics WM97xx"
>> + select MFD_CORE
>> + select REGMAP_AC97
>> + select AC97_BUS_COMPAT if AC97_BUS_NEW
>> + help
>> +
>
> Surplus '\n' here.
Right, for v2.
>> + The WM9705, WM9712 and WM9713 is a highly integrated hi-fi CODEC
>> + designed for smartphone applications. As well as audio functionality
>> + it has on board GPIO and a touchscreen functionality which is
>> + supported via the relevant subsystems. This driver provides core
>> + support for the WM97xx, in order to use the actual functionaltiy of
>
> Always spell check your work.
For v2.
>> + * Copyright (C) 2016 Robert Jarzmik
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Features:
>> + * - an AC97 audio codec
>> + * - a touchscreen driver
>> + * - a GPIO block
>
> Place this above the Copyright.
Right, for v2.
>> + */
>> +
>> +#include <linux/module.h>
>
> Why is this seperted?
No specific reason, I will remove the blank line, for v2.
>> +#include <linux/device.h>
>> +#include <linux/mfd/core.h>
>> +#include <linux/mfd/wm97xx.h>
>> +#include <linux/wm97xx.h>
>> +#include <linux/regmap.h>
>> +#include <linux/slab.h>
>> +#include <sound/ac97/codec.h>
>> +#include <sound/ac97/compat.h>
>
> Alphabetical.
Ah yeah, the linux/wm97xx.h ... for v2.
>> +#define WM9705_VENDOR_ID 0x574d4c05
>> +#define WM9712_VENDOR_ID 0x574d4c12
>> +#define WM9713_VENDOR_ID 0x574d4c13
>> +#define WM97xx_VENDOR_ID_MASK 0xffffffff
>
> Use tabs, not spaces.
Right, for v2.
> These are probably better represented as enums.
These are ids, just as devicetree ids, or PCI ids, I don't think an enum will
fit.
>> +struct wm97xx_priv {
>> + struct regmap *regmap;
>> + struct snd_ac97 *ac97;
>> + struct device *dev;
>> +};
>
> Replace _priv with _ddata.
Ok, will do, would you care to explain if this is something specific to your mfd
tree, or is it a kernel overall recommendation ?
> Also document using kerneldoc.
Right, for v2.
>
>> +static bool wm97xx_readable_reg(struct device *dev, unsigned int reg)
>> +{
>> + switch (reg) {
>> + case AC97_RESET ... AC97_PCM_SURR_DAC_RATE:
>> + case AC97_PCM_LR_ADC_RATE:
>> + case AC97_CENTER_LFE_MASTER:
>> + case AC97_SPDIF ... AC97_LINE1_LEVEL:
>> + case AC97_GPIO_CFG ... 0x5c:
>
> Please define.
>> + case AC97_CODEC_CLASS_REV ... AC97_PCI_SID:
>> + case 0x74 ... AC97_VENDOR_ID2:
>
> As above.
Right, for v2.
>> +static bool wm97xx_writeable_reg(struct device *dev, unsigned int reg)
>> +{
>> + switch (reg) {
>> + case AC97_VENDOR_ID1:
>> + case AC97_VENDOR_ID2:
>> + return false;
>> + default:
>> + return wm97xx_readable_reg(dev, reg);
>> + }
>> +}
>> +
>> +static const struct reg_default wm97xx_reg_defaults[] = {
>> +};
>
> What's the point in this?
Ah, that's a reminder I have still more work on this patch ... Either I remove
support for wm9705 and wm9712 in the first version, or I complete it and add the
tables :
- wm9705_reg_defaults
- wm9712_reg_defaults
>> +static int wm9705_register(struct wm97xx_priv *wm97xx)
>> +{
>> + return 0;
>> +}
>> +
>> +static int wm9712_register(struct wm97xx_priv *wm97xx)
>> +{
>> + return 0;
>> +}
>
> I don't get it?
>
> Either populate or don't provide.
Same story as above, either I complete wm9705 and wm9712 support or I remove it.
>> +static int wm9713_register(struct wm97xx_priv *wm97xx,
>> + struct wm97xx_pdata *pdata)
>> +{
>
> What are you lining this up with?
Emacs ... I don't see your point though, seeing it not aligned in the diff chunk
doesn't mean it's not properly aligned.
>> + struct wm97xx_platform_data codec_pdata;
>> + const struct mfd_cell cells[] = {
>> + {
>> + .name = "wm9713-codec",
>> + .platform_data = &codec_pdata,
>> + .pdata_size = sizeof(codec_pdata),
>> + },
>> + {
>> + .name = "wm97xx-ts",
>> + .platform_data = &codec_pdata,
>> + .pdata_size = sizeof(codec_pdata),
>> + },
>> + };
>> +
>> + codec_pdata.ac97 = wm97xx->ac97;
>> + codec_pdata.regmap = devm_regmap_init_ac97(wm97xx->ac97,
>> + &wm9713_regmap_config);
>> + codec_pdata.batt_pdata = pdata->batt_pdata;
>> + if (IS_ERR(codec_pdata.regmap))
>> + return PTR_ERR(codec_pdata.regmap);
>
> This doesn't look like pdata. You can get rid of all of this hoop
> jumping if you add it to ddata and set it as such.
You mean I should pass ddata to mfd sub-cells, right ?
>> + return devm_mfd_add_devices(wm97xx->dev, -1, cells,
>
> Use the defines.
Ok.
>
>> + ARRAY_SIZE(cells), NULL, 0, NULL);
>> +}
>> +
>> +static int wm97xx_ac97_probe(struct ac97_codec_device *adev)
>
> This looks sound specific.
>
> Why isn't this a plane platform driver?
That's the whole purpose of the patch serie.
This serie transforms the wm97xx drivers from a platform driver model to an ac97
model, where the ac97 devices are automatically discovered. The long explanation
is in patch 0/9, on how it started and what is the global purpose.
The short story is : switch to the new AC97 bus driver model.
As for the "sound specific part", it's because AC97 bus is mainly used in sound
oriented drivers, but still the codec IPs provide more than just sound, as the
Wolfson codecs for instance.
>> +{
>> + struct wm97xx_priv *wm97xx;
>> + int ret;
>> + void *pdata = snd_ac97_codec_get_platdata(adev);
>> +
>> + wm97xx = devm_kzalloc(ac97_codec_dev2dev(adev),
>> + sizeof(*wm97xx), GFP_KERNEL);
>> + if (!wm97xx)
>> + return -ENOMEM;
>> +
>> + wm97xx->dev = ac97_codec_dev2dev(adev);
>> + wm97xx->ac97 = snd_ac97_compat_alloc(adev);
>> + if (IS_ERR(wm97xx->ac97))
>> + return PTR_ERR(wm97xx->ac97);
>> +
>> +
>> + ac97_set_drvdata(adev, wm97xx);
>> + dev_info(wm97xx->dev, "wm97xx core found, id=0x%x\n",
>> + adev->vendor_id);
>
> All of this ac97/sound stuff should be done in the ac97/sound driver.
Nope, it's not sound adherence you're seeing here, it's ac97 bus and driver
model adherence you're seeing. Would the bus be in drivers/ac97 instead of
sound/ac97, the code would remain the same, would be bus be i2c you would see
the same kind of calls but with i2c_xxx and not ac97_xxx.
The wm97xx needs an ac97 bus to interact with the hardware, to provide sound,
gpio, adc, etc ... functions. That's what is expressed here, and the fact that
this ac97 access has to shared amongst the mfd sub-cells, and that these cells
require :
- wm97xx->ac97 : this one is for drivers/input/touchscreen/wm97xx-core.c
So the requirement in this case is not for ac97/sound but input/touchscreen.
>> diff --git a/include/linux/mfd/wm97xx.h b/include/linux/mfd/wm97xx.h
>> new file mode 100644
>> index 000000000000..627322f14d48
>> --- /dev/null
>> +++ b/include/linux/mfd/wm97xx.h
>> @@ -0,0 +1,31 @@
>> +/*
>> + * wm97xx client interface
>> + *
>> + * Copyright (C) 2016 Robert Jarzmik
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#ifndef __LINUX_MFD_WM97XX_H
>> +#define __LINUX_MFD_WM97XX_H
>> +
>> +struct regmap;
>> +struct wm97xx_batt_pdata;
>> +struct snd_ac97;
>
> Why can't you just add the include files?
I could, but I don't need to, do I ?
Moreover, if a mfd sub-cell doesn't use regmap for example, I won't include a
useless define.
Thanks for the review, Lee. This will iterate, I'll split out mfd patch(es) to
follow up the review with you and Mark to lessen the burden on your mailbox.
Cheers.
--
Robert
^ permalink raw reply
* [PATCH v3 1/6] Documentation: dt-bindings: Document STM32 ADC DT bindings
From: Jonathan Cameron @ 2016-11-19 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116151549.m6phclc6cqy4lj2y@rob-hp-laptop>
On 16/11/16 15:15, Rob Herring wrote:
> On Tue, Nov 15, 2016 at 04:30:56PM +0100, Fabrice Gasnier wrote:
>> This patch adds documentation of device tree bindings for the STM32 ADC.
>>
>> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
>> ---
>> .../devicetree/bindings/iio/adc/st,stm32-adc.txt | 83 ++++++++++++++++++++++
>> 1 file changed, 83 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
>
> Acked-by: Rob Herring <robh@kernel.org>
Applied to the togreg branch of iio.git.
Thanks,
Jonathan
> --
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^ permalink raw reply
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