Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / mirror / Atom feed

* [PATCH v6 2/5] drm: sun8i: add HDMI video support to A83T and H3
From: Jean-Francois Moine @ 2016-11-20  9:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1479641523.git.moinejf@free.fr>

This patch adds a HDMI video driver to the Allwinner's SoCs A83T and H3.

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
 .../devicetree/bindings/display/sunxi/hdmi.txt     |  53 ++
 drivers/gpu/drm/sun8i/Kconfig                      |   7 +
 drivers/gpu/drm/sun8i/Makefile                     |   2 +
 drivers/gpu/drm/sun8i/de2_hdmi.c                   | 394 ++++++++++
 drivers/gpu/drm/sun8i/de2_hdmi.h                   |  51 ++
 drivers/gpu/drm/sun8i/de2_hdmi_io.c                | 839 +++++++++++++++++++++
 6 files changed, 1346 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi_io.c

diff --git a/Documentation/devicetree/bindings/display/sunxi/hdmi.txt b/Documentation/devicetree/bindings/display/sunxi/hdmi.txt
new file mode 100644
index 0000000..85709ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sunxi/hdmi.txt
@@ -0,0 +1,53 @@
+Allwinner HDMI Transmitter
+==========================
+
+The Allwinner HDMI transmitters are included in the SoCs.
+They support audio and video.
+
+Required properties:
+ - #address-cells : should be <1>
+ - #size-cells : should be <0>
+ - compatible : should be one of
+		"allwinner,sun8i-a83t-hdmi"
+		"allwinner,sun8i-h3-hdmi"
+ - clocks : phandles to the HDMI clocks as described in
+	Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names : must be
+		"gate" : bus gate
+		"clock" : streaming clock
+		"ddc-clock" : DDC clock
+ - resets : One or two phandles to the HDMI resets
+ - reset-names : when 2 phandles, must be
+		"hdmi0" and "hdmi1"
+
+Required nodes:
+ - port: Audio and video input port nodes with endpoint definitions
+	as defined in Documentation/devicetree/bindings/graph.txt.
+	port at 0 is video and port at 1 is audio.
+
+Example:
+
+	hdmi: hdmi at 01ee0000 {
+		compatible = "allwinner,sun8i-a83t-hdmi";
+		reg = <0x01ee0000 0x20000>;
+		clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,
+			 <&ccu CLK_HDMI_DDC>;
+		clock-names = "gate", "clock", "ddc-clock";
+		resets = <&ccu RST_HDMI0>, <&ccu RST_HDMI1>;
+		reset-names = "hdmi0", "hdmi1";
+		...
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port at 0 {			/* video */
+			reg = <0>;
+			hdmi_lcd1: endpoint {
+				remote-endpoint = <&lcd1_hdmi>;
+			};
+		};
+		port at 1 {			/* audio */
+			reg = <1>;
+			hdmi_i2s2: endpoint {
+				remote-endpoint = <&i2s2_hdmi>;
+			};
+		};
+	};
diff --git a/drivers/gpu/drm/sun8i/Kconfig b/drivers/gpu/drm/sun8i/Kconfig
index 6940895..5c4607b 100644
--- a/drivers/gpu/drm/sun8i/Kconfig
+++ b/drivers/gpu/drm/sun8i/Kconfig
@@ -17,3 +17,10 @@ config DRM_SUN8I_DE2
 	  Choose this option if your Allwinner chipset has the DE2 interface
 	  as the A64, A83T and H3. If M is selected the module will be called
 	  sun8i-de2-drm.
+
+config DRM_SUN8I_DE2_HDMI
+	tristate "Support for DE2 HDMI"
+	depends on DRM_SUN8I_DE2
+	help
+	  Choose this option if you use want HDMI on DE2.
+	  If M is selected the module will be called sun8i-de2-hdmi.
diff --git a/drivers/gpu/drm/sun8i/Makefile b/drivers/gpu/drm/sun8i/Makefile
index f107919..6ba97c2 100644
--- a/drivers/gpu/drm/sun8i/Makefile
+++ b/drivers/gpu/drm/sun8i/Makefile
@@ -3,5 +3,7 @@
 #
 
 sun8i-de2-drm-objs := de2_drv.o de2_crtc.o de2_plane.o
+sun8i-de2-hdmi-objs := de2_hdmi.o de2_hdmi_io.o
 
 obj-$(CONFIG_DRM_SUN8I_DE2) += sun8i-de2-drm.o
+obj-$(CONFIG_DRM_SUN8I_DE2_HDMI) += sun8i-de2-hdmi.o
diff --git a/drivers/gpu/drm/sun8i/de2_hdmi.c b/drivers/gpu/drm/sun8i/de2_hdmi.c
new file mode 100644
index 0000000..9898a12
--- /dev/null
+++ b/drivers/gpu/drm/sun8i/de2_hdmi.c
@@ -0,0 +1,394 @@
+/*
+ * Allwinner DRM driver - HDMI
+ *
+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/component.h>
+#include <linux/clk.h>
+#include <linux/hdmi.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_of.h>
+
+#include "de2_hdmi.h"
+
+static const struct of_device_id de2_hdmi_dt_ids[] = {
+	{ .compatible = "allwinner,sun8i-a83t-hdmi",
+					.data = (void *) SOC_A83T },
+	{ .compatible = "allwinner,sun8i-h3-hdmi",
+					.data = (void *) SOC_H3 },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, de2_hdmi_dt_ids);
+
+#define conn_to_priv(x) \
+	container_of(x, struct de2_hdmi_priv, connector)
+
+#define enc_to_priv(x) \
+	container_of(x, struct de2_hdmi_priv, encoder)
+
+/* --- encoder functions --- */
+
+static void de2_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+				      struct drm_display_mode *mode,
+				      struct drm_display_mode *adjusted_mode)
+{
+	struct de2_hdmi_priv *priv = enc_to_priv(encoder);
+	struct clk *parent_clk;
+	u32 parent_rate;
+	int ret;
+
+	priv->cea_mode = drm_match_cea_mode(mode);
+
+	DRM_DEBUG_DRIVER("cea_mode %d\n", priv->cea_mode);
+
+	/* determine and set the best rate for the parent clock (pll-video) */
+	if ((270000 * 2) % mode->clock == 0)
+		parent_rate = 270000000;
+	else if (297000 % mode->clock == 0)
+		parent_rate = 297000000;
+	else
+		return;			/* "640x480" rejected */
+	parent_clk = clk_get_parent(priv->clk);
+
+	ret = clk_set_rate(parent_clk, parent_rate);
+	if (ret) {
+		dev_err(priv->dev, "set parent rate failed %d\n", ret);
+		return;
+	}
+	ret = clk_set_rate(priv->clk, mode->clock * 1000);
+	if (ret)
+		dev_err(priv->dev, "set rate failed %d\n", ret);
+
+	mutex_lock(&priv->mutex);
+	hdmi_io_video_mode(priv, mode);
+	mutex_unlock(&priv->mutex);
+}
+
+static void de2_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+	struct de2_hdmi_priv *priv = enc_to_priv(encoder);
+
+	mutex_lock(&priv->mutex);
+	hdmi_io_video_on(priv);
+	mutex_unlock(&priv->mutex);
+}
+
+static void de2_hdmi_encoder_disable(struct drm_encoder *encoder)
+{
+	struct de2_hdmi_priv *priv = enc_to_priv(encoder);
+
+	mutex_lock(&priv->mutex);
+	hdmi_io_video_off(priv);
+	mutex_unlock(&priv->mutex);
+}
+
+static const struct drm_encoder_helper_funcs de2_hdmi_encoder_helper_funcs = {
+	.mode_set = de2_hdmi_encoder_mode_set,
+	.enable = de2_hdmi_encoder_enable,
+	.disable = de2_hdmi_encoder_disable,
+};
+
+static const struct drm_encoder_funcs de2_hdmi_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+/* --- connector functions --- */
+
+static int de2_hdmi_connector_mode_valid(struct drm_connector *connector,
+					struct drm_display_mode *mode)
+{
+	int cea_mode = drm_match_cea_mode(mode);
+
+	if (hdmi_io_mode_valid(cea_mode) < 0)
+		return MODE_NOMODE;
+
+	return MODE_OK;
+}
+
+static enum drm_connector_status de2_hdmi_connector_detect(
+				struct drm_connector *connector, bool force)
+{
+	struct de2_hdmi_priv *priv = conn_to_priv(connector);
+	int ret;
+
+	mutex_lock(&priv->mutex);
+	ret = hdmi_io_get_hpd(priv);
+	mutex_unlock(&priv->mutex);
+
+	return ret ? connector_status_connected :
+			connector_status_disconnected;
+}
+
+static int read_edid_block(void *data, u8 *buf,
+			   unsigned int blk, size_t length)
+{
+	struct de2_hdmi_priv *priv = data;
+	int ret;
+
+	mutex_lock(&priv->mutex);
+	ret = hdmi_io_ddc_read(priv,
+				blk / 2, (blk & 1) ? 128 : 0,
+				length, buf);
+	mutex_unlock(&priv->mutex);
+
+	return ret;
+}
+
+static int de2_hdmi_connector_get_modes(struct drm_connector *connector)
+{
+	struct de2_hdmi_priv *priv = conn_to_priv(connector);
+	struct edid *edid;
+	int n;
+
+	edid = drm_do_get_edid(connector, read_edid_block, priv);
+
+	if (!edid) {
+		dev_warn(priv->dev, "failed to read EDID\n");
+		if (!connector->cmdline_mode.specified)
+			return 0;
+
+		return drm_add_modes_noedid(connector,
+					connector->cmdline_mode.xres,
+					connector->cmdline_mode.yres);
+	}
+
+	drm_mode_connector_update_edid_property(connector, edid);
+	n = drm_add_edid_modes(connector, edid);
+
+	drm_edid_to_eld(connector, edid);
+
+	kfree(edid);
+
+	DRM_DEBUG_DRIVER("%s EDID ok %d modes\n",
+		connector->eld[0] ? "HDMI" : "DVI", n);
+
+	return n;
+}
+
+static const
+struct drm_connector_helper_funcs de2_hdmi_connector_helper_funcs = {
+	.get_modes = de2_hdmi_connector_get_modes,
+	.mode_valid = de2_hdmi_connector_mode_valid,
+};
+
+static const struct drm_connector_funcs de2_hdmi_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.reset = drm_atomic_helper_connector_reset,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = de2_hdmi_connector_detect,
+	.destroy = drm_connector_cleanup,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static void de2_hdmi_cleanup(struct de2_hdmi_priv *priv)
+{
+	clk_disable_unprepare(priv->clk_ddc);
+	clk_disable_unprepare(priv->clk);
+	clk_disable_unprepare(priv->gate);
+	reset_control_assert(priv->reset1);
+	reset_control_assert(priv->reset0);
+}
+
+static int de2_hdmi_bind(struct device *dev, struct device *master, void *data)
+{
+	struct drm_device *drm = data;
+	struct de2_hdmi_priv *priv = dev_get_drvdata(dev);
+	struct drm_encoder *encoder = &priv->encoder;
+	struct drm_connector *connector = &priv->connector;
+	int ret;
+
+	encoder->possible_crtcs =
+			drm_of_find_possible_crtcs(drm, dev->of_node);
+
+	/* if no CRTC, delay */
+	if (encoder->possible_crtcs == 0)
+		return -EPROBE_DEFER;
+
+	/* HDMI init */
+	ret = reset_control_deassert(priv->reset0);
+	if (ret)
+		goto err;
+	ret = reset_control_deassert(priv->reset1);
+	if (ret)
+		goto err;
+	ret = clk_prepare_enable(priv->gate);
+	if (ret)
+		goto err;
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		goto err;
+	ret = clk_prepare_enable(priv->clk_ddc);
+	if (ret)
+		goto err;
+
+	mutex_lock(&priv->mutex);
+	hdmi_io_init(priv);
+	mutex_unlock(&priv->mutex);
+
+	/* encoder init */
+	ret = drm_encoder_init(drm, encoder, &de2_hdmi_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS, NULL);
+	if (ret)
+		goto err;
+
+	drm_encoder_helper_add(encoder, &de2_hdmi_encoder_helper_funcs);
+
+	/* connector init */
+	ret = drm_connector_init(drm, connector,
+				 &de2_hdmi_connector_funcs,
+				 DRM_MODE_CONNECTOR_HDMIA);
+	if (ret)
+		goto err_connector;
+
+	connector->interlace_allowed = 1;
+	connector->polled = DRM_CONNECTOR_POLL_CONNECT |
+				 DRM_CONNECTOR_POLL_DISCONNECT;
+	drm_connector_helper_add(connector,
+				 &de2_hdmi_connector_helper_funcs);
+
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	return 0;
+
+err_connector:
+	drm_encoder_cleanup(encoder);
+err:
+	dev_err(dev, "err %d\n", ret);
+	return ret;
+}
+
+static void de2_hdmi_unbind(struct device *dev, struct device *master,
+			   void *data)
+{
+	struct de2_hdmi_priv *priv = dev_get_drvdata(dev);
+
+	if (priv->connector.dev)
+		drm_connector_cleanup(&priv->connector);
+	drm_encoder_cleanup(&priv->encoder);
+	de2_hdmi_cleanup(priv);
+}
+
+static const struct component_ops de2_hdmi_ops = {
+	.bind = de2_hdmi_bind,
+	.unbind = de2_hdmi_unbind,
+};
+
+static int de2_hdmi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct de2_hdmi_priv *priv;
+	struct resource *res;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, priv);
+	priv->dev = dev;
+
+	mutex_init(&priv->mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "failed to get memory resource\n");
+		return -ENXIO;
+	}
+	priv->mmio = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->mmio)) {
+		ret = PTR_ERR(priv->mmio);
+		dev_err(dev, "failed to map registers err %d\n", ret);
+		return ret;
+	}
+
+	priv->gate = devm_clk_get(dev, "bus");
+	if (IS_ERR(priv->gate)) {
+		ret = PTR_ERR(priv->gate);
+		dev_err(dev, "gate clock err %d\n", ret);
+		return ret;
+	}
+
+	priv->clk = devm_clk_get(dev, "clock");
+	if (IS_ERR(priv->clk)) {
+		ret = PTR_ERR(priv->clk);
+		dev_err(dev, "hdmi clock err %d\n", ret);
+		return ret;
+	}
+
+	priv->clk_ddc = devm_clk_get(dev, "ddc-clock");
+	if (IS_ERR(priv->clk_ddc)) {
+		ret = PTR_ERR(priv->clk_ddc);
+		dev_err(dev, "hdmi-ddc clock err %d\n", ret);
+		return ret;
+	}
+
+	priv->reset0 = devm_reset_control_get(dev, "hdmi0");
+	if (IS_ERR(priv->reset0)) {
+		ret = PTR_ERR(priv->reset0);
+		dev_err(dev, "reset controller err %d\n", ret);
+		return ret;
+	}
+
+	priv->reset1 = devm_reset_control_get(dev, "hdmi1");
+	if (IS_ERR(priv->reset1)) {
+		ret = PTR_ERR(priv->reset1);
+		dev_err(dev, "reset controller err %d\n", ret);
+		return ret;
+	}
+
+	priv->soc_type = (int) of_match_device(de2_hdmi_dt_ids,
+						&pdev->dev)->data;
+
+	return component_add(dev, &de2_hdmi_ops);
+}
+
+static int de2_hdmi_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &de2_hdmi_ops);
+
+	return 0;
+}
+
+static struct platform_driver de2_hdmi_driver = {
+	.probe = de2_hdmi_probe,
+	.remove = de2_hdmi_remove,
+	.driver = {
+		.name = "sun8i-de2-hdmi",
+		.of_match_table = of_match_ptr(de2_hdmi_dt_ids),
+	},
+};
+
+/* create the video HDMI driver */
+static int __init de2_hdmi_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&de2_hdmi_driver);
+
+	return ret;
+}
+
+static void __exit de2_hdmi_fini(void)
+{
+	platform_driver_unregister(&de2_hdmi_driver);
+}
+
+module_init(de2_hdmi_init);
+module_exit(de2_hdmi_fini);
+
+MODULE_AUTHOR("Jean-Francois Moine <moinejf@free.fr>");
+MODULE_DESCRIPTION("Allwinner DE2 HDMI encoder/connector");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/sun8i/de2_hdmi.h b/drivers/gpu/drm/sun8i/de2_hdmi.h
new file mode 100644
index 0000000..1f0b1d9
--- /dev/null
+++ b/drivers/gpu/drm/sun8i/de2_hdmi.h
@@ -0,0 +1,51 @@
+#ifndef __DE2_HDMI_H__
+#define __DE2_HDMI_H__
+/*
+ * Copyright (C) 2016 Jean-Fran??ois Moine
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <drm/drmP.h>
+
+/* SoC types */
+#define SOC_A83T 0
+#define SOC_H3 1
+
+struct de2_hdmi_priv {
+	struct device *dev;
+	void __iomem *mmio;
+
+	struct drm_encoder encoder;
+	struct drm_connector connector;
+
+	struct clk *clk;
+	struct clk *clk_ddc;
+	struct clk *gate;
+	struct reset_control *reset0;
+	struct reset_control *reset1;
+
+	struct mutex mutex;
+	u8 soc_type;
+	u8 cea_mode;
+};
+
+/* in de2_hdmi_io.c */
+void hdmi_io_init(struct de2_hdmi_priv *priv);
+void hdmi_io_video_on(struct de2_hdmi_priv *priv);
+void hdmi_io_video_off(struct de2_hdmi_priv *priv);
+int hdmi_io_video_mode(struct de2_hdmi_priv *priv,
+			struct drm_display_mode *mode);
+int hdmi_io_ddc_read(struct de2_hdmi_priv *priv,
+			char pointer, char offset,
+			int nbyte, char *pbuf);
+int hdmi_io_get_hpd(struct de2_hdmi_priv *priv);
+int hdmi_io_mode_valid(int cea_mode);
+
+#endif /* __DE2_HDMI_H__ */
diff --git a/drivers/gpu/drm/sun8i/de2_hdmi_io.c b/drivers/gpu/drm/sun8i/de2_hdmi_io.c
new file mode 100644
index 0000000..8c690bf
--- /dev/null
+++ b/drivers/gpu/drm/sun8i/de2_hdmi_io.c
@@ -0,0 +1,839 @@
+/*
+ * Allwinner A83T and H3 HDMI lowlevel functions
+ *
+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
+ * Adapted from the sun8iw6 and sun8iw7 disp2 drivers
+ *	Copyright (c) 2016 Allwinnertech Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/*
+ * The HDMI controller in the A83T and H3 seems to be a
+ * Synopsys DesignWare HDMI controller.
+ * The PHYs are unknown.
+ * Documentation:
+ *	https://linux-sunxi.org/DWC_HDMI_Controller
+ *	https://www.synopsys.com/dw/doc.php/ds/c/dwc_hdmi_tx_csds.pdf
+ */
+
+#include <linux/hdmi.h>
+
+#include "de2_hdmi.h"
+
+/* guessed PHY registers */
+#define HDMI_PHY_LOCK_READ_REG	0x10010
+#define HDMI_PHY_CTRL_REG	0x10020
+#define HDMI_PHY_24_REG		0x10024
+#define HDMI_PHY_28_REG		0x10028
+#define HDMI_PHY_PLL_REG	0x1002c
+#define HDMI_PHY_CLK_REG	0x10030
+#define HDMI_PHY_34_REG		0x10034
+#define HDMI_PHY_STATUS_REG	0x10038
+
+/* DW registers (obfuscated addresses) */
+
+/* Interrupt Registers */
+#define R_0100_HDMI_IH_FC_STAT0 0x0010
+#define R_0101_HDMI_IH_FC_STAT1 0x0011
+#define R_0102_HDMI_IH_FC_STAT2 0x8010
+#define R_0103_HDMI_IH_AS_STAT0 0x8011
+#define R_0104_HDMI_IH_PHY_STAT0 0x0012
+#define R_0105_HDMI_IH_I2CM_STAT0 0x0013
+#define R_0106_HDMI_IH_CEC_STAT0 0x8012
+#define R_0107_HDMI_IH_VP_STAT0 0x8013
+#define R_0108_HDMI_IH_I2CMPHY_STAT0 0x4010
+#define R_01ff_HDMI_IH_MUTE 0xf01f
+
+/* Video Sample Registers */
+#define R_0200_HDMI_TX_INVID0 0x0800
+#define R_0201_HDMI_TX_INSTUFFING 0x0801
+#define R_0202_HDMI_TX_GYDATA0 0x8800
+#define R_0203_HDMI_TX_GYDATA1 0x8801
+#define R_0204_HDMI_TX_RCRDATA0 0x0802
+#define R_0205_HDMI_TX_RCRDATA1 0x0803
+#define R_0206_HDMI_TX_BCBDATA0 0x8802
+#define R_0207_HDMI_TX_BCBDATA1 0x8803
+
+/* Video Packetizer Registers */
+#define R_0801_HDMI_VP_PR_CD 0x0401
+#define R_0802_HDMI_VP_STUFF 0x8400
+#define R_0803_HDMI_VP_REMAP 0x8401
+#define R_0804_HDMI_VP_CONF 0x0402
+#define R_0807_HDMI_VP_MASK 0x8403
+
+/* Frame Composer Registers */
+#define R_1000_HDMI_FC_INVIDCONF 0x0040
+#define		HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH 0x10
+#define R_1001_HDMI_FC_INHACTV0 0x0041
+#define R_1002_HDMI_FC_INHACTV1 0x8040
+#define R_1003_HDMI_FC_INHBLANK0 0x8041
+#define R_1004_HDMI_FC_INHBLANK1 0x0042
+#define R_1005_HDMI_FC_INVACTV0 0x0043
+#define R_1006_HDMI_FC_INVACTV1 0x8042
+#define R_1007_HDMI_FC_INVBLANK 0x8043
+#define R_1008_HDMI_FC_HSYNCINDELAY0 0x4040
+#define R_1009_HDMI_FC_HSYNCINDELAY1 0x4041
+#define R_100a_HDMI_FC_HSYNCINWIDTH0 0xc040
+#define R_100b_HDMI_FC_HSYNCINWIDTH1 0xc041
+#define R_100c_HDMI_FC_VSYNCINDELAY 0x4042
+#define R_100d_HDMI_FC_VSYNCINWIDTH 0x4043
+#define R_1011_HDMI_FC_CTRLDUR 0x0045
+#define R_1012_HDMI_FC_EXCTRLDUR 0x8044
+#define R_1013_HDMI_FC_EXCTRLSPAC 0x8045
+#define R_1014_HDMI_FC_CH0PREAM 0x0046
+#define R_1015_HDMI_FC_CH1PREAM 0x0047
+#define R_1016_HDMI_FC_CH2PREAM 0x8046
+#define R_1018_HDMI_FC_GCP 0x4044
+#define R_1019_HDMI_FC_AVICONF0 0x4045
+#define		HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN 0x20
+#define R_101a_HDMI_FC_AVICONF1 0xc044
+#define R_101b_HDMI_FC_AVICONF2 0xc045
+#define R_101c_HDMI_FC_AVIVID 0x4046
+#define R_1025_HDMI_FC_AUDICONF0 0x2043
+#define R_1026_HDMI_FC_AUDICONF1 0xa042
+#define R_1027_HDMI_FC_AUDICONF2 0xa043
+#define R_1028_HDMI_FC_AUDICONF3 0x6040
+#define R_1029_HDMI_FC_VSDIEEEID0 0x6041
+#define R_1030_HDMI_FC_VSDIEEEID1 0x2044
+#define R_1031_HDMI_FC_VSDIEEEID2 0x2045
+#define R_1032_HDMI_FC_VSDPAYLOAD0 0xa044
+#define R_1033_HDMI_FC_VSDPAYLOAD1 0xa045
+#define R_1034_HDMI_FC_VSDPAYLOAD2 0x2046
+#define R_1063_HDMI_FC_AUDSCONF 0xa049
+#define R_1065_HDMI_FC_AUDSV 0x204b
+#define R_1066_HDMI_FC_AUDSU 0xa04a
+#define R_1067_HDMI_FC_AUDSCHNLS0 0xa04b
+#define		HDMI_FC_AUDSCHNLS0_CGMSA 0x30
+#define R_1068_HDMI_FC_AUDSCHNLS1 0x6048
+#define R_1069_HDMI_FC_AUDSCHNLS2 0x6049
+#define R_106a_HDMI_FC_AUDSCHNLS3 0xe048
+#define		HDMI_FC_AUDSCHNLS3_OIEC_CH0(v) (v)
+#define		HDMI_FC_AUDSCHNLS3_OIEC_CH1(v) (v << 4)
+#define R_106b_HDMI_FC_AUDSCHNLS4 0xe049
+#define		HDMI_FC_AUDSCHNLS4_OIEC_CH2(v) (v)
+#define		HDMI_FC_AUDSCHNLS4_OIEC_CH3(v) (v << 4)
+#define R_106c_HDMI_FC_AUDSCHNLS5 0x604a
+#define		HDMI_FC_AUDSCHNLS5_OIEC_CH0(v) (v)
+#define		HDMI_FC_AUDSCHNLS5_OIEC_CH1(v) (v << 4)
+#define R_106d_HDMI_FC_AUDSCHNLS6 0x604b
+#define		HDMI_FC_AUDSCHNLS6_OIEC_CH2(v) (v)
+#define		HDMI_FC_AUDSCHNLS6_OIEC_CH3(v) (v << 4)
+#define R_106e_HDMI_FC_AUDSCHNLS7 0xe04a
+#define R_106f_HDMI_FC_AUDSCHNLS8 0xe04b
+#define		HDMI_FC_AUDSCHNLS8_WORDLENGTH(v) (v)
+#define R_10b3_HDMI_FC_DATAUTO0 0xb045
+#define R_10b4_HDMI_FC_DATAUTO1 0x3046
+#define R_10b5_HDMI_FC_DATAUTO2 0x3047
+#define R_10d2_HDMI_FC_MASK0 0x904c
+#define R_10d6_HDMI_FC_MASK1 0x904e
+#define R_10da_HDMI_FC_MASK2 0xd04c
+#define R_10e0_HDMI_FC_PRCONF 0x3048
+#define R_1103_HDMI_FC_GMD_CONF 0x8051
+#define R_1104_HDMI_FC_GMD_HB 0x0052
+#define R_1200_HDMI_FC_DBGFORCE 0x0840
+#define		HDMI_FC_DBGFORCE_FORCEAUDIO BIT(4)
+#define		HDMI_FC_DBGFORCE_FORCEVIDEO BIT(0)
+#define R_1219_HDMI_FC_DBGTMDS0 0x4845
+
+/* HDMI Source PHY Registers */
+#define R_3000_HDMI_PHY_CONF0 0x0240
+#define		HDMI_PHY_CONF0_PDZ BIT(7)
+#define		HDMI_PHY_CONF0_ENTMDS BIT(6)
+#define		HDMI_PHY_CONF0_SPARECTRL BIT(5)
+#define		HDMI_PHY_CONF0_GEN2_PDDQ BIT(4)
+#define		HDMI_PHY_CONF0_GEN2_TXPWRON BIT(3)
+#define		HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE BIT(2)
+#define		HDMI_PHY_CONF0_SELDATAENPOL BIT(1)
+#define		HDMI_PHY_CONF0_SELDIPIF BIT(0)
+#define R_3001_HDMI_PHY_TST0 0x0241
+#define		HDMI_PHY_TST0_TSTCLR BIT(5)
+#define R_3005_HDMI_PHY_INT0 0x0243
+#define R_3006_HDMI_PHY_MASK0 0x8242
+
+/* HDMI Master PHY Registers */
+#define R_3020_HDMI_PHY_I2CM_SLAVE_ADDR 0x2240
+#define		HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 0x69
+#define R_3021_HDMI_PHY_I2CM_ADDRESS_ADDR 0x2241
+#define R_3022_HDMI_PHY_I2CM_DATAO_1_ADDR 0xa240
+#define R_3023_HDMI_PHY_I2CM_DATAO_0_ADDR 0xa241
+#define R_3026_HDMI_PHY_I2CM_OPERATION_ADDR 0xa242
+#define		HDMI_PHY_I2CM_OPERATION_ADDR_WRITE 0x10
+#define R_3027_HDMI_PHY_I2CM_INT_ADDR 0xa243
+#define R_3028_HDMI_PHY_I2CM_CTLINT_ADDR 0x6240
+
+/* Audio Sampler Registers */
+#define R_3100_HDMI_AUD_CONF0 0x0250
+#define		HDMI_AUD_CONF0_SW_RESET 0x80
+#define		HDMI_AUD_CONF0_I2S_ALL_ENABLE 0x2f
+#define R_3101_HDMI_AUD_CONF1 0x0251
+#define R_3102_HDMI_AUD_INT 0x8250
+#define R_3103_HDMI_AUD_CONF2 0x8251
+#define R_3200_HDMI_AUD_N1 0x0a40
+#define R_3201_HDMI_AUD_N2 0x0a41
+#define R_3202_HDMI_AUD_N3 0x8a40
+#define R_3205_HDMI_AUD_CTS3 0x0a43
+#define R_3206_HDMI_AUD_INPUTCLKFS 0x8a42
+#define		HDMI_AUD_INPUTCLKFS_64FS 0x04
+#define R_3302_HDMI_AUD_SPDIFINT 0x8a50
+
+/* Generic Parallel Audio Interface Registers */
+#define R_3506_HDMI_GP_POL 0x8272
+
+/* Main Controller Registers */
+#define R_4001_HDMI_MC_CLKDIS 0x0081
+#define		HDMI_MC_CLKDIS_HDCPCLK_DISABLE BIT(6)
+#define		HDMI_MC_CLKDIS_AUDCLK_DISABLE BIT(3)
+#define		HDMI_MC_CLKDIS_TMDSCLK_DISABLE BIT(1)
+#define R_4002_HDMI_MC_SWRSTZ 0x8080
+#define R_4004_HDMI_MC_FLOWCTRL 0x0082
+#define R_4005_HDMI_MC_PHYRSTZ 0x0083
+#define		HDMI_MC_PHYRSTZ_DEASSERT BIT(0)
+
+/* HDCP Encryption Engine Registers */
+#define R_5000_HDMI_A_HDCPCFG0 0x00c0
+#define R_5001_HDMI_A_HDCPCFG1 0x00c1
+#define		HDMI_A_HDCPCFG1_PH2UPSHFTENC BIT(2)
+#define		HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE BIT(1)
+#define		HDMI_A_HDCPCFG1_SWRESET BIT(0)
+#define R_5008_HDMI_A_APIINTMSK 0x40c0
+#define R_5009_HDMI_A_VIDPOLCFG 0x40c1
+#define		HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH BIT(4)
+
+/* CEC Engine Registers */
+#define R_7d02_HDMI_CEC_MASK 0x86f0
+
+/* I2C Master Registers (E-DDC) */
+#define R_7e00_HDMI_I2CM_SLAVE 0x0ee0
+#define R_7e01_HDMI_I2CM_ADDRESS 0x0ee1
+#define R_7e03_HDMI_I2CM_DATAI 0x8ee1
+#define R_7e04_HDMI_I2CM_OPERATION 0x0ee2
+#define		HDMI_I2CM_OPERATION_DDC_READ 0x02
+#define R_7e05_HDMI_I2CM_INT 0x0ee3
+#define R_7e06_HDMI_I2CM_CTLINT 0x8ee2
+#define R_7e07_HDMI_I2CM_DIV 0x8ee3
+#define R_7e08_HDMI_I2CM_SEGADDR 0x4ee0
+#define R_7e09_HDMI_I2CM_SOFTRSTZ 0x4ee1
+#define R_7e0a_HDMI_I2CM_SEGPTR 0xcee0
+#define R_7e0b_HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0xcee1
+#define R_7e0c_HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x4ee2
+#define R_7e0d_HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x4ee3
+#define R_7e0e_HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0xcee2
+#define R_7e0f_HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0xcee3
+#define R_7e10_HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x0ee4
+#define R_7e11_HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x0ee5
+
+#define VIC_720x480_60		2
+#define VIC_1280x720_60		4
+#define VIC_1920x1080i_60	5
+#define VIC_720x480i_60		6
+#define VIC_1920x1080_60	16
+#define VIC_720x576_50		17
+#define VIC_1280x720_50		19
+#define VIC_1920x1080i_50	20
+#define VIC_720x576i_50		21
+#define VIC_1920x1080_50	31
+#define VIC_1920x1080_24	32
+#define VIC_1920x1080_25	33
+#define VIC_1920x1080_30	34
+
+static inline u8 hdmi_readb(struct de2_hdmi_priv *priv, u32 addr)
+{
+	return readb_relaxed(priv->mmio + addr);
+}
+
+static inline u32 hdmi_readl(struct de2_hdmi_priv *priv, u32 addr)
+{
+	return readl_relaxed(priv->mmio + addr);
+}
+
+static inline void hdmi_writeb(struct de2_hdmi_priv *priv, u32 addr, u8 data)
+{
+	writeb_relaxed(data, priv->mmio + addr);
+}
+
+static inline void hdmi_writel(struct de2_hdmi_priv *priv, u32 addr, u32 data)
+{
+	writel_relaxed(data, priv->mmio + addr);
+}
+
+static inline void hdmi_orb(struct de2_hdmi_priv *priv, u32 addr, u8 data)
+{
+	writeb_relaxed(readb_relaxed(priv->mmio + addr) | data,
+			priv->mmio + addr);
+}
+
+static inline void hdmi_orl(struct de2_hdmi_priv *priv, u32 addr, u32 data)
+{
+	writel_relaxed(readl_relaxed(priv->mmio + addr) | data,
+			priv->mmio + addr);
+}
+
+static inline void hdmi_andl(struct de2_hdmi_priv *priv, u32 addr, u32 data)
+{
+	writel_relaxed(readl_relaxed(priv->mmio + addr) & data,
+			priv->mmio + addr);
+}
+
+/* read lock/unlock functions */
+static inline void hdmi_lock_read(struct de2_hdmi_priv *priv)
+{
+	hdmi_writel(priv, HDMI_PHY_LOCK_READ_REG, 0x54524545);
+}
+static inline void hdmi_unlock_read(struct de2_hdmi_priv *priv)
+{
+	hdmi_writel(priv, HDMI_PHY_LOCK_READ_REG, 0x57415452);
+}
+
+static void hdmi_inner_init(struct de2_hdmi_priv *priv)
+{
+	u8 clkdis = priv->soc_type == SOC_H3 ?
+				~HDMI_MC_CLKDIS_TMDSCLK_DISABLE : 0xff;
+
+	hdmi_lock_read(priv);
+
+	/* software reset */
+	hdmi_writeb(priv, R_4002_HDMI_MC_SWRSTZ,  0x00);
+	udelay(2);
+
+	/* mask all interrupts */
+	hdmi_writeb(priv, R_01ff_HDMI_IH_MUTE, 0x00);
+	hdmi_writeb(priv, R_0807_HDMI_VP_MASK, 0xff);
+	hdmi_writeb(priv, R_10d2_HDMI_FC_MASK0, 0xff);
+	hdmi_writeb(priv, R_10d6_HDMI_FC_MASK1, 0xff);
+	hdmi_writeb(priv, R_10da_HDMI_FC_MASK2, 0xff);
+	hdmi_writeb(priv, R_3102_HDMI_AUD_INT, 0xff);
+	hdmi_writeb(priv, R_3302_HDMI_AUD_SPDIFINT, 0xff);
+	hdmi_writeb(priv, R_3506_HDMI_GP_POL, 0xff);
+	hdmi_writeb(priv, R_5008_HDMI_A_APIINTMSK, 0xff);
+	hdmi_writeb(priv, R_7d02_HDMI_CEC_MASK, 0xff);
+	hdmi_writeb(priv, R_7e05_HDMI_I2CM_INT, 0xff);
+	hdmi_writeb(priv, R_7e06_HDMI_I2CM_CTLINT, 0xff);
+
+	hdmi_writeb(priv, R_1063_HDMI_FC_AUDSCONF, 0xf0);
+	hdmi_writeb(priv, R_10b3_HDMI_FC_DATAUTO0, 0x1e);
+	hdmi_writeb(priv, R_5001_HDMI_A_HDCPCFG1, 0x00);
+	hdmi_writeb(priv, R_5001_HDMI_A_HDCPCFG1,
+				HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE |
+				HDMI_A_HDCPCFG1_SWRESET);
+	hdmi_writeb(priv, R_5000_HDMI_A_HDCPCFG0, 0x00);
+	hdmi_writeb(priv, R_5009_HDMI_A_VIDPOLCFG,
+				HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH);
+	hdmi_writeb(priv, R_4001_HDMI_MC_CLKDIS, clkdis);
+	hdmi_writeb(priv, R_4001_HDMI_MC_CLKDIS, 0x00);
+	hdmi_writeb(priv, R_4001_HDMI_MC_CLKDIS, clkdis);
+	hdmi_writeb(priv, R_0100_HDMI_IH_FC_STAT0, 0xff);
+	hdmi_writeb(priv, R_0101_HDMI_IH_FC_STAT1, 0xff);
+	hdmi_writeb(priv, R_0102_HDMI_IH_FC_STAT2, 0xff);
+	hdmi_writeb(priv, R_0103_HDMI_IH_AS_STAT0, 0xff);
+	hdmi_writeb(priv, R_0105_HDMI_IH_I2CM_STAT0, 0xff);
+	hdmi_writeb(priv, R_0106_HDMI_IH_CEC_STAT0, 0xff);
+	hdmi_writeb(priv, R_0107_HDMI_IH_VP_STAT0, 0xff);
+}
+
+static void hdmi_phy_init_a83t(struct de2_hdmi_priv *priv)
+{
+	hdmi_inner_init(priv);
+
+	hdmi_writeb(priv, 0x10000, 0x01);
+	hdmi_writeb(priv, 0x10001, 0x00);
+	hdmi_writeb(priv, 0x10002, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
+	hdmi_writeb(priv, 0x10003, 0x00);
+	hdmi_writeb(priv, 0x10007, 0xa0);
+	hdmi_writeb(priv, R_4005_HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_DEASSERT);
+	udelay(1);
+	hdmi_writeb(priv, R_3000_HDMI_PHY_CONF0,
+					HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE |
+					HDMI_PHY_CONF0_SELDATAENPOL);
+	hdmi_writeb(priv, R_3000_HDMI_PHY_CONF0,
+					HDMI_PHY_CONF0_GEN2_PDDQ |
+					HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE |
+					HDMI_PHY_CONF0_SELDATAENPOL);
+	hdmi_writeb(priv, R_3000_HDMI_PHY_CONF0,
+					HDMI_PHY_CONF0_GEN2_PDDQ |
+					HDMI_PHY_CONF0_SELDATAENPOL);
+	hdmi_writeb(priv, R_3006_HDMI_PHY_MASK0, 0xf0);
+	hdmi_writeb(priv, R_3027_HDMI_PHY_I2CM_INT_ADDR, 0xff);
+	hdmi_writeb(priv, R_3028_HDMI_PHY_I2CM_CTLINT_ADDR, 0xff);
+	hdmi_writeb(priv, R_0104_HDMI_IH_PHY_STAT0, 0xff);
+	hdmi_writeb(priv, R_0108_HDMI_IH_I2CMPHY_STAT0, 0xff);
+	hdmi_writeb(priv, R_4005_HDMI_MC_PHYRSTZ, 0x00);
+	hdmi_writeb(priv, R_3000_HDMI_PHY_CONF0,
+					HDMI_PHY_CONF0_GEN2_PDDQ |
+					HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE |
+					HDMI_PHY_CONF0_SELDATAENPOL);
+	hdmi_writeb(priv, R_3000_HDMI_PHY_CONF0,
+					HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE |
+					HDMI_PHY_CONF0_SELDATAENPOL);
+	hdmi_writeb(priv, R_3001_HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR);
+	hdmi_writeb(priv, R_3020_HDMI_PHY_I2CM_SLAVE_ADDR,
+					HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
+	hdmi_writeb(priv, R_3001_HDMI_PHY_TST0, 0x00);
+}
+
+static void hdmi_phy_init_h3(struct de2_hdmi_priv *priv)
+{
+	int to_cnt;
+	u32 tmp;
+
+	hdmi_writel(priv, HDMI_PHY_CTRL_REG, 0);
+	hdmi_writel(priv, HDMI_PHY_CTRL_REG, 1 << 0);
+	udelay(5);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 1 << 16);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 1 << 1);
+	udelay(10);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 1 << 2);
+	udelay(5);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 1 << 3);
+	usleep_range(40, 50);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 1 << 19);
+	usleep_range(100, 120);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 1 << 18);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 7 << 4);
+
+	to_cnt = 10;
+	while (1) {
+		if (hdmi_readl(priv, HDMI_PHY_STATUS_REG) & 0x80)
+			break;
+		usleep_range(200, 250);
+		if (--to_cnt == 0) {
+			pr_warn("hdmi phy init timeout\n");
+			break;
+		}
+	}
+
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 0xf << 8);
+	hdmi_orl(priv, HDMI_PHY_CTRL_REG, 1 << 7);
+
+	hdmi_writel(priv, HDMI_PHY_PLL_REG, 0x39dc5040);
+	hdmi_writel(priv, HDMI_PHY_CLK_REG, 0x80084343);
+	msleep(20);
+	hdmi_writel(priv, HDMI_PHY_34_REG, 0x00000001);
+	hdmi_orl(priv, HDMI_PHY_PLL_REG, 0x02000000);
+	msleep(100);
+	tmp = hdmi_readl(priv, HDMI_PHY_STATUS_REG);
+	hdmi_orl(priv, HDMI_PHY_PLL_REG, 0xc0000000);
+	hdmi_orl(priv, HDMI_PHY_PLL_REG, (tmp >> 11) & 0x3f);
+	hdmi_writel(priv, HDMI_PHY_CTRL_REG, 0x01ff0f7f);
+	hdmi_writel(priv, HDMI_PHY_24_REG, 0x80639000);
+	hdmi_writel(priv, HDMI_PHY_28_REG, 0x0f81c405);
+
+	hdmi_inner_init(priv);
+}
+
+static void hdmi_i2cm_write(struct de2_hdmi_priv *priv,
+			    int addr, u8 valh, u8 vall)
+{
+	hdmi_writeb(priv, R_3021_HDMI_PHY_I2CM_ADDRESS_ADDR, addr);
+	hdmi_writeb(priv, R_3022_HDMI_PHY_I2CM_DATAO_1_ADDR, valh);
+	hdmi_writeb(priv, R_3023_HDMI_PHY_I2CM_DATAO_0_ADDR, vall);
+	hdmi_writeb(priv, R_3026_HDMI_PHY_I2CM_OPERATION_ADDR,
+					HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);
+	usleep_range(2000, 2500);
+}
+
+static int get_divider(int rate)
+{
+	if (rate <= 27000)
+		return 11;
+	if (rate <= 74250)
+		return 4;
+	if (rate <= 148500)
+		return 2;
+	return 1;
+}
+
+static void hdmi_phy_set_a83t(struct de2_hdmi_priv *priv,
+				struct drm_display_mode *mode)
+{
+	switch (get_divider(mode->clock)) {
+	case 1:
+		hdmi_i2cm_write(priv, 0x06, 0x00, 0x00);
+		hdmi_i2cm_write(priv, 0x15, 0x00, 0x0f);
+		hdmi_i2cm_write(priv, 0x10, 0x00, 0x00);
+		hdmi_i2cm_write(priv, 0x19, 0x00, 0x02);
+		hdmi_i2cm_write(priv, 0x0e, 0x00, 0x00);
+		hdmi_i2cm_write(priv, 0x09, 0x80, 0x2b);
+		break;
+	case 2:				/* 1080P @ 60 & 50 */
+		hdmi_i2cm_write(priv, 0x06, 0x04, 0xa0);
+		hdmi_i2cm_write(priv, 0x15, 0x00, 0x0a);
+		hdmi_i2cm_write(priv, 0x10, 0x00, 0x00);
+		hdmi_i2cm_write(priv, 0x19, 0x00, 0x02);
+		hdmi_i2cm_write(priv, 0x0e, 0x00, 0x21);
+		hdmi_i2cm_write(priv, 0x09, 0x80, 0x29);
+		break;
+	case 4:				/* 720P @ 50 & 60, 1080I, 1080P */
+		hdmi_i2cm_write(priv, 0x06, 0x05, 0x40);
+		hdmi_i2cm_write(priv, 0x15, 0x00, 0x05);
+		hdmi_i2cm_write(priv, 0x10, 0x00, 0x00);
+		hdmi_i2cm_write(priv, 0x19, 0x00, 0x07);
+		hdmi_i2cm_write(priv, 0x0e, 0x02, 0xb5);
+		hdmi_i2cm_write(priv, 0x09, 0x80, 0x09);
+		break;
+/*	case 11:			* 480P/576P */
+	default:
+		hdmi_i2cm_write(priv, 0x06, 0x01,
+			mode->flags & DRM_MODE_FLAG_DBLCLK ? 0xe3 : 0xe0);
+		hdmi_i2cm_write(priv, 0x15, 0x00, 0x00);
+		hdmi_i2cm_write(priv, 0x10, 0x08, 0xda);
+		hdmi_i2cm_write(priv, 0x19, 0x00, 0x07);
+		hdmi_i2cm_write(priv, 0x0e, 0x03, 0x18);
+		hdmi_i2cm_write(priv, 0x09, 0x80, 0x09);
+		break;
+	}
+	hdmi_i2cm_write(priv, 0x1e, 0x00, 0x00);
+	hdmi_i2cm_write(priv, 0x13, 0x00, 0x00);
+	hdmi_i2cm_write(priv, 0x17, 0x00, 0x00);
+	hdmi_writeb(priv, R_3000_HDMI_PHY_CONF0,
+					HDMI_PHY_CONF0_GEN2_TXPWRON |
+					HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE |
+					HDMI_PHY_CONF0_SELDATAENPOL);
+}
+
+static void hdmi_phy_set_h3(struct de2_hdmi_priv *priv,
+			struct drm_display_mode *mode)
+{
+	u32 tmp;
+
+	hdmi_andl(priv, HDMI_PHY_CTRL_REG, ~0xf000);
+
+	switch (get_divider(mode->clock)) {
+	case 1:
+		hdmi_writel(priv, HDMI_PHY_PLL_REG, 0x31dc5fc0);
+		hdmi_writel(priv, HDMI_PHY_CLK_REG, 0x800863c0);
+		msleep(20);
+		hdmi_writel(priv, HDMI_PHY_34_REG, 0x00000001);
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0x02000000);
+		msleep(200);
+		tmp = (hdmi_readl(priv, HDMI_PHY_STATUS_REG) >> 11) & 0x3f;
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0xc0000000);
+		if (tmp < 0x3d)
+			tmp += 2;
+		else
+			tmp = 0x3f;
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, tmp);
+		msleep(100);
+		hdmi_writel(priv, HDMI_PHY_CTRL_REG, 0x01ffff7f);
+		hdmi_writel(priv, HDMI_PHY_24_REG, 0x8063b000);
+		hdmi_writel(priv, HDMI_PHY_28_REG, 0x0f8246b5);
+		break;
+	case 2:				/* 1080P @ 60 & 50 */
+		hdmi_writel(priv, HDMI_PHY_PLL_REG, 0x39dc5040);
+		hdmi_writel(priv, HDMI_PHY_CLK_REG, 0x80084381);
+		msleep(20);
+		hdmi_writel(priv, HDMI_PHY_34_REG, 0x00000001);
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0x02000000);
+		msleep(100);
+		tmp = (hdmi_readl(priv, HDMI_PHY_STATUS_REG) >> 11) & 0x3f;
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0xc0000000);
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, tmp);
+		hdmi_writel(priv, HDMI_PHY_CTRL_REG, 0x01ffff7f);
+		hdmi_writel(priv, HDMI_PHY_24_REG, 0x8063a800);
+		hdmi_writel(priv, HDMI_PHY_28_REG, 0x0f81c485);
+		break;
+	case 4:				/* 720P @ 50 & 60, 1080I, 1080P */
+		hdmi_writel(priv, HDMI_PHY_PLL_REG, 0x39dc5040);
+		hdmi_writel(priv, HDMI_PHY_CLK_REG, 0x80084343);
+		msleep(20);
+		hdmi_writel(priv, HDMI_PHY_34_REG, 0x00000001);
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0x02000000);
+		msleep(100);
+		tmp = (hdmi_readl(priv, HDMI_PHY_STATUS_REG) >> 11) & 0x3f;
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0xc0000000);
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, tmp);
+		hdmi_writel(priv, HDMI_PHY_CTRL_REG, 0x01ffff7f);
+		hdmi_writel(priv, HDMI_PHY_24_REG, 0x8063b000);
+		hdmi_writel(priv, HDMI_PHY_28_REG, 0x0f81c405);
+		break;
+	default:
+/*	case 11:				* 480P/576P */
+		hdmi_writel(priv, HDMI_PHY_PLL_REG, 0x39dc5040);
+		hdmi_writel(priv, HDMI_PHY_CLK_REG, 0x8008430a);
+		msleep(20);
+		hdmi_writel(priv, HDMI_PHY_34_REG, 0x00000001);
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0x02000000);
+		msleep(100);
+		tmp = (hdmi_readl(priv, HDMI_PHY_STATUS_REG) >> 11) & 0x3f;
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, 0xc0000000);
+		hdmi_orl(priv, HDMI_PHY_PLL_REG, tmp);
+		hdmi_writel(priv, HDMI_PHY_CTRL_REG, 0x01ffff7f);
+		hdmi_writel(priv, HDMI_PHY_24_REG, 0x8063b000);
+		hdmi_writel(priv, HDMI_PHY_28_REG, 0x0f81c405);
+		break;
+	}
+}
+
+/* HDMI functions */
+
+void hdmi_io_init(struct de2_hdmi_priv *priv)
+{
+	if (priv->soc_type == SOC_H3)
+		hdmi_phy_init_h3(priv);
+	else
+		hdmi_phy_init_a83t(priv);
+
+	/* hpd reset */
+	hdmi_writeb(priv, R_5001_HDMI_A_HDCPCFG1,
+					HDMI_A_HDCPCFG1_PH2UPSHFTENC);
+	hdmi_writeb(priv, R_4001_HDMI_MC_CLKDIS,
+					HDMI_MC_CLKDIS_HDCPCLK_DISABLE);
+}
+
+void hdmi_io_video_on(struct de2_hdmi_priv *priv)
+{
+	if (priv->soc_type == SOC_H3)
+		hdmi_orl(priv, HDMI_PHY_CTRL_REG, 0x0f << 12);
+}
+
+void hdmi_io_video_off(struct de2_hdmi_priv *priv)
+{
+	if (priv->soc_type == SOC_H3)
+		hdmi_andl(priv, HDMI_PHY_CTRL_REG, ~(0x0f << 12));
+}
+
+/* video init */
+int hdmi_io_video_mode(struct de2_hdmi_priv *priv,
+			struct drm_display_mode *mode)
+{
+	int avi_d2;			/* AVI InfoFrame Data Byte 2 */
+	int h_blank, v_blank, h_sync_w, h_front_p;
+	int invidconf;
+
+	/* colorimetry and aspect ratio */
+	switch (priv->cea_mode) {
+	case VIC_720x480_60:
+	case VIC_720x480i_60:
+	case VIC_720x576_50:
+	case VIC_720x576i_50:
+		avi_d2 = (HDMI_COLORIMETRY_ITU_601 << 6) |
+			(HDMI_PICTURE_ASPECT_4_3 << 4) | 0x08;
+		break;
+	default:
+		avi_d2 = (HDMI_COLORIMETRY_ITU_709 << 6) |
+			(HDMI_PICTURE_ASPECT_16_9 << 4) | 0x08;
+		break;
+	}
+
+	h_blank = mode->htotal - mode->hdisplay;
+	v_blank = mode->vtotal - mode->vdisplay;
+	h_sync_w = mode->hsync_end - mode->hsync_start;
+	h_front_p = mode->hsync_start - mode->hdisplay;
+
+	invidconf = 0;
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+		invidconf |= 0x01;
+	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
+		invidconf |= 0x20;
+	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+		invidconf |= 0x40;
+
+	if (priv->soc_type == SOC_H3) {
+		hdmi_phy_set_h3(priv, mode);
+		hdmi_inner_init(priv);
+	} else {
+		hdmi_io_init(priv);
+	}
+
+	hdmi_writeb(priv, R_1200_HDMI_FC_DBGFORCE,
+					HDMI_FC_DBGFORCE_FORCEVIDEO);
+	hdmi_writeb(priv, R_1219_HDMI_FC_DBGTMDS0, 0x00);
+	hdmi_writeb(priv, R_1000_HDMI_FC_INVIDCONF,
+				invidconf |
+				HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH);
+	hdmi_writeb(priv, 0x10001,
+			invidconf < 0x60 ? 0x03 : 0x00);
+	hdmi_writeb(priv, R_1002_HDMI_FC_INHACTV1,
+			mode->hdisplay >> 8);
+	hdmi_writeb(priv, R_100d_HDMI_FC_VSYNCINWIDTH,
+			mode->vsync_end - mode->vsync_start);
+	hdmi_writeb(priv, R_1006_HDMI_FC_INVACTV1,
+			mode->vdisplay >> 8);
+	hdmi_writeb(priv, R_1004_HDMI_FC_INHBLANK1,
+			h_blank >> 8);
+	hdmi_writeb(priv, R_100c_HDMI_FC_VSYNCINDELAY,
+			mode->vsync_start - mode->vdisplay);
+	hdmi_writeb(priv, R_1009_HDMI_FC_HSYNCINDELAY1,
+			h_front_p >> 8);
+	hdmi_writeb(priv, R_100b_HDMI_FC_HSYNCINWIDTH1,
+			h_sync_w >> 8);
+	hdmi_writeb(priv, R_1001_HDMI_FC_INHACTV0,
+			mode->hdisplay);
+	hdmi_writeb(priv, R_1003_HDMI_FC_INHBLANK0,
+			h_blank);
+	hdmi_writeb(priv, R_1008_HDMI_FC_HSYNCINDELAY0,
+			h_front_p);
+	hdmi_writeb(priv, R_100a_HDMI_FC_HSYNCINWIDTH0,
+			h_sync_w);
+	hdmi_writeb(priv, R_1005_HDMI_FC_INVACTV0,
+			mode->vdisplay);
+	hdmi_writeb(priv, R_1007_HDMI_FC_INVBLANK,
+			v_blank);
+	hdmi_writeb(priv, R_1011_HDMI_FC_CTRLDUR, 12);
+	hdmi_writeb(priv, R_1012_HDMI_FC_EXCTRLDUR, 32);
+	hdmi_writeb(priv, R_1013_HDMI_FC_EXCTRLSPAC, 1);
+	hdmi_writeb(priv, R_1014_HDMI_FC_CH0PREAM, 0x0b);
+	hdmi_writeb(priv, R_1015_HDMI_FC_CH1PREAM, 0x16);
+	hdmi_writeb(priv, R_1016_HDMI_FC_CH2PREAM, 0x21);
+	hdmi_writeb(priv, R_10e0_HDMI_FC_PRCONF,
+			mode->flags & DRM_MODE_FLAG_DBLCLK ? 0x21 : 0x10);
+	hdmi_writeb(priv, R_0801_HDMI_VP_PR_CD,
+			mode->flags & DRM_MODE_FLAG_DBLCLK ? 0x41 : 0x40);
+	hdmi_writeb(priv, R_0802_HDMI_VP_STUFF, 0x07);
+	hdmi_writeb(priv, R_0803_HDMI_VP_REMAP, 0x00);
+	hdmi_writeb(priv, R_0804_HDMI_VP_CONF, 0x47);
+	hdmi_writeb(priv, R_0200_HDMI_TX_INVID0, 0x01);
+	hdmi_writeb(priv, R_0201_HDMI_TX_INSTUFFING, 0x07);
+	hdmi_writeb(priv, R_0202_HDMI_TX_GYDATA0, 0x00);
+	hdmi_writeb(priv, R_0203_HDMI_TX_GYDATA1, 0x00);
+	hdmi_writeb(priv, R_0204_HDMI_TX_RCRDATA0, 0x00);
+	hdmi_writeb(priv, R_0205_HDMI_TX_RCRDATA1, 0x00);
+	hdmi_writeb(priv, R_0206_HDMI_TX_BCBDATA0, 0x00);
+	hdmi_writeb(priv, R_0207_HDMI_TX_BCBDATA1, 0x00);
+
+	if (priv->connector.eld[0]) {		/* if audio/HDMI */
+		hdmi_writeb(priv, R_10b3_HDMI_FC_DATAUTO0, 0x08);
+		hdmi_writeb(priv, R_1031_HDMI_FC_VSDIEEEID2, 0x00);
+		hdmi_writeb(priv, R_1030_HDMI_FC_VSDIEEEID1,
+						HDMI_IEEE_OUI >> 8);
+		hdmi_writeb(priv, R_1029_HDMI_FC_VSDIEEEID0,
+						HDMI_IEEE_OUI & 0xff);
+		hdmi_writeb(priv, R_1032_HDMI_FC_VSDPAYLOAD0, 0x00);
+		hdmi_writeb(priv, R_1033_HDMI_FC_VSDPAYLOAD1, 0x00);
+		hdmi_writeb(priv, R_1034_HDMI_FC_VSDPAYLOAD2, 0x00);
+		hdmi_writeb(priv, R_10b4_HDMI_FC_DATAUTO1, 0x01);
+		hdmi_writeb(priv, R_10b5_HDMI_FC_DATAUTO2, 0x11);
+		hdmi_writeb(priv, R_1018_HDMI_FC_GCP, 0x00);
+		hdmi_writeb(priv, R_1104_HDMI_FC_GMD_HB, 0x00);
+		hdmi_writeb(priv, R_1103_HDMI_FC_GMD_CONF, 0x11);
+
+		hdmi_lock_read(priv);
+		hdmi_orb(priv, R_1000_HDMI_FC_INVIDCONF, 0x08);
+		hdmi_unlock_read(priv);
+
+		/* AVI */
+		hdmi_writeb(priv, R_1019_HDMI_FC_AVICONF0,
+					HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN);
+		hdmi_writeb(priv, R_101a_HDMI_FC_AVICONF1, avi_d2);
+
+		hdmi_writeb(priv, R_101b_HDMI_FC_AVICONF2, 0x08);
+		hdmi_writeb(priv, R_101c_HDMI_FC_AVIVID, priv->cea_mode);
+	}
+
+	hdmi_writeb(priv, R_4004_HDMI_MC_FLOWCTRL, 0x00);
+	hdmi_writeb(priv, R_4001_HDMI_MC_CLKDIS, 0x00);	/* enable all clocks */
+
+	if (priv->soc_type != SOC_H3)
+		hdmi_phy_set_a83t(priv, mode);
+
+	hdmi_writeb(priv, R_1200_HDMI_FC_DBGFORCE, 0x00);
+
+	return 0;
+}
+
+/* get a block of EDID */
+int hdmi_io_ddc_read(struct de2_hdmi_priv *priv,
+			char pointer, char off,
+			int nbyte, char *pbuf)
+{
+	unsigned int to_cnt;
+	u8 reg;
+	int ret = 0;
+
+	hdmi_lock_read(priv);
+	hdmi_writeb(priv, R_7e09_HDMI_I2CM_SOFTRSTZ, 0x00);
+	to_cnt = 50;
+	while (!(hdmi_readb(priv, R_7e09_HDMI_I2CM_SOFTRSTZ) & 0x01)) {
+		udelay(10);
+		if (--to_cnt == 0) {	/* wait for 500us for timeout */
+			pr_warn("hdmi ddc reset timeout\n");
+			break;
+		}
+	}
+
+	hdmi_writeb(priv, R_7e07_HDMI_I2CM_DIV, 0x05);
+	hdmi_writeb(priv, R_7e05_HDMI_I2CM_INT, 0x08);
+	hdmi_writeb(priv, R_7e0c_HDMI_I2CM_SS_SCL_HCNT_0_ADDR, 0xd8);
+	hdmi_writeb(priv, R_7e0e_HDMI_I2CM_SS_SCL_LCNT_0_ADDR, 0xfe);
+
+	while (nbyte > 0) {
+		hdmi_writeb(priv, R_7e00_HDMI_I2CM_SLAVE, 0xa0 >> 1);
+		hdmi_writeb(priv, R_7e01_HDMI_I2CM_ADDRESS, off);
+		hdmi_writeb(priv, R_7e08_HDMI_I2CM_SEGADDR, 0x60 >> 1);
+		hdmi_writeb(priv, R_7e0a_HDMI_I2CM_SEGPTR, pointer);
+		hdmi_writeb(priv, R_7e04_HDMI_I2CM_OPERATION,
+					HDMI_I2CM_OPERATION_DDC_READ);
+
+		to_cnt = 200;				/* timeout 100ms */
+		while (1) {
+			reg = hdmi_readb(priv, R_0105_HDMI_IH_I2CM_STAT0);
+			hdmi_writeb(priv, R_0105_HDMI_IH_I2CM_STAT0, reg);
+			if (reg & 0x02) {
+				*pbuf++ = hdmi_readb(priv,
+						R_7e03_HDMI_I2CM_DATAI);
+				break;
+			}
+			if (reg & 0x01) {
+				pr_warn("hdmi ddc read error\n");
+				ret = -1;
+				break;
+			}
+			if (--to_cnt == 0) {
+				if (!ret) {
+					pr_warn("hdmi ddc read timeout\n");
+					ret = -1;
+				}
+				break;
+			}
+			usleep_range(500, 800);
+		}
+		if (ret)
+			break;
+		nbyte--;
+		off++;
+	}
+	hdmi_unlock_read(priv);
+
+	return ret;
+}
+
+int hdmi_io_get_hpd(struct de2_hdmi_priv *priv)
+{
+	int ret;
+
+	hdmi_lock_read(priv);
+
+	if (priv->soc_type == SOC_H3)
+		ret = hdmi_readl(priv, HDMI_PHY_STATUS_REG) & 0x80000;
+	else
+		ret = hdmi_readb(priv, R_3005_HDMI_PHY_INT0) & 0x02;
+
+	hdmi_unlock_read(priv);
+
+	return ret != 0;
+}
+
+int hdmi_io_mode_valid(int cea_mode)
+{
+	/* check the known working resolutions */
+	switch (cea_mode) {
+	case VIC_720x480_60:
+	case VIC_1280x720_60:
+	case VIC_1920x1080i_60:
+	case VIC_720x480i_60:
+	case VIC_1920x1080_60:
+	case VIC_720x576_50:
+	case VIC_1280x720_50:
+	case VIC_1920x1080i_50:
+	case VIC_720x576i_50:
+	case VIC_1920x1080_50:
+	case VIC_1920x1080_24:
+	case VIC_1920x1080_25:
+	case VIC_1920x1080_30:
+		return 1;
+	}
+	return -1;
+}
-- 
2.10.2

^ permalink raw reply related

* [PATCH v4 0/3] dmaengine: sun6i: add the support for the Allwinner A64 SOC.
From: Hao Zhang @ 2016-11-20 10:45 UTC (permalink / raw)
  To: linux-arm-kernel

Abort Allwinner A64 SOC :
Allwinner A64 (sun50i) 64bit  SoC features a Quad-Core Cortex-A53 ARM CPU, 
and a Mali400 MP2 GPU from ARM.

It has 8 channel DMA which flexible
data width of 8/16/32/64-bit. Detailed info about it is on
Allwinner_A64_User_Manual_V1.0 page 196 and A64_Datasheet_V1.1 page 8.

Document:
A64 Datasheet v1.1: http://files.pine64.org/doc/datasheet/pine64/A64_Datasheet_V1.1.pdf
A64 User Manual v1.0: http://files.pine64.org/doc/datasheet/pine64/Allwinner_A64_User_Manual_V1.0.pdf


Abort Pine64:
The Pine64 is a cost-optimized board with SOC A64 sporting ARMv8 (64-bit ARM) capable cores.
Detail info : 
https://linux-sunxi.org/Pine64 
http://wiki.pine64.org/index.php/Main_Page


PATCH LOG:
PATCH[v3,1/3]: https://patchwork.kernel.org/patch/9415765/
PATCH[v3,2/3]: https://patchwork.kernel.org/patch/9415761/
PATCH[V3,3/3]: https://patchwork.kernel.org/patch/9415761/

Changes in v4 :

PATCH[v4,1/3]:
Since PATCH[v3,1/3] has Acked-by  Maxime Ripard and Rob Herring
this is resend it.

PATCH[v4,2/3]:
Accept the comments from Maxime Ripard and add the dma nodes by
base adress, thinks!

PATCH[V4,3/3]:
Accept the hint from Maxime Ripard, add the 8 bytes bus width for
A64 dma and add the buswidth test, thinks!


It has test on Pine64 using dmatest.


Regards :)


Hao Zhang (3):
  Documentation: DT: add dma compatible for sun50i A64 SOC
  ARM64: dts: sun6i: add dma node for a64.
  dmaengine: sun6i: share the dma driver with sun50i

 .../devicetree/bindings/dma/sun6i-dma.txt          |  1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      |  9 ++++++
 drivers/dma/sun6i-dma.c                            | 33 +++++++++++++++++++++-
 3 files changed, 42 insertions(+), 1 deletion(-)

-- 
2.7.4

^ permalink raw reply

* [PATCH v4 1/3] Documentation: DT: add dma compatible for sun50i A64 SOC
From: Hao Zhang @ 2016-11-20 10:45 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1479638740-20520-1-git-send-email-hao5781286@gmail.com>

This add the property of Allwinner sun50i A64 dma.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
index 6b26704..4398b99 100644
--- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
+++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
@@ -9,6 +9,7 @@ Required properties:
 		  "allwinner,sun8i-a23-dma"
 		  "allwinner,sun8i-a83t-dma"
 		  "allwinner,sun8i-h3-dma"
+		  "allwinner,sun50i-a64-dma"
 - reg:		Should contain the registers base address and length
 - interrupts:	Should contain a reference to the interrupt used by this device
 - clocks:	Should contain a reference to the parent AHB clock
-- 
2.7.4

^ permalink raw reply related

* [PATCH v4 2/3] ARM64: dts: sun6i: add dma node for a64.
From: Hao Zhang @ 2016-11-20 10:45 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1479638740-20520-1-git-send-email-hao5781286@gmail.com>

Accroding to the Allwinner_A64_User_Manual_V1.0 P198
the DMA base address is 0x01c02000.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index e3c3d7d8..403bbfa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -122,6 +122,15 @@
 		#size-cells = <1>;
 		ranges;
 
+		dma: dma-controller at 1c02000 {
+			compatible = "allwinner,sun50i-a64-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_DMA>;
+			resets = <&ccu RST_BUS_DMA>;
+			#dma-cells = <1>;
+		};
+
 		ccu: clock at 01c20000 {
 			compatible = "allwinner,sun50i-a64-ccu";
 			reg = <0x01c20000 0x400>;
-- 
2.7.4

^ permalink raw reply related

* [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i
From: Hao Zhang @ 2016-11-20 10:45 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1479638740-20520-1-git-send-email-hao5781286@gmail.com>

Changes the limited buswith to 8 bytes,and add
the test in sun6i_dma_config function

Accroding to sun6i dma driver, i think ,if the client
doesn't configure the address width with dmaengine_slave_config
function, it would use the default width. So we can add the test
in sun6i_dma_config function called by dmaengine_slave_config,
and test the configuration whether is support for the device.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index a235878..f7c90b6 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
 {
 	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
-	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
+	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
 		return -EINVAL;
 
 	return addr_width >> 1;
@@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
 {
 	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 
+	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
+		chan->device->src_addr_widths) {
+		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
+		return -EINVAL;
+	}
+
+	if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
+			chan->device->dst_addr_widths) {
+		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
+		return -EINVAL;
+	}
+
 	memcpy(&vchan->cfg, config, sizeof(*config));
 
 	return 0;
@@ -1028,11 +1040,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
 	.nr_max_vchans   = 34,
 };
 
+/*
+ * The A64 has 8 physical channels, a maximum DRQ port id of 27,
+ * and a total of 38 usable source and destination endpoints.
+ */
+
+static struct sun6i_dma_config sun50i_a64_dma_cfg = {
+	.nr_max_channels = 8,
+	.nr_max_requests = 27,
+	.nr_max_vchans   = 38,
+};
+
 static const struct of_device_id sun6i_dma_match[] = {
 	{ .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
 	{ .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
 	{ .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
 	{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
+	{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
@@ -1112,6 +1136,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)
 						  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 	sdc->slave.directions			= BIT(DMA_DEV_TO_MEM) |
 						  BIT(DMA_MEM_TO_DEV);
+
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "allwinner,sun50i-a64-dma")) {
+		sdc->slave.src_addr_widths	|= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+		sdc->slave.dst_addr_widths	|= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+	}
+
 	sdc->slave.residue_granularity		= DMA_RESIDUE_GRANULARITY_BURST;
 	sdc->slave.dev = &pdev->dev;
 
-- 
2.7.4

^ permalink raw reply related

* [PATCH v6 3/5] ARM: dts: sun8i-h3: add HDMI video nodes
From: Jean-Francois Moine @ 2016-11-20 11:20 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1479641523.git.moinejf@free.fr>

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 416b825..7c6b1d5 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -140,6 +140,16 @@
 		#size-cells = <1>;
 		ranges;
 
+		de: de-controller at 01000000 {
+			compatible = "allwinner,sun8i-h3-display-engine";
+			reg = <0x01000000 0x400000>;
+			clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
+			clock-names = "bus", "clock";
+			resets = <&ccu RST_BUS_DE>;
+			ports = <&lcd0_p>;
+			status = "disabled";
+		};
+
 		dma: dma-controller at 01c02000 {
 			compatible = "allwinner,sun8i-h3-dma";
 			reg = <0x01c02000 0x1000>;
@@ -149,6 +159,23 @@
 			#dma-cells = <1>;
 		};
 
+		lcd0: lcd-controller at 01c0c000 {
+			compatible = "allwinner,sun8i-a83t-tcon";
+			reg = <0x01c0c000 0x400>;
+			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
+			clock-names = "bus", "clock";
+			resets = <&ccu RST_BUS_TCON0>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			lcd0_p: port {
+				lcd0_hdmi: endpoint {
+					remote-endpoint = <&hdmi_lcd0>;
+				};
+			};
+		};
+
 		mmc0: mmc at 01c0f000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
@@ -314,6 +341,11 @@
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+
+			assigned-clocks = <&ccu CLK_PLL_DE>,
+					  <&ccu CLK_DE>;
+			assigned-clock-rates =  <864000000>,
+						<432000000>;
 		};
 
 		pio: pinctrl at 01c20800 {
@@ -564,6 +596,25 @@
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		hdmi: hdmi at 01ee0000 {
+			compatible = "allwinner,sun8i-h3-hdmi";
+			reg = <0x01ee0000 0x20000>;
+			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,
+				 <&ccu CLK_HDMI_DDC>;
+			clock-names = "bus", "clock", "ddc-clock";
+			resets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;
+			reset-names = "hdmi0", "hdmi1";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port at 0 {			/* video */
+				reg = <0>;
+				hdmi_lcd0: endpoint {
+					remote-endpoint = <&lcd0_hdmi>;
+				};
+			};
+		};
+
 		rtc: rtc at 01f00000 {
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
-- 
2.10.2

^ permalink raw reply related

* [PATCH v6 4/5] ARM: dts: sun8i-h3: Add HDMI video to the Banana Pi M2+
From: Jean-Francois Moine @ 2016-11-20 11:23 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1479641523.git.moinejf@free.fr>

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index c0c49dd..4b5baae 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -55,6 +55,7 @@
 	aliases {
 		serial0 = &uart0;
 		serial1 = &uart1;
+		lcd0 = &lcd0;
 	};
 
 	chosen {
@@ -93,6 +94,10 @@
 	};
 };
 
+&de {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -101,12 +106,20 @@
 	status = "okay";
 };
 
+&hdmi {
+	status = "okay";
+};
+
 &ir {
 	pinctrl-names = "default";
 	pinctrl-0 = <&ir_pins_a>;
 	status = "okay";
 };
 
+&lcd0 {
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
-- 
2.10.2

^ permalink raw reply related

* [PATCH v6 5/5] ARM: dts: sun8i-h3: Add HDMI video to the Orange PI 2
From: Jean-Francois Moine @ 2016-11-20 11:26 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1479641523.git.moinejf@free.fr>

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 047e9e1..9ecc6f1 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -56,6 +56,7 @@
 		serial0 = &uart0;
 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
 		ethernet1 = &rtl8189;
+		lcd0 = &lcd0;
 	};
 
 	chosen {
@@ -105,16 +106,28 @@
 	};
 };
 
+&de {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
 
+&hdmi {
+	status = "okay";
+};
+
 &ir {
 	pinctrl-names = "default";
 	pinctrl-0 = <&ir_pins_a>;
 	status = "okay";
 };
 
+&lcd0 {
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
-- 
2.10.2

^ permalink raw reply related

* [PATCH] ARM: davinci: PM: fix build when da850 not compiled in
From: Sekhar Nori @ 2016-11-20 11:29 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161116164438.9881-1-khilman@baylibre.com>

On Wednesday 16 November 2016 10:14 PM, Kevin Hilman wrote:
> Currently, suspend/resume support is only available on da850 platforms,
> and the platform PM code has dependencies on da850 functions.  However,
> CONFIG_SUSPEND might be enabled even when da850 support is not, causing
> build failure:
> 
> arch/arm/mach-davinci/built-in.o: In function `davinci_pm_init':
> pm_domain.c:(.init.text+0x1fb8): undefined reference to `da8xx_get_mem_ctlr'
> pm_domain.c:(.init.text+0x20b0): undefined reference to `da8xx_syscfg1_base'
> 
> Fix this by only building the PM core when da850 is enabled.
> 
> Reported-by: Sekhar Nori <nsekhar@ti.com>
> Fixes: aa9aa1ec2df6 ARM: davinci: PM: rework init, remove platform device
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Applied. Documentation asks for ("") around commit headline in Fixes:
tag, so I added that.

Thanks
Sekhar

^ permalink raw reply

* commit 4dd1837d7589f468ed109556513f476e7a7f9121 breaks build
From: Russell King - ARM Linux @ 2016-11-20 11:30 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <58310EC6.4020402@math.uni-bielefeld.de>

None of the autobuilders are finding this problem, and they build a
wide range of configurations.  Maybe it's something specific to how
you're building the kernel - can you give step by step instructions
how to reproduce this please?

On Sun, Nov 20, 2016 at 03:47:34AM +0100, Tobias Jakobi wrote:
> Hello,
> 
> this is a resend of my initial mail, see below, to Al Viro (which sadly
> was ignored).
> 
> It's rc5 now, and this issue still remains. Putting some more lists on
> the Cc now.
> 
> Reverting the commit still works for me.
> 
> 
> With best wishes,
> Tobias
> 
> ----------------
> 
> 
> Hello Al,
> 
> compiled a kernel on armv7 with torvalds/master today and getting some
> errors during the modpost phase.
> 
> > ERROR: "_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> > ERROR: "_test_and_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> > ERROR: "_clear_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> > ERROR: "_test_and_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_test_and_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_test_and_clear_bit" [sound/core/seq/snd-seq.ko] undefined!
> <snip>
> 
> It seems like the commit 'arm: move exports to definitions' introduces
> this issue.
> 
> I quickly went over the commit and I noticed that while it removes the
> EXPORT_SYMBOL()s for the bitops from armksyms.c, it doesn't move them
> anywhere.
> 
> Maybe you can take a look at this?
> 
> With best wishes,
> Tobias
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply

* [PATCH v6 0/5] drm: sun8i: Add DE2 HDMI video support
From: Jean-Francois Moine @ 2016-11-20 11:32 UTC (permalink / raw)
  To: linux-arm-kernel

This patchset series adds HDMI video support to the Allwinner
sun8i SoCs which include the display engine 2 (DE2).
The driver contains the code for the A83T and H3, but it could be
used/extended for other SoCs as the A64, H2 and H5.

v6:
	- remove audio support (other patchset to come)
	- use DRM modeset data for HDMI configuration
		(thanks to Jernej ??krabec)
	- more meaningfull register names
	- use a mutex for DE I/O protection
	- merge DE and plane into one file
	- don't activate the video hardware when video not started
		(Maxime Ripard)
	- remove 'type = "video" in DT graph ports
		(Rob Herring)
	- change the I/O accesses by #define instead of struct
		(Maxime Ripard, Andr?? Przywara)
	- remove pm functions (Maxime Ripard)
	- set the pll-de/de clocks in the DT (Maxime Ripard)
	- use platform_get_irq instead of irq_of_parse_and_map
		(Maxime Ripard)
	- rename sunxi to sun8i (Maxime Ripard)
	- fix coding style errors (Maxime Ripard)
	- subclass the drm structure in private data (Daniel Vetter)
	- move drm_dev_register at end of init (Daniel Vetter)
v5:
	- add overlay plane
	- add audio support
	- add support for the A83T
	- add back the HDMI driver
	- many bug fixes
v4: 
	- drivers/clk/sunxi/Makefile was missing (Emil Velikov)
v3:
	- add the hardware cursor
	- simplify and fix the DE2 init sequences
	- generation for all SUNXI SoCs (Andre Przywara)
v2:
	- remove the HDMI driver
	- remarks from Chen-Yu Tsai and Russell King
	- DT documentation added

Jean-Francois Moine (5):
  drm: sun8i: Add a basic DRM driver for Allwinner DE2
  drm: sunxi: add HDMI video support to A83T and H3
  ARM: dts: sun8i-h3: add HDMI video nodes
  ARM: dts: sun8i-h3: Add HDMI video to the Banana Pi M2+
  ARM: dts: sun8i-h3: Add HDMI video to the Orange PI 2

 .../devicetree/bindings/display/sunxi/hdmi.txt     |  53 ++
 .../bindings/display/sunxi/sun8i-de2.txt           |  83 ++
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts    |  13 +
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts          |  13 +
 arch/arm/boot/dts/sun8i-h3.dtsi                    |  51 ++
 drivers/gpu/drm/Kconfig                            |   2 +
 drivers/gpu/drm/Makefile                           |   1 +
 drivers/gpu/drm/sun8i/Kconfig                      |  26 +
 drivers/gpu/drm/sun8i/Makefile                     |   9 +
 drivers/gpu/drm/sun8i/de2_crtc.c                   | 440 +++++++++++
 drivers/gpu/drm/sun8i/de2_crtc.h                   |  50 ++
 drivers/gpu/drm/sun8i/de2_drm.h                    |  48 ++
 drivers/gpu/drm/sun8i/de2_drv.c                    | 379 ++++++++++
 drivers/gpu/drm/sun8i/de2_hdmi.c                   | 394 ++++++++++
 drivers/gpu/drm/sun8i/de2_hdmi.h                   |  51 ++
 drivers/gpu/drm/sun8i/de2_hdmi_io.c                | 839 +++++++++++++++++++++
 drivers/gpu/drm/sun8i/de2_plane.c                  | 712 +++++++++++++++++
 17 files changed, 3164 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
 create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
 create mode 100644 drivers/gpu/drm/sun8i/Kconfig
 create mode 100644 drivers/gpu/drm/sun8i/Makefile
 create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_drm.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_drv.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi_io.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_plane.c

-- 
2.10.2

^ permalink raw reply

* [RFC 2/6] drm/etnaviv: allow building etnaviv on omap devices
From: Russell King - ARM Linux @ 2016-11-20 11:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <2481825.ONQ5ft592J@diplodocus>

On Sat, Nov 19, 2016 at 03:58:15AM -0800, Joshua Clayton wrote:
> On Friday, November 18, 2016 10:33:42 AM Rob Herring wrote:
> > On Thu, Nov 17, 2016 at 08:44:32PM -0600, Robert Nelson wrote:
> > > Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
> > > CC: Christian Gmeiner <christian.gmeiner@gmail.com>
> > > CC: Russell King <rmk+kernel@arm.linux.org.uk>
> > > CC: Lucas Stach <l.stach@pengutronix.de>
> > > ---
> > >  drivers/gpu/drm/etnaviv/Kconfig | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig
> > > index 2cde7a5..b776f41 100644
> > > --- a/drivers/gpu/drm/etnaviv/Kconfig
> > > +++ b/drivers/gpu/drm/etnaviv/Kconfig
> > > @@ -2,7 +2,7 @@
> > >  config DRM_ETNAVIV
> > >  	tristate "ETNAVIV (DRM support for Vivante GPU IP cores)"
> > >  	depends on DRM
> > > -	depends on ARCH_MXC || ARCH_DOVE
> > > +	depends on ARCH_MXC || ARCH_DOVE || ARCH_OMAP2PLUS
> > 
> > Why not just drop this line. Then it will get better build testing, too.
> > 
> > >  	select SHMEM
> > >  	select TMPFS
> > >  	select IOMMU_API
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> ...building with ARCH=x86_64
>             ^
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c: In function ?etnaviv_gpu_init?:
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c:633:18: error: ?PHYS_OFFSET? undeclared (first use in this function)
>    if (dma_mask < PHYS_OFFSET + SZ_2G)
>                   ^
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c:633:18: note: each undeclared identifier is reported only once for each function it appears in

... and that's why we don't drop the dependency, although changing it
to "depends on ARM" will open it up to wider build testing on other
ARM platforms, I don't think that gains very much.

The issue is that the command buffers must be located within the first
2GB of GPU virtual address space, and that space can only be translated
(offset).  What the code here is trying to do is to locate the 2GB of
virtual address space such that it overlaps the CMA region if RAM is
bigger than 2GB, or covers all of the RAM if not.

For that, we need to know where physical RAM starts.

I guess we could replace PHYS_OFFSET with virt_to_phys(PAGE_OFFSET)
here instead, which would be more arch-portable - although that would
be assuming there's no (system?) IOMMU between memory and the GPU.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply

* commit 4dd1837d7589f468ed109556513f476e7a7f9121 breaks build
From: Tobias Jakobi @ 2016-11-20 11:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161120113007.GS1041@n2100.armlinux.org.uk>

Hello Russell,


Russell King - ARM Linux wrote:
> None of the autobuilders are finding this problem, and they build a
> wide range of configurations.  Maybe it's something specific to how
> you're building the kernel - can you give step by step instructions
> how to reproduce this please?
Just using plain make here, no cross-compiler or anything involved. gcc
is version 4.9.4.

Build platform is a Exynos4412 based ODROID-X2.


The complete log from the 'build modules' step:
>   Building modules, stage 2.
>   Kernel: arch/arm/boot/Image is ready
>   MODPOST 52 modules
>   XZKERN  arch/arm/boot/compressed/piggy_data
>   SHIPPED arch/arm/boot/compressed/lib1funcs.S
>   SHIPPED arch/arm/boot/compressed/ashldi3.S
>   SHIPPED arch/arm/boot/compressed/bswapsdi2.S
>   AS      arch/arm/boot/compressed/lib1funcs.o
>   AS      arch/arm/boot/compressed/ashldi3.o
>   AS      arch/arm/boot/compressed/bswapsdi2.o
> ERROR: "_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> ERROR: "_test_and_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> ERROR: "_clear_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> ERROR: "_test_and_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> ERROR: "_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> ERROR: "_test_and_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> ERROR: "_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> ERROR: "_test_and_clear_bit" [sound/core/seq/snd-seq.ko] undefined!
> ERROR: "_test_and_set_bit" [sound/core/seq/snd-seq.ko] undefined!
> ERROR: "_set_bit" [net/bridge/bridge.ko] undefined!
> ERROR: "_clear_bit" [net/bridge/bridge.ko] undefined!
> ERROR: "_test_and_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> ERROR: "_set_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> ERROR: "_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> ERROR: "_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> ERROR: "_test_and_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> ERROR: "_clear_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> ERROR: "_test_and_clear_bit" [fs/fuse/fuse.ko] undefined!
> ERROR: "_set_bit" [fs/fuse/fuse.ko] undefined!
> ERROR: "_test_and_set_bit" [fs/fuse/fuse.ko] undefined!
> ERROR: "_clear_bit" [fs/fuse/fuse.ko] undefined!
> ERROR: "_test_and_clear_bit" [fs/cifs/cifs.ko] undefined!
> ERROR: "_set_bit" [fs/cifs/cifs.ko] undefined!
> ERROR: "_test_and_set_bit" [fs/cifs/cifs.ko] undefined!
> ERROR: "_clear_bit" [fs/cifs/cifs.ko] undefined!
> ERROR: "_test_and_clear_bit" [fs/btrfs/btrfs.ko] undefined!
> ERROR: "_set_bit" [fs/btrfs/btrfs.ko] undefined!
> ERROR: "_test_and_set_bit" [fs/btrfs/btrfs.ko] undefined!
> ERROR: "_clear_bit" [fs/btrfs/btrfs.ko] undefined!
> ERROR: "_test_and_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> ERROR: "_set_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> ERROR: "_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> ERROR: "_set_bit" [drivers/usb/gadget/libcomposite.ko] undefined!
> ERROR: "_set_bit" [drivers/usb/gadget/function/usb_f_rndis.ko] undefined!
> ERROR: "_test_and_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> ERROR: "_test_and_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> ERROR: "_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> ERROR: "_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> ERROR: "_test_and_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> ERROR: "_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> ERROR: "_test_and_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> ERROR: "_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> ERROR: "_clear_bit" [drivers/md/dm-crypt.ko] undefined!
> ERROR: "_set_bit" [drivers/md/dm-crypt.ko] undefined!
> ERROR: "_set_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
> ERROR: "_clear_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
> ERROR: "_test_and_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
> ERROR: "_test_and_set_bit" [drivers/bluetooth/btusb.ko] undefined!
> ERROR: "_set_bit" [drivers/bluetooth/btusb.ko] undefined!
> ERROR: "_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
> ERROR: "_set_bit" [drivers/bluetooth/btintel.ko] undefined!
> ERROR: "_set_bit" [drivers/bluetooth/btbcm.ko] undefined!
> scripts/Makefile.modpost:91: recipe for target '__modpost' failed
> make[1]: *** [__modpost] Error 1
> Makefile:1191: recipe for target 'modules' failed
> make: *** [modules] Error 2


This is the config I'm using for the build:
https://github.com/tobiasjakobi/odroid-environment/blob/master/sourcecode/system/vanilla-4.9-debug.conf


Let me know which additional information you need.

With best wishes,
Tobias


> On Sun, Nov 20, 2016 at 03:47:34AM +0100, Tobias Jakobi wrote:
>> Hello,
>>
>> this is a resend of my initial mail, see below, to Al Viro (which sadly
>> was ignored).
>>
>> It's rc5 now, and this issue still remains. Putting some more lists on
>> the Cc now.
>>
>> Reverting the commit still works for me.
>>
>>
>> With best wishes,
>> Tobias
>>
>> ----------------
>>
>>
>> Hello Al,
>>
>> compiled a kernel on armv7 with torvalds/master today and getting some
>> errors during the modpost phase.
>>
>>> ERROR: "_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
>>> ERROR: "_test_and_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
>>> ERROR: "_clear_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_test_and_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [sound/core/seq/snd-seq.ko] undefined!
>> <snip>
>>
>> It seems like the commit 'arm: move exports to definitions' introduces
>> this issue.
>>
>> I quickly went over the commit and I noticed that while it removes the
>> EXPORT_SYMBOL()s for the bitops from armksyms.c, it doesn't move them
>> anywhere.
>>
>> Maybe you can take a look at this?
>>
>> With best wishes,
>> Tobias
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

^ permalink raw reply

* [PATCH v4] crypto: arm64/sha2: integrate OpenSSL implementations of SHA256/SHA512
From: Ard Biesheuvel @ 2016-11-20 11:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1479642121-17912-1-git-send-email-ard.biesheuvel@linaro.org>

On 20 November 2016 at 11:42, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> This integrates both the accelerated scalar and the NEON implementations
> of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.
>
> Relative performance compared to the respective generic C versions:
>
>                  |  SHA256-scalar  | SHA256-NEON* |  SHA512  |
>      ------------+-----------------+--------------+----------+
>      Cortex-A53  |      1.63x      |     1.63x    |   2.34x  |
>      Cortex-A57  |      1.43x      |     1.59x    |   1.95x  |
>      Cortex-A73  |      1.26x      |     1.56x    |     ?    |
>
> The core crypto code was authored by Andy Polyakov of the OpenSSL
> project, in collaboration with whom the upstream code was adapted so
> that this module can be built from the same version of sha512-armv8.pl.
>
> The version in this patch was taken from OpenSSL commit 32bbb62ea634
> ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")
>
> * The core SHA algorithm is fundamentally sequential, but there is a
>   secondary transformation involved, called the schedule update, which
>   can be performed independently. The NEON version of SHA-224/SHA-256
>   only implements this part of the algorithm using NEON instructions,
>   the sequential part is always done using scalar instructions.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---

Missing changelog:

v4: fixed the big-endian build; this required an upstream change (even
    though upstream was not actually broken, since it explicitly defines
    __ARMEB__ on AArch64 big-endian builds), so this patch is now based
    on a more recent upstream OpenSSL commit (the __ILP32__ #ifdefs are
    still present but never active)

v3: at Will's request, the generated assembly files are now included
    as .S_shipped files, for which generic build rules are defined
    already.

Note that sizeable patches like this one have caused issues in the past with
patchwork, so for Herbert's convenience, the patch can be pulled from
http://git.kernel.org/cgit/linux/kernel/git/ardb/linux.git, branch
arm64-sha256 (based on today's cryptodev)

^ permalink raw reply

* mmc: core: complete/wait_for_completion performance
From: Jörg Krause @ 2016-11-20 12:27 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

I started the discussion on this mailing list in another thread [1],
but I'd like to move it to a new thread, because it might be mmc
specific.

The issue is that I am noticed low wifi network throughput on an i.MX28
board with the mainline kernel (v4.7.10, about 6 Mbps) compared to the
vendor kernel (Freescale v2.6.35.3, about 20 Mbps). The wifi chip is
attached using the SDIO interface.

I started investigation where the bottleneck in the mainline
kernel?might come from. Therefore I checked that the configs and
settings for the interfaces and drivers are the same. They are.

For comparing both kernel version I measured the latency for the
different parts in the code flow by adding some GPIOs to toggle and
useing an osci.

It turns out, that the time needed do pass a mmc request from the wifi
driver to the dma and waiting for the response of the dma is almost the
same for both kernel versions. So the path from the wifi driver to the
dma driver is not the issue.

However, the major difference was the time needed to signal the
completion of the request back to the mmc core driver.

For mainline, the time elapsed?from calling complete() in
mmc_wait_done() [2] in the mmc core driver until actually receiving the
completion signal in mmc_wait_for_req_done() [3] is about 120 us. 

Whereas, for the vendor kernel,?the elapsed time for this notifcation
is about 100 us less!

I wonder why the notification takes so much longer in the mainline
kernel than in the vendor kernel? Where should I start looking at to
eliminate this bottleneck? Is it a scheduling issue?

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-October/
461137.html
[2] http://lxr.free-electrons.com/source/drivers/mmc/core/core.c#L386
[3] http://lxr.free-electrons.com/source/drivers/mmc/core/core.c#L492

Best regards,
J?rg Krause

^ permalink raw reply

* commit 4dd1837d7589f468ed109556513f476e7a7f9121 breaks build
From: Russell King - ARM Linux @ 2016-11-20 12:34 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <58318C6A.50104@math.uni-bielefeld.de>

On Sun, Nov 20, 2016 at 12:43:38PM +0100, Tobias Jakobi wrote:
> Hello Russell,
> 
> Russell King - ARM Linux wrote:
> > None of the autobuilders are finding this problem, and they build a
> > wide range of configurations.  Maybe it's something specific to how
> > you're building the kernel - can you give step by step instructions
> > how to reproduce this please?
> Just using plain make here, no cross-compiler or anything involved. gcc
> is version 4.9.4.

Hmm.  The commit you mention was merged during the merge window, so
anyone building 4.9-rc1 or later should be seeing this problem, but
they aren't.  I've built many kernels post -rc1, and I'm not seeing
the problem with my 4.7.4 cross compiler.

> Build platform is a Exynos4412 based ODROID-X2.
> 
> 
> The complete log from the 'build modules' step:
> >   Building modules, stage 2.
> >   Kernel: arch/arm/boot/Image is ready
> >   MODPOST 52 modules
> >   XZKERN  arch/arm/boot/compressed/piggy_data
> >   SHIPPED arch/arm/boot/compressed/lib1funcs.S
> >   SHIPPED arch/arm/boot/compressed/ashldi3.S
> >   SHIPPED arch/arm/boot/compressed/bswapsdi2.S
> >   AS      arch/arm/boot/compressed/lib1funcs.o
> >   AS      arch/arm/boot/compressed/ashldi3.o
> >   AS      arch/arm/boot/compressed/bswapsdi2.o
> > ERROR: "_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> > ERROR: "_test_and_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> > ERROR: "_clear_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> > ERROR: "_test_and_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_test_and_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> > ERROR: "_test_and_clear_bit" [sound/core/seq/snd-seq.ko] undefined!
> > ERROR: "_test_and_set_bit" [sound/core/seq/snd-seq.ko] undefined!
> > ERROR: "_set_bit" [net/bridge/bridge.ko] undefined!
> > ERROR: "_clear_bit" [net/bridge/bridge.ko] undefined!
> > ERROR: "_test_and_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> > ERROR: "_set_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> > ERROR: "_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> > ERROR: "_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> > ERROR: "_test_and_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> > ERROR: "_clear_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> > ERROR: "_test_and_clear_bit" [fs/fuse/fuse.ko] undefined!
> > ERROR: "_set_bit" [fs/fuse/fuse.ko] undefined!
> > ERROR: "_test_and_set_bit" [fs/fuse/fuse.ko] undefined!
> > ERROR: "_clear_bit" [fs/fuse/fuse.ko] undefined!
> > ERROR: "_test_and_clear_bit" [fs/cifs/cifs.ko] undefined!
> > ERROR: "_set_bit" [fs/cifs/cifs.ko] undefined!
> > ERROR: "_test_and_set_bit" [fs/cifs/cifs.ko] undefined!
> > ERROR: "_clear_bit" [fs/cifs/cifs.ko] undefined!
> > ERROR: "_test_and_clear_bit" [fs/btrfs/btrfs.ko] undefined!
> > ERROR: "_set_bit" [fs/btrfs/btrfs.ko] undefined!
> > ERROR: "_test_and_set_bit" [fs/btrfs/btrfs.ko] undefined!
> > ERROR: "_clear_bit" [fs/btrfs/btrfs.ko] undefined!
> > ERROR: "_test_and_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> > ERROR: "_set_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> > ERROR: "_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> > ERROR: "_set_bit" [drivers/usb/gadget/libcomposite.ko] undefined!
> > ERROR: "_set_bit" [drivers/usb/gadget/function/usb_f_rndis.ko] undefined!
> > ERROR: "_test_and_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> > ERROR: "_test_and_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> > ERROR: "_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> > ERROR: "_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> > ERROR: "_test_and_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> > ERROR: "_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> > ERROR: "_test_and_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> > ERROR: "_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> > ERROR: "_clear_bit" [drivers/md/dm-crypt.ko] undefined!
> > ERROR: "_set_bit" [drivers/md/dm-crypt.ko] undefined!
> > ERROR: "_set_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
> > ERROR: "_clear_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
> > ERROR: "_test_and_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
> > ERROR: "_test_and_set_bit" [drivers/bluetooth/btusb.ko] undefined!
> > ERROR: "_set_bit" [drivers/bluetooth/btusb.ko] undefined!
> > ERROR: "_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
> > ERROR: "_set_bit" [drivers/bluetooth/btintel.ko] undefined!
> > ERROR: "_set_bit" [drivers/bluetooth/btbcm.ko] undefined!
> > scripts/Makefile.modpost:91: recipe for target '__modpost' failed
> > make[1]: *** [__modpost] Error 1
> > Makefile:1191: recipe for target 'modules' failed
> > make: *** [modules] Error 2
> 
> 
> This is the config I'm using for the build:
> https://github.com/tobiasjakobi/odroid-environment/blob/master/sourcecode/system/vanilla-4.9-debug.conf

You have CONFIG_TRIM_UNUSED_KSYMS enabled - I wonder if that's the
issue.  I've just enabled that here, and building I see:

  EXPORTS lib/lib-ksyms.o
  LD      lib/built-in.o
  CHK     include/generated/autoksyms.h
  KSYMS   symbols: before=0, after=2413, changed=2413
  UPD     include/generated/autoksyms.h

and then the build seems to restart from the very beginning, which seems
rather fishy - it doubles the build time of the kernel.  The second
build doesn't even hit any ccache entries from the first build.  Then we
get through the rebuild, and I get:

  EXPORTS lib/lib-ksyms.o
  LD      lib/built-in.o
  CHK     include/generated/autoksyms.h
  LD      vmlinux.o
...
  LD      vmlinux
  SORTEX  vmlinux
  SYSMAP  System.map
  Building modules, stage 2.
  OBJCOPY arch/arm/boot/Image
  Kernel: arch/arm/boot/Image is ready
  AS      arch/arm/boot/compressed/head.o
  LZO     arch/arm/boot/compressed/piggy_data
  MODPOST 465 modules
ERROR:   CC      arch/arm/boot/compressed/misc.o
"_clear_bit" [net/sched/sch_teql.ko] undefined!
ERROR: "_set_bit" [net/sched/sch_teql.ko] undefined!
ERROR: "_set_bit" [net/sched/cls_u32.ko] undefined!
ERROR: "_test_and_set_bit" [net/netfilter/nfnetlink_acct.ko] undefined!
ERROR: "_clear_bit" [net/netfilter/nfnetlink_acct.ko] undefined!
ERROR: "_test_and_clear_bit" [net/mac80211/mac80211.ko] undefined!
ERROR: "_set_bit" [net/mac80211/mac80211.ko] undefined!
ERROR: "_test_and_set_bit" [net/mac80211/mac80211.ko] undefined!
ERROR: "_clear_bit" [net/mac80211/mac80211.ko] undefined!

So yes, it's caused by this ksyms trimming.

Now, the thing is that include/generated/autoksyms.h contains:

#define __KSYM__change_bit 1
#define __KSYM__clear_bit 1
#define __KSYM__set_bit 1
#define __KSYM__test_and_change_bit 1
#define __KSYM__test_and_clear_bit 1
#define __KSYM__test_and_set_bit 1

amongst many other stuff - presumably this is a list of ksyms which
should be included, rather than a list of what should be excluded.

I'm afraid that I never saw the patches which changed the way the ksyms
stuff worked for the assembly files, and these patches have caused
several problems for ARM.  I'm not aware of what the changes were, or
how the damn exports now work, so I'm currently at a loss what to
suggest at the moment, other than to disable CONFIG_TRIM_UNUSED_KSYMS in
your configuration until someone can work out wtf is going on.

I guess I'm going to have to work out how this stuff now works - don't
expect a solution quickly, especially as building with this option
enabled is soo time consuming (like, half an hour per build.)

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply

* [PATCH] mfd: twl-core: export twl_get_regmap
From: Nicolae Rosia @ 2016-11-20 12:54 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161118185548.GA23246@dell.home>

On Fri, Nov 18, 2016 at 8:55 PM, Lee Jones <lee.jones@linaro.org> wrote:
> On Sat, 12 Nov 2016, Nicolae Rosia wrote:
>
>> We want to get rid of global twl_i2c_{write/read}.
>> As a first step, allow clients to get the regmap and write directly
>
> What's stopping you from passing it through device data?
>
Could you elaborate a bit?
The regmaps are stored in struct twl_client [0], stored in struct
twl_private [1], both structs are defined in the source file, not in
header.
I could however just fix the problem by reworking the struct, exposing
it and use mfd_add_device as real mfd drivers do.

[0] http://lxr.free-electrons.com/source/drivers/mfd/twl-core.c#L152
[1] http://lxr.free-electrons.com/source/drivers/mfd/twl-core.c#L163

^ permalink raw reply

* commit 4dd1837d7589f468ed109556513f476e7a7f9121 breaks build
From: Tobias Jakobi @ 2016-11-20 12:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161120123422.GT1041@n2100.armlinux.org.uk>

Hey Russell,

thanks for the quick reply and looking into this!

Added Nicolas Pitre to Cc since the ksym trim stuff came from him.


Russell King - ARM Linux wrote:
> On Sun, Nov 20, 2016 at 12:43:38PM +0100, Tobias Jakobi wrote:
>> Hello Russell,
>>
>> Russell King - ARM Linux wrote:
>>> None of the autobuilders are finding this problem, and they build a
>>> wide range of configurations.  Maybe it's something specific to how
>>> you're building the kernel - can you give step by step instructions
>>> how to reproduce this please?
>> Just using plain make here, no cross-compiler or anything involved. gcc
>> is version 4.9.4.
> 
> Hmm.  The commit you mention was merged during the merge window, so
> anyone building 4.9-rc1 or later should be seeing this problem, but
> they aren't.  I've built many kernels post -rc1, and I'm not seeing
> the problem with my 4.7.4 cross compiler.
> 
>> Build platform is a Exynos4412 based ODROID-X2.
>>
>>
>> The complete log from the 'build modules' step:
>>>   Building modules, stage 2.
>>>   Kernel: arch/arm/boot/Image is ready
>>>   MODPOST 52 modules
>>>   XZKERN  arch/arm/boot/compressed/piggy_data
>>>   SHIPPED arch/arm/boot/compressed/lib1funcs.S
>>>   SHIPPED arch/arm/boot/compressed/ashldi3.S
>>>   SHIPPED arch/arm/boot/compressed/bswapsdi2.S
>>>   AS      arch/arm/boot/compressed/lib1funcs.o
>>>   AS      arch/arm/boot/compressed/ashldi3.o
>>>   AS      arch/arm/boot/compressed/bswapsdi2.o
>>> ERROR: "_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
>>> ERROR: "_test_and_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
>>> ERROR: "_clear_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_test_and_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [sound/core/seq/snd-seq.ko] undefined!
>>> ERROR: "_test_and_set_bit" [sound/core/seq/snd-seq.ko] undefined!
>>> ERROR: "_set_bit" [net/bridge/bridge.ko] undefined!
>>> ERROR: "_clear_bit" [net/bridge/bridge.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
>>> ERROR: "_set_bit" [net/bluetooth/hidp/hidp.ko] undefined!
>>> ERROR: "_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
>>> ERROR: "_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
>>> ERROR: "_test_and_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
>>> ERROR: "_clear_bit" [net/bluetooth/bnep/bnep.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [fs/fuse/fuse.ko] undefined!
>>> ERROR: "_set_bit" [fs/fuse/fuse.ko] undefined!
>>> ERROR: "_test_and_set_bit" [fs/fuse/fuse.ko] undefined!
>>> ERROR: "_clear_bit" [fs/fuse/fuse.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [fs/cifs/cifs.ko] undefined!
>>> ERROR: "_set_bit" [fs/cifs/cifs.ko] undefined!
>>> ERROR: "_test_and_set_bit" [fs/cifs/cifs.ko] undefined!
>>> ERROR: "_clear_bit" [fs/cifs/cifs.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [fs/btrfs/btrfs.ko] undefined!
>>> ERROR: "_set_bit" [fs/btrfs/btrfs.ko] undefined!
>>> ERROR: "_test_and_set_bit" [fs/btrfs/btrfs.ko] undefined!
>>> ERROR: "_clear_bit" [fs/btrfs/btrfs.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
>>> ERROR: "_set_bit" [drivers/usb/storage/usb-storage.ko] undefined!
>>> ERROR: "_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
>>> ERROR: "_set_bit" [drivers/usb/gadget/libcomposite.ko] undefined!
>>> ERROR: "_set_bit" [drivers/usb/gadget/function/usb_f_rndis.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
>>> ERROR: "_test_and_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
>>> ERROR: "_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
>>> ERROR: "_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
>>> ERROR: "_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
>>> ERROR: "_test_and_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
>>> ERROR: "_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
>>> ERROR: "_clear_bit" [drivers/md/dm-crypt.ko] undefined!
>>> ERROR: "_set_bit" [drivers/md/dm-crypt.ko] undefined!
>>> ERROR: "_set_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
>>> ERROR: "_clear_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
>>> ERROR: "_test_and_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
>>> ERROR: "_test_and_set_bit" [drivers/bluetooth/btusb.ko] undefined!
>>> ERROR: "_set_bit" [drivers/bluetooth/btusb.ko] undefined!
>>> ERROR: "_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
>>> ERROR: "_set_bit" [drivers/bluetooth/btintel.ko] undefined!
>>> ERROR: "_set_bit" [drivers/bluetooth/btbcm.ko] undefined!
>>> scripts/Makefile.modpost:91: recipe for target '__modpost' failed
>>> make[1]: *** [__modpost] Error 1
>>> Makefile:1191: recipe for target 'modules' failed
>>> make: *** [modules] Error 2
>>
>>
>> This is the config I'm using for the build:
>> https://github.com/tobiasjakobi/odroid-environment/blob/master/sourcecode/system/vanilla-4.9-debug.conf
> 
> You have CONFIG_TRIM_UNUSED_KSYMS enabled - I wonder if that's the
> issue.  I've just enabled that here, and building I see:
Thanks, I had this enabled on purpose since I don't need any out-of-tree
drivers for this board.

I'll check if disabling TRIM_UNUSED_KSYMS also does the trick for me.


With best wishes,
Tobias


>   EXPORTS lib/lib-ksyms.o
>   LD      lib/built-in.o
>   CHK     include/generated/autoksyms.h
>   KSYMS   symbols: before=0, after=2413, changed=2413
>   UPD     include/generated/autoksyms.h
> 
> and then the build seems to restart from the very beginning, which seems
> rather fishy - it doubles the build time of the kernel.  The second
> build doesn't even hit any ccache entries from the first build.  Then we
> get through the rebuild, and I get:
> 
>   EXPORTS lib/lib-ksyms.o
>   LD      lib/built-in.o
>   CHK     include/generated/autoksyms.h
>   LD      vmlinux.o
> ...
>   LD      vmlinux
>   SORTEX  vmlinux
>   SYSMAP  System.map
>   Building modules, stage 2.
>   OBJCOPY arch/arm/boot/Image
>   Kernel: arch/arm/boot/Image is ready
>   AS      arch/arm/boot/compressed/head.o
>   LZO     arch/arm/boot/compressed/piggy_data
>   MODPOST 465 modules
> ERROR:   CC      arch/arm/boot/compressed/misc.o
> "_clear_bit" [net/sched/sch_teql.ko] undefined!
> ERROR: "_set_bit" [net/sched/sch_teql.ko] undefined!
> ERROR: "_set_bit" [net/sched/cls_u32.ko] undefined!
> ERROR: "_test_and_set_bit" [net/netfilter/nfnetlink_acct.ko] undefined!
> ERROR: "_clear_bit" [net/netfilter/nfnetlink_acct.ko] undefined!
> ERROR: "_test_and_clear_bit" [net/mac80211/mac80211.ko] undefined!
> ERROR: "_set_bit" [net/mac80211/mac80211.ko] undefined!
> ERROR: "_test_and_set_bit" [net/mac80211/mac80211.ko] undefined!
> ERROR: "_clear_bit" [net/mac80211/mac80211.ko] undefined!
> 
> So yes, it's caused by this ksyms trimming.
> 
> Now, the thing is that include/generated/autoksyms.h contains:
> 
> #define __KSYM__change_bit 1
> #define __KSYM__clear_bit 1
> #define __KSYM__set_bit 1
> #define __KSYM__test_and_change_bit 1
> #define __KSYM__test_and_clear_bit 1
> #define __KSYM__test_and_set_bit 1
> 
> amongst many other stuff - presumably this is a list of ksyms which
> should be included, rather than a list of what should be excluded.
> 
> I'm afraid that I never saw the patches which changed the way the ksyms
> stuff worked for the assembly files, and these patches have caused
> several problems for ARM.  I'm not aware of what the changes were, or
> how the damn exports now work, so I'm currently at a loss what to
> suggest at the moment, other than to disable CONFIG_TRIM_UNUSED_KSYMS in
> your configuration until someone can work out wtf is going on.
> 
> I guess I'm going to have to work out how this stuff now works - don't
> expect a solution quickly, especially as building with this option
> enabled is soo time consuming (like, half an hour per build.)
> 

^ permalink raw reply

* [PATCH] mfd: twl-core: make driver DT only
From: Nicolae Rosia @ 2016-11-20 12:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161118190115.GB23246@dell.home>

Hi,

On Fri, Nov 18, 2016 at 9:01 PM, Lee Jones <lee.jones@linaro.org> wrote:
> On Sat, 12 Nov 2016, Nicolae Rosia wrote:
>
>> All users are DT-only and it makes no sense to keep
>> unused code
>>
>> Signed-off-by: Nicolae Rosia <Nicolae_Rosia@mentor.com>
>> ---
>>  drivers/mfd/Kconfig    |   1 +
>>  drivers/mfd/twl-core.c | 395 ++-----------------------------------------------
>>  2 files changed, 10 insertions(+), 386 deletions(-)
>
> I think it would be courteous to add some of the serious contributors
> to the review list.
>
> There may still be some out of tree users who might wish for a
> heads-up that this change is about to be merged.
Thanks, sure, I will do that in v2.

^ permalink raw reply

* [PATCH] spi: davinci: Allow device tree devices to use DMA
From: Sekhar Nori @ 2016-11-20 12:59 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1479530464-12538-1-git-send-email-david@lechnology.com>

On Saturday 19 November 2016 10:11 AM, David Lechner wrote:
> This makes SPI devices specified in a device tree use DMA when the master
> controller has DMA configured.
> 
> Since device tree is supposed to only describe the hardware, adding a
> configuration option to device tree to enable DMA per-device would not be
> acceptable. So, this is the best we can do for now to get SPI devices
> working with DMA when using device tree.
> 
> Unfortunately, this excludes the possibility of using one SPI device with
> DMA and one without on the same master.
> 
> I have tested this on LEGO MINDSTORMS EV3 using the NOR flash. Reading the
> flash memory would fail with -EIO when DMA is not enabled for the device.
> 
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
>  drivers/spi/spi-davinci.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
> index d36c11b..c6cf73a 100644
> --- a/drivers/spi/spi-davinci.c
> +++ b/drivers/spi/spi-davinci.c
> @@ -388,6 +388,7 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
>  static int davinci_spi_of_setup(struct spi_device *spi)
>  {
>  	struct davinci_spi_config *spicfg = spi->controller_data;
> +	struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
>  	struct device_node *np = spi->dev.of_node;
>  	u32 prop;
>  
> @@ -400,6 +401,9 @@ static int davinci_spi_of_setup(struct spi_device *spi)
>  		if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
>  			spicfg->wdelay = (u8)prop;
>  		spi->controller_data = spicfg;
> +		/* Use DMA for device if master supports it */
> +		if (dspi->dma_rx)

This should be

		if (!(IS_ERR(dpsi->dma_rx) || IS_ERR(dspi->dma_tx))

> +			spicfg->io_type = SPI_IO_TYPE_DMA;

Otherwise looks good to me.

Thanks,
Sekhar

^ permalink raw reply

* commit 4dd1837d7589f468ed109556513f476e7a7f9121 breaks build
From: Corentin Labbe @ 2016-11-20 13:02 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161120123422.GT1041@n2100.armlinux.org.uk>

On Sun, Nov 20, 2016 at 12:34:22PM +0000, Russell King - ARM Linux wrote:
> On Sun, Nov 20, 2016 at 12:43:38PM +0100, Tobias Jakobi wrote:
> > Hello Russell,
> > 
> > Russell King - ARM Linux wrote:
> > > None of the autobuilders are finding this problem, and they build a
> > > wide range of configurations.  Maybe it's something specific to how
> > > you're building the kernel - can you give step by step instructions
> > > how to reproduce this please?
> > Just using plain make here, no cross-compiler or anything involved. gcc
> > is version 4.9.4.
> 
> Hmm.  The commit you mention was merged during the merge window, so
> anyone building 4.9-rc1 or later should be seeing this problem, but
> they aren't.  I've built many kernels post -rc1, and I'm not seeing
> the problem with my 4.7.4 cross compiler.
> 

I have the same issue here on all my Allwinner ARM device.
I have not reported this issue since I believed to see some report of it.

I cross compile with armv7a-hardfloat-linux-gnueabi-4.9.3.

With CONFIG_UNUSED_SYMBOLS set, the issue disapear

Regards

^ permalink raw reply

* i.MX6UL: feature state of linux-fslc 4.1.x vs mainline
From: Fabio Estevam @ 2016-11-20 13:04 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <CAKP5S=2WAdCfONGQEAup7yUGXp615QUZ83oAYmyJ6kjGhAG_YQ@mail.gmail.com>

Hi Nicolae,

On Thu, Nov 17, 2016 at 10:56 AM, Nicolae Rosia
<nicolae.rosia.oss@gmail.com> wrote:
> Hello,
>
> I'm wondering if there is a table of missing features that are present
> in Linux freescale 4.1.x [0] and are not present in latest mainline
> kernel with regards to NXP i.MX6UL SoC.

I don't think there is such table available.

> Is there a reason why I should go with linux-fslc for this SoC ?

You can use mainline kernel with mx6ul.

>From the top of my head it still misses PXP and camera support though.

^ permalink raw reply

* [PATCH v5 0/2] platform: Add DT support for DA8xx
From: Sekhar Nori @ 2016-11-20 13:08 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1479294456-7942-1-git-send-email-abailon@baylibre.com>

On Wednesday 16 November 2016 04:37 PM, Alexandre Bailon wrote:
> This add and enable the usb otg for da850 and da850-lcdk.
> This series depends on "driver: dd DT support for DA8xx" patch set.

I see that Bin has already applied this.

> If this series is applied before the "usb: musb: da8xx: Fix few issues" patch
> set then the usb driver will always retrun -ENODEV.

And this seems to be applied too. So I am going ahead and applying this
series.

For future, please add some information on which device you are
referring to in the subject line. Reading the subject line for the
cover-letter, there is no way to know what exactly is being worked on here.

Thanks,
Sekhar

^ permalink raw reply

* [PATCH v8 6/7] arm/arm64: vgic: Implement VGICv3 CPU interface access
From: Christoffer Dall @ 2016-11-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <CALicx6uxU8nC+gayWAxf_BX7JrZ9twsFr4YfMr64bNUSneqZow@mail.gmail.com>

On Sat, Nov 19, 2016 at 12:18:53AM +0530, Vijay Kilari wrote:
> On Thu, Nov 17, 2016 at 9:39 PM, Christoffer Dall
> <christoffer.dall@linaro.org> wrote:
> > On Thu, Nov 17, 2016 at 09:25:59PM +0530, Vijay Kilari wrote:
> >> On Thu, Nov 17, 2016 at 12:22 AM, Christoffer Dall
> >> <christoffer.dall@linaro.org> wrote:
> >> > On Fri, Nov 04, 2016 at 04:43:32PM +0530, vijay.kilari at gmail.com wrote:
> >> >> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >> >>
> >> >> VGICv3 CPU interface registers are accessed using
> >> >> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
> >> >> as 64-bit. The cpu MPIDR value is passed along with register id.
> >> >> is used to identify the cpu for registers access.
> >> >>
> >> >> The version of VGIC v3 specification is define here
> >> >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
> >> >>
> >> >> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
> >> >> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >> >> ---
> >> >>  arch/arm64/include/uapi/asm/kvm.h   |   3 +
> >> >>  arch/arm64/kvm/Makefile             |   1 +
> >> >>  include/kvm/arm_vgic.h              |   9 +
> >> >>  virt/kvm/arm/vgic/vgic-kvm-device.c |  27 +++
> >> >>  virt/kvm/arm/vgic/vgic-mmio-v3.c    |  19 +++
> >> >>  virt/kvm/arm/vgic/vgic-sys-reg-v3.c | 324 ++++++++++++++++++++++++++++++++++++
> >> >>  virt/kvm/arm/vgic/vgic-v3.c         |   8 +
> >> >>  virt/kvm/arm/vgic/vgic.h            |   4 +
> >> >>  8 files changed, 395 insertions(+)
> >> >>
> >> >> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> >> >> index 56dc08d..91c7137 100644
> >> >> --- a/arch/arm64/include/uapi/asm/kvm.h
> >> >> +++ b/arch/arm64/include/uapi/asm/kvm.h
> >> >> @@ -206,9 +206,12 @@ struct kvm_arch_memory_slot {
> >> >>                       (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
> >> >>  #define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT      0
> >> >>  #define   KVM_DEV_ARM_VGIC_OFFSET_MASK       (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
> >> >> +#define   KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
> >> >>  #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
> >> >>  #define KVM_DEV_ARM_VGIC_GRP_CTRL    4
> >> >>  #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
> >> >> +#define KVM_DEV_ARM_VGIC_CPU_SYSREGS    6
> >> >> +
> >> >>  #define   KVM_DEV_ARM_VGIC_CTRL_INIT 0
> >> >>
> >> >>  /* Device Control API on vcpu fd */
> >> >> diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
> >> >> index d50a82a..1a14e29 100644
> >> >> --- a/arch/arm64/kvm/Makefile
> >> >> +++ b/arch/arm64/kvm/Makefile
> >> >> @@ -32,5 +32,6 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-mmio-v3.o
> >> >>  kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-kvm-device.o
> >> >>  kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-its.o
> >> >>  kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o
> >> >> +kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-sys-reg-v3.o
> >> >
> >> > Thi is making me wonder:  Are we properly handling GICv3 save/restore
> >> > for AArch32 now that we have GICv3 support for AArch32?  By properly I
> >> > mean that either it is clearly only supported on AArch64 systems or it's
> >> > supported on both AArch64 and AArch32, but it shouldn't break randomly
> >> > on AArch32.
> >>
> >> It supports both AArch64 and AArch64 in handling of system registers
> >> save/restore.
> >> All system registers that we save/restore are 32-bit for both aarch64
> >> and aarch32.
> >> Though opcode op0 should be zero for aarch32, the remaining Op and CRn codes
> >> are same. However the codes sent by qemu is matched and register
> >> are handled properly irrespective of AArch32 or AArch64.
> >>
> >> I don't have platform which support AArch32 guests to verify.
> >
> > Actually this is not about the guest, it's about an ARMv8 AArch32 host
> > that has a GICv3.
> >
> > I just tried to do a v7 compile with your patches, and it results in an
> > epic failure, so there's something for you to look at.
> >
> 
> Could you please share you config file?. I tried with multi_v7 defconfig with
> CONFIG KVM and CONFIG_KVM_ARM_HOST enabled. it compiled for me.

I think this has to do with which branch you apply your patches to.
When applied to kvmarm/next, it fails.

Here's the integration I did:
https://git.linaro.org/people/christoffer.dall/linux-kvm-arm.git tmp-gicv3-migrate-v8

Here's the config:
https://transfer.sh/xkAxp/.config

Here's the compile output:

/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-mmio-v3.c:26:22: fatal error: sys_regs.h: No such file or directory
 #include "sys_regs.h"
                      ^
compilation terminated.
make[2]: *** [arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-mmio-v3.o] Error 1
make[2]: *** Waiting for unfinished jobs....
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c: In function ?vgic_v3_parse_attr?:
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:438:29: error: ?KVM_DEV_ARM_VGIC_V3_MPIDR_MASK? undeclared (first use in this function)
  vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
                             ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:438:29: note: each undeclared identifier is reported only once for each function it appears in
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:439:9: error: ?KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT? undeclared (first use in this function)
         KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
         ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:441:2: error: implicit declaration of function ?MPIDR_LEVEL_SHIFT? [-Werror=implicit-function-declaration]
  mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
  ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c: In function ?vgic_v3_attr_regs_access?:
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:497:7: error: ?KVM_DEV_ARM_VGIC_GRP_REDIST_REGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:505:7: error: ?KVM_DEV_ARM_VGIC_CPU_SYSREGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_CPU_SYSREGS: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:508:25: error: ?KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK? undeclared (first use in this function)
   regid = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
                         ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:513:7: error: ?KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:516:24: error: ?KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK? undeclared (first use in this function)
   info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
                        ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:517:4: error: ?KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT? undeclared (first use in this function)
    KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
    ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:518:15: error: ?VGIC_LEVEL_INFO_LINE_LEVEL? undeclared (first use in this function)
   if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
               ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:522:5: error: ?KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK? undeclared (first use in this function)
     KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
     ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c: In function ?vgic_v3_set_attr?:
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:554:7: error: ?KVM_DEV_ARM_VGIC_GRP_REDIST_REGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:565:7: error: ?KVM_DEV_ARM_VGIC_CPU_SYSREGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_CPU_SYSREGS: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:574:7: error: ?KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c: In function ?vgic_v3_get_attr?:
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:600:7: error: ?KVM_DEV_ARM_VGIC_GRP_REDIST_REGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:611:7: error: ?KVM_DEV_ARM_VGIC_CPU_SYSREGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_CPU_SYSREGS: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:620:7: error: ?KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c: In function ?vgic_v3_has_attr?:
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:647:7: error: ?KVM_DEV_ARM_VGIC_GRP_REDIST_REGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:648:7: error: ?KVM_DEV_ARM_VGIC_CPU_SYSREGS? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_CPU_SYSREGS:
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:652:7: error: ?KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO? undeclared (first use in this function)
  case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
       ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:653:22: error: ?KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK? undeclared (first use in this function)
   if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
                      ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:654:9: error: ?KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT? undeclared (first use in this function)
         KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
         ^
/home/christoffer/src/kvmarm/linux/arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.c:655:9: error: ?VGIC_LEVEL_INFO_LINE_LEVEL? undeclared (first use in this function)
         VGIC_LEVEL_INFO_LINE_LEVEL)
         ^
cc1: some warnings being treated as errors
make[2]: *** [arch/arm/kvm/../../../virt/kvm/arm/vgic/vgic-kvm-device.o] Error 1
make[1]: *** [arch/arm/kvm] Error 2
make[1]: *** Waiting for unfinished jobs....
make: *** [sub-make] Error 2

Thanks,
-Christoffer

^ permalink raw reply

* commit 4dd1837d7589f468ed109556513f476e7a7f9121 breaks build
From: Russell King - ARM Linux @ 2016-11-20 13:25 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <58319D70.7030106@math.uni-bielefeld.de>

On Sun, Nov 20, 2016 at 01:56:16PM +0100, Tobias Jakobi wrote:
> Hey Russell,
> 
> thanks for the quick reply and looking into this!
> 
> Added Nicolas Pitre to Cc since the ksym trim stuff came from him.

Arnd's patch "kbuild: provide include/asm/asm-prototypes.h for ARM" fixes
it, but I think it's a mixture of fixes, and partially dependent on some
other patches.  I don't know what the status of his patch is, but my
feeling is that it consists of more than a single fix, and needs
splitting.  Certainly the asm-prototypes.h is not relevant to this
problem, but the rest of it seems to be.

> Russell King - ARM Linux wrote:
> > On Sun, Nov 20, 2016 at 12:43:38PM +0100, Tobias Jakobi wrote:
> >> Hello Russell,
> >>
> >> Russell King - ARM Linux wrote:
> >>> None of the autobuilders are finding this problem, and they build a
> >>> wide range of configurations.  Maybe it's something specific to how
> >>> you're building the kernel - can you give step by step instructions
> >>> how to reproduce this please?
> >> Just using plain make here, no cross-compiler or anything involved. gcc
> >> is version 4.9.4.
> > 
> > Hmm.  The commit you mention was merged during the merge window, so
> > anyone building 4.9-rc1 or later should be seeing this problem, but
> > they aren't.  I've built many kernels post -rc1, and I'm not seeing
> > the problem with my 4.7.4 cross compiler.
> > 
> >> Build platform is a Exynos4412 based ODROID-X2.
> >>
> >>
> >> The complete log from the 'build modules' step:
> >>>   Building modules, stage 2.
> >>>   Kernel: arch/arm/boot/Image is ready
> >>>   MODPOST 52 modules
> >>>   XZKERN  arch/arm/boot/compressed/piggy_data
> >>>   SHIPPED arch/arm/boot/compressed/lib1funcs.S
> >>>   SHIPPED arch/arm/boot/compressed/ashldi3.S
> >>>   SHIPPED arch/arm/boot/compressed/bswapsdi2.S
> >>>   AS      arch/arm/boot/compressed/lib1funcs.o
> >>>   AS      arch/arm/boot/compressed/ashldi3.o
> >>>   AS      arch/arm/boot/compressed/bswapsdi2.o
> >>> ERROR: "_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> >>> ERROR: "_clear_bit" [sound/usb/snd-usbmidi-lib.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> >>> ERROR: "_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [sound/usb/snd-usb-audio.ko] undefined!
> >>> ERROR: "_clear_bit" [sound/usb/snd-usb-audio.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [sound/core/seq/snd-seq.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [sound/core/seq/snd-seq.ko] undefined!
> >>> ERROR: "_set_bit" [net/bridge/bridge.ko] undefined!
> >>> ERROR: "_clear_bit" [net/bridge/bridge.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> >>> ERROR: "_set_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> >>> ERROR: "_clear_bit" [net/bluetooth/hidp/hidp.ko] undefined!
> >>> ERROR: "_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> >>> ERROR: "_clear_bit" [net/bluetooth/bnep/bnep.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [fs/fuse/fuse.ko] undefined!
> >>> ERROR: "_set_bit" [fs/fuse/fuse.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [fs/fuse/fuse.ko] undefined!
> >>> ERROR: "_clear_bit" [fs/fuse/fuse.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [fs/cifs/cifs.ko] undefined!
> >>> ERROR: "_set_bit" [fs/cifs/cifs.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [fs/cifs/cifs.ko] undefined!
> >>> ERROR: "_clear_bit" [fs/cifs/cifs.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [fs/btrfs/btrfs.ko] undefined!
> >>> ERROR: "_set_bit" [fs/btrfs/btrfs.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [fs/btrfs/btrfs.ko] undefined!
> >>> ERROR: "_clear_bit" [fs/btrfs/btrfs.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> >>> ERROR: "_clear_bit" [drivers/usb/storage/usb-storage.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/usb/gadget/libcomposite.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/usb/gadget/function/usb_f_rndis.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> >>> ERROR: "_clear_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/usb/gadget/function/u_ether.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> >>> ERROR: "_clear_bit" [drivers/media/platform/s5p-mfc/s5p-mfc.ko] undefined!
> >>> ERROR: "_clear_bit" [drivers/md/dm-crypt.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/md/dm-crypt.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
> >>> ERROR: "_clear_bit" [drivers/gpu/arm/mali/maligpu.ko] undefined!
> >>> ERROR: "_test_and_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
> >>> ERROR: "_test_and_set_bit" [drivers/bluetooth/btusb.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/bluetooth/btusb.ko] undefined!
> >>> ERROR: "_clear_bit" [drivers/bluetooth/btusb.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/bluetooth/btintel.ko] undefined!
> >>> ERROR: "_set_bit" [drivers/bluetooth/btbcm.ko] undefined!
> >>> scripts/Makefile.modpost:91: recipe for target '__modpost' failed
> >>> make[1]: *** [__modpost] Error 1
> >>> Makefile:1191: recipe for target 'modules' failed
> >>> make: *** [modules] Error 2
> >>
> >>
> >> This is the config I'm using for the build:
> >> https://github.com/tobiasjakobi/odroid-environment/blob/master/sourcecode/system/vanilla-4.9-debug.conf
> > 
> > You have CONFIG_TRIM_UNUSED_KSYMS enabled - I wonder if that's the
> > issue.  I've just enabled that here, and building I see:
> Thanks, I had this enabled on purpose since I don't need any out-of-tree
> drivers for this board.
> 
> I'll check if disabling TRIM_UNUSED_KSYMS also does the trick for me.
> 
> 
> With best wishes,
> Tobias
> 
> 
> >   EXPORTS lib/lib-ksyms.o
> >   LD      lib/built-in.o
> >   CHK     include/generated/autoksyms.h
> >   KSYMS   symbols: before=0, after=2413, changed=2413
> >   UPD     include/generated/autoksyms.h
> > 
> > and then the build seems to restart from the very beginning, which seems
> > rather fishy - it doubles the build time of the kernel.  The second
> > build doesn't even hit any ccache entries from the first build.  Then we
> > get through the rebuild, and I get:
> > 
> >   EXPORTS lib/lib-ksyms.o
> >   LD      lib/built-in.o
> >   CHK     include/generated/autoksyms.h
> >   LD      vmlinux.o
> > ...
> >   LD      vmlinux
> >   SORTEX  vmlinux
> >   SYSMAP  System.map
> >   Building modules, stage 2.
> >   OBJCOPY arch/arm/boot/Image
> >   Kernel: arch/arm/boot/Image is ready
> >   AS      arch/arm/boot/compressed/head.o
> >   LZO     arch/arm/boot/compressed/piggy_data
> >   MODPOST 465 modules
> > ERROR:   CC      arch/arm/boot/compressed/misc.o
> > "_clear_bit" [net/sched/sch_teql.ko] undefined!
> > ERROR: "_set_bit" [net/sched/sch_teql.ko] undefined!
> > ERROR: "_set_bit" [net/sched/cls_u32.ko] undefined!
> > ERROR: "_test_and_set_bit" [net/netfilter/nfnetlink_acct.ko] undefined!
> > ERROR: "_clear_bit" [net/netfilter/nfnetlink_acct.ko] undefined!
> > ERROR: "_test_and_clear_bit" [net/mac80211/mac80211.ko] undefined!
> > ERROR: "_set_bit" [net/mac80211/mac80211.ko] undefined!
> > ERROR: "_test_and_set_bit" [net/mac80211/mac80211.ko] undefined!
> > ERROR: "_clear_bit" [net/mac80211/mac80211.ko] undefined!
> > 
> > So yes, it's caused by this ksyms trimming.
> > 
> > Now, the thing is that include/generated/autoksyms.h contains:
> > 
> > #define __KSYM__change_bit 1
> > #define __KSYM__clear_bit 1
> > #define __KSYM__set_bit 1
> > #define __KSYM__test_and_change_bit 1
> > #define __KSYM__test_and_clear_bit 1
> > #define __KSYM__test_and_set_bit 1
> > 
> > amongst many other stuff - presumably this is a list of ksyms which
> > should be included, rather than a list of what should be excluded.
> > 
> > I'm afraid that I never saw the patches which changed the way the ksyms
> > stuff worked for the assembly files, and these patches have caused
> > several problems for ARM.  I'm not aware of what the changes were, or
> > how the damn exports now work, so I'm currently at a loss what to
> > suggest at the moment, other than to disable CONFIG_TRIM_UNUSED_KSYMS in
> > your configuration until someone can work out wtf is going on.
> > 
> > I guess I'm going to have to work out how this stuff now works - don't
> > expect a solution quickly, especially as building with this option
> > enabled is soo time consuming (like, half an hour per build.)
> > 
> 

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply

page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox