* [PATCH 5/7] add bindings for stm32 IIO timer drivers
From: Benjamin Gaignard @ 2016-11-22 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479831207-32699-1-git-send-email-benjamin.gaignard@st.com>
Define bindings for stm32 IIO timer
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../bindings/iio/timer/stm32-iio-timer.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
new file mode 100644
index 0000000..b80025e
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
@@ -0,0 +1,33 @@
+timer IIO trigger bindings for STM32
+
+Must be a child of STM32 multifunctions timer driver
+
+Required parameters:
+- compatible: must be one of the follow value:
+ "st,stm32-iio-timer1"
+ "st,stm32-iio-timer2"
+ "st,stm32-iio-timer3"
+ "st,stm32-iio-timer4"
+ "st,stm32-iio-timer5"
+ "st,stm32-iio-timer6"
+ "st,stm32-iio-timer7"
+ "st,stm32-iio-timer8"
+ "st,stm32-iio-timer9"
+ "st,stm32-iio-timer10"
+ "st,stm32-iio-timer11"
+ "st,stm32-iio-timer12"
+ "st,stm32-iio-timer13"
+ "st,stm32-iio-timer14"
+
+Example:
+ mfd_timer1: mfdtimer1 at 40010000 {
+ compatible = "st,stm32-mfd-timer1";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <27>;
+
+ trigger1: trigger1 at 40010000 {
+ compatible = "st,stm32-iio-timer1";
+ };
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH 4/7] add pwm driver for stm32 plaftorm
From: Benjamin Gaignard @ 2016-11-22 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479831207-32699-1-git-send-email-benjamin.gaignard@st.com>
This driver add support for pwm driver on stm32 platform.
The SoC have multiple instances of the hardware IP and each
of them could have small differences: number of channels,
complementary output, counter register size...
To handle those variations each block have its own compatible
linked to internal table that describe them.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
drivers/pwm/Kconfig | 8 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-stm32.c | 358 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 367 insertions(+)
create mode 100644 drivers/pwm/pwm-stm32.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index bf01288..aeee045 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -388,6 +388,14 @@ config PWM_STI
To compile this driver as a module, choose M here: the module
will be called pwm-sti.
+config PWM_STM32
+ bool "STMicroelectronics STM32 PWM"
+ depends on ARCH_STM32
+ depends on OF
+ select MFD_STM32_TIMER
+ help
+ Generic PWM framework driver for STM32 SoCs.
+
config PWM_STMPE
bool "STMPE expander PWM export"
depends on MFD_STMPE
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 1194c54..5aa9308 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
+obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
new file mode 100644
index 0000000..2d71ee7
--- /dev/null
+++ b/drivers/pwm/pwm-stm32.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Gerald Baeza <gerald.baeza@st.com>
+ * License terms: GNU General Public License (GPL), version 2
+ *
+ * Inspired by timer-stm32.c from Maxime Coquelin
+ * pwm-atmel.c from Bo Shen
+ */
+
+#include <linux/module.h>
+#include <linux/pwm.h>
+
+#include <linux/mfd/stm32-mfd-timer.h>
+
+#define DRIVER_NAME "stm32-pwm"
+
+#define CAP_COMPLEMENTARY BIT(0)
+#define CAP_32BIT_COUNTER BIT(1)
+#define CAP_BREAKINPUT BIT(2)
+
+struct stm32_pwm_cfg {
+ int npwm;
+ int caps;
+};
+
+static struct stm32_pwm_cfg f4_pwm_cfg[] = {
+ /* for pwm 1 and 8 */
+ {
+ .npwm = 4,
+ .caps = CAP_COMPLEMENTARY | CAP_BREAKINPUT,
+ },
+ /* for pwm 2 and 5 */
+ {
+ .npwm = 4,
+ .caps = CAP_32BIT_COUNTER,
+ },
+ /* for pwm 3 and 4 */
+ {
+ .npwm = 4,
+ .caps = 0,
+ },
+ /* for pwm 9 and 12 */
+ {
+ .npwm = 2,
+ .caps = 0,
+ },
+ /* for pwm 10, 11, 13 and 14 */
+ {
+ .npwm = 1,
+ .caps = 0,
+ },
+};
+
+struct stm32_pwm_dev {
+ struct device *dev;
+ struct clk *clk;
+ struct regmap *regmap;
+ struct pwm_chip chip;
+ struct stm32_pwm_cfg *cfg;
+ bool have_breakinput;
+ u32 breakinput_polarity;
+};
+
+#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm_dev, chip)
+
+static u32 __active_channels(struct stm32_pwm_dev *pwm_dev)
+{
+ u32 ccer;
+
+ regmap_read(pwm_dev->regmap, TIM_CCER, &ccer);
+
+ return ccer & TIM_CCER_CCXE;
+}
+
+static int write_ccrx(struct stm32_pwm_dev *dev, struct pwm_device *pwm,
+ u32 ccr)
+{
+ switch (pwm->hwpwm) {
+ case 0:
+ return regmap_write(dev->regmap, TIM_CCR1, ccr);
+ case 1:
+ return regmap_write(dev->regmap, TIM_CCR2, ccr);
+ case 2:
+ return regmap_write(dev->regmap, TIM_CCR3, ccr);
+ case 3:
+ return regmap_write(dev->regmap, TIM_CCR4, ccr);
+ }
+ return -EINVAL;
+}
+
+static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+ int duty_ns, int period_ns)
+{
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+ unsigned long long prd, div, dty;
+ int prescaler = 0;
+ u32 max_arr = 0xFFFF, ccmr, mask, shift, bdtr;
+
+ if (dev->cfg->caps & CAP_32BIT_COUNTER)
+ max_arr = 0xFFFFFFFF;
+
+ /* Period and prescaler values depends of clock rate */
+ div = (unsigned long long)clk_get_rate(dev->clk) * period_ns;
+
+ do_div(div, NSEC_PER_SEC);
+ prd = div;
+
+ while (div > max_arr) {
+ prescaler++;
+ div = prd;
+ do_div(div, (prescaler + 1));
+ }
+ prd = div;
+
+ if (prescaler > MAX_TIM_PSC) {
+ dev_err(chip->dev, "prescaler exceeds the maximum value\n");
+ return -EINVAL;
+ }
+
+ /* All channels share the same prescaler and counter so
+ * when two channels are active at the same we can't change them
+ */
+ if (__active_channels(dev) & ~(1 << pwm->hwpwm * 4)) {
+ u32 psc, arr;
+
+ regmap_read(dev->regmap, TIM_PSC, &psc);
+ regmap_read(dev->regmap, TIM_ARR, &arr);
+
+ if ((psc != prescaler) || (arr != prd - 1))
+ return -EINVAL;
+ }
+
+ regmap_write(dev->regmap, TIM_PSC, prescaler);
+ regmap_write(dev->regmap, TIM_ARR, prd - 1);
+ regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
+
+ /* Calculate the duty cycles */
+ dty = prd * duty_ns;
+ do_div(dty, period_ns);
+
+ write_ccrx(dev, pwm, dty);
+
+ /* Configure output mode */
+ shift = (pwm->hwpwm & 0x1) * 8;
+ ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
+ mask = 0xFF << shift;
+
+ if (pwm->hwpwm & 0x2)
+ regmap_update_bits(dev->regmap, TIM_CCMR2, mask, ccmr);
+ else
+ regmap_update_bits(dev->regmap, TIM_CCMR1, mask, ccmr);
+
+ bdtr = TIM_BDTR_MOE | TIM_BDTR_AOE;
+ if (dev->have_breakinput) {
+ bdtr |= TIM_BDTR_BKE;
+ if (dev->breakinput_polarity)
+ bdtr |= TIM_BDTR_BKP;
+ }
+
+ regmap_update_bits(dev->regmap, TIM_BDTR,
+ TIM_BDTR_MOE | TIM_BDTR_AOE |
+ TIM_BDTR_BKP | TIM_BDTR_BKE,
+ bdtr);
+
+ return 0;
+}
+
+static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ u32 mask;
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+
+ mask = TIM_CCER_CC1P << (pwm->hwpwm * 4);
+ if (dev->cfg->caps & CAP_COMPLEMENTARY)
+ mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4);
+
+ regmap_update_bits(dev->regmap, TIM_CCER, mask,
+ polarity == PWM_POLARITY_NORMAL ? 0 : mask);
+
+ return 0;
+}
+
+static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ u32 mask;
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+
+ clk_enable(dev->clk);
+
+ /* Enable channel */
+ mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
+ if (dev->cfg->caps & CAP_COMPLEMENTARY)
+ mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
+
+ regmap_update_bits(dev->regmap, TIM_CCER, mask, mask);
+
+ /* Make sure that registers are updated */
+ regmap_update_bits(dev->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
+
+ /* Enable controller */
+ regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
+
+ return 0;
+}
+
+static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ u32 mask;
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+
+ /* Disable channel */
+ mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
+ if (dev->cfg->caps & CAP_COMPLEMENTARY)
+ mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
+
+ regmap_update_bits(dev->regmap, TIM_CCER, mask, 0);
+
+ /* When all channels are disabled, we can disable the controller */
+ if (!__active_channels(dev))
+ regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+
+ clk_disable(dev->clk);
+}
+
+static const struct pwm_ops stm32pwm_ops = {
+ .config = stm32_pwm_config,
+ .set_polarity = stm32_pwm_set_polarity,
+ .enable = stm32_pwm_enable,
+ .disable = stm32_pwm_disable,
+};
+
+static const struct of_device_id stm32_pwm_of_match[] = {
+ {
+ .compatible = "st,stm32-pwm1",
+ .data = &f4_pwm_cfg[0],
+ },
+ {
+ .compatible = "st,stm32-pwm2",
+ .data = &f4_pwm_cfg[1],
+ },
+ {
+ .compatible = "st,stm32-pwm3",
+ .data = &f4_pwm_cfg[2],
+ },
+ {
+ .compatible = "st,stm32-pwm4",
+ .data = &f4_pwm_cfg[2],
+ },
+ {
+ .compatible = "st,stm32-pwm5",
+ .data = &f4_pwm_cfg[1],
+ },
+ {
+ .compatible = "st,stm32-pwm8",
+ .data = &f4_pwm_cfg[0],
+ },
+ {
+ .compatible = "st,stm32-pwm9",
+ .data = &f4_pwm_cfg[3],
+ },
+ {
+ .compatible = "st,stm32-pwm10",
+ .data = &f4_pwm_cfg[4],
+ },
+ {
+ .compatible = "st,stm32-pwm11",
+ .data = &f4_pwm_cfg[4],
+ },
+ {
+ .compatible = "st,stm32-pwm12",
+ .data = &f4_pwm_cfg[3],
+ },
+ {
+ .compatible = "st,stm32-pwm13",
+ .data = &f4_pwm_cfg[4],
+ },
+ {
+ .compatible = "st,stm32-pwm14",
+ .data = &f4_pwm_cfg[4],
+ },
+ {
+ /* end node */
+ },
+};
+MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
+
+static int stm32_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct stm32_mfd_timer_dev *mfd = pdev->dev.platform_data;
+ struct stm32_pwm_dev *pwm;
+ int ret;
+
+ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ return -ENOMEM;
+
+ pwm->regmap = mfd->regmap;
+ pwm->clk = mfd->clk;
+
+ if (!pwm->regmap || !pwm->clk)
+ return -EINVAL;
+
+ /* populate data structure depending on compatibility */
+ if (!of_match_node(stm32_pwm_of_match, np)->data)
+ return -EINVAL;
+
+ pwm->cfg =
+ (struct stm32_pwm_cfg *)of_match_node(stm32_pwm_of_match, np)->data;
+
+ if (pwm->cfg->caps & CAP_BREAKINPUT) {
+ if (!of_property_read_u32(np, "st,breakinput-polarity",
+ &pwm->breakinput_polarity))
+ pwm->have_breakinput = true;
+ }
+
+ pwm->chip.base = -1;
+ pwm->chip.dev = dev;
+ pwm->chip.ops = &stm32pwm_ops;
+ pwm->chip.npwm = pwm->cfg->npwm;
+
+ ret = pwmchip_add(&pwm->chip);
+ if (ret < 0)
+ return ret;
+
+ platform_set_drvdata(pdev, pwm);
+
+ return 0;
+}
+
+static int stm32_pwm_remove(struct platform_device *pdev)
+{
+ struct stm32_pwm_dev *pwm = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < pwm->cfg->npwm; i++)
+ pwm_disable(&pwm->chip.pwms[i]);
+
+ pwmchip_remove(&pwm->chip);
+
+ return 0;
+}
+
+static struct platform_driver stm32_pwm_driver = {
+ .probe = stm32_pwm_probe,
+ .remove = stm32_pwm_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = stm32_pwm_of_match,
+ },
+};
+module_platform_driver(stm32_pwm_driver);
+
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
+MODULE_LICENSE("GPL");
--
1.9.1
^ permalink raw reply related
* [PATCH 3/7] add pwm-stm32 DT bindings
From: Benjamin Gaignard @ 2016-11-22 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479831207-32699-1-git-send-email-benjamin.gaignard@st.com>
Define binding for pwm-stm32
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../devicetree/bindings/pwm/pwm-stm32.txt | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
new file mode 100644
index 0000000..819e024
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
@@ -0,0 +1,43 @@
+STMicroelectronics PWM driver bindings for STM32
+--------------------------------------
+
+Must be a child of STM32 multifunctions timer driver
+
+Required parameters:
+- compatible : "st,stm32-pwm1"
+ "st,stm32-pwm2"
+ "st,stm32-pwm3"
+ "st,stm32-pwm4"
+ "st,stm32-pwm5"
+ "st,stm32-pwm8"
+ "st,stm32-pwm9"
+ "st,stm32-pwm10"
+ "st,stm32-pwm11"
+ "st,stm32-pwm12"
+ "st,stm32-pwm13"
+ "st,stm32-pwm14"
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration nodes
+ for PWM module.
+ For Pinctrl properties, please refer to [1].
+
+Optional parameters:
+- st,breakinput-polarity if set enable break input feature.
+ The value define the active polarity:
+ - 0 (active LOW)
+ - 1 (active HIGH)
+
+[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+Example:
+ mfd_timer1: mfdtimer1 at 40010000 {
+ compatible = "st,stm32-mfd-timer1";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <27>;
+
+ pwm1: pwm1 at 40010000 {
+ compatible = "st,stm32-pwm1";
+ };
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH 2/7] add MFD for stm32 timer IP
From: Benjamin Gaignard @ 2016-11-22 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479831207-32699-1-git-send-email-benjamin.gaignard@st.com>
This hardware block could at used at same time for PWM generation
and IIO timer for other IPs like DAC, ADC or other timers.
PWM and IIO timer configuration are mixed in the same registers
so we need a MFD to be able to share those registers.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
drivers/mfd/Kconfig | 10 ++
drivers/mfd/Makefile | 2 +
drivers/mfd/stm32-mfd-timer.c | 236 ++++++++++++++++++++++++++++++++++++
include/linux/mfd/stm32-mfd-timer.h | 78 ++++++++++++
4 files changed, 326 insertions(+)
create mode 100644 drivers/mfd/stm32-mfd-timer.c
create mode 100644 include/linux/mfd/stm32-mfd-timer.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..63aee36 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1607,6 +1607,15 @@ config MFD_STW481X
in various ST Microelectronics and ST-Ericsson embedded
Nomadik series.
+config MFD_STM32_TIMER
+ tristate "Support for STM32 multifunctions timer"
+ select MFD_CORE
+ select REGMAP
+ depends on ARCH_STM32
+ depends on OF
+ help
+ Select multifunction driver (pwm, IIO trigger) for stm32 timers
+
menu "Multimedia Capabilities Port drivers"
depends on ARCH_SA1100
@@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
on the ARM Ltd. Versatile Express board.
endmenu
+
endif
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..b348c3e 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
+
+obj-$(CONFIG_MFD_STM32_TIMER) += stm32-mfd-timer.o
diff --git a/drivers/mfd/stm32-mfd-timer.c b/drivers/mfd/stm32-mfd-timer.c
new file mode 100644
index 0000000..67e7db3
--- /dev/null
+++ b/drivers/mfd/stm32-mfd-timer.c
@@ -0,0 +1,236 @@
+/*
+ * stm32-timer.c
+ *
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <linux/mfd/stm32-mfd-timer.h>
+
+static const struct stm32_mfd_timer_cfg mfd_cells_cfg[] = {
+ {
+ .pwm_name = "pwm1",
+ .pwm_compatible = "st,stm32-pwm1",
+ .trigger_name = "iiotimer1",
+ .trigger_compatible = "st,stm32-iio-timer1",
+ },
+ {
+ .pwm_name = "pwm2",
+ .pwm_compatible = "st,stm32-pwm2",
+ .trigger_name = "iiotimer2",
+ .trigger_compatible = "st,stm32-iio-timer2",
+ },
+ {
+ .pwm_name = "pwm3",
+ .pwm_compatible = "st,stm32-pwm3",
+ .trigger_name = "iiotimer3",
+ .trigger_compatible = "st,stm32-iio-timer3",
+ },
+ {
+ .pwm_name = "pwm4",
+ .pwm_compatible = "st,stm32-pwm4",
+ .trigger_name = "iiotimer4",
+ .trigger_compatible = "st,stm32-iio-timer4",
+ },
+ {
+ .pwm_name = "pwm5",
+ .pwm_compatible = "st,stm32-pwm5",
+ .trigger_name = "iiotimer5",
+ .trigger_compatible = "st,stm32-iio-timer5",
+ },
+ {
+ .trigger_name = "iiotimer6",
+ .trigger_compatible = "st,stm32-iio-timer6",
+ },
+ {
+ .trigger_name = "iiotimer7",
+ .trigger_compatible = "st,stm32-iio-timer7",
+ },
+ {
+ .pwm_name = "pwm8",
+ .pwm_compatible = "st,stm32-pwm8",
+ .trigger_name = "iiotimer8",
+ .trigger_compatible = "st,stm32-iio-timer8",
+ },
+ {
+ .pwm_name = "pwm9",
+ .pwm_compatible = "st,stm32-pwm9",
+ .trigger_name = "iiotimer9",
+ .trigger_compatible = "st,stm32-iio-timer9",
+ },
+ {
+ .pwm_name = "pwm10",
+ .pwm_compatible = "st,stm32-pwm10",
+ },
+ {
+ .pwm_name = "pwm11",
+ .pwm_compatible = "st,stm32-pwm11",
+ },
+ {
+ .pwm_name = "pwm12",
+ .pwm_compatible = "st,stm32-pwm12",
+ .trigger_name = "iiotimer12",
+ .trigger_compatible = "st,stm32-iio-timer12",
+ },
+ {
+ .pwm_name = "pwm13",
+ .pwm_compatible = "st,stm32-pwm13",
+ },
+ {
+ .pwm_name = "pwm14",
+ .pwm_compatible = "st,stm32-pwm14",
+ },
+};
+
+static const struct of_device_id stm32_timer_of_match[] = {
+ {
+ .compatible = "st,stm32-mfd-timer1",
+ .data = &mfd_cells_cfg[0],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer2",
+ .data = &mfd_cells_cfg[1],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer3",
+ .data = &mfd_cells_cfg[2],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer4",
+ .data = &mfd_cells_cfg[3],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer5",
+ .data = &mfd_cells_cfg[4],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer6",
+ .data = &mfd_cells_cfg[5],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer7",
+ .data = &mfd_cells_cfg[6],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer8",
+ .data = &mfd_cells_cfg[7],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer9",
+ .data = &mfd_cells_cfg[8],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer10",
+ .data = &mfd_cells_cfg[9],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer11",
+ .data = &mfd_cells_cfg[10],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer12",
+ .data = &mfd_cells_cfg[11],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer13",
+ .data = &mfd_cells_cfg[12],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer14",
+ .data = &mfd_cells_cfg[13],
+ },
+};
+
+static const struct regmap_config stm32_timer_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = sizeof(u32),
+ .max_register = 0x400,
+ .fast_io = true,
+};
+
+static int stm32_mfd_timer_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct stm32_mfd_timer_dev *mfd;
+ struct resource *res;
+ int ret, nb_cells = 0;
+ struct mfd_cell *cell = NULL;
+ void __iomem *mmio;
+
+ mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
+ if (!mfd)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOMEM;
+
+ mmio = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mmio))
+ return PTR_ERR(mmio);
+
+ mfd->regmap = devm_regmap_init_mmio_clk(dev, "mfd_timer_clk", mmio,
+ &stm32_timer_regmap_cfg);
+ if (IS_ERR(mfd->regmap))
+ return PTR_ERR(mfd->regmap);
+
+ mfd->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(mfd->clk))
+ return PTR_ERR(mfd->clk);
+
+ mfd->irq = platform_get_irq(pdev, 0);
+ if (mfd->irq < 0)
+ return -EINVAL;
+
+ /* populate data structure depending on compatibility */
+ if (!of_match_node(stm32_timer_of_match, np)->data)
+ return -EINVAL;
+
+ mfd->cfg =
+ (struct stm32_mfd_timer_cfg *)of_match_node(stm32_timer_of_match, np)->data;
+
+ if (mfd->cfg->pwm_name && mfd->cfg->pwm_compatible) {
+ cell = &mfd->cells[nb_cells++];
+ cell->name = mfd->cfg->pwm_name;
+ cell->of_compatible = mfd->cfg->pwm_compatible;
+ cell->platform_data = mfd;
+ cell->pdata_size = sizeof(*mfd);
+ }
+
+ if (mfd->cfg->trigger_name && mfd->cfg->trigger_compatible) {
+ cell = &mfd->cells[nb_cells++];
+ cell->name = mfd->cfg->trigger_name;
+ cell->of_compatible = mfd->cfg->trigger_compatible;
+ cell->platform_data = mfd;
+ cell->pdata_size = sizeof(*mfd);
+ }
+
+ ret = devm_mfd_add_devices(&pdev->dev, pdev->id, mfd->cells,
+ nb_cells, NULL, 0, NULL);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, mfd);
+
+ return 0;
+}
+
+static struct platform_driver stm32_mfd_timer_driver = {
+ .probe = stm32_mfd_timer_probe,
+ .driver = {
+ .name = "stm32-mfd-timer",
+ .of_match_table = stm32_timer_of_match,
+ },
+};
+module_platform_driver(stm32_mfd_timer_driver);
+
+MODULE_DESCRIPTION("STMicroelectronics STM32 Timer MFD");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/stm32-mfd-timer.h b/include/linux/mfd/stm32-mfd-timer.h
new file mode 100644
index 0000000..4a79c22
--- /dev/null
+++ b/include/linux/mfd/stm32-mfd-timer.h
@@ -0,0 +1,78 @@
+/*
+ * stm32-mfd-timer.h
+ *
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _LINUX_MFD_STM32_TIMER_H_
+#define _LINUX_MFD_STM32_TIMER_H_
+
+#include <linux/clk.h>
+#include <linux/mfd/core.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define TIM_CR1 0x00 /* Control Register 1 */
+#define TIM_CR2 0x04 /* Control Register 2 */
+#define TIM_SMCR 0x08 /* Slave mode control reg */
+#define TIM_DIER 0x0C /* DMA/interrupt register */
+#define TIM_SR 0x10 /* Status register */
+#define TIM_EGR 0x14 /* Event Generation Reg */
+#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
+#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
+#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
+#define TIM_PSC 0x28 /* Prescaler */
+#define TIM_ARR 0x2c /* Auto-Reload Register */
+#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
+#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
+#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
+#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
+#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
+
+#define TIM_CR1_CEN BIT(0) /* Counter Enable */
+#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
+#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
+#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
+#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
+#define TIM_DIER_UIE BIT(0) /* Update interrupt */
+#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
+#define TIM_EGR_UG BIT(0) /* Update Generation */
+#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
+#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
+#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
+#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
+#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
+#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
+#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
+#define TIM_BDTR_BKE BIT(12) /* Break input enable */
+#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
+#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
+#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
+
+#define STM32_TIMER_CELLS 2
+#define MAX_TIM_PSC 0xFFFF
+
+struct stm32_mfd_timer_cfg {
+ const char *pwm_name;
+ const char *pwm_compatible;
+ const char *trigger_name;
+ const char *trigger_compatible;
+};
+
+struct stm32_mfd_timer_dev {
+ /* Device data */
+ struct device *dev;
+ struct clk *clk;
+ int irq;
+
+ /* Registers mapping */
+ struct regmap *regmap;
+
+ /* Private data */
+ struct mfd_cell cells[STM32_TIMER_CELLS];
+ struct stm32_mfd_timer_cfg *cfg;
+};
+
+#endif
--
1.9.1
^ permalink raw reply related
* [PATCH 1/7] add binding for stm32 multifunctions timer driver
From: Benjamin Gaignard @ 2016-11-22 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479831207-32699-1-git-send-email-benjamin.gaignard@st.com>
Add bindings information for stm32 timer MFD
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../devicetree/bindings/mfd/stm32-timer.txt | 53 ++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timer.txt
diff --git a/Documentation/devicetree/bindings/mfd/stm32-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
new file mode 100644
index 0000000..3cefce1
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
@@ -0,0 +1,53 @@
+STM32 multifunctions timer driver
+
+stm32 timer MFD allow to handle at the same time pwm and IIO timer devices
+
+Required parameters:
+- compatible: must be one of the follow value:
+ "st,stm32-mfd-timer1"
+ "st,stm32-mfd-timer2"
+ "st,stm32-mfd-timer3"
+ "st,stm32-mfd-timer4"
+ "st,stm32-mfd-timer5"
+ "st,stm32-mfd-timer6"
+ "st,stm32-mfd-timer7"
+ "st,stm32-mfd-timer8"
+ "st,stm32-mfd-timer9"
+ "st,stm32-mfd-timer10"
+ "st,stm32-mfd-timer11"
+ "st,stm32-mfd-timer12"
+ "st,stm32-mfd-timer13"
+ "st,stm32-mfd-timer14"
+
+- reg : Physical base address and length of the controller's
+ registers.
+- clock-names: Set to "mfd_timer_clk".
+- clocks: Phandle of the clock used by the timer module.
+ For Clk properties, please refer to [1].
+- interrupts : Reference to the timer interrupt
+
+Optional parameters:
+- resets : Reference to a reset controller asserting the timer
+
+Optional subnodes:
+- pwm: See Documentation/devicetree/bindings/pwm/pwm-stm32.txt
+- iiotimer: See Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Example:
+ mfd_timer1: mfdtimer1 at 40010000 {
+ compatible = "st,stm32-mfd-timer1";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <27>;
+
+ pwm1: pwm1 at 40010000 {
+ compatible = "st,stm32-pwm1";
+ };
+
+ iiotimer1: iiotimer1 at 40010000 {
+ compatible = "st,stm32-iio-timer1";
+ };
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH 0/7] Add pwm and IIO timer drivers for stm32
From: Benjamin Gaignard @ 2016-11-22 16:13 UTC (permalink / raw)
To: linux-arm-kernel
The following patches enable pwm and IIO Timer features for stm32 platforms.
Those two features are mixed into the registers of the same hardware block
(named timer) which lead to introduce a multifunctions driver on the top to
be able to share the registers.
In stm32 14 instances of timer hardware block exist, even if they all have
the same register mapping they could have a different number of pwm channels
and/or different triggers capabilities. To keep the code as simple as possible
we use compatible and platform_data to distinguish them.
The MFD (stm32-mfd-timer.c) takes care of clock, interrupt and register mapping
by using regmap. stm32_mfd_timer_dev structure is provided to its children to
share those information.
PWM driver is implemented into pwm-stm32.c. Depending of the instance we may
have up to 4 channels, sometime with complementary outputs or 32 bits counter
instead of 16 bits. Some hardware blocks may also have a break input function
which allows to stop pwm depending of a level, defined in devicetree, on an
external pin.
IIO timer driver (stm32-iio-timer.c and stm32-iio-timers.h) define a list of
hardware triggers usable by hardware blocks like ADC, DAC or other timers.
The matrix of possible connections between blocks is quite complex so we use
trigger names and is_stm32_iio_timer_trigger() function to be sure that
triggers are valid and configure the IPs.
Timer hardware blocks can configure (through "master_mode" IIO device attribute)
which internal signal (counter enable, reset, comparison block, etc...) is
used to generate the trigger.
By using "slave_mode" IIO device attribute timer can also configure on which
event (level, rising edge) of the block is enabled.
Since we can use trigger from one hardware to control an other block, we can
use a pwm to control an other one. The following example shows how to configure
pwm1 and pwm3 to make pwm3 generate pulse only when pwm1 pulse level is high.
/sys/bus/iio/devices # ls
iio:device0 iio:device1 trigger0 trigger1
configure timer1 to use pwm1 channel 0 as output trigger
/sys/bus/iio/devices # echo 4 > iio\:device0/master_mode
configure timer3 to enable only when input is high
/sys/bus/iio/devices # echo 5 > iio\:device1/slave_mode
/sys/bus/iio/devices # cat trigger0/name
tim1_trgo
configure timer2 to use timer1 trigger is input
/sys/bus/iio/devices # echo "tim1_trgo" > iio\:device1/trigger/current_trigger
configure pwm3 channel 0 to generate a signal with a period of 100ms and a
duty cycle of 50%
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 0 > export
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 100000000 > pwm0/period
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 50000000 > pwm0/duty_cycle
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 1 > pwm0/enable
here pwm3 channel 0, as expected, doesn't start because has to be triggered by
pwm1 channel 0
configure pwm1 channel 0 to generate a signal with a period of 1s and a
duty cycle of 50%
/sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 0 > export
/sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 1000000000 > pwm0/period
/sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 500000000 > pwm0/duty_cycle
/sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 1 > pwm0/enable
finally pwm1 starts and pwm3 only generates pulse when pwm1 signal is high
An other example to use a timer as source of clock for another device.
Here timer1 is used a source clock for pwm3:
/sys/bus/iio/devices # echo 100000 > trigger0/sampling_frequency
/sys/bus/iio/devices # echo tim1_trgo > iio\:device1/trigger/current_trigger
/sys/bus/iio/devices # echo 7 > iio\:device1/slave_mode
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 0 > export
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 1000000 > pwm0/period
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 500000 > pwm0/duty_cycle
/sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 1 > pwm0/enable
Benjamin Gaignard (7):
add binding for stm32 multifunctions timer driver
add MFD for stm32 timer IP
add pwm-stm32 DT bindings
add pwm driver for stm32 plaftorm
add bindings for stm32 IIO timer drivers
add STM32 IIO timer driver
add stm32 multi-functions timer driver in DT
.../bindings/iio/timer/stm32-iio-timer.txt | 33 +
.../devicetree/bindings/mfd/stm32-timer.txt | 53 ++
.../devicetree/bindings/pwm/pwm-stm32.txt | 43 ++
arch/arm/boot/dts/stm32f429.dtsi | 246 +++++++
arch/arm/boot/dts/stm32f469-disco.dts | 29 +
drivers/iio/Kconfig | 2 +-
drivers/iio/Makefile | 1 +
drivers/iio/timer/Kconfig | 15 +
drivers/iio/timer/Makefile | 1 +
drivers/iio/timer/stm32-iio-timer.c | 766 +++++++++++++++++++++
drivers/iio/trigger/Kconfig | 1 -
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 2 +
drivers/mfd/stm32-mfd-timer.c | 236 +++++++
drivers/pwm/Kconfig | 8 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-stm32.c | 358 ++++++++++
include/linux/iio/timer/stm32-iio-timers.h | 25 +
include/linux/mfd/stm32-mfd-timer.h | 78 +++
19 files changed, 1906 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timer.txt
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
create mode 100644 drivers/iio/timer/Kconfig
create mode 100644 drivers/iio/timer/Makefile
create mode 100644 drivers/iio/timer/stm32-iio-timer.c
create mode 100644 drivers/mfd/stm32-mfd-timer.c
create mode 100644 drivers/pwm/pwm-stm32.c
create mode 100644 include/linux/iio/timer/stm32-iio-timers.h
create mode 100644 include/linux/mfd/stm32-mfd-timer.h
--
1.9.1
^ permalink raw reply
* [PATCH net-next] net: mvneta: Only disable mvneta_bm for 64-bits
From: David Miller @ 2016-11-22 16:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122160037.14400-1-gregory.clement@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Tue, 22 Nov 2016 17:00:37 +0100
> Actually only the mvneta_bm support is not 64-bits compatible.
> The mvneta code itself can run on 64-bits architecture.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
No it cannot, it emits warnings because it casts pointers to and
from 32-bit integers.
I'm not applying this.
drivers/net/ethernet/marvell/mvneta.c: In function ?mvneta_rx_refill?:
drivers/net/ethernet/marvell/mvneta.c:1802:42: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
^
drivers/net/ethernet/marvell/mvneta.c: In function ?mvneta_rxq_drop_pkts?:
drivers/net/ethernet/marvell/mvneta.c:1864:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
void *data = (void *)rx_desc->buf_cookie;
^
drivers/net/ethernet/marvell/mvneta.c: In function ?mvneta_rx_swbm?:
drivers/net/ethernet/marvell/mvneta.c:1902:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
data = (unsigned char *)rx_desc->buf_cookie;
^
drivers/net/ethernet/marvell/mvneta.c: In function ?mvneta_rx_hwbm?:
drivers/net/ethernet/marvell/mvneta.c:2023:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
data = (unsigned char *)rx_desc->buf_cookie;
^
^ permalink raw reply
* [PATCH] net: mvneta: Only disable mvneta_bm for 64-bits
From: Gregory CLEMENT @ 2016-11-22 16:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122153848.13071-1-gregory.clement@free-electrons.com>
Hi,
On mar., nov. 22 2016, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Actually only the mvneta_bm support is not 64-bits compatible.
> The mvneta code itself can run on 64-bits architecture.
I have just realized that my topic prefix was wrong (net-next was
missing), I am send a new email with the correct prefix.
Sorry for the noise.
Gregory
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> drivers/net/ethernet/marvell/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig
> index 66fd9dbb2ca7..2ccea9dd9248 100644
> --- a/drivers/net/ethernet/marvell/Kconfig
> +++ b/drivers/net/ethernet/marvell/Kconfig
> @@ -44,6 +44,7 @@ config MVMDIO
> config MVNETA_BM_ENABLE
> tristate "Marvell Armada 38x/XP network interface BM support"
> depends on MVNETA
> + depends on !64BIT
> ---help---
> This driver supports auxiliary block of the network
> interface units in the Marvell ARMADA XP and ARMADA 38x SoC
> @@ -58,7 +59,6 @@ config MVNETA
> tristate "Marvell Armada 370/38x/XP network interface support"
> depends on PLAT_ORION || COMPILE_TEST
> depends on HAS_DMA
> - depends on !64BIT
> select MVMDIO
> select FIXED_PHY
> ---help---
> @@ -71,6 +71,7 @@ config MVNETA
>
> config MVNETA_BM
> tristate
> + depends on !64BIT
> default y if MVNETA=y && MVNETA_BM_ENABLE!=n
> default MVNETA_BM_ENABLE
> select HWBM
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH net-next] net: mvneta: Only disable mvneta_bm for 64-bits
From: Gregory CLEMENT @ 2016-11-22 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig
index 66fd9dbb2ca7..2ccea9dd9248 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -44,6 +44,7 @@ config MVMDIO
config MVNETA_BM_ENABLE
tristate "Marvell Armada 38x/XP network interface BM support"
depends on MVNETA
+ depends on !64BIT
---help---
This driver supports auxiliary block of the network
interface units in the Marvell ARMADA XP and ARMADA 38x SoC
@@ -58,7 +59,6 @@ config MVNETA
tristate "Marvell Armada 370/38x/XP network interface support"
depends on PLAT_ORION || COMPILE_TEST
depends on HAS_DMA
- depends on !64BIT
select MVMDIO
select FIXED_PHY
---help---
@@ -71,6 +71,7 @@ config MVNETA
config MVNETA_BM
tristate
+ depends on !64BIT
default y if MVNETA=y && MVNETA_BM_ENABLE!=n
default MVNETA_BM_ENABLE
select HWBM
--
2.10.2
^ permalink raw reply related
* [PATCH] dt-bindings: mfd: Improve readability for TPS65217 interrupt sources
From: Lee Jones @ 2016-11-22 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122155759.GG10134@dell.home>
On Tue, 22 Nov 2016, Lee Jones wrote:
> On Mon, 21 Nov 2016, Milo Kim wrote:
>
> > AC and USB interrupts are related with external power input.
> > PB interrupt means push button pressed or released event.
> > Use better human readable definitions.
> >
> > Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
> > ---
> > arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++--
> > include/dt-bindings/mfd/tps65217.h | 6 +++---
> > 2 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
> > index dc561d5..1848d58 100644
> > --- a/arch/arm/boot/dts/am335x-bone-common.dtsi
> > +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
> > @@ -319,13 +319,13 @@
> > ti,pmic-shutdown-controller;
> >
> > charger {
> > - interrupts = <TPS65217_IRQ_AC>, <TPS65217_IRQ_USB>;
> > + interrupts = <TPS65217_IRQ_AC_POWER>, <TPS65217_IRQ_USB_POWER>;
> > interrupts-names = "AC", "USB";
> > status = "okay";
> > };
> >
> > pwrbutton {
> > - interrupts = <TPS65217_IRQ_PB>;
> > + interrupts = <TPS65217_IRQ_PUSHBUTTON>;
>
> Push button or power button?
>
> > status = "okay";
> > };
> >
> > diff --git a/include/dt-bindings/mfd/tps65217.h b/include/dt-bindings/mfd/tps65217.h
> > index cafb9e6..0293fdd 100644
> > --- a/include/dt-bindings/mfd/tps65217.h
> > +++ b/include/dt-bindings/mfd/tps65217.h
> > @@ -19,8 +19,8 @@
> > #ifndef __DT_BINDINGS_TPS65217_H__
> > #define __DT_BINDINGS_TPS65217_H__
> >
> > -#define TPS65217_IRQ_USB 0
> > -#define TPS65217_IRQ_AC 1
> > -#define TPS65217_IRQ_PB 2
> > +#define TPS65217_IRQ_USB_POWER 0 /* USB power state change */
> > +#define TPS65217_IRQ_AC_POWER 1 /* AC power state change */
> > +#define TPS65217_IRQ_PUSHBUTTON 2 /* Push button state change */
>
> This changes the ABI.
>
> It will require a DT Ack.
Tell a lie. Sorry, I was getting false positives from my grep. It
looks like you use the same scheme from within include/linux. I
suggest that you probable don't want to do that.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 3/3] arm64: dts: sunxi: enable EHCI1, OHCI1 and USB PHY nodes in Pine64
From: Icenowy Zheng @ 2016-11-22 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122155831.8724-1-icenowy@aosc.xyz>
Pine64 have two USB Type-A ports, which are wired to the two ports of
A64 USB PHY, and the lower port is the EHCI/OHCI1 port.
Enable the necessary nodes to enable the lower USB port to work.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes since v1:
- Sort the nodes.
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c32ebc7..f9a11e6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -57,6 +57,10 @@
};
};
+&ehci1 {
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -67,8 +71,16 @@
bias-pull-up;
};
+&ohci1 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+
+&usbphy {
+ status = "okay";
+};
--
2.10.2
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: sunxi: sort the nodes in sun50i-a64-pine64.dts
From: Icenowy Zheng @ 2016-11-22 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122155831.8724-1-icenowy@aosc.xyz>
In this dts file, uart0 node is put before i2c1.
Move the uart0 node to the end to satisfy alphebetical order.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
New patch added into v2.
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 4709590..c32ebc7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -57,12 +57,6 @@
};
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
-};
-
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -72,3 +66,9 @@
&i2c1_pins {
bias-pull-up;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--
2.10.2
^ permalink raw reply related
* [PATCH v2 1/3] arm64: dts: add USB1-related nodes of Allwinner A64
From: Icenowy Zheng @ 2016-11-22 15:58 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
PHY device which have two ports. One of the port is wired to both a HCI
USB controller and the OTG controller, which is currently not supported.
The another one is only wired to a HCI controller, and the device node of
OHCI/EHCI controller of the port can be added now.
Also the A64 USB PHY device node is also added for the HCI controllers to
work.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes since v1:
- Remove manual CLK_USB_OHCI0 gate, as it's dealed by ccu driver now.
- Sort the nodes and fixed {e,o}hci1 regs.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 44 +++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 3d70be3..2572dd6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -122,6 +122,50 @@
#size-cells = <1>;
ranges;
+ usbphy: phy at 01c19400 {
+ compatible = "allwinner,sun50i-a64-usb-phy";
+ reg = <0x01c19400 0x14>,
+ <0x01c1b800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu1";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>;
+ clock-names = "usb0_phy",
+ "usb1_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>;
+ reset-names = "usb0_reset",
+ "usb1_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ohci1: usb at 01c1b400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb at 01c1b000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
ccu: clock at 01c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
--
2.10.2
^ permalink raw reply related
* [PATCH] dt-bindings: mfd: Improve readability for TPS65217 interrupt sources
From: Lee Jones @ 2016-11-22 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121131515.8040-1-woogyom.kim@gmail.com>
On Mon, 21 Nov 2016, Milo Kim wrote:
> AC and USB interrupts are related with external power input.
> PB interrupt means push button pressed or released event.
> Use better human readable definitions.
>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
> ---
> arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++--
> include/dt-bindings/mfd/tps65217.h | 6 +++---
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
> index dc561d5..1848d58 100644
> --- a/arch/arm/boot/dts/am335x-bone-common.dtsi
> +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
> @@ -319,13 +319,13 @@
> ti,pmic-shutdown-controller;
>
> charger {
> - interrupts = <TPS65217_IRQ_AC>, <TPS65217_IRQ_USB>;
> + interrupts = <TPS65217_IRQ_AC_POWER>, <TPS65217_IRQ_USB_POWER>;
> interrupts-names = "AC", "USB";
> status = "okay";
> };
>
> pwrbutton {
> - interrupts = <TPS65217_IRQ_PB>;
> + interrupts = <TPS65217_IRQ_PUSHBUTTON>;
Push button or power button?
> status = "okay";
> };
>
> diff --git a/include/dt-bindings/mfd/tps65217.h b/include/dt-bindings/mfd/tps65217.h
> index cafb9e6..0293fdd 100644
> --- a/include/dt-bindings/mfd/tps65217.h
> +++ b/include/dt-bindings/mfd/tps65217.h
> @@ -19,8 +19,8 @@
> #ifndef __DT_BINDINGS_TPS65217_H__
> #define __DT_BINDINGS_TPS65217_H__
>
> -#define TPS65217_IRQ_USB 0
> -#define TPS65217_IRQ_AC 1
> -#define TPS65217_IRQ_PB 2
> +#define TPS65217_IRQ_USB_POWER 0 /* USB power state change */
> +#define TPS65217_IRQ_AC_POWER 1 /* AC power state change */
> +#define TPS65217_IRQ_PUSHBUTTON 2 /* Push button state change */
This changes the ABI.
It will require a DT Ack.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i
From: Maxime Ripard @ 2016-11-22 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479638740-20520-4-git-send-email-hao5781286@gmail.com>
Hi,
On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
>
> Accroding to sun6i dma driver, i think ,if the client
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
>
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
> drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
> static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
> {
> if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> - (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> + (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
> return -EINVAL;
>
> return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
> {
> struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>
> + if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> + chan->device->src_addr_widths) {
Using an and operator would make this more obvious.
> + dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> + return -EINVAL;
> + }
> +
> + if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
> + chan->device->dst_addr_widths) {
> + dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> + return -EINVAL;
> + }
> +
And I really think both these tests should be in
dmaengine_slave_config directly. There's nothing special about those
tests, and they apply to all the DMA drivers.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] drm/sun4i: Fix a return value in case of error
From: Maxime Ripard @ 2016-11-22 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118181847.8436-1-christophe.jaillet@wanadoo.fr>
On Fri, Nov 18, 2016 at 07:18:47PM +0100, Christophe JAILLET wrote:
> If 'sun4i_backend_drm_format_to_layer()' does not return 0, then 'val' is
> left unmodified.
> As it is not initialized either, the return value can be anything.
>
> It is likely that returning the error code was expected here.
>
> As the only caller of 'sun4i_backend_update_layer_formats()' does not check
> the return value, this fix is purely theorical.
>
> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 1/3] of: base: add support to get machine compatible string
From: Sudeep Holla @ 2016-11-22 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <67a3c2c7-0cb9-9764-2710-6ee66fc4dde4@ti.com>
Hi Sekhar,
On 22/11/16 15:06, Sekhar Nori wrote:
> Hi Sudeep,
>
> On Tuesday 22 November 2016 04:23 PM, Sudeep Holla wrote:
>>
>>
>> On 22/11/16 10:41, Bartosz Golaszewski wrote:
>>> Add a function allowing to retrieve the compatible string of the root
>>> node of the device tree.
>>>
>>
>> Rob has queued [1] and it's in -next today. You can reuse that if you
>> are planning to target this for v4.11 or just use open coding in your
>> driver for v4.10 and target this move for v4.11 to avoid cross tree
>> dependencies as I already mentioned in your previous thread.
>
> I dont have your original patch in my mailbox, but I wonder if
> returning a pointer to property string for a node whose reference has
> already been released is safe to do? Probably not an issue for the root
> node, but still feels counter-intuitive.
>
I am not sure if I understand the issue here. Are you referring a case
where of_root is freed ?
Also I have seen drivers today just using this pointer directly, but
it's better to copy the string(I just saw this done in one case)
> This is the code for reference:
>
> +int of_machine_get_model_name(const char **model)
> +{
> + int error;
> +
> + if (!of_node_get(of_root))
> + return -EINVAL;
> +
> + error = of_property_read_string(of_root, "model", model);
> + if (error)
> + error = of_property_read_string_index(of_root, "compatible",
> + 0, model);
> + of_node_put(of_root);
> +
> + return error;
> +}
> +EXPORT_SYMBOL(of_machine_get_model_name);
>
> Thanks,
> Sekhar
>
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v2] ARM: dts: AM571x-IDK Initial Support
From: Rob Herring @ 2016-11-22 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122041732.8385-1-lokeshvutla@ti.com>
On Mon, Nov 21, 2016 at 10:17 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> From: Schuyler Patton <spatton@ti.com>
>
> The AM571x-IDK board is a board based on TI's AM5718 SOC
> which has a single core 1.5GHz A15 processor. This board is a
> development platform for the Industrial market with:
> - 1GB of DDR3L
> - Dual 1Gbps Ethernet
> - HDMI,
> - PRU-ICSS
> - uSD
> - 16GB eMMC
> - CAN
> - RS-485
> - PCIe
> - USB3.0
> - Video Input Port
> - Industrial IO port and expansion connector
>
> The link to the data sheet and TRM can be found here:
>
> http://www.ti.com/product/AM5718
>
> Initial support is only for basic peripherals.
>
> Signed-off-by: Schuyler Patton <spatton@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> Cahnges since v1:
> - Dropped "ti,dra722", and "ti,dra72" from compatibles
> - Fixes few node names as suggested by Rob.
> Logs: http://pastebin.ubuntu.com/23515001/
Please add acks when posting new versions.
Rob
^ permalink raw reply
* [RESEND PATCH 2/3] ARM: davinci: hawk: Remove vbus and over current gpios
From: Axel Haslam @ 2016-11-22 15:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cf13650b-1880-7dda-e249-9763bfe3032a@ti.com>
Hi Sekhar
On Tue, Nov 22, 2016 at 11:37 AM, Sekhar Nori <nsekhar@ti.com> wrote:
> On Monday 21 November 2016 10:23 PM, Axel Haslam wrote:
>> The hawk board VBUS is fixed to a 5v source, and the over
>> current pin is actually not connected to the SoC.
>>
>> Do not reseve these gpios for OHCI as they are not related
>> to usb.
>>
>> Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
>
> As discussed over the MMC/SD patches, this patch should be based off the
> hawkboard schematic, not the LCDK schematic.
>
I looked at the hawkboard schematics and they are the same
as the lcdk as far as usb i concerned:
The ohci vbus is fixed to 5v, and the over current pins of the
TPS are not connected. so this patch should be ok for
both the hawk and the lcdk.
Regards
Axel
> Thanks,
> Sekhar
^ permalink raw reply
* [PATCH] net: mvneta: Only disable mvneta_bm for 64-bits
From: Gregory CLEMENT @ 2016-11-22 15:38 UTC (permalink / raw)
To: linux-arm-kernel
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig
index 66fd9dbb2ca7..2ccea9dd9248 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -44,6 +44,7 @@ config MVMDIO
config MVNETA_BM_ENABLE
tristate "Marvell Armada 38x/XP network interface BM support"
depends on MVNETA
+ depends on !64BIT
---help---
This driver supports auxiliary block of the network
interface units in the Marvell ARMADA XP and ARMADA 38x SoC
@@ -58,7 +59,6 @@ config MVNETA
tristate "Marvell Armada 370/38x/XP network interface support"
depends on PLAT_ORION || COMPILE_TEST
depends on HAS_DMA
- depends on !64BIT
select MVMDIO
select FIXED_PHY
---help---
@@ -71,6 +71,7 @@ config MVNETA
config MVNETA_BM
tristate
+ depends on !64BIT
default y if MVNETA=y && MVNETA_BM_ENABLE!=n
default MVNETA_BM_ENABLE
select HWBM
--
2.10.2
^ permalink raw reply related
* [PATCH] drm/sun4i: Only count TCON endpoints as valid outputs
From: Maxime Ripard @ 2016-11-22 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65sorc-Q5c39ZURTAAorvF4ETVW=qj_ue9mUzLei2scJQ@mail.gmail.com>
Hi,
On Fri, Nov 18, 2016 at 10:22:40AM +0800, Chen-Yu Tsai wrote:
> On Fri, Nov 18, 2016 at 3:02 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Wed, Nov 16, 2016 at 05:37:31PM +0800, Chen-Yu Tsai wrote:
> >> The sun4i DRM driver counts the number of endpoints it found and
> >> registers the whole DRM pipeline if any endpoints are found.
> >>
> >> However, if the TCON and its child endpoints (LCD panels, TV encoder,
> >> HDMI encoder, MIPI DSI encoder, etc.) aren't found, that means we
> >> don't have any usable CRTCs, and the display pipeline is incomplete
> >> and useless.
> >
> > If some node set as available is not probed, then yes, it does, but
> > I'm not really sure how it's a problem. Quite the opposite actually.
>
> Actually the problem occurs when the TCON is _not_ available, but
> the other endpoints preceding it are.
By preceding, you mean the display engine or the HDMI or TV encoders?
> >> The debug message "Queued %d outputs on pipeline %d\n" is also telling.
> >>
> >> This patch makes the driver only count enabled TCON endpoints. If
> >> none are found, the DRM pipeline is not used. This avoids screwing
> >> up the simple framebuffer provided by the bootloader in cases where
> >> we aren't able to support the display with the DRM subsystem, due
> >> to lack of panel or bridge drivers, or just lack of progress.
> >
> > The framebuffer is removed only at bind time, which means that all the
> > drivers have probed already. Lack of progress isn't an issue here,
> > since the node simply won't be there, and we wouldn't have it in the
> > component lists. And lack of drivers shouldn't be an issue either,
> > since in order for bind to be called, all the drivers would have
> > gone through their probe.
> >
> > So I'm not really sure what it fixes.
>
> To recap, on sun6i I had enabled the display engine node by default
> in the dtsi, along with the backend and drc. The tcon is disabled
> by default, so it doesn't get added to the list of components.
> The available components get probed, binded, and simplefb gets
> pushed out.
>
> I suppose disabling the display engine by default would be better?
> At least simplefb still works.
Yep, that works for me.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] ARM: davinci_all_defconfig: Enable OHCI as module
From: Sekhar Nori @ 2016-11-22 15:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121170131.30157-1-ahaslam@baylibre.com>
On Monday 21 November 2016 10:31 PM, Axel Haslam wrote:
> Enable the davinci ohci driver as a module for usb
> tested with the omap138-lcdk hawk board.
>
> Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Applied to v4.10/defconfg after dropping "hawk" from commit description.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] boot-wrapper: configure: fix file detection when cross-compiling
From: Andre Przywara @ 2016-11-22 15:15 UTC (permalink / raw)
To: linux-arm-kernel
The autotools documentation states that CHECKFILES cannot be used when
cross-compiling[1], because it's meant to check files in the target
system, not on the build host. When just giving --host on the configure
command line, the script detects cross compilation rather late; and as the
file test just happens to execute earlier, this works anyway.
However if one gives both --host and --build, cross compilation is
detected very early and ./configure complains:
checking for /src/linux-arm64... configure: error: cannot check for file existence when cross compiling
So replace the checkfile macro usage with a simple "test -f" call (which
is the recommended way of checking for files on the build host) and output
proper error messages.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[1] https://www.gnu.org/software/autoconf/manual/autoconf.html#Files
---
configure.ac | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/configure.ac b/configure.ac
index ab8f5b3..e0daec4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -41,12 +41,25 @@ AC_ARG_WITH([dtb],
[KERN_DTB="$withval"])
# Ensure that the user has provided us with a sane kernel dir.
-m4_define([CHECKFILES], [KERN_DIR,
- KERN_DTB,
- KERN_IMAGE])
+if ! test -d $KERN_DIR; then
+ AC_MSG_ERROR([Could not find Linux kernel dir $KERN_DIR.])
+fi
+
+AC_MSG_CHECKING([whether DTB file exists])
+if ! test -f $KERN_DTB; then
+ AC_MSG_RESULT([no])
+ AC_MSG_ERROR([You need to specify a valid DTB file, could not find: $KERN_DTB])
+else
+ AC_MSG_RESULT([yes])
+fi
-m4_foreach([checkfile], [CHECKFILES],
- [AC_CHECK_FILE([$checkfile], [], AC_MSG_ERROR([No such file or directory: $checkfile]))])
+AC_MSG_CHECKING([whether kernel image exists])
+if ! test -f $KERN_IMAGE; then
+ AC_MSG_RESULT([no])
+ AC_MSG_ERROR([You need to compile a kernel first, could not find: $KERN_IMAGE])
+else
+ AC_MSG_RESULT([yes])
+fi
AC_SUBST([KERNEL_IMAGE], [$KERN_IMAGE])
AC_SUBST([KERNEL_DTB], [$KERN_DTB])
--
2.9.0
^ permalink raw reply related
* [PATCH v2 4/4] Explicitly clean linux-system.axf and xen-system.axf
From: Andre Przywara @ 2016-11-22 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122150917.16524-1-andre.przywara@arm.com>
From: Christoffer Dall <christoffer.dall@linaro.org>
When doing a make clean, only the output image currently configured to
build is being removed. However, one would expect all build artifacts
to be removed when doing a 'make clean' and when switching between Xen
and Linux builds, it is easy to accidentally run an older build than
intended. Simply hardcode the axf image file names.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.am b/Makefile.am
index db97f9c..506a1d9 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -130,7 +130,7 @@ OFILES += $(addprefix $(ARCH_SRC),boot.o stack.o $(BOOTMETHOD) utils.o)
all: $(IMAGE)
-CLEANFILES = $(IMAGE) $(OFILES) model.lds fdt.dtb
+CLEANFILES = $(IMAGE) linux-system.axf xen-system.axf $(OFILES) model.lds fdt.dtb
$(IMAGE): $(OFILES) model.lds fdt.dtb $(KERNEL_IMAGE) $(FILESYSTEM) $(XEN_IMAGE)
$(LD) $(LDFLAGS) $(OFILES) -o $@ --script=model.lds
--
2.9.0
^ permalink raw reply related
* [PATCH v2 3/4] Xen: Select correct dom0 console
From: Andre Przywara @ 2016-11-22 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122150917.16524-1-andre.przywara@arm.com>
From: Ian Campbell <ian.campbell@citrix.com>
If Xen is enabled, tell Dom0 to use the 'hvc0' console, and fall back to
the usual ttyAMA0 otherwise.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
configure.ac | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index aff4aad..c959ab8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -92,7 +92,8 @@ AC_ARG_WITH([initrd],
AC_SUBST([FILESYSTEM], [$USE_INITRD])
AM_CONDITIONAL([INITRD], [test "x$USE_INITRD" != "x"])
-C_CMDLINE="console=ttyAMA0 earlyprintk=pl011,0x1c090000"
+AS_IF([test "x$X_IMAGE" = "x"],[C_CONSOLE="ttyAMA0"],[C_CONSOLE="hvc0"])
+C_CMDLINE="console=$C_CONSOLE earlyprintk=pl011,0x1c090000"
AC_ARG_WITH([cmdline],
AS_HELP_STRING([--with-cmdline], [set a command line for the kernel]),
[C_CMDLINE=$withval])
--
2.9.0
^ permalink raw reply related
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