* [PATCH v17 3/4] arm64: dts: mt8173: Add GCE node
From: HS Liao @ 2016-11-23 8:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479890343-4979-1-git-send-email-hs.liao@mediatek.com>
This patch adds the device node of the GCE hardware for CMDQ module.
Signed-off-by: HS Liao <hs.liao@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 1c71e25..d50c044 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -414,6 +414,16 @@
status = "disabled";
};
+ gce: gce at 10212000 {
+ compatible = "mediatek,mt8173-gce";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+
+ #mbox-cells = <2>;
+ };
+
mipi_tx0: mipi-dphy at 10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
--
1.9.1
^ permalink raw reply related
* [PATCH v17 4/4] soc: mediatek: Add Mediatek CMDQ helper
From: HS Liao @ 2016-11-23 8:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479890343-4979-1-git-send-email-hs.liao@mediatek.com>
Add Mediatek CMDQ helper to create CMDQ packet and assemble GCE op code.
Signed-off-by: HS Liao <hs.liao@mediatek.com>
---
drivers/soc/mediatek/Kconfig | 11 ++
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-cmdq-helper.c | 310 +++++++++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 174 ++++++++++++++++++
4 files changed, 496 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-cmdq-helper.c
create mode 100644 include/linux/soc/mediatek/mtk-cmdq.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..94651ed 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -1,6 +1,17 @@
#
# MediaTek SoC drivers
#
+config MTK_CMDQ
+ bool "MediaTek CMDQ Support"
+ depends on ARM64 && ( ARCH_MEDIATEK || COMPILE_TEST )
+ select MTK_CMDQ_MBOX
+ select MTK_INFRACFG
+ help
+ Say yes here to add support for the MediaTek Command Queue (CMDQ)
+ driver. The CMDQ is used to help read/write registers with critical
+ time limitation, such as updating display configuration during the
+ vblank.
+
config MTK_INFRACFG
bool "MediaTek INFRACFG Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 12998b0..64ce5ee 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
new file mode 100644
index 0000000..7809e65
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/completion.h>
+#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#define CMDQ_SUBSYS_SHIFT 16
+#define CMDQ_ARG_A_WRITE_MASK 0xffff
+#define CMDQ_WRITE_ENABLE_MASK BIT(0)
+#define CMDQ_EOC_IRQ_EN BIT(0)
+#define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
+ << 32 | CMDQ_EOC_IRQ_EN)
+
+struct cmdq_subsys {
+ u32 base;
+ int id;
+};
+
+static const struct cmdq_subsys gce_subsys[] = {
+ {0x1400, 1},
+ {0x1401, 2},
+ {0x1402, 3},
+};
+
+static int cmdq_subsys_base_to_id(u32 base)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gce_subsys); i++)
+ if (gce_subsys[i].base == base)
+ return gce_subsys[i].id;
+ return -EFAULT;
+}
+
+static int cmdq_pkt_realloc_cmd_buffer(struct cmdq_pkt *pkt, size_t size)
+{
+ void *new_buf;
+
+ new_buf = krealloc(pkt->va_base, size, GFP_KERNEL | __GFP_ZERO);
+ if (!new_buf)
+ return -ENOMEM;
+ pkt->va_base = new_buf;
+ pkt->buf_size = size;
+ return 0;
+}
+
+struct cmdq_base *cmdq_register_device(struct device *dev)
+{
+ struct cmdq_base *cmdq_base;
+ struct resource res;
+ int subsys;
+ u32 base;
+
+ if (of_address_to_resource(dev->of_node, 0, &res))
+ return NULL;
+ base = (u32)res.start;
+
+ subsys = cmdq_subsys_base_to_id(base >> 16);
+ if (subsys < 0)
+ return NULL;
+
+ cmdq_base = devm_kmalloc(dev, sizeof(*cmdq_base), GFP_KERNEL);
+ if (!cmdq_base)
+ return NULL;
+ cmdq_base->subsys = subsys;
+ cmdq_base->base = base;
+
+ return cmdq_base;
+}
+EXPORT_SYMBOL(cmdq_register_device);
+
+struct cmdq_client *cmdq_mbox_create(struct device *dev, int index)
+{
+ struct cmdq_client *client;
+
+ client = kzalloc(sizeof(*client), GFP_KERNEL);
+ client->client.dev = dev;
+ client->client.tx_block = false;
+ client->chan = mbox_request_channel(&client->client, index);
+ return client;
+}
+EXPORT_SYMBOL(cmdq_mbox_create);
+
+void cmdq_mbox_destroy(struct cmdq_client *client)
+{
+ mbox_free_channel(client->chan);
+ kfree(client);
+}
+EXPORT_SYMBOL(cmdq_mbox_destroy);
+
+int cmdq_pkt_create(struct cmdq_pkt **pkt_ptr)
+{
+ struct cmdq_pkt *pkt;
+ int err;
+
+ pkt = kzalloc(sizeof(*pkt), GFP_KERNEL);
+ if (!pkt)
+ return -ENOMEM;
+ err = cmdq_pkt_realloc_cmd_buffer(pkt, PAGE_SIZE);
+ if (err < 0) {
+ kfree(pkt);
+ return err;
+ }
+ *pkt_ptr = pkt;
+ return 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_create);
+
+void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
+{
+ kfree(pkt->va_base);
+ kfree(pkt);
+}
+EXPORT_SYMBOL(cmdq_pkt_destroy);
+
+static bool cmdq_pkt_is_finalized(struct cmdq_pkt *pkt)
+{
+ u64 *expect_eoc;
+
+ if (pkt->cmd_buf_size < CMDQ_INST_SIZE << 1)
+ return false;
+
+ expect_eoc = pkt->va_base + pkt->cmd_buf_size - (CMDQ_INST_SIZE << 1);
+ if (*expect_eoc == CMDQ_EOC_CMD)
+ return true;
+
+ return false;
+}
+
+static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
+ u32 arg_a, u32 arg_b)
+{
+ u64 *cmd_ptr;
+ int err;
+
+ if (WARN_ON(cmdq_pkt_is_finalized(pkt)))
+ return -EBUSY;
+ if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
+ err = cmdq_pkt_realloc_cmd_buffer(pkt, pkt->buf_size << 1);
+ if (err < 0)
+ return err;
+ }
+ cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
+ (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
+ pkt->cmd_buf_size += CMDQ_INST_SIZE;
+ return 0;
+}
+
+int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, struct cmdq_base *base,
+ u32 offset)
+{
+ u32 arg_a = ((base->base + offset) & CMDQ_ARG_A_WRITE_MASK) |
+ (base->subsys << CMDQ_SUBSYS_SHIFT);
+ return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
+}
+EXPORT_SYMBOL(cmdq_pkt_write);
+
+int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
+ struct cmdq_base *base, u32 offset, u32 mask)
+{
+ u32 offset_mask = offset;
+ int err;
+
+ if (mask != 0xffffffff) {
+ err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
+ if (err < 0)
+ return err;
+ offset_mask |= CMDQ_WRITE_ENABLE_MASK;
+ }
+ return cmdq_pkt_write(pkt, value, base, offset_mask);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_mask);
+
+static const u32 cmdq_event_value[CMDQ_MAX_EVENT] = {
+ /* Display start of frame(SOF) events */
+ [CMDQ_EVENT_DISP_OVL0_SOF] = 11,
+ [CMDQ_EVENT_DISP_OVL1_SOF] = 12,
+ [CMDQ_EVENT_DISP_RDMA0_SOF] = 13,
+ [CMDQ_EVENT_DISP_RDMA1_SOF] = 14,
+ [CMDQ_EVENT_DISP_RDMA2_SOF] = 15,
+ [CMDQ_EVENT_DISP_WDMA0_SOF] = 16,
+ [CMDQ_EVENT_DISP_WDMA1_SOF] = 17,
+ /* Display end of frame(EOF) events */
+ [CMDQ_EVENT_DISP_OVL0_EOF] = 39,
+ [CMDQ_EVENT_DISP_OVL1_EOF] = 40,
+ [CMDQ_EVENT_DISP_RDMA0_EOF] = 41,
+ [CMDQ_EVENT_DISP_RDMA1_EOF] = 42,
+ [CMDQ_EVENT_DISP_RDMA2_EOF] = 43,
+ [CMDQ_EVENT_DISP_WDMA0_EOF] = 44,
+ [CMDQ_EVENT_DISP_WDMA1_EOF] = 45,
+ /* Mutex end of frame(EOF) events */
+ [CMDQ_EVENT_MUTEX0_STREAM_EOF] = 53,
+ [CMDQ_EVENT_MUTEX1_STREAM_EOF] = 54,
+ [CMDQ_EVENT_MUTEX2_STREAM_EOF] = 55,
+ [CMDQ_EVENT_MUTEX3_STREAM_EOF] = 56,
+ [CMDQ_EVENT_MUTEX4_STREAM_EOF] = 57,
+ /* Display underrun events */
+ [CMDQ_EVENT_DISP_RDMA0_UNDERRUN] = 63,
+ [CMDQ_EVENT_DISP_RDMA1_UNDERRUN] = 64,
+ [CMDQ_EVENT_DISP_RDMA2_UNDERRUN] = 65,
+};
+
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, enum cmdq_event event)
+{
+ u32 arg_b;
+
+ if (event >= CMDQ_MAX_EVENT || event < 0)
+ return -EINVAL;
+
+ /*
+ * WFE arg_b
+ * bit 0-11: wait value
+ * bit 15: 1 - wait, 0 - no wait
+ * bit 16-27: update value
+ * bit 31: 1 - update, 0 - no update
+ */
+ arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
+ return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE,
+ cmdq_event_value[event], arg_b);
+}
+EXPORT_SYMBOL(cmdq_pkt_wfe);
+
+int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, enum cmdq_event event)
+{
+ if (event >= CMDQ_MAX_EVENT || event < 0)
+ return -EINVAL;
+
+ return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE,
+ cmdq_event_value[event], CMDQ_WFE_UPDATE);
+}
+EXPORT_SYMBOL(cmdq_pkt_clear_event);
+
+static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
+{
+ int err;
+
+ if (cmdq_pkt_is_finalized(pkt))
+ return 0;
+
+ /* insert EOC and generate IRQ for each command iteration */
+ err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN);
+ if (err < 0)
+ return err;
+
+ /* JUMP to end */
+ err = cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+int cmdq_pkt_flush_async(struct cmdq_client *client, struct cmdq_pkt *pkt,
+ cmdq_async_flush_cb cb, void *data)
+{
+ int err;
+
+ err = cmdq_pkt_finalize(pkt);
+ if (err < 0)
+ return err;
+
+ pkt->cb.cb = cb;
+ pkt->cb.data = data;
+
+ mbox_send_message(client->chan, pkt);
+ /* We can send next packet immediately, so just call txdone. */
+ mbox_client_txdone(client->chan, 0);
+
+ return 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_flush_async);
+
+struct cmdq_flush_completion {
+ struct completion cmplt;
+ bool err;
+};
+
+static void cmdq_pkt_flush_cb(struct cmdq_cb_data data)
+{
+ struct cmdq_flush_completion *cmplt = data.data;
+
+ cmplt->err = data.err;
+ complete(&cmplt->cmplt);
+}
+
+int cmdq_pkt_flush(struct cmdq_client *client, struct cmdq_pkt *pkt)
+{
+ struct cmdq_flush_completion cmplt;
+ int err;
+
+ init_completion(&cmplt.cmplt);
+ err = cmdq_pkt_flush_async(client, pkt, cmdq_pkt_flush_cb, &cmplt);
+ if (err < 0)
+ return err;
+ wait_for_completion(&cmplt.cmplt);
+ return cmplt.err ? -EFAULT : 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_flush);
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
new file mode 100644
index 0000000..5b35d73
--- /dev/null
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MTK_CMDQ_H__
+#define __MTK_CMDQ_H__
+
+#include <linux/mailbox_client.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+
+/* display events in command queue(CMDQ) */
+enum cmdq_event {
+ /* Display start of frame(SOF) events */
+ CMDQ_EVENT_DISP_OVL0_SOF,
+ CMDQ_EVENT_DISP_OVL1_SOF,
+ CMDQ_EVENT_DISP_RDMA0_SOF,
+ CMDQ_EVENT_DISP_RDMA1_SOF,
+ CMDQ_EVENT_DISP_RDMA2_SOF,
+ CMDQ_EVENT_DISP_WDMA0_SOF,
+ CMDQ_EVENT_DISP_WDMA1_SOF,
+ /* Display end of frame(EOF) events */
+ CMDQ_EVENT_DISP_OVL0_EOF,
+ CMDQ_EVENT_DISP_OVL1_EOF,
+ CMDQ_EVENT_DISP_RDMA0_EOF,
+ CMDQ_EVENT_DISP_RDMA1_EOF,
+ CMDQ_EVENT_DISP_RDMA2_EOF,
+ CMDQ_EVENT_DISP_WDMA0_EOF,
+ CMDQ_EVENT_DISP_WDMA1_EOF,
+ /* Mutex end of frame(EOF) events */
+ CMDQ_EVENT_MUTEX0_STREAM_EOF,
+ CMDQ_EVENT_MUTEX1_STREAM_EOF,
+ CMDQ_EVENT_MUTEX2_STREAM_EOF,
+ CMDQ_EVENT_MUTEX3_STREAM_EOF,
+ CMDQ_EVENT_MUTEX4_STREAM_EOF,
+ /* Display underrun events */
+ CMDQ_EVENT_DISP_RDMA0_UNDERRUN,
+ CMDQ_EVENT_DISP_RDMA1_UNDERRUN,
+ CMDQ_EVENT_DISP_RDMA2_UNDERRUN,
+ /* Keep this at the end */
+ CMDQ_MAX_EVENT,
+};
+
+struct cmdq_pkt;
+
+struct cmdq_base {
+ int subsys;
+ u32 base;
+};
+
+struct cmdq_client {
+ struct mbox_client client;
+ struct mbox_chan *chan;
+};
+
+/**
+ * cmdq_register_device() - register device which needs CMDQ
+ * @dev: device for CMDQ to access its registers
+ *
+ * Return: cmdq_base pointer or NULL for failed
+ */
+struct cmdq_base *cmdq_register_device(struct device *dev);
+
+/**
+ * cmdq_mbox_create() - create CMDQ mailbox client and channel
+ * @dev: device of CMDQ mailbox client
+ * @index: index of CMDQ mailbox channel
+ *
+ * Return: CMDQ mailbox client pointer
+ */
+struct cmdq_client *cmdq_mbox_create(struct device *dev, int index);
+
+/**
+ * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
+ * @client: the CMDQ mailbox client
+ */
+void cmdq_mbox_destroy(struct cmdq_client *client);
+
+/**
+ * cmdq_pkt_create() - create a CMDQ packet
+ * @pkt_ptr: CMDQ packet pointer to retrieve cmdq_pkt
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_create(struct cmdq_pkt **pkt_ptr);
+
+/**
+ * cmdq_pkt_destroy() - destroy the CMDQ packet
+ * @pkt: the CMDQ packet
+ */
+void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
+
+/**
+ * cmdq_pkt_write() - append write command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @value: the specified target register value
+ * @base: the CMDQ base
+ * @offset: register offset from module base
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value,
+ struct cmdq_base *base, u32 offset);
+
+/**
+ * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @value: the specified target register value
+ * @base: the CMDQ base
+ * @offset: register offset from module base
+ * @mask: the specified target register mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
+ struct cmdq_base *base, u32 offset, u32 mask);
+
+/**
+ * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @event: the desired event type to "wait and CLEAR"
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, enum cmdq_event event);
+
+/**
+ * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @event: the desired event to be cleared
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, enum cmdq_event event);
+
+/**
+ * cmdq_pkt_flush() - trigger CMDQ to execute the CMDQ packet
+ * @client: the CMDQ mailbox client
+ * @pkt: the CMDQ packet
+ *
+ * Return: 0 for success; else the error code is returned
+ *
+ * Trigger CMDQ to execute the CMDQ packet. Note that this is a
+ * synchronous flush function. When the function returned, the recorded
+ * commands have been done.
+ */
+int cmdq_pkt_flush(struct cmdq_client *client, struct cmdq_pkt *pkt);
+
+/**
+ * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
+ * packet and call back at the end of done packet
+ * @client: the CMDQ mailbox client
+ * @pkt: the CMDQ packet
+ * @cb: called at the end of done packet
+ * @data: this data will pass back to cb
+ *
+ * Return: 0 for success; else the error code is returned
+ *
+ * Trigger CMDQ to asynchronously execute the CMDQ packet and call back
+ * at the end of done packet. Note that this is an ASYNC function. When the
+ * function returned, it may or may not be finished.
+ */
+int cmdq_pkt_flush_async(struct cmdq_client *client, struct cmdq_pkt *pkt,
+ cmdq_async_flush_cb cb, void *data);
+
+#endif /* __MTK_CMDQ_H__ */
--
1.9.1
^ permalink raw reply related
* [GIT PULL] STi defconfig fix for v4.9-rcs
From: Patrice Chotard @ 2016-11-23 8:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Olof, Kevin
Please consider this set for inclusion into the v4.9-rc.
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git tags/sti-defconfig-for-4.9-rc
for you to fetch changes up to bb8d1edc272b972758dc75e861c9c17cddcd1d21:
ARM: multi_v7_defconfig: enable STMicroelectronics HVA driver (2016-11-23 09:25:23 +0100)
----------------------------------------------------------------
STi defconfig fix:
Enable HVA (Hardware Video Accelerator) video encoder
driver for STMicroelectronics SoC.
----------------------------------------------------------------
Patrice Chotard (1):
ARM: multi_v7_defconfig: enable STMicroelectronics HVA driver
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
^ permalink raw reply
* [GIT PULL] STi DT fix for v4.9-rcs round 2
From: Patrice Chotard @ 2016-11-23 8:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Olof, Kevin
Please consider this second round for inclusion into the v4.9-rc.
The following changes since commit 5bf7b6e86f29f064979d7b3e6dd21c5dd1feb855:
ARM: dts: STiH410-b2260: Fix typo in spi0 chipselect definition (2016-11-15 11:29:25 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git sti-dt-for-v4.9-rc-round2
for you to fetch changes up to 86b4522d19329b3bf9c05722f217568b803439f7:
ARM: dts: STiH407-family: fix i2c nodes (2016-11-23 09:09:03 +0100)
----------------------------------------------------------------
STi DT fix:
The I2C nodes are missing #address-cells and #size-cells.
This is causing warning at device tree compilation when
some I2C device sub-nodes are defined.
----------------------------------------------------------------
Loic Pallardy (1):
ARM: dts: STiH407-family: fix i2c nodes
arch/arm/boot/dts/stih407-family.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
^ permalink raw reply
* [GIT PULL v2] ARM: OXNAS SoC updates for 4.10
From: Neil Armstrong @ 2016-11-23 9:01 UTC (permalink / raw)
To: linux-arm-kernel
Dear arm-soc maintainers,
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
https://github.com/OXNAS/linux.git tags/oxnas-arm-soc-for-4.10-v2
for you to fetch changes up to e330ea5e8cea7ba58f0ba9d40063b13cf8639555:
ARM: oxnas: Add OX820 config and makefile entry (2016-11-23 09:53:55 +0100)
----------------------------------------------------------------
- Add SMP support for the Oxford Semiconductor OX820 SoC
from http://lkml.kernel.org/r/20161021085848.1754-1-narmstrong at baylibre.com
Changes since v1 Pull Request at : http://lkml.kernel.org/r/1305c61f-b1ef-7caf-7788-67e2b907e873 at baylibre.com
- Clarify copyright dates in commit message
- Remove linux/arch/... lines from the top of the files
----------------------------------------------------------------
Neil Armstrong (2):
ARM: oxnas: Add OX820 SMP support
ARM: oxnas: Add OX820 config and makefile entry
arch/arm/Makefile | 1 +
arch/arm/mach-oxnas/Kconfig | 30 ++++++++----
arch/arm/mach-oxnas/Makefile | 2 +
arch/arm/mach-oxnas/headsmp.S | 26 ++++++++++
arch/arm/mach-oxnas/hotplug.c | 109 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-oxnas/platsmp.c | 102 +++++++++++++++++++++++++++++++++++++++
6 files changed, 261 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/mach-oxnas/Makefile
create mode 100644 arch/arm/mach-oxnas/headsmp.S
create mode 100644 arch/arm/mach-oxnas/hotplug.c
create mode 100644 arch/arm/mach-oxnas/platsmp.c
Thanks,
Neil
^ permalink raw reply
* [PATCH v2 2/3] arm64: dts: sunxi: sort the nodes in sun50i-a64-pine64.dts
From: Maxime Ripard @ 2016-11-23 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122155831.8724-2-icenowy@aosc.xyz>
On Tue, Nov 22, 2016 at 11:58:30PM +0800, Icenowy Zheng wrote:
> In this dts file, uart0 node is put before i2c1.
>
> Move the uart0 node to the end to satisfy alphebetical order.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Fixed the prefix and applied. Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v2 3/3] arm64: dts: sunxi: enable EHCI1, OHCI1 and USB PHY nodes in Pine64
From: Maxime Ripard @ 2016-11-23 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122155831.8724-3-icenowy@aosc.xyz>
On Tue, Nov 22, 2016 at 11:58:31PM +0800, Icenowy Zheng wrote:
> Pine64 have two USB Type-A ports, which are wired to the two ports of
> A64 USB PHY, and the lower port is the EHCI/OHCI1 port.
>
> Enable the necessary nodes to enable the lower USB port to work.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Fixed the prefix and applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 1/7] add binding for stm32 multifunctions timer driver
From: Lee Jones @ 2016-11-23 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+M3ks4cVLtVe4zSvSiDUz6jKy0Wbw8j24VuStf_31D5ntwfvw@mail.gmail.com>
On Wed, 23 Nov 2016, Benjamin Gaignard wrote:
> 2016-11-22 17:52 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> > On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
> >
> >> Add bindings information for stm32 timer MFD
> >>
> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> >> ---
> >> .../devicetree/bindings/mfd/stm32-timer.txt | 53 ++++++++++++++++++++++
> >> 1 file changed, 53 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timer.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/stm32-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
> >> new file mode 100644
> >> index 0000000..3cefce1
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
> >> @@ -0,0 +1,53 @@
> >> +STM32 multifunctions timer driver
> >
> > "STM32 Multi-Function Timer/PWM device bindings"
> >
> > Doesn't this shared device have a better name?
>
> In SoC documentation those hardware blocks are named "advanced-control
> timers", "general purpose timers" or "basic timers"
> "stm32-timer" name is already used for clock source driver, that why I
> have prefix it with mfd
MFD is a Linuxisum and has no place in hardware description.
Please used one of the names you mentioned above.
Hopefully the one that best fits.
> >> +stm32 timer MFD allow to handle at the same time pwm and IIO timer devices
> >
> > No need for this sentence.
> >
> OK
>
> >> +Required parameters:
> >> +- compatible: must be one of the follow value:
> >> + "st,stm32-mfd-timer1"
> >> + "st,stm32-mfd-timer2"
> >> + "st,stm32-mfd-timer3"
> >> + "st,stm32-mfd-timer4"
> >> + "st,stm32-mfd-timer5"
> >> + "st,stm32-mfd-timer6"
> >> + "st,stm32-mfd-timer7"
> >> + "st,stm32-mfd-timer8"
> >> + "st,stm32-mfd-timer9"
> >> + "st,stm32-mfd-timer10"
> >> + "st,stm32-mfd-timer11"
> >> + "st,stm32-mfd-timer12"
> >> + "st,stm32-mfd-timer13"
> >> + "st,stm32-mfd-timer14"
> >
> > We don't normally number devices.
> >
> > What's stopping you from simply doing:
> >
> > pwm1: pwm1 at 40010000 {
> > compatible = "st,stm32-pwm";
> > };
> > pwm2: pwm1 at 40020000 {
> > compatible = "st,stm32-pwm";
> > };
> > pwm3: pwm1 at 40030000 {
> > compatible = "st,stm32-pwm";
> > };
> >
>
> Because each instance of the hardware is slightly different: number of
> pwm channels, triggers capabilities, etc ..
> so I need to distinguish them.
> Since it look to be a problem I will follow your suggestion and add a
> property this driver to be able to identify each instance.
> Do you think that "id" parameter (integer for 1 to 14) is acceptable ?
Unfortunately not. IDs aren't allowed in DT.
What about "pwm-chans" and "trigger"?
pwm-chans : Number of available channels available
trigger : Boolean value specifying whether a timer is present
Why can't you let of_platform_populate() register the devices for you?
Then you can get rid of all of the meaningless numbers all over the place.
> >> +- reg : Physical base address and length of the controller's
> >> + registers.
> >> +- clock-names: Set to "mfd_timer_clk".
> >
> Only one but I use devm_regmap_init_mmio_clk() to avoid calling
> clk_{enable/disable}
> everywhere in the drivers when reading/writing regsister.
> devm_regmap_init_mmio_clk() find the clock by it name that why I have
> put it here
> In the doc this clock in named "clk_int" I will use this name.
Please reply *below* the quote.
But okay, "clk_int" sounds like a more suitable name.
> > How many clocks are there?
> >
> > If only 1, you don't need this property.
> >
> > "mfd_timer_clk" is not the correct name.
> >
> > What is it called in the datasheet?
> >
> >> +- clocks: Phandle of the clock used by the timer module.
> >
> > "Phandle to the clock ..."
> >
> >> + For Clk properties, please refer to [1].
> >> +- interrupts : Reference to the timer interrupt
> >
> > Reference to?
> >
> > See how other binding documents describe this property.
> >
> >> +Optional parameters:
> >> +- resets : Reference to a reset controller asserting the timer
> >
> > As above.
> >
> >> +Optional subnodes:
> >
> > Either use ":" or " :" or "<tab>:", but keep it consistent.
> >
> >> +- pwm: See Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> >> +- iiotimer: See Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
> >> +
> >> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >
> > Use the relative paths "../clock/", "../pwm/", "../iio/".
> >
> OK
>
> >> +Example:
> >> + mfd_timer1: mfdtimer1 at 40010000 {
> >
> > This is not an "MFD timer". MFD is a Linuxisum.
> >
> >> + compatible = "st,stm32-mfd-timer1";
> >
> > Better description required.
> >
> >> + reg = <0x40010000 0x400>;
> >> + clocks = <&rcc 0 160>;
> >> + clock-names = "mfd_timer_clk";
> >> + interrupts = <27>;
> >> +
> >> + pwm1: pwm1 at 40010000 {
> >> + compatible = "st,stm32-pwm1";
> >> + };
> >> +
> >> + iiotimer1: iiotimer1 at 40010000 {
> >> + compatible = "st,stm32-iio-timer1";
> >> + };
> >> + };
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 2/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Andre Przywara @ 2016-11-23 9:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123075713.ks6gmud3rszjbdsh@lukather>
Hi Maxime,
On 23/11/16 07:57, Maxime Ripard wrote:
> On Tue, Nov 22, 2016 at 12:24:20AM +0800, Icenowy Zheng wrote:
>> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC.
>>
>> Add a device tree file for it.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>> ---
>> Changes since v2:
>> - Use generic pinconf binding instead of legacy allwinner pinctrl binding.
>> - removed uart3, which is not accessible on Orange Pi Zero.
>> - Removed sun8i-h2plus.dtsi and make Orange Pi Zero dts directly include
>> sun8i-h3.dtsi.
>> - Removed allwinner,sun8i-h3 compatible.
>>
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts | 137 +++++++++++++++++++++++
>
> Ditto, h2-plus-orangepi-zero.
>
>> 2 files changed, 138 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 802a10d..51a1dd7 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -834,6 +834,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>> sun8i-a33-sinlinx-sina33.dtb \
>> sun8i-a83t-allwinner-h8homlet-v2.dtb \
>> sun8i-a83t-cubietruck-plus.dtb \
>> + sun8i-h2plus-orangepi-zero.dtb \
>> sun8i-h3-bananapi-m2-plus.dtb \
>> sun8i-h3-nanopi-neo.dtb \
>> sun8i-h3-orangepi-2.dtb \
>> diff --git a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>> new file mode 100644
>> index 0000000..b428e47
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>> @@ -0,0 +1,137 @@
>> +/*
>> + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
>> + *
>> + * Based on sun8i-h3-orangepi-one.dts, which is:
>> + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +#include "sun8i-h3.dtsi"
>> +#include "sunxi-common-regulators.dtsi"
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> + model = "Xunlong Orange Pi Zero";
>> + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2plus";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&leds_opi0>, <&leds_r_opi0>;
>> +
>> + pwr_led {
>> + label = "orangepi:green:pwr";
>> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> +
>> + status_led {
>> + label = "orangepi:red:status";
>> + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
>> + };
>> + };
>> +};
>> +
>> +&ehci1 {
>> + status = "okay";
>> +};
>> +
>> +&mmc0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
>> + vmmc-supply = <®_vcc3v3>;
>> + bus-width = <4>;
>> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
>> + cd-inverted;
>> + status = "okay";
>> +};
>> +
>> +&ohci1 {
>> + status = "okay";
>> +};
>> +
>> +&pio {
>> + leds_opi0: led_pins at 0 {
>> + pins = "PA17";
>> + function = "gpio_out";
>> + };
>> +};
>> +
>> +&r_pio {
>> + leds_r_opi0: led_pins at 0 {
>> + pins = "PL10";
>> + function = "gpio_out";
>> + };
>> +};
>> +
>> +&uart0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins_a>;
>> + status = "okay";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart1_pins>;
>> + status = "disabled";
>> +};
>> +
>> +&uart2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart2_pins>;
>> + status = "disabled";
>> +};
>
> I'm not sure you answered me on this one. Are those exposed on the
> headers? why did you put them as disabled here?
So they are on headers, though you have to solder the actual header pins
yourself [1]. But also these are the normal pins multiplexed with GPIOs
and other peripherals, so keeping them disabled is in line with the
existing policy, if I got this correctly.
I agree that the status="disabled" is redundant, since we have that
exact line already in the .dtsi. But I saw it in other DTs as well, most
prominently in the sun8i-h3-orangepi-one.dts.
So I think we should remove the "status=" lines here, dtc will generate
an identical dtb out of it. But we should keep the uart descriptions in
to make it easier for users to see which SoC pins are used for these
pins labeled UART[012] in the board description and schematic. Also all
it takes to enable those is to overwrite the status property, which can
easily be done inline (without resizing the dtb).
Cheers,
Andre.
[1] http://linux-sunxi.org/Xunlong_Orange_Pi_Zero
^ permalink raw reply
* [PATCH v2 3/3] usb: ohci-da8xx: rename driver to ohci-da8xx
From: Greg KH @ 2016-11-23 9:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKXjFTME9Y+KEg21i05zP6+10tB4bW=cMbSftAbYhozEg1B8ZA@mail.gmail.com>
On Mon, Nov 21, 2016 at 06:10:50PM +0100, Axel Haslam wrote:
> Hi Greg,
>
> On Thu, Nov 3, 2016 at 5:03 PM, Axel Haslam <ahaslam@baylibre.com> wrote:
> > The davinci ohci driver name (currently "ohci") is too generic.
> > To be consistent with other usb dirvers, append the "-da8xx" postfix
> > to the name.
> >
>
> if there are no objections, would it be possible to pick up this patch?
> the corresponding phy patch was merged and the platform changes
> are ack'ed, and will we taken by the davinci maintainer once this patch
> gets in.
Now applied.
thanks,
greg k-h
^ permalink raw reply
* [PATCH 1/2] kbuild: provide include/asm/asm-prototypes.h for ARM
From: Russell King - ARM Linux @ 2016-11-23 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.20.1611222030050.1814@knanqh.ubzr>
On Tue, Nov 22, 2016 at 08:35:48PM -0500, Nicolas Pitre wrote:
> On Wed, 23 Nov 2016, Nicholas Piggin wrote:
>
> > On Tue, 22 Nov 2016 11:34:48 -0500 (EST)
> > Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> >
> > > On Tue, 22 Nov 2016, Arnd Bergmann wrote:
> > >
> > > > This adds an asm/asm-prototypes.h header for ARM to fix the broken symbol
> > > > versioning for symbols exported from assembler files.
> > > >
> > > > I couldn't find the correct prototypes for the compiler builtins,
> > > > so I went with the fake 'void f(void)' prototypes that we had
> > > > before, restoring the state before they were moved.
> > > >
> > > > Originally I assumed that the problem was just a harmless warning
> > > > in unusual configurations, but as Uwe found, we actually need this
> > > > to load most modules when symbol versioning is enabled, as it is
> > > > in many distro kernels.
> > > >
> > > > Cc: Uwe Kleine-K?nig <uwe@kleine-koenig.org>
> > > > Fixes: 4dd1837d7589 ("arm: move exports to definitions")
> > > > Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> > > > ---
> > > > Compared to the earlier version, I dropped the changes to the
> > > > csumpartial files, which now get handled correctly by Kbuild
> > > > even when the export comes from a macro, and I also dropped the
> > > > changes to the bitops files, which were already fixed in a
> > > > patch from Nico.
> > > >
> > > > The patch applies cleanly on top of the rmk/fixes tree but has
> > > > no effect there, as it also needs 4efca4ed05cb ("kbuild: modversions
> > > > for EXPORT_SYMBOL() for asm") and cc6acc11cad1 ("kbuild: be more
> > > > careful about matching preprocessed asm ___EXPORT_SYMBOL").
> > > >
> > > > With the combination of rmk/fixes, torvalds/master and these two
> > > > patches, symbol versioning works again on ARM. As it is still
> > > > broken on almost all other architectures (powerpc is fixed,
> > > > x86 has a patch), I wonder if we should make CONFIG_MODVERSIONS
> > > > as broken for everything else.
> > >
> > > I'm not sure I like this at all.
> > >
> > > The goal for moving EXPORT_SYMBOL() to assembly code where symbols were
> > > defined is to make things close together and avoid those centralized
> > > list of symbols that you can easily miss when modifying the actual code.
> >
> > Right.
> >
> > >
> > > This series is therefore bringing back a centralized list of symbols in
> > > a slightly different form, nullifying the advantages from having moved
> > > EXPORT_SYMBOL() to asm code. To me this looks like a big step backward.
> >
> > Exported symbols have C declarations in headers already. For the most
> > part, anyway -- these ones Arnd adds are for compiler runtime which is
> > why some architectures haven't had the prototypes.
>
> Hmmm. That's right. That makes it much more justifiable.
> My main objection is withdrawn.
I don't see it makes any difference - the armksyms.c originally had
the same:
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/cryptohash.h>
-#include <linux/delay.h>
-#include <linux/in6.h>
-#include <linux/syscalls.h>
-#include <linux/uaccess.h>
-#include <linux/io.h>
-#include <linux/arm-smccc.h>
-
-#include <asm/checksum.h>
-#include <asm/ftrace.h>
followed by prototypes for the GCC internal functions, and:
-extern void fpundefinstr(void);
-
-void mmioset(void *, unsigned int, size_t);
-void mmiocpy(void *, const void *, size_t);
So, the asm-prototypes.h approach is just the same, only that we now
have a bunch of prototypes in a header file, and the EXPORT_SYMBOL()s
in the assembly files.
As the C prototypes are remote from the definitions, it means that
the C prototypes are going to get forgotten about in exactly the same
way that armksyms.c would've been forgotten about too.
It _is_ worse than that though - with the armksyms.c approach, if the
assembly code for it is removed, you get a build error reminding you
to remove the export (and prototype). With this approach, you get no
reminder to touch asm-prototypes.h.
It's also error prone for another reason - adding a new assembly level
export, if you forget to add it to asm-prototypes.h, we're back into
the problem we have right now with MODVERSIONS breaking.
So, I still think the whole approach is wrong - it's added extra
fragility that wasn't there with the armksyms.c approach.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH v6 3/3] arm: dts: mt2701: Add node for Mediatek JPEG Decoder
From: Rick Chang @ 2016-11-23 9:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479866054.8964.21.camel@mtksdaap41>
On Wed, 2016-11-23 at 09:54 +0800, Rick Chang wrote:
> Hi Hans,
>
> On Tue, 2016-11-22 at 13:43 +0100, Hans Verkuil wrote:
> > On 22/11/16 04:21, Rick Chang wrote:
> > > Hi Hans,
> > >
> > > On Mon, 2016-11-21 at 15:51 +0100, Hans Verkuil wrote:
> > >> On 17/11/16 04:38, Rick Chang wrote:
> > >>> Signed-off-by: Rick Chang <rick.chang@mediatek.com>
> > >>> Signed-off-by: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
> > >>> ---
> > >>> This patch depends on:
> > >>> CCF "Add clock support for Mediatek MT2701"[1]
> > >>> iommu and smi "Add the dtsi node of iommu and smi for mt2701"[2]
> > >>>
> > >>> [1] http://lists.infradead.org/pipermail/linux-mediatek/2016-October/007271.html
> > >>> [2] https://patchwork.kernel.org/patch/9164013/
> > >>
> > >> I assume that 1 & 2 will appear in 4.10? So this patch needs to go in
> > >> after the
> > >> other two are merged in 4.10?
> > >>
> > >> Regards,
> > >>
> > >> Hans
> > >
> > > [1] will appear in 4.10, but [2] will appear latter than 4.10.So this
> > > patch needs to go in after [1] & [2] will be merged in 4.11.
> >
> > So what should I do? Merge the driver for 4.11 and wait with this patch
> > until [2] is merged in 4.11? Does that sound reasonable?
> >
> > Regards,
> >
> > Hans
>
> What do you think about this? You merge the driver first and I send this
> patch again after [1] & [2] is merged.
BTW, to prevent merging conflict, the dtsi should be merged by mediatek
SoC maintainer, Matthias.I think we can only take care on the driver
part at this moment.
^ permalink raw reply
* [PATCHv3 5/6] arm64: Use __pa_symbol for kernel symbols
From: Mark Rutland @ 2016-11-23 9:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92635df6-9a58-02cf-3230-1a84c28370d1@redhat.com>
On Mon, Nov 21, 2016 at 09:40:06AM -0800, Laura Abbott wrote:
> On 11/18/2016 06:35 AM, Mark Rutland wrote:
> > On Thu, Nov 17, 2016 at 05:16:55PM -0800, Laura Abbott wrote:
> >> /* Grab the vDSO code pages. */
> >> for (i = 0; i < vdso_pages; i++)
> >> - vdso_pagelist[i + 1] = pfn_to_page(PHYS_PFN(__pa(&vdso_start)) + i);
> >> + vdso_pagelist[i + 1] = pfn_to_page(PHYS_PFN(__pa_symbol(&vdso_start)) + i);
> >
> > Nit: phys_to_page() again.
>
> I think it makes sense to keep this one as is. It's offsetting
> by pfn number and trying force phys_to_page would make it more
> difficult to read.
My bad; I failed to spot the + i.
That sounds good to me; sorry for the noise there.
Thanks,
Mark.
^ permalink raw reply
* [PATCH] ARM: dts: am335x-baltos: use phy-phandle declarations
From: yegorslists at googlemail.com @ 2016-11-23 9:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
---
arch/arm/boot/dts/am335x-baltos-ir2110.dts | 10 ++++++++--
arch/arm/boot/dts/am335x-baltos-ir3220.dts | 2 +-
arch/arm/boot/dts/am335x-baltos-ir5221.dts | 2 +-
arch/arm/boot/dts/am335x-baltos.dtsi | 5 ++++-
4 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index a9a9730..501c752 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -54,16 +54,22 @@
dr_mode = "host";
};
+&davinci_mdio {
+ phy0: ethernet-phy at 0 {
+ reg = <1>;
+ };
+};
+
&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index fe002a1..19f53b8 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -109,9 +109,9 @@
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index f599350..2b9d7f4 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -127,9 +127,9 @@
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index 09b9541..efb5eae 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -364,11 +364,14 @@
};
&davinci_mdio {
+ status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
+ phy1: ethernet-phy at 1 {
+ reg = <7>;
+ };
};
&mmc1 {
--
2.1.4
^ permalink raw reply related
* [PATCH 7/7] add stm32 multi-functions timer driver in DT
From: Lee Jones @ 2016-11-23 9:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479831207-32699-8-git-send-email-benjamin.gaignard@st.com>
On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
> Add timers MFD and childs into DT for stm32f4.
> Define and enable pwm1 and pwm3 for stm32f469 discovery board
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> arch/arm/boot/dts/stm32f429.dtsi | 246 ++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stm32f469-disco.dts | 29 ++++
> 2 files changed, 275 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index bca491d..28a0fe9 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -355,6 +355,21 @@
> slew-rate = <2>;
> };
> };
> +
> + pwm1_pins: pwm at 1 {
> + pins {
> + pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
> + <STM32F429_PB13_FUNC_TIM1_CH1N>,
> + <STM32F429_PB12_FUNC_TIM1_BKIN>;
> + };
> + };
> +
> + pwm3_pins: pwm at 3 {
> + pins {
> + pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
> + <STM32F429_PB5_FUNC_TIM3_CH2>;
> + };
> + };
> };
>
> rcc: rcc at 40023810 {
> @@ -426,6 +441,237 @@
> interrupts = <80>;
> clocks = <&rcc 0 38>;
> };
> +
> + mfd_timer1: mfdtimer1 at 40010000 {
Do you reference this node?
If not, it should read:
advanced-control at 40010000
> + compatible = "st,stm32-mfd-timer1";
"st,stm32-advanced-control"
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "mfd_timer_clk";
"clk_int"
> + interrupts = <27>;
This is a timer property.
Also move the associated registration C code into the timer driver.
> + status = "disabled";
> +
> + pwm1: pwm1 at 40010000 {
pwm at 0 {
> + compatible = "st,stm32-pwm1";
st,stm32-advanced-control-pwm
> + status = "disabled";
> + };
> +
> + iiotimer1: iiotimer1 at 40010000 {
Same here:
timer at 0
> + compatible = "st,stm32-iio-timer1";
st,stm32-advanced-control-timer
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer2: mfdtimer2 at 40000000 {
> + compatible = "st,stm32-mfd-timer2";
> + reg = <0x40000000 0x400>;
> + clocks = <&rcc 0 128>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <28>;
> + status = "disabled";
> +
> + pwm2: pwm2 at 40000000 {
> + compatible = "st,stm32-pwm2";
> + status = "disabled";
> + };
> + iiotimer2: iiotimer2 at 40000000 {
> + compatible = "st,stm32-iio-timer2";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer3: mfdtimer3 at 40000400 {
> + compatible = "st,stm32-mfd-timer3";
> + reg = <0x40000400 0x400>;
> + clocks = <&rcc 0 129>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <29>;
> + status = "disabled";
> +
> + pwm3: pwm3 at 40000400 {
> + compatible = "st,stm32-pwm3";
> + status = "disabled";
> + };
> + iiotimer3: iiotimer3 at 40000400 {
> + compatible = "st,stm32-iio-timer3";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer4: mfdtimer4 at 40000800 {
> + compatible = "st,stm32-mfd-timer4";
> + reg = <0x40000800 0x400>;
> + clocks = <&rcc 0 130>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <30>;
> + status = "disabled";
> +
> + pwm4: pwm4 at 40000800 {
> + compatible = "st,stm32-pwm4";
> + status = "disabled";
> + };
> + iiotimer4: iiotimer4 at 40000800 {
> + compatible = "st,stm32-iio-timer4";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer5: mfdtimer5 at 40000C00 {
> + compatible = "st,stm32-mfd-timer5";
> + reg = <0x40000C00 0x400>;
> + clocks = <&rcc 0 131>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <50>;
> + status = "disabled";
> +
> + pwm5: pwm5 at 40000C00 {
> + compatible = "st,stm32-pwm5";
> + status = "disabled";
> + };
> + iiotimer5: iiotimer5 at 40000800 {
> + compatible = "st,stm32-iio-timer5";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer6: mfdtimer6 at 40001000 {
> + compatible = "st,stm32-mfd-timer6";
> + reg = <0x40001000 0x400>;
> + clocks = <&rcc 0 132>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <54>;
> + status = "disabled";
> +
> + iiotimer6: iiotimer6 at 40001000 {
> + compatible = "st,stm32-iio-timer6";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer7: mfdtimer7 at 40001400 {
> + compatible = "st,stm32-mfd-timer7";
> + reg = <0x40001400 0x400>;
> + clocks = <&rcc 0 133>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <55>;
> + status = "disabled";
> +
> + iiotimer7: iiotimer7 at 40001400 {
> + compatible = "st,stm32-iio-timer7";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer8: mfdtimer8 at 40010400 {
> + compatible = "st,stm32-mfd-timer8";
> + reg = <0x40010400 0x400>;
> + clocks = <&rcc 0 161>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <46>;
> + status = "disabled";
> +
> + pwm8: pwm8 at 40010400 {
> + compatible = "st,stm32-pwm8";
> + status = "disabled";
> + };
> +
> + iiotimer8: iiotimer7 at 40010400 {
> + compatible = "st,stm32-iio-timer8";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer9: mfdtimer9 at 40014000 {
> + compatible = "st,stm32-mfd-timer9";
> + reg = <0x40014000 0x400>;
> + clocks = <&rcc 0 176>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <24>;
> + status = "disabled";
> +
> + pwm9: pwm9 at 40014000 {
> + compatible = "st,stm32-pwm9";
> + status = "disabled";
> + };
> +
> + iiotimer9: iiotimer9 at 40014000 {
> + compatible = "st,stm32-iio-timer9";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer10: mfdtimer10 at 40014400 {
> + compatible = "st,stm32-mfd-timer10";
> + reg = <0x40014400 0x400>;
> + clocks = <&rcc 0 177>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <25>;
> + status = "disabled";
> +
> + pwm10: pwm10 at 40014400 {
> + compatible = "st,stm32-pwm10";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer11: mfdtimer11 at 40014800 {
> + compatible = "st,stm32-mfd-timer11";
> + reg = <0x40014800 0x400>;
> + clocks = <&rcc 0 178>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <26>;
> + status = "disabled";
> +
> + pwm11: pwm11 at 40014800 {
> + compatible = "st,stm32-pwm11";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer12: mfdtimer12 at 40001800 {
> + compatible = "st,stm32-mfd-timer12";
> + reg = <0x40001800 0x400>;
> + clocks = <&rcc 0 134>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <43>;
> + status = "disabled";
> +
> + pwm12: pwm12 at 40001800 {
> + compatible = "st,stm32-pwm12";
> + status = "disabled";
> + };
> + iiotimer12: iiotimer12 at 40001800 {
> + compatible = "st,stm32-iio-timer12";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer13: mfdtimer13 at 40001C00 {
> + compatible = "st,stm32-mfd-timer13";
> + reg = <0x40001C00 0x400>;
> + clocks = <&rcc 0 135>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <44>;
> + status = "disabled";
> +
> + pwm13: pwm13 at 40001C00 {
> + compatible = "st,stm32-pwm13";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer14: mfdtimer14 at 40002000 {
> + compatible = "st,stm32-mfd-timer14";
> + reg = <0x40002000 0x400>;
> + clocks = <&rcc 0 136>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <45>;
> + status = "disabled";
> +
> + pwm14: pwm14 at 40002000 {
> + compatible = "st,stm32-pwm14";
> + status = "disabled";
> + };
> + };
> };
> };
>
> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
> index 8a163d7..a8f1788 100644
> --- a/arch/arm/boot/dts/stm32f469-disco.dts
> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
> @@ -81,3 +81,32 @@
> &usart3 {
> status = "okay";
> };
> +
> +&mfd_timer1 {
> + status = "okay";
> +};
> +
> +&pwm1 {
> + pinctrl-0 = <&pwm1_pins>;
> + pinctrl-names = "default";
> + st,breakinput-polarity = <0>;
Is this documented?
I'm sure we have generic polarity properties somewhere already?
> + status = "okay";
> +};
> +
> +&iiotimer1 {
> + status = "okay";
> +};
> +
> +&mfd_timer3 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + pinctrl-0 = <&pwm3_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&iiotimer3 {
> + status = "okay";
> +};
I've always disliked this way of referencing nodes!
Any chance we can represent them in a hierarchy, so we don't lose that
information and we can get rid of all those horrible labels?
I'm happy to do the work.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible
From: Jisheng Zhang @ 2016-11-23 9:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2948812.F3se4ieqO6@wuerfel>
On Tue, 22 Nov 2016 22:04:12 +0100 Arnd Bergmann wrote:
> On Tuesday, November 22, 2016 5:48:41 PM CET Gregory CLEMENT wrote:
> > +#ifdef CONFIG_64BIT
> > + void *data_tmp;
> > +
> > + /* In Neta HW only 32 bits data is supported, so in order to
> > + * obtain whole 64 bits address from RX descriptor, we store
> > + * the upper 32 bits when allocating buffer, and put it back
> > + * when using buffer cookie for accessing packet in memory.
> > + * Frags should be allocated from single 'memory' region,
> > + * hence common upper address half should be sufficient.
> > + */
> > + data_tmp = mvneta_frag_alloc(pp->frag_size);
> > + if (data_tmp) {
> > + pp->data_high = (u64)upper_32_bits((u64)data_tmp) << 32;
> > + mvneta_frag_free(pp->frag_size, data_tmp);
> > + }
> >
>
> How does this work when the region spans a n*4GB address boundary?
indeed. We also make use of this driver on 64bit platforms. We use
different solution to make the driver 64bit safe.
solA: make use of the reserved field in the mvneta_rx_desc, such
as reserved2 etc. Yes, the field is marked as "for future use, PnC", but
now it's not used at all. This is one possible solution however.
solB: allocate a shadow buf cookie during init, e.g
rxq->descs_bufcookie = kmalloc(rxq->size * sizeof(void*), GFP_KERNEL);
then modify mvneta_rx_desc_fill a bit to save the 64bit pointer in
the shadow buf cookie, e.g
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
u32 phys_addr, u32 cookie,
struct mvneta_rx_queue *rxq)
{
int i;
rx_desc->buf_cookie = cookie;
rx_desc->buf_phys_addr = phys_addr;
i = rx_desc - rxq->descs;
rxq->descs_bufcookie[i] = cookie;
}
then fetch the desc from the shadow buf cookie in all code path, such
as mvneta_rx() etc.
Both solutions should not have the problems pointed out by Arnd.
Thanks,
Jisheng
^ permalink raw reply
* [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.10
From: Simon Horman @ 2016-11-23 9:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121105315.GA19845@verge.net.au>
On Mon, Nov 21, 2016 at 11:53:18AM +0100, Simon Horman wrote:
> On Fri, Nov 18, 2016 at 05:49:29PM -0800, Olof Johansson wrote:
> > On Thu, Nov 17, 2016 at 03:11:45PM +0100, Simon Horman wrote:
> > > Hi Olof, Hi Kevin, Hi Arnd,
> > >
> > > Please consider these second round of Renesas ARM based SoC DT updates for v4.10.
> > >
> > > This pull request is based on a merge of:
> > >
> > > * The previous round of such requests, tagged as renesas-dt-for-v4.10,
> > > which I have already sent a pull-request for.
> > > * The rzg-clock-defs tag of Geert Uytterhoeven's renesas-driver's tree.
> > > This is to provide dependencies for adding the r8a7743 and r8a7745 SoCs.
> > > * The "Second Round of Renesas ARM Based SoC Drivers Updates for v4.10",
> > > tagged as renesas-drivers2-for-v4.10, which I have also sent a pull
> > > request for. This is included to provide dependencies for adding device
> > > nodes for PRR, and adding the r8a7743 and r8a7745 SoCs.
> >
> > Again, nack. And again, I don't understand why you create dependencies that
> > aren't needed. Please fix.
>
> Hi Olof,
>
> I agree that calling out PRR above was incorrect. Please disregard that.
>
> However, there are dependencies for adding r8a7743 and r8a7745 SoCs
> in the form of header files:
>
> * The rzg-clock-defs tag provides dt-bindings/clock/r8a774[35]-cpg-mssr.h
> * The renesas-drivers2-for-v4.10 tag provides
> dt-bindings/power/r8a774[35]-sysc.h
>
> The drivers branches are usually pretty light-weight. But this time it is a
> bit heavy and you rightly raised some questions about it. After some
> discussion with Geert we'd like to suggest that for future releases
> we provide a "driver-defs" branch which both driver code and DT can
> depend on. Thus avoiding pulling (non essential) driver changes into the DT
> branch.
>
> Unfortunately its a bit late to do that for v4.10 as the r8a7743 sysc
> driver and its defines were already accepted accepted together
> (renesas-drivers-for-v4.10 tag). So for this release we would be grateful
> if you could re-consider the renesas-drivers2-for-v4.10 tag given the
> feedback which Geert has provided. And in turn re-consider this pull
> request.
Hi again,
while the above remains my preferred option I would like to put another one
on the table in case it would help in any way for v4.10.
I could split this pull-request up as follows:
1. The patches that add the r8a774[35] SoCs:
- r8a7743 depends on renesas-drivers-for-v4.10 and rzg-clock-defs
- r8a7745 depends on renesas-drivers2-for-v4.10 and rzg-clock-defs
2. The patches rest of the patches
- I believe these have no special dependencies
^ permalink raw reply
* serial: Add LED trigger support
From: Sascha Hauer @ 2016-11-23 10:01 UTC (permalink / raw)
To: linux-arm-kernel
This series brings LED trigger support to the serial_core layer
and adopts some driver to use it.
This is an updated version of https://patchwork.kernel.org/patch/9212885/
which added LED trigger support to the i.MX serial driver only.
Sascha
----------------------------------------------------------------
Sascha Hauer (4):
serial: core: Add LED trigger support
serial: 8250: Add LED trigger support
serial: cpm_uart: Add LED trigger support
serial: imx: Add LED trigger support
drivers/tty/serial/8250/8250_core.c | 12 ++++-
drivers/tty/serial/8250/8250_port.c | 4 ++
drivers/tty/serial/cpm_uart/cpm_uart_core.c | 22 ++++++++-
drivers/tty/serial/imx.c | 24 +++++++++-
drivers/tty/serial/serial_core.c | 73 +++++++++++++++++++++++++++++
include/linux/serial_core.h | 10 ++++
6 files changed, 139 insertions(+), 6 deletions(-)
^ permalink raw reply
* [PATCH 1/4] serial: core: Add LED trigger support
From: Sascha Hauer @ 2016-11-23 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123100106.15969-1-s.hauer@pengutronix.de>
With this patch the serial core provides LED triggers for RX and TX.
As the serial core layer does not know when the hardware actually sends
or receives characters, this needs help from the UART drivers. The
LED triggers are registered in uart_add_led_triggers() called from
the UART drivers which want to support LED triggers. All the driver
has to do then is to call uart_led_trigger_[tx|rx] to indicate
activity.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/tty/serial/serial_core.c | 73 ++++++++++++++++++++++++++++++++++++++++
include/linux/serial_core.h | 10 ++++++
2 files changed, 83 insertions(+)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index f2303f3..3e8afb7 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -34,6 +34,7 @@
#include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/mutex.h>
+#include <linux/leds.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
@@ -2703,6 +2704,77 @@ static const struct attribute_group tty_dev_attr_group = {
.attrs = tty_dev_attrs,
};
+void uart_led_trigger_tx(struct uart_port *uport)
+{
+ unsigned long delay = 50;
+
+ led_trigger_blink_oneshot(uport->led_trigger_tx, &delay, &delay, 0);
+}
+
+void uart_led_trigger_rx(struct uart_port *uport)
+{
+ unsigned long delay = 50;
+
+ led_trigger_blink_oneshot(uport->led_trigger_rx, &delay, &delay, 0);
+}
+
+/**
+ * uart_add_led_triggers - register LED triggers for a UART
+ * @drv: pointer to the uart low level driver structure for this port
+ * @uport: uart port structure to use for this port.
+ *
+ * Called by the driver to register LED triggers for a UART. It's the
+ * drivers responsibility to call uart_led_trigger_rx/tx on received
+ * and transmitted chars then.
+ */
+int uart_add_led_triggers(struct uart_driver *drv, struct uart_port *uport)
+{
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_LEDS_TRIGGERS))
+ return 0;
+
+ uport->led_trigger_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
+ drv->dev_name, uport->line);
+ uport->led_trigger_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
+ drv->dev_name, uport->line);
+ if (!uport->led_trigger_tx_name || !uport->led_trigger_rx_name) {
+ ret = -ENOMEM;
+ goto err_alloc;
+ }
+
+ led_trigger_register_simple(uport->led_trigger_tx_name,
+ &uport->led_trigger_tx);
+ led_trigger_register_simple(uport->led_trigger_rx_name,
+ &uport->led_trigger_rx);
+
+ return 0;
+
+err_alloc:
+ kfree(uport->led_trigger_tx_name);
+ kfree(uport->led_trigger_rx_name);
+
+ return ret;
+}
+
+/**
+ * uart_remove_led_triggers - remove LED triggers
+ * @drv: pointer to the uart low level driver structure for this port
+ * @uport: uart port structure to use for this port.
+ *
+ * Remove LED triggers previously registered with uart_add_led_triggers
+ */
+void uart_remove_led_triggers(struct uart_port *uport)
+{
+ if (uport->led_trigger_rx)
+ led_trigger_unregister_simple(uport->led_trigger_rx);
+ kfree(uport->led_trigger_rx_name);
+
+ if (uport->led_trigger_tx)
+ led_trigger_unregister_simple(uport->led_trigger_tx);
+ kfree(uport->led_trigger_tx_name);
+}
+
/**
* uart_add_one_port - attach a driver-defined port structure
* @drv: pointer to the uart low level driver structure for this port
@@ -2872,6 +2944,7 @@ int uart_remove_one_port(struct uart_driver *drv, struct uart_port *uport)
WARN_ON(atomic_dec_return(&state->refcount) < 0);
wait_event(state->remove_wait, !atomic_read(&state->refcount));
state->uart_port = NULL;
+
mutex_unlock(&port->mutex);
out:
mutex_unlock(&port_mutex);
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 3442014..1b0a169 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -29,6 +29,7 @@
#include <linux/tty.h>
#include <linux/mutex.h>
#include <linux/sysrq.h>
+#include <linux/leds.h>
#include <uapi/linux/serial_core.h>
#ifdef CONFIG_SERIAL_CORE_CONSOLE
@@ -249,6 +250,10 @@ struct uart_port {
const struct attribute_group **tty_groups; /* all attributes (serial core use only) */
struct serial_rs485 rs485;
void *private_data; /* generic platform data pointer */
+ struct led_trigger *led_trigger_rx;
+ char *led_trigger_rx_name;
+ struct led_trigger *led_trigger_tx;
+ char *led_trigger_tx_name;
};
static inline int serial_port_in(struct uart_port *up, int offset)
@@ -392,6 +397,11 @@ void uart_console_write(struct uart_port *port, const char *s,
unsigned int count,
void (*putchar)(struct uart_port *, int));
+int uart_add_led_triggers(struct uart_driver *drv, struct uart_port *uport);
+void uart_remove_led_triggers(struct uart_port *uport);
+void uart_led_trigger_tx(struct uart_port *port);
+void uart_led_trigger_rx(struct uart_port *port);
+
/*
* Port/driver registration/removal
*/
--
2.10.2
^ permalink raw reply related
* [PATCH 2/4] serial: 8250: Add LED trigger support
From: Sascha Hauer @ 2016-11-23 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123100106.15969-1-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/tty/serial/8250/8250_core.c | 12 ++++++++++--
drivers/tty/serial/8250/8250_port.c | 4 ++++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 240a361..bbcd2539 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -581,6 +581,7 @@ serial8250_register_ports(struct uart_driver *drv, struct device *dev)
up->port.flags |= UPF_NO_TXEN_TEST;
uart_add_one_port(drv, &up->port);
+ uart_add_led_triggers(drv, &up->port);
}
}
@@ -974,8 +975,10 @@ int serial8250_register_8250_port(struct uart_8250_port *up)
uart = serial8250_find_match_or_unused(&up->port);
if (uart && uart->port.type != PORT_8250_CIR) {
- if (uart->port.dev)
+ if (uart->port.dev) {
uart_remove_one_port(&serial8250_reg, &uart->port);
+ uart_remove_led_triggers(&uart->port);
+ }
uart->port.iobase = up->port.iobase;
uart->port.membase = up->port.membase;
@@ -1047,8 +1050,11 @@ int serial8250_register_8250_port(struct uart_8250_port *up)
ret = uart_add_one_port(&serial8250_reg,
&uart->port);
- if (ret == 0)
+ if (ret == 0) {
+ uart_add_led_triggers(&serial8250_reg,
+ &uart->port);
ret = uart->port.line;
+ }
} else {
dev_info(uart->port.dev,
"skipping CIR port at 0x%lx / 0x%llx, IRQ %d\n",
@@ -1087,6 +1093,7 @@ void serial8250_unregister_port(int line)
}
uart_remove_one_port(&serial8250_reg, &uart->port);
+ uart_remove_led_triggers(&uart->port);
if (serial8250_isa_devs) {
uart->port.flags &= ~UPF_BOOT_AUTOCONF;
if (skip_txen_test)
@@ -1095,6 +1102,7 @@ void serial8250_unregister_port(int line)
uart->port.dev = &serial8250_isa_devs->dev;
uart->capabilities = 0;
uart_add_one_port(&serial8250_reg, &uart->port);
+ uart_add_led_triggers(&serial8250_reg, &uart->port);
} else {
uart->port.dev = NULL;
}
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 1731b98..c301ec1 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -1703,6 +1703,8 @@ unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
struct uart_port *port = &up->port;
int max_count = 256;
+ uart_led_trigger_rx(port);
+
do {
serial8250_read_char(up, lsr);
if (--max_count == 0)
@@ -1736,6 +1738,8 @@ void serial8250_tx_chars(struct uart_8250_port *up)
return;
}
+ uart_led_trigger_tx(port);
+
count = up->tx_loadsz;
do {
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
--
2.10.2
^ permalink raw reply related
* [PATCH 3/4] serial: cpm_uart: Add LED trigger support
From: Sascha Hauer @ 2016-11-23 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123100106.15969-1-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/tty/serial/cpm_uart/cpm_uart_core.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
index d3e3d42..5d5633d 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
@@ -255,6 +255,8 @@ static void cpm_uart_int_rx(struct uart_port *port)
pr_debug("CPM uart[%d]:RX INT\n", port->line);
+ uart_led_trigger_rx(port);
+
/* Just loop through the closed BDs and copy the characters into
* the buffer.
*/
@@ -721,6 +723,8 @@ static int cpm_uart_tx_pump(struct uart_port *port)
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
+ uart_led_trigger_tx(port);
+
while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
xmit->tail != xmit->head) {
count = 0;
@@ -1426,13 +1430,27 @@ static int cpm_uart_probe(struct platform_device *ofdev)
if (ret)
return ret;
- return uart_add_one_port(&cpm_reg, &pinfo->port);
+ ret = uart_add_one_port(&cpm_reg, &pinfo->port);
+ if (ret)
+ return ret;
+
+ uart_add_led_triggers(&cpm_reg, &pinfo->port);
+
+ return 0;
}
static int cpm_uart_remove(struct platform_device *ofdev)
{
struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
- return uart_remove_one_port(&cpm_reg, &pinfo->port);
+ int ret;
+
+ ret = uart_remove_one_port(&cpm_reg, &pinfo->port);
+ if (ret)
+ return ret;
+
+ uart_remove_led_triggers(&pinfo->port);
+
+ return 0;
}
static const struct of_device_id cpm_uart_match[] = {
--
2.10.2
^ permalink raw reply related
* [PATCH 4/4] serial: imx: Add LED trigger support
From: Sascha Hauer @ 2016-11-23 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123100106.15969-1-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/tty/serial/imx.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index a70356d..5eaf576 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -444,6 +444,8 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
return;
}
+ uart_led_trigger_tx(&sport->port);
+
if (sport->dma_is_enabled) {
/*
* We've just sent a X-char Ensure the TX DMA is enabled
@@ -569,6 +571,7 @@ static void imx_dma_tx(struct imx_port *sport)
/* fire it */
sport->dma_is_txing = 1;
dmaengine_submit(desc);
+ uart_led_trigger_tx(&sport->port);
dma_async_issue_pending(chan);
return;
}
@@ -655,6 +658,8 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
struct tty_port *port = &sport->port.state->port;
unsigned long flags, temp;
+ uart_led_trigger_rx(&sport->port);
+
spin_lock_irqsave(&sport->port.lock, flags);
while (readl(sport->port.membase + USR2) & USR2_RDR) {
@@ -729,6 +734,8 @@ static void imx_dma_rxint(struct imx_port *sport)
unsigned long temp;
unsigned long flags;
+ uart_led_trigger_rx(&sport->port);
+
spin_lock_irqsave(&sport->port.lock, flags);
temp = readl(sport->port.membase + USR2);
@@ -2184,14 +2191,27 @@ static int serial_imx_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, sport);
- return uart_add_one_port(&imx_reg, &sport->port);
+ ret = uart_add_one_port(&imx_reg, &sport->port);
+ if (ret)
+ return ret;
+
+ uart_add_led_triggers(&imx_reg, &sport->port);
+
+ return 0;
}
static int serial_imx_remove(struct platform_device *pdev)
{
struct imx_port *sport = platform_get_drvdata(pdev);
+ int ret;
- return uart_remove_one_port(&imx_reg, &sport->port);
+ ret = uart_remove_one_port(&imx_reg, &sport->port);
+ if (ret)
+ return ret;
+
+ uart_remove_led_triggers(&sport->port);
+
+ return 0;
}
static void serial_imx_restore_context(struct imx_port *sport)
--
2.10.2
^ permalink raw reply related
* [PATCH 1/3] of: base: add support to get machine compatible string
From: Sudeep Holla @ 2016-11-23 10:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ae92e013-b41b-6caa-b32f-284ffb6f5aa0@ti.com>
On 23/11/16 07:49, Sekhar Nori wrote:
> On Tuesday 22 November 2016 09:16 PM, Sudeep Holla wrote:
>> Hi Sekhar,
>>
>> On 22/11/16 15:06, Sekhar Nori wrote:
>>> Hi Sudeep,
>>>
>>> On Tuesday 22 November 2016 04:23 PM, Sudeep Holla wrote:
>>>>
>>>>
>>>> On 22/11/16 10:41, Bartosz Golaszewski wrote:
>>>>> Add a function allowing to retrieve the compatible string of the root
>>>>> node of the device tree.
>>>>>
>>>>
>>>> Rob has queued [1] and it's in -next today. You can reuse that if you
>>>> are planning to target this for v4.11 or just use open coding in your
>>>> driver for v4.10 and target this move for v4.11 to avoid cross tree
>>>> dependencies as I already mentioned in your previous thread.
>>>
>>> I dont have your original patch in my mailbox, but I wonder if
>>> returning a pointer to property string for a node whose reference has
>>> already been released is safe to do? Probably not an issue for the root
>>> node, but still feels counter-intuitive.
>>>
>>
>> I am not sure if I understand the issue here. Are you referring a case
>> where of_root is freed ?
>
> Yes, right, thats what I was hinting at. Since you are giving up the
> reference to the device node before the function returns, the user can
> be left with a dangling reference.
>
Yes I agree.
>> Also I have seen drivers today just using this pointer directly, but
>> it's better to copy the string(I just saw this done in one case)
>
> Hmm, the reference is given up before the API returns, so I doubt
> copying it later is any additional benefit.
>
True.
> I suspect this is a theoretical issue though since root device node is
> probably never freed.
>
Indeed, not sure if it's worth adding additional code to release the nod
at all call sites.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH 1/4] serial: core: Add LED trigger support
From: Greg Kroah-Hartman @ 2016-11-23 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123100106.15969-2-s.hauer@pengutronix.de>
On Wed, Nov 23, 2016 at 11:01:03AM +0100, Sascha Hauer wrote:
> With this patch the serial core provides LED triggers for RX and TX.
>
> As the serial core layer does not know when the hardware actually sends
> or receives characters, this needs help from the UART drivers. The
> LED triggers are registered in uart_add_led_triggers() called from
> the UART drivers which want to support LED triggers. All the driver
> has to do then is to call uart_led_trigger_[tx|rx] to indicate
> activity.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/tty/serial/serial_core.c | 73 ++++++++++++++++++++++++++++++++++++++++
> include/linux/serial_core.h | 10 ++++++
> 2 files changed, 83 insertions(+)
>
> diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
> index f2303f3..3e8afb7 100644
> --- a/drivers/tty/serial/serial_core.c
> +++ b/drivers/tty/serial/serial_core.c
> @@ -34,6 +34,7 @@
> #include <linux/serial_core.h>
> #include <linux/delay.h>
> #include <linux/mutex.h>
> +#include <linux/leds.h>
>
> #include <asm/irq.h>
> #include <asm/uaccess.h>
> @@ -2703,6 +2704,77 @@ static const struct attribute_group tty_dev_attr_group = {
> .attrs = tty_dev_attrs,
> };
>
> +void uart_led_trigger_tx(struct uart_port *uport)
> +{
> + unsigned long delay = 50;
> +
> + led_trigger_blink_oneshot(uport->led_trigger_tx, &delay, &delay, 0);
> +}
> +
> +void uart_led_trigger_rx(struct uart_port *uport)
> +{
> + unsigned long delay = 50;
> +
> + led_trigger_blink_oneshot(uport->led_trigger_rx, &delay, &delay, 0);
> +}
Don't these functions need an EXPORT_SYMBOL_GPL() to work properly with
uart drivers being built as a module?
thanks,
greg k-h
^ permalink raw reply
* [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible
From: Arnd Bergmann @ 2016-11-23 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123175341.4777595f@xhacker>
On Wednesday, November 23, 2016 5:53:41 PM CET Jisheng Zhang wrote:
> On Tue, 22 Nov 2016 22:04:12 +0100 Arnd Bergmann wrote:
>
> > On Tuesday, November 22, 2016 5:48:41 PM CET Gregory CLEMENT wrote:
> > > +#ifdef CONFIG_64BIT
> > > + void *data_tmp;
> > > +
> > > + /* In Neta HW only 32 bits data is supported, so in order to
> > > + * obtain whole 64 bits address from RX descriptor, we store
> > > + * the upper 32 bits when allocating buffer, and put it back
> > > + * when using buffer cookie for accessing packet in memory.
> > > + * Frags should be allocated from single 'memory' region,
> > > + * hence common upper address half should be sufficient.
> > > + */
> > > + data_tmp = mvneta_frag_alloc(pp->frag_size);
> > > + if (data_tmp) {
> > > + pp->data_high = (u64)upper_32_bits((u64)data_tmp) << 32;
> > > + mvneta_frag_free(pp->frag_size, data_tmp);
> > > + }
> > >
> >
> > How does this work when the region spans a n*4GB address boundary?
>
> indeed. We also make use of this driver on 64bit platforms. We use
> different solution to make the driver 64bit safe.
>
> solA: make use of the reserved field in the mvneta_rx_desc, such
> as reserved2 etc. Yes, the field is marked as "for future use, PnC", but
> now it's not used at all. This is one possible solution however.
Right, this sounds like the most straightforward choice.
> solB: allocate a shadow buf cookie during init, e.g
>
> rxq->descs_bufcookie = kmalloc(rxq->size * sizeof(void*), GFP_KERNEL);
>
> then modify mvneta_rx_desc_fill a bit to save the 64bit pointer in
> the shadow buf cookie, e.g
> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
> u32 phys_addr, u32 cookie,
> struct mvneta_rx_queue *rxq)
>
> {
> int i;
>
> rx_desc->buf_cookie = cookie;
> rx_desc->buf_phys_addr = phys_addr;
> i = rx_desc - rxq->descs;
> rxq->descs_bufcookie[i] = cookie;
> }
>
> then fetch the desc from the shadow buf cookie in all code path, such
> as mvneta_rx() etc.
>
> Both solutions should not have the problems pointed out by Arnd.
Wait, since you compute an index 'i' here, can't you just store 'i'
directly in the descriptor instead of the pointer?
Arnd
^ permalink raw reply
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