* [PATCH] SCPI (pre-v1.0): fix reading sensor value
From: Martin Blumenstingl @ 2016-11-24 0:18 UTC (permalink / raw)
To: linux-arm-kernel
I observed the following "strange" value when trying to read the SCPI
temperature sensor on my Amlogic GXM S912 device:
$ cat /sys/class/hwmon/hwmon0/temp1_input
6875990994467160116
The value reported by the original kernel (Amlogic vendor kernel, after
a reboot obviously) was 53C.
The Amlogic SCPI driver only uses a single 32bit value to read the
sensor value, instead of two. After stripping the upper 32bits from
above value gives "52" as result, which is basically identical to
what the vendor kernel reports.
I also compared this with the value shown by u-boot (since there's
less delay between "reboot to u-boot" compared to "reboot from mainline
kernel to vendor kernel") and the temperature reported by u-boot always
matches the lower 32bits of the value from scpi-hwmon temp1_input.
This patch introduces a separate function for reading the sensor value
on pre-v1.0 SCPI firmwares. I also tried initializing the "buf"
variable in scpi_sensor_get_value() but this didn't work (because we
request a 64bit payload from the SCPI firmware, but the firmware only
replies with a 32bit payload).
Martin Blumenstingl (1):
firmware: arm_scpi: fix reading sensor values on pre-1.0 SCPI
firmwares
drivers/firmware/arm_scpi.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--
2.10.2
^ permalink raw reply
* [PATCH] firmware: arm_scpi: fix reading sensor values on pre-1.0 SCPI firmwares
From: Martin Blumenstingl @ 2016-11-24 0:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124001845.20830-1-martin.blumenstingl@googlemail.com>
The pre-1.0 SCPI firmwares are using one __le32 as sensor value, while
the 1.0 SCPI protocol uses two __le32 as sensor values (a total of
64bit, split into 32bit upper and 32bit lower value).
Using an "struct sensor_value" to read the sensor value on a pre-1.0
SCPI firmware gives garbage in the "hi_val" field. Introducing a
separate function which handles scpi_ops.sensor_get_value for pre-1.0
SCPI firmware implementations ensures that we do not read memory which
was not written by the SCPI firmware (which fixes for example the
temperature reported by scpi-hwmon).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/firmware/arm_scpi.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
index 70e1323..19f750d 100644
--- a/drivers/firmware/arm_scpi.c
+++ b/drivers/firmware/arm_scpi.c
@@ -728,6 +728,20 @@ static int scpi_sensor_get_value(u16 sensor, u64 *val)
return ret;
}
+static int legacy_scpi_sensor_get_value(u16 sensor, u64 *val)
+{
+ __le16 id = cpu_to_le16(sensor);
+ __le32 value;
+ int ret;
+
+ ret = scpi_send_message(CMD_SENSOR_VALUE, &id, sizeof(id),
+ &value, sizeof(value));
+ if (!ret)
+ *val = le32_to_cpu(value);
+
+ return ret;
+}
+
static int scpi_device_get_power_state(u16 dev_id)
{
int ret;
@@ -960,6 +974,7 @@ static int scpi_probe(struct platform_device *pdev)
if (scpi_info->is_legacy) {
/* Replace with legacy variants */
scpi_ops.clk_set_val = legacy_scpi_clk_set_val;
+ scpi_ops.sensor_get_value = legacy_scpi_sensor_get_value;
scpi_info->commands = scpi_legacy_commands;
/* Fill priority bitmap */
--
2.10.2
^ permalink raw reply related
* [PATCH 4/6] dt-bindings: change hi6220-reset.txt according to reset-hi6220.c
From: zhangfei @ 2016-11-24 0:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123230637.m4cvc2l4huxlf5dd@rob-hp-laptop>
Hi, Rob
On 2016?11?24? 07:06, Rob Herring wrote:
> On Tue, Nov 22, 2016 at 09:48:32AM +0100, Arnd Bergmann wrote:
>> On Tuesday, November 22, 2016 3:49:19 PM CET Zhangfei Gao wrote:
>>> Required properties:
>>> - compatible: should be one of the following:
>>> - - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
>>> - - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
>>> -- reg: should be register base and length as documented in the
>>> - datasheet
>>> + - "hisilicon,hi6220-reset-sysctrl" : For peripheral reset controller.
>>> + - "hisilicon,hi6220-reset-mediactrl" : For media reset controller.
>>> +- hisi,rst-syscon: phandle of the reset's syscon.
>>> - #reset-cells: 1, see below
>>>
>> Please keep the old strings around for compatibility.
> Why are these even changing? The commit message should say why.
Have send [RFC V2:PATCH 0/2] add reset-hi3660
Not touching this file any more.
Only handle hi3660.
But hi6220 can directly use the driver.
Only need list reset info to hi6220.dts, same as hi3660.
Like
+ iomcu_rst: iomcu_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ #reset-cells = <1>;
+ hisi,rst-syscon = <&iomcu>;
+ hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */
+ 0x20 0x10 /* 1: i2c1 */
+ 0x20 0x20 /* 2: i2c2 */
+ 0x20 0x8000000>; /* 3: i2c6 */
+ };
Thanks
^ permalink raw reply
* [PATCH 2/2] clk: uniphier: add clock data for cpufreq
From: Masahiro Yamada @ 2016-11-24 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124000503.GE6095@codeaurora.org>
Hi Stephen,
2016-11-24 9:05 GMT+09:00 Stephen Boyd <sboyd@codeaurora.org>:
>> +#if 1
>> + /*
>> + * TODO:
>> + * The return type of .round_rate() is "long", which is 32 bit wide on
>> + * 32 bit systems. Clock rate greater than LONG_MAX (~ 2.15 GHz) is
>> + * treated as an error. Needs a workaround until the problem is fixed.
>> + */
>
> Just curious is the problem internal to the clk framework because
> of the clk_ops::round_rate design? Or does the consumer, cpufreq
> in this case, have to deal with rates that are larger than
> unsigned long on a 32 bit system? If it's just a clk_ops problem
> and we need to support rates up to 32 bits wide (~ 4.3 GHz) on
> the system then the driver could be changed to use
> .determine_rate() ops and that would allow us to use all the bits
> of unsigned long to figure out rates.
>
> If the problem is rates even larger than unsigned long on 32 bit
> systems, then at the least I'd like to see some sort of plan to
> fix that in the framework before merging code. Hopefully it can
> be done gradually, but as I start looking at it it seems more and
> more complicated to support this so this will be a long term
> project.
>
> We can discuss the clk API changes needed as well if those are
> required, but that is another issue that requires changes in
> other places outside of clk drivers.
>
I understand your point, but core frame-work changes
need more careful review than clk data changes in low-level drivers.
It is too late to be included in v4.10.
If I drop 32bit SoC things, and send v2 only for 64bit SoCs,
is that acceptable for 4.10-rc1?
Our ARMv8 SoCs are more actively developed, so
getting 64bit clk data in first will be helpful.
I postpone the 32bit SoC data until
I figure out the root cause of the problem
(and possible change for the API if necessary).
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [RESEND PATCH 0/6] apalis-tk1: updates for v1.1 hw
From: marcel at ziswiler.com @ 2016-11-24 1:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This series updates the device tree for the upcoming V1.1 HW samples.
All changes are purely opportunistic meaning they fix stuff which on
older HW was anyway broken so there should be no backwards
compatibility issues.
Marcel Ziswiler (6):
apalis-tk1: remove spurious new lines
apalis-tk1: temp alert pull-up
apalis-tk1: optional displayport hot-plug detect
apalis-tk1: adjust pin muxing for v1.1 hw
apalis-tk1: working sd card detect on v1.1 hw
apalis-tk1: update compatibility comment
arch/arm/boot/dts/tegra124-apalis-eval.dts | 11 +----
arch/arm/boot/dts/tegra124-apalis.dtsi | 73 +++++++++++-------------------
2 files changed, 29 insertions(+), 55 deletions(-)
--
2.9.3
^ permalink raw reply
* [RESEND PATCH 1/6] apalis-tk1: remove spurious new lines
From: marcel at ziswiler.com @ 2016-11-24 1:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Remove some spurious new lines.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis-eval.dts | 1 -
arch/arm/boot/dts/tegra124-apalis.dtsi | 12 ------------
2 files changed, 13 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index 653044a..2b5a0f3 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -232,7 +232,6 @@
backlight: backlight {
compatible = "pwm-backlight";
-
/* BKL1_PWM */
pwms = <&pwm 3 5000000>;
brightness-levels = <255 231 223 207 191 159 127 0>;
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 0819721..6aa4952 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -56,7 +56,6 @@
pcie-controller at 01003000 {
status = "okay";
-
avddio-pex-supply = <&vdd_1v05>;
avdd-pex-pll-supply = <&vdd_1v05>;
avdd-pll-erefe-supply = <&avdd_1v05>;
@@ -85,7 +84,6 @@
hdmi at 54280000 {
pll-supply = <®_1v05_avdd_hdmi_pll>;
vdd-supply = <®_3v3_avdd_hdmi>;
-
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
@@ -1607,15 +1605,11 @@
compatible = "ams,as3722";
reg = <0x40>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-
ams,system-power-controller;
-
#interrupt-cells = <2>;
interrupt-controller;
-
gpio-controller;
#gpio-cells = <2>;
-
pinctrl-names = "default";
pinctrl-0 = <&as3722_default>;
@@ -1790,7 +1784,6 @@
reg = <0x4c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
-
#thermal-sensor-cells = <1>;
};
};
@@ -1823,7 +1816,6 @@
sata at 70020000 {
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
phy-names = "sata-0";
-
avdd-supply = <&vdd_1v05>;
hvdd-supply = <®_3v3>;
vddio-supply = <&vdd_1v05>;
@@ -1837,7 +1829,6 @@
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
-
avddio-pex-supply = <&vdd_1v05>;
avdd-pll-erefe-supply = <&avdd_1v05>;
avdd-pll-utmip-supply = <&vddio_1v8>;
@@ -1919,7 +1910,6 @@
usb2-0 {
status = "okay";
mode = "otg";
-
vbus-supply = <®_usbo1_vbus>;
};
@@ -1927,7 +1917,6 @@
usb2-1 {
status = "okay";
mode = "host";
-
vbus-supply = <®_usbh_vbus>;
};
@@ -1935,7 +1924,6 @@
usb2-2 {
status = "okay";
mode = "host";
-
vbus-supply = <®_usbh_vbus>;
};
--
2.9.3
^ permalink raw reply related
* [RESEND PATCH 2/6] apalis-tk1: temp alert pull-up
From: marcel at ziswiler.com @ 2016-11-24 1:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Pull-up GPIO_PI6 connected to TMP451's ALERT#/THERM2#.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 6aa4952..0534601 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1151,11 +1151,11 @@
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- /* GPIO_PI6 aka TEMP_ALERT_L */
+ /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
pi6 {
nvidia,pins = "pi6";
nvidia,function = "rsvd1";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
--
2.9.3
^ permalink raw reply related
* [RESEND PATCH 3/6] apalis-tk1: optional displayport hot-plug detect
From: marcel at ziswiler.com @ 2016-11-24 1:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Configure DP_HPD_PFF0 pin as optional DisplayPort hot-plug detect.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 0534601..747ce81 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -255,7 +255,7 @@
};
dp_hpd_pff0 {
nvidia,pins = "dp_hpd_pff0";
- nvidia,function = "rsvd2";
+ nvidia,function = "dp";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
--
2.9.3
^ permalink raw reply related
* [RESEND PATCH 4/6] apalis-tk1: adjust pin muxing for v1.1 hw
From: marcel at ziswiler.com @ 2016-11-24 1:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Configure Apalis MMC1 D6 GPIO on SDMMC3_CLK_LB_IN as reserved function
without any pull-up/down.
Configure GPIO_PV2 as SD1_CD# according to latest V1.1 HW.
Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka
not tristated and input driver enabled as well as it features some
magic properties even though the external loopback is disabled and the
internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's
SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! This pin is
now a not-connect on V1.1 HW in order to avoid any interference.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 53 +++++++++++++++-------------------
1 file changed, 23 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 747ce81..2bfc579 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -414,18 +414,10 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
nvidia,pins = "sdmmc3_clk_lb_in_pee5";
- nvidia,function = "sdmmc3";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
@@ -520,20 +512,12 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
- sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
- nvidia,pins = "sdmmc3_clk_lb_out_pee4";
- nvidia,function = "rsvd2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ sdmmc3_cd_n_pv2 { /* CD# GPIO */
+ nvidia,pins = "sdmmc3_cd_n_pv2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Apalis SPDIF */
@@ -1512,13 +1496,6 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- sdmmc3_cd_n_pv2 { /* NC */
- nvidia,pins = "sdmmc3_cd_n_pv2";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- };
gpio_x1_aud_px1 { /* NC */
nvidia,pins = "gpio_x1_aud_px1";
nvidia,function = "rsvd2";
@@ -1568,6 +1545,22 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
+ /*
+ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
+ * driver enabled aka not tristated and input driver
+ * enabled as well as it features some magic properties
+ * even though the external loopback is disabled and the
+ * internal loopback used as per
+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+ * bits being set to 0xfffd according to the TRM!
+ */
+ sdmmc3_clk_lb_out_pee4 { /* NC */
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
};
};
--
2.9.3
^ permalink raw reply related
* [RESEND PATCH 5/6] apalis-tk1: working sd card detect on v1.1 hw
From: marcel at ziswiler.com @ 2016-11-24 1:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add sd card detect SD1_CD# applicable for V1.1 modules using GPIO_PV2.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis-eval.dts | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index 2b5a0f3..2715692 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -187,14 +187,8 @@
/* Apalis SD1 */
sdhci at 700b0400 {
status = "okay";
- /*
- * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
- * features some magic properties even though the external
- * loopback is disabled and the internal loopback used as per
- * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being
- * set to 0xfffd according to the TRM!
- * cd-gpios = <&gpio TEGRA_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
- */
+ /* SD1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
bus-width = <4>;
vqmmc-supply = <&vddio_sdmmc3>;
};
--
2.9.3
^ permalink raw reply related
* [RESEND PATCH 6/6] apalis-tk1: update compatibility comment
From: marcel at ziswiler.com @ 2016-11-24 1:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Now with the new V1.1A HW card detect being implemented update resp.
compatibility information.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 2bfc579..2276073 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -44,7 +44,7 @@
/*
* Toradex Apalis TK1 Module Device Tree
- * Compatible for Revisions 2GB: V1.0A
+ * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
*/
/ {
model = "Toradex Apalis TK1";
--
2.9.3
^ permalink raw reply related
* [RFC PATCH 0/5] arm64: Allwinner H5 support
From: Andre Przywara @ 2016-11-24 1:17 UTC (permalink / raw)
To: linux-arm-kernel
This series adds support for the recently released Allwinner H5 SoC [1] and
the Orange Pi PC 2 board [2].
This exercise is rather easy this time, since the new SoC is very similar
to the existing H3 SoC and can thus share a lot of support.
To express this, the first patch splits the H3 .dtsi to allow reusing
it later. The last two patches add the H5 .dtsi and the .dts for the
first available board featuring this chip, based on that shared base DT.
This is some early version, it's based on a merge of various -for-4.10
branches from Maxime's repository.
I can boot this on the OPi board and MMC and USB seem to work fine.
I haven't tested any other peripherals yet.
Some open issues:
- The naming: Following the Allwinner scheme this should be "sun50i-h5"
(which I use in this series), but it shares so much with the H3 that
"sun8i-h5" wouldn't be wrong either. It gets a bit weird with that shared
.dtsi, which I call sun8i-h3-h5.dtsi for now.
- The clocks and pinctrl look _almost_ similar. I may sound like a broken
record, but our habit of requiring kernel support for those almost identical
SoCs really bites us now. As the MMC got updated, I fear there is _one_
additional pin that we need for the HS400 transfer mode. Also I am afraid
the MMC clock may be slightly different due to the advanced MMC support.
At the moment this is not an issue, as the driver only support DDR50 at
most anyway, so we get away with it now.
I wonder if it's feasible to add those things to the existing H3 clocks
and pinctrl to avoid another set of drivers.
- I just see that I missed those patches that add just the names to the
binding docs. I will send them once we agreed on the naming.
Let me know what you think.
Cheers,
Andre.
[1] http://linux-sunxi.org/images/d/de/Allwinner_H5_Datasheet_V1.0.pdf
[2] http://linux-sunxi.org/Xunlong_Orange_Pi_PC_2
Andre Przywara (5):
arm: dts: sun8i: split Allwinner H3 .dtsi
dmaengine: allow sun6i-dma for more SoCs
arm64: defconfig: sunxi: include options for Allwinner H5 SoC
arm64: dts: sunxi: add Allwinner H5 .dtsi
arm64: dts: sunxi: add support for the Orange Pi PC 2 board
arch/arm/boot/dts/sun8i-h3-h5.dtsi | 519 +++++++++++++++++++++
arch/arm/boot/dts/sun8i-h3.dtsi | 465 +-----------------
arch/arm64/Kconfig.platforms | 6 +-
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 183 ++++++++
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 165 +++++++
arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi | 1 +
drivers/dma/Kconfig | 2 +-
8 files changed, 876 insertions(+), 466 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-h3-h5.dtsi
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
create mode 120000 arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi
--
2.8.2
^ permalink raw reply
* [RFC PATCH 1/5] arm: dts: sun8i: split Allwinner H3 .dtsi
From: Andre Przywara @ 2016-11-24 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479950235-26821-1-git-send-email-andre.przywara@arm.com>
The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the
Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller
updated. So we should really share almost the whole .dtsi.
In preparation for that move the peripheral parts of the existing
sun8i-h3.dtsi into a new sun8i-h3-h5.dtsi.
The actual sun8i-h3.dtsi then includes that and defines the H3 specific
parts on top of it.
On the way get rid of skeleton.dtsi, as recommended in that very file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/boot/dts/sun8i-h3-h5.dtsi | 519 +++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/sun8i-h3.dtsi | 465 +--------------------------------
2 files changed, 520 insertions(+), 464 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-h3-h5.dtsi
diff --git a/arch/arm/boot/dts/sun8i-h3-h5.dtsi b/arch/arm/boot/dts/sun8i-h3-h5.dtsi
new file mode 100644
index 0000000..2569567b
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-h5.dtsi
@@ -0,0 +1,519 @@
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ apb0: apb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk at 01f01428 {
+ compatible = "allwinner,sun8i-h3-apb0-gates-clk",
+ "allwinner,sun4i-a10-gates-clk";
+ reg = <0x01f01428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <1>;
+ clock-output-names = "apb0_pio", "apb0_ir";
+ };
+
+ ir_clk: ir_clk at 01f01454 {
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01f01454 0x4>;
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "ir";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma: dma-controller at 01c02000 {
+ compatible = "allwinner,sun8i-h3-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
+ usbphy: phy at 01c19400 {
+ compatible = "allwinner,sun8i-h3-usb-phy";
+ reg = <0x01c19400 0x2c>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>,
+ <0x01c1c800 0x4>,
+ <0x01c1d800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>,
+ <&ccu CLK_USB_PHY3>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb at 01c1b000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb at 01c1b400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb at 01c1c000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
+ resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb at 01c1c400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb at 01c1d000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1d000 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
+ resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb at 01c1d400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1d400 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pio: pinctrl at 01c20800 {
+ compatible = "allwinner,sun8i-h3-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ i2c0_pins: i2c0 {
+ allwinner,pins = "PA11", "PA12";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins: i2c1 {
+ allwinner,pins = "PA18", "PA19";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins: i2c2 {
+ allwinner,pins = "PE12", "PE13";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin: mmc0_cd_pin at 0 {
+ allwinner,pins = "PF6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_pins_a: mmc1 at 0 {
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_8bit_pins: mmc2_8bit {
+ allwinner,pins = "PC5", "PC6", "PC8",
+ "PC9", "PC10", "PC11",
+ "PC12", "PC13", "PC14",
+ "PC15", "PC16";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi0_pins: spi0 {
+ allwinner,pins = "PC0", "PC1", "PC2", "PC3";
+ allwinner,function = "spi0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi1_pins: spi1 {
+ allwinner,pins = "PA15", "PA16", "PA14", "PA13";
+ allwinner,function = "spi1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_a: uart0 at 0 {
+ allwinner,pins = "PA4", "PA5";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins: uart1 {
+ allwinner,pins = "PG6", "PG7";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_rts_cts_pins: uart1_rts_cts {
+ allwinner,pins = "PG8", "PG9";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_pins: uart2 {
+ allwinner,pins = "PA0", "PA1";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins: uart3 {
+ allwinner,pins = "PG13", "PG14";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ timer at 01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ spi0: spi at 01c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi at 01c69000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ wdt0: watchdog at 01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pwm: pwm at 01c21400 {
+ compatible = "allwinner,sun8i-h3-pwm";
+ reg = <0x01c21400 0x8>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ uart0: serial at 01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial at 01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial at 01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial at 01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c at 01c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c at 01c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c at 01c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ rtc: rtc at 01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apb0_reset: reset at 01f014b0 {
+ reg = <0x01f014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
+ ir: ir at 01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&apb0_gates 1>, <&ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apb0_reset 1>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl at 01f02c00 {
+ compatible = "allwinner,sun8i-h3-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ resets = <&apb0_reset 0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ ir_pins_a: ir at 0 {
+ allwinner,pins = "PL11";
+ allwinner,function = "s_cir_rx";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3c6596f..cdcffee 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -40,12 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
-#include <dt-bindings/clock/sun8i-h3-ccu.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include "sun8i-h3-h5.dtsi"
/ {
interrupt-parent = <&gic>;
@@ -87,68 +82,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
-
- apb0: apb0_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk at 01f01428 {
- compatible = "allwinner,sun8i-h3-apb0-gates-clk",
- "allwinner,sun4i-a10-gates-clk";
- reg = <0x01f01428 0x4>;
- #clock-cells = <1>;
- clocks = <&apb0>;
- clock-indices = <0>, <1>;
- clock-output-names = "apb0_pio", "apb0_ir";
- };
-
- ir_clk: ir_clk at 01f01454 {
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01f01454 0x4>;
- #clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>;
- clock-output-names = "ir";
- };
- };
-
soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- dma: dma-controller at 01c02000 {
- compatible = "allwinner,sun8i-h3-dma";
- reg = <0x01c02000 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DMA>;
- resets = <&ccu RST_BUS_DMA>;
- #dma-cells = <1>;
- };
-
mmc0: mmc at 01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -206,107 +140,6 @@
#size-cells = <0>;
};
- usbphy: phy at 01c19400 {
- compatible = "allwinner,sun8i-h3-usb-phy";
- reg = <0x01c19400 0x2c>,
- <0x01c1a800 0x4>,
- <0x01c1b800 0x4>,
- <0x01c1c800 0x4>,
- <0x01c1d800 0x4>;
- reg-names = "phy_ctrl",
- "pmu0",
- "pmu1",
- "pmu2",
- "pmu3";
- clocks = <&ccu CLK_USB_PHY0>,
- <&ccu CLK_USB_PHY1>,
- <&ccu CLK_USB_PHY2>,
- <&ccu CLK_USB_PHY3>;
- clock-names = "usb0_phy",
- "usb1_phy",
- "usb2_phy",
- "usb3_phy";
- resets = <&ccu RST_USB_PHY0>,
- <&ccu RST_USB_PHY1>,
- <&ccu RST_USB_PHY2>,
- <&ccu RST_USB_PHY3>;
- reset-names = "usb0_reset",
- "usb1_reset",
- "usb2_reset",
- "usb3_reset";
- status = "disabled";
- #phy-cells = <1>;
- };
-
- ehci1: usb at 01c1b000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1b000 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci1: usb at 01c1b400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1b400 0x100>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
- <&ccu CLK_USB_OHCI1>;
- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci2: usb at 01c1c000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1c000 0x100>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci2: usb at 01c1c400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1c400 0x100>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
- <&ccu CLK_USB_OHCI2>;
- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci3: usb at 01c1d000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1d000 0x100>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci3: usb at 01c1d400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1d400 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
- <&ccu CLK_USB_OHCI3>;
- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
ccu: clock at 01c20000 {
compatible = "allwinner,sun8i-h3-ccu";
reg = <0x01c20000 0x400>;
@@ -316,122 +149,6 @@
#reset-cells = <1>;
};
- pio: pinctrl at 01c20800 {
- compatible = "allwinner,sun8i-h3-pinctrl";
- reg = <0x01c20800 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
- clock-names = "apb", "hosc", "losc";
- gpio-controller;
- #gpio-cells = <3>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- i2c0_pins: i2c0 {
- allwinner,pins = "PA11", "PA12";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2c1_pins: i2c1 {
- allwinner,pins = "PA18", "PA19";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2c2_pins: i2c2 {
- allwinner,pins = "PE12", "PE13";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_pins_a: mmc0 at 0 {
- allwinner,pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_cd_pin: mmc0_cd_pin at 0 {
- allwinner,pins = "PF6";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- mmc1_pins_a: mmc1 at 0 {
- allwinner,pins = "PG0", "PG1", "PG2", "PG3",
- "PG4", "PG5";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc2_8bit_pins: mmc2_8bit {
- allwinner,pins = "PC5", "PC6", "PC8",
- "PC9", "PC10", "PC11",
- "PC12", "PC13", "PC14",
- "PC15", "PC16";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- spi0_pins: spi0 {
- allwinner,pins = "PC0", "PC1", "PC2", "PC3";
- allwinner,function = "spi0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- spi1_pins: spi1 {
- allwinner,pins = "PA15", "PA16", "PA14", "PA13";
- allwinner,function = "spi1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart0_pins_a: uart0 at 0 {
- allwinner,pins = "PA4", "PA5";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_pins: uart1 {
- allwinner,pins = "PG6", "PG7";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_rts_cts_pins: uart1_rts_cts {
- allwinner,pins = "PG8", "PG9";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart2_pins: uart2 {
- allwinner,pins = "PA0", "PA1";
- allwinner,function = "uart2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart3_pins: uart3 {
- allwinner,pins = "PG13", "PG14";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
- };
-
timer at 01c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
@@ -440,143 +157,6 @@
clocks = <&osc24M>;
};
- spi0: spi at 01c68000 {
- compatible = "allwinner,sun8i-h3-spi";
- reg = <0x01c68000 0x1000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
- clock-names = "ahb", "mod";
- dmas = <&dma 23>, <&dma 23>;
- dma-names = "rx", "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>;
- resets = <&ccu RST_BUS_SPI0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi at 01c69000 {
- compatible = "allwinner,sun8i-h3-spi";
- reg = <0x01c69000 0x1000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
- clock-names = "ahb", "mod";
- dmas = <&dma 24>, <&dma 24>;
- dma-names = "rx", "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- resets = <&ccu RST_BUS_SPI1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- wdt0: watchdog at 01c20ca0 {
- compatible = "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pwm: pwm at 01c21400 {
- compatible = "allwinner,sun8i-h3-pwm";
- reg = <0x01c21400 0x8>;
- clocks = <&osc24M>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- uart0: serial at 01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART0>;
- resets = <&ccu RST_BUS_UART0>;
- dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart1: serial at 01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART1>;
- resets = <&ccu RST_BUS_UART1>;
- dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart2: serial at 01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART2>;
- resets = <&ccu RST_BUS_UART2>;
- dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart3: serial at 01c28c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28c00 0x400>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART3>;
- resets = <&ccu RST_BUS_UART3>;
- dmas = <&dma 9>, <&dma 9>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c0: i2c at 01c2ac00 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2ac00 0x400>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C0>;
- resets = <&ccu RST_BUS_I2C0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c at 01c2b000 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C1>;
- resets = <&ccu RST_BUS_I2C1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c at 01c2b400 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C2>;
- resets = <&ccu RST_BUS_I2C2>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
gic: interrupt-controller at 01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
@@ -587,48 +167,5 @@
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
-
- rtc: rtc at 01f00000 {
- compatible = "allwinner,sun6i-a31-rtc";
- reg = <0x01f00000 0x54>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- apb0_reset: reset at 01f014b0 {
- reg = <0x01f014b0 0x4>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- #reset-cells = <1>;
- };
-
- ir: ir at 01f02000 {
- compatible = "allwinner,sun5i-a13-ir";
- clocks = <&apb0_gates 1>, <&ir_clk>;
- clock-names = "apb", "ir";
- resets = <&apb0_reset 1>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x01f02000 0x40>;
- status = "disabled";
- };
-
- r_pio: pinctrl at 01f02c00 {
- compatible = "allwinner,sun8i-h3-r-pinctrl";
- reg = <0x01f02c00 0x400>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
- clock-names = "apb", "hosc", "losc";
- resets = <&apb0_reset 0>;
- gpio-controller;
- #gpio-cells = <3>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- ir_pins_a: ir at 0 {
- allwinner,pins = "PL11";
- allwinner,function = "s_cir_rx";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
- };
};
};
--
2.8.2
^ permalink raw reply related
* [RFC PATCH 2/5] dmaengine: allow sun6i-dma for more SoCs
From: Andre Przywara @ 2016-11-24 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479950235-26821-1-git-send-email-andre.przywara@arm.com>
The sun6i DMA driver is used in the Allwinner A64 and H5 SoC, which
have arm64 capable cores. Add the generic sunxi config symbol to allow
the driver to be selected by arm64 Kconfigs, which don't feature
SoC specific MACH_xxxx configs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/dma/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index af63a6b..003c284 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -157,7 +157,7 @@ config DMA_SUN4I
config DMA_SUN6I
tristate "Allwinner A31 SoCs DMA support"
- depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST
+ depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST || ARCH_SUNXI
depends on RESET_CONTROLLER
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
--
2.8.2
^ permalink raw reply related
* [RFC PATCH 3/5] arm64: defconfig: sunxi: include options for Allwinner H5 SoC
From: Andre Przywara @ 2016-11-24 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479950235-26821-1-git-send-email-andre.przywara@arm.com>
The Allwinner H5 SoC is closely related to the H3 SoC, so select the
basic pinctrl driver and the DMA driver to let a defconfig kernel boot
on those boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/Kconfig.platforms | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index cfbdf02..8300677 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -5,8 +5,12 @@ config ARCH_SUNXI
select GENERIC_IRQ_CHIP
select PINCTRL
select PINCTRL_SUN50I_A64
+ select PINCTRL_SUN8I_H3
+ select PINCTRL_SUN8I_H3_R
+ select DMA_SUN6I
help
- This enables support for Allwinner sunxi based SoCs like the A64.
+ This enables support for Allwinner sunxi based SoCs like the A64
+ and the H5.
config ARCH_ALPINE
bool "Annapurna Labs Alpine platform"
--
2.8.2
^ permalink raw reply related
* [RFC PATCH 4/5] arm64: dts: sunxi: add Allwinner H5 .dtsi
From: Andre Przywara @ 2016-11-24 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479950235-26821-1-git-send-email-andre.przywara@arm.com>
The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses
Cortex-A53 cores instead.
Based on the now shared base .dtsi describing the common peripherals
describe the H5 specific nodes on top of that.
That symlinks in the sun8i-h3-h5.dtsi from the arch/arm tree.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 165 +++++++++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi | 1 +
2 files changed, 166 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
create mode 120000 arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
new file mode 100644
index 0000000..495edf5
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-h5.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu at 1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu at 2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu at 3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ccu: clock at 01c20000 {
+ compatible = "allwinner,sun50i-h5-ccu",
+ "allwinner,sun8i-h3-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller at 1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi
new file mode 120000
index 0000000..74f3ce9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi
@@ -0,0 +1 @@
+../../../../arm/boot/dts/sun8i-h3-h5.dtsi
\ No newline at end of file
--
2.8.2
^ permalink raw reply related
* [RFC PATCH 5/5] arm64: dts: sunxi: add support for the Orange Pi PC 2 board
From: Andre Przywara @ 2016-11-24 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479950235-26821-1-git-send-email-andre.przywara@arm.com>
The Orange Pi PC 2 is a typical single board computer using the
Allwinner H5 SoC. Apart from the usual suspects it features three
separately driven USB ports and a Gigabit Ethernet port.
Also it has a SPI NOR flash soldered, from which the board can boot
from. This enables the SBC to behave like a "real computer" with
built-in firmware.
Add the board specific .dts file, which includes the H5 .dtsi and
enables the peripherals that we support so far.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 183 +++++++++++++++++++++
2 files changed, 184 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 1e29a5a..b26bb46 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
new file mode 100644
index 0000000..a29ca6b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi PC 2";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+ pwr_led {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status_led {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ leds_opc: led_pins at 0 {
+ allwinner,pins = "PA15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_opc: led_pins at 0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_opc: key_pins at 0 {
+ allwinner,pins = "PL3";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
--
2.8.2
^ permalink raw reply related
* [PATCH] cpufreq: dt: Add support for r8a7743 and r8a7745
From: Rafael J. Wysocki @ 2016-11-24 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116100906.GA20987@vireshk-i7>
On Wednesday, November 16, 2016 03:39:06 PM Viresh Kumar wrote:
> On 16-11-16, 11:05, Geert Uytterhoeven wrote:
> > Add the compatible strings for supporting the generic cpufreq driver on
> > the Renesas RZ/G1M (r8a7743) and RZ/G1E (r8a7745) SoCs.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > Support for RZ/G1M and RZ/G1E is expected to land in v4.10.
>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Applied.
Thanks,
Rafael
^ permalink raw reply
* [alsa-devel] [PATCH v2] clkdev: add devm_of_clk_get()
From: Kuninori Morimoto @ 2016-11-24 1:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123191037.GE25626@codeaurora.org>
Hi Stephen
Thank you for your feedback
> I've seen bindings that have the 'clocks' property at the top
> level and the appropriate 'clock-names' property to relate the
> clocks to a subnode.
>
> sound_soc {
> clocks = <&xxx>, <&xxx>;
> clock-names = "cpu", "codec";
> ...
> cpu {
> ...
> };
> codec {
> ...
> };
> };
>
> Then the subnodes call clk_get() with the top level device and
> the name of their node and things match up. I suppose this
> binding is finalized though, so we can't really do that?
>
> I see that the gpio framework has a similar design called
> devm_get_gpiod_from_child(), so how about we add a
> devm_get_clk_from_child() API? That would more closely match the
> intent here, which is to restrict the clk_get() operation to
> child nodes of the device passed as the first argument.
>
> struct clk *devm_get_clk_from_child(struct device *dev,
> const char *con_id,
> struct device_node *child);
Thanks. I will check above 2 ideas.
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* [PATCH 2/2] clk: uniphier: add clock data for cpufreq
From: Stephen Boyd @ 2016-11-24 2:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK7LNAQ6XeSHd7DbvD1jWeMfOqk8+R27Q-fNDWtXxpRd=OFgjA@mail.gmail.com>
On 11/24, Masahiro Yamada wrote:
> Hi Stephen,
>
>
> 2016-11-24 9:05 GMT+09:00 Stephen Boyd <sboyd@codeaurora.org>:
>
> >> +#if 1
> >> + /*
> >> + * TODO:
> >> + * The return type of .round_rate() is "long", which is 32 bit wide on
> >> + * 32 bit systems. Clock rate greater than LONG_MAX (~ 2.15 GHz) is
> >> + * treated as an error. Needs a workaround until the problem is fixed.
> >> + */
> >
> > Just curious is the problem internal to the clk framework because
> > of the clk_ops::round_rate design? Or does the consumer, cpufreq
> > in this case, have to deal with rates that are larger than
> > unsigned long on a 32 bit system? If it's just a clk_ops problem
> > and we need to support rates up to 32 bits wide (~ 4.3 GHz) on
> > the system then the driver could be changed to use
> > .determine_rate() ops and that would allow us to use all the bits
> > of unsigned long to figure out rates.
> >
> > If the problem is rates even larger than unsigned long on 32 bit
> > systems, then at the least I'd like to see some sort of plan to
> > fix that in the framework before merging code. Hopefully it can
> > be done gradually, but as I start looking at it it seems more and
> > more complicated to support this so this will be a long term
> > project.
> >
> > We can discuss the clk API changes needed as well if those are
> > required, but that is another issue that requires changes in
> > other places outside of clk drivers.
> >
>
> I understand your point, but core frame-work changes
> need more careful review than clk data changes in low-level drivers.
> It is too late to be included in v4.10.
>
> If I drop 32bit SoC things, and send v2 only for 64bit SoCs,
> is that acceptable for 4.10-rc1?
Sure. That sounds fine for now. I'll reply to your other thread
with a plan of attack on how to do the framework changes. I think
we need to do those regardless of the outcome of your
investigation.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3] clk: qoriq: added ls1012a clock configuration
From: yuantian.tang at nxp.com @ 2016-11-24 2:36 UTC (permalink / raw)
To: linux-arm-kernel
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
v3:
- rebased to latest kernel and re-sorted the code
v2:
- remove commit message as it is duplicated to title
drivers/clk/clk-qoriq.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 7dd4351..697310e 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -291,6 +291,14 @@ static const struct clockgen_muxinfo ls1046a_hwa2 = {
},
};
+static const struct clockgen_muxinfo ls1012a_cmux = {
+ {
+ [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+ {},
+ [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+ }
+};
+
static const struct clockgen_muxinfo t1023_hwa1 = {
{
{},
@@ -529,6 +537,16 @@ static const struct clockgen_chipinfo chipinfo[] = {
.flags = CG_PLL_8BIT,
},
{
+ .compat = "fsl,ls1012a-clockgen",
+ .cmux_groups = {
+ &ls1012a_cmux
+ },
+ .cmux_to_group = {
+ 0, -1
+ },
+ .pll_mask = 0x03,
+ },
+ {
.compat = "fsl,ls2080a-clockgen",
.cmux_groups = {
&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
@@ -1316,6 +1334,7 @@ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
/* Legacy nodes */
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH v7 4/4] vcodec: mediatek: Add Maintainers entry for Mediatek JPEG driver
From: Rick Chang @ 2016-11-24 2:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479786377-11567-5-git-send-email-rick.chang@mediatek.com>
Hi Hans,
Is it possible to update this patch? or I should create another new one.
I may need to update it.
Sorry for the inconvenience.
On Tue, 2016-11-22 at 11:46 +0800, Rick Chang wrote:
> Signed-off-by: Rick Chang <rick.chang@mediatek.com>
> Signed-off-by: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
> ---
> MAINTAINERS | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 93e9f42..a9e7ee0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7818,6 +7818,13 @@ L: netdev at vger.kernel.org
> S: Maintained
> F: drivers/net/ethernet/mediatek/
>
> +MEDIATEK JPEG DRIVER
> +M: Rick Chang <rick.chang@mediatek.com>
> +M: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
> +S: Supported
> +F: drivers/media/platform/mtk-jpeg/
> +F: Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
> +
> MEDIATEK MEDIA DRIVER
> M: Tiffany Lin <tiffany.lin@mediatek.com>
> M: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
^ permalink raw reply
* [PATCH v16 13/15] acpi/arm64: Add memory-mapped timer support in GTDT driver
From: Fu Wei @ 2016-11-24 3:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CADyBb7sTVWC3d6kRDTA=SGYz9J4pwWvaJxXu3AMBAgQT4y7fTw@mail.gmail.com>
Hi Lorenzo,
On 23 November 2016 at 19:53, Fu Wei <fu.wei@linaro.org> wrote:
> Hi Lorenzo,
>
> On 18 November 2016 at 22:22, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
>> On Wed, Nov 16, 2016 at 09:49:06PM +0800, fu.wei at linaro.org wrote:
>>> From: Fu Wei <fu.wei@linaro.org>
>>>
>>> On platforms booting with ACPI, architected memory-mapped timers'
>>> configuration data is provided by firmware through the ACPI GTDT
>>> static table.
>>>
>>> The clocksource architected timer kernel driver requires a firmware
>>> interface to collect timer configuration and configure its driver.
>>> this infrastructure is present for device tree systems, but it is
>>> missing on systems booting with ACPI.
>>>
>>> Implement the kernel infrastructure required to parse the static
>>> ACPI GTDT table so that the architected timer clocksource driver can
>>> make use of it on systems booting with ACPI, therefore enabling
>>> the corresponding timers configuration.
>>>
>>> Signed-off-by: Fu Wei <fu.wei@linaro.org>
>>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>>> ---
>>> drivers/acpi/arm64/gtdt.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++
>>> include/linux/acpi.h | 1 +
>>> 2 files changed, 96 insertions(+)
>>>
>>> diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
>>> index 2de79aa..08d9506 100644
>>> --- a/drivers/acpi/arm64/gtdt.c
>>> +++ b/drivers/acpi/arm64/gtdt.c
>>> @@ -51,6 +51,14 @@ static inline bool is_timer_block(void *platform_timer)
>>> return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK;
>>> }
>>>
>>> +static inline struct acpi_gtdt_timer_block *get_timer_block(unsigned int index)
>>> +{
>>> + if (index >= acpi_gtdt_desc.timer_block_count || !timer_block)
>>> + return NULL;
>>> +
>>> + return timer_block[index];
>>> +}
>>> +
>>> static inline bool is_watchdog(void *platform_timer)
>>> {
>>> struct acpi_gtdt_header *gh = platform_timer;
>>> @@ -214,3 +222,90 @@ int __init acpi_gtdt_init(struct acpi_table_header *table)
>>> acpi_gtdt_release();
>>> return -EINVAL;
>>> }
>>> +
>>> +/*
>>> + * Get ONE GT block info for memory-mapped timer from GTDT table.
>>> + * @data: the GT block data (parsing result)
>>> + * @index: the index number of GT block
>>> + * Note: we already verify @data in caller, it can't be NULL here.
>>> + * Returns 0 if success, -EINVAL/-ENODEV if error.
>>> + */
>>
>> Documentation/kernel-doc-nano-HOWTO.txt
>
> Great thanks , will fix all the comments :-)
>
>>
>>> +int __init gtdt_arch_timer_mem_init(struct arch_timer_mem *data,
>>> + unsigned int index)
>>
>> Nit: acpi_arch_timer_mem_init() to make it consistent with other ACPI
>> calls ?
>
> yes, it makes sense, will do this way for the function which is exported
>
>>
>>> +{
>>> + struct acpi_gtdt_timer_block *block;
>>> + struct acpi_gtdt_timer_entry *frame;
>>> + int i;
>>> +
>>> + block = get_timer_block(index);
>>> + if (!block)
>>> + return -ENODEV;
>>> +
>>> + if (!block->timer_count) {
>>> + pr_err(FW_BUG "GT block present, but frame count is zero.");
>>> + return -ENODEV;
>>> + }
>>> +
>>> + if (block->timer_count > ARCH_TIMER_MEM_MAX_FRAMES) {
>>> + pr_err(FW_BUG "GT block lists %d frames, ACPI spec only allows 8\n",
>>> + block->timer_count);
>>> + return -EINVAL;
>>> + }
>>
>> Nit: these two checks can be carried out at GTDT init where the GTDT
>> is parsed first. Actually you could have two functions one to init
>
> this check is the verify the data in GT block, but the GTDT init
> won't get into the block,
> so I think that is better to keep this in GT block init function
> "acpi_arch_timer_mem_init()"
>
>> timers (say acpi_gtdt_timers_init()) and one watchdogs, that would
>> eliminate the duplicated timer_block/watchdog arrays (both sized
>> Platform Timer Count) and acpi_gtdt_timers_init() can return
>> the number of entries found so that you can loop with a determined
>> upper bound in the arm arch timer driver.
>
> Yes, I did this way in previous patchset, but we still need to do scan
> loop in both functions for
> two types of platform timer.
> So I decide to keep the scan loop in the acpi_gtdt_init to get the
> number and the entries pointer
> of each type of platform timers in one go. then we don't need to scan
> GTDT in two functions.
I have thought about this again, I think I should keep the loop in each
type of platform timers. The benefit we can get from this are:
(1) reduce the global variables:
static struct acpi_gtdt_timer_block **timer_block __initdata;
static struct acpi_gtdt_watchdog **watchdog __initdata;
make them in thire own init function.
(2) avoid allocating and free memory in different functions.
we also can return all the GT block info in one go.
>
>>
>> Just thinking aloud, these are just improvements I can carry them
>> out later, the more important question here is the interface between the
>> parsing code and the arch timer probing code which depends on other
>> patches and that needs to be agreed, this patch is not really a problem.
>
> yes, every time I modify the interface I have to change the driver :-(
>
>>
>>> + data->cntctlbase = (phys_addr_t)block->block_address;
>>> + /*
>>> + * We can NOT get the size info from GTDT table,
>>> + * but according to "Table * CNTCTLBase memory map" of
>>> + * <ARM Architecture Reference Manual> for ARMv8,
>>> + * it should be 4KB(Offset 0x000 ? 0xFFC).
>>
>> That's the reason why it is not explicit in the GTDT table :)
>>
>>> + data->size = SZ_4K;
>>> + data->num_frames = block->timer_count;
>>> +
>>> + frame = (void *)block + block->timer_offset;
>>> + if (frame + block->timer_count != (void *)block + block->header.length)
>>> + return -EINVAL;
>>> +
>>> + /*
>>> + * Get the GT timer Frame data for every GT Block Timer
>>> + */
>>> + for (i = 0; i < block->timer_count; i++, frame++) {
>>> + if (!frame->base_address || !frame->timer_interrupt)
>>> + return -EINVAL;
>>> +
>>> + data->frame[i].phys_irq = map_gt_gsi(frame->timer_interrupt,
>>> + frame->timer_flags);
>>> + if (data->frame[i].phys_irq <= 0) {
>>> + pr_warn("failed to map physical timer irq in frame %d.\n",
>>> + i);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + if (frame->virtual_timer_interrupt) {
>>> + data->frame[i].virt_irq =
>>> + map_gt_gsi(frame->virtual_timer_interrupt,
>>> + frame->virtual_timer_flags);
>>> + if (data->frame[i].virt_irq <= 0) {
>>> + pr_warn("failed to map virtual timer irq in frame %d.\n",
>>> + i);
>>> + return -EINVAL;
>>
>> You should unregister phys_irq here for correctness, right ?
>
> yup, thanks for pointing this bug out. :-)
>
>>
>>> + }
>>> + }
>>> +
>>> + data->frame[i].frame_nr = frame->frame_number;
>>> + data->frame[i].cntbase = frame->base_address;
>>> + /*
>>> + * We can NOT get the size info from GTDT table,
>>> + * but according to "Table * CNTBaseN memory map" of
>>> + * <ARM Architecture Reference Manual> for ARMv8,
>>> + * it should be 4KB(Offset 0x000 ? 0xFFC).
>>
>> See above.
>
> yes, you are right, I will fix both comments
>
>>
>>> + */
>>> + data->frame[i].size = SZ_4K;
>>> + }
>>> +
>>> + if (acpi_gtdt_desc.timer_block_count)
>>> + pr_info("parsed No.%d of %d memory-mapped timer block(s).\n",
>>> + index, acpi_gtdt_desc.timer_block_count);
>>
>> I am not sure how helpful this message can be honestly.
>
> yup, I will simplify it :-)
>
>>
>>> +
>>> + return 0;
>>> +}
>>> diff --git a/include/linux/acpi.h b/include/linux/acpi.h
>>> index a1611d1..44b8c1b 100644
>>> --- a/include/linux/acpi.h
>>> +++ b/include/linux/acpi.h
>>> @@ -582,6 +582,7 @@ int acpi_gtdt_init(struct acpi_table_header *table);
>>> int acpi_gtdt_map_ppi(int type);
>>> bool acpi_gtdt_c3stop(int type);
>>> void acpi_gtdt_release(void);
>>> +int gtdt_arch_timer_mem_init(struct arch_timer_mem *data, unsigned int index);
>>
>> See above.
>>
>> Overall it looks fine as long as the interface with clocksource is
>> settled, which is what really needs to be agreed upon in this series.
>
> Thanks for your help :-)
>
>>
>> Lorenzo
>>
>>> #endif
>>>
>>> #else /* !CONFIG_ACPI */
>>> --
>>> 2.7.4
>>>
>
>
>
> --
> Best regards,
>
> Fu Wei
> Software Engineer
> Red Hat
--
Best regards,
Fu Wei
Software Engineer
Red Hat
^ permalink raw reply
* [RFC PATCH 2/5] dmaengine: allow sun6i-dma for more SoCs
From: Chen-Yu Tsai @ 2016-11-24 4:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479950235-26821-3-git-send-email-andre.przywara@arm.com>
Hi,
On Thu, Nov 24, 2016 at 9:17 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> The sun6i DMA driver is used in the Allwinner A64 and H5 SoC, which
> have arm64 capable cores. Add the generic sunxi config symbol to allow
> the driver to be selected by arm64 Kconfigs, which don't feature
> SoC specific MACH_xxxx configs.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> drivers/dma/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index af63a6b..003c284 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -157,7 +157,7 @@ config DMA_SUN4I
>
> config DMA_SUN6I
> tristate "Allwinner A31 SoCs DMA support"
> - depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST
> + depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST || ARCH_SUNXI
AFAIK ARCH_SUNXI encompasses/supersedes MACH_SUN*I.
(And I don't have to add MACH_SUN9I later :) )
ChenYu
> depends on RESET_CONTROLLER
> select DMA_ENGINE
> select DMA_VIRTUAL_CHANNELS
> --
> 2.8.2
>
^ permalink raw reply
* [PATCH 4/4] serial: imx: Add LED trigger support
From: kbuild test robot @ 2016-11-24 4:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123100106.15969-5-s.hauer@pengutronix.de>
Hi Sascha,
[auto build test ERROR on tty/tty-testing]
[also build test ERROR on v4.9-rc6 next-20161123]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Sascha-Hauer/serial-core-Add-LED-trigger-support/20161124-010846
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing
config: s390-allmodconfig (attached as .config)
compiler: s390x-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=s390
All errors (new ones prefixed by >>):
>> ERROR: "uart_remove_led_triggers" [drivers/tty/serial/imx.ko] undefined!
>> ERROR: "uart_led_trigger_rx" [drivers/tty/serial/imx.ko] undefined!
>> ERROR: "uart_led_trigger_tx" [drivers/tty/serial/imx.ko] undefined!
>> ERROR: "uart_add_led_triggers" [drivers/tty/serial/imx.ko] undefined!
ERROR: "uart_led_trigger_rx" [drivers/tty/serial/8250/8250_base.ko] undefined!
ERROR: "uart_led_trigger_tx" [drivers/tty/serial/8250/8250_base.ko] undefined!
ERROR: "uart_remove_led_triggers" [drivers/tty/serial/8250/8250.ko] undefined!
ERROR: "uart_add_led_triggers" [drivers/tty/serial/8250/8250.ko] undefined!
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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