* [PATCH v2 1/2] arm64: dts: zx: Fix gic GICR property
From: Arnd Bergmann @ 2016-11-25 22:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017204919.GE3264@localhost>
On Monday, October 17, 2016 1:49:19 PM CET Olof Johansson wrote:
> On Thu, Oct 13, 2016 at 08:31:20PM +0800, Jun Nie wrote:
> > GICR for multiple CPU can be described with start address and stride,
> > or with multiple address. Current multiple address and stride are
> > both used. Fix it.
> >
> > vmalloc patch 727a7f5a9 triggered this bug:
> > [ 0.097146] Unable to handle kernel paging request at virtual address ffff000008060008
> > [ 0.097150] pgd = ffff000008602000
> > [ 0.097160] [ffff000008060008] *pgd=000000007fffe003, *pud=000000007fffd003, *pmd=000000007fffc003, *pte=0000000000000000
> > [ 0.097165] Internal error: Oops: 96000007 [#1] PREEMPT SMP
> > [ 0.097170] Modules linked in:
> > [ 0.097177] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.8.0+ #1474
> > [ 0.097179] Hardware name: ZTE zx296718 evaluation board (DT)
> > [ 0.097183] task: ffff80003e8c8b80 task.stack: ffff80003e8d0000
> > [ 0.097197] PC is at gic_populate_rdist+0x74/0x15c
> > [ 0.097202] LR is at gic_starting_cpu+0xc/0x20
> > [ 0.097206] pc : [<ffff0000082b1b18>] lr : [<ffff0000082b26e0>] pstate: 600001c5
> >
> > Signed-off-by: Jun Nie <jun.nie@linaro.org>
>
> A Fixes: tag would be useful on a patch like this, to tell what patch
> introduced the problem. Please consider using them in the future.
>
> I've applied this one to fixes now.
Hi Olof,
I happened to still have this one in my todo folder as I must have
missed your reply, and I stumbled over it while looking for things
that may have gone missing.
I don't see it in v4.9-rc6, did it get dropped accidentally?
Arnd
^ permalink raw reply
* [PATCH] ARM: pxa: ezx: fix a910 camera data
From: Arnd Bergmann @ 2016-11-25 22:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87inrbqr16.fsf@belgarion.home>
On Friday, November 25, 2016 8:48:53 PM CET Robert Jarzmik wrote:
> Arnd Bergmann <arnd@arndb.de> writes:
>
> > The camera_supply_dummy_device definition is shared between a780 and a910,
> > but only provided when the first is enabled and fails to build for a
> > configuration with only a910:
> >
> > arch/arm/mach-pxa/ezx.c:1097:3: error: 'camera_supply_dummy_device' undeclared here (not in a function)
> >
> > This moves the definition into its own section.
> >
> > Fixes: 6c1b417adc8f ("ARM: pxa: ezx: use the new pxa_camera platform_data")
> > Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> Ah yes, I'll queue that up in pxa/fixes.
>
> This also means that you have a test robot which beats my Jenkins, as mine
> didn't complain. Do you have a specific defconfig or is it a randconfig which
> reveals that ?
>
It showed up in randconfig builds, two out of several hundred.
I'm not surprised that nobody else caught it.
Arnd
^ permalink raw reply
* [RESEND PATCH] arm: assabet_defconfig: disable IDE subsystem
From: Arnd Bergmann @ 2016-11-25 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512445.DtnT51NQqg@amdc3058>
On Monday, October 31, 2016 7:24:46 PM CET Bartlomiej Zolnierkiewicz wrote:
> On Monday, October 31, 2016 07:14:13 PM Bartlomiej Zolnierkiewicz wrote:
> > On Monday, October 31, 2016 03:46:22 PM Russell King - ARM Linux wrote:
> > > On Wed, Oct 26, 2016 at 07:01:12PM +0200, Bartlomiej Zolnierkiewicz wrote:
> > > > > I'd be fine with just getting a pull request with all the patches that
> > > > > had no negative feedback and that were not already applied (if any).
> > > >
> > > > Here it is (sorry for taking so long).
> > >
> > > I've just been digging in the dmesg logs from when I was using the
> > > Assabet+Neponset as my firewall, and it was having to use the IDE
> > > ide-cs driver rather than the pata pcmcia driver.
> > >
> > > I don't recall whether the pata pcmcia driver was a problem or not,
> > > as the PCMCIA interface can't cope with _any_ 32-bit accesses. I
> > > think PATA tries to use the "highest" possible access size by
> > > default...
> >
> > It doesn't actually - it defaults to 16-bits for PIO data access and
> > you must explicitly enable 32-bits using ATA_PFLAG_PIO32 port flag
> > (pata_pcmcia doesn't set it so it should be okay). Also taskfile
> > registers are accessed using 8-bits access by default transport
> > functions (which are used by pata_pcmcia).
>
> Please also note that:
>
> - assebet_defconfig currently doesn't even enable ide-cs
> (CONFIG_BLK_DEV_IDECS) in the mainline kernel
>
> - neponset_defconfig doesn't even enable IDE (CONFIG_IDE)
> in the mainline kernel
>
> so there is no risk of breaking anything..
I noticed this older pull request in my todo folder, my interpretation
is that the concern was resolved and we simply missed it.
I've pulled it into next/defconfig for v4.10 now, with the above
in the merge commit text for reference.
Thanks,
Arnd
^ permalink raw reply
* [PATCH 1/2] drivers: psci: PSCI checker module
From: Arnd Bergmann @ 2016-11-25 22:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161108175547.31146-1-lorenzo.pieralisi@arm.com>
On Tuesday, November 8, 2016 5:55:46 PM CET Lorenzo Pieralisi wrote:
> From: Kevin Brodsky <kevin.brodsky@arm.com>
>
> On arm and arm64, PSCI is one of the possible firmware interfaces
> used for power management. This includes both turning CPUs on and off,
> and suspending them (entering idle states).
>
> This patch adds a PSCI checker module that enables basic testing of
> PSCI operations during startup. There are two main tests: CPU
> hotplugging and suspending.
>
> In the hotplug tests, the hotplug API is used to turn off and on again
> all CPUs in the system, and then all CPUs in each cluster, checking
> the consistency of the return codes.
>
> In the suspend tests, a high-priority thread is created on each core
> and uses low-level cpuidle functionalities to enter suspend, in all
> the possible states and multiple times. This should allow a maximum
> number of CPUs to enter the same sleep state at the same or slightly
> different time.
>
> In essence, the suspend tests use a principle similar to that of the
> intel_powerclamp driver (drivers/thermal/intel_powerclamp.c), but the
> threads are only kept for the duration of the test (they are already
> gone when userspace is started) and it does not require to stop/start
> the tick.
>
> While in theory power management PSCI functions (CPU_{ON,OFF,SUSPEND})
> could be directly called, this proved too difficult as it would imply
> the duplication of all the logic used by the kernel to allow for a
> clean shutdown/bringup/suspend of the CPU (the deepest sleep states
> implying potentially the shutdown of the CPU).
>
> Note that this file cannot be compiled as a loadable module, since it
> uses a number of non-exported identifiers (essentially for
> PSCI-specific checks and direct use of cpuidle) and relies on the
> absence of userspace to avoid races when calling hotplug and cpuidle
> functions.
>
> For now at least, CONFIG_PSCI_CHECKER is mutually exclusive with
> CONFIG_TORTURE_TEST, because torture tests may also use hotplug and
> cause false positives in the hotplug tests.
>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Kevin Hilman <khilman@kernel.org>
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Acked-by: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> [torture test config]
> Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
> [lpieralisi: added cpuidle locking, reworded commit log/kconfig entry]
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Applied both patches to the next/drivers tree in arm-soc now, sorry
for the delay,
Arnd
^ permalink raw reply
* [GIT PULL] ARM: OXNAS SoC DT updates for 4.10
From: Arnd Bergmann @ 2016-11-25 23:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <85ecb958-a6cb-bdd2-10db-873e1b894ad7@baylibre.com>
On Friday, November 4, 2016 11:26:30 AM CET Neil Armstrong wrote:
> - Add DTSI for Oxford Semiconductor OX820
> - Add DTS for Cloud Engines PogoPlug v3 board
> - Fix MAINTAINERS Oxnas entry for dts files
> from http://lkml.kernel.org/r/20161102141850.25164-1-narmstrong at baylibre.com
>
>
This one seemed to have gone missing after Olof asked for a respin
of the other oxnas branch. I've pulled it into next/dt now.
I'd probably have put the MAINTAINERS update into a different
branch (possibly even for v4.9), but it doesn't seem too important
since there was no change in the maintainers and it's unlikely
to cause conflicts.
Arnd
^ permalink raw reply
* [PATCH net-next 1/5] net: mvneta: Use cacheable memory to store the rx buffer virtual address
From: kbuild test robot @ 2016-11-25 23:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7e6004f918d3fcde9ae71e7893d26b19086236a3.1480087510.git-series.gregory.clement@free-electrons.com>
Hi Gregory,
[auto build test ERROR on ]
url: https://github.com/0day-ci/linux/commits/Gregory-CLEMENT/Support-Armada-37xx-SoC-ARMv8-64-bits-in-mvneta-driver/20161126-050621
base:
config: parisc-allmodconfig (attached as .config)
compiler: hppa-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=parisc
Note: the linux-review/Gregory-CLEMENT/Support-Armada-37xx-SoC-ARMv8-64-bits-in-mvneta-driver/20161126-050621 HEAD 5f44108a5c983ae4477f811485fdc4ee12294e72 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
vim +2745 drivers/net/ethernet/marvell/mvneta.c
2739 DMA_FROM_DEVICE);
2740 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
2741 mvneta_frag_free(pp->frag_size, data);
2742 return -ENOMEM;
2743 }
2744
> 2745 phys_addr += pp->rx_offset_correction;
2746 rx_desc->buf_phys_addr = phys_addr;
2747 rx_desc->buf_cookie = (uintptr_t)data;
2748
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [GIT PULL] arm64: dts: uniphier: UniPhier DT updates (64bit) for v4.10
From: Arnd Bergmann @ 2016-11-25 23:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK7LNASgYKnhpRM4jj1oHagK=MvO71QnbnaSr=Gt+hkV+6vxXg@mail.gmail.com>
On Sunday, November 6, 2016 12:25:15 AM CET Masahiro Yamada wrote:
> UniPhier ARM64 SoC DT updates for v4.10
>
> - Switch CPU enable-method from spin-table to PSCI
> - Add OPP tables to support generic cpufreq driver
> - Misc fixes
>
>
I don't see an email from Olof about merging this one,
for reference I have verified that he put it into the next/dt64
branch on Nov 17.
Arnd
^ permalink raw reply
* [GIT PULL]: ARM ARTPEC changes for 4.10
From: Arnd Bergmann @ 2016-11-25 23:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161110150930.GB19804@axis.com>
On Thursday, November 10, 2016 4:09:31 PM CET Jesper Nilsson wrote:
> Please pull the below signed tag for a trio of minor changes
> adding PCIe for the ARM ARTPEC SoC.
>
> Thanks!
>
> /Jesper
>
> The following changes since commit bc33b0ca11e3df467777a4fa7639ba488c9d4911:
>
> Linux 4.9-rc4 (2016-11-05 16:23:36 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/jesper/artpec.git tags/artpec-for-4.10
>
> for you to fetch changes up to fa5541fc806771a108cd2a48245a229f1ba539ea:
>
> ARM: dts: artpec: add pcie support (2016-11-10 15:51:10 +0100)
>
> ----------------------------------------------------------------
> ARTPEC changes for 4.10
>
> ----------------------------------------------------------------
> Niklas Cassel (3):
> ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6
> ARM: ARTPEC-6: add pcie related options
> ARM: dts: artpec: add pcie support
>
>
Hi Jesper and Niklas,
I just found the old pull request while going through my mail backlog.
A few things for you to remember for next time:
- please send pull requests "To: arm at kernel.org" so we know they
are destined for arm-soc
- please split up changes to the platform code from dts changes,
defconfig changes and driver changes. Each of them gets sent
to Linus in a separate arm-soc branch, so we have to pull them
in separately too
- For the signed tag, please put in a cleartext description of
the branch, just like you describe each commit in its changelog
text. The tag comment becomes the merge commit text.
- I've looked at the three patches individually and cherry-picked
the first into next/soc and the third into next/dt. The patch
"ARM: ARTPEC-6: add pcie related options" is no longer needed
after commit e13688f ("ARM: select PCI_DOMAINS config from
ARCH_MULTIPLATFORM"), so I dropped that.
Arnd
^ permalink raw reply
* [GIT PULL] ARM: at91: drivers for 4.10
From: Arnd Bergmann @ 2016-11-25 23:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114184438.k5ysd6pgcadlo5vw@piout.net>
On Monday, November 14, 2016 7:44:38 PM CET Alexandre Belloni wrote:
> Drivers for 4.10:
>
> - few fixes for the memory drivers
> - minimal security module driver
> - support for the Secure SRAM
>
For reference, Olof pulled this into next/drivers on Nov 18.
Arnd
^ permalink raw reply
* [PATCH] ARM: ixp4xx: drop duplicate header gpio.h
From: Arnd Bergmann @ 2016-11-25 23:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <319a5803aac795e175306d4978134f0247cf87bc.1479457751.git.geliangtang@gmail.com>
On Friday, November 18, 2016 10:21:10 PM CET Geliang Tang wrote:
> Drop duplicate header gpio.h from dsmg600-setup.c.
>
> Signed-off-by: Geliang Tang <geliangtang@gmail.com>
>
Applied to arm-soc/next/fixes-non-critical, thanks
Arnd
^ permalink raw reply
* [PATCH] ARM: lpc32xx: drop duplicate header device.h
From: Arnd Bergmann @ 2016-11-25 23:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479761945.1477.0.camel@localhost>
On Monday, November 21, 2016 3:59:05 PM CET Sylvain Lemieux wrote:
> On Fri, 2016-11-18 at 22:21 +0800, Geliang Tang wrote:
> > Drop duplicate header device.h from phy3250.c.
> >
> > Signed-off-by: Geliang Tang <geliangtang@gmail.com>
> Reviewed-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
>
Applied into arm-soc/next/fixes-non-critical, I see we already merged
your other pull requests, so it seems appropriate to take this
trivial change directly.
Arnd
^ permalink raw reply
* [GIT PULL v2] pxa-dt for v4.10
From: Arnd Bergmann @ 2016-11-25 23:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87mvgvsspi.fsf@belgarion.home>
On Saturday, November 19, 2016 10:51:37 AM CET Robert Jarzmik wrote:
> This device-tree pxa update brings :
> - pxa25x support
> - cpu operating points in preparation for cpufreq-dt
> - small fixes
>
Pulled into next/dt, thanks for the rework!
Arnd
^ permalink raw reply
* [GIT PULL v2] Qualcomm Device Tree Changes for v4.10
From: Arnd Bergmann @ 2016-11-25 23:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479535031-14817-1-git-send-email-andy.gross@linaro.org>
On Friday, November 18, 2016 11:57:11 PM CET Andy Gross wrote:
> Qualcomm Device Tree Changes for v4.10 - v2
>
> * Add EBI2 support to MSM8660
> * Add SMSC ethernet support to APQ8060
> * Add support for display, pstore, iommu, and hdmi to APQ8064
> * Add SDHCI node to MSM8974 Hammerhead
> * Add WP8548 MangOH board support (MDM9615)
Thanks for respinning the pull request
> ----------------------------------------------------------------
> Archit Taneja (2):
> arm: dts: qcom: apq8064: Add display DT nodes
> arm: dts: qcom: apq8064-ifc6410: Add HDMI support
>
> Bhushan Shah (1):
> ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node
>
> John Stultz (3):
> arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
> arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes
> arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7
I see that some of the subject lines are still not what they
should be, as Archit and John both used 'arm' instead of 'ARM'
as the prefix.
It doesn't seem to justify doing a v3 for that, just watch out
for merges in the future. Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [PATCH] ARM: pxa: ezx: fix a910 camera data
From: Stefan Schmidt @ 2016-11-25 23:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87eg1zqqub.fsf@belgarion.home>
Hello.
On 25.11.2016 20:53, Robert Jarzmik wrote:
> Stefan Schmidt <stefan@datenfreihafen.org> writes:
>
>> Hello.
>>
>> On 24.11.2016 17:29, Arnd Bergmann wrote:
>>> The camera_supply_dummy_device definition is shared between a780 and a910,
>>> but only provided when the first is enabled and fails to build for a
>>> configuration with only a910:
>>>
>>> arch/arm/mach-pxa/ezx.c:1097:3: error: 'camera_supply_dummy_device' undeclared here (not in a function)
>>>
>>> This moves the definition into its own section.
>>>
>>> Fixes: 6c1b417adc8f ("ARM: pxa: ezx: use the new pxa_camera platform_data")
>>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>>> ---
>>> arch/arm/mach-pxa/ezx.c | 56 ++++++++++++++++++++++++++-----------------------
>>
>> I wonder what we should do with ezx.c.
>>
>> As far as I know neither Daniel nor Harald or myself are doing anything
>> with this devices anymore. Besides a basic compile test having an ack or
>> reviewed by from our side is a bit worthless. :/
>>
>> I should still have some of these phones around in a box somewhere. If
>> there is someone with a good motivation and time to take over on this
>> platform we will find a way to get the person this devices.
>>
>> Any takers? Robert? I guess you are already overloaded but you might
>> also have an interest. Worth asking :)
> Oh yes, I'm very interested in your box. Besides I really like old platforms
> :)
Great! I should have at least 3 or 4 different devices from the EZX
platform around. I will go and search for the box over the weekend :)
>> In the case nobody wants to pick up here what would you consider the
>> bets way forward? I could send a patch removing ezx platform support
>> from the kernel (basically ezx.c plus build support) or I can send a
>> patch marking it at least orphan in MAINTAINERS. Let me know what you think.
>>
>> Daniel, Harald, if one of you is still interested in these and what to
>> pick up the work again, please speak up now. :)
> Unless another maintainer steps in, you can submit a patch to transfer the
> maintainance onto me, and we'll see off mailing lists how we could arange the
> boards transfer.
I cc'ed another developer who did a lot of work regarding EZX.
Antonio, as you can see from the mail above we are pondering what who
will maintain the ezx platform in the kernel going forward. Neither
Daniel, Harald or me is going to do so. If you have time, interest and
motivation to do so please speak up. I know life moved on and you ahve
other projects and interests so do not feel pressured here. Just say no
if you have no interest. Robert already agreed to act as a fallback so
we would still be safe. :)
regards
Stefan Schmidt
^ permalink raw reply
* [GIT PULL v2] ARM: OXNAS SoC updates for 4.10
From: Arnd Bergmann @ 2016-11-25 23:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <55c31b07-ae4e-5bb3-3576-b597805c009d@baylibre.com>
On Wednesday, November 23, 2016 10:01:08 AM CET Neil Armstrong wrote:
> - Add SMP support for the Oxford Semiconductor OX820 SoC
> from http://lkml.kernel.org/r/20161021085848.1754-1-narmstrong at baylibre.com
>
> Changes since v1 Pull Request at : http://lkml.kernel.org/r/1305c61f-b1ef-7caf-7788-67e2b907e873 at baylibre.com
> - Clarify copyright dates in commit message
> - Remove linux/arch/... lines from the top of the files
>
>
Thanks for the v2 update, pulled into next/soc now.
Arnd
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt for v4.10 (#1)
From: Arnd Bergmann @ 2016-11-25 23:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8760njamyn.fsf@free-electrons.com>
On Saturday, November 19, 2016 9:33:04 AM CET Gregory CLEMENT wrote:
> Here is the first pull request for dt for mvebu for v4.10. It repalces
> the previous one sent 2 days ago as requested by Olof.
>
> I take the opportunity to add new commits:
> "ARM: dts: kirkwood: fix spelling mistake" which as applied recently but
> which is harmless and trivial.
>
> I also add all the non controversial patches removing the DTC
> warning. They wre posted two weeks ago and was in linux-next since this
> day. As there is still some discussions about MBUS_ID and ranges, I will
> prepare a new series for them which I still hope mnage to be part of
> 4.10.
>
Pulled into next/dt, thanks for the respin!
Arnd
^ permalink raw reply
* [GIT PULL] ARM: mvebu: soc for v4.10 (#1)
From: Arnd Bergmann @ 2016-11-25 23:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <874m33ampm.fsf@free-electrons.com>
On Saturday, November 19, 2016 9:38:29 AM CET Gregory CLEMENT wrote:
> mvebu soc for 4.10 (part 1)
>
> remove legacy support of orion5x ls-chl
>
Pulled into next/soc, thanks!
Arnd
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt64 for v4.10 (#2)
From: Arnd Bergmann @ 2016-11-25 23:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8737inamem.fsf@free-electrons.com>
On Saturday, November 19, 2016 9:45:05 AM CET Gregory CLEMENT wrote:
> mvebu dt64 for 4.10 (part 2)
>
> Fix DTC warning on Armada 37xx and 7K/8K
>
Pulled into next/dt64, thanks!
Arnd
^ permalink raw reply
* [PATCH 0/4] net: thunderx: Support for 80xx, RED, PFC e.t.c
From: David Miller @ 2016-11-26 1:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479979083-15963-1-git-send-email-sunil.kovvuri@gmail.com>
From: sunil.kovvuri@gmail.com
Date: Thu, 24 Nov 2016 14:47:59 +0530
> This patch series adds support for SLM modules present on 80xx
> silicon, enables ramdom early discard, backpressure generation,
> PFC and some ethtool changes to display supported link modes e.t.c.
Series applied to net-next.
^ permalink raw reply
* net: stmmac: Meson GXBB: attempting to execute userspace memory
From: Heinrich Schuchardt @ 2016-11-26 7:53 UTC (permalink / raw)
To: linux-arm-kernel
For Odroid C2 I have compiled kernel
4.9.0-rc6-next-20161124-00001-gbf7e142
with one additional patch
https://github.com/xypron/kernel-odroid-c2/blob/master/patch/0001-stmmac-RTL8211F-Meson-GXBB-TX-throughput-problems.patch
I repeatedly see faults like the one below:
[ 2557.400796] Unhandled fault: synchronous external abort (0x92000010)
at 0x000040001e8ee4b0
[ 2557.952413] CPU: 0 PID: 22837 Comm: cc1 Tainted: G D
4.9.0-rc6-next-20161124-00001-gbf7e142 #1
[ 2557.962062] Hardware name: Hardkernel ODROID-C2 (DT)
[ 2557.966980] task: ffff80006ddb7080 task.stack: ffff80006dd9c000
[ 2557.972846] PC is at 0x6a0d98
[ 2557.975776] LR is at 0x6a0e54
[ 2557.978709] pc : [<00000000006a0d98>] lr : [<00000000006a0e54>]
pstate: 80000000
[ 2557.986040] sp : 0000fffff3ee5f80
[ 2557.989318] x29: 0000fffff3ee5f80 x28: 000040000b3f1240
[ 2557.994578] x27: 00000000012a7000 x26: 000040000b3f1288
[ 2557.999840] x25: 0000000000f58f88 x24: 000040000b3f1240
[ 2558.005101] x23: 0000000000000000 x22: 0000000000000001
[ 2558.010362] x21: 0000000000000001 x20: 000040000b3f1250
[ 2558.015623] x19: 0000000000000054 x18: 0000000000000001
[ 2558.020885] x17: 0000400008acaa10 x16: 0000000001285050
[ 2558.026146] x15: 000040000ad96dc8 x14: 000000000000001f
[ 2558.031407] x13: 000040000b3f1270 x12: 000040000b3f1258
[ 2558.036668] x11: 0000000001347000 x10: 0000000000000661
[ 2558.041930] x9 : 0000000000000005 x8 : 0000000000000003
[ 2558.047191] x7 : 000040000b3f1240 x6 : 0000000020020033
[ 2558.052452] x5 : 000040000b402020 x4 : 000040000b3e1aa0
[ 2558.057713] x3 : 000000000000000c x2 : 0000000000000020
[ 2558.062974] x1 : 0000000000f45000 x0 : 0000000000000065
[ 2558.068235]
[ 2558.069712] Internal error: Attempting to execute userspace memory:
8600000f [#7] PREEMPT SMP
[ 2558.078155] Modules linked in: meson_rng rng_core meson_gxbb_wdt
ip_tables x_tables ipv6 dwmac_generic realtek dwmac_meson8b
stmmac_platform stmmac
[ 2558.091267] CPU: 0 PID: 22837 Comm: cc1 Tainted: G D
4.9.0-rc6-next-20161124-00001-gbf7e142 #1
[ 2558.100925] Hardware name: Hardkernel ODROID-C2 (DT)
[ 2558.105841] task: ffff80006ddb7080 task.stack: ffff80006dd9c000
[ 2558.111706] PC is at 0x6a0e54
[ 2558.114638] LR is at 0x6a0e54
[ 2558.117571] pc : [<00000000006a0e54>] lr : [<00000000006a0e54>]
pstate: 600003c5
[ 2558.124902] sp : ffff80006dd9fec0
[ 2558.128179] x29: 0000000000000000 x28: ffff80006ddb7080
[ 2558.133441] x27: 00000000012a7000 x26: 000040000b3f1288
[ 2558.138702] x25: 0000000000f58f88 x24: 000040000b3f1240
[ 2558.143963] x23: 0000000080000000 x22: 00000000006a0d98
[ 2558.149225] x21: ffffffffffffffff x20: 000080006e223000
[ 2558.154486] x19: 0000000000000000 x18: 0000000000000010
[ 2558.159747] x17: 0000400008acaa10 x16: 0000000001285050
[ 2558.165008] x15: ffff000088e91f07 x14: 0000000000000006
[ 2558.170270] x13: ffff000008e91f15 x12: 000000000000000f
[ 2558.175531] x11: 0000000000000002 x10: 00000000000002ea
[ 2558.180792] x9 : ffff80006dd9fb40 x8 : 0000000000010a8b
[ 2558.186053] x7 : 0000000000000000 x6 : 000000000000020e
[ 2558.191315] x5 : 00000000020f020e x4 : 0000000000000000
[ 2558.196576] x3 : 0000000000000000 x2 : 000000000000020f
[ 2558.201837] x1 : ffff80006ddb7080 x0 : 0000000000000000
[ 2558.207098]
[ 2558.208565] Process cc1 (pid: 22837, stack limit = 0xffff80006dd9c000)
[ 2558.215035] Stack: (0xffff80006dd9fec0 to 0xffff80006dda0000)
[ 2558.220728] fec0: 0000000000000065 0000000000f45000 0000000000000020
000000000000000c
[ 2558.228490] fee0: 000040000b3e1aa0 000040000b402020 0000000020020033
000040000b3f1240
[ 2558.236253] ff00: 0000000000000003 0000000000000005 0000000000000661
0000000001347000
[ 2558.244015] ff20: 000040000b3f1258 000040000b3f1270 000000000000001f
000040000ad96dc8
[ 2558.251778] ff40: 0000000001285050 0000400008acaa10 0000000000000001
0000000000000054
[ 2558.259540] ff60: 000040000b3f1250 0000000000000001 0000000000000001
0000000000000000
[ 2558.267303] ff80: 000040000b3f1240 0000000000f58f88 000040000b3f1288
00000000012a7000
[ 2558.275065] ffa0: 000040000b3f1240 0000fffff3ee5f80 00000000006a0e54
0000fffff3ee5f80
[ 2558.282828] ffc0: 00000000006a0d98 0000000080000000 0000000000000003
ffffffffffffffff
[ 2558.290590] ffe0: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2558.298351] Call trace:
[ 2558.300769] Exception stack(0xffff80006dd9fcf0 to 0xffff80006dd9fe20)
[ 2558.307149] fce0: 0000000000000000
0001000000000000
[ 2558.314913] fd00: ffff80006dd9fec0 00000000006a0e54 ffff800073acf500
0000000000000004
[ 2558.322675] fd20: 0000000000000000 ffff000008dbbc18 ffff80006ddb7080
000000006dd9fdd0
[ 2558.330438] fd40: ffff80006dd9fd90 ffff0000080ca878 ffff80006dd9fe40
ffff80006ddb7080
[ 2558.338200] fd60: 0000000000000004 00000000000003c0 ffff80006dd9fe40
000040000b3f1240
[ 2558.345963] fd80: 0000000000f58f88 000040000b3f1288 0000000000000000
ffff80006ddb7080
[ 2558.353725] fda0: 000000000000020f 0000000000000000 0000000000000000
00000000020f020e
[ 2558.361487] fdc0: 000000000000020e 0000000000000000 0000000000010a8b
ffff80006dd9fb40
[ 2558.369250] fde0: 00000000000002ea 0000000000000002 000000000000000f
ffff000008e91f15
[ 2558.377012] fe00: 0000000000000006 ffff000088e91f07 0000000001285050
0000400008acaa10
[ 2558.384775] [<00000000006a0e54>] 0x6a0e54
[ 2558.388743] Code: d503201f f9400280 2a1703e1 97ffff0a (aa0003f3)
[ 2558.395241] ---[ end trace 7d280955c14d4ff1 ]---
[ 2558.584022] Bad mode in Error handler detected on CPU0, code
0xbf000000 -- SError
[ 2558.585871] CPU: 0 PID: 22867 Comm: cc1 Tainted: G D
4.9.0-rc6-next-20161124-00001-gbf7e142 #1
[ 2558.595527] Hardware name: Hardkernel ODROID-C2 (DT)
[ 2558.600444] task: ffff80007454d780 task.stack: ffff8000660bc000
[ 2558.606310] PC is at 0x631928
[ 2558.609240] LR is at 0xb59ce0
[ 2558.612172] pc : [<0000000000631928>] lr : [<0000000000b59ce0>]
pstate: 80000000
[ 2558.619503] sp : 0000ffffed764d90
[ 2558.622782] x29: 0000ffffed764d90 x28: 0000000000000028
[ 2558.628042] x27: 000000001a1062f0 x26: 0000000001299198
[ 2558.633303] x25: 0000000000000001 x24: 0000000000000000
[ 2558.638564] x23: 0000000000000004 x22: 00000000013513c8
[ 2558.643825] x21: 0000400039d43488 x20: 0000000000000000
[ 2558.649086] x19: 0000400039d2d730 x18: 0000000000000000
[ 2558.654348] x17: 0000400039a7c378 x16: 0000000001285138
[ 2558.659609] x15: 0000000000000001 x14: 0000000000000000
[ 2558.664870] x13: ffffff0000000000 x12: 0000000000000000
[ 2558.670131] x11: 0000000000000028 x10: 000000000129b2b8
[ 2558.675393] x9 : 0000000000000041 x8 : 0000000000000003
[ 2558.680654] x7 : 0000000000000050 x6 : 000000000003d2c8
[ 2558.685915] x5 : 0000000000000002 x4 : 0000000000000004
[ 2558.691176] x3 : 0000000000000003 x2 : 0000000001349000
[ 2558.696438] x1 : 000000000003cb90 x0 : 0000400039d45050
[ 2558.701699]
[ 2558.703177] Internal error: Attempting to execute userspace memory:
8600000f [#8] PREEMPT SMP
[ 2558.711618] Modules linked in: meson_rng rng_core meson_gxbb_wdt
ip_tables x_tables ipv6 dwmac_generic realtek dwmac_meson8b
stmmac_platform stmmac
[ 2558.724731] CPU: 0 PID: 22867 Comm: cc1 Tainted: G D
4.9.0-rc6-next-20161124-00001-gbf7e142 #1
[ 2558.734388] Hardware name: Hardkernel ODROID-C2 (DT)
[ 2558.739304] task: ffff80007454d780 task.stack: ffff8000660bc000
[ 2558.745169] PC is at 0xb59ce0
[ 2558.748102] LR is at 0xb59ce0
[ 2558.751035] pc : [<0000000000b59ce0>] lr : [<0000000000b59ce0>]
pstate: 600003c5
[ 2558.758365] sp : ffff8000660bfec0
[ 2558.761643] x29: 0000000000000000 x28: ffff80007454d780
[ 2558.766904] x27: 000000001a1062f0 x26: 0000000001299198
[ 2558.772165] x25: 0000000000000001 x24: 0000000000000000
[ 2558.777426] x23: 0000000080000000 x22: 0000000000631928
[ 2558.782688] x21: ffffffffffffffff x20: 000080006e223000
[ 2558.787949] x19: 0000000000000000 x18: 0000000000000010
[ 2558.793210] x17: 0000400039a7c378 x16: 0000000001285138
[ 2558.798471] x15: ffff000088e91f07 x14: 0000000000000006
[ 2558.803733] x13: ffff000008e91f15 x12: 000000000000000f
[ 2558.808994] x11: 0000000000000002 x10: 0000000000000336
[ 2558.814255] x9 : ffff8000660bfb40 x8 : 00000000000ab503
[ 2558.819516] x7 : 0000000000000000 x6 : 00000000000000dd
[ 2558.824778] x5 : 0000000000de00dd x4 : 0000000000000000
[ 2558.830039] x3 : 0000000000000000 x2 : 00000000000000de
[ 2558.835300] x1 : ffff80007454d780 x0 : 0000000000000000
[ 2558.840561]
[ 2558.842029] Process cc1 (pid: 22867, stack limit = 0xffff8000660bc000)
[ 2558.848498] Stack: (0xffff8000660bfec0 to 0xffff8000660c0000)
[ 2558.854191] fec0: 0000400039d45050 000000000003cb90 0000000001349000
0000000000000003
[ 2558.861953] fee0: 0000000000000004 0000000000000002 000000000003d2c8
0000000000000050
[ 2558.869716] ff00: 0000000000000003 0000000000000041 000000000129b2b8
0000000000000028
[ 2558.877478] ff20: 0000000000000000 ffffff0000000000 0000000000000000
0000000000000001
[ 2558.885241] ff40: 0000000001285138 0000400039a7c378 0000000000000000
0000400039d2d730
[ 2558.893003] ff60: 0000000000000000 0000400039d43488 00000000013513c8
0000000000000004
[ 2558.900766] ff80: 0000000000000000 0000000000000001 0000000001299198
000000001a1062f0
[ 2558.908529] ffa0: 0000000000000028 0000ffffed764d90 0000000000b59ce0
0000ffffed764d90
[ 2558.916291] ffc0: 0000000000631928 0000000080000000 000000001a18c000
ffffffffffffffff
[ 2558.924053] ffe0: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2558.931814] Call trace:
[ 2558.934232] Exception stack(0xffff8000660bfcf0 to 0xffff8000660bfe20)
[ 2558.940613] fce0: 0000000000000000
0001000000000000
[ 2558.948376] fd00: ffff8000660bfec0 0000000000b59ce0 ffff800073acf640
0000000000000004
[ 2558.956138] fd20: 0000000000000000 ffff000008dbbc18 ffff80007454d780
00000000660bfdd0
[ 2558.963901] fd40: ffff8000660bfd90 ffff0000080ca878 ffff8000660bfe40
ffff80007454d780
[ 2558.971663] fd60: 0000000000000004 00000000000003c0 ffff8000660bfe40
0000000000000000
[ 2558.979426] fd80: 0000000000000001 0000000001299198 0000000000000000
ffff80007454d780
[ 2558.987188] fda0: 00000000000000de 0000000000000000 0000000000000000
0000000000de00dd
[ 2558.994951] fdc0: 00000000000000dd 0000000000000000 00000000000ab503
ffff8000660bfb40
[ 2559.002713] fde0: 0000000000000336 0000000000000002 000000000000000f
ffff000008e91f15
[ 2559.010476] fe00: 0000000000000006 ffff000088e91f07 0000000001285138
0000400039a7c378
[ 2559.018238] [<0000000000b59ce0>] 0xb59ce0
[ 2559.022207] Code: d2800001 d2800002 d2800500 97eb5e9d (a9007c1f)
[ 2559.028376] ---[ end trace 7d280955c14d4ff2 ]---
[ 2559.034397] Bad mode in Error handler detected on CPU2, code
0xbf000000 -- SError
[ 2559.040235] CPU: 2 PID: 22866 Comm: gcc Tainted: G D
4.9.0-rc6-next-20161124-00001-gbf7e142 #1
[ 2559.049892] Hardware name: Hardkernel ODROID-C2 (DT)
[ 2559.054808] task: ffff80007454e400 task.stack: ffff80006de9c000
[ 2559.060674] PC is at 0x40003c0400d8
[ 2559.064122] LR is at 0x46d4e0
[ 2559.067055] pc : [<000040003c0400d8>] lr : [<000000000046d4e0>]
pstate: 80000000
[ 2559.074385] sp : 0000ffffe6387270
[ 2559.077664] x29: 0000ffffe6387270 x28: 0000000016c0ff90
[ 2559.082924] x27: 0000000000000002 x26: 0000000000000001
[ 2559.088185] x25: 0000ffffe63873f4 x24: 0000ffffe63873f8
[ 2559.093447] x23: 0000ffffe63873f4 x22: 0000ffffe63873f8
[ 2559.098708] x21: 0000000016c104e0 x20: 0000000000005953
[ 2559.103969] x19: 0000000000000000 [ 2559.107102] Unhandled fault:
synchronous external abort (0x96000010) at 0xffff800000c1e000
[ 2559.107108] Internal error: : 96000010 [#9] PREEMPT SMP
[ 2559.107110] Modules linked in:
[ 2559.107113] meson_rng rng_core meson_gxbb_wdt ip_tables x_tables
ipv6 dwmac_generic realtek dwmac_meson8b stmmac_platform stmmac[
2559.107131] CPU: 0 PID: 1124 Comm: mmcqd/1 Tainted: G D 1
[ 2559.107132] Hardware name: Hardkernel ODROID-C2 (DT)
[ 2559.107135] task: ffff8000704abe80 task.stack: ffff8000734d0000
[ 2559.107147] PC is at __memcpy+0x100/0x180
[ 2559.107152] LR is at sg_copy_buffer+0xb0/0x110
[ 2559.107155] pc : [<ffff00000837ee00>] lr : [<ffff00000838e928>]
pstate: 200001c5
[ 2559.107155] sp : ffff8000734d3bb0
[ 2559.107157] x29: ffff8000734d3bb0
[ 2559.107158] x28: ffff800073a14800 x27: ffff800073a14b68
[ 2559.107162] x26: 0000000000000000 x25: 0000000000000140
[ 2559.107165] x24: 0000000000000001 x23: 0000000000001000
[ 2559.107168] x22: ffff8000746a2000 x21: 0000000000001000
[ 2559.107170] x20: 0000000000000000 x19: 0000000000001000
[ 2559.107172] x18: 0000000000000000 x17: ffffffffffffffff
[ 2559.107175] x16: 00000000000006be x15: ffff000008c34000
[ 2559.107178] x14: 747962342e090a34 x13: 3278302038323162
[ 2559.107181] x12: 656c752e090a3864 x11: ffff800073866800
[ 2559.107183] x10: ffff80006bf68eb0 x9 : 0000000000000000
[ 2559.107186] x8 : ffff800073a94920 x7 : 0000000000000000
[ 2559.107188] x6 : ffff8000746a2000 x5 : 0000820000000000
[ 2559.107191] x4 : 0000000000000000 x3 : 0000000000000000
[ 2559.107193] x2 : 0000000000000f80 x1 : ffff800000c1e000
[ 2559.107196] x0 : ffff8000746a2000
[ 2559.107199] Process mmcqd/1 (pid: 1124, stack limit = 0xffff8000734d0000)
[ 2559.107202] Stack: (0xffff8000734d3bb0 to 0xffff8000734d4000)
[ 2559.107205] 3ba0: ffff8000734d3c50
ffff00000838e9bc
[ 2559.107208] 3bc0: ffff800073a14000 ffff800073a14a30 ffff80006bf68eb0
ffff800073a14a28
[ 2559.107212] 3be0: ffff800073a14818 ffff800073a14800 0000000000000000
ffff00000838e1c4
[ 2559.107215] 3c00: ffff800073a94900 ffff7e0000030780 ffff800000c1e000
0000000000001000
[ 2559.107218] 3c20: 0000000000001000 ffff800073ad0a00 0000000100000000
0000000000000001
[ 2559.107221] 3c40: 0000100000000000 0000000000000005 ffff8000734d3c60
ffff00000874c1bc
[ 2559.107224] 3c60: ffff8000734d3c70 ffff000008748010 ffff8000734d3cd0
ffff000008749908
[ 2559.107228] 3c80: ffff80006bf68eb0 ffff800073a14000 ffff8000734c8000
ffff800073a14818
[ 2559.107231] 3ca0: ffff800073a14800 ffff800073a14800 ffff80006bf68eb0
ffff800073a14a28
[ 2559.107234] 3cc0: ffff80006bf68eb0 ffff000008749bc8 ffff8000734d3d70
ffff00000874b298
[ 2559.107237] 3ce0: ffff800073a14000 ffff800073a14818 ffff8000734c8000
0000000000000000
[ 2559.107240] 3d00: ffff800073a14800 ffff800073a14800 ffff800073a13800
0000000000000000
[ 2559.107243] 3d20: ffff80006bf68eb0 0000000000000000 00000000012853f0
ffff000008c0fcb8
[ 2559.107246] 3d40: 0000000000000000 000000000835bf14 ffff000008a05f58
ffff800000000000
[ 2559.107249] 3d60: ffff8000734c8000 0000000000000001 ffff8000734d3de0
ffff00000874b6f4
[ 2559.107252] 3d80: ffff800073a14818 ffff80006bf68eb0 ffff8000734c8000
0000000000000001
[ 2559.107255] 3da0: ffff800073a14828 0000000000000000 0000000000000000
0000000000000000
[ 2559.107258] 3dc0: 0000000000000000 0000000000000000 ffff800073a14818
ffff00000874b6c4
[ 2559.107261] 3de0: ffff8000734d3e20 ffff0000080daa84 ffff800073a94980
ffff000008e8eb08
[ 2559.107264] 3e00: ffff000008b75b50 ffff800073a14818 ffff00000874b658
0000000000000000
[ 2559.107267] 3e20: 0000000000000000 ffff000008082ec0 ffff0000080da9b8
ffff800073a94980
[ 2559.107270] 3e40: 0000000000000000 0000000000000000 0000000000000000
000003ff01893600
[ 2559.107273] 3e60: ffff8000734d3ea0 0000000000000000 ffff0000080da9b8
ffff800073a14818
[ 2559.107276] 3e80: 0000000000000000 0000000000000000 ffff8000734d3e90
ffff8000734d3e90
[ 2559.107279] 3ea0: 0000000000000000 ffff000000000000 ffff8000734d3eb0
ffff8000734d3eb0
[ 2559.107281] 3ec0: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107284] 3ee0: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107287] 3f00: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107290] 3f20: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107293] 3f40: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107295] 3f60: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107298] 3f80: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107300] 3fa0: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.107303] 3fc0: 0000000000000000 0000000000000005 0000000000000000
0000000000000000
[ 2559.107306] 3fe0: 0000000000000000 0000000000000000 0000001800002cba
26000000a01b3800
[ 2559.107308] Call trace:
[ 2559.107312] Exception stack(0xffff8000734d39e0 to 0xffff8000734d3b10)
[ 2559.107315] 39e0: 0000000000001000 0001000000000000 ffff8000734d3bb0
ffff00000837ee00
[ 2559.107318] 3a00: 0000000000000007 ffff800000000000 ffff800000c1e000
0000000100100010
[ 2559.107321] 3a20: ffff8000734d3ac0 ffff000008748d88 ffff8000734d3b8c
0000000000000001
[ 2559.107324] 3a40: ffff8000734d3b40 ffff0000081c9dac ffff800074401d00
ffff0000081745d8
[ 2559.107327] 3a60: ffff7e0001b72f80 ffff80006dcbe300 00000000031fda40
0000000000000000
[ 2559.107330] 3a80: ffff8000746a2000 ffff800000c1e000 0000000000000f80
0000000000000000
[ 2559.107333] 3aa0: 0000000000000000 0000820000000000 ffff8000746a2000
0000000000000000
[ 2559.107336] 3ac0: ffff800073a94920 0000000000000000 ffff80006bf68eb0
ffff800073866800
[ 2559.107339] 3ae0: 656c752e090a3864 3278302038323162 747962342e090a34
ffff000008c34000
[ 2559.107341] 3b00: 00000000000006be ffffffffffffffff
[ 2559.107346] [<ffff00000837ee00>] __memcpy+0x100/0x180
[ 2559.107349] [<ffff00000838e9bc>] sg_copy_to_buffer+0x14/0x20
[ 2559.107357] [<ffff00000874c1bc>] mmc_queue_bounce_pre+0x34/0x40
[ 2559.107362] [<ffff000008748010>] mmc_blk_rw_rq_prep+0x288/0x3a0
[ 2559.107365] [<ffff000008749908>] mmc_blk_issue_rw_rq+0x3c0/0x998
[ 2559.107368] [<ffff00000874b298>] mmc_blk_issue_rq+0x150/0x510
[ 2559.107371] [<ffff00000874b6f4>] mmc_queue_thread+0x9c/0x140
[ 2559.107377] [<ffff0000080daa84>] kthread+0xcc/0xe0
[ 2559.107383] [<ffff000008082ec0>] ret_from_fork+0x10/0x50
[ 2559.107387] Code: d503201f d503201f d503201f d503201f (a8c12027)
[ 2559.107409] ---[ end trace 7d280955c14d4ff3 ]---
[ 2559.107417] note: mmcqd/1[1124] exited with preempt_count 1
[ 2559.688313] x18: 0000000000040900 x17: 0000000000590578 x16:
000040003c0400a8
[ 2559.695471] x15: 000000000000065c x14: 0000000000000000
[ 2559.700733] x13: 002f362f756e672d x12: 78756e696c2d3436
[ 2559.705994] x11: 0000000000000001 x10: 0101010101010101
[ 2559.711255] x9 : 0000000000000001 x8 : 0000000000000104
[ 2559.716516] x7 : 000000000046d448 x6 : 0000ffffe63873f4
[ 2559.721778] x5 : 0000ffffe63873f8 x4 : 0000000000000000
[ 2559.727039] x3 : 0000000000000000 x2 : 0000000000000000
[ 2559.732300] x1 : 0000000016c104e0 x0 : 0000000000005953
[ 2559.737561]
[ 2559.739036] Internal error: Attempting to execute userspace memory:
8600000f [#10] PREEMPT SMP
[ 2559.747566] Modules linked in: meson_rng rng_core meson_gxbb_wdt
ip_tables x_tables ipv6 dwmac_generic realtek dwmac_meson8b
stmmac_platform stmmac
[ 2559.760678] CPU: 2 PID: 22866 Comm: gcc Tainted: G D
4.9.0-rc6-next-20161124-00001-gbf7e142 #1
[ 2559.770337] Hardware name: Hardkernel ODROID-C2 (DT)
[ 2559.775254] task: ffff80007454e400 task.stack: ffff80006de9c000
[ 2559.781118] PC is at 0x46d4e0
[ 2559.784051] LR is at 0x46d4e0
[ 2559.786983] pc : [<000000000046d4e0>] lr : [<000000000046d4e0>]
pstate: 600003c5
[ 2559.794314] sp : ffff80006de9fec0
[ 2559.797591] x29: 0000000000000000 x28: ffff80007454e400
[ 2559.802853] x27: 0000000000000002 x26: 0000000000000001
[ 2559.808114] x25: 0000ffffe63873f4 x24: 0000ffffe63873f8
[ 2559.813375] x23: 0000000080000000 x22: 000040003c0400d8
[ 2559.818636] x21: ffffffffffffffff x20: 000080006e24d000
[ 2559.823898] x19: 0000000000000000 x18: 0000000000000010
[ 2559.829159] x17: 0000000000590578 x16: 000040003c0400a8
[ 2559.834420] x15: ffff000088e91f07 x14: 0000000000000006
[ 2559.839682] x13: ffff000008e91f15 x12: 000000000000000f
[ 2559.844943] x11: 0000000000000002 x10: 00000000000003f4
[ 2559.850204] x9 : ffff80006de9fb40 x8 : 00000000000b4119
[ 2559.855465] x7 : 0000000000000000 x6 : 000000000000019d
[ 2559.860726] x5 : 00000000019e019d x4 : 0000000000000000
[ 2559.865988] x3 : 0000000000000002 x2 : 000000000000019e
[ 2559.871249] x1 : ffff80007454e400 x0 : 0000000000000000
[ 2559.876510]
[ 2559.877977] Process gcc (pid: 22866, stack limit = 0xffff80006de9c000)
[ 2559.884446] Stack: (0xffff80006de9fec0 to 0xffff80006dea0000)
[ 2559.890140] fec0: 0000000000005953 0000000016c104e0 0000000000000000
0000000000000000
[ 2559.897902] fee0: 0000000000000000 0000ffffe63873f8 0000ffffe63873f4
000000000046d448
[ 2559.905664] ff00: 0000000000000104 0000000000000001 0101010101010101
0000000000000001
[ 2559.913427] ff20: 78756e696c2d3436 002f362f756e672d 0000000000000000
000000000000065c
[ 2559.921190] ff40: 000040003c0400a8 0000000000590578 0000000000040900
0000000000000000
[ 2559.928952] ff60: 0000000000005953 0000000016c104e0 0000ffffe63873f8
0000ffffe63873f4
[ 2559.936714] ff80: 0000ffffe63873f8 0000ffffe63873f4 0000000000000001
0000000000000002
[ 2559.944477] ffa0: 0000000016c0ff90 0000ffffe6387270 000000000046d4e0
0000ffffe6387270
[ 2559.952240] ffc0: 000040003c0400d8 0000000080000000 0000000000005953
ffffffffffffffff
[ 2559.960002] ffe0: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[ 2559.967762] Call trace:
[ 2559.970179] Exception stack(0xffff80006de9fcf0 to 0xffff80006de9fe20)
[ 2559.976561] fce0: 0000000000000000
0001000000000000
[ 2559.984324] fd00: ffff80006de9fec0 000000000046d4e0 ffff80007366f8c0
0000000000000004
[ 2559.992087] fd20: 0000000000000000 ffff000008dbbc18 ffff80007454e400
000000006de9fdd0
[ 2559.999850] fd40: ffff80006de9fd90 ffff0000080ca878 ffff80006de9fe40
ffff80007454e400
[ 2560.007612] fd60: 0000000000000004 00000000000003c0 ffff80006de9fe40
0000ffffe63873f8
[ 2560.015374] fd80: 0000ffffe63873f4 0000000000000001 0000000000000000
ffff80007454e400
[ 2560.023137] fda0: 000000000000019e 0000000000000002 0000000000000000
00000000019e019d
[ 2560.030899] fdc0: 000000000000019d 0000000000000000 00000000000b4119
ffff80006de9fb40
[ 2560.038662] fde0: 00000000000003f4 0000000000000002 000000000000000f
ffff000008e91f15
[ 2560.046425] fe00: 0000000000000006 ffff000088e91f07 000040003c0400a8
0000000000590578
[ 2560.054186] [<000000000046d4e0>] 0x46d4e0
[ 2560.058155] Code: aa1503e1 2a1403e0 52800002 97fe895d (2a0003e1)
[ 2560.064244] ---[ end trace 7d280955c14d4ff4 ]---
^ permalink raw reply
* [PATCH v4 0/6] arm64: arch_timer: Add workaround for hisilicon-161601 erratum
From: Ding Tianhong @ 2016-11-26 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Erratum Hisilicon-161601 says that the ARM generic timer counter "has the
potential to contain an erroneous value when the timer value changes".
Accesses to TVAL (both read and write) are also affected due to the implicit counter
read. Accesses to CVAL are not affected.
The workaround is to reread the system count registers until the value of the second
read is larger than the first one by less than 32, the system counter can be guaranteed
not to return wrong value twice by back-to-back read and the error value is always larger
than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601.
Significant rework based on feedback, including seperate the fsl erratum a008585
to another patch, update the erratum name and remove unwanted code.
v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
and make the #define __fsl_a008585_read_reg to be private to the .c file instead of
being globally visible. After discussion with Marc and Will, a consensus decision was
made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,
and make some generic name more specific, export timer_unstable_counter_workaround
for module access.
Significant rework based on feedback, including fix some alignment problem, make the
#define __hisi_161601_read_reg to be private to the .c file instead of being globally
visible, add more accurate annotation and modify a bit of logical format to enable
arch_timer_read_ool_enabled, remove the kernel commandline parameter
clocksource.arm_arch_timer.hisilicon-161601.
Introduce a generic aquick framework for erratum in ACPI mode.
v4: rename the quirk handler parameter to make it more generic, and
avoid break loop when handling the quirk becasue it need to
support multi quirks handler.
update some data structures for acpi mode.
Ding Tianhong (4):
arm64: arch_timer: Add device tree binding for hisilicon-161601
erratum
arm64: arch_timer: Introduce a generic erratum handing mechanism for
fsl-a008585
arm64: arch_timer: Work around Erratum Hisilicon-161601
arm64: arch timer: Add timer erratum property for Hip05-d02 and
Hip06-d03
Hanjun Guo (2):
arm64: arch_timer: apci: Introduce a generic aquirk framework for
erratum
arm64: arch_timer: acpi: add hisi timer errata data
Documentation/arm64/silicon-errata.txt | 1 +
.../devicetree/bindings/arm/arch_timer.txt | 8 +
Documentation/kernel-parameters.txt | 9 -
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 +
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 +
arch/arm64/include/asm/arch_timer.h | 38 ++--
drivers/clocksource/Kconfig | 9 +
drivers/clocksource/arm_arch_timer.c | 197 +++++++++++++++++----
8 files changed, 194 insertions(+), 70 deletions(-)
--
1.9.0
^ permalink raw reply
* [PATCH v4 1/6] arm64: arch_timer: Add device tree binding for hisilicon-161601 erratum
From: Ding Tianhong @ 2016-11-26 8:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480147248-12828-1-git-send-email-dingtianhong@huawei.com>
This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward. So, describe it
in the device tree.
v2: Use the new erratum name and update the description.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ef5fbe9..c27b2c4 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,14 @@ to deliver its interrupts via SPIs.
This also affects writes to the tval register, due to the implicit
counter read.
+- hisilicon,erratum-161601 : A boolean property. Indicates the presence of
+ erratum 161601, which says that reading the counter is unreliable unless
+ reading twice on the register and the value of the second read is larger
+ than the first by less than 32. If the verification is unsuccessful, then
+ discard the value of this read and repeat this procedure until the verification
+ is successful. This also affects writes to the tval register, due to the
+ implicit counter read.
+
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
--
1.9.0
^ permalink raw reply related
* [PATCH v4 2/6] arm64: arch_timer: Introduce a generic erratum handing mechanism for fsl-a008585
From: Ding Tianhong @ 2016-11-26 8:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480147248-12828-1-git-send-email-dingtianhong@huawei.com>
The workaround for hisilicon,161601 will check the return value of the system counter
by different way, in order to distinguish with the fsl-a008585 workaround, introduce
a new generic erratum handing mechanism for fsl-a008585 and rename some functions.
v2: Introducing a new generic erratum handling mechanism for fsl erratum a008585.
v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
and make the #define __fsl_a008585_read_reg to be private to the .c file instead of
being globally visible. After discussion with Marc and Will, a consensus decision was
made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,
and make some generic name more specific, export timer_unstable_counter_workaround
for module access.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/kernel-parameters.txt | 9 -----
arch/arm64/include/asm/arch_timer.h | 36 ++++++-----------
drivers/clocksource/arm_arch_timer.c | 78 +++++++++++++++++++++---------------
3 files changed, 58 insertions(+), 65 deletions(-)
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 37babf9..c9db07c 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -738,15 +738,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
loops can be debugged more effectively on production
systems.
- clocksource.arm_arch_timer.fsl-a008585=
- [ARM64]
- Format: <bool>
- Enable/disable the workaround of Freescale/NXP
- erratum A-008585. This can be useful for KVM
- guests, if the guest device tree doesn't show the
- erratum. If unspecified, the workaround is
- enabled based on the device tree.
-
clearcpuid=BITNUM [X86]
Disable CPUID feature X for the kernel. See
arch/x86/include/asm/cpufeatures.h for the valid bit
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index eaa5bbe..f882c7c 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -31,39 +31,27 @@
#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
extern struct static_key_false arch_timer_read_ool_enabled;
-#define needs_fsl_a008585_workaround() \
+#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
#else
-#define needs_fsl_a008585_workaround() false
+#define needs_unstable_timer_counter_workaround() false
#endif
-u32 __fsl_a008585_read_cntp_tval_el0(void);
-u32 __fsl_a008585_read_cntv_tval_el0(void);
-u64 __fsl_a008585_read_cntvct_el0(void);
-/*
- * The number of retries is an arbitrary value well beyond the highest number
- * of iterations the loop has been observed to take.
- */
-#define __fsl_a008585_read_reg(reg) ({ \
- u64 _old, _new; \
- int _retries = 200; \
- \
- do { \
- _old = read_sysreg(reg); \
- _new = read_sysreg(reg); \
- _retries--; \
- } while (unlikely(_old != _new) && _retries); \
- \
- WARN_ON_ONCE(!_retries); \
- _new; \
-})
+struct arch_timer_erratum_workaround {
+ int erratum; /* Indicate the Erratum ID */
+ u32 (*read_cntp_tval_el0)(void);
+ u32 (*read_cntv_tval_el0)(void);
+ u64 (*read_cntvct_el0)(void);
+};
+
+extern struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
- if (needs_fsl_a008585_workaround()) \
- _val = __fsl_a008585_read_##reg(); \
+ if (needs_unstable_timer_counter_workaround()) \
+ _val = timer_unstable_counter_workaround->read_##reg();\
else \
_val = read_sysreg(reg); \
_val; \
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 73c487d..696386f 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -95,40 +95,53 @@ static int __init early_evtstrm_cfg(char *buf)
*/
#ifdef CONFIG_FSL_ERRATUM_A008585
-DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
-EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
-
-static int fsl_a008585_enable = -1;
+struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
+EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
-static int __init early_fsl_a008585_cfg(char *buf)
-{
- int ret;
- bool val;
+#define FSL_A008585 0x0001
- ret = strtobool(buf, &val);
- if (ret)
- return ret;
-
- fsl_a008585_enable = val;
- return 0;
-}
-early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg);
+DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
+EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
-u32 __fsl_a008585_read_cntp_tval_el0(void)
+/*
+ * The number of retries is an arbitrary value well beyond the highest number
+ * of iterations the loop has been observed to take.
+ */
+#define __fsl_a008585_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 200; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely(_old != _new) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+static u32 fsl_a008585_read_cntp_tval_el0(void)
{
return __fsl_a008585_read_reg(cntp_tval_el0);
}
-u32 __fsl_a008585_read_cntv_tval_el0(void)
+static u32 fsl_a008585_read_cntv_tval_el0(void)
{
return __fsl_a008585_read_reg(cntv_tval_el0);
}
-u64 __fsl_a008585_read_cntvct_el0(void)
+static u64 fsl_a008585_read_cntvct_el0(void)
{
return __fsl_a008585_read_reg(cntvct_el0);
}
-EXPORT_SYMBOL(__fsl_a008585_read_cntvct_el0);
+
+static struct arch_timer_erratum_workaround arch_timer_fsl_a008585 = {
+ .erratum = FSL_A008585,
+ .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
+ .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+};
#endif /* CONFIG_FSL_ERRATUM_A008585 */
static __always_inline
@@ -281,7 +294,7 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
}
#ifdef CONFIG_FSL_ERRATUM_A008585
-static __always_inline void fsl_a008585_set_next_event(const int access,
+static __always_inline void erratum_set_next_event_generic(const int access,
unsigned long evt, struct clock_event_device *clk)
{
unsigned long ctrl;
@@ -299,17 +312,17 @@ static __always_inline void fsl_a008585_set_next_event(const int access,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-static int fsl_a008585_set_next_event_virt(unsigned long evt,
+static int erratum_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
return 0;
}
-static int fsl_a008585_set_next_event_phys(unsigned long evt,
+static int erratum_set_next_event_phys(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
return 0;
}
#endif /* CONFIG_FSL_ERRATUM_A008585 */
@@ -342,16 +355,16 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
return 0;
}
-static void fsl_a008585_set_sne(struct clock_event_device *clk)
+static void erratum_workaround_set_sne(struct clock_event_device *clk)
{
#ifdef CONFIG_FSL_ERRATUM_A008585
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
return;
if (arch_timer_uses_ppi == VIRT_PPI)
- clk->set_next_event = fsl_a008585_set_next_event_virt;
+ clk->set_next_event = erratum_set_next_event_virt;
else
- clk->set_next_event = fsl_a008585_set_next_event_phys;
+ clk->set_next_event = erratum_set_next_event_phys;
#endif
}
@@ -384,7 +397,7 @@ static void __arch_timer_setup(unsigned type,
BUG();
}
- fsl_a008585_set_sne(clk);
+ erratum_workaround_set_sne(clk);
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
@@ -891,9 +904,10 @@ static int __init arch_timer_of_init(struct device_node *np)
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
#ifdef CONFIG_FSL_ERRATUM_A008585
- if (fsl_a008585_enable < 0)
- fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585");
- if (fsl_a008585_enable) {
+ if (!timer_unstable_counter_workaround && of_property_read_bool(np, "fsl,erratum-a008585"))
+ timer_unstable_counter_workaround = &arch_timer_fsl_a008585;
+
+ if (timer_unstable_counter_workaround) {
static_branch_enable(&arch_timer_read_ool_enabled);
pr_info("Enabling workaround for FSL erratum A-008585\n");
}
--
1.9.0
^ permalink raw reply related
* [PATCH v4 3/6] arm64: arch_timer: Work around Erratum Hisilicon-161601
From: Ding Tianhong @ 2016-11-26 8:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480147248-12828-1-git-send-email-dingtianhong@huawei.com>
Erratum Hisilicon-161601 says that the ARM generic timer counter "has the
potential to contain an erroneous value when the timer value changes".
Accesses to TVAL (both read and write) are also affected due to the implicit counter
read. Accesses to CVAL are not affected.
The workaround is to reread the system count registers until the value of the second
read is larger than the first one by less than 32, the system counter can be guaranteed
not to return wrong value twice by back-to-back read and the error value is always larger
than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
The workaround is enabled if the hisilicon,erratum-161601 property is found in
the timer node in the device tree. This can be overridden with the
clocksource.arm_arch_timer.hisilicon-161601 boot parameter, which allows KVM
users to enable the workaround until a mechanism is implemented to
automatically communicate this information.
Fix some description for fsl erratum a008585.
v2: Significant rework based on feedback, including seperate the fsl erratum a008585
to another patch, update the erratum name and remove unwanted code.
v3: Significant rework based on feedback, including fix some alignment problem, make the
#define __hisi_161601_read_reg to be private to the .c file instead of being globally
visible, add more accurate annotation and modify a bit of logical format to enable
arch_timer_read_ool_enabled, remove the kernel commandline parameter
clocksource.arm_arch_timer.hisilicon-161601.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/include/asm/arch_timer.h | 2 +-
drivers/clocksource/Kconfig | 9 +++++
drivers/clocksource/arm_arch_timer.c | 67 +++++++++++++++++++++++++++++++---
4 files changed, 73 insertions(+), 6 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 405da11..1c1a95f 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -63,3 +63,4 @@ stable kernels.
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
+| Hisilicon | Hip0{5,6,7} | #161601 | HISILICON_ERRATUM_161601|
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index f882c7c..ebf4cde 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -29,7 +29,7 @@
#include <clocksource/arm_arch_timer.h>
-#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
extern struct static_key_false arch_timer_read_ool_enabled;
#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e2c6e43..6847ef8 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -315,6 +315,15 @@ config FSL_ERRATUM_A008585
value"). The workaround will only be active if the
fsl,erratum-a008585 property is found in the timer node.
+config HISILICON_ERRATUM_161601
+ bool "Workaround for Hisilicon Erratum 161601"
+ default y
+ depends on ARM_ARCH_TIMER && ARM64
+ help
+ This option enables a workaround for Hisilicon Erratum
+ 161601. The workaround will be active if the hisilicon,erratum-161601
+ property is found in the timer node.
+
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select CLKSRC_OF if OF
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 696386f..3d59af1 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -94,15 +94,18 @@ static int __init early_evtstrm_cfg(char *buf)
* Architected system timer support.
*/
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if CONFIG_FSL_ERRATUM_A008585 || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
#define FSL_A008585 0x0001
+#define HISILICON_161601 0x0002
DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+#endif
+#ifdef CONFIG_FSL_ERRATUM_A008585
/*
* The number of retries is an arbitrary value well beyond the highest number
* of iterations the loop has been observed to take.
@@ -144,6 +147,51 @@ static u64 fsl_a008585_read_cntvct_el0(void)
};
#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+/*
+ * Theoretically the erratum should not occur more than twice in succession,
+ * so set the retry count to 2 is sufficient here.
+ * Verify whether the value of the second read is larger than the first by
+ * less than 32 is the only way to confirm the value is correct, so clear the
+ * lower 5 bits to check whether the difference is greater than 32 or not.
+ */
+#define __hisi_161601_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 2; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely((_new - _old) >> 5) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+static u32 hisi_161601_read_cntp_tval_el0(void)
+{
+ return __hisi_161601_read_reg(cntp_tval_el0);
+}
+
+static u32 hisi_161601_read_cntv_tval_el0(void)
+{
+ return __hisi_161601_read_reg(cntv_tval_el0);
+}
+
+static u64 hisi_161601_read_cntvct_el0(void)
+{
+ return __hisi_161601_read_reg(cntvct_el0);
+}
+
+static struct arch_timer_erratum_workaround arch_timer_hisi_161601 = {
+ .erratum = HISILICON_161601,
+ .read_cntp_tval_el0 = hisi_161601_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = hisi_161601_read_cntv_tval_el0,
+ .read_cntvct_el0 = hisi_161601_read_cntvct_el0,
+};
+#endif /* CONFIG_HISILICON_ERRATUM_161601 */
+
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
struct clock_event_device *clk)
@@ -293,7 +341,7 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
static __always_inline void erratum_set_next_event_generic(const int access,
unsigned long evt, struct clock_event_device *clk)
{
@@ -357,7 +405,7 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
static void erratum_workaround_set_sne(struct clock_event_device *clk)
{
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
return;
@@ -617,7 +665,7 @@ static void __init arch_counter_register(unsigned type)
clocksource_counter.archdata.vdso_direct = true;
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
/*
* Don't use the vdso fastpath if errata require using
* the out-of-line counter accessor.
@@ -906,10 +954,19 @@ static int __init arch_timer_of_init(struct device_node *np)
#ifdef CONFIG_FSL_ERRATUM_A008585
if (!timer_unstable_counter_workaround && of_property_read_bool(np, "fsl,erratum-a008585"))
timer_unstable_counter_workaround = &arch_timer_fsl_a008585;
+#endif
+
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+ if (!timer_unstable_counter_workaround && of_property_read_bool(np, "hisilicon,erratum-161601"))
+ timer_unstable_counter_workaround = &arch_timer_hisi_161601;
+#endif
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
if (timer_unstable_counter_workaround) {
static_branch_enable(&arch_timer_read_ool_enabled);
- pr_info("Enabling workaround for FSL erratum A-008585\n");
+ pr_info("Enabling workaround for %s\n",
+ timer_unstable_counter_workaround->erratum == FSL_A008585 ?
+ "FSL ERRATUM A-008585" : "HISILICON ERRATUM 161601");
}
#endif
--
1.9.0
^ permalink raw reply related
* [PATCH v4 4/6] arm64: arch timer: Add timer erratum property for Hip05-d02 and Hip06-d03
From: Ding Tianhong @ 2016-11-26 8:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480147248-12828-1-git-send-email-dingtianhong@huawei.com>
Enable workaround for hisilicon erratum 161601 on Hip05-d02 and Hip06-d03 board.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 +
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4b472a3..a8e9969 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -281,6 +281,7 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ hisilicon,erratum-161601;
};
pmu {
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index b548763..c31f9f9 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -260,6 +260,7 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ hisilicon,erratum-161601;
};
pmu {
--
1.9.0
^ permalink raw reply related
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