* [PATCH] clocksource/arm_global_timer: reconfigure clockevents after cpufreq change
From: Alexander Kochetkov @ 2016-11-29 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480421716-30782-1-git-send-email-al.kochet@gmail.com>
After a cpufreq transition, update the clockevent's frequency
by fetching the new clock rate from the clock framework and
reprogram the next clock event.
The clock supplying the arm-global-timer on the rk3188 is coming
from the the cpu clock itself and thus changes its rate everytime
cpufreq adjusts the cpu frequency.
Found by code review, real impact not known. Assume what actual
HZ value will be different from expected on platforms using
arm-global-timer as clockevent.
The patch is port of commit 4fd7f9b12810 ("ARM: 7212/1: smp_twd:
reconfigure clockevents after cpufreq change") and
commit 2b25d9f64b54 ("ARM: 7535/1: Reprogram smp_twd based on
new common clk framework notifiers").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
---
drivers/clocksource/arm_global_timer.c | 93 +++++++++++++++++++++++++++++++-
1 file changed, 92 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c
index 8da0329..55addeb 100644
--- a/drivers/clocksource/arm_global_timer.c
+++ b/drivers/clocksource/arm_global_timer.c
@@ -49,6 +49,7 @@
* the units for all operations.
*/
static void __iomem *gt_base;
+static struct clk *gt_clk;
static unsigned long gt_clk_rate;
static int gt_ppi;
static struct clock_event_device __percpu *gt_evt;
@@ -137,6 +138,97 @@ static int gt_clockevent_set_next_event(unsigned long evt,
return 0;
}
+#ifdef CONFIG_COMMON_CLK
+
+/*
+ * Updates clockevent frequency when the cpu frequency changes.
+ * Called on the cpu that is changing frequency with interrupts disabled.
+ */
+static void gt_update_frequency(void *new_rate)
+{
+ gt_clk_rate = *((unsigned long *) new_rate);
+
+ clockevents_update_freq(raw_cpu_ptr(gt_evt), gt_clk_rate);
+}
+
+static int gt_rate_change(struct notifier_block *nb,
+ unsigned long flags, void *data)
+{
+ struct clk_notifier_data *cnd = data;
+
+ /*
+ * The gt clock events must be reprogrammed to account for the new
+ * frequency. The timer is local to a cpu, so cross-call to the
+ * changing cpu.
+ */
+ if (flags == POST_RATE_CHANGE)
+ on_each_cpu(gt_update_frequency,
+ (void *)&cnd->new_rate, 1);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block gt_clk_nb = {
+ .notifier_call = gt_rate_change,
+};
+
+static int gt_clk_init(void)
+{
+ if (gt_evt && raw_cpu_ptr(gt_evt) && !IS_ERR(gt_clk))
+ return clk_notifier_register(gt_clk, >_clk_nb);
+
+ return 0;
+}
+core_initcall(gt_clk_init);
+
+#elif defined (CONFIG_CPU_FREQ)
+
+#include <linux/cpufreq.h>
+
+/*
+ * Updates clockevent frequency when the cpu frequency changes.
+ * Called on the cpu that is changing frequency with interrupts disabled.
+ */
+static void gt_update_frequency(void *data)
+{
+ gt_clk_rate = clk_get_rate(gt_clk);
+
+ clockevents_update_freq(raw_cpu_ptr(gt_evt), gt_clk_rate);
+}
+
+static int gt_cpufreq_transition(struct notifier_block *nb,
+ unsigned long state, void *data)
+{
+ struct cpufreq_freqs *freqs = data;
+
+ /*
+ * The gt clock events must be reprogrammed to account for the new
+ * frequency. The timer is local to a cpu, so cross-call to the
+ * changing cpu.
+ */
+ if (state == CPUFREQ_POSTCHANGE)
+ smp_call_function_single(freqs->cpu, gt_update_frequency,
+ NULL, 1);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block gt_cpufreq_nb = {
+ .notifier_call = gt_cpufreq_transition,
+};
+
+static int gt_cpufreq_init(void)
+{
+ if (gt_evt && raw_cpu_ptr(gt_evt) && !IS_ERR(gt_clk))
+ return cpufreq_register_notifier(>_cpufreq_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+
+ return 0;
+}
+core_initcall(gt_cpufreq_init);
+
+#endif
+
static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
@@ -257,7 +349,6 @@ static int __init gt_clocksource_init(void)
static int __init global_timer_of_register(struct device_node *np)
{
- struct clk *gt_clk;
int err = 0;
/*
--
1.7.9.5
^ permalink raw reply related
* [PATCH] clocksource/arm_global_timer: reconfigure clockevents after cpufreq change
From: Alexander Kochetkov @ 2016-11-29 12:15 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
I found what arm-global-timer doesn't update clockevent's frequency
after cpufreq change. So I've backported two patches from
local-timer (smp_twd) to implement clockevent frequency adjustment.
Alexander Kochetkov (1):
clocksource/arm_global_timer: reconfigure clockevents after cpufreq
change
drivers/clocksource/arm_global_timer.c | 93 +++++++++++++++++++++++++++++++-
1 file changed, 92 insertions(+), 1 deletion(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH v9 08/16] drivers: acpi: iort: add node match function
From: Hanjun Guo @ 2016-11-29 12:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121100148.24769-9-lorenzo.pieralisi@arm.com>
On 2016/11/21 18:01, Lorenzo Pieralisi wrote:
> Device drivers (eg ARM SMMU) need to know if a specific component
> is part of the IORT table, so that kernel data structures are not
> initialized at initcalls time if the respective component is not
> part of the IORT table.
>
> To this end, this patch adds a trivial function that allows detecting
> if a given IORT node type is present or not in the ACPI table, providing
> an ACPI IORT equivalent for of_find_matching_node().
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Reviewed-by: Tomasz Nowicki <tn@semihalf.com>
> Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
> Tested-by: Tomasz Nowicki <tn@semihalf.com>
> Cc: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Hanjun Guo <hanjun.guo@linaro.org>
Thanks
Hanjun
^ permalink raw reply
* [PATCH V7 2/3] ACPI: Add support for ResourceSource/IRQ domain mapping
From: Lorenzo Pieralisi @ 2016-11-29 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e12155805a9d92d3f5edc81395a76f48@codeaurora.org>
Hi Agustin,
On Mon, Nov 28, 2016 at 05:40:24PM -0500, Agustin Vega-Frias wrote:
> Hi Rafael,
>
> Can you chime in on Lorenzo's feedback and the discussion below?
> It would be great if you can comment on the reason ACPI does things
> in a certain way.
>
> Hi Lorenzo,
>
> On 2016-11-25 06:40, Lorenzo Pieralisi wrote:
> >Hi Agustin,
> >
> >On Thu, Nov 24, 2016 at 04:15:48PM +0000, Lorenzo Pieralisi wrote:
> >
> >[...]
> >
> >>> @@ -448,6 +449,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
> >>> {
> >>> struct acpi_resource_irq *irq;
> >>> struct acpi_resource_extended_irq *ext_irq;
> >>> + struct fwnode_handle *src;
> >>>
> >>> switch (ares->type) {
> >>> case ACPI_RESOURCE_TYPE_IRQ:
> >>> @@ -460,7 +462,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
> >>> acpi_dev_irqresource_disabled(res, 0);
> >>> return false;
> >>> }
> >>> - acpi_dev_get_irqresource(res, irq->interrupts[index],
> >>> + acpi_dev_get_irqresource(res, irq->interrupts[index], NULL,
> >>> irq->triggering, irq->polarity,
> >>> irq->sharable, true);
> >>> break;
> >>> @@ -470,7 +472,8 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
> >>> acpi_dev_irqresource_disabled(res, 0);
> >>> return false;
> >>> }
> >>> - acpi_dev_get_irqresource(res, ext_irq->interrupts[index],
> >>> + src = acpi_get_irq_source_fwhandle(&ext_irq->resource_source);
> >>
> >>Is there a reason why we need to do the domain look-up here ?
>
> Because we need to pass the resource down to acpi_dev_get_irqresource
> which does the mapping through acpi_register_irq/acpi_register_gsi.
>
> >>
> >>I would like to understand if, by reshuffling the code (and by
> >>returning
> >>the resource_source to the calling code - somehow), it would be
> >>possible
> >>to just mirror what the OF code does in of_irq_get(), namely:
> >>
> >>(1) parse the irq entry -> of_irq_parse_one()
> >>(2) look the domain up -> irq_find_host()
> >>(3) create the mapping -> irq_create_of_mapping()
> >>
> >>You wrote the code already, I think it is just a matter of shuffling
> >>it around (well, minus returning the resource_source to the caller
> >>which is phandle equivalent in DT).
>
> This is one area in which DT and ACPI are fundamentally different. In DT
> once the flattened blob is expanded the data is fixed. In ACPI the data
> returned by a method can change. In reality most methods like CRS return
> constants, but given that per-spec they are methods the interpreter has
> to be involved, which makes it an expensive operation. I believe that is
> the reason the resource parsing code in ACPI attempts all mappings
> during
> the bus scan. Rafael can you comment on this?
>
> One way to do what you suggest would be to defer IRQ mapping by, e.g.,
> populating res->start with the HW IRQ number and res->end with the
> fwnode.
> That way we can avoid having to walk the resource buffer when a mapping
> is needed. I don't think that approach would deviate much more from
> the spec from what the current ahead-of-time mapping does, but it would
> require more changes in the core code. An alternative would be to do
> that only for resources that fail to map.
>
> >>
> >>You abstracted away (2) and (3) behind acpi_register_irq(), that
> >>on anything than does not use ACPI_GENERIC_GSI is just glue code
> >>to acpi_register_gsi().
> >>
> >>Also, it is not a question on this patch but I ask it here because it
> >>is related. On ACPI you are doing the reverse of what is done in
> >>DT in platform_get_irq():
> >>
> >>- get the resources already parsed -> platform_get_resource()
> >>- if they are disabled -> acpi_irq_get()
> >>
> >>and I think the ordering is tied to my question above because
> >>you carry out the domain look up in acpi_dev_resource_interrupt()
> >>so that if for any reason it fails the corresponding resource
> >>is disabled so that we try to get it again through acpi_irq_get().
> >>
> >>I suspect you did it this way to make sure:
> >>
> >>a) keep the current ACPI IRQ parsing interface changes to a mininum
> >>b) avoid changing the behaviour on x86/ia64; in particular, calling
> >> acpi_register_gsi() for the _same_ mapping (an IRQ that was already
> >> registered at device creation resource parsing) multiple times can
> >> trigger issues on x86/ia64
>
> You are correct about my reasons. I wanted to keep ACPI core code
> changes
> to a minimum, and I also needed to work within the current
> implementation
> which uses the pre-converted IRQ resources.
>
> >>
> >>I think that's a reasonable approach but I wanted to get these
> >>clarifications, I do not think you are far from getting this
> >>done but since it is a significant change I think it is worth
> >>discussing the points I raised above because I think the DT code
> >>sequence in of_irq_get() (1-2-3 above) is cleaner from an IRQ
> >>layer perspective (instead of having the domain look-up buried
> >>inside the ACPI IRQ resource parsing API).
> >
> >I had another look and to achieve the above one way of doing that is to
> >implement acpi_irq_get() only for ACPI_GENERIC_GSI and stub it out for
> >!ACPI_GENERIC_GSI (ie return an error code so that on !ACPI_GENERIC_GSI
> >we would fall back to current solution for ACPI). Within acpi_irq_get()
> >you can easily carry out the same steps (1->2->3) above in ACPI
> >you have
> >the code already there I think it is easy to change the
> >acpi_irq_get_cb() interface to return a filled in struct irq_fwspec and
> >the interface would become identical to of_irq_get() that is an
> >advantage to maintain it from an IRQ maintainership perspective I
> >think,
> >that's my opinion.
>
> I think I get what you mean. I'll take a stab at implementing
> acpi_irq_get()
> in the way you suggest.
>
> >
> >There is still a nagging snag though. When platform devices are
> >created, core ACPI code parse the resources through:
> >
> >acpi_dev_get_resources()
> >
> >and we _have_ to have way to avoid initializing IRQ resources that
> >have a dependency (ie there is a resource_source pointer that is valid
> >in their descriptors) that's easy to do if we think that's the right
> >thing to do and can hardly break current code (which ignores the
> >resource_source altogether).
>
> I'd rather keep the core code as-is with regard to the ahead-of-time
> conversion. Whether a resource source is available at the time of
> the bus
> scan should be transparent to the code in drivers/acpi/resource.c, and
> we need the initialization as a disabled resource to signal the need
> to retry anyway.
Yes, exactly that's the nub. Your current code works, I am trying to
make it more modular and similar to the DT/irqdomain IRQ look-up path,
which has its advantages.
There are two options IMHO:
- always disable the resource if it has a resource_source dependency and defer
its parsing to acpi_irq_get() (where you can easily implement steps 1-2-3 above).
What I wanted to say is that, by disabling the resource if it has a
resource_source dependency you can't break x86/ia64 (it is ignored at
present - hopefully there is nothing that we are not aware of behind
that choice). On x86/ia64 acpi_irq_get() would be an empty stub.
This way you would keep the irqdomain look-up out of the ACPI resource
parsing API, correct ?
- keep code as-is
Your point on _CRS being _current_ resource setting is perfectly valid
so platform_get_resource() in platform_get_irq() must always take
precedence over acpi_irq_get() (which should just apply to disabled
resources), I am not sure that doing it the other way around is safe.
> Rafael, do you have any other suggestions/feedback on how to go about
> doing this?
Yes, comments very appreciated, these changes are not trivial and need
agreement.
Thanks,
Lorenzo
>
> Thanks,
> Agustin
>
> >
> >It is an important difference with DT probing, where the IRQ
> >resources are only created if the domain reference (ie interrupt
> >controller phandle) is satisfied at of_device_alloc() time
> >(see of_device_alloc()).
> >
> >Thoughts ? Please let me know, the code to implement what I say
> >is already in these patches, it is just a matter of reshuffling it.
> >
> >Thanks !
> >Lorenzo
>
> --
> Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm
> Technologies, Inc.
> Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a
> Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH 7/10] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
From: Ziji Hu @ 2016-11-29 12:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPDyKFp=KHYogJE9WkJUYKphJhsrMfLjxxvNKmiAB+35bER4FQ@mail.gmail.com>
Hi Ulf,
On 2016/11/29 19:11, Ulf Hansson wrote:
> [...]
>
>>>>>
>>>>
>>>> Sorry that I didn't make myself clear.
>>>>
>>>> Our host PHY delay line consists of hundreds of sampling points.
>>>> Each sampling point represents a different phase shift.
>>>>
>>>> In lower speed mode, our host driver will scan the delay line.
>>>> It will select and test multiple sampling points, other than testing
>>>> only single sampling point.
>>>>
>>>> If a sampling point fails to transfer cmd/data, our host driver will
>>>> move to test next sampling point, until we find out a group of successful
>>>> sampling points which can transfer cmd/data. At last we will select
>>>> a perfect one from them.
>>>
>>> Ahh, I see. Unfortunate, this is going to be very hard to implement properly.
>>>
>>> The main problem is that the host driver has *no* knowledge about the
>>> internal state of the card, as that is the responsibility of the mmc
>>> core to keep track of.
>>>
>>> If the host driver would send a command during every update of the
>>> "ios" setting, from ->set_ios(), for sure it would lead to commands
>>> being sent that are "forbidden" in the current internal state of the
>>> card.
>>> This would lead to that the card initialization sequence fails,
>>> because the card may move to an unknown internal state and the mmc
>>> core would have no knowledge about what happened.
>>>
>>
>> Yes. In theory, host layer should not initiate a command by itself.
>>
>> We assume that bus is idle and card is stable in Tran state, when core layer
>> asks host to switch "ios".
>
> Understand, but this is a wrong assumption. The card may very well in
> another state than Tran state.
>
Could you please provide an example that card might not be in Tran state?
It seems that card should be in Tran state after CMD6 succeed.
If CMD6 fails, mmc driver will not execute ios setting. Thus ->set_ios()
will not be called.
>> Besides, we only select the commands which is valid in the whole procedure,
>> such as CMD8 for eMMC.
>> Those test commands are actually like read operations to card registers.
>> The card will return to Tran state even if transfer fails. It is also easy
>> for host to recover.
>
> For example, I would recommend you to investigate in detail the
> sequence for when a CMD6 command is sent to the card.
> The host must *not* start sending commands from ->set_ios() during a
> CMD6 sequence. For example a CMD8 is not allowed.
>
> Moreover, due to this, I wonder if it is even possible to get this HW
> to work properly.
>
In my very own opinion, ->set_ios() is only executed after CMD6 sequence
succeeds, based on current mmc.c/sd.c/sdio.c.
I personally think that it should not interfere CMD6 sequence.
I'm afraid that HW cannot help and SW driver has to take care of this.
>>
>>> Hmm..
>>>
>>> Can you specify, *exactly*, under which "ios updates" you need to
>>> verify updated PHY setting changes by sending a cmd/data? Also, please
>>> specify if it's enough to only test the CMD line or also DATA lines.
>>>
>>
>> When one of the three parameters in below changes, our host driver needs
>> to adjust PHY in lower speed mode.
>> 1. Speed Mode (timing): like legacy mode --> HS DDR
>> 2. Bus Clock: like 400KHz --> 50MHz
>> 3. Bus Width: like 1-bit --> 4-bit/8-bit
>>
>> For eMMC, we use CMD8 to test sampling point.
>> For SD, we use CMD13.
>> For SDIO, currently CMD52 is used to read a register from CCCR.
>> Those commands in above are all valid during the whole procedure to switch
>> to high speed mode from legacy mode.
>>
>> It is the best case if the test command can transfer both on CMD and DAT lines.
>> CMD8 for eMMC can test both CMD line and DAT lines. CMD13 and CMD52 only test
>> CMD line. We might use ACMD51 for SD and CMD53 for SDIO later thus DAT lines
>> are also under test.
>
> Thanks for sharing these details!
>
> So, if possible, I would recommend you to discuss these issues with
> some of the HW designers. Perhaps you can figure out an alternative
> method of confirming/testing PHY setting changes? Sending commands to
> the card just doesn't work well for all cases.
>
Thanks a lot for you patience.
Actually, we, including HW engineers, have been working on this for
a very long time. We also test a lot on many actual products. It is
quiet stable in real use scenarios.
I know it is still not good enough. It seems to be impossible to find
another practical and reliable solution, based on our tests.
Could you please provide some suggestions thus we can try our best to improve it
to meet your requirement?
Thank you.
Best regards,
Hu Ziji
> Kind regards
> Uffe
>
^ permalink raw reply
* [PATCH v2 2/2] ARM: dts: da850-lcdk: specify the maximum pixel clock rate for tilcdc
From: Bartosz Golaszewski @ 2016-11-29 11:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4f2a02c4-062f-6faf-1024-2a8718a9701f@ti.com>
2016-11-29 11:53 GMT+01:00 Sekhar Nori <nsekhar@ti.com>:
> On Monday 28 November 2016 05:45 PM, Bartosz Golaszewski wrote:
>> Due to memory throughput constraints any display mode for which the
>> pixel clock rate exceeds the recommended value of 37500 KHz must be
>> filtered out.
>
> I think there might be more reasons than memory throughput constraints
> for the reasoning behind 37.5Mhz cap on pixel clock. Why not just refer
> to the datasheet section that places this constraint so we know its a
> hardware restriction.
>
>>
>> Specify the max-pixelclock property for the display node for
>> da850-lcdk.
>>
>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> ---
>> arch/arm/boot/dts/da850-lcdk.dts | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
>> index d864f11..1283263 100644
>> --- a/arch/arm/boot/dts/da850-lcdk.dts
>> +++ b/arch/arm/boot/dts/da850-lcdk.dts
>> @@ -285,6 +285,7 @@
>>
>> &display {
>> status = "okay";
>> + max-pixelclock = <37500>;
>
> Should this not be in da850.dtsi since its an SoC imposed constraint? If
> a board needs narrower constraint, it can override it. But I guess most
> well designed boards will just hit the SoC constraint.
>
Both issues fixed in v3.
Thanks,
Bartosz Golaszewski
^ permalink raw reply
* [PATCH v3 2/2] ARM: dts: da850: specify the maximum pixel clock rate for tilcdc
From: Bartosz Golaszewski @ 2016-11-29 11:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480420624-23544-1-git-send-email-bgolaszewski@baylibre.com>
At maximum CPU frequency of 300 MHz the maximum pixel clock frequency
is 37.5 MHz[1]. We must filter out any mode for which the calculated
pixel clock rate would exceed this value.
Specify the max-pixelclock property for the display node for
da850-lcdk.
[1] http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_LCD_Controller_(LCDC)_Throughput_and_Optimization_Techniques
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/boot/dts/da850.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 5f4ba2e..00692d3 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -453,6 +453,7 @@
compatible = "ti,da850-tilcdc";
reg = <0x213000 0x1000>;
interrupts = <52>;
+ max-pixelclock = <37500>;
status = "disabled";
ports {
--
2.9.3
^ permalink raw reply related
* [PATCH v3 1/2] ARM: dts: da850-lcdk: add the dumb-vga-dac node
From: Bartosz Golaszewski @ 2016-11-29 11:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480420624-23544-1-git-send-email-bgolaszewski@baylibre.com>
Add the dumb-vga-dac node to the board DT together with corresponding
ports and vga connector. This allows to retrieve the edid info from
the display automatically.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/boot/dts/da850-lcdk.dts | 58 ++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/da850.dtsi | 17 ++++++++++++
2 files changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 711b9ad..d864f11 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -50,6 +50,53 @@
system-clock-frequency = <24576000>;
};
};
+
+ vga_bridge {
+ compatible = "dumb-vga-dac";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ vga_bridge_in: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&display_out_vga>;
+ };
+ };
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ vga_bridge_out: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ ddc-i2c-bus = <&i2c0>;
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
};
&pmx_core {
@@ -235,3 +282,14 @@
&memctrl {
status = "okay";
};
+
+&display {
+ status = "okay";
+};
+
+&display_out {
+ display_out_vga: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vga_bridge_in>;
+ };
+};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 4070619..5f4ba2e 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -454,6 +454,23 @@
reg = <0x213000 0x1000>;
interrupts = <52>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ display_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
};
aemif: aemif at 68000000 {
--
2.9.3
^ permalink raw reply related
* [PATCH v3 0/2] ARM: dts: da850: tilcdc related DT changes
From: Bartosz Golaszewski @ 2016-11-29 11:57 UTC (permalink / raw)
To: linux-arm-kernel
his series contains the last DT changes required for LCDC support
on da850-lcdk. The first one adds the dumb-vga-dac nodes, the second
limits the maximum pixel clock rate.
v1 -> v2:
- drop patch 3/3 (already merged)
- use max-pixelclock instead of max-bandwidth for display mode limiting
v2 -> v3:
- make the commit message in patch [2/2] more detailed
- move the max-pixelclock property to da850.dtsi as the limit
affects all da850-based boards
Bartosz Golaszewski (2):
ARM: dts: da850-lcdk: add the dumb-vga-dac node
ARM: dts: da850: specify the maximum pixel clock rate for tilcdc
arch/arm/boot/dts/da850-lcdk.dts | 58 ++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/da850.dtsi | 18 +++++++++++++
2 files changed, 76 insertions(+)
--
2.9.3
^ permalink raw reply
* [PATCH net-next] net: thunderx: Fix transmit queue timeout issue
From: sunil.kovvuri at gmail.com @ 2016-11-29 11:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Sunil Goutham <sgoutham@cavium.com>
Transmit queue timeout issue is seen in two cases
- Due to a race condition btw setting stop_queue at xmit()
and checking for stopped_queue in NAPI poll routine, at times
transmission from a SQ comes to a halt. This is fixed
by using barriers and also added a check for SQ free descriptors,
incase SQ is stopped and there are only CQE_RX i.e no CQE_TX.
- Contrary to an assumption, a HW errata where HW doesn't stop transmission
even though there are not enough CQEs available for a CQE_TX is
not fixed in T88 pass 2.x. This results in a Qset error with
'CQ_WR_FULL' stalling transmission. This is fixed by adjusting
RXQ's RED levels for CQ level such that there is always enough
space left for CQE_TXs.
Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
---
drivers/net/ethernet/cavium/thunder/nicvf_main.c | 52 ++++++++++++++++++----
drivers/net/ethernet/cavium/thunder/nicvf_queues.c | 24 ++--------
drivers/net/ethernet/cavium/thunder/nicvf_queues.h | 15 ++++---
3 files changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
index 1eacec8..ced1802 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
@@ -644,6 +644,7 @@ static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
struct cmp_queue *cq = &qs->cq[cq_idx];
struct cqe_rx_t *cq_desc;
struct netdev_queue *txq;
+ struct snd_queue *sq;
unsigned int tx_pkts = 0, tx_bytes = 0;
spin_lock_bh(&cq->lock);
@@ -709,16 +710,20 @@ static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
done:
/* Wakeup TXQ if its stopped earlier due to SQ full */
- if (tx_done) {
+ sq = &nic->qs->sq[cq_idx];
+ if (tx_done ||
+ (atomic_read(&sq->free_cnt) >= MIN_SQ_DESC_PER_PKT_XMIT)) {
netdev = nic->pnicvf->netdev;
txq = netdev_get_tx_queue(netdev,
nicvf_netdev_qidx(nic, cq_idx));
if (tx_pkts)
netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
- nic = nic->pnicvf;
+ /* To read updated queue and carrier status */
+ smp_mb();
if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {
- netif_tx_start_queue(txq);
+ netif_tx_wake_queue(txq);
+ nic = nic->pnicvf;
this_cpu_inc(nic->drv_stats->txq_wake);
if (netif_msg_tx_err(nic))
netdev_warn(netdev,
@@ -1054,6 +1059,9 @@ static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
struct nicvf *nic = netdev_priv(netdev);
int qid = skb_get_queue_mapping(skb);
struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
+ struct nicvf *snic;
+ struct snd_queue *sq;
+ int tmp;
/* Check for minimum packet length */
if (skb->len <= ETH_HLEN) {
@@ -1061,13 +1069,39 @@ static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
return NETDEV_TX_OK;
}
- if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) {
+ snic = nic;
+ /* Get secondary Qset's SQ structure */
+ if (qid >= MAX_SND_QUEUES_PER_QS) {
+ tmp = qid / MAX_SND_QUEUES_PER_QS;
+ snic = (struct nicvf *)nic->snicvf[tmp - 1];
+ if (!snic) {
+ netdev_warn(nic->netdev,
+ "Secondary Qset#%d's ptr not initialized\n",
+ tmp - 1);
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+ }
+ qid = qid % MAX_SND_QUEUES_PER_QS;
+ }
+
+ sq = &snic->qs->sq[qid];
+ if (!netif_tx_queue_stopped(txq) &&
+ !nicvf_sq_append_skb(snic, sq, skb, qid)) {
netif_tx_stop_queue(txq);
- this_cpu_inc(nic->drv_stats->txq_stop);
- if (netif_msg_tx_err(nic))
- netdev_warn(netdev,
- "%s: Transmit ring full, stopping SQ%d\n",
- netdev->name, qid);
+
+ /* Barrier, so that stop_queue visible to other cpus */
+ smp_mb();
+
+ /* Check again, incase another cpu freed descriptors */
+ if (atomic_read(&sq->free_cnt) > MIN_SQ_DESC_PER_PKT_XMIT) {
+ netif_tx_start_queue(txq);
+ } else {
+ this_cpu_inc(nic->drv_stats->txq_stop);
+ if (netif_msg_tx_err(nic))
+ netdev_warn(netdev,
+ "%s: Transmit ring full, stopping SQ%d\n",
+ netdev->name, qid);
+ }
return NETDEV_TX_BUSY;
}
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
index 7b336cd..d2ac133 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
@@ -1190,30 +1190,12 @@ static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq,
}
/* Append an skb to a SQ for packet transfer. */
-int nicvf_sq_append_skb(struct nicvf *nic, struct sk_buff *skb)
+int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
+ struct sk_buff *skb, u8 sq_num)
{
int i, size;
int subdesc_cnt, tso_sqe = 0;
- int sq_num, qentry;
- struct queue_set *qs;
- struct snd_queue *sq;
-
- sq_num = skb_get_queue_mapping(skb);
- if (sq_num >= MAX_SND_QUEUES_PER_QS) {
- /* Get secondary Qset's SQ structure */
- i = sq_num / MAX_SND_QUEUES_PER_QS;
- if (!nic->snicvf[i - 1]) {
- netdev_warn(nic->netdev,
- "Secondary Qset#%d's ptr not initialized\n",
- i - 1);
- return 1;
- }
- nic = (struct nicvf *)nic->snicvf[i - 1];
- sq_num = sq_num % MAX_SND_QUEUES_PER_QS;
- }
-
- qs = nic->qs;
- sq = &qs->sq[sq_num];
+ int qentry;
subdesc_cnt = nicvf_sq_subdesc_required(nic, skb);
if (subdesc_cnt > atomic_read(&sq->free_cnt))
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
index 20511f2..9e21046 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
@@ -88,13 +88,13 @@
/* RED and Backpressure levels of CQ for pkt reception
* For CQ, level is a measure of emptiness i.e 0x0 means full
- * eg: For CQ of size 4K, and for pass/drop levels of 128/96
- * HW accepts pkt if unused CQE >= 2048
- * RED accepts pkt if unused CQE < 2048 & >= 1536
- * DROPs pkts if unused CQE < 1536
+ * eg: For CQ of size 4K, and for pass/drop levels of 160/144
+ * HW accepts pkt if unused CQE >= 2560
+ * RED accepts pkt if unused CQE < 2304 & >= 2560
+ * DROPs pkts if unused CQE < 2304
*/
-#define RQ_PASS_CQ_LVL 128ULL
-#define RQ_DROP_CQ_LVL 96ULL
+#define RQ_PASS_CQ_LVL 160ULL
+#define RQ_DROP_CQ_LVL 144ULL
/* RED and Backpressure levels of RBDR for pkt reception
* For RBDR, level is a measure of fullness i.e 0x0 means empty
@@ -306,7 +306,8 @@ void nicvf_sq_disable(struct nicvf *nic, int qidx);
void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt);
void nicvf_sq_free_used_descs(struct net_device *netdev,
struct snd_queue *sq, int qidx);
-int nicvf_sq_append_skb(struct nicvf *nic, struct sk_buff *skb);
+int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
+ struct sk_buff *skb, u8 sq_num);
struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx);
void nicvf_rbdr_task(unsigned long data);
--
2.7.4
^ permalink raw reply related
* [PATCH v2] arm64: head.S: Fix CNTHCTL_EL2 access on VHE system
From: Catalin Marinas @ 2016-11-29 11:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480385582-24176-1-git-send-email-jintack@cs.columbia.edu>
On Mon, Nov 28, 2016 at 09:13:02PM -0500, Jintack Lim wrote:
> From: Jintack <jintack@cs.columbia.edu>
>
> Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
> EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they
> are 11th and 10th bits respectively when E2H is set. Current code is
> unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set.
>
> In fact, we don't need to set those two bits, which allow EL1 and EL0 to
> access physical timer and counter respectively, if E2H and TGE are set
> for the host kernel. They will be configured later as necessary. First,
> we don't need to configure those bits for EL1, since the host kernel
> runs in EL2. It is a hypervisor's responsibility to configure them
> before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses
> are configured in the later stage of boot process.
>
> Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Queued for 4.10. Thanks.
--
Catalin
^ permalink raw reply
* [PATCH V7 0/3] irqchip: qcom: Add IRQ combiner driver
From: Hanjun Guo @ 2016-11-29 11:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479074375-2629-1-git-send-email-agustinv@codeaurora.org>
Hi Agustin,
On 2016/11/14 5:59, Agustin Vega-Frias wrote:
> Add support for IRQ combiners in the Top-level Control and Status
> Registers (TCSR) hardware block in Qualcomm Technologies chips.
>
> The first patch fixes IRQ probe deferral by allowing platform_device
> IRQ resources to be re-initialized if the ACPI core failed to find
> the IRQ domain during ACPI bus scan.
>
> The second patch adds support for ResourceSource/IRQ domain mapping
> when using Extended IRQ Resources with a specific ResourceSource.
> These changes are conditional on the ACPI_GENERIC_GSI config.
>
> The third patch takes advantage of the new capabilities to implement
> the driver for the IRQ combiners.
>
> Tested on top of v4.9-rc4.
>
> Changes V6 -> V7:
> * Consolidate changes for ResourceSource/IRQ domain mapping to the same
> source file implementing the generic GSI support, making it conditional
> on CONFIG_ACPI_GENERIC_GSI.
> * Eliminate some code duplication by implementing acpi_register_gsi in
> terms of the new acpi_register_irq API.
I had a test on Hisilicon D03 which needs patch 1 and 2 in this patch
set to enable the mbigen irqchip, and it works pretty good.
Patch 1/3 can remove the device dependency for the irqchip and platform
devices, and I removed my patch (ACPI: irq: introduce interrupt
producer) then add your patch 2/3, devices such as SAS and native
network works fine on my D03.
I will comment on the patches later.
Thanks
Hanjun
^ permalink raw reply
* [PATCH V5 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1
From: Shiju Jose @ 2016-11-29 11:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479767763-27532-3-git-send-email-tbaicar@codeaurora.org>
> -----Original Message-----
> From: linux-acpi-owner at vger.kernel.org [mailto:linux-acpi-
> owner at vger.kernel.org] On Behalf Of Tyler Baicar
> Sent: 21 November 2016 22:36
> To: marc.zyngier at arm.com; pbonzini at redhat.com; rkrcmar at redhat.com;
> linux at armlinux.org.uk; catalin.marinas at arm.com; will.deacon at arm.com;
> rjw at rjwysocki.net; lenb at kernel.org; matt at codeblueprint.co.uk;
> robert.moore at intel.com; lv.zheng at intel.com; nkaje at codeaurora.org;
> zjzhang at codeaurora.org; mark.rutland at arm.com; james.morse at arm.com;
> akpm at linux-foundation.org; eun.taik.lee at samsung.com;
> sandeepa.s.prabhu at gmail.com; shijie.huang at arm.com;
> rruigrok at codeaurora.org; paul.gortmaker at windriver.com;
> tomasz.nowicki at linaro.org; fu.wei at linaro.org; rostedt at goodmis.org;
> bristot at redhat.com; linux-arm-kernel at lists.infradead.org;
> kvmarm at lists.cs.columbia.edu; kvm at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-acpi at vger.kernel.org; linux-
> efi at vger.kernel.org; Suzuki.Poulose at arm.com; punit.agrawal at arm.com;
> astone at redhat.com; harba at codeaurora.org; hanjun.guo at linaro.org
> Cc: Tyler Baicar
> Subject: [PATCH V5 02/10] ras: acpi/apei: cper: generic error data
> entry v3 per ACPI 6.1
>
> Currently when a RAS error is reported it is not timestamped.
> The ACPI 6.1 spec adds the timestamp field to the generic error data
> entry v3 structure. The timestamp of when the firmware generated the
> error is now being reported.
>
> Signed-off-by: Jonathan (Zhixiong) Zhang <zjzhang@codeaurora.org>
> Signed-off-by: Richard Ruigrok <rruigrok@codeaurora.org>
> Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org>
> Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
> ---
> drivers/acpi/apei/ghes.c | 14 +++++++---
> drivers/firmware/efi/cper.c | 62 +++++++++++++++++++++++++++++++++++--
> --------
> include/acpi/ghes.h | 10 ++++++++
> include/linux/cper.h | 12 +++++++++
> 4 files changed, 80 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index
> b79abc5..9063d68 100644
> --- a/drivers/acpi/apei/ghes.c
> +++ b/drivers/acpi/apei/ghes.c
> @@ -420,7 +420,8 @@ static void ghes_handle_memory_failure(struct
> acpi_hest_generic_data *gdata, int
> int flags = -1;
> int sec_sev = ghes_severity(gdata->error_severity);
> struct cper_sec_mem_err *mem_err;
> - mem_err = (struct cper_sec_mem_err *)(gdata + 1);
> +
> + mem_err = acpi_hest_generic_data_payload(gdata);
>
> if (!(mem_err->validation_bits & CPER_MEM_VALID_PA))
> return;
> @@ -450,14 +451,18 @@ static void ghes_do_proc(struct ghes *ghes, {
> int sev, sec_sev;
> struct acpi_hest_generic_data *gdata;
> + uuid_le sec_type;
>
> sev = ghes_severity(estatus->error_severity);
> apei_estatus_for_each_section(estatus, gdata) {
> sec_sev = ghes_severity(gdata->error_severity);
> - if (!uuid_le_cmp(*(uuid_le *)gdata->section_type,
> + sec_type = *(uuid_le *)gdata->section_type;
> +
> + if (!uuid_le_cmp(sec_type,
> CPER_SEC_PLATFORM_MEM)) {
> struct cper_sec_mem_err *mem_err;
> - mem_err = (struct cper_sec_mem_err *)(gdata+1);
> +
> + mem_err = acpi_hest_generic_data_payload(gdata);
> ghes_edac_report_mem_error(ghes, sev, mem_err);
>
> arch_apei_report_mem_error(sev, mem_err); @@ -467,7
> +472,8 @@ static void ghes_do_proc(struct ghes *ghes,
> else if (!uuid_le_cmp(*(uuid_le *)gdata->section_type,
> CPER_SEC_PCIE)) {
> struct cper_sec_pcie *pcie_err;
> - pcie_err = (struct cper_sec_pcie *)(gdata+1);
> +
> + pcie_err = acpi_hest_generic_data_payload(gdata);
> if (sev == GHES_SEV_RECOVERABLE &&
> sec_sev == GHES_SEV_RECOVERABLE &&
> pcie_err->validation_bits &
> CPER_PCIE_VALID_DEVICE_ID && diff --git a/drivers/firmware/efi/cper.c
> b/drivers/firmware/efi/cper.c index d425374..7e2439e 100644
> --- a/drivers/firmware/efi/cper.c
> +++ b/drivers/firmware/efi/cper.c
> @@ -32,6 +32,9 @@
> #include <linux/acpi.h>
> #include <linux/pci.h>
> #include <linux/aer.h>
> +#include <linux/printk.h>
> +#include <linux/bcd.h>
> +#include <acpi/ghes.h>
>
> #define INDENT_SP " "
>
> @@ -386,13 +389,37 @@ static void cper_print_pcie(const char *pfx,
> const struct cper_sec_pcie *pcie,
> pfx, pcie->bridge.secondary_status, pcie->bridge.control); }
>
> +static void cper_estatus_print_section_v300(const char *pfx,
> + const struct acpi_hest_generic_data_v300 *gdata) {
> + __u8 hour, min, sec, day, mon, year, century, *timestamp;
> +
> + if (gdata->validation_bits & ACPI_HEST_GEN_VALID_TIMESTAMP) {
> + timestamp = (__u8 *)&(gdata->time_stamp);
> + sec = bcd2bin(timestamp[0]);
> + min = bcd2bin(timestamp[1]);
> + hour = bcd2bin(timestamp[2]);
> + day = bcd2bin(timestamp[4]);
> + mon = bcd2bin(timestamp[5]);
> + year = bcd2bin(timestamp[6]);
> + century = bcd2bin(timestamp[7]);
> + printk("%stime: %7s %02d%02d-%02d-%02d %02d:%02d:%02d\n",
> pfx,
> + 0x01 & *(timestamp + 3) ? "precise" : "", century,
> + year, mon, day, hour, min, sec);
> + }
> +}
> +
> static void cper_estatus_print_section(
> - const char *pfx, const struct acpi_hest_generic_data *gdata, int
> sec_no)
> + const char *pfx, struct acpi_hest_generic_data *gdata, int sec_no)
> {
> uuid_le *sec_type = (uuid_le *)gdata->section_type;
> __u16 severity;
> char newpfx[64];
>
> + if (acpi_hest_generic_data_version(gdata) >= 3)
> + cper_estatus_print_section_v300(pfx,
> + (const struct acpi_hest_generic_data_v300 *)gdata);
> +
> severity = gdata->error_severity;
> printk("%s""Error %d, type: %s\n", pfx, sec_no,
> cper_severity_str(severity));
> @@ -403,14 +430,18 @@ static void cper_estatus_print_section(
>
> snprintf(newpfx, sizeof(newpfx), "%s%s", pfx, INDENT_SP);
> if (!uuid_le_cmp(*sec_type, CPER_SEC_PROC_GENERIC)) {
> - struct cper_sec_proc_generic *proc_err = (void *)(gdata +
> 1);
> + struct cper_sec_proc_generic *proc_err;
> +
> + proc_err = acpi_hest_generic_data_payload(gdata);
> printk("%s""section_type: general processor error\n",
> newpfx);
> if (gdata->error_data_length >= sizeof(*proc_err))
> cper_print_proc_generic(newpfx, proc_err);
> else
> goto err_section_too_small;
> } else if (!uuid_le_cmp(*sec_type, CPER_SEC_PLATFORM_MEM)) {
> - struct cper_sec_mem_err *mem_err = (void *)(gdata + 1);
> + struct cper_sec_mem_err *mem_err;
> +
> + mem_err = acpi_hest_generic_data_payload(gdata);
> printk("%s""section_type: memory error\n", newpfx);
> if (gdata->error_data_length >=
> sizeof(struct cper_sec_mem_err_old)) @@ -419,7 +450,9
> @@ static void cper_estatus_print_section(
> else
> goto err_section_too_small;
> } else if (!uuid_le_cmp(*sec_type, CPER_SEC_PCIE)) {
> - struct cper_sec_pcie *pcie = (void *)(gdata + 1);
> + struct cper_sec_pcie *pcie;
> +
> + pcie = acpi_hest_generic_data_payload(gdata);
> printk("%s""section_type: PCIe error\n", newpfx);
> if (gdata->error_data_length >= sizeof(*pcie))
> cper_print_pcie(newpfx, pcie, gdata); @@ -438,7
> +471,7 @@ void cper_estatus_print(const char *pfx,
> const struct acpi_hest_generic_status *estatus) {
> struct acpi_hest_generic_data *gdata;
> - unsigned int data_len, gedata_len;
> + unsigned int data_len;
> int sec_no = 0;
> char newpfx[64];
> __u16 severity;
> @@ -451,12 +484,12 @@ void cper_estatus_print(const char *pfx,
> printk("%s""event severity: %s\n", pfx,
> cper_severity_str(severity));
> data_len = estatus->data_length;
> gdata = (struct acpi_hest_generic_data *)(estatus + 1);
> +
> snprintf(newpfx, sizeof(newpfx), "%s%s", pfx, INDENT_SP);
> - while (data_len >= sizeof(*gdata)) {
> - gedata_len = gdata->error_data_length;
> +
> + while (data_len >= acpi_hest_generic_data_size(gdata)) {
> cper_estatus_print_section(newpfx, gdata, sec_no);
> - data_len -= gedata_len + sizeof(*gdata);
> - gdata = (void *)(gdata + 1) + gedata_len;
> + gdata = acpi_hest_generic_data_next(gdata);
> sec_no++;
> }
> }
Hi Tyler,
Will the above while loop does not come out because data_len is not getting updated as it did in V4 patch?
This is the behaviour seen when we tested on our platform. It worked fine when we update the data_len.
> @@ -486,12 +519,13 @@ int cper_estatus_check(const struct
> acpi_hest_generic_status *estatus)
> return rc;
> data_len = estatus->data_length;
> gdata = (struct acpi_hest_generic_data *)(estatus + 1);
> - while (data_len >= sizeof(*gdata)) {
> - gedata_len = gdata->error_data_length;
> - if (gedata_len > data_len - sizeof(*gdata))
> +
> + while (data_len >= acpi_hest_generic_data_size(gdata)) {
> + gedata_len = acpi_hest_generic_data_error_length(gdata);
> + if (gedata_len > data_len -
> acpi_hest_generic_data_size(gdata))
> return -EINVAL;
> - data_len -= gedata_len + sizeof(*gdata);
> - gdata = (void *)(gdata + 1) + gedata_len;
> + data_len -= gedata_len + acpi_hest_generic_data_size(gdata);
> + gdata = acpi_hest_generic_data_next(gdata);
> }
> if (data_len)
> return -EINVAL;
> diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index
> 68f088a..56b9679 100644
> --- a/include/acpi/ghes.h
> +++ b/include/acpi/ghes.h
> @@ -73,3 +73,13 @@ static inline void ghes_edac_unregister(struct ghes
> *ghes) { } #endif
> +
> +#define acpi_hest_generic_data_version(gdata) \
> + (gdata->revision >> 8)
> +
> +static inline void *acpi_hest_generic_data_payload(struct
> +acpi_hest_generic_data *gdata) {
> + return acpi_hest_generic_data_version(gdata) >= 3 ?
> + (void *)(((struct acpi_hest_generic_data_v300 *)(gdata)) +
> 1) :
> + gdata + 1;
> +}
> diff --git a/include/linux/cper.h b/include/linux/cper.h index
> dcacb1a..13ea41c 100644
> --- a/include/linux/cper.h
> +++ b/include/linux/cper.h
> @@ -255,6 +255,18 @@ enum {
>
> #define CPER_PCIE_SLOT_SHIFT 3
>
> +#define acpi_hest_generic_data_error_length(gdata) \
> + (((struct acpi_hest_generic_data *)(gdata))->error_data_length)
> +#define acpi_hest_generic_data_size(gdata) \
> + ((acpi_hest_generic_data_version(gdata) >= 3) ? \
> + sizeof(struct acpi_hest_generic_data_v300) : \
> + sizeof(struct acpi_hest_generic_data))
> +#define acpi_hest_generic_data_record_size(gdata) \
> + (acpi_hest_generic_data_size(gdata) + \
> + acpi_hest_generic_data_error_length(gdata))
> +#define acpi_hest_generic_data_next(gdata) \
> + ((void *)(gdata) + acpi_hest_generic_data_record_size(gdata))
> +
> /*
> * All tables and structs must be byte-packed to match CPER
> * specification, since the tables are provided by the system BIOS
> --
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.
> Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a
> Linux Foundation Collaborative Project.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-acpi"
> in the body of a message to majordomo at vger.kernel.org More majordomo
> info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly
From: Jintack Lim @ 2016-11-29 11:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0a475329-6f50-42ae-3244-f0767c56ce09@arm.com>
On Tue, Nov 29, 2016 at 4:36 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On 29/11/16 03:28, Jintack Lim wrote:
>> On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>> On 28/11/16 17:43, Marc Zyngier wrote:
>>>> Hi Jintack,
>>
>> Hi Marc,
>>
>>>>
>>>> On 28/11/16 16:46, Jintack Lim wrote:
>>>>> Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
>>>>> EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they
>>>>> are 11th and 10th bits respectively when E2H is set. Current code is
>>>>> unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set, which
>>>>> may allow guest OS to access physical timer. So, fix it.
>>>>>
>>>>> Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
>>>>> ---
>>>>> arch/arm/include/asm/kvm_timer.h | 33 +++++++++++++++++++
>>>>> arch/arm64/include/asm/kvm_timer.h | 62 ++++++++++++++++++++++++++++++++++++
>>>>> include/clocksource/arm_arch_timer.h | 6 ++--
>>>>> virt/kvm/arm/hyp/timer-sr.c | 8 ++---
>>>>> 4 files changed, 103 insertions(+), 6 deletions(-)
>>>>> create mode 100644 arch/arm/include/asm/kvm_timer.h
>>>>> create mode 100644 arch/arm64/include/asm/kvm_timer.h
>>>>>
>>>
>>> [...]
>>>
>>>> We could make it nicer (read "faster") by introducing a
>>>> hyp_alternate_select construct that only returns a value instead
>>>> of calling a function. I remember writing something like that
>>>> at some point, and dropping it...
>>>
>>> So here's what this could look like (warning, wacky code ahead,
>>> though I fixed a stupid bug that was present in the previous patch).
>>> The generated code is quite nice (no branch, only an extra mov
>>> instruction on the default path)... Of course, completely untested!
>>
>> This looks much cleaner than my patch.
>> While we are at it, is it worth to consider that we just need to set
>> those bits once for VHE case, not for every world switch as an
>> optimization?
>
> Ah! That's a much better idea indeed! And we could stop messing with
> cntvoff_el2 as well, as it doesn't need to be restored to zero on exit.
> Could you try and respin something along those lines?
Yes, I can.
Thanks,
Jintack
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
>
^ permalink raw reply
* [PATCH] ARM: davinci: da8xx: Fix sleeping function called from invalid context
From: Alexandre Bailon @ 2016-11-29 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <36a2e5e1-e7b7-2ca0-0484-98636771ec65@ti.com>
On 11/29/2016 11:48 AM, Sekhar Nori wrote:
> On Monday 28 November 2016 09:59 PM, Alexandre Bailon wrote:
>> Everytime the usb20 phy is enabled, there is a
>> "sleeping function called from invalid context" BUG.
>
> Who calls PHY clk_enable() from non-preemptible context? Can you provide
> the call stack?
Actually, clk_enable() is called from preemptible context (from phy
driver) but it disables interrupts before to call the clk_enable()
callback.
I attached the call stack that is probably more understandable than
my explanation.
>
>> usb20_phy_clk_enable(), called with the irq disabled uses
>> clk_get() and clk_enable_prepapre() which may sleep.
>> Move clk_get() to da8xx_register_usb20_phy_clk() and
>> replace clk_prepare_enable() by clk_enable().
>>
>> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
>> ---
>> arch/arm/mach-davinci/usb-da8xx.c | 15 +++++++++------
>> 1 file changed, 9 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
>> index b010e5f..c9b5cd4 100644
>> --- a/arch/arm/mach-davinci/usb-da8xx.c
>> +++ b/arch/arm/mach-davinci/usb-da8xx.c
>> @@ -156,23 +156,23 @@ int __init da8xx_register_usb_refclkin(int rate)
>> return 0;
>> }
>>
>> +static struct clk *usb20_clk;
>> +
>> static void usb20_phy_clk_enable(struct clk *clk)
>> {
>> - struct clk *usb20_clk;
>> int err;
>> u32 val;
>> u32 timeout = 500000; /* 500 msec */
>>
>> val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
>>
>> - usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
>> - if (IS_ERR(usb20_clk)) {
>> + if (!usb20_clk || IS_ERR(usb20_clk)) {
>
> NULL is a valid clock handle. There is no way clock enable of
> usb20_phy_clk can be invoked if its not registered. So, you can assume
> that usb20_clk is valid if you get here.
OK.
>
>> pr_err("could not get usb20 clk: %ld\n", PTR_ERR(usb20_clk));
>> return;
>> }
>>
>> /* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
>> - err = clk_prepare_enable(usb20_clk);
>> + err = clk_enable(usb20_clk);
>> if (err) {
>> pr_err("failed to enable usb20 clk: %d\n", err);
>> clk_put(usb20_clk);
>> @@ -197,8 +197,7 @@ static void usb20_phy_clk_enable(struct clk *clk)
>>
>> pr_err("Timeout waiting for USB 2.0 PHY clock good\n");
>> done:
>> - clk_disable_unprepare(usb20_clk);
>> - clk_put(usb20_clk);
>> + clk_disable(usb20_clk);
>
>
> I noticed that we are missing clk_disable(usb20_clk) in
> usb20_phy_clk_disable(). It will now be easier to do that after this
> patch. Can you add that in a separate patch?
>
I don't think we need it.
What we don't see in this patch is that usb20_clk is enabled and,
it is disabled right after the PHY PLL is ready in usb20_phy_clk_enable().
>> }
>>
>> static void usb20_phy_clk_disable(struct clk *clk)
>> @@ -287,6 +286,10 @@ int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
>> struct clk *parent;
>> int ret = 0;
>>
>> + usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
>> + if (IS_ERR(usb20_clk))
>> + return PTR_ERR(parent);
>> +
>> parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux");
>> if (IS_ERR(parent))
>> return PTR_ERR(parent);
>
> clk_put(usb20_clk) should be called here on failure path.
I will fix it.
>
> Thanks,
> Sekhar
>
Thanks,
Alexandre
-------------- next part --------------
BUG: sleeping function called from invalid context at kernel/locking/mutex.c:97
in_atomic(): 1, irqs_disabled(): 128, pid: 1053, name: udevd
Preemption disabled at:[<c0017220>] clk_enable+0x40/0x94
CPU: 0 PID: 1053 Comm: udevd Not tainted 4.9.0-rc5-08315-gc26ef3f-dirty #90
Hardware name: Generic DA850/OMAP-L138/AM18x
Backtrace:
[<c000d968>] (dump_backtrace) from [<c000dcf8>] (show_stack+0x20/0x24)
r6:c0531e04 r5:c0017220
r4:00000000 r3:00000000
[<c000dcd8>] (show_stack) from [<c025b398>] (dump_stack+0x20/0x28)
[<c025b378>] (dump_stack) from [<c00432e4>] (___might_sleep+0x140/0x1d8)
[<c00431a4>] (___might_sleep) from [<c00433e8>] (__might_sleep+0x6c/0xac)
r5:00000061 r4:00000000
[<c004337c>] (__might_sleep) from [<c049487c>] (mutex_lock+0x28/0x4c)
r7:c06592cc r6:0000ef32
r5:c052b8a8 r4:c06592cc
[<c0494854>] (mutex_lock) from [<c02abc2c>] (clk_get_sys+0x2c/0x118)
r4:c0676cbc r3:c06231f8
[<c02abc00>] (clk_get_sys) from [<c02abd48>] (clk_get+0x30/0x34)
r10:4ea11003 r9:00000000
r8:bf1fb620 r7:fee00000
r6:0000ef32 r5:80000013
r4:c0676cbc
[<c02abd18>] (clk_get) from [<c0018504>] (usb20_phy_clk_enable+0x2c/0x140)
[<c00184d8>] (usb20_phy_clk_enable) from [<c00171bc>] (__clk_enable+0x60/0x84)
r7:fee00000 r6:c7bdbd80
r5:80000013 r4:c0623388
[<c001715c>] (__clk_enable) from [<c0017228>] (clk_enable+0x48/0x94)
r4:c0623388
[<c00171e0>] (clk_enable) from [<bf000238>] (da8xx_usb20_phy_power_on+0x38/0x88 [phy_da8xx_usb])
r5:c7ba0fd0 r4:c0623388
[<bf000200>] (da8xx_usb20_phy_power_on [phy_da8xx_usb]) from [<c0284348>] (phy_power_on+0x9c/0xec)
r5:c7bdbc00 r4:fffffdf4
[<c02842ac>] (phy_power_on) from [<bf1fa4dc>] (da8xx_musb_init+0xe4/0x1dc [da8xx])
r6:c71fee50 r5:00000000
r4:c7a3a010 r3:00000081
[<bf1fa3f8>] (da8xx_musb_init [da8xx]) from [<bf1deba4>] (musb_probe+0x1b4/0xc2c [musb_hdrc])
r10:c7164540 r8:bf1ed3b8
r7:bf1ee420 r6:bf1fae00
r5:fee00000 r4:c7a3a010
[<bf1de9f0>] (musb_probe [musb_hdrc]) from [<c02f02e8>] (platform_drv_probe+0x48/0x98)
r10:0000000c r9:00000000
r8:bf1ed3b8 r7:00000000
r6:c70d5410 r5:bf1ed3b8
r4:bf1de9f0
[<c02f02a0>] (platform_drv_probe) from [<c02ee114>] (driver_probe_device+0x24c/0x448)
r6:c0673938 r5:c06dce14
r4:c70d5410 r3:c02f02a0
[<c02edec8>] (driver_probe_device) from [<c02ee694>] (__device_attach_driver+0xc0/0x128)
r10:00000000 r8:c799d010
r7:c710bb40 r6:c70d5410
r5:bf1ed3b8 r4:00000001
[<c02ee5d4>] (__device_attach_driver) from [<c02ec104>] (bus_for_each_drv+0x70/0x98)
r7:00000000 r6:00000000
r5:c02ee5d4 r4:c710bb40
[<c02ec094>] (bus_for_each_drv) from [<c02eddbc>] (__device_attach+0xac/0x138)
r6:00000001 r5:c70d5444
r4:c70d5410
[<c02edd10>] (__device_attach) from [<c02ee718>] (device_initial_probe+0x1c/0x20)
r7:00000000 r6:c70d5410
r5:c065dff8 r4:c70d5410
[<c02ee6fc>] (device_initial_probe) from [<c02ed164>] (bus_probe_device+0x94/0x9c)
[<c02ed0d0>] (bus_probe_device) from [<c02eaf70>] (device_add+0x31c/0x570)
r6:c06dcdf0 r5:c70d5418
r4:c70d5410 r3:00000001
[<c02eac54>] (device_add) from [<c02f0504>] (platform_device_add+0x130/0x264)
r10:00000000 r9:00000000
r8:ffffffff r7:00000001
r6:c70d5410 r5:c70d5400
r4:00000002
[<c02f03d4>] (platform_device_add) from [<c02f0dbc>] (platform_device_register_full+0xec/0x118)
r7:c710bc10 r6:c71fee90
r5:c70d5400 r4:c710bc50
[<c02f0cd0>] (platform_device_register_full) from [<bf1facac>] (da8xx_probe+0x1a8/0x284 [da8xx])
r5:c71fee50 r4:c799d010
[<bf1fab04>] (da8xx_probe [da8xx]) from [<c02f02e8>] (platform_drv_probe+0x48/0x98)
r10:0000000b r9:bf1fb4a8
r8:bf1fb360 r7:00000000
r6:c799d010 r5:bf1fb360
r4:bf1fab04
[<c02f02a0>] (platform_drv_probe) from [<c02ee114>] (driver_probe_device+0x24c/0x448)
r6:c0673938 r5:c06dce14
r4:c799d010 r3:c02f02a0
[<c02edec8>] (driver_probe_device) from [<c02ee40c>] (__driver_attach+0xfc/0x128)
r10:c8ae54a4 r8:00000000
r7:c0673860 r6:bf1fb360
r5:c799d010 r4:c799d044
[<c02ee310>] (__driver_attach) from [<c02ec194>] (bus_for_each_dev+0x68/0x98)
r6:00000000 r5:c02ee310
r4:bf1fb360 r3:00000000
[<c02ec12c>] (bus_for_each_dev) from [<c02ed7b8>] (driver_attach+0x28/0x30)
r6:c065dff8 r5:c723b420
r4:bf1fb360
[<c02ed790>] (driver_attach) from [<c02ed43c>] (bus_add_driver+0x18c/0x268)
[<c02ed2b0>] (bus_add_driver) from [<c02ef0d0>] (driver_register+0x88/0x104)
r8:bf1fd000 r7:c71fedc0
r6:00000000 r5:00000001
r4:bf1fb360
[<c02ef048>] (driver_register) from [<c02f0058>] (__platform_driver_register+0x40/0x54)
r5:00000001 r4:bf1fb460
[<c02f0018>] (__platform_driver_register) from [<bf1fd018>] (da8xx_driver_init+0x18/0x24 [da8xx])
[<bf1fd000>] (da8xx_driver_init [da8xx]) from [<c0009af0>] (do_one_initcall+0x50/0x188)
[<c0009aa0>] (do_one_initcall) from [<c0085a2c>] (do_init_module+0x6c/0x1e8)
r8:bf1fb460 r7:c71fedc0
r6:c7164240 r5:00000001
r4:bf1fb460
[<c00859c0>] (do_init_module) from [<c008795c>] (load_module+0x1ce8/0x2344)
r6:00000001 r5:00000001
r4:c710bf34
[<c0085c74>] (load_module) from [<c00881f4>] (SyS_finit_module+0xb4/0xe0)
r10:00000000 r9:c710a000
r8:c000aaa4 r7:00000000
r6:7fffffff r5:0004f8c0
r4:00000000
[<c0088140>] (SyS_finit_module) from [<c000a900>] (ret_fast_syscall+0x0/0x38)
r7:0000017b r6:00000000
r5:0004f8c0 r4:00020000
^ permalink raw reply
* [PATCH v9 00/16] ACPI IORT ARM SMMU support
From: Hanjun Guo @ 2016-11-29 11:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121100148.24769-1-lorenzo.pieralisi@arm.com>
On 2016/11/21 18:01, Lorenzo Pieralisi wrote:
> This patch series is v9 of a previous posting:
>
> https://lkml.org/lkml/2016/11/16/386
>
> v8 -> v9
> - Updated bypass flag handling in ARM SMMU v3 according to
> reviews
> - Removed SMMUv1/v2 configuration interrupt handling
> - Rebased against v4.9-rc5
> - Updated tags
I rebased on top of latest 4.9-rc7 (can apply cleanly), and tested on
Hisilicon D03, the SMMUv3 works fine as previous version.
Thanks
Hanjun
^ permalink raw reply
* [PATCH 7/10] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
From: Ulf Hansson @ 2016-11-29 11:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <02725a0f-c061-e7f2-9a01-8975c62ab5a7@marvell.com>
[...]
>>>>
>>>
>>> Sorry that I didn't make myself clear.
>>>
>>> Our host PHY delay line consists of hundreds of sampling points.
>>> Each sampling point represents a different phase shift.
>>>
>>> In lower speed mode, our host driver will scan the delay line.
>>> It will select and test multiple sampling points, other than testing
>>> only single sampling point.
>>>
>>> If a sampling point fails to transfer cmd/data, our host driver will
>>> move to test next sampling point, until we find out a group of successful
>>> sampling points which can transfer cmd/data. At last we will select
>>> a perfect one from them.
>>
>> Ahh, I see. Unfortunate, this is going to be very hard to implement properly.
>>
>> The main problem is that the host driver has *no* knowledge about the
>> internal state of the card, as that is the responsibility of the mmc
>> core to keep track of.
>>
>> If the host driver would send a command during every update of the
>> "ios" setting, from ->set_ios(), for sure it would lead to commands
>> being sent that are "forbidden" in the current internal state of the
>> card.
>> This would lead to that the card initialization sequence fails,
>> because the card may move to an unknown internal state and the mmc
>> core would have no knowledge about what happened.
>>
>
> Yes. In theory, host layer should not initiate a command by itself.
>
> We assume that bus is idle and card is stable in Tran state, when core layer
> asks host to switch "ios".
Understand, but this is a wrong assumption. The card may very well in
another state than Tran state.
> Besides, we only select the commands which is valid in the whole procedure,
> such as CMD8 for eMMC.
> Those test commands are actually like read operations to card registers.
> The card will return to Tran state even if transfer fails. It is also easy
> for host to recover.
For example, I would recommend you to investigate in detail the
sequence for when a CMD6 command is sent to the card.
The host must *not* start sending commands from ->set_ios() during a
CMD6 sequence. For example a CMD8 is not allowed.
Moreover, due to this, I wonder if it is even possible to get this HW
to work properly.
>
>> Hmm..
>>
>> Can you specify, *exactly*, under which "ios updates" you need to
>> verify updated PHY setting changes by sending a cmd/data? Also, please
>> specify if it's enough to only test the CMD line or also DATA lines.
>>
>
> When one of the three parameters in below changes, our host driver needs
> to adjust PHY in lower speed mode.
> 1. Speed Mode (timing): like legacy mode --> HS DDR
> 2. Bus Clock: like 400KHz --> 50MHz
> 3. Bus Width: like 1-bit --> 4-bit/8-bit
>
> For eMMC, we use CMD8 to test sampling point.
> For SD, we use CMD13.
> For SDIO, currently CMD52 is used to read a register from CCCR.
> Those commands in above are all valid during the whole procedure to switch
> to high speed mode from legacy mode.
>
> It is the best case if the test command can transfer both on CMD and DAT lines.
> CMD8 for eMMC can test both CMD line and DAT lines. CMD13 and CMD52 only test
> CMD line. We might use ACMD51 for SD and CMD53 for SDIO later thus DAT lines
> are also under test.
Thanks for sharing these details!
So, if possible, I would recommend you to discuss these issues with
some of the HW designers. Perhaps you can figure out an alternative
method of confirming/testing PHY setting changes? Sending commands to
the card just doesn't work well for all cases.
Kind regards
Uffe
^ permalink raw reply
* [PATCH v28 0/9] arm64: add kdump support
From: Will Deacon @ 2016-11-29 11:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161125162039.GB22099@e104818-lin.cambridge.arm.com>
On Fri, Nov 25, 2016 at 04:20:40PM +0000, Catalin Marinas wrote:
> On Thu, Nov 24, 2016 at 06:55:23PM +0900, AKASHI Takahiro wrote:
> > AKASHI Takahiro (8):
> > arm64: kdump: reserve memory for crash dump kernel
> > memblock: add memblock_cap_memory_range()
> > arm64: limit memory regions based on DT property, usable-memory-range
> > arm64: kdump: implement machine_crash_shutdown()
> > arm64: kdump: add kdump support
> > arm64: kdump: add VMCOREINFO's for user-space coredump tools
> > arm64: kdump: enable kdump in the arm64 defconfig
> > arm64: kdump: update a kernel doc
>
> Given that it's nearly -rc7, holiday in the US and more acks needed, we
> should defer merging this series to 4.11. In the meantime, since Will is
> going to handle the 4.11 merging window, I'm acking the whole series:
>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Okey doke. I'll keep my eyes peeled for a new version in the new year.
Will
^ permalink raw reply
* [PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly
From: Marc Zyngier @ 2016-11-29 10:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161129104753.GA15346@cbox>
On 29/11/16 10:47, Christoffer Dall wrote:
> On Tue, Nov 29, 2016 at 09:37:07AM +0000, Marc Zyngier wrote:
>> On 28/11/16 19:42, Christoffer Dall wrote:
>>> On Mon, Nov 28, 2016 at 06:39:04PM +0000, Marc Zyngier wrote:
>>>> On 28/11/16 17:43, Marc Zyngier wrote:
>>>>> Hi Jintack,
>>>>>
>>>>> On 28/11/16 16:46, Jintack Lim wrote:
>>>>>> Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
>>>>>> EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they
>>>>>> are 11th and 10th bits respectively when E2H is set. Current code is
>>>>>> unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set, which
>>>>>> may allow guest OS to access physical timer. So, fix it.
>>>>>>
>>>>>> Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
>>>>>> ---
>>>>>> arch/arm/include/asm/kvm_timer.h | 33 +++++++++++++++++++
>>>>>> arch/arm64/include/asm/kvm_timer.h | 62 ++++++++++++++++++++++++++++++++++++
>>>>>> include/clocksource/arm_arch_timer.h | 6 ++--
>>>>>> virt/kvm/arm/hyp/timer-sr.c | 8 ++---
>>>>>> 4 files changed, 103 insertions(+), 6 deletions(-)
>>>>>> create mode 100644 arch/arm/include/asm/kvm_timer.h
>>>>>> create mode 100644 arch/arm64/include/asm/kvm_timer.h
>>>>>>
>>>>
>>>> [...]
>>>>
>>>>> We could make it nicer (read "faster") by introducing a
>>>>> hyp_alternate_select construct that only returns a value instead
>>>>> of calling a function. I remember writing something like that
>>>>> at some point, and dropping it...
>>>>
>>>> So here's what this could look like (warning, wacky code ahead,
>>>> though I fixed a stupid bug that was present in the previous patch).
>>>> The generated code is quite nice (no branch, only an extra mov
>>>> instruction on the default path)... Of course, completely untested!
>>>
>>> Isn't this all about determining which bitmask to use, statically, once,
>>> after the system has booted?
>>>
>>> How about a good old fashioned static variable, or global struct like
>>> the global one we use for the VGIC, which sets the proper mit mask
>>> during kvm init, and the world-switch code just uses a variable?
>>
>> We could indeed do that (I've been carried away with my tendency for
>> weird and wonderful hacks).
>>
>> But as Jintack mentioned, there is a much better approach, which is to
>> do nothing at all on the VHE path (we can set the permission bits once
>> and for all). cntvoff_el2 also falls into the same category of things we
>> should be able to only restore and not bother resetting (as it doesn't
>> affect the EL2 virtual counter).
>>
>> Thoughts?
>>
> Yes, that sounds much better.
>
> I have some patches to get rid of a lot of things, like cntvoff, during
> the world-switch for VHE, so if Jintack just wants to focus on the
> cnthctl I will catch cntvoff later.
Sound good to me.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v2 2/2] ARM: dts: da850-lcdk: specify the maximum pixel clock rate for tilcdc
From: Sekhar Nori @ 2016-11-29 10:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480335328-4010-3-git-send-email-bgolaszewski@baylibre.com>
On Monday 28 November 2016 05:45 PM, Bartosz Golaszewski wrote:
> Due to memory throughput constraints any display mode for which the
> pixel clock rate exceeds the recommended value of 37500 KHz must be
> filtered out.
I think there might be more reasons than memory throughput constraints
for the reasoning behind 37.5Mhz cap on pixel clock. Why not just refer
to the datasheet section that places this constraint so we know its a
hardware restriction.
>
> Specify the max-pixelclock property for the display node for
> da850-lcdk.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> arch/arm/boot/dts/da850-lcdk.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
> index d864f11..1283263 100644
> --- a/arch/arm/boot/dts/da850-lcdk.dts
> +++ b/arch/arm/boot/dts/da850-lcdk.dts
> @@ -285,6 +285,7 @@
>
> &display {
> status = "okay";
> + max-pixelclock = <37500>;
Should this not be in da850.dtsi since its an SoC imposed constraint? If
a board needs narrower constraint, it can override it. But I guess most
well designed boards will just hit the SoC constraint.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH V10 4/6] arm: arm64: pmu: Assign platform PMU CPU affinity
From: Will Deacon @ 2016-11-29 10:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478734793-6341-5-git-send-email-jeremy.linton@arm.com>
On Wed, Nov 09, 2016 at 05:39:51PM -0600, Jeremy Linton wrote:
> On systems with multiple PMU types the PMU to CPU affinity
> needs to be detected and set. The CPU to interrupt affinity
> should also be set.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> drivers/perf/arm_pmu.c | 63 ++++++++++++++++++++++++++++++++++++++++++--------
> 1 file changed, 53 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
> index b37b572..6008be9 100644
> --- a/drivers/perf/arm_pmu.c
> +++ b/drivers/perf/arm_pmu.c
> @@ -11,6 +11,7 @@
> */
> #define pr_fmt(fmt) "hw perfevents: " fmt
>
> +#include <linux/acpi.h>
> #include <linux/bitmap.h>
> #include <linux/cpumask.h>
> #include <linux/cpu_pm.h>
> @@ -24,6 +25,7 @@
> #include <linux/irq.h>
> #include <linux/irqdesc.h>
>
> +#include <asm/cpu.h>
> #include <asm/cputype.h>
> #include <asm/irq_regs.h>
>
> @@ -889,25 +891,67 @@ static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
> }
>
> /*
> - * CPU PMU identification and probing.
> + * CPU PMU identification and probing. Its possible to have
> + * multiple CPU types in an ARM machine. Assure that we are
> + * picking the right PMU types based on the CPU in question
> */
> -static int probe_current_pmu(struct arm_pmu *pmu,
> - const struct pmu_probe_info *info)
> +static int probe_plat_pmu(struct arm_pmu *pmu,
> + const struct pmu_probe_info *info,
> + unsigned int pmuid)
> {
> - int cpu = get_cpu();
> - unsigned int cpuid = read_cpuid_id();
> int ret = -ENODEV;
> + int cpu;
> + int aff_ctr = 0;
> + static int duplicate_pmus;
> + struct platform_device *pdev = pmu->plat_device;
> + int irq = platform_get_irq(pdev, 0);
>
> - pr_info("probing PMU on CPU %d\n", cpu);
> + if (irq >= 0 && !irq_is_percpu(irq)) {
> + pmu->irq_affinity = kcalloc(pdev->num_resources, sizeof(int),
> + GFP_KERNEL);
> + if (!pmu->irq_affinity)
> + return -ENOMEM;
> + }
>
> + for_each_possible_cpu(cpu) {
> + unsigned int cpuid = read_specific_cpuid(cpu);
> +
> + if (cpuid == pmuid) {
> + cpumask_set_cpu(cpu, &pmu->supported_cpus);
> + if (pmu->irq_affinity) {
> + pmu->irq_affinity[aff_ctr] = cpu;
> + aff_ctr++;
> + }
> + }
> + }
> +
> + /* find the type of PMU given the CPU */
> for (; info->init != NULL; info++) {
> - if ((cpuid & info->mask) != info->cpuid)
> + if ((pmuid & info->mask) != info->cpuid)
> continue;
> ret = info->init(pmu);
> + /*
> + * if this pmu declaration is unspecified and we have
> + * previously found a PMU on this platform then append
> + * a PMU number to the pmu name. This avoids changing
> + * the names of PMUs that are specific to a class of CPUs.
> + * The assumption is that if we match a specific PMU in the
> + * provided pmu_probe_info then it's unique, and another PMU
> + * in the system will match a different entry rather than
> + * needing the _number to assure its unique.
> + */
> + if ((!info->cpuid) && (duplicate_pmus)) {
This is a bit grim: if you had a PMU with a non-zero info->cpuid, then you
later found a PMU with a zeroed info->cpuid, the latter would get a
redundant suffix. This doesn't happen in reality, because the ACPI case
always has info->cpuid == 0, but if somebody extends armv8_pmu_probe_table
then we'd get this and probably not realise.
I think the duplicate_pmus counter needs to be tied explicitly to the
"default type" (i.e. when info->cpuid == 0, but see my next comment).
> + pmu->name = kasprintf(GFP_KERNEL, "%s_%d",
> + pmu->name, duplicate_pmus);
> + if (!pmu->name) {
> + kfree(pmu->irq_affinity);
> + ret = -ENOMEM;
> + }
> + }
This code doesn't run for the device-tree probing case, but I think it would
be useful to do the same numbering trick for e.g. systems with multiple PMUs
that all end up matching on armv8_pmuv3.
Will
^ permalink raw reply
* [PATCH v9 06/11] arm/arm64: vgic: Implement VGICv3 CPU interface access
From: Christoffer Dall @ 2016-11-29 10:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALicx6uK9kQ5fuW=SGnny7oerPbhGbVDw=MMi0Tna_B4XdJqeg@mail.gmail.com>
On Tue, Nov 29, 2016 at 03:31:44PM +0530, Vijay Kilari wrote:
> On Tue, Nov 29, 2016 at 2:07 PM, Christoffer Dall
> <christoffer.dall@linaro.org> wrote:
> > On Tue, Nov 29, 2016 at 01:08:26PM +0530, Vijay Kilari wrote:
> >> On Tue, Nov 29, 2016 at 1:09 AM, Christoffer Dall
> >> <christoffer.dall@linaro.org> wrote:
> >> > On Wed, Nov 23, 2016 at 06:31:53PM +0530, vijay.kilari at gmail.com wrote:
> >> >> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >> >>
> >> >> VGICv3 CPU interface registers are accessed using
> >> >> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
> >> >> as 64-bit. The cpu MPIDR value is passed along with register id.
> >> >> is used to identify the cpu for registers access.
> >> >>
> >> >> The VM that supports SEIs expect it on destination machine to handle
> >> >> guest aborts and hence checked for ICC_CTLR_EL1.SEIS compatibility.
> >> >> Similarly, VM that supports Affinity Level 3 that is required for AArch64
> >> >> mode, is required to be supported on destination machine. Hence checked
> >> >> for ICC_CTLR_EL1.A3V compatibility.
> >> >>
> >> >> The CPU system register handling is spitted into two files
> >> >
> >> > spitted? Did you mean 'split into' ?
> >> >
> >> >> vgic-sys-reg-common.c and vgic-sys-reg-v3.c.
> >> >> The vgic-sys-reg-common.c handles read and write of VGIC CPU registers
> >> >
> >> > So this is weird because everything in virt/kvm/arm/ is exactly supposed
> >> > to be common between arm and arm64 already.
> >> >
> >> > I would rather that you had a copy of vgic-sys-reg-v3.c in arch/arm/kvm/
> >> > and in arch/arm64/kvm/ each taking care of its own architecture.
> >> >
> >> > But note that I didn't actually require that you implemented support for
> >> > GICv3 migration on AArch32 hosts for these patches, I just didn't want
> >> > thigns to silently break.
> >> >
> >> > If we cannot test the AArch32 implementation, we should potentially just
> >> > make sure that is not supported yet, return a proper error to userspace
> >> > and get the AArch64 host implementation correct.
> >> >
> >> > I suggest you move your:
> >> > virt/kvm/arm/vgic/vgic-sys-reg-v3.c to
> >> > arch/arm64/kvm/vgic-sys-reg-v3.c
> >> >
> >> > and rename
> >> > virt/kvm/arm/vgic/vgic-sys-reg-common.c to
> >> > virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> >> >
> >> > And then wait with the AArch32 host side for now, but just make sure it
> >> > compiles and returns an error as opposed to crashing the system if
> >> > someone tries to excercise this interface on an AArch32 host.
> >>
> >> I will add arch/arm/kvm/vgic-coproc-v3.c (pls check if file name is ok or not?)
> >
> > I would call it vgic-v3-coproc.c
> >
> >> and return -ENXIO as shown below and update document accordingly.
> >>
> >> int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
> >> u64 *reg)
> >> {
> >> /*
> >> * TODO: Implement for AArch32
> >> */
> >> return -ENXIO;
> >> }
> >>
> >> int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, u64 id,
> >> u64 *reg)
> >> {
> >> /*
> >> * TODO: Implement for AArch32
> >> */
> >> return -ENXIO;
> >> }
> >
> >
> >>
> >> >
> >> >> for both AArch64 and AArch32 mode. The vgic-sys-reg-v3.c handles AArch64
> >> >> mode and is compiled only for AArch64 mode.
> >> >>
> >> >> Updated arch/arm/include/uapi/asm/kvm.h with new definitions
> >> >> required to compile for AArch32.
> >> >>
> >> >> The version of VGIC v3 specification is define here
> >> >> Documentation/virtual/kvm/devices/arm-vgic-v3.txt
> >> >>
> >> >> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
> >> >> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >> >> ---
> >> [...]
> >> >> +static bool access_gic_aprn(struct kvm_vcpu *vcpu, bool is_write, u8 apr,
> >> >> + u8 idx, unsigned long *reg)
> >> >> +{
> >> >> + struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
> >> >> +
> >> >> + /* num_pri_bits are initialized with HW supported values.
> >> >> + * We can rely safely on num_pri_bits even if VM has not
> >> >> + * restored ICC_CTLR_EL1 before restoring APnR registers.
> >> >> + */
> >> >
> >> > nit: commenting style
> >> ok
> >> >
> >> >> + switch (vgic_v3_cpu->num_pri_bits) {
> >> >> + case 7:
> >> >> + vgic_v3_access_apr_reg(vcpu, is_write, apr, idx, reg);
> >> >> + break;
> >> >> + case 6:
> >> >> + if (idx > 1)
> >> >> + goto err;
> >> >> + vgic_v3_access_apr_reg(vcpu, is_write, apr, idx, reg);
> >> >> + break;
> >> >> + default:
> >> >> + if (idx > 0)
> >> >> + goto err;
> >> >> + vgic_v3_access_apr_reg(vcpu, is_write, apr, idx, reg);
> >> >> + }
> >> >
> >> > It looks to me like userspace can then program active priorities with
> >> > higher numbers than what it will program num_pri_bits to later. Is that
> >> > not weird, or am I missing something?
> >>
> >> As long as it is within HW supported priorities it is safe.
> >
> > I know that it is safe on the hardware, but it is weird to define a VM
> > with some max priority and still be able to set a higher active priority
> > is it not?
>
> In that case, we need to cache the highest active priorities updated
> by a VM in a variable
> when APnR is restored and later check against num_pri_bits when
> ICC_CTLR_EL1 is updated.
> If the value cached is greater than num_pri_bits restored then reject
> ICC_CTLR_EL1 restore.
>
> This variable should be initialized with value 5 ( min priority)
>
> >
> > On the other hand, if we cannot enforce this at runtime, it may not
> > matter?
>
> At VM runtime irrespective of VM's num_pri_bits all the APnR registers that
> HW supports are saved and restored.
>
Yes, never mind my comment. Since we cannot enforce this constraint
once the VM runs, I don't think there's any concern here.
> >> >
> >> >> +
> >> >> + return true;
> >> >> +err:
> >> >> + if (!is_write)
> >> >> + *reg = 0;
> >> >> +
> >> >> + return false;
> >> >> +}
> >> >> +
> >> >> +bool access_gic_ap0r_reg(struct kvm_vcpu *vcpu, bool is_write, u8 idx,
> >> >> + unsigned long *reg)
> >> >> +{
> >> >> + return access_gic_aprn(vcpu, is_write, 0, idx, reg);
> >> >> +}
> >> >> +
> >> >> +bool access_gic_ap1r_reg(struct kvm_vcpu *vcpu, bool is_write, u8 idx,
> >> >> + unsigned long *reg)
> >> >> +{
> >> >> + return access_gic_aprn(vcpu, is_write, 1, idx, reg);
> >> >> +}
> >> >> +
> >> >> +bool access_gic_sre_reg(struct kvm_vcpu *vcpu, bool is_write,
> >> >> + unsigned long *reg)
> >> >> +{
> >> >> + struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
> >> >> +
> >> >> + /* Validate SRE bit */
> >> >> + if (is_write) {
> >> >> + if (!(*reg & ICC_SRE_EL1_SRE))
> >> >> + return false;
> >> >> + } else {
> >> >> + *reg = vgicv3->vgic_sre;
> >> >> + }
> >> >> +
> >> >> + return true;
> >> >> +}
> >> >> diff --git a/virt/kvm/arm/vgic/vgic-sys-reg-v3.c b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> >> >> new file mode 100644
> >> >> index 0000000..82c2f02
> >> >> --- /dev/null
> >> >> +++ b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> >> >> @@ -0,0 +1,142 @@
> >> >> +/*
> >> >> + * VGIC system registers handling functions
> >> >> + *
> >> >> + * This program is free software; you can redistribute it and/or modify
> >> >> + * it under the terms of the GNU General Public License version 2 as
> >> >> + * published by the Free Software Foundation.
> >> >> + *
> >> >> + * This program is distributed in the hope that it will be useful,
> >> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> >> + * GNU General Public License for more details.
> >> >> + */
> >> >> +
> >> >> +#include <linux/kvm.h>
> >> >> +#include <linux/kvm_host.h>
> >> >> +#include <asm/kvm_emulate.h>
> >> >> +#include "vgic.h"
> >> >> +#include "sys_regs.h"
> >> >> +
> >> >> +#define ACCESS_SYS_REG(REG) \
> >> >> +static bool access_gic_##REG##_sys_reg(struct kvm_vcpu *vcpu, \
> >> >> + struct sys_reg_params *p, \
> >> >> + const struct sys_reg_desc *r) \
> >> >> +{ \
> >> >> + unsigned long tmp; \
> >> >> + bool ret; \
> >> >> + \
> >> >> + if (p->is_write) \
> >> >> + tmp = p->regval; \
> >> >> + ret = access_gic_##REG##_reg(vcpu, p->is_write, &tmp); \
> >> >> + if (!p->is_write) \
> >> >> + p->regval = tmp; \
> >> >> + \
> >> >> + return ret; \
> >> >> +}
> >> >> +
> >> >> +ACCESS_SYS_REG(ctlr)
> >> >> +ACCESS_SYS_REG(pmr)
> >> >> +ACCESS_SYS_REG(bpr0)
> >> >> +ACCESS_SYS_REG(bpr1)
> >> >> +ACCESS_SYS_REG(sre)
> >> >> +ACCESS_SYS_REG(grpen0)
> >> >> +ACCESS_SYS_REG(grpen1)
> >> >> +
> >> >> +#define ACCESS_APNR_SYS_REG(REG) \
> >> >> +static bool access_gic_##REG##_sys_reg(struct kvm_vcpu *vcpu, \
> >> >> + struct sys_reg_params *p, \
> >> >> + const struct sys_reg_desc *r) \
> >> >> +{ \
> >> >> + unsigned long tmp; \
> >> >> + u8 idx = p->Op2 & 3; \
> >> >> + bool ret; \
> >> >> + \
> >> >> + if (p->is_write) \
> >> >> + tmp = p->regval; \
> >> >> + ret = access_gic_##REG##_reg(vcpu, p->is_write, idx, &tmp); \
> >> >> + if (!p->is_write) \
> >> >> + p->regval = tmp; \
> >> >> + \
> >> >> + return ret; \
> >> >> +}
> >> >> +
> >> >> +ACCESS_APNR_SYS_REG(ap0r)
> >> >> +ACCESS_APNR_SYS_REG(ap1r)
> >> >
> >> > I don't get these indirections. Why can't you call the functions
> >> > directly?
> >>
> >> The code is same for accessing the registers hence added this indirection.
> >>
> >
> > That's not answering my question.
> >
> > What is the benefit of adding this indirection as opposed to having the
> > functions called directly?
>
> In sys_reg_desc the access function is of type
>
> bool (*access)(struct kvm_vcpu *,
> struct sys_reg_params *,
> const struct sys_reg_desc *);
>
> Where as the each register access function is of type below to support
> access to AArch32(later if not now).
>
> bool access_gic_xxx(struct kvm_vcpu *vcpu, bool is_write, unsigned long *reg);
>
> I can drop this macro and make function calls for each reg access.
>
Please don't worry about the 32-bit side until we actually implement
that. And once we do, we can move things around in patches to support
the 32-bit side so that it makes sense to the reader.
So, for now, just have this one file, moved to arch/arm64/kvm/ where all
the access functions are static in this file and called directly from
the single dispatch function.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH V2 fix 5/6] mm: hugetlb: add a new function to allocate a new gigantic page
From: Vlastimil Babka @ 2016-11-29 10:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161129090322.GB16569@sha-win-210.asiapac.arm.com>
On 11/29/2016 10:03 AM, Huang Shijie wrote:
> On Mon, Nov 28, 2016 at 03:17:28PM +0100, Vlastimil Babka wrote:
>> On 11/16/2016 07:55 AM, Huang Shijie wrote:
>> > +static struct page *__hugetlb_alloc_gigantic_page(struct hstate *h,
>> > + struct vm_area_struct *vma, unsigned long addr, int nid)
>> > +{
>> > + NODEMASK_ALLOC(nodemask_t, nodes_allowed, GFP_KERNEL | __GFP_NORETRY);
>>
>> What if the allocation fails and nodes_allowed is NULL?
>> It might work fine now, but it's rather fragile, so I'd rather see an
> Yes.
>
>> explicit check.
> See the comment below.
>
>>
>> BTW same thing applies to __nr_hugepages_store_common().
>>
>> > + struct page *page = NULL;
>> > +
>> > + /* Not NUMA */
>> > + if (!IS_ENABLED(CONFIG_NUMA)) {
>> > + if (nid == NUMA_NO_NODE)
>> > + nid = numa_mem_id();
>> > +
>> > + page = alloc_gigantic_page(nid, huge_page_order(h));
>> > + if (page)
>> > + prep_compound_gigantic_page(page, huge_page_order(h));
>> > +
>> > + NODEMASK_FREE(nodes_allowed);
>> > + return page;
>> > + }
>> > +
>> > + /* NUMA && !vma */
>> > + if (!vma) {
>> > + if (nid == NUMA_NO_NODE) {
>> > + if (!init_nodemask_of_mempolicy(nodes_allowed)) {
>> > + NODEMASK_FREE(nodes_allowed);
>> > + nodes_allowed = &node_states[N_MEMORY];
>> > + }
>> > + } else if (nodes_allowed) {
> The check is here.
It's below a possible usage of nodes_allowed as an argument of
init_nodemask_of_mempolicy(mask). Which does
if (!(mask && current->mempolicy))
return false;
which itself looks like an error at first sight :)
> Do we really need to re-arrange the code here for the explicit check? :)
We don't need it *now* to be correct, but I still find it fragile. Also it
mixes up the semantic of NULL as a conscious "default" value, and NULL as
a side-effect of memory allocation failure. Nothing good can come from that in
the long term :)
> Thanks
> Huang Shijie
>> > + init_nodemask_of_node(nodes_allowed, nid);
>> > + } else {
>> > + nodes_allowed = &node_states[N_MEMORY];
>> > + }
>> > +
>> > + page = alloc_fresh_gigantic_page(h, nodes_allowed, true);
>> > +
>
^ permalink raw reply
* [PATCH] ARM: davinci: da8xx: Fix sleeping function called from invalid context
From: Sekhar Nori @ 2016-11-29 10:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480350566-26225-1-git-send-email-abailon@baylibre.com>
On Monday 28 November 2016 09:59 PM, Alexandre Bailon wrote:
> Everytime the usb20 phy is enabled, there is a
> "sleeping function called from invalid context" BUG.
Who calls PHY clk_enable() from non-preemptible context? Can you provide
the call stack?
> usb20_phy_clk_enable(), called with the irq disabled uses
> clk_get() and clk_enable_prepapre() which may sleep.
> Move clk_get() to da8xx_register_usb20_phy_clk() and
> replace clk_prepare_enable() by clk_enable().
>
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> ---
> arch/arm/mach-davinci/usb-da8xx.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
> index b010e5f..c9b5cd4 100644
> --- a/arch/arm/mach-davinci/usb-da8xx.c
> +++ b/arch/arm/mach-davinci/usb-da8xx.c
> @@ -156,23 +156,23 @@ int __init da8xx_register_usb_refclkin(int rate)
> return 0;
> }
>
> +static struct clk *usb20_clk;
> +
> static void usb20_phy_clk_enable(struct clk *clk)
> {
> - struct clk *usb20_clk;
> int err;
> u32 val;
> u32 timeout = 500000; /* 500 msec */
>
> val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
>
> - usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
> - if (IS_ERR(usb20_clk)) {
> + if (!usb20_clk || IS_ERR(usb20_clk)) {
NULL is a valid clock handle. There is no way clock enable of
usb20_phy_clk can be invoked if its not registered. So, you can assume
that usb20_clk is valid if you get here.
> pr_err("could not get usb20 clk: %ld\n", PTR_ERR(usb20_clk));
> return;
> }
>
> /* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
> - err = clk_prepare_enable(usb20_clk);
> + err = clk_enable(usb20_clk);
> if (err) {
> pr_err("failed to enable usb20 clk: %d\n", err);
> clk_put(usb20_clk);
> @@ -197,8 +197,7 @@ static void usb20_phy_clk_enable(struct clk *clk)
>
> pr_err("Timeout waiting for USB 2.0 PHY clock good\n");
> done:
> - clk_disable_unprepare(usb20_clk);
> - clk_put(usb20_clk);
> + clk_disable(usb20_clk);
I noticed that we are missing clk_disable(usb20_clk) in
usb20_phy_clk_disable(). It will now be easier to do that after this
patch. Can you add that in a separate patch?
> }
>
> static void usb20_phy_clk_disable(struct clk *clk)
> @@ -287,6 +286,10 @@ int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
> struct clk *parent;
> int ret = 0;
>
> + usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
> + if (IS_ERR(usb20_clk))
> + return PTR_ERR(parent);
> +
> parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux");
> if (IS_ERR(parent))
> return PTR_ERR(parent);
clk_put(usb20_clk) should be called here on failure path.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly
From: Christoffer Dall @ 2016-11-29 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c75fe6ae-8ae0-285d-6f47-3e28c7e8f431@arm.com>
On Tue, Nov 29, 2016 at 09:37:07AM +0000, Marc Zyngier wrote:
> On 28/11/16 19:42, Christoffer Dall wrote:
> > On Mon, Nov 28, 2016 at 06:39:04PM +0000, Marc Zyngier wrote:
> >> On 28/11/16 17:43, Marc Zyngier wrote:
> >>> Hi Jintack,
> >>>
> >>> On 28/11/16 16:46, Jintack Lim wrote:
> >>>> Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
> >>>> EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they
> >>>> are 11th and 10th bits respectively when E2H is set. Current code is
> >>>> unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set, which
> >>>> may allow guest OS to access physical timer. So, fix it.
> >>>>
> >>>> Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
> >>>> ---
> >>>> arch/arm/include/asm/kvm_timer.h | 33 +++++++++++++++++++
> >>>> arch/arm64/include/asm/kvm_timer.h | 62 ++++++++++++++++++++++++++++++++++++
> >>>> include/clocksource/arm_arch_timer.h | 6 ++--
> >>>> virt/kvm/arm/hyp/timer-sr.c | 8 ++---
> >>>> 4 files changed, 103 insertions(+), 6 deletions(-)
> >>>> create mode 100644 arch/arm/include/asm/kvm_timer.h
> >>>> create mode 100644 arch/arm64/include/asm/kvm_timer.h
> >>>>
> >>
> >> [...]
> >>
> >>> We could make it nicer (read "faster") by introducing a
> >>> hyp_alternate_select construct that only returns a value instead
> >>> of calling a function. I remember writing something like that
> >>> at some point, and dropping it...
> >>
> >> So here's what this could look like (warning, wacky code ahead,
> >> though I fixed a stupid bug that was present in the previous patch).
> >> The generated code is quite nice (no branch, only an extra mov
> >> instruction on the default path)... Of course, completely untested!
> >
> > Isn't this all about determining which bitmask to use, statically, once,
> > after the system has booted?
> >
> > How about a good old fashioned static variable, or global struct like
> > the global one we use for the VGIC, which sets the proper mit mask
> > during kvm init, and the world-switch code just uses a variable?
>
> We could indeed do that (I've been carried away with my tendency for
> weird and wonderful hacks).
>
> But as Jintack mentioned, there is a much better approach, which is to
> do nothing at all on the VHE path (we can set the permission bits once
> and for all). cntvoff_el2 also falls into the same category of things we
> should be able to only restore and not bother resetting (as it doesn't
> affect the EL2 virtual counter).
>
> Thoughts?
>
Yes, that sounds much better.
I have some patches to get rid of a lot of things, like cntvoff, during
the world-switch for VHE, so if Jintack just wants to focus on the
cnthctl I will catch cntvoff later.
-Christoffer
^ permalink raw reply
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