* [PATCH v2 2/2] soc: zte: pm_domains: Add support for zx296718 board
From: Jun Nie @ 2016-12-06 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480987828-20549-2-git-send-email-baoyou.xie@linaro.org>
2016-12-06 9:30 GMT+08:00 Baoyou Xie <baoyou.xie@linaro.org>:
> This patch introduces the power domain driver of zx296718
> which belongs to zte's 2967 family.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> ---
> drivers/soc/zte/Makefile | 2 +-
> drivers/soc/zte/zx296718_pm_domains.c | 182 ++++++++++++++++++++++++++++++++++
> 2 files changed, 183 insertions(+), 1 deletion(-)
> create mode 100644 drivers/soc/zte/zx296718_pm_domains.c
>
> diff --git a/drivers/soc/zte/Makefile b/drivers/soc/zte/Makefile
> index 97ac8ea..2d2a2cc 100644
> --- a/drivers/soc/zte/Makefile
> +++ b/drivers/soc/zte/Makefile
> @@ -1,4 +1,4 @@
> #
> # zx SOC drivers
> #
> -obj-$(CONFIG_ZX_PM_DOMAINS) += pm_domains.o
> +obj-$(CONFIG_ZX_PM_DOMAINS) += pm_domains.o zx296718_pm_domains.o
> diff --git a/drivers/soc/zte/zx296718_pm_domains.c b/drivers/soc/zte/zx296718_pm_domains.c
> new file mode 100644
> index 0000000..ed18b33
> --- /dev/null
> +++ b/drivers/soc/zte/zx296718_pm_domains.c
> @@ -0,0 +1,182 @@
> +/*
> + * Copyright (C) 2015 ZTE Ltd.
> + *
> + * Author: Baoyou Xie <baoyou.xie@linaro.org>
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +#include <dt-bindings/arm/zte_pm_domains.h>
> +#include "pm_domains.h"
> +
> +static u16 zx296718_offsets[REG_ARRAY_SIZE] = {
> + [REG_CLKEN] = 0x18,
> + [REG_ISOEN] = 0x1c,
> + [REG_RSTEN] = 0x20,
> + [REG_PWREN] = 0x24,
> + [REG_ACK_SYNC] = 0x28,
> +};
> +
> +enum {
> + PCU_DM_VOU = 0,
> + PCU_DM_SAPPU,
> + PCU_DM_VDE,
> + PCU_DM_VCE,
> + PCU_DM_HDE,
> + PCU_DM_VIU,
> + PCU_DM_USB20,
> + PCU_DM_USB21,
> + PCU_DM_USB30,
> + PCU_DM_HSIC,
> + PCU_DM_GMAC,
> + PCU_DM_TS,
> +};
> +
> +static struct zx_pm_domain vou_domain = {
> + .dm = {
> + .name = "vou_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_VOU,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain sappu_domain = {
> + .dm = {
> + .name = "sappu_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_SAPPU,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain vde_domain = {
> + .dm = {
> + .name = "vde_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_VDE,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain vce_domain = {
> + .dm = {
> + .name = "vce_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_VCE,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain hde_domain = {
> + .dm = {
> + .name = "hde_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_HDE,
> + .reg_offset = zx296718_offsets,
> +};
> +
> +static struct zx_pm_domain viu_domain = {
> + .dm = {
> + .name = "viu_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_VIU,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain usb20_domain = {
> + .dm = {
> + .name = "usb20_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_USB20,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain usb21_domain = {
> + .dm = {
> + .name = "usb21_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_USB21,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain usb30_domain = {
> + .dm = {
> + .name = "usb30_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_USB30,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain hsic_domain = {
> + .dm = {
> + .name = "hsic_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_HSIC,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain gmac_domain = {
> + .dm = {
> + .name = "gmac_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_GMAC,
> + .reg_offset = zx296718_offsets,
> +};
> +static struct zx_pm_domain ts_domain = {
> + .dm = {
> + .name = "ts_domain",
> + .power_off = zx_normal_power_off,
> + .power_on = zx_normal_power_on,
> + },
> + .bit = PCU_DM_TS,
> + .reg_offset = zx296718_offsets,
> +};
> +struct generic_pm_domain *zx296718_pm_domains[] = {
> + [DM_ZX296718_SAPPU] = &sappu_domain.dm,
> + [DM_ZX296718_VDE] = &vde_domain.dm,
> + [DM_ZX296718_VCE] = &vce_domain.dm,
> + [DM_ZX296718_HDE] = &hde_domain.dm,
> + [DM_ZX296718_VIU] = &viu_domain.dm,
> + [DM_ZX296718_USB20] = &usb20_domain.dm,
> + [DM_ZX296718_USB21] = &usb21_domain.dm,
> + [DM_ZX296718_USB30] = &usb30_domain.dm,
> + [DM_ZX296718_HSIC] = &hsic_domain.dm,
> + [DM_ZX296718_GMAC] = &gmac_domain.dm,
> + [DM_ZX296718_TS] = &ts_domain.dm,
> + [DM_ZX296718_VOU] = &vou_domain.dm,
> +};
> +
> +static int zx296718_pd_probe(struct platform_device *pdev)
> +{
> + return zx_pd_probe(pdev,
> + zx296718_pm_domains,
> + ARRAY_SIZE(zx296718_pm_domains));
> +}
> +
> +static const struct of_device_id zx296718_pm_domain_matches[] = {
> + { .compatible = "zte,zx296718-pcu", },
> + { },
> +};
> +
> +static struct platform_driver zx296718_pd_driver = {
> + .driver = {
> + .name = "zx-powerdomain",
> + .owner = THIS_MODULE,
> + .of_match_table = zx296718_pm_domain_matches,
> + },
> + .probe = zx296718_pd_probe,
> +};
> +
> +static int __init zx296718_pd_init(void)
> +{
> + return platform_driver_register(&zx296718_pd_driver);
> +}
> +subsys_initcall(zx296718_pd_init);
> --
> 2.7.4
>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply
* [RFC PATCH 0/3] clk: at91: audio PLL clock
From: Nicolas Ferre @ 2016-12-06 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1481021115.git.nicolas.ferre@atmel.com>
Le 06/12/2016 ? 11:55, Nicolas Ferre a ?crit :
> This series covers the addition of the Audio PLL clock found on AT91 SoCs like
> the SAMA5D2.
> I also added the use of these clocks by the ClassD audi amplifier in both SoC
> and board DT.
>
> The Audio PLL is described in the sama5d2 datasheet chapter "29.8 Audio PLL".
>
> Even if "it works" (!), note that I'm not satisfied with the current code and
> would need some advice from people more accustomed with the CCF and
> particularly composite audio PLL/clocks like these. For example, I do not take
> into account the limits of these clocks (as described in the datasheet) and the
> dependency between the PAD and the PMC child clocks.
>
> Thanks in advance for your inputs.
Note as well that Boris already sent me a review of the first posting of
this patch ("[PATCH] clk: at91: add audio pll clock driver" on 31 Jul.
2015) and most of his comments are still relevant.
https://patchwork.kernel.org/patch/6910111/
https://www.spinics.net/lists/arm-kernel/msg436120.html
But I would like some comments about the whole architecture of these
clocks and how I could rearrange them and maybe use some of the common
facilities of the CCF (composite with gate + fractionnal? + divider?, etc.)
Regards,
> Cyrille Pitchen (2):
> ARM: dts: at91: sama5d2: add classd nodes
> ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
>
> Nicolas Ferre (1):
> clk: at91: add audio pll clock driver
>
> .../devicetree/bindings/clock/at91-clock.txt | 10 +
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 16 ++
> arch/arm/boot/dts/sama5d2.dtsi | 39 +++-
> arch/arm/mach-at91/Kconfig | 4 +
> drivers/clk/at91/Makefile | 2 +
> drivers/clk/at91/clk-audio-pll-pad.c | 238 +++++++++++++++++++
> drivers/clk/at91/clk-audio-pll-pmc.c | 184 +++++++++++++++
> drivers/clk/at91/clk-audio-pll.c | 253 +++++++++++++++++++++
> include/linux/clk/at91_pmc.h | 25 ++
> 9 files changed, 770 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c
> create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c
> create mode 100644 drivers/clk/at91/clk-audio-pll.c
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly
From: Marc Zyngier @ 2016-12-06 11:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480620725-9864-1-git-send-email-jintack@cs.columbia.edu>
On 01/12/16 19:32, Jintack Lim wrote:
> Current KVM world switch code is unintentionally setting wrong bits to
> CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
> timer. Bit positions of CNTHCTL_EL2 are changing depending on
> HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
> not set, but they are 11th and 10th bits respectively when E2H is set.
>
> In fact, on VHE we only need to set those bits once, not for every world
> switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
> 1, which makes those bits have no effect for the host kernel execution.
> So we just set those bits once for guests, and that's it.
>
> Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
> ---
> v2->v3:
> - Perform the initialization including CPU hotplug case.
> - Move has_vhe() to asm/virt.h
>
> v1->v2:
> - Skip configuring cnthctl_el2 in world switch path on VHE system.
> - Write patch based on linux-next.
> ---
> arch/arm/include/asm/virt.h | 5 +++++
> arch/arm/kvm/arm.c | 3 +++
> arch/arm64/include/asm/virt.h | 10 ++++++++++
> include/kvm/arm_arch_timer.h | 1 +
> virt/kvm/arm/arch_timer.c | 23 +++++++++++++++++++++++
> virt/kvm/arm/hyp/timer-sr.c | 33 +++++++++++++++++++++------------
> 6 files changed, 63 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
> index a2e75b8..6dae195 100644
> --- a/arch/arm/include/asm/virt.h
> +++ b/arch/arm/include/asm/virt.h
> @@ -80,6 +80,11 @@ static inline bool is_kernel_in_hyp_mode(void)
> return false;
> }
>
> +static inline bool has_vhe(void)
> +{
> + return false;
> +}
> +
> /* The section containing the hypervisor idmap text */
> extern char __hyp_idmap_text_start[];
> extern char __hyp_idmap_text_end[];
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index 8f92efa..13e54e8 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -1099,6 +1099,9 @@ static void cpu_init_hyp_mode(void *dummy)
> __cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
> __cpu_init_stage2();
>
> + if (is_kernel_in_hyp_mode())
> + kvm_timer_init_vhe();
> +
> kvm_arm_init_debug();
> }
>
> diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
> index fea1073..b043cfd 100644
> --- a/arch/arm64/include/asm/virt.h
> +++ b/arch/arm64/include/asm/virt.h
> @@ -47,6 +47,7 @@
> #include <asm/ptrace.h>
> #include <asm/sections.h>
> #include <asm/sysreg.h>
> +#include <asm/cpufeature.h>
>
> /*
> * __boot_cpu_mode records what mode CPUs were booted in.
> @@ -80,6 +81,15 @@ static inline bool is_kernel_in_hyp_mode(void)
> return read_sysreg(CurrentEL) == CurrentEL_EL2;
> }
>
> +static inline bool has_vhe(void)
> +{
> +#ifdef CONFIG_ARM64_VHE
Is there a particular reason why this should be guarded by a #ifdef? All
the symbols should always be available, and since this is a static key,
the overhead should be really insignificant (provided that you use a
non-prehistoric compiler...).
> + if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))
> + return true;
> +#endif
> + return false;
> +}
> +
> #ifdef CONFIG_ARM64_VHE
> extern void verify_cpu_run_el(void);
> #else
> diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
> index dda39d8..2d54903 100644
> --- a/include/kvm/arm_arch_timer.h
> +++ b/include/kvm/arm_arch_timer.h
> @@ -76,4 +76,5 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
>
> void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
>
> +void kvm_timer_init_vhe(void);
> #endif
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index 17b8fa5..c7c3bfd 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -24,6 +24,7 @@
>
> #include <clocksource/arm_arch_timer.h>
> #include <asm/arch_timer.h>
> +#include <asm/kvm_hyp.h>
>
> #include <kvm/arm_vgic.h>
> #include <kvm/arm_arch_timer.h>
> @@ -507,3 +508,25 @@ void kvm_timer_init(struct kvm *kvm)
> {
> kvm->arch.timer.cntvoff = kvm_phys_timer_read();
> }
> +
> +/*
> + * On VHE system, we only need to configure trap on physical timer and counter
> + * accesses in EL0 and EL1 once, not for every world switch.
> + * The host kernel runs at EL2 with HCR_EL2.TGE == 1,
> + * and this makes those bits have no effect for the host kernel execution.
> + */
> +void kvm_timer_init_vhe(void)
> +{
> + /* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */
> + u32 cnthctl_shift = 10;
> + u64 val;
> +
> + /*
> + * Disallow physical timer access for the guest.
> + * Physical counter access is allowed.
> + */
> + val = read_sysreg(cnthctl_el2);
> + val &= ~(CNTHCTL_EL1PCEN << cnthctl_shift);
> + val |= (CNTHCTL_EL1PCTEN << cnthctl_shift);
> + write_sysreg(val, cnthctl_el2);
> +}
> diff --git a/virt/kvm/arm/hyp/timer-sr.c b/virt/kvm/arm/hyp/timer-sr.c
> index 798866a..63e28dd 100644
> --- a/virt/kvm/arm/hyp/timer-sr.c
> +++ b/virt/kvm/arm/hyp/timer-sr.c
> @@ -35,10 +35,16 @@ void __hyp_text __timer_save_state(struct kvm_vcpu *vcpu)
> /* Disable the virtual timer */
> write_sysreg_el0(0, cntv_ctl);
>
> - /* Allow physical timer/counter access for the host */
> - val = read_sysreg(cnthctl_el2);
> - val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
> - write_sysreg(val, cnthctl_el2);
> + /*
> + * We don't need to do this for VHE since the host kernel runs in EL2
> + * with HCR_EL2.TGE ==1, which makes those bits have no impact.
> + */
> + if (!has_vhe()) {
> + /* Allow physical timer/counter access for the host */
> + val = read_sysreg(cnthctl_el2);
> + val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
> + write_sysreg(val, cnthctl_el2);
> + }
>
> /* Clear cntvoff for the host */
> write_sysreg(0, cntvoff_el2);
> @@ -50,14 +56,17 @@ void __hyp_text __timer_restore_state(struct kvm_vcpu *vcpu)
> struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
> u64 val;
>
> - /*
> - * Disallow physical timer access for the guest
> - * Physical counter access is allowed
> - */
> - val = read_sysreg(cnthctl_el2);
> - val &= ~CNTHCTL_EL1PCEN;
> - val |= CNTHCTL_EL1PCTEN;
> - write_sysreg(val, cnthctl_el2);
> + /* Those bits are already configured at boot on VHE-system */
> + if (!has_vhe()) {
> + /*
> + * Disallow physical timer access for the guest
> + * Physical counter access is allowed
> + */
> + val = read_sysreg(cnthctl_el2);
> + val &= ~CNTHCTL_EL1PCEN;
> + val |= CNTHCTL_EL1PCTEN;
> + write_sysreg(val, cnthctl_el2);
> + }
>
> if (timer->enabled) {
> write_sysreg(kvm->arch.timer.cntvoff, cntvoff_el2);
>
Otherwise, and assuming you're OK with me fixing the above nit (no need
to resend):
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v2] arm/arm64: KVM: VGIC: limit ITARGETSR bits to number of VCPUs
From: Marc Zyngier @ 2016-12-06 11:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116175716.31578-1-andre.przywara@arm.com>
On 16/11/16 17:57, Andre Przywara wrote:
> The GICv2 spec says in section 4.3.12 that a "CPU targets field bit that
> corresponds to an unimplemented CPU interface is RAZ/WI."
> Currently we allow the guest to write any value in there and it can
> read that back.
> Mask the written value with the proper CPU mask to be spec compliant.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Changes v1 .. v2:
> - use GENMASK() instead of open-coding mask
> - drop explicit 0xff masking, since cpu_mask is stronger anyway
>
> virt/kvm/arm/vgic/vgic-mmio-v2.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v2.c b/virt/kvm/arm/vgic/vgic-mmio-v2.c
> index b44b359..78e34bc 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio-v2.c
> +++ b/virt/kvm/arm/vgic/vgic-mmio-v2.c
> @@ -129,6 +129,7 @@ static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
> unsigned long val)
> {
> u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
> + u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
> int i;
>
> /* GICD_ITARGETSR[0-7] are read-only */
> @@ -141,7 +142,7 @@ static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
>
> spin_lock(&irq->irq_lock);
>
> - irq->targets = (val >> (i * 8)) & 0xff;
> + irq->targets = (val >> (i * 8)) & cpu_mask;
> target = irq->targets ? __ffs(irq->targets) : 0;
> irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
>
>
Applied, thanks.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH] arm/arm64: KVM: Check for properly initialized timer on init
From: Marc Zyngier @ 2016-12-06 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205093211.11870-1-christoffer.dall@linaro.org>
On 05/12/16 09:32, Christoffer Dall wrote:
> When the arch timer code fails to initialize (for example because the
> memory mapped timer doesn't work, which is currently seen with the AEM
> model), then KVM just continues happily with a final result that KVM
> eventually does a NULL pointer dereference of the uninitialized cycle
> counter.
>
> Check directly for this in the init path and give the user a reasonable
> error in this case.
>
> Cc: Shih-Wei Li <shihwei@cs.columbia.edu>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> ---
> virt/kvm/arm/arch_timer.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index 27a1f63..5c12f53 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -425,6 +425,11 @@ int kvm_timer_hyp_init(void)
> info = arch_timer_get_kvm_info();
> timecounter = &info->timecounter;
>
> + if (!timecounter->cc) {
> + kvm_err("arch_timer: uninitialized timecounter\n");
For consistency, I'll change the error message to say "kvm_arch_timer",
just like the below case.
> + return -ENODEV;
> + }
> +
> if (info->virtual_irq <= 0) {
> kvm_err("kvm_arch_timer: invalid virtual timer IRQ: %d\n",
> info->virtual_irq);
>
Otherwise looks good to me. I'll queue it now.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH] SCPI (pre-v1.0): fix reading sensor value
From: Sudeep Holla @ 2016-12-06 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFBinCD4RexWZPTm2hKjk6hqcmuCHiGoBDhwzgtx+0ns6sE70A@mail.gmail.com>
On 02/12/16 22:54, Martin Blumenstingl wrote:
> Hello Sudeep,
>
> On Fri, Nov 25, 2016 at 1:56 AM, Martin Blumenstingl
> <martin.blumenstingl@googlemail.com> wrote:
>> On Thu, Nov 24, 2016 at 12:15 PM, Martin Blumenstingl
>> <martin.blumenstingl@googlemail.com> wrote:
>>> On Thu, Nov 24, 2016 at 11:47 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:
>>>>
>>>>
>>>> On 24/11/16 00:18, Martin Blumenstingl wrote:
>>>>>
>>>>> I observed the following "strange" value when trying to read the SCPI
>>>>> temperature sensor on my Amlogic GXM S912 device:
>>>>> $ cat /sys/class/hwmon/hwmon0/temp1_input
>>>>> 6875990994467160116
>>>>>
>>>>> The value reported by the original kernel (Amlogic vendor kernel, after
>>>>> a reboot obviously) was 53C.
>>>>> The Amlogic SCPI driver only uses a single 32bit value to read the
>>>>> sensor value, instead of two. After stripping the upper 32bits from
>>>>> above value gives "52" as result, which is basically identical to
>>>>> what the vendor kernel reports.
>>>>
>>>>
>>>> Can you check why the upper 32-bit is not set to 0 ?
>>>>
>>>> In scpi_process_cmd, we memset extra rx_buf length by 0 and that should
>>>> take care. Neil had mentioned that works but now I doubt if firmware
>>>> returns 8 instead of 4 in the size which is wrong as it supports only
>>>> 32-bit.
>>> according to the code "RX Length is not replied by the legacy
>>> Firmware", so for legacy firmwares the "if (match->rx_len > len)"
>>> condition will never be true (because both values are always equal).
>>> in the sensor case we then go and copy 8 byte from mem->payload to
>>> match->rx_buf, but SCPI firmware only wrote 4 bytes to mem->payload.
>>> This means we are simply reading 4 byte (hi_val) of uninitialized
>>> memory - which may be all zeroes if we're lucky - but in my case I got
>>> "garbage" (I guess it's the second byte from the *previous* command
>>> which are leaking here).
>>>
>>> while writing this I see a second (more generic) approach which might
>>> work as well:
>>> scpi_chan does not hold any information about rx_payload/tx_payload
>>> sizes (these are calculated in scpi_probe but not stored anywhere).
>>> (for now, let's assume we had the rx_payload_size available)
>>> we could then go ahead and memset(rx_payload, 0, rx_payload_size) in
>>> scpi_tx_prepare or scpi_send_message.
>>> However, I am not sure if that would have any side-effects (for
>>> example on newer SCPI implementations).
>> I simply tried implementing this solution and I find it better than
>> the old one. However, I am still not sure if there are any
>> side-effects. maybe you can simply review v2 of this series which
>> implements the described approach (the result is the same as with v1:
>> temp1_input contains the correct value).
>
> did you have time to review this yet?
>
I was away, I will look into this today or tomorrow.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v9 01/11] arm/arm64: vgic: Implement support for userspace access
From: Auger Eric @ 2016-12-06 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161128130512.GC18170@cbox>
Hi,
On 28/11/2016 14:05, Christoffer Dall wrote:
> On Wed, Nov 23, 2016 at 06:31:48PM +0530, vijay.kilari at gmail.com wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>
>> Read and write of some registers like ISPENDR and ICPENDR
>> from userspace requires special handling when compared to
>> guest access for these registers.
>>
>> Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
>> for handling of ISPENDR, ICPENDR registers handling.
>>
>> Add infrastructure to support guest and userspace read
>> and write for the required registers
>> Also moved vgic_uaccess from vgic-mmio-v2.c to vgic-mmio.c
>>
>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>> ---
>> virt/kvm/arm/vgic/vgic-mmio-v2.c | 25 ----------
>> virt/kvm/arm/vgic/vgic-mmio-v3.c | 102 ++++++++++++++++++++++++++++++++-------
>> virt/kvm/arm/vgic/vgic-mmio.c | 78 +++++++++++++++++++++++++++---
>> virt/kvm/arm/vgic/vgic-mmio.h | 19 ++++++++
>> 4 files changed, 175 insertions(+), 49 deletions(-)
>>
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v2.c b/virt/kvm/arm/vgic/vgic-mmio-v2.c
>> index b44b359..0b32f40 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio-v2.c
>> +++ b/virt/kvm/arm/vgic/vgic-mmio-v2.c
>> @@ -406,31 +406,6 @@ int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
>> return -ENXIO;
>> }
>>
>> -/*
>> - * When userland tries to access the VGIC register handlers, we need to
>> - * create a usable struct vgic_io_device to be passed to the handlers and we
>> - * have to set up a buffer similar to what would have happened if a guest MMIO
>> - * access occurred, including doing endian conversions on BE systems.
>> - */
>> -static int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
>> - bool is_write, int offset, u32 *val)
>> -{
>> - unsigned int len = 4;
>> - u8 buf[4];
>> - int ret;
>> -
>> - if (is_write) {
>> - vgic_data_host_to_mmio_bus(buf, len, *val);
>> - ret = kvm_io_gic_ops.write(vcpu, &dev->dev, offset, len, buf);
>> - } else {
>> - ret = kvm_io_gic_ops.read(vcpu, &dev->dev, offset, len, buf);
>> - if (!ret)
>> - *val = vgic_data_mmio_bus_to_host(buf, len);
>> - }
>> -
>> - return ret;
>> -}
>> -
>> int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
>> int offset, u32 *val)
>> {
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
>> index 50f42f0..8e76d04 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
>> +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
>> @@ -207,6 +207,66 @@ static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
>> return 0;
>> }
>>
>> +static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
>> + gpa_t addr, unsigned int len)
>> +{
>> + u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
>> + u32 value = 0;
>> + int i;
>> +
>> + /*
>> + * A level triggerred interrupt pending state is latched in both
>> + * "soft_pending" and "line_level" variables. Userspace will save
>> + * and restore soft_pending and line_level separately.
>> + * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
>> + * handling of ISPENDR and ICPENDR.
>> + */
>> + for (i = 0; i < len * 8; i++) {
>> + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>> +
>> + if (irq->config == VGIC_CONFIG_LEVEL && irq->soft_pending)
>> + value |= (1U << i);
>> + if (irq->config == VGIC_CONFIG_EDGE && irq->pending)
>> + value |= (1U << i);
>> +
>> + vgic_put_irq(vcpu->kvm, irq);
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static void vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
>> + gpa_t addr, unsigned int len,
>> + unsigned long val)
>> +{
>> + u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
>> + int i;
>> +
>> + for (i = 0; i < len * 8; i++) {
>> + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>> +
>> + spin_lock(&irq->irq_lock);
>> + if (test_bit(i, &val)) {
>> + /* soft_pending is set irrespective of irq type
>> + * (level or edge) to avoid dependency that VM should
>> + * restore irq config before pending info.
>> + */
>
> nit: kernel commenting style
>
>> + irq->pending = true;
>> + irq->soft_pending = true;
>> + vgic_queue_irq_unlock(vcpu->kvm, irq);
>> + } else {
>> + irq->soft_pending = false;
>> + if (irq->config == VGIC_CONFIG_EDGE ||
>> + (irq->config == VGIC_CONFIG_LEVEL &&
>> + !irq->line_level))
>> + irq->pending = false;
I am confused by the comment above. Since we test the irq config here
don't we assume the config was restored before the pending state?
>> + spin_unlock(&irq->irq_lock);
>> + }
>> +
>> + vgic_put_irq(vcpu->kvm, irq);
>> + }
>> +}
>> +
>> /* We want to avoid outer shareable. */
>> u64 vgic_sanitise_shareability(u64 field)
>> {
>> @@ -356,7 +416,7 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
>> * We take some special care here to fix the calculation of the register
>> * offset.
>> */
>> -#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
>> +#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
>> { \
>> .reg_offset = off, \
>> .bits_per_irq = bpi, \
>> @@ -371,6 +431,8 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
>> .access_flags = acc, \
>> .read = rd, \
>> .write = wr, \
>> + .uaccess_read = ur, \
>> + .uaccess_write = uw, \
>> }
>>
>> static const struct vgic_register_region vgic_v3_dist_registers[] = {
>> @@ -378,40 +440,42 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
>> vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
>> - vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
>> + vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
>> - vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
>> + vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
>> - vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
>> + vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
>> - vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
>> + vgic_mmio_read_pending, vgic_mmio_write_spending,
>> + vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
>> - vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
>> + vgic_mmio_read_pending, vgic_mmio_write_cpending,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
>> - vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
>> + vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
>> - vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
>> + vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
>> - vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
>> - VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
>> + vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
>> + 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
>> - vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
>> VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
>> - vgic_mmio_read_config, vgic_mmio_write_config, 2,
>> + vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
>> - vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
>> - vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
>> + vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
>> VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
>> vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
>> @@ -449,11 +513,13 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
>> REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
>> vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
>> VGIC_ACCESS_32bit),
>> - REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
>> - vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
>> + REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
>> + vgic_mmio_read_pending, vgic_mmio_write_spending,
>> + vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
>> VGIC_ACCESS_32bit),
>> - REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
>> - vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
>> + REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
>> + vgic_mmio_read_pending, vgic_mmio_write_cpending,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
>> vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
>> index ebe1b9f..d5f3ee2 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio.c
>> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
>> @@ -484,6 +484,74 @@ static bool check_region(const struct kvm *kvm,
>> return false;
>> }
>>
>> +static const struct vgic_register_region *
>> +vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
>> + gpa_t addr, int len)
>> +{
>> + const struct vgic_register_region *region;
>> +
>> + region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
>> + addr - iodev->base_addr);
>> + if (!region || !check_region(vcpu->kvm, region, addr, len))
>> + return NULL;
>> +
>> + return region;
>> +}
>> +
>> +static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
>> + gpa_t addr, u32 *val)
>> +{
>> + struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
>> + const struct vgic_register_region *region;
>> + struct kvm_vcpu *r_vcpu;
>> +
>> + region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
>> + if (!region) {
>> + *val = 0;
>> + return 0;
do we really want to return 0 here? -ENXIO?
I see that dispatch_mmio_read/write return 0 in that case but I don't
see any reason either? Other kvm_io_device_ops seem to return
-EOPNOTSUPP in such a case.
Thanks
Eric
>> + }
>> +
>> + r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
>> + if (region->uaccess_read)
>> + *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
>> + else
>> + *val = region->read(r_vcpu, addr, sizeof(u32));
>> +
>> + return 0;
>> +}
>> +
>> +static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
>> + gpa_t addr, const u32 *val)
>> +{
>> + struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
>> + const struct vgic_register_region *region;
>> + struct kvm_vcpu *r_vcpu;
>> +
>> + region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
>> + if (!region)
>> + return 0;
same?
>> +
>> + r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
>> + if (region->uaccess_write)
>> + region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
>> + else
>> + region->write(r_vcpu, addr, sizeof(u32), *val);
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Userland access to VGIC registers.
>> + */
>> +int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
>> + bool is_write, int offset, u32 *val)
>> +{
>> + if (is_write)
>> + return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
>> + else
>> + return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
>> +}
>> +
>> static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
>> gpa_t addr, int len, void *val)
>> {
>> @@ -491,9 +559,8 @@ static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
>> const struct vgic_register_region *region;
>> unsigned long data = 0;
>>
>> - region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
>> - addr - iodev->base_addr);
>> - if (!region || !check_region(vcpu->kvm, region, addr, len)) {
>> + region = vgic_get_mmio_region(vcpu, iodev, addr, len);
>> + if (!region) {
>> memset(val, 0, len);
>> return 0;
>> }
>> @@ -524,9 +591,8 @@ static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
>> const struct vgic_register_region *region;
>> unsigned long data = vgic_data_mmio_bus_to_host(val, len);
>>
>> - region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
>> - addr - iodev->base_addr);
>> - if (!region || !check_region(vcpu->kvm, region, addr, len))
>> + region = vgic_get_mmio_region(vcpu, iodev, addr, len);
>> + if (!region)
>> return 0;
>>
>> switch (iodev->iodev_type) {
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
>> index 84961b4..7b30296 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio.h
>> +++ b/virt/kvm/arm/vgic/vgic-mmio.h
>> @@ -34,6 +34,10 @@ struct vgic_register_region {
>> gpa_t addr, unsigned int len,
>> unsigned long val);
>> };
>> + unsigned long (*uaccess_read)(struct kvm_vcpu *vcpu, gpa_t addr,
>> + unsigned int len);
>> + void (*uaccess_write)(struct kvm_vcpu *vcpu, gpa_t addr,
>> + unsigned int len, unsigned long val);
>> };
>>
>> extern struct kvm_io_device_ops kvm_io_gic_ops;
>> @@ -86,6 +90,18 @@ struct vgic_register_region {
>> .write = wr, \
>> }
>>
>> +#define REGISTER_DESC_WITH_LENGTH_UACCESS(off, rd, wr, urd, uwr, length, acc) \
>> + { \
>> + .reg_offset = off, \
>> + .bits_per_irq = 0, \
>> + .len = length, \
>> + .access_flags = acc, \
>> + .read = rd, \
>> + .write = wr, \
>> + .uaccess_read = urd, \
>> + .uaccess_write = uwr, \
>> + }
>> +
>> int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
>> struct vgic_register_region *reg_desc,
>> struct vgic_io_device *region,
>> @@ -158,6 +174,9 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
>> gpa_t addr, unsigned int len,
>> unsigned long val);
>>
>> +int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
>> + bool is_write, int offset, u32 *val);
>> +
>> unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
>>
>> unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
>> --
>> 1.9.1
>>
>
> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCHv4 05/10] arm64: Use __pa_symbol for kernel symbols
From: Catalin Marinas @ 2016-12-06 11:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <72eb08c8-4f2c-6cb9-1e23-0860fd153a2e@gmail.com>
On Mon, Dec 05, 2016 at 04:50:33PM -0800, Florian Fainelli wrote:
> On 11/29/2016 10:55 AM, Laura Abbott wrote:
> > __pa_symbol is technically the marco that should be used for kernel
> > symbols. Switch to this as a pre-requisite for DEBUG_VIRTUAL which
> > will do bounds checking. As part of this, introduce lm_alias, a
> > macro which wraps the __va(__pa(...)) idiom used a few places to
> > get the alias.
> >
> > Signed-off-by: Laura Abbott <labbott@redhat.com>
> > ---
> > v4: Stop calling __va early, conversion of a few more sites. I decided against
> > wrapping the __p*d_populate calls into new functions since the call sites
> > should be limited.
> > ---
>
>
> > - pud_populate(&init_mm, pud, bm_pmd);
> > + if (pud_none(*pud))
> > + __pud_populate(pud, __pa_symbol(bm_pmd), PMD_TYPE_TABLE);
> > pmd = fixmap_pmd(addr);
> > - pmd_populate_kernel(&init_mm, pmd, bm_pte);
> > + __pmd_populate(pmd, __pa_symbol(bm_pte), PMD_TYPE_TABLE);
>
> Is there a particular reason why pmd_populate_kernel() is not changed to
> use __pa_symbol() instead of using __pa()? The other users in the arm64
> kernel is arch/arm64/kernel/hibernate.c which seems to call this against
> kernel symbols as well?
create_safe_exec_page() may allocate a pte from the linear map and
passes such pointer to pmd_populate_kernel(). The copy_pte() function
does something similar. In addition, we have the generic
__pte_alloc_kernel() in mm/memory.c using linear addresses.
--
Catalin
^ permalink raw reply
* [PATCH v3] arm64: Add DTS support for FSL's LS1012A SoC
From: Harninder Rai @ 2016-12-06 11:50 UTC (permalink / raw)
To: linux-arm-kernel
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.
Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:
- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.
- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.
- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.
- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
Changes in v3: Incorporated Shawn's comments
- Change PPI interrupts to IRQ_TYPE_LEVEL_LOW and
- SPI interrupts to IRQ_TYPE_LEVEL_HIGH
Changes in v2: Incorporated Shawn's comments
- Brief introduction of the SoC in commit message
- Alphabetic ordering of labeled nodes
- Better naming to be used for regulator node
- Make timer node's comments more readable
- Sort nodes with unit-address in order of the address
arch/arm64/boot/dts/freescale/Makefile | 3 +
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 115 ++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 128 +++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 59 +++++
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 245 +++++++++++++++++++++
5 files changed, 550 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6602718..39db645 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,3 +1,6 @@
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000..81bd689
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -0,0 +1,115 @@
+/*
+ * Device Tree file for Freescale LS1012A Freedom Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A Freedom Board";
+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ regulator_1p8v: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <25000000>;
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ codec: sgtl5000 at a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ VDDA-supply = <®ulator_1p8v>;
+ VDDIO-supply = <®ulator_1p8v>;
+ clocks = <&sys_mclk>;
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
new file mode 100644
index 0000000..b841251
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -0,0 +1,128 @@
+/*
+ * Device Tree file for Freescale LS1012A QDS Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A QDS Board";
+ compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ regulator_3p3v: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <24576000>;
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9547 at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ codec: sgtl5000 at a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ VDDA-supply = <®ulator_3p3v>;
+ VDDIO-supply = <®ulator_3p3v>;
+ clocks = <&sys_mclk>;
+ };
+ };
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
new file mode 100644
index 0000000..62c5c71
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -0,0 +1,59 @@
+/*
+ * Device Tree file for Freescale LS1012A RDB Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A RDB Board";
+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
new file mode 100644
index 0000000..92e64f3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -0,0 +1,245 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "fsl,ls1012a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+ <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
+ <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x2000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&dcfg>;
+ offset = <0xb0>;
+ mask = <0x02>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1012a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1012a-dcfg",
+ "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ big-endian;
+ };
+
+ clockgen: clocking at 1ee1000 {
+ compatible = "fsl,ls1012a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ i2c0: i2c at 2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ gpio0: gpio at 2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio at 2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wdog0: wdog at 2ad0000 {
+ compatible = "fsl,ls1012a-wdt",
+ "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ big-endian;
+ };
+
+ sai1: sai at 2b50000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b50000 0x0 0x10000>;
+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
+ <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 47>,
+ <&edma0 1 46>;
+ status = "disabled";
+ };
+
+ sai2: sai at 2b60000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b60000 0x0 0x10000>;
+ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
+ <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 45>,
+ <&edma0 1 44>;
+ status = "disabled";
+ };
+
+ edma0: edma at 2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
+ <0 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 3>,
+ <&clockgen 4 3>;
+ };
+
+ sata: sata at 3200000 {
+ compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] firmware: qcom: scm: Fix interrupted SCM calls
From: Will Deacon @ 2016-12-06 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480405463-23165-3-git-send-email-andy.gross@linaro.org>
On Tue, Nov 29, 2016 at 01:44:23AM -0600, Andy Gross wrote:
> This patch adds a Qualcomm specific quirk to the arm_smccc_smc call.
>
> On Qualcomm ARM64 platforms, the SMC call can return before it has
> completed. If this occurs, the call can be restarted, but it requires
> using the returned session ID value from the interrupted SMC call.
>
> The quirk stores off the session ID from the interrupted call in the
> quirk structure so that it can be used by the caller.
>
> This patch folds in a fix given by Sricharan R:
> https://lkml.org/lkml/2016/9/28/272
>
> Signed-off-by: Andy Gross <andy.gross@linaro.org>
> ---
> arch/arm64/kernel/smccc-call.S | 9 ++++++++-
> drivers/firmware/qcom_scm-64.c | 11 +++++++++--
> include/linux/arm-smccc.h | 11 ++++++++---
> 3 files changed, 25 insertions(+), 6 deletions(-)
Acked-by: Will Deacon <will.deacon@arm.com>
Will
^ permalink raw reply
* [PATCH 1/2] arm: kernel: Add SMC structure parameter
From: Will Deacon @ 2016-12-06 11:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480405463-23165-2-git-send-email-andy.gross@linaro.org>
Hi Andy,
On Tue, Nov 29, 2016 at 01:44:22AM -0600, Andy Gross wrote:
> This patch adds a quirk parameter to the arm_smccc_smc call. The quirk
> structure allows for specialized SMC operations due to SoC specific
> requirements.
>
> This patch also fixes up all the current users of the arm_smccc_smc API.
>
> This patch and partial implementation was suggested by Will Deacon.
>
> Signed-off-by: Andy Gross <andy.gross@linaro.org>
> ---
> arch/arm/kernel/smccc-call.S | 3 ++-
> arch/arm/mach-artpec/board-artpec6.c | 2 +-
> arch/arm64/kernel/asm-offsets.c | 7 +++++--
> arch/arm64/kernel/smccc-call.S | 3 ++-
> drivers/clk/rockchip/clk-ddr.c | 6 +++---
> drivers/devfreq/rk3399_dmc.c | 6 +++---
> drivers/firmware/meson/meson_sm.c | 2 +-
> drivers/firmware/psci.c | 2 +-
> drivers/firmware/qcom_scm-64.c | 4 ++--
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 +-
> include/linux/arm-smccc.h | 18 ++++++++++++++++--
> 11 files changed, 37 insertions(+), 18 deletions(-)
Thanks for respinning this; I'd forgotten about it!
> diff --git a/arch/arm/kernel/smccc-call.S b/arch/arm/kernel/smccc-call.S
> index 37669e7..e77950a 100644
> --- a/arch/arm/kernel/smccc-call.S
> +++ b/arch/arm/kernel/smccc-call.S
> @@ -47,7 +47,8 @@ UNWIND( .fnend)
> /*
> * void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
> * unsigned long a3, unsigned long a4, unsigned long a5,
> - * unsigned long a6, unsigned long a7, struct arm_smccc_res *res)
> + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
> + * struct arm_smccc_quirk *quirk)
I'd not thought of doing it like this -- I envisaged embedding the quirk
structure into arm_smccc_res, but this works too. I wonder if we could avoid
having to pass NULL everywhere if we renamed arm_smccc_{hvc.smc} and added
a default wrapper around them?
For example, rename arm_smccc_smc to __arm_smccc_smc, add a macro called
arm_smccc_smc that passes a NULL argument for the quirk, then finally add
a macro arm_smccc_smc_quirk that takes the additional parameter?
Will
^ permalink raw reply
* [PATCH v3 1/3] ARM: da850: fix infinite loop in clk_set_rate()
From: Bartosz Golaszewski @ 2016-12-06 11:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <689efaa1-d8d9-6937-5880-3ed7a1401268@ti.com>
2016-12-05 11:15 GMT+01:00 Sekhar Nori <nsekhar@ti.com>:
> On Monday 05 December 2016 03:39 PM, Bartosz Golaszewski wrote:
>> The aemif clock is added twice to the lookup table in da850.c. This
>> breaks the children list of pll0_sysclk3 as we're using the same list
>> links in struct clk. When calling clk_set_rate(), we get stuck in
>> propagate_rate().
>>
>> Create a separate clock for nand, inheriting the rate of the aemif
>> clock and retrieve it in the davinci_nand module.
>>
>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> ---
>> arch/arm/mach-davinci/da850.c | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
>> index e770c97..c008e5e 100644
>> --- a/arch/arm/mach-davinci/da850.c
>> +++ b/arch/arm/mach-davinci/da850.c
>> @@ -367,6 +367,11 @@ static struct clk aemif_clk = {
>> .flags = ALWAYS_ENABLED,
>> };
>>
>> +static struct clk aemif_nand_clk = {
>> + .name = "nand",
>> + .parent = &aemif_clk,
>> +};
>> +
>> static struct clk usb11_clk = {
>> .name = "usb11",
>> .parent = &pll0_sysclk4,
>> @@ -537,7 +542,7 @@ static struct clk_lookup da850_clks[] = {
>> CLK("da830-mmc.0", NULL, &mmcsd0_clk),
>> CLK("da830-mmc.1", NULL, &mmcsd1_clk),
>> CLK("ti-aemif", NULL, &aemif_clk),
>> - CLK(NULL, "aemif", &aemif_clk),
>> + CLK(NULL, "aemif", &aemif_nand_clk),
>
> Why use a NULL device name here?
Hi Sekhar,
there's an issue with this bit. I added an of_dev_auxdata entry to
da8xx-dt.c for the nand node, but it didn't work (the nand driver
could not get the clock). When I dug deeper, it turned out, the nand
node is created from aemif_probe() instead of from
da850_init_machine() and the lookup table is not passed as argument to
of_platform_populate().
There are two solutions: one is using "620000000.nand" as dev_id in
the clock lookup table, but that's ugly. The second is leaving dev_id
as NULL - I verified that the nand driver works correctly having only
the connector id. Please let me know which one you prefer or if you
have other ideas.
Best regards,
Bartosz Golaszewski
^ permalink raw reply
* [PATCH] arm: MAINTAINERS: transfer maintainership for the EZX platform
From: Robert Jarzmik @ 2016-12-06 12:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480802397-25575-1-git-send-email-stefan@datenfreihafen.org>
Stefan Schmidt <stefan@datenfreihafen.org> writes:
> Neither Daniel, Harald or myself are looking into this anymore.
> Robert thankfully agreed to handle the maintenance from now on.
> Also remove the outdated entries for website, git tree and
> mailing list.
>
> Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
Daniel and Harald, could we have your acks please for [1] ?
Cheers.
--
Robert
[1] Stefan's patch
---8>---
Neither Daniel, Harald or myself are looking into this anymore.
Robert thankfully agreed to handle the maintenance from now on.
Also remove the outdated entries for website, git tree and
mailing list.
Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
---
MAINTAINERS | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2dd40c5..661af76 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1203,13 +1203,9 @@ S: Maintained
N: efm32
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
-M: Daniel Ribeiro <drwyrm@gmail.com>
-M: Stefan Schmidt <stefan@openezx.org>
-M: Harald Welte <laforge@openezx.org>
-L: openezx-devel at lists.openezx.org (moderated for non-subscribers)
-W: http://www.openezx.org/
+M: Robert Jarzmik <robert.jarzmik@free.fr>
+L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
-T: topgit git://git.openezx.org/openezx.git
F: arch/arm/mach-pxa/ezx.c
^ permalink raw reply related
* [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly
From: Christoffer Dall @ 2016-12-06 12:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <49451f06-10a6-4921-eae6-c37a5510197a@arm.com>
On Tue, Dec 06, 2016 at 11:17:40AM +0000, Marc Zyngier wrote:
> On 01/12/16 19:32, Jintack Lim wrote:
> > Current KVM world switch code is unintentionally setting wrong bits to
> > CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
> > timer. Bit positions of CNTHCTL_EL2 are changing depending on
> > HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
> > not set, but they are 11th and 10th bits respectively when E2H is set.
> >
> > In fact, on VHE we only need to set those bits once, not for every world
> > switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
> > 1, which makes those bits have no effect for the host kernel execution.
> > So we just set those bits once for guests, and that's it.
> >
> > Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
> > ---
> > v2->v3:
> > - Perform the initialization including CPU hotplug case.
> > - Move has_vhe() to asm/virt.h
> >
> > v1->v2:
> > - Skip configuring cnthctl_el2 in world switch path on VHE system.
> > - Write patch based on linux-next.
> > ---
> > arch/arm/include/asm/virt.h | 5 +++++
> > arch/arm/kvm/arm.c | 3 +++
> > arch/arm64/include/asm/virt.h | 10 ++++++++++
> > include/kvm/arm_arch_timer.h | 1 +
> > virt/kvm/arm/arch_timer.c | 23 +++++++++++++++++++++++
> > virt/kvm/arm/hyp/timer-sr.c | 33 +++++++++++++++++++++------------
> > 6 files changed, 63 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
> > index a2e75b8..6dae195 100644
> > --- a/arch/arm/include/asm/virt.h
> > +++ b/arch/arm/include/asm/virt.h
> > @@ -80,6 +80,11 @@ static inline bool is_kernel_in_hyp_mode(void)
> > return false;
> > }
> >
> > +static inline bool has_vhe(void)
> > +{
> > + return false;
> > +}
> > +
> > /* The section containing the hypervisor idmap text */
> > extern char __hyp_idmap_text_start[];
> > extern char __hyp_idmap_text_end[];
> > diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> > index 8f92efa..13e54e8 100644
> > --- a/arch/arm/kvm/arm.c
> > +++ b/arch/arm/kvm/arm.c
> > @@ -1099,6 +1099,9 @@ static void cpu_init_hyp_mode(void *dummy)
> > __cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
> > __cpu_init_stage2();
> >
> > + if (is_kernel_in_hyp_mode())
> > + kvm_timer_init_vhe();
> > +
> > kvm_arm_init_debug();
> > }
> >
> > diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
> > index fea1073..b043cfd 100644
> > --- a/arch/arm64/include/asm/virt.h
> > +++ b/arch/arm64/include/asm/virt.h
> > @@ -47,6 +47,7 @@
> > #include <asm/ptrace.h>
> > #include <asm/sections.h>
> > #include <asm/sysreg.h>
> > +#include <asm/cpufeature.h>
> >
> > /*
> > * __boot_cpu_mode records what mode CPUs were booted in.
> > @@ -80,6 +81,15 @@ static inline bool is_kernel_in_hyp_mode(void)
> > return read_sysreg(CurrentEL) == CurrentEL_EL2;
> > }
> >
> > +static inline bool has_vhe(void)
> > +{
> > +#ifdef CONFIG_ARM64_VHE
>
> Is there a particular reason why this should be guarded by a #ifdef? All
> the symbols should always be available, and since this is a static key,
> the overhead should be really insignificant (provided that you use a
> non-prehistoric compiler...).
>
Isn't this code called from a file shared between 32-bit arm and arm64?
Does the cpus_have_const_cap work on ARM64?
-Christoffer
^ permalink raw reply
* [PATCH] trace: extend trace_clock to support arch_arm clock counter
From: Will Deacon @ 2016-12-06 12:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5843D587.5010407@codeaurora.org>
On Sun, Dec 04, 2016 at 02:06:23PM +0530, Srinivas Ramana wrote:
> On 12/02/2016 04:38 PM, Will Deacon wrote:
> >On Fri, Dec 02, 2016 at 01:44:55PM +0530, Srinivas Ramana wrote:
> >>Extend the trace_clock to support the arch timer cycle
> >>counter so that we can get the monotonic cycle count
> >>in the traces. This will help in correlating the traces with the
> >>timestamps/events in other subsystems in the soc which share
> >>this common counter for driving their timers.
> >
> >I'm not sure I follow this reasoning. What's wrong with nanoseconds? In
> >particular, the "perf" trace_clock hangs off sched_clock, which should
> >be backed by the architected counter anyway. What does the cycle counter in
> >isolation tell you, given that the frequency isn't architected?
> >
> >I think I'm missing something here.
> >
>
> Having cycle counter would help in the cases where we want to correlate the
> time with other subsystems which are outside cpu subsystem.
Do you have an example of these subsystems? Can they be used to generate
trace data with mainline?
> local_clock or even the perf track_clock uses sched_clock which gets
> suspended during system suspend. Yes, they are backed up by the
> architected counter but they ignore the cycles spent in suspend.i
Does mono_raw solve this (also hangs off the architected counter and is
supported in the vdso)?
> so, when comparing with monotonically increasing cycle counter, other
> clocks doesn't help. It seems X86 uses the TSC counter to help such cases.
Does this mean we need a way to expose the frequency to userspace, too?
Will
^ permalink raw reply
* [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly
From: Christoffer Dall @ 2016-12-06 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206121221.GA3681@cbox>
On Tue, Dec 06, 2016 at 01:12:21PM +0100, Christoffer Dall wrote:
> On Tue, Dec 06, 2016 at 11:17:40AM +0000, Marc Zyngier wrote:
> > On 01/12/16 19:32, Jintack Lim wrote:
> > > Current KVM world switch code is unintentionally setting wrong bits to
> > > CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
> > > timer. Bit positions of CNTHCTL_EL2 are changing depending on
> > > HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
> > > not set, but they are 11th and 10th bits respectively when E2H is set.
> > >
> > > In fact, on VHE we only need to set those bits once, not for every world
> > > switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
> > > 1, which makes those bits have no effect for the host kernel execution.
> > > So we just set those bits once for guests, and that's it.
> > >
> > > Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
> > > ---
> > > v2->v3:
> > > - Perform the initialization including CPU hotplug case.
> > > - Move has_vhe() to asm/virt.h
> > >
> > > v1->v2:
> > > - Skip configuring cnthctl_el2 in world switch path on VHE system.
> > > - Write patch based on linux-next.
> > > ---
> > > arch/arm/include/asm/virt.h | 5 +++++
> > > arch/arm/kvm/arm.c | 3 +++
> > > arch/arm64/include/asm/virt.h | 10 ++++++++++
> > > include/kvm/arm_arch_timer.h | 1 +
> > > virt/kvm/arm/arch_timer.c | 23 +++++++++++++++++++++++
> > > virt/kvm/arm/hyp/timer-sr.c | 33 +++++++++++++++++++++------------
> > > 6 files changed, 63 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
> > > index a2e75b8..6dae195 100644
> > > --- a/arch/arm/include/asm/virt.h
> > > +++ b/arch/arm/include/asm/virt.h
> > > @@ -80,6 +80,11 @@ static inline bool is_kernel_in_hyp_mode(void)
> > > return false;
> > > }
> > >
> > > +static inline bool has_vhe(void)
> > > +{
> > > + return false;
> > > +}
> > > +
> > > /* The section containing the hypervisor idmap text */
> > > extern char __hyp_idmap_text_start[];
> > > extern char __hyp_idmap_text_end[];
> > > diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> > > index 8f92efa..13e54e8 100644
> > > --- a/arch/arm/kvm/arm.c
> > > +++ b/arch/arm/kvm/arm.c
> > > @@ -1099,6 +1099,9 @@ static void cpu_init_hyp_mode(void *dummy)
> > > __cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
> > > __cpu_init_stage2();
> > >
> > > + if (is_kernel_in_hyp_mode())
> > > + kvm_timer_init_vhe();
> > > +
> > > kvm_arm_init_debug();
> > > }
> > >
> > > diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
> > > index fea1073..b043cfd 100644
> > > --- a/arch/arm64/include/asm/virt.h
> > > +++ b/arch/arm64/include/asm/virt.h
> > > @@ -47,6 +47,7 @@
> > > #include <asm/ptrace.h>
> > > #include <asm/sections.h>
> > > #include <asm/sysreg.h>
> > > +#include <asm/cpufeature.h>
> > >
> > > /*
> > > * __boot_cpu_mode records what mode CPUs were booted in.
> > > @@ -80,6 +81,15 @@ static inline bool is_kernel_in_hyp_mode(void)
> > > return read_sysreg(CurrentEL) == CurrentEL_EL2;
> > > }
> > >
> > > +static inline bool has_vhe(void)
> > > +{
> > > +#ifdef CONFIG_ARM64_VHE
> >
> > Is there a particular reason why this should be guarded by a #ifdef? All
> > the symbols should always be available, and since this is a static key,
> > the overhead should be really insignificant (provided that you use a
> > non-prehistoric compiler...).
> >
>
> Isn't this code called from a file shared between 32-bit arm and arm64?
> Does the cpus_have_const_cap work on ARM64?
Duh, I meant on 32-bit arm of course.
-Christoffer
^ permalink raw reply
* [PATCH v2 0/3] ARM: dts: imx6: Support Poslab Savageboard dual & quad
From: Fabio Estevam @ 2016-12-06 12:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f4e2d926-3f91-c751-67f3-b495dc0f0ba4@gmail.com>
On Tue, Dec 6, 2016 at 8:25 AM, Milo Kim <woogyom.kim@gmail.com> wrote:
>
> Oh, I didn't notice because I build the dtbs manually.
> Thanks for catching this.
>
> And do you think other patches look OK?
Yes, they look good for me.
^ permalink raw reply
* [PATCH v3] arm: dts: zynq: Add MicroZed board support
From: Michal Simek @ 2016-12-06 12:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD6G_RQuJTaXsuHLCGBZMekaGXOc7pzdi7pkoZ0gNq2LWU9ptA@mail.gmail.com>
On 5.12.2016 17:28, Jagan Teki wrote:
> On Mon, Sep 26, 2016 at 8:22 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> On 23.9.2016 11:48, Jagan Teki wrote:
>>> From: Jagan Teki <jteki@openedev.com>
>>>
>>> Added basic dts support for MicroZed board.
>>>
>>> - UART
>>> - SDHCI
>>> - Ethernet
>>>
>>> Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
>>> Cc: Michal Simek <michal.simek@xilinx.com>
>>> Signed-off-by: Jagan Teki <jteki@openedev.com>
>>> ---
>>> Changes for v3:
>>> - Add Xilinx copyright
>>> Changes for v2:
>>> - Add SDHCI
>>> - Add Ethernet
>>>
>>> arch/arm/boot/dts/Makefile | 1 +
>>> arch/arm/boot/dts/zynq-microzed.dts | 96 +++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 97 insertions(+)
>>> create mode 100644 arch/arm/boot/dts/zynq-microzed.dts
>>>
>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>> index faacd52..4d7b858 100644
>>> --- a/arch/arm/boot/dts/Makefile
>>> +++ b/arch/arm/boot/dts/Makefile
>>> @@ -862,6 +862,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
>>> wm8750-apc8750.dtb \
>>> wm8850-w70v2.dtb
>>> dtb-$(CONFIG_ARCH_ZYNQ) += \
>>> + zynq-microzed.dtb \
>>> zynq-parallella.dtb \
>>> zynq-zc702.dtb \
>>> zynq-zc706.dtb \
>>> diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts
>>> new file mode 100644
>>> index 0000000..b9376a4
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/zynq-microzed.dts
>>> @@ -0,0 +1,96 @@
>>> +/*
>>> + * Copyright (C) 2011 - 2014 Xilinx
>>> + * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
>>> + *
>>> + * This software is licensed under the terms of the GNU General Public
>>> + * License version 2, as published by the Free Software Foundation, and
>>> + * may be copied, distributed, and modified under those terms.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + */
>>> +/dts-v1/;
>>> +/include/ "zynq-7000.dtsi"
>>> +
>>> +/ {
>>> + model = "Zynq MicroZED Development Board";
>>> + compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
>>> +
>>> + aliases {
>>> + ethernet0 = &gem0;
>>> + serial0 = &uart1;
>>> + };
>>> +
>>> + memory {
>>> + device_type = "memory";
>>> + reg = <0x0 0x40000000>;
>>> + };
>>> +
>>> + chosen {
>>> + bootargs = "earlycon";
>>> + stdout-path = "serial0:115200n8";
>>> + };
>>> +
>>> + usb_phy0: phy0 {
>>> + compatible = "usb-nop-xceiv";
>>> + #phy-cells = <0>;
>>> + };
>>> +};
>>> +
>>> +&clkc {
>>> + ps-clk-frequency = <33333333>;
>>> +};
>>> +
>>> +&gem0 {
>>> + status = "okay";
>>> + phy-mode = "rgmii-id";
>>> + phy-handle = <ðernet_phy>;
>>> +
>>> + ethernet_phy: ethernet-phy at 0 {
>>> + reg = <0>;
>>> + };
>>> +};
>>> +
>>> +&sdhci0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart1 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&usb0 {
>>> + status = "okay";
>>> + dr_mode = "host";
>>> + usb-phy = <&usb_phy0>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_usb0_default>;
>>> +};
>>> +
>>> +&pinctrl0 {
>>> + pinctrl_usb0_default: usb0-default {
>>> + mux {
>>> + groups = "usb0_0_grp";
>>> + function = "usb0";
>>> + };
>>> +
>>> + conf {
>>> + groups = "usb0_0_grp";
>>> + slew-rate = <0>;
>>> + io-standard = <1>;
>>> + };
>>> +
>>> + conf-rx {
>>> + pins = "MIO29", "MIO31", "MIO36";
>>> + bias-high-impedance;
>>> + };
>>> +
>>> + conf-tx {
>>> + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
>>> + "MIO35", "MIO37", "MIO38", "MIO39";
>>> + bias-disable;
>>> + };
>>> + };
>>> +};
>>>
>>
>> Applied.
>
> Was it missed? I couldn't see it on the source for a while. any help?
Thanks for reminder. I have that patch in one branch (was in different)
https://github.com/Xilinx/linux-xlnx/commits/zynq/dt
Thanks,
Michal
^ permalink raw reply
* [PATCH v3 1/3] ARM: da850: fix infinite loop in clk_set_rate()
From: Sekhar Nori @ 2016-12-06 12:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMpxmJUCE86Y030jpLVD7=S6UThmRB2p-xS-oD3swnUSvMWe2w@mail.gmail.com>
On Tuesday 06 December 2016 05:28 PM, Bartosz Golaszewski wrote:
> 2016-12-05 11:15 GMT+01:00 Sekhar Nori <nsekhar@ti.com>:
>> On Monday 05 December 2016 03:39 PM, Bartosz Golaszewski wrote:
>>> The aemif clock is added twice to the lookup table in da850.c. This
>>> breaks the children list of pll0_sysclk3 as we're using the same list
>>> links in struct clk. When calling clk_set_rate(), we get stuck in
>>> propagate_rate().
>>>
>>> Create a separate clock for nand, inheriting the rate of the aemif
>>> clock and retrieve it in the davinci_nand module.
>>>
>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>> ---
>>> arch/arm/mach-davinci/da850.c | 7 ++++++-
>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
>>> index e770c97..c008e5e 100644
>>> --- a/arch/arm/mach-davinci/da850.c
>>> +++ b/arch/arm/mach-davinci/da850.c
>>> @@ -367,6 +367,11 @@ static struct clk aemif_clk = {
>>> .flags = ALWAYS_ENABLED,
>>> };
>>>
>>> +static struct clk aemif_nand_clk = {
>>> + .name = "nand",
>>> + .parent = &aemif_clk,
>>> +};
>>> +
>>> static struct clk usb11_clk = {
>>> .name = "usb11",
>>> .parent = &pll0_sysclk4,
>>> @@ -537,7 +542,7 @@ static struct clk_lookup da850_clks[] = {
>>> CLK("da830-mmc.0", NULL, &mmcsd0_clk),
>>> CLK("da830-mmc.1", NULL, &mmcsd1_clk),
>>> CLK("ti-aemif", NULL, &aemif_clk),
>>> - CLK(NULL, "aemif", &aemif_clk),
>>> + CLK(NULL, "aemif", &aemif_nand_clk),
>>
>> Why use a NULL device name here?
>
> Hi Sekhar,
>
> there's an issue with this bit. I added an of_dev_auxdata entry to
> da8xx-dt.c for the nand node, but it didn't work (the nand driver
> could not get the clock). When I dug deeper, it turned out, the nand
> node is created from aemif_probe() instead of from
> da850_init_machine() and the lookup table is not passed as argument to
> of_platform_populate().
>
> There are two solutions: one is using "620000000.nand" as dev_id in
> the clock lookup table, but that's ugly. The second is leaving dev_id
> as NULL - I verified that the nand driver works correctly having only
> the connector id. Please let me know which one you prefer or if you
> have other ideas.
Alright, I will take a look at whats going on here. This series will
have to wait for v4.11 anyway.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] arm64: Add CMDLINE_EXTEND
From: Will Deacon @ 2016-12-06 12:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b958f2b6-73fd-e4f5-4fa5-6d2f8330da8f@infradead.org>
On Mon, Dec 05, 2016 at 09:41:06AM -0800, Geoff Levand wrote:
> On 12/05/2016 04:08 AM, Catalin Marinas wrote:
> > On Fri, Dec 02, 2016 at 02:17:02PM -0800, Geoff Levand wrote:
> >> The device tree code already supports CMDLINE_EXTEND,
> >> so add the config option to make it available on arm64.
> >
> > What's your use-case for this patch? Note that both CMDLINE_FORCE and
> > CMDLINE_EXTEND (if we introduce it) are ignored by the EFI stub.
> > However, we don't seem to have stated this anywhere.
>
> I use this in CoreOS, where we need to set "acpi=force" for
> arm64. CoreOS uses a proper UEFI + grub.
So why can't you just set that in grub if you want to boot with ACPI?
Will
^ permalink raw reply
* [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly
From: Christoffer Dall @ 2016-12-06 12:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480620725-9864-1-git-send-email-jintack@cs.columbia.edu>
On Thu, Dec 01, 2016 at 02:32:05PM -0500, Jintack Lim wrote:
> Current KVM world switch code is unintentionally setting wrong bits to
> CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
> timer. Bit positions of CNTHCTL_EL2 are changing depending on
> HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
> not set, but they are 11th and 10th bits respectively when E2H is set.
>
> In fact, on VHE we only need to set those bits once, not for every world
> switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
> 1, which makes those bits have no effect for the host kernel execution.
> So we just set those bits once for guests, and that's it.
>
> Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
> ---
> v2->v3:
> - Perform the initialization including CPU hotplug case.
> - Move has_vhe() to asm/virt.h
>
> v1->v2:
> - Skip configuring cnthctl_el2 in world switch path on VHE system.
> - Write patch based on linux-next.
> ---
> arch/arm/include/asm/virt.h | 5 +++++
> arch/arm/kvm/arm.c | 3 +++
> arch/arm64/include/asm/virt.h | 10 ++++++++++
> include/kvm/arm_arch_timer.h | 1 +
> virt/kvm/arm/arch_timer.c | 23 +++++++++++++++++++++++
> virt/kvm/arm/hyp/timer-sr.c | 33 +++++++++++++++++++++------------
> 6 files changed, 63 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
> index a2e75b8..6dae195 100644
> --- a/arch/arm/include/asm/virt.h
> +++ b/arch/arm/include/asm/virt.h
> @@ -80,6 +80,11 @@ static inline bool is_kernel_in_hyp_mode(void)
> return false;
> }
>
> +static inline bool has_vhe(void)
> +{
> + return false;
> +}
> +
> /* The section containing the hypervisor idmap text */
> extern char __hyp_idmap_text_start[];
> extern char __hyp_idmap_text_end[];
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index 8f92efa..13e54e8 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -1099,6 +1099,9 @@ static void cpu_init_hyp_mode(void *dummy)
> __cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
> __cpu_init_stage2();
>
> + if (is_kernel_in_hyp_mode())
> + kvm_timer_init_vhe();
> +
> kvm_arm_init_debug();
> }
>
> diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
> index fea1073..b043cfd 100644
> --- a/arch/arm64/include/asm/virt.h
> +++ b/arch/arm64/include/asm/virt.h
> @@ -47,6 +47,7 @@
> #include <asm/ptrace.h>
> #include <asm/sections.h>
> #include <asm/sysreg.h>
> +#include <asm/cpufeature.h>
>
> /*
> * __boot_cpu_mode records what mode CPUs were booted in.
> @@ -80,6 +81,15 @@ static inline bool is_kernel_in_hyp_mode(void)
> return read_sysreg(CurrentEL) == CurrentEL_EL2;
> }
>
> +static inline bool has_vhe(void)
> +{
> +#ifdef CONFIG_ARM64_VHE
> + if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))
> + return true;
> +#endif
> + return false;
> +}
> +
> #ifdef CONFIG_ARM64_VHE
> extern void verify_cpu_run_el(void);
> #else
> diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
> index dda39d8..2d54903 100644
> --- a/include/kvm/arm_arch_timer.h
> +++ b/include/kvm/arm_arch_timer.h
> @@ -76,4 +76,5 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
>
> void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
>
> +void kvm_timer_init_vhe(void);
> #endif
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index 17b8fa5..c7c3bfd 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -24,6 +24,7 @@
>
> #include <clocksource/arm_arch_timer.h>
> #include <asm/arch_timer.h>
> +#include <asm/kvm_hyp.h>
>
> #include <kvm/arm_vgic.h>
> #include <kvm/arm_arch_timer.h>
> @@ -507,3 +508,25 @@ void kvm_timer_init(struct kvm *kvm)
> {
> kvm->arch.timer.cntvoff = kvm_phys_timer_read();
> }
> +
> +/*
> + * On VHE system, we only need to configure trap on physical timer and counter
> + * accesses in EL0 and EL1 once, not for every world switch.
> + * The host kernel runs at EL2 with HCR_EL2.TGE == 1,
> + * and this makes those bits have no effect for the host kernel execution.
> + */
> +void kvm_timer_init_vhe(void)
> +{
> + /* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */
> + u32 cnthctl_shift = 10;
> + u64 val;
> +
> + /*
> + * Disallow physical timer access for the guest.
> + * Physical counter access is allowed.
> + */
> + val = read_sysreg(cnthctl_el2);
> + val &= ~(CNTHCTL_EL1PCEN << cnthctl_shift);
> + val |= (CNTHCTL_EL1PCTEN << cnthctl_shift);
> + write_sysreg(val, cnthctl_el2);
> +}
> diff --git a/virt/kvm/arm/hyp/timer-sr.c b/virt/kvm/arm/hyp/timer-sr.c
> index 798866a..63e28dd 100644
> --- a/virt/kvm/arm/hyp/timer-sr.c
> +++ b/virt/kvm/arm/hyp/timer-sr.c
> @@ -35,10 +35,16 @@ void __hyp_text __timer_save_state(struct kvm_vcpu *vcpu)
> /* Disable the virtual timer */
> write_sysreg_el0(0, cntv_ctl);
>
> - /* Allow physical timer/counter access for the host */
> - val = read_sysreg(cnthctl_el2);
> - val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
> - write_sysreg(val, cnthctl_el2);
> + /*
> + * We don't need to do this for VHE since the host kernel runs in EL2
> + * with HCR_EL2.TGE ==1, which makes those bits have no impact.
> + */
> + if (!has_vhe()) {
> + /* Allow physical timer/counter access for the host */
> + val = read_sysreg(cnthctl_el2);
> + val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
> + write_sysreg(val, cnthctl_el2);
> + }
>
> /* Clear cntvoff for the host */
> write_sysreg(0, cntvoff_el2);
> @@ -50,14 +56,17 @@ void __hyp_text __timer_restore_state(struct kvm_vcpu *vcpu)
> struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
> u64 val;
>
> - /*
> - * Disallow physical timer access for the guest
> - * Physical counter access is allowed
> - */
> - val = read_sysreg(cnthctl_el2);
> - val &= ~CNTHCTL_EL1PCEN;
> - val |= CNTHCTL_EL1PCTEN;
> - write_sysreg(val, cnthctl_el2);
> + /* Those bits are already configured at boot on VHE-system */
> + if (!has_vhe()) {
> + /*
> + * Disallow physical timer access for the guest
> + * Physical counter access is allowed
> + */
> + val = read_sysreg(cnthctl_el2);
> + val &= ~CNTHCTL_EL1PCEN;
> + val |= CNTHCTL_EL1PCTEN;
> + write_sysreg(val, cnthctl_el2);
> + }
>
> if (timer->enabled) {
> write_sysreg(kvm->arch.timer.cntvoff, cntvoff_el2);
> --
> 1.9.1
>
>
The discussion around CONFIG_ARM64_VHE notwithstanding:
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
^ permalink raw reply
* [STLinux Kernel] [PATCH 2/3] serial: st-asc: Provide RTS functionality
From: Peter Griffin @ 2016-12-06 12:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5e652529-8dcb-568e-a748-0ec745099211@st.com>
Hi Lee,
On Mon, 05 Dec 2016, Patrice Chotard wrote:
> Hi Lee
>
> On 12/02/2016 03:11 PM, Lee Jones wrote:
> > Until this point, it has not been possible for serial applications
> > to toggle the UART RTS line. This can be useful with certain
> > configurations. For example, when using a Mezzanine on a Linaro
> > 96board, RTS line is used to take the the on-board microcontroller
>
> typo "the the on"
>
> > in and out of reset.
> >
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > drivers/tty/serial/st-asc.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/tty/serial/st-asc.c b/drivers/tty/serial/st-asc.c
> > index 379e5bd..ce46898 100644
> > --- a/drivers/tty/serial/st-asc.c
> > +++ b/drivers/tty/serial/st-asc.c
> > @@ -30,6 +30,7 @@
> > #include <linux/of_platform.h>
> > #include <linux/serial_core.h>
> > #include <linux/clk.h>
> > +#include <linux/gpio/consumer.h>
> >
> > #define DRIVER_NAME "st-asc"
> > #define ASC_SERIAL_NAME "ttyAS"
> > @@ -38,6 +39,7 @@
> >
> > struct asc_port {
> > struct uart_port port;
> > + struct gpio_desc *rts;
> > struct clk *clk;
> > unsigned int hw_flow_control:1;
> > unsigned int force_m1:1;
> > @@ -381,12 +383,16 @@ static unsigned int asc_tx_empty(struct uart_port *port)
> >
> > static void asc_set_mctrl(struct uart_port *port, unsigned int mctrl)
> > {
> > + struct asc_port *ascport = to_asc_port(port);
> > +
> > /*
> > * This routine is used for seting signals of: DTR, DCD, CTS/RTS
> > * We use ASC's hardware for CTS/RTS, so don't need any for that.
> > * Some boards have DTR and DCD implemented using PIO pins,
> > * code to do this should be hooked in here.
> > */
> > +
> > + gpiod_set_value(ascport->rts, mctrl & TIOCM_RTS);
This now puts the code and the comment above out of sync with each
other.
However just checking the stih410 datasheet and I don't think this patch
to control RTS via a GPIO is required anyway.
The correct way of handling this is to add UART10_RTS and UART10_CTS pins
to the pinctrl_serial0 group so they are properly configured for their cts/rts
alternate function. Once the pins are correctly configured, the IP block should
control the signals correctly like the comment says.
regards,
Peter.
^ permalink raw reply
* How do I define SRAM chip in GPMC device tree ?
From: Mark Jackson @ 2016-12-06 12:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi
We have an existing board supported in Linux v4.1 (see am335x-nano.dts)
and I was looking to update to a more recent kernel but have hit a stumbling
block.
Our unit has an SRAM device connected to CS1 and we currently rely on uboot
to init the GPMC settings.
>From v4.2+ I now see that the GPMC code has been changed to reset all the
GPMC settings when the kernel starts, so our SRAM is now inaccessible.
I've tried the following to add an extra device to the GPMC, but no go:-
sram at 1,0 {
reg = <1 0x00000000 0x01000000>;
/*compatible = "mmio-sram";*/
bank-width = <2>;
gpmc,mux-add-data = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <160>;
gpmc,cs-wr-off-ns = <160>;
gpmc,adv-on-ns = <10>;
gpmc,adv-rd-off-ns = <30>;
gpmc,adv-wr-off-ns = <30>;
gpmc,oe-on-ns = <40>;
gpmc,oe-off-ns = <160>;
gpmc,we-on-ns = <40>;
gpmc,we-off-ns = <160>;
gpmc,rd-cycle-ns = <160>;
gpmc,wr-cycle-ns = <160>;
gpmc,access-ns = <150>;
gpmc,page-burst-access-ns = <10>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-delay-ns = <20>;
gpmc,wr-data-mux-bus-ns = <70>;
gpmc,wr-access-ns = <80>;
};
Looking at drivers/memory/omap-gpmc.c, I can see that when the GPMC
children are scanned, only the following are matched:-
"nand","onenand","ethernet","nor","uart"
So can anyone explain how to add a standard SRAM chip ?
Cheers
Mark J.
^ permalink raw reply
* [RFC PATCH 00/23] arm: defconfigs: use kconfig fragments
From: Bartlomiej Zolnierkiewicz @ 2016-12-06 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This RFC patchset starts convertion of ARM defconfigs to use kconfig
fragments and dynamically generate defconfigs. The goals of this
work are to:
- remove duplication between defconfigs
- add a possibility to generate board/SoC/SoC-family/Multi specific
defconfigs in the future (without duplicating defconfigs)
This patchset is only a start of the work for discussion purposes
(I'm not entirely satisfied with the resulting patches):
- the major disadvantage of using kconfig fragments is that it is
now more difficult to update defconfigs
- split on hardware and system specific defconfig fragments is not
obvious and requires more thought
Patches description:
- patch 01 adds defconfigs dynamic generation support (based on
PowerPC code)
- patches 02-21 remove duplication between selected defconfigs
(without splitting them on hardware and system specific parts)
- patches 22-23 start a conversion of multi_v7_defconfig to be
dynamically generated and remove duplication between Multi
defconfig and SoC-family specific defconfigs (only Exynos and
Tegra defconfigs are converted for RFC purposes, defconfigs
are splitted on hardware and system specific parts)
The patchset is against v4.9-rc6 kernel.
FIXMEs:
- add sys_m and sys_m_shared kconfig fragments
- audit hardware/system split
- convert all defconfigs touched by patchset to use:
* hw_y, hw_y_shared, hw_m, hw_m_shared
* sys_y, sys_y_shared, sys_m, sys_m_shared
kconfig fragments
- convert remaining defconfigs
Bartlomiej Zolnierkiewicz (23):
arm: add kconfig fragments support
arm: use kconfig fragments for ARCH_ASPEED defconfigs
arm: update defconfigs for ARCH_KS8695
arm: use kconfig fragments for ARCH_ASPEED defconfigs
arm: update defconfigs for ARCH_MMP
arm: use kconfig fragments for ARCH_ASPEED defconfigs
arm: update defconfigs for PLAT_SPEAR
arm: use kconfig fragments for PLAT_SPEAR defconfigs
arm: update defconfigs for ARCH_W90X900
arm: use kconfig fragments for ARCH_W90X900 defconfigs
arm: update mainstone_defconfig
arm: update lubbock_defconfig
arm: update pxa255-idp_defconfig
arm: update lpd270_defconfig
arm: use kconfig fragments for ARCH_PXA defconfigs (part 1)
arm: update corgi_defconfig
arm: update spitz_defconfig
arm: use kconfig fragments for ARCH_PXA defconfigs (part 2)
arm: update ezx_defconfig
arm: imote2_defconfig
arm: use kconfig fragments for ARCH_PXA defconfigs (part 3)
arm: use kconfig fragments for exynos_defconfig/multi_v7_defconfig
arm: use kconfig fragments for tegra_defconfig/multi_v7_defconfig
arch/arm/Makefile | 107 ++++++
arch/arm/configs/acs5k.config | 32 ++
arch/arm/configs/acs5k_defconfig | 86 -----
arch/arm/configs/acs5k_tiny.config | 24 ++
arch/arm/configs/acs5k_tiny_defconfig | 80 ----
...{aspeed_g4_defconfig => aspeed_basic_defconfig} | 1 -
arch/arm/configs/aspeed_g4.config | 1 +
arch/arm/configs/aspeed_g5.config | 3 +
arch/arm/configs/aspeed_g5_defconfig | 88 -----
arch/arm/configs/corgi.config | 11 +
arch/arm/configs/dummy_defconfig | 1 +
arch/arm/configs/exynos/hw_m.config | 2 +
arch/arm/configs/exynos/hw_m_shared.config | 18 +
arch/arm/configs/exynos/hw_y.config | 93 +++++
arch/arm/configs/exynos/hw_y_shared.config | 93 +++++
arch/arm/configs/exynos/sys_y.config | 33 ++
arch/arm/configs/exynos/sys_y_shared.config | 37 ++
arch/arm/configs/exynos_defconfig | 274 --------------
arch/arm/configs/ezx.config | 39 ++
arch/arm/configs/ezx_defconfig | 418 ---------------------
arch/arm/configs/imote2.config | 17 +
arch/arm/configs/ks8695.config | 21 ++
.../{ks8695_defconfig => ks8695_basic_defconfig} | 33 --
arch/arm/configs/lpd270.config | 20 +
arch/arm/configs/lpd270_defconfig | 64 ----
arch/arm/configs/lubbock.config | 11 +
arch/arm/configs/lubbock_defconfig | 56 ---
arch/arm/configs/mainstone.config | 11 +
arch/arm/configs/mmp2.config | 32 ++
arch/arm/configs/mmp2_defconfig | 98 -----
.../{pxa168_defconfig => mmp_basic_defconfig} | 27 +-
...{multi_v7_defconfig => multi_v7_base_defconfig} | 268 -------------
arch/arm/configs/nuc910_defconfig | 19 +-
arch/arm/configs/nuc950.config | 14 +
arch/arm/configs/nuc950_defconfig | 76 ----
arch/arm/configs/nuc960.config | 5 +
arch/arm/configs/nuc960_defconfig | 66 ----
arch/arm/configs/pxa168.config | 3 +
arch/arm/configs/pxa255-idp.config | 14 +
arch/arm/configs/pxa255-idp_defconfig | 58 ---
arch/arm/configs/pxa910.config | 8 +
arch/arm/configs/pxa910_defconfig | 80 ----
.../{mainstone_defconfig => pxa_basic1_defconfig} | 21 +-
.../{corgi_defconfig => pxa_basic2_defconfig} | 70 +---
.../{imote2_defconfig => pxa_basic3_defconfig} | 101 +----
arch/arm/configs/spear13xx.config | 35 ++
arch/arm/configs/spear13xx_defconfig | 110 ------
arch/arm/configs/spear3xx.config | 15 +
arch/arm/configs/spear3xx_defconfig | 89 -----
arch/arm/configs/spear6xx.config | 5 +
.../{spear6xx_defconfig => spear_basic_defconfig} | 13 +-
arch/arm/configs/spitz.config | 10 +
arch/arm/configs/spitz_defconfig | 273 --------------
arch/arm/configs/tegra/hw_m.config | 1 +
arch/arm/configs/tegra/hw_m_shared.config | 3 +
arch/arm/configs/tegra/hw_y.config | 48 +++
arch/arm/configs/tegra/hw_y_shared.config | 151 ++++++++
arch/arm/configs/tegra/sys_y.config | 63 ++++
arch/arm/configs/tegra/sys_y_shared.config | 40 ++
arch/arm/configs/tegra_defconfig | 305 ---------------
60 files changed, 1052 insertions(+), 2743 deletions(-)
create mode 100644 arch/arm/configs/acs5k.config
delete mode 100644 arch/arm/configs/acs5k_defconfig
create mode 100644 arch/arm/configs/acs5k_tiny.config
delete mode 100644 arch/arm/configs/acs5k_tiny_defconfig
rename arch/arm/configs/{aspeed_g4_defconfig => aspeed_basic_defconfig} (98%)
create mode 100644 arch/arm/configs/aspeed_g4.config
create mode 100644 arch/arm/configs/aspeed_g5.config
delete mode 100644 arch/arm/configs/aspeed_g5_defconfig
create mode 100644 arch/arm/configs/corgi.config
create mode 100644 arch/arm/configs/dummy_defconfig
create mode 100644 arch/arm/configs/exynos/hw_m.config
create mode 100644 arch/arm/configs/exynos/hw_m_shared.config
create mode 100644 arch/arm/configs/exynos/hw_y.config
create mode 100644 arch/arm/configs/exynos/hw_y_shared.config
create mode 100644 arch/arm/configs/exynos/sys_y.config
create mode 100644 arch/arm/configs/exynos/sys_y_shared.config
delete mode 100644 arch/arm/configs/exynos_defconfig
create mode 100644 arch/arm/configs/ezx.config
delete mode 100644 arch/arm/configs/ezx_defconfig
create mode 100644 arch/arm/configs/imote2.config
create mode 100644 arch/arm/configs/ks8695.config
rename arch/arm/configs/{ks8695_defconfig => ks8695_basic_defconfig} (56%)
create mode 100644 arch/arm/configs/lpd270.config
delete mode 100644 arch/arm/configs/lpd270_defconfig
create mode 100644 arch/arm/configs/lubbock.config
delete mode 100644 arch/arm/configs/lubbock_defconfig
create mode 100644 arch/arm/configs/mainstone.config
create mode 100644 arch/arm/configs/mmp2.config
delete mode 100644 arch/arm/configs/mmp2_defconfig
rename arch/arm/configs/{pxa168_defconfig => mmp_basic_defconfig} (61%)
rename arch/arm/configs/{multi_v7_defconfig => multi_v7_base_defconfig} (71%)
create mode 100644 arch/arm/configs/nuc950.config
delete mode 100644 arch/arm/configs/nuc950_defconfig
create mode 100644 arch/arm/configs/nuc960.config
delete mode 100644 arch/arm/configs/nuc960_defconfig
create mode 100644 arch/arm/configs/pxa168.config
create mode 100644 arch/arm/configs/pxa255-idp.config
delete mode 100644 arch/arm/configs/pxa255-idp_defconfig
create mode 100644 arch/arm/configs/pxa910.config
delete mode 100644 arch/arm/configs/pxa910_defconfig
rename arch/arm/configs/{mainstone_defconfig => pxa_basic1_defconfig} (62%)
rename arch/arm/configs/{corgi_defconfig => pxa_basic2_defconfig} (83%)
rename arch/arm/configs/{imote2_defconfig => pxa_basic3_defconfig} (75%)
create mode 100644 arch/arm/configs/spear13xx.config
delete mode 100644 arch/arm/configs/spear13xx_defconfig
create mode 100644 arch/arm/configs/spear3xx.config
delete mode 100644 arch/arm/configs/spear3xx_defconfig
create mode 100644 arch/arm/configs/spear6xx.config
rename arch/arm/configs/{spear6xx_defconfig => spear_basic_defconfig} (87%)
create mode 100644 arch/arm/configs/spitz.config
delete mode 100644 arch/arm/configs/spitz_defconfig
create mode 100644 arch/arm/configs/tegra/hw_m.config
create mode 100644 arch/arm/configs/tegra/hw_m_shared.config
create mode 100644 arch/arm/configs/tegra/hw_y.config
create mode 100644 arch/arm/configs/tegra/hw_y_shared.config
create mode 100644 arch/arm/configs/tegra/sys_y.config
create mode 100644 arch/arm/configs/tegra/sys_y_shared.config
delete mode 100644 arch/arm/configs/tegra_defconfig
--
1.9.1
^ permalink raw reply
* [RFC PATCH 01/23] arm: add kconfig fragments support
From: Bartlomiej Zolnierkiewicz @ 2016-12-06 12:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481027938-31831-1-git-send-email-b.zolnierkie@samsung.com>
Add support for generating defconfigs from kconfig fragments.
This is based on changes to arch/powerpc/Makefile from
commit ea4d1a87e6de ("powerpc/configs: Replace pseries_le_defconfig
with a Makefile target using merge_config") by Cyril Bur.
Cc: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/Makefile | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6be9ee1..f2c0683 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -343,6 +343,17 @@ dtbs: prepare scripts
dtbs_install:
$(Q)$(MAKE) $(dtbinst)=$(boot)/dts
+# Used to create 'merged defconfigs'
+# To use it $(call) it with the first argument as the base defconfig
+# and the second argument as a space separated list of .config files to merge,
+# without the .config suffix.
+define merge_into_defconfig
+ $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
+ -m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/$(1) \
+ $(foreach config,$(2),$(srctree)/arch/$(ARCH)/configs/$(config).config)
+ +$(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig
+endef
+
PHONY += vdso_install
vdso_install:
ifeq ($(CONFIG_VDSO),y)
--
1.9.1
^ permalink raw reply related
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