* [PATCH 08/12] ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Add pinctrl groups for both GPT input capture channels.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 944a4fa..d74882a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -457,6 +457,18 @@
>;
};
+ pinctrl_gpt_input_capture0: gptinputcapture0grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x80000000
+ >;
+ };
+
+ pinctrl_gpt_input_capture1: gptinputcapture1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x80000000
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
--
2.7.4
^ permalink raw reply related
* [PATCH 07/12] ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
The reset pin to the port expander chip (MAX7310) is controlled by a gpio,
so define a reset-gpios property to control it. There are three MAX7310's
on the SabreAuto CPU card (max7310_[abc]), but all use the same pin for
their reset. Since all can't acquire the same pin, assign it to max7310_b,
that chip is needed by more functions (usb and adv7180).
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 043d20c..944a4fa 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -136,6 +136,9 @@
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max7310>;
+ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
max7310_c: gpio at 34 {
@@ -442,6 +445,12 @@
>;
};
+ pinctrl_max7310: max7310grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
^ permalink raw reply related
* [PATCH 06/12] ARM: dts: imx6-sabreauto: create i2cmux for i2c3
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
The sabreauto uses a steering pin to select between the SDA signal on
i2c3 bus, and a data-in pin for an SPI NOR chip. Use i2cmux to control
this steering pin. Idle state of the i2cmux selects SPI NOR. This is not
a classic way to use i2cmux, since one side of the mux selects something
other than an i2c bus, but it works and is probably the cleanest
solution. Note that if one thread is attempting to access SPI NOR while
another thread is accessing i2c3, the SPI NOR access will fail since the
i2cmux has selected the SDA pin rather than SPI NOR data-in. This couldn't
be avoided in any case, the board is not designed to allow concurrent
i2c3 and SPI NOR functions (and the default device-tree does not enable
SPI NOR anyway).
Devices hanging off i2c3 should now be defined under i2cmux, so
that the steering pin can be properly controlled to access those
devices. The port expanders (MAX7310) are thus moved into i2cmux.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 65 +++++++++++++++++++++-----------
1 file changed, 44 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e000e6f..043d20c 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -108,6 +108,44 @@
default-brightness-level = <7>;
status = "okay";
};
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3mux>;
+ mux-gpios = <&gpio5 4 0>;
+ i2c-parent = <&i2c3>;
+ idle-state = <0>;
+
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ max7310_a: gpio at 30 {
+ compatible = "maxim,max7310";
+ reg = <0x30>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_b: gpio at 32 {
+ compatible = "maxim,max7310";
+ reg = <0x32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_c: gpio at 34 {
+ compatible = "maxim,max7310";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
};
&clks {
@@ -291,27 +329,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
-
- max7310_a: gpio at 30 {
- compatible = "maxim,max7310";
- reg = <0x30>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_b: gpio at 32 {
- compatible = "maxim,max7310";
- reg = <0x32>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_c: gpio at 34 {
- compatible = "maxim,max7310";
- reg = <0x34>;
- gpio-controller;
- #gpio-cells = <2>;
- };
};
&iomuxc {
@@ -419,6 +436,12 @@
>;
};
+ pinctrl_i2c3mux: i2c3muxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
^ permalink raw reply related
* [PATCH 05/12] ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
The OV5640 connects to the input port on the MIPI CSI-2 receiver on
mipi_csi. It is set to transmit over MIPI virtual channel 1.
Until the OV5652 sensor module compatible with the SabreSD becomes
available for testing, the ov5642 node is currently disabled.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6dl-sabresd.dts | 5 ++
arch/arm/boot/dts/imx6q-sabresd.dts | 5 ++
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 114 ++++++++++++++++++++++++++++++++-
3 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 1e45f2f..6cf7a50 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,3 +15,8 @@
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 9cbdfe7..8c1d7ad 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -23,3 +23,8 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 8e9e0d9..e36e1e7 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -10,6 +10,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -146,6 +147,33 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
+&mipi_csi {
+ status = "okay";
+};
+
+/* Incoming port from sensor */
+&mipi_csi_from_mipi_sensor {
+ remote-endpoint = <&ov5640_to_mipi_csi>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -214,7 +242,33 @@
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
- };
+ };
+
+ camera: ov5642 at 3c {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ reg = <0x3c>;
+ xclk = <24000000>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen5_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwdn-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* SD1_DAT0 */
+ reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; /* SD1_DAT1 */
+ status = "disabled";
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
};
&i2c2 {
@@ -322,6 +376,34 @@
};
};
};
+
+ mipi_camera: ov5640 at 3c {
+ compatible = "ovti,ov5640_mipi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ xclk = <24000000>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen5_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwdn-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; /* SD1_DAT2 */
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; /* SD1_CLK */
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_csi_from_mipi_sensor>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+ };
+ };
+ };
};
&i2c3 {
@@ -426,6 +508,36 @@
>;
};
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x80000000
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x80000000
+ >;
+ };
+
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
--
2.7.4
^ permalink raw reply related
* [PATCH 04/12] ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
Both hang off the same i2c2 bus, so they require different (and non-
default) i2c slave addresses.
The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
The OV5640 connects to the input port on the MIPI CSI-2 receiver on
mipi_csi. It is set to transmit over MIPI virtual channel 1.
Note there is a pin conflict with GPIO6. This pin functions as a power
input pin to the OV5642, but ENET uses it as the h/w workaround for
erratum ERR006687, to wake-up the ARM cores on normal RX and TX packet
done events (see 6261c4c8). So workaround 6261c4c8 is reverted here to
support the OV5642, and the "fsl,err006687-workaround-present" boolean
also must be removed. The result is that the CPUidle driver will no longer
allow entering the deep idle states on the sabrelite.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 ++
arch/arm/boot/dts/imx6q-sabrelite.dts | 6 ++
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 122 ++++++++++++++++++++++++++++++-
3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts
index 0f06ca5..fec2524 100644
--- a/arch/arm/boot/dts/imx6dl-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts
@@ -48,3 +48,8 @@
model = "Freescale i.MX6 DualLite SABRE Lite Board";
compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 66d10d8..9e2d26d 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -52,3 +52,9 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 81dd6cd..d7fcb1a2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -39,6 +39,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -96,6 +98,15 @@
};
};
+ mipi_xclk: mipi_xclk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ clock-output-names = "mipi_pwm3";
+ pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
+ status = "okay";
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -220,6 +231,22 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -271,9 +298,6 @@
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
- fsl,err006687-workaround-present;
status = "okay";
};
@@ -302,6 +326,52 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+
+ camera: ov5642 at 42 {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-names = "xclk";
+ reg = <0x42>;
+ xclk = <24000000>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ pwdn-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+
+ mipi_camera: ov5640 at 40 {
+ compatible = "ovti,ov5640_mipi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ clocks = <&mipi_xclk>;
+ clock-names = "xclk";
+ reg = <0x40>;
+ xclk = <22000000>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
+ pwdn-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_csi_from_mipi_sensor>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+ };
+ };
+ };
};
&i2c3 {
@@ -374,7 +444,6 @@
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@@ -449,6 +518,39 @@
>;
};
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
+ MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x80000000
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+ >;
+ };
+
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
@@ -605,3 +707,15 @@
vmmc-supply = <®_3p3v>;
status = "okay";
};
+
+&mipi_csi {
+ status = "okay";
+};
+
+/* Incoming port from sensor */
+&mipi_csi_from_mipi_sensor {
+ remote-endpoint = <&ov5640_to_mipi_csi>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
--
2.7.4
^ permalink raw reply related
* [PATCH 03/12] ARM: dts: imx6qdl: add video capture devices and connections
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
From: Philipp Zabel <p.zabel@pengutronix.de>
This patch adds the IPU subunit devices involved in video capture and
image conversion, and defines all the possible hardware connections
between them via OF graphs.
External to the IPU:
Video input multiplexers are defined that multiplex inputs from camera
sensors and the MIPI-CSI2 gasket, to the IPU CSIs.
On i.MX6Q/D two two-input multiplexers in front of IPU1 CSI0 and IPU2 CSI1
allow to select between CSI0/1 parallel input pads and the MIPI CSI-2 virtual
channels 0/3.
On i.MX6DL/S two five-input multiplexers in front of IPU1 CSI0 and IPU1 CSI1
allow to select between CSI0/1 parallel input pads and any of the four MIPI
CSI-2 virtual channels.
Internal to the IPU:
The IPU CSI, SMFC, IC-PRPENC, IC-PRPVF, and IC-PP subunits are added
as children of the IPUs, along with the hardware-supported connections
between them.
Finally, a media device node is defined. A video camera interface
and mem2mem device are defined as children of the media device.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/boot/dts/imx6dl.dtsi | 190 ++++++++++++++++
arch/arm/boot/dts/imx6q.dtsi | 487 +++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx6qdl.dtsi | 368 +++++++++++++++++++++++++++++++
3 files changed, 1045 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ade195..4bab076 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -109,6 +109,120 @@
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
};
+
+ ipu1_csi0_mux: ipu1_csi0_mux at 34 {
+ compatible = "imx-video-mux";
+ reg = <0x34 0x07>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <5>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ipu1_csi0_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu1_csi1_mux: ipu1_csi1_mux at 34 {
+ compatible = "imx-video-mux";
+ reg = <0x34 0x38>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <5>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi1_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi1_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi1_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ipu1_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ ipu1_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+
+ ipu1_csi1_mux_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
+ };
+ };
+ };
};
&gpio1 {
@@ -184,3 +298,79 @@
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};
+
+&ipu1_csi1 {
+ port at 0 {
+ reg = <0>;
+ ipu1_csi1_from_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
+ };
+ };
+};
+
+&mipi_csi {
+ sink-ports = <1>;
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_csi_from_mipi_sensor: endpoint {
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+
+ mipi_vc0_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc1_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
+ };
+
+ mipi_vc1_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc2_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
+ };
+
+ mipi_vc2_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc3_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
+ };
+
+ mipi_vc3_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 2b261ba..a0602c5 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -142,11 +142,270 @@
resets = <&src 4>;
ipu2_csi0: ipu2_csi at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_csi0_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_csi0_to_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_from_csi0>;
+ };
+ ipu2_csi0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_csi0>;
+ };
+ ipu2_csi0_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_from_csi0>;
+ };
+ };
};
ipu2_csi1: ipu2_csi at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_csi1_from_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_csi1_to_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_from_csi1>;
+ };
+ ipu2_csi1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_csi1>;
+ };
+ ipu2_csi1_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_from_csi1>;
+ };
+ };
+ };
+
+ ipu2_smfc0: ipu2_smfc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_smfc0_from_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_to_smfc0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_smfc0_to_ic_pp1: pp-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_from_smfc0>;
+ };
+ ipu2_smfc0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_smfc0>;
+ };
+ ipu2_smfc0_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_smfc0>;
+ };
+ ipu2_smfc0_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_smfc0>;
+ };
+ };
+ };
+
+ ipu2_smfc1: ipu2_smfc at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_smfc1_from_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_to_smfc1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_smfc1_to_ic_pp2: pp-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_from_smfc1>;
+ };
+ ipu2_smfc1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_smfc1>;
+ };
+ ipu2_smfc1_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_smfc1>;
+ };
+ ipu2_smfc1_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_smfc1>;
+ };
+ };
+ };
+
+ ipu2_ic_prpenc: ipu2_ic_prpenc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_prpenc_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu2_csi0_to_ic_prpenc>;
+ };
+ ipu2_ic_prpenc_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu2_csi1_to_ic_prpenc>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_prpenc_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_prpenc>;
+ };
+ ipu2_ic_prpenc_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_prpenc>;
+ };
+ };
+ };
+
+ ipu2_ic_prpvf: ipu2_ic_prpvf at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_prpvf_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu2_csi0_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu2_csi1_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_to_ic_prpvf>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_prpvf_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_from_ic_prpvf>;
+ };
+ };
+ };
+
+ ipu2_ic_pp0: ipu2_ic_pp at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_pp0_from_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_to_ic_pp0>;
+ };
+ ipu2_ic_pp0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_pp0_to_m2m1: endpoint {
+ remote-endpoint = <&m2m1_from_ic_pp0>;
+ };
+ };
+ };
+
+ ipu2_ic_pp1: ipu2_ic_pp at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_pp1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_ic_pp1>;
+ };
+ ipu2_ic_pp1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_pp1_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_pp1>;
+ };
+ ipu2_ic_pp1_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_pp1>;
+ };
+ };
+ };
+
+ ipu2_ic_pp2: ipu2_ic_pp at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <2>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_pp2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_ic_pp2>;
+ };
+ ipu2_ic_pp2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp2>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_pp2_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_pp2>;
+ };
+ ipu2_ic_pp2_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_pp2>;
+ };
+ };
};
ipu2_di0: ipu2_di at 0 {
@@ -207,6 +466,73 @@
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
};
+
+
+ ipu1_csi0_mux: ipu1_csi0_mux at 4 {
+ compatible = "imx-video-mux";
+ reg = <0x04 0x80000>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu2_csi1_mux: ipu2_csi1_mux at 4 {
+ compatible = "imx-video-mux";
+ reg = <0x04 0x100000>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu2_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu2_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu2_csi1_mux_to_ipu2_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
+ };
+ };
+ };
};
&gpio1 {
@@ -266,6 +592,15 @@
};
};
+&ipu1_csi1 {
+ port at 0 {
+ reg = <0>;
+ ipu1_csi1_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
+ };
+ };
+};
+
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -312,6 +647,49 @@
};
};
+&mipi_csi {
+ sink-ports = <1>;
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_csi_from_mipi_sensor: endpoint {
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ mipi_vc1_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ mipi_vc2_to_ipu2_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ mipi_vc3_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
+
&mipi_dsi {
ports {
port at 2 {
@@ -335,3 +713,112 @@
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
+
+&media0 {
+ m2m1: m2m at 1 {
+ compatible = "fsl,imx-media-mem2mem";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ };
+
+ port at 1 {
+ reg = <1>;
+ m2m1_from_ic_pp0: endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_to_m2m1>;
+ };
+ m2m1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_m2m1>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+ m2m1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_m2m1>;
+ };
+ m2m1_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_from_m2m1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+ };
+ };
+
+ camif2: camif at 2 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <2>;
+
+ port at 0 {
+ reg = <0>;
+ camif2_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_camif2>;
+ };
+ camif2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_camif2>;
+ };
+ camif2_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_to_camif2>;
+ };
+ camif2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_camif2>;
+ };
+ camif2_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_to_camif2>;
+ };
+ camif2_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_to_camif2>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+
+ camif3: camif at 3 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <3>;
+
+ port at 0 {
+ reg = <0>;
+ camif3_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_camif3>;
+ };
+ camif3_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_camif3>;
+ };
+ camif3_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_to_camif3>;
+ };
+ camif3_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_camif3>;
+ };
+ camif3_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_to_camif3>;
+ };
+ camif3_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_to_camif3>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 2465187..ea1e2f3 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1123,6 +1123,8 @@
mipi_csi: mipi at 021dc000 {
compatible = "fsl,imx-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 100 0x04>, <0 101 0x04>;
clocks = <&clks IMX6QDL_CLK_HSI_TX>,
<&clks IMX6QDL_CLK_VIDEO_27M>,
@@ -1227,11 +1229,263 @@
resets = <&src 2>;
ipu1_csi0: ipu1_csi at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_csi0_from_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_csi0_to_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_from_csi0>;
+ };
+ ipu1_csi0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_csi0>;
+ };
+ ipu1_csi0_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_from_csi0>;
+ };
+ };
};
ipu1_csi1: ipu1_csi at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 1 {
+ reg = <1>;
+ ipu1_csi1_to_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_from_csi1>;
+ };
+ ipu1_csi1_to_ic_prpvf: prendpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_csi1>;
+ };
+ ipu1_csi1_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_from_csi1>;
+ };
+ };
+ };
+
+ ipu1_smfc0: ipu1_smfc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_smfc0_from_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_to_smfc0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_smfc0_to_ic_pp1: pp-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_from_smfc0>;
+ };
+ ipu1_smfc0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_smfc0>;
+ };
+ ipu1_smfc0_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_smfc0>;
+ };
+ ipu1_smfc0_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_smfc0>;
+ };
+ };
+ };
+
+ ipu1_smfc1: ipu1_smfc at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_smfc1_from_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_to_smfc1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_smfc1_to_ic_pp2: pp-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_from_smfc1>;
+ };
+ ipu1_smfc1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_smfc1>;
+ };
+ ipu1_smfc1_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_smfc1>;
+ };
+ ipu1_smfc1_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_smfc1>;
+ };
+ };
+ };
+
+ ipu1_ic_prpenc: ipu1_ic_prpenc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_prpenc_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu1_csi0_to_ic_prpenc>;
+ };
+ ipu1_ic_prpenc_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu1_csi1_to_ic_prpenc>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_prpenc_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_prpenc>;
+ };
+ ipu1_ic_prpenc_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_prpenc>;
+ };
+ };
+ };
+
+ ipu1_ic_prpvf: ipu1_ic_prpvf at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_prpvf_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu1_csi0_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu1_csi1_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_to_ic_prpvf>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_prpvf_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_from_ic_prpvf>;
+ };
+ };
+ };
+
+ ipu1_ic_pp0: ipu1_ic_pp at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_pp0_from_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_to_ic_pp0>;
+ };
+ ipu1_ic_pp0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_pp0_to_m2m0: endpoint {
+ remote-endpoint = <&m2m0_from_ic_pp0>;
+ };
+ };
+ };
+
+ ipu1_ic_pp1: ipu1_ic_pp at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_pp1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_ic_pp1>;
+ };
+ ipu1_ic_pp1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_pp1_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_pp1>;
+ };
+ ipu1_ic_pp1_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_pp1>;
+ };
+ };
+ };
+
+ ipu1_ic_pp2: ipu1_ic_pp at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <2>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_pp2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_ic_pp2>;
+ };
+ ipu1_ic_pp2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp2>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_pp2_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_pp2>;
+ };
+ ipu1_ic_pp2_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_pp2>;
+ };
+ };
};
ipu1_di0: ipu1_di at 0 {
@@ -1284,5 +1538,119 @@
};
};
};
+
+ media0: media at 0 {
+ compatible = "fsl,imx-media", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ m2m0: m2m at 0 {
+ compatible = "fsl,imx-media-mem2mem";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ };
+
+ port at 1 {
+ reg = <1>;
+ m2m0_from_ic_pp0: endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_to_m2m0>;
+ };
+ m2m0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_m2m0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+ m2m0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_m2m0>;
+ };
+ m2m0_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_from_m2m0>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+ };
+ };
+
+ camif0: camif at 0 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ camif0_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_camif0>;
+ };
+ camif0_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_camif0>;
+ };
+ camif0_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_to_camif0>;
+ };
+ camif0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_camif0>;
+ };
+ camif0_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_to_camif0>;
+ };
+ camif0_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_to_camif0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+
+ camif1: camif at 1 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ camif1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_camif1>;
+ };
+ camif1_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_camif1>;
+ };
+ camif1_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_to_camif1>;
+ };
+ camif1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_camif1>;
+ };
+ camif1_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_to_camif1>;
+ };
+ camif1_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_to_camif1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 02/12] ARM: dts: imx6qdl: rename ipu client nodes
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
To allow for IPU client devices that are composed of more than one
port for input and output (SMFC and IC), change the nodes from being
a single port node to nodes that can contain multiple ports. Rename
the nodes to use the following format: "ipu<id>_<subunit>".
The IPUv3 driver will then need to lookup the client nodes by name
rather than by port id.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6q.dtsi | 12 ++++++------
arch/arm/boot/dts/imx6qdl.dtsi | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9a5d0b..2b261ba 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -141,18 +141,18 @@
clock-names = "bus", "di0", "di1";
resets = <&src 4>;
- ipu2_csi0: port at 0 {
+ ipu2_csi0: ipu2_csi at 0 {
reg = <0>;
};
- ipu2_csi1: port at 1 {
+ ipu2_csi1: ipu2_csi at 1 {
reg = <1>;
};
- ipu2_di0: port at 2 {
+ ipu2_di0: ipu2_di at 0 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
+ reg = <0>;
ipu2_di0_disp0: disp0-endpoint {
};
@@ -174,10 +174,10 @@
};
};
- ipu2_di1: port at 3 {
+ ipu2_di1: ipu2_di at 1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <3>;
+ reg = <1>;
ipu2_di1_hdmi: hdmi-endpoint {
remote-endpoint = <&hdmi_mux_3>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e01e5d5..2465187 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1226,18 +1226,18 @@
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
- ipu1_csi0: port at 0 {
+ ipu1_csi0: ipu1_csi at 0 {
reg = <0>;
};
- ipu1_csi1: port at 1 {
+ ipu1_csi1: ipu1_csi at 1 {
reg = <1>;
};
- ipu1_di0: port at 2 {
+ ipu1_di0: ipu1_di at 0 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
+ reg = <0>;
ipu1_di0_disp0: disp0-endpoint {
};
@@ -1259,10 +1259,10 @@
};
};
- ipu1_di1: port at 3 {
+ ipu1_di1: ipu1_di at 1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <3>;
+ reg = <1>;
ipu1_di1_disp1: disp1-endpoint {
};
--
2.7.4
^ permalink raw reply related
* [PATCH 01/12] ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Add to the MIPI CSI2 receiver node: compatible string, interrupt sources,
clocks.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index b13b0b2..e01e5d5 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1121,7 +1121,14 @@
};
mipi_csi: mipi at 021dc000 {
+ compatible = "fsl,imx-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ interrupts = <0 100 0x04>, <0 101 0x04>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
+ <&clks IMX6QDL_CLK_VIDEO_27M>,
+ <&clks IMX6QDL_CLK_EIM_SEL>;
+ clock-names = "dphy_clk", "cfg_clk", "pix_clk";
+ status = "disabled";
};
mipi_dsi: mipi at 021e0000 {
--
2.7.4
^ permalink raw reply related
* [PATCH 00/12] i.MX media devices and connections
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Philipp, Sascha, Shawn, et al,
I've been working for the past few months on a media driver for i.MX.
In addition to the media entities for the IPU-external units involved
with video capture (video mux and MIPI CSI-2 receiver), I've created
media entities for the IPU CSI, SMFC, and IC subunits. The IC entities
carry out scaling, CSC, horizontal/vertical flip, and rotation. In
addition, the IC-PRPVF entity carries out motion compensated
de-interlace.
The following series adds the OF device nodes and graphs that define
all the possible hardware connections supported by the i.MX involved
in video capture and image conversion.
Here are some of the pipelines defined by the OF graphs:
CSI -> IC-PRPENC
CSI -> IC-PRPVF
CSI -> IC-PRPVF -> IC-PP
CSI -> SMFC
CSI -> SMFC -> IC-PRPVF
CSI -> SMFC -> IC-PP
CSI -> SMFC -> IC-PRPVF -> IC-PP
You will notice that three IC-PP nodes are defined (ipu1_ic_pp0,
ipu1_ic_pp1, ipu1_ic_pp2, and same for ipu2). The reason for that
is that the IC-PP media entity uses the new ipu-image-conversion
API, which allows for multiple conversion contexts to be created.
Each IC-PP entity thus creates its own conversion context, and there
can be any number of IC-PP entities instantiated as needed by the OF
graph.
Camera sensor nodes are also added for the SabreAuto, SabreSD, and
SabreLite reference platforms.
The media driver is now in fairly good shape. It parses the OF graphs
to create the media pads and links. All the pipelines defined by the
OF graphs have been tested and are working. My media driver work is
at:
git at github.com:slongerbeam/mediatree.git, branch imx-media-staging-md-v2.
For an overview of the pipelines supported and usage notes for the
reference boards, you can refer to Documentation/media/v4l-drivers/imx.rst.
I realize there is collision here with the recent patch series posted by
Philipp, particularly around the video multiplexer and mipi csi-2 receiver
subdevs and OF graphs, as well as v4l2 capture drivers.
Philipp Zabel (1):
ARM: dts: imx6qdl: add video capture devices and connections
Steve Longerbeam (11):
ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
ARM: dts: imx6qdl: rename ipu client nodes
ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
ARM: dts: imx6-sabreauto: create i2cmux for i2c3
ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b
ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture
ARM: dts: imx6-sabreauto: add the ADV7180 video decoder
gpu: ipu-v3: Add ipu_unit_type enumeration
gpu: ipu-v3: lookup ipu client nodes by name
gpu: ipu-v3: Add smfc and ic client devices
arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 +
arch/arm/boot/dts/imx6dl-sabresd.dts | 5 +
arch/arm/boot/dts/imx6dl.dtsi | 190 ++++++++++++
arch/arm/boot/dts/imx6q-sabrelite.dts | 6 +
arch/arm/boot/dts/imx6q-sabresd.dts | 5 +
arch/arm/boot/dts/imx6q.dtsi | 497 ++++++++++++++++++++++++++++++-
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 148 +++++++--
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 122 +++++++-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 114 ++++++-
arch/arm/boot/dts/imx6qdl.dtsi | 385 +++++++++++++++++++++++-
drivers/gpu/ipu-v3/ipu-common.c | 142 ++++++++-
include/video/imx-ipu-v3.h | 21 ++
12 files changed, 1593 insertions(+), 47 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH] ARM: dts: imx7d: fix LCDIF clock assignment
From: Shawn Guo @ 2016-12-08 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207205314.GA20203@localhost>
On Wed, Dec 07, 2016 at 12:53:14PM -0800, Olof Johansson wrote:
> Applied, with the fixes line. In the future, please email arm at kernel.org too,
> it's easier to make sure we don't miss it that way.
Noted. Thanks, Olof.
Shawn
^ permalink raw reply
* [PATCH v3 2/2] clk: uniphier: add cpufreq data for LD11, LD20 SoCs
From: Stephen Boyd @ 2016-12-08 0:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481074353-31535-2-git-send-email-yamada.masahiro@socionext.com>
On 12/07, Masahiro Yamada wrote:
> Add more data to 64bit SoCs for the cpufreq support.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 1/2] clk: uniphier: add CPU-gear change (cpufreq) support
From: Stephen Boyd @ 2016-12-08 0:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481074353-31535-1-git-send-email-yamada.masahiro@socionext.com>
On 12/07, Masahiro Yamada wrote:
> Core support code for CPU frequency changes, which will be used by
> the generic cpufreq driver.
>
> The register view is different from the generic clk-mux; it has
> a separate status register, and an update bit to load the register
> setting.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] drm: hdlcd: Work properly in big-endian mode
From: Ilia Mirkin @ 2016-12-08 0:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <548dc9d9-4d21-7f93-cc92-5bc3234f1b8f@arm.com>
On Wed, Dec 7, 2016 at 11:42 AM, Robin Murphy <robin.murphy@arm.com> wrote:
> By comparison, the same use-cases (fbcon and fb-test) under the same
> big-endian kernel do *not* show the same problem with nouveau driving a
> PCIe 7600GT card, which led me to believe it was HDLCD-specific.
Just to randomly insert info here... NV11+ cards have a "big endian"
mode, where you can do 32-bit mmio from a big-endian cpu, and the card
will auto-swap those. There are similar additional bits that make
operating and accelerating off a big-endian CPU tolerable. Some care
has gone into the kernel to make sure that all that stuff works. (One
of those bits is that data gets byteswapped on upload to VRAM by
virtue of being uploaded by sticking data into a pushbuf, as I
recall.)
-ilia
^ permalink raw reply
* [PATCH v2.1 1/4] ARM: dts: davinci: da850: VPIF: add node and muxing
From: Kevin Hilman @ 2016-12-08 0:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207193137.27947-2-khilman@baylibre.com>
Add VPIF node an pins to da850 and enable on boards. VPIF has two input
channels described using the standard DT ports and enpoints.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
---
v2 -> v2.1: moved ports from SoC .dtsi to board .dts files.
arch/arm/boot/dts/da850-evm.dts | 20 ++++++++++++++++++++
arch/arm/boot/dts/da850-lcdk.dts | 13 +++++++++++++
arch/arm/boot/dts/da850.dtsi | 27 ++++++++++++++++++++++++++-
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 41de15fe15a2..cea36ee6fd07 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -289,3 +289,23 @@
};
};
};
+
+&vpif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vpif_capture_pins>;
+ status = "okay";
+
+ /* VPIF capture port */
+ port {
+ vpif_ch0: endpoint at 0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+
+ vpif_ch1: endpoint at 1 {
+ reg = <1>;
+ bus-width = <8>;
+ data-shift = <8>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 7b8ab21fed6c..5fc21528e0ba 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -219,3 +219,16 @@
};
};
};
+
+&vpif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vpif_capture_pins>;
+ status = "okay";
+
+ /* VPIF capture port */
+ port {
+ vpif_ch0: endpoint {
+ bus-width = <8>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index f79e1b91c680..5f0b40510b2b 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -186,7 +186,18 @@
0xc 0x88888888 0xffffffff
>;
};
-
+ vpif_capture_pins: vpif_capture_pins {
+ pinctrl-single,bits = <
+ /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
+ 0x38 0x11111111 0xffffffff
+ /* VP_DIN[10..15,0..1] */
+ 0x3c 0x11111111 0xffffffff
+ /* VP_DIN[8..9] */
+ 0x40 0x00000011 0x000000ff
+ /* VP_CLKIN3, VP_CLKIN2 */
+ 0x4c 0x00010100 0x000f0f00
+ >;
+ };
};
edma0: edma at 0 {
compatible = "ti,edma3-tpcc";
@@ -399,7 +410,21 @@
<&edma0 0 1>;
dma-names = "tx", "rx";
};
+
+ vpif: video at 217000 {
+ compatible = "ti,da850-vpif";
+ reg = <0x217000 0x1000>;
+ interrupts = <92>;
+ status = "disabled";
+
+ /* VPIF capture port */
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
+
aemif: aemif at 68000000 {
compatible = "ti,da850-aemif";
#address-cells = <2>;
--
2.9.3
^ permalink raw reply related
* linux-next: manual merge of the sunxi tree with the arm-soc tree
From: Stephen Rothwell @ 2016-12-08 0:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi Maxime,
Today's linux-next merge of the sunxi tree got a conflict in:
arch/arm/boot/dts/sun8i-h3.dtsi
between commit:
4367c1d84655 ("dts: sun8i-h3: correct UART3 pin definitions")
from the arm-soc tree and commits:
acac77949d26 ("ARM: sunxi: Remove useless allwinner,drive property")
3872abae96ef ("ARM: sunxi: Remove useless allwinner,pull property")
264969c22623 ("ARM: sunxi: Convert pinctrl nodes to generic bindings")
from the sunxi tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc arch/arm/boot/dts/sun8i-h3.dtsi
index 6c14a6f72820,fca66bf2dec5..000000000000
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@@ -425,10 -406,8 +406,8 @@@
};
uart3_pins: uart3 {
- allwinner,pins = "PA13", "PA14";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- pins = "PG13", "PG14";
++ pins = "PA13", "PA14";
+ function = "uart3";
};
};
^ permalink raw reply
* [PATCH 3/3] clk: keystone: Add sci-clk driver support
From: Stephen Boyd @ 2016-12-08 0:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477053961-27128-4-git-send-email-t-kristo@ti.com>
On 10/21, Tero Kristo wrote:
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 6a8ac04..dce08a7 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -169,6 +169,15 @@ config COMMON_CLK_NXP
> ---help---
> Support for clock providers on NXP platforms.
>
> +config TI_SCI_CLK
> + tristate "TI System Control Interface clock drivers"
> + depends on (TI_SCI_PROTOCOL && COMMON_CLK_KEYSTONE) || COMPILE_TEST
Given that we depend on COMMON_CLK_KEYSTONE (just for the
Makefile dependency?) this should be moved to right below the
COMMON_CLK_KEYSTONE config. And we should consider making a
Kconfig file in drivers/clk/keystone/ to hold both those configs
instead of having them at the toplevel.
> + default TI_SCI_PROTOCOL
> + ---help---
> + This adds the clock driver support over TI System Control Interface.
> + If you wish to use clock resources from the PMMC firmware, say Y.
> + Otherwise, say N.
> +
> config COMMON_CLK_PALMAS
> tristate "Clock driver for TI Palmas devices"
> depends on MFD_PALMAS
> diff --git a/drivers/clk/keystone/Makefile b/drivers/clk/keystone/Makefile
> index 0477cf6..0e7993d 100644
> --- a/drivers/clk/keystone/Makefile
> +++ b/drivers/clk/keystone/Makefile
> @@ -1 +1,2 @@
> obj-y += pll.o gate.o
> +obj-$(CONFIG_TI_SCI_CLK) += sci-clk.o
> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
> new file mode 100644
> index 0000000..f6af5bd
> --- /dev/null
> +++ b/drivers/clk/keystone/sci-clk.c
> @@ -0,0 +1,589 @@
[...]
> +
> +/**
> + * sci_clk_recalc_rate - Get clock rate for a TI SCI clock
> + * @hw: clock to get rate for
> + * @parent_rate: parent rate provided by common clock framework, not used
> + *
> + * Gets the current clock rate of a TI SCI clock. Returns the current
> + * clock rate, or zero in failure.
> + */
> +static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct sci_clk *clk = to_sci_clk(hw);
> + u64 freq;
> + int ret;
> +
> + ret = clk->provider->ops->get_freq(clk->provider->sci, clk->dev_id,
> + clk->clk_id, &freq);
> + if (ret) {
> + dev_err(clk->provider->dev,
> + "recalc-rate failed for dev=%d, clk=%d, ret=%d\n",
> + clk->dev_id, clk->clk_id, ret);
> + return 0;
> + }
> +
> + return (u32)freq;
Do we need the cast? sizeof(u32) doesn't always equal
sizeof(unsigned long).
> +
> +/**
> + * _sci_clk_get - Gets a handle for an SCI clock
> + * @provider: Handle to SCI clock provider
> + * @dev_id: device ID for the clock to register
> + * @clk_id: clock ID for the clock to register
> + *
> + * Gets a handle to an existing TI SCI hw clock, or builds a new clock
> + * entry and registers it with the common clock framework. Called from
> + * the common clock framework, when a corresponding of_clk_get call is
> + * executed, or recursively from itself when parsing parent clocks.
> + * Returns a pointer to the hw clock struct, or ERR_PTR value in failure.
> + */
> +static struct clk_hw *_sci_clk_build(struct sci_clk_provider *provider,
> + u16 dev_id, u8 clk_id)
> +{
> + struct clk_init_data init = { NULL };
> + struct sci_clk *sci_clk = NULL;
> + char *name = NULL;
> + char **parent_names = NULL;
> + int i;
> + int ret;
> +
> + sci_clk = devm_kzalloc(provider->dev, sizeof(*sci_clk), GFP_KERNEL);
> + if (!sci_clk)
> + return ERR_PTR(-ENOMEM);
> +
> + sci_clk->dev_id = dev_id;
> + sci_clk->clk_id = clk_id;
> + sci_clk->provider = provider;
> +
> + ret = provider->ops->get_num_parents(provider->sci, dev_id,
> + clk_id,
> + &init.num_parents);
> + if (ret)
> + goto err;
> +
> + name = kasprintf(GFP_KERNEL, "%s:%d:%d", dev_name(provider->dev),
> + sci_clk->dev_id, sci_clk->clk_id);
> +
> + init.name = name;
> +
> + if (init.num_parents < 2)
> + init.num_parents = 0;
This deserves a comment. Why is num_parents == 1 the same as
num_parents == 0?
> +
> + if (init.num_parents) {
> + parent_names = devm_kcalloc(provider->dev, init.num_parents,
> + sizeof(char *), GFP_KERNEL);
> +
> + if (!parent_names) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + for (i = 0; i < init.num_parents; i++) {
> + char *parent_name;
> +
> + parent_name = kasprintf(GFP_KERNEL, "%s:%d:%d",
> + dev_name(provider->dev),
> + sci_clk->dev_id,
> + sci_clk->clk_id + 1 + i);
> + if (!parent_name) {
> + ret = -ENOMEM;
> + goto err;
> + }
> + parent_names[i] = parent_name;
> + }
> + init.parent_names = (const char * const *)parent_names;
Does that really need a cast?
> + }
> +
> + init.ops = &sci_clk_ops;
> + sci_clk->hw.init = &init;
> +
> + ret = devm_clk_hw_register(provider->dev, &sci_clk->hw);
> + if (ret) {
> + dev_err(provider->dev, "failed clk register with %d\n", ret);
> + goto err;
> + }
> + kfree(name);
> +
> + return &sci_clk->hw;
> +
> +err:
> + if (parent_names) {
> + for (i = 0; i < init.num_parents; i++)
> + devm_kfree(provider->dev, parent_names[i]);
> +
> + devm_kfree(provider->dev, parent_names);
Shouldn't we be freeing the parent names all the time? It should
be deep copied in the framework.
> + }
> +
> + devm_kfree(provider->dev, sci_clk);
> +
> + kfree(name);
> +
> + return ERR_PTR(ret);
> +}
[..]
> +
> +static int ti_sci_init_clocks(struct sci_clk_provider *p)
> +{
> + struct sci_clk_data *data = p->clocks;
> + struct clk_hw *hw;
> + int i;
> +
> + while (data->num_clks) {
> + data->clocks = devm_kcalloc(p->dev, data->num_clks,
> + sizeof(struct sci_clk),
> + GFP_KERNEL);
> + if (!data->clocks)
> + return -ENOMEM;
> +
> + for (i = 0; i < data->num_clks; i++) {
> + hw = _sci_clk_build(p, data->dev, i);
> + if (!IS_ERR(hw)) {
> + data->clocks[i] = hw;
> + continue;
> + }
> +
> + /* Skip any holes in the clock lists */
> + if (PTR_ERR(hw) == -ENODEV)
Does this happen? I don't see where _sci_clk_build() returns
-ENODEV.
> + continue;
> +
> + return PTR_ERR(hw);
> + }
> + data++;
> + }
> +
> + return 0;
> +}
> +
> +
> +/**
> + * ti_sci_clk_probe - Probe function for the TI SCI clock driver
> + * @pdev: platform device pointer to be probed
> + *
> + * Probes the TI SCI clock device. Allocates a new clock provider
> + * and registers this to the common clock framework. Also applies
> + * any required flags to the identified clocks via clock lists
> + * supplied from DT. Returns 0 for success, negative error value
> + * for failure.
> + */
> +static int ti_sci_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct sci_clk_provider *provider;
> + const struct ti_sci_handle *handle;
> + struct sci_clk_data *data;
> + int ret;
> +
> + data = (struct sci_clk_data *)
> + of_match_node(ti_sci_clk_of_match, np)->data;
Just use of_device_get_match_data() instead.
> +
> + handle = devm_ti_sci_get_handle(dev);
> + if (IS_ERR(handle))
> + return PTR_ERR(handle);
> +
> + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
> + if (!provider)
> + return -ENOMEM;
> +
> + provider->clocks = data;
> +
> + provider->sci = handle;
> + provider->ops = &handle->ops.clk_ops;
> + provider->dev = dev;
> +
> + ti_sci_init_clocks(provider);
And if this fails?
> +
> + ret = of_clk_add_hw_provider(np, sci_clk_get, provider);
> + if (ret)
> + return ret;
> +
> + return 0;
Just "return of_clk_add_hw_provider()" please.
> +}
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] PM / Domains: Fix compatible for domain idle state
From: Rafael J. Wysocki @ 2016-12-08 0:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1616414.c1s7NxTqJS@aspire.rjw.lan>
On Thursday, December 01, 2016 10:21:59 PM Rafael J. Wysocki wrote:
> On Tuesday, November 29, 2016 09:47:03 AM Ulf Hansson wrote:
> > On 10 November 2016 at 20:58, Rob Herring <robh@kernel.org> wrote:
> > > On Mon, Nov 07, 2016 at 12:14:28PM +0100, Ulf Hansson wrote:
> > >> On 3 November 2016 at 22:54, Lina Iyer <lina.iyer@linaro.org> wrote:
> > >> > Re-using idle state definition provided by arm,idle-state for domain
> > >> > idle states creates a lot of confusion and limits further evolution of
> > >> > the domain idle definition. To keep things clear and simple, define a
> > >> > idle states for domain using a new compatible "domain-idle-state".
> > >> >
> > >> > Fix existing PM domains code to look for the newly defined compatible.
> > >> >
> > >> > Cc: <devicetree@vger.kernel.org>
> > >> > Cc: Rob Herring <robh@kernel.org>
> > >> > Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> > >> > ---
> > >> > .../bindings/power/domain-idle-state.txt | 33 ++++++++++++++++++++++
> > >> > .../devicetree/bindings/power/power_domain.txt | 8 +++---
> > >> > drivers/base/power/domain.c | 2 +-
> > >> > 3 files changed, 38 insertions(+), 5 deletions(-)
> > >> > create mode 100644 Documentation/devicetree/bindings/power/domain-idle-state.txt
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/power/domain-idle-state.txt b/Documentation/devicetree/bindings/power/domain-idle-state.txt
> > >> > new file mode 100644
> > >> > index 0000000..eefc7ed
> > >> > --- /dev/null
> > >> > +++ b/Documentation/devicetree/bindings/power/domain-idle-state.txt
> > >> > @@ -0,0 +1,33 @@
> > >> > +PM Domain Idle State Node:
> > >> > +
> > >> > +A domain idle state node represents the state parameters that will be used to
> > >> > +select the state when there are no active components in the domain.
> > >> > +
> > >> > +The state node has the following parameters -
> > >> > +
> > >> > +- compatible:
> > >> > + Usage: Required
> > >> > + Value type: <string>
> > >> > + Definition: Must be "domain-idle-state".
> > >> > +
> > >> > +- entry-latency-us
> > >> > + Usage: Required
> > >> > + Value type: <prop-encoded-array>
> > >> > + Definition: u32 value representing worst case latency in
> > >> > + microseconds required to enter the idle state.
> > >> > + The exit-latency-us duration may be guaranteed
> > >> > + only after entry-latency-us has passed.
> > >>
> > >> As we anyway are going to change this, why not use an u64 and have the
> > >> value in ns instead of us?
> > >
> > > I can't imagine that you would need more resolution or range. For times
> > > less than 1us, s/w and register access times are going to dominate the
> > > time.
> > >
> > > Unless there is a real need, I'd keep alignment with the existing
> > > binding.
> >
> > Rob, are you fine with this? I thought it would be great to get this
> > in for 4.10 rc1.
>
> Rob, any objections here?
Well, no objections, so applied.
Thanks,
Rafael
^ permalink raw reply
* [PATCH] drm: hdlcd: Work properly in big-endian mode
From: Daniel Vetter @ 2016-12-07 23:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <36dcbbc5-607a-1773-17e4-af2a9810a06e@arm.com>
On Wed, Dec 07, 2016 at 04:50:31PM +0000, Robin Murphy wrote:
> On 07/12/16 16:42, Robin Murphy wrote:
> > On 07/12/16 15:57, Daniel Vetter wrote:
> >> On Wed, Dec 07, 2016 at 03:31:40PM +0000, Robin Murphy wrote:
> >>> Under a big-endian kernel, colours on the framebuffer all come out a
> >>> delightful shade of wrong, since we fail to take the reversed byte
> >>> order into account. Fortunately, the HDLCD has a control bit to make it
> >>> automatically byteswap big-endian data; let's use it as appropriate.
> >>>
> >>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> >>
> >> fourcc codes (and the drm fourcc codes) are supposed to be little-endian.
> >> All of them. So either we fix up the drivers and userspace to set that
> >> flag correctly (which would mean hdlcd should expose twice as many
> >> formats, each one with the little and big endian mode).
> >
> > AFAICS, SIMPLEFB_FORMATS *is* supposed to be explicitly little-endian
> > modes. I see that DRM_FORMAT_BIG_ENDIAN exists, but nothing in-tree ever
> > sets it :/
> >
> > My vague (and probably wrong) assumption was that the HDLCD is still
> > expecting little-endian data, but the the CPU is writing framebuffer
> > data as host-endian words, hence what the HDLCD thinks is xRGB is
> > actually RGBx under a big-endian kernel - It's certainly consistent
> > between kernel (fbcon) and userspace (fb-test[1]): white is yellow, blue
> > is black, green is red and red is green. I don't know how to test
> > "proper" DRM (I've failed to get X to work with the Arch Linux ARM
> > distro I have on there at the moment).
> >
> > Once again I'm somewhat out of my depth here - I just found a thing that
> > seemed appropriate and visibly resolved the immediate problem :)
> > By comparison, the same use-cases (fbcon and fb-test) under the same
> > big-endian kernel do *not* show the same problem with nouveau driving a
> > PCIe 7600GT card, which led me to believe it was HDLCD-specific.
>
> Off the back of that, upon closer inspection, nv_crtc_commit() would
> appear to already be doing very much the equivalent thing to what I'm
> doing in this patch, so now I have no idea whether this is right or
> everything's wrong.
Congrats for finding a really big can of worms. Unfortunately I can't
really help you with figuring out what's the right choice here :(
Trying to fix up everything is probably going to be lots of work, but
assuming that everything is broken for big endian is probably correct.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply
* [PATCH] USB: OHCI: nxp: fix code warnings
From: csmanjuvijay at gmail.com @ 2016-12-07 23:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Manjunath Goudar <csmanjuvijay@gmail.com>
This patch will fix the checkpatch.pl following warnings:
WARNING: Missing a blank line after declarations
WARNING: braces {} are not necessary for single statement blocks
Signed-off-by: Manjunath Goudar <csmanjuvijay@gmail.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-usb at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
---
drivers/usb/host/ohci-nxp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index 1843f04..6df8e2e 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -125,6 +125,7 @@ static inline void isp1301_vbus_off(void)
static void ohci_nxp_start_hc(void)
{
unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
+
__raw_writel(tmp, USB_OTG_STAT_CONTROL);
isp1301_vbus_on();
}
@@ -132,6 +133,7 @@ static void ohci_nxp_start_hc(void)
static void ohci_nxp_stop_hc(void)
{
unsigned long tmp;
+
isp1301_vbus_off();
tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
__raw_writel(tmp, USB_OTG_STAT_CONTROL);
@@ -153,9 +155,8 @@ static int ohci_hcd_nxp_probe(struct platform_device *pdev)
}
isp1301_i2c_client = isp1301_get_client(isp1301_node);
- if (!isp1301_i2c_client) {
+ if (!isp1301_i2c_client)
return -EPROBE_DEFER;
- }
ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
--
2.7.4
^ permalink raw reply related
* [PATCH 08/16] drivers/fsi: Add crc4 helpers
From: Jeremy Kerr @ 2016-12-07 23:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207090219.GA14742@kroah.com>
Hi Greg,
> Why not just create lib/crc4.c with these functions, like the other crc
> functions in the kernel?
Two (bad) reasons:
- The crc4 implementation here is pretty specific to the FSI
usage (only supporting 4-bit-sized chunks), to keep the math & lookup
table simple
- I'm lazy
So yes, we should spend the effort now to make this generic enough for
a lib/crc4.c. Would we want to support different values for the
polynomial?
Chris: do you want me to to that, or will you?
Cheers,
Jeremy
^ permalink raw reply
* [PATCH 05/16] drivers/fsi: Add fake master driver
From: Jeremy Kerr @ 2016-12-07 23:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207120905.GD7054@leverpostej>
Hi Mark & Chris,
> On Tue, Dec 06, 2016 at 06:14:26PM -0600, Chris Bostic wrote:
>> From: Jeremy Kerr <jk@ozlabs.org>
>>
>> For debugging, add a fake master driver, that only supports reads,
>> returning a fixed set of data.
>
>> +config FSI_MASTER_FAKE
>> + tristate "Fake FSI master"
>> + depends on FSI
>> + ---help---
>> + This option enables a fake FSI master driver for debugging.
>> +endif
>
>> +static const struct of_device_id fsi_master_fake_match[] = {
>> + { .compatible = "ibm,fsi-master-fake" },
>> + { },
>> +};
>
> NAK.
>
> DT should be treated as an ABI, and should describe the HW explicitly.
> This makes no sense. This is also missing a binding document.
>
> Have your module take a module parameter allowing you to bind it to
> arbitrary devices, or do something like what PCI does where you can
> bind/unbind arbitrary drivers to devices using sysfs.
This driver is purely for testing the FSI engine scan code; we could
probably just drop this patch since I suspect that it's no longer useful
(now that we have an actual master driver).
If we do want to keep it though, I'd say we remove the device tree
dependency; all this is doing at the moment is triggering the ->probe,
and there are better ways to do that.
Cheers,
Jeremy
^ permalink raw reply
* [PATCH v2 1/2] arm64: dts: zx: Fix gic GICR property
From: Arnd Bergmann @ 2016-12-07 23:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMh5=R18+wfM5WjUPnQ2a7UFi35t11cRDyTwCYHxpySnMg@mail.gmail.com>
On Wednesday, December 7, 2016 2:12:23 PM CET Olof Johansson wrote:
> > I checked the other branches now and found two other commits missing
> > in next/fixes-non-critical:
> >
> >
> > arm64: tegra: Add missing Smaug revision
> > arm64: tegra: Add VDD_GPU regulator to Jetson TX1
> >
> > Both sent by Thierry Reding last Friday. I can add them back on top
> > or you pick them up again if you are already busy doing merges.
> >
> > For the first patch, I had amended the changelog text, this is the
> > version I had.
>
> I'm done touching the tree for today so you can rebase and push your
> versions if you want -- probably easiest all around.
>
Done.
Arnd
^ permalink raw reply
* [PATCH v2 1/4] ARM: dts: davinci: da850: VPIF: add node and muxing
From: Kevin Hilman @ 2016-12-07 23:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <37047453.6bLpOkkjm4@avalon>
Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:
> Hi Kevin,
>
> Thank you for the patch.
>
> On Wednesday 07 Dec 2016 11:31:34 Kevin Hilman wrote:
>> Add VPIF node an pins to da850 and enable on boards. VPIF has two input
>> channels described using the standard DT ports and enpoints.
>>
>> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
>> ---
>> arch/arm/boot/dts/da850-evm.dts | 6 ++++++
>> arch/arm/boot/dts/da850-lcdk.dts | 6 ++++++
>> arch/arm/boot/dts/da850.dtsi | 38 +++++++++++++++++++++++++++++++++++-
>> 3 files changed, 49 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/da850-evm.dts
>> b/arch/arm/boot/dts/da850-evm.dts index 41de15fe15a2..212b50d4f84b 100644
>> --- a/arch/arm/boot/dts/da850-evm.dts
>> +++ b/arch/arm/boot/dts/da850-evm.dts
>> @@ -289,3 +289,9 @@
>> };
>> };
>> };
>> +
>> +&vpif {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vpif_capture_pins>;
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/da850-lcdk.dts
>> b/arch/arm/boot/dts/da850-lcdk.dts index 7b8ab21fed6c..67f846f5bb35 100644
>> --- a/arch/arm/boot/dts/da850-lcdk.dts
>> +++ b/arch/arm/boot/dts/da850-lcdk.dts
>> @@ -219,3 +219,9 @@
>> };
>> };
>> };
>> +
>> +&vpif {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vpif_capture_pins>;
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>> index f79e1b91c680..dd2a13ed106e 100644
>> --- a/arch/arm/boot/dts/da850.dtsi
>> +++ b/arch/arm/boot/dts/da850.dtsi
>> @@ -186,7 +186,18 @@
>> 0xc 0x88888888 0xffffffff
>>
>> >;
>>
>> };
>> -
>> + vpif_capture_pins: vpif_capture_pins {
>> + pinctrl-single,bits = <
>> + /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0
> */
>> + 0x38 0x11111111 0xffffffff
>> + /* VP_DIN[10..15,0..1] */
>> + 0x3c 0x11111111 0xffffffff
>> + /* VP_DIN[8..9] */
>> + 0x40 0x00000011 0x000000ff
>> + /* VP_CLKIN3, VP_CLKIN2 */
>> + 0x4c 0x00010100 0x000f0f00
>> + >;
>> + };
>> };
>> edma0: edma at 0 {
>> compatible = "ti,edma3-tpcc";
>> @@ -399,7 +410,32 @@
>> <&edma0 0 1>;
>> dma-names = "tx", "rx";
>> };
>> +
>> + vpif: video at 217000 {
>> + compatible = "ti,da850-vpif";
>> + reg = <0x217000 0x1000>;
>> + interrupts = <92>;
>> + status = "disabled";
>> +
>> + /* VPIF capture: input channels */
>> + port {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + vpif_ch0: endpoint at 0 {
>> + reg = <0>;
>> + bus-width = <8>;
>> + };
>> +
>> + vpif_ch1: endpoint at 1 {
>> + reg = <1>;
>> + bus-width = <8>;
>> + data-shift = <8>;
>> + };
>
> Given that the VPIF can also accept a single 16-bit input, I'd move the
> endpoints to board files.
>
Yes, good point. Will move them.
Kevin
^ permalink raw reply
* [PATCH v2] ARM: dts: lpc32xx: add pwm-cells to base dts file
From: Vladimir Zapolskiy @ 2016-12-07 22:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481139047-13166-1-git-send-email-slemieux.tyco@gmail.com>
Hi Sylvain,
On 12/07/2016 09:30 PM, Sylvain Lemieux wrote:
> From: Sylvain Lemieux <slemieux@tycoint.com>
>
> There is no need to define the "pwm-cells" in the board
> specific dts file; move the entry to the base dts file.
>
> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
> ---
thank you for the change,
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH] clk: uniphier: Fix build with gcc-4.4.
From: Arnd Bergmann @ 2016-12-07 22:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206231642.GA4388@codeaurora.org>
On Tuesday, December 6, 2016 3:16:42 PM CET Stephen Boyd wrote:
> On 12/03, Masahiro Yamada wrote:
> > 2016-12-03 9:37 GMT+09:00 Vinson Lee <vlee@freedesktop.org>:
> > > gcc-4.4 has issues with anonymous unions in initializers.
> > >
> > > CC drivers/clk/uniphier/clk-uniphier-sys.o
> > > drivers/clk/uniphier/clk-uniphier-sys.c:45: error: unknown field ?factor? specified in initializer
> > >
> I'll go drop all three patches and wreck Andrew's merge of this
> patch to -mm.
While the specific bug is resolved now, I'm curious about the
motivation for the first fix: Vinson, are you actually using
a seven year old compiler to build modern kernels in order
to run them on real systems, or is this for the purpose of
build testing only?
It would be good to know if there are actual requirements
for using compilers this old (or even older, as according
to the README file, we theoretically support building even
with gcc-3.2 from 2002), in case we ever want to officially
raise the minimum required versions.
I see that gcc-4.3 builds an ARM defconfig kernel 17% faster than
gcc-7.0, which may be nice for build testing, but it also produces
thousands of false-positive warnings, which makes it rather
useless for actually finding bugs in build testing.
Arnd
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox