* [PATCH v8 1/3] ARM: sunxi_defconfig: Add CONFIG_THERMAL_OF
From: Quentin Schulz @ 2016-12-09 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161209102236.17655-1-quentin.schulz@free-electrons.com>
This enables CONFIG_THERMAL_OF by default for sunxi_defconfig. It is
required to get Allwinner SoCs' temperature from the GPADC driver.
The Allwinner SoCs all have an ADC that can also act as a touchscreen
controller and a thermal sensor. The first four channels can be used
either for the ADC or the touchscreen and the fifth channel is used for
the thermal sensor.
The thermal sensor requires the IP to be in touchscreen mode to return
correct values. Therefore, if the user is continuously reading the ADC
channel(s), the thermal framework in which the thermal sensor is
registered will switch the IP in touchscreen mode to get a temperature
value and requires a delay of 100ms (because of the mode switching),
then the ADC will switch back to ADC mode and requires also a delay of
100ms. If the ADC readings are critical to user and the SoC temperature
is not, the GPADC driver is capable of not registering the thermal
sensor in the thermal framework and thus, "quicken" the ADC readings. In
most use cases, the SoC temperature is more critical (for cpu throttling
for example or activating cooling devices) than ADC readings, thus it is
now enabled by default.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
v8:
- more explanatory commit log,
added in v7
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 714da33..8aaeae3 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -83,6 +83,7 @@ CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y
CONFIG_AXP20X_POWER=y
CONFIG_THERMAL=y
+CONFIG_THERMAL_OF=y
CONFIG_CPU_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
--
2.9.3
^ permalink raw reply related
* [PATCH v8 0/3] add support for Allwinner SoCs ADC
From: Quentin Schulz @ 2016-12-09 10:22 UTC (permalink / raw)
To: linux-arm-kernel
The Allwinner SoCs all have an ADC that can also act as a touchscreen
controller and a thermal sensor. The first four channels can be used
either for the ADC or the touchscreen and the fifth channel is used for
the thermal sensor. We currently have a driver for the two latter
functions in drivers/input/touchscreen/sun4i-ts.c but we don't have
access to the ADC feature at all. It is meant to replace the current
driver by using MFD and subdrivers.
This adds initial support for Allwinner SoCs ADC with all features. Yet,
the touchscreen is not implemented but will be added later. To switch
between touchscreen and ADC modes, you need to poke a few bits in
registers and (de)activate an interrupt (pen-up).
When changing modes or channels, the IP is in inconsistent mode and has
no register or interrupt to notify the kernel when it's stable and ready
to return correct values. Therefore, we add a delay of 100ms when
changing modes and 10ms when changing channels. These values have been
found empirically.
An MFD is provided to let the input driver activate the pen-up interrupt
through a virtual interrupt, poke a few bits via regmap and read data
from the ADC driver while both (and iio_hwmon) are probed by the MFD.
The thermal sensor requires the IP to be in touchscreen mode to return
correct values. Therefore, if the user is continuously reading the ADC
channel(s), the thermal framework in which the thermal sensor is
registered will switch the IP in touchscreen mode to get a temperature
value and requires a delay of 100ms (because of the mode switching),
then the ADC will switch back to ADC mode and requires also a delay of
100ms. If the ADC readings are critical to user and the SoC temperature
is not, this driver is capable of not registering the thermal sensor in
the thermal framework and thus, "quicken" the ADC readings. In most use
cases, the SoC temperature is more critical (for cpu throttling for
example or activating cooling devices) than ADC readings, thus it is
enabled by default in multi_v7_defconfig and in sunxi_defconfig (default
being added in this patch series).
There are slight variations between the different SoCs ADC like the
address of some registers and the scale and offset to apply to raw
thermal sensor values. These variations are handled by using different
platform_device_id, passed to the sub-drivers when they are probed by
the MFD.
Removal of proposed patch for iio_hwmon's iio channel's label in v3. The
patch induces irreversible ABI changes and will be handled as a separate
patch since I think it is not absolutely necessary to have labels yet in
iio_hwmon.
Removal of proposed patch for reattaching of_node of the MFD to the MFD
cell device structure in v3. As Lee Jones said, this patch might cause
"unintended side-effects for existing drivers.". Moreover, this patch
introduced a bug of multiple probe of this MFD driver I haven't
identified yet. This patch aimed at allowing the ADC driver (which is a
child of the MFD and not present in the DT) to register in the thermal
framework. The thermal driver has a phandle to the MFD node which is
used to match against the MFD of_node but since the ADC driver has no
node in the DT, could not register in the thermal framework. The other
solution is to "impersonate" the MFD when registering in the thermal
framework since the device is only used to match the phandle and the
of_node, an other structure passed by parameter being used to compute
temperatures.
(in the ADC driver, probed by the MFD driver) instead of:
tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, info,
&sun4i_ts_tz_ops);
we now have:
tzd = devm_thermal_zone_of_sensor_register(pdev->dev.parent, 0, info,
&sun4i_ts_tz_ops);
Removal of proposed patch to use late_initcall for iio_hwmon probe
deferring.
Removal of patch for iio_hwmon probe deferring due to being applied to
-next by Guenter Roeck.
This patch series requires this[1] patch which has already been merged
by Lee Jones.
[1] https://patchwork.kernel.org/patch/9333547/
Quentin Schulz (3):
ARM: sunxi_defconfig: Add CONFIG_THERMAL_OF
mfd: Kconfig: MFD_SUN4I_GPADC depends on !TOUCHSCREN_SUN4I_GPADC
iio: adc: add support for Allwinner SoCs ADC
arch/arm/configs/sunxi_defconfig | 1 +
drivers/iio/adc/Kconfig | 16 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/sun4i-gpadc-iio.c | 612 ++++++++++++++++++++++++++++++++++++++
drivers/mfd/Kconfig | 1 +
include/linux/mfd/sun4i-gpadc.h | 2 +
6 files changed, 633 insertions(+)
create mode 100644 drivers/iio/adc/sun4i-gpadc-iio.c
--
2.9.3
^ permalink raw reply
* [PATCH v6 2/5] [media] davinci: vpif_capture: remove hard-coded I2C adapter id
From: Sakari Ailus @ 2016-12-09 10:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207183025.20684-3-khilman@baylibre.com>
Hi Kevin,
On Wed, Dec 07, 2016 at 10:30:22AM -0800, Kevin Hilman wrote:
> Remove hard-coded I2C adapter in favor of getting the
> ID from platform_data.
>
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
> ---
> drivers/media/platform/davinci/vpif_capture.c | 5 ++++-
> include/media/davinci/vpif_types.h | 1 +
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c
> index 20c4344ed118..c24049acd40a 100644
> --- a/drivers/media/platform/davinci/vpif_capture.c
> +++ b/drivers/media/platform/davinci/vpif_capture.c
> @@ -1486,7 +1486,10 @@ static __init int vpif_probe(struct platform_device *pdev)
> }
>
> if (!vpif_obj.config->asd_sizes) {
> - i2c_adap = i2c_get_adapter(1);
> + int i2c_id = vpif_obj.config->i2c_adapter_id;
Is there a particular reason to use a temporary variable just once? I'd use
the i2c_adapter_field directly instead. Up to you.
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> +
> + i2c_adap = i2c_get_adapter(i2c_id);
> + WARN_ON(!i2c_adap);
> for (i = 0; i < subdev_count; i++) {
> subdevdata = &vpif_obj.config->subdev_info[i];
> vpif_obj.sd[i] =
> diff --git a/include/media/davinci/vpif_types.h b/include/media/davinci/vpif_types.h
> index 3cb1704a0650..4282a7db99d4 100644
> --- a/include/media/davinci/vpif_types.h
> +++ b/include/media/davinci/vpif_types.h
> @@ -82,6 +82,7 @@ struct vpif_capture_config {
> struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS];
> struct vpif_subdev_info *subdev_info;
> int subdev_count;
> + int i2c_adapter_id;
> const char *card_name;
> struct v4l2_async_subdev **asd; /* Flat array, arranged in groups */
> int *asd_sizes; /* 0-terminated array of asd group sizes */
--
Sakari Ailus
e-mail: sakari.ailus at iki.fi XMPP: sailus at retiisi.org.uk
^ permalink raw reply
* [PATCH v2 1/2] firmware: arm_scpi: zero RX buffer before requesting data from the mbox
From: Jon Medhurst (Tixy) @ 2016-12-09 10:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161125005432.1205-2-martin.blumenstingl@googlemail.com>
On Fri, 2016-11-25 at 01:54 +0100, Martin Blumenstingl wrote:
> The original code was relying on the fact that the SCPI firmware
> responds with the same number of bytes (or more, all extra data would be
> ignored in that case) as requested.
> However, we have some pre-v1.0 SCPI firmwares which are responding with
> less data for some commands (sensor_value.hi_val did not exist in the
> old implementation). This means that some data from the previous
> command's RX buffer was leaked into the current command (as the RX
> buffer is re-used for all commands on the same channel). Clearing the
> RX buffer before (re-) using it ensures we get a consistent result, even
> if the SCPI firmware returns less bytes than requested.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/firmware/arm_scpi.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
> index 70e1323..8c183d8 100644
> --- a/drivers/firmware/arm_scpi.c
> +++ b/drivers/firmware/arm_scpi.c
> @@ -259,6 +259,7 @@ struct scpi_chan {
> struct mbox_chan *chan;
> void __iomem *tx_payload;
> void __iomem *rx_payload;
> + resource_size_t max_payload_len;
Ah, here's max_payload_len, sorry, I reviewed the patches in the wrong
order. And reflecting on things, having the runtime
> struct list_head rx_pending;
> struct list_head xfers_list;
> struct scpi_xfer *xfers;
> @@ -470,6 +471,20 @@ static void scpi_tx_prepare(struct mbox_client *c, void *msg)
> if (t->rx_buf) {
> if (!(++ch->token))
> ++ch->token;
> +
> + /* clear the RX buffer as it is shared across all commands on
> + * the same channel (to make sure we're not leaking data from
> + * the previous response into the current command if the SCPI
> + * firmware writes less data than requested).
> + * This is especially important for pre-v1.0 SCPI firmwares
> + * where some fields in the responses do not exist (while they
> + * exist but are optional in newer versions). One example for
> + * this problem is sensor_value.hi_val, which would contain
> + * ("leak") the second 4 bytes of the RX buffer from the
> + * previous command.
> + */
> + memset_io(ch->rx_payload, 0, ch->max_payload_len);
> +
Isn't the payload size specified in the header? In which case the bug
you describe is due to the implementation writing 4 bytes and setting
the length to 8. Anyway, this seems almost like a quirk of a specific
implementation and perhaps should be handled as such, rather that doing
this for all commands on all boards using SCPI.
> ADD_SCPI_TOKEN(t->cmd, ch->token);
> spin_lock_irqsave(&ch->rx_lock, flags);
> list_add_tail(&t->node, &ch->rx_pending);
> @@ -921,7 +936,9 @@ static int scpi_probe(struct platform_device *pdev)
> ret = -EADDRNOTAVAIL;
> goto err;
> }
> - pchan->tx_payload = pchan->rx_payload + (size >> 1);
> +
> + pchan->max_payload_len = size / 2;
> + pchan->tx_payload = pchan->rx_payload + pchan->max_payload_len;
>
> cl->dev = dev;
> cl->rx_callback = scpi_handle_remote_msg;
--
Tixy
^ permalink raw reply
* [PATCH renesas/devel] arm64: dts: r8a7795: Use Gen 3 fallback compat string for PCIE
From: Simon Horman @ 2016-12-09 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdV9uumxxwsU_7pL+8Eo+n7+-Os+h7n8tbNvtdVp4pH5hg@mail.gmail.com>
On Fri, Dec 09, 2016 at 11:01:00AM +0100, Geert Uytterhoeven wrote:
> On Thu, Dec 8, 2016 at 4:29 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> > Use recently added en 3 fallback compat string for PCIE
> > in r8a7795 DT.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have queued this up for v4.11.
^ permalink raw reply
* [PATCH v6 1/5] [media] davinci: VPIF: fix module loading, init errors
From: Sakari Ailus @ 2016-12-09 10:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207183025.20684-2-khilman@baylibre.com>
On Wed, Dec 07, 2016 at 10:30:21AM -0800, Kevin Hilman wrote:
> Fix problems with automatic module loading by adding MODULE_ALIAS. Also
> fix various load-time errors cause by incorrect or not present
> platform_data.
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
--
Sakari Ailus
e-mail: sakari.ailus at iki.fi XMPP: sailus at retiisi.org.uk
^ permalink raw reply
* [PATCH renesas/devel] arm64: dts: r8a7795: Use Gen 3 fallback compat string for PCIE
From: Geert Uytterhoeven @ 2016-12-09 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481210969-2574-1-git-send-email-horms+renesas@verge.net.au>
On Thu, Dec 8, 2016 at 4:29 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> Use recently added en 3 fallback compat string for PCIE
> in r8a7795 DT.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v3 0/4] mm: fix the "counter.sh" failure for libhugetlbfs
From: Huang Shijie @ 2016-12-09 9:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161208095253.GB8330@dhcp22.suse.cz>
On Thu, Dec 08, 2016 at 10:52:54AM +0100, Michal Hocko wrote:
> On Thu 08-12-16 17:36:24, Huang Shijie wrote:
> > On Wed, Dec 07, 2016 at 11:02:38PM +0800, Michal Hocko wrote:
> [...]
> > > I haven't yet checked your patchset but I can tell you one thing.
> >
> > Could you please review the patch set when you have time? Thanks a lot.
>
> From a quick glance you do not handle the reservation code at all. You
Thanks, I will study the code again, and try to find What we need to do
with the reservation code.
> just make sure that the allocation doesn't fail unconditionally. I might
> be wrong here and Naoya resp. Mike will know much better but this seems
> far from enough to me.
>
> Well, this would take me quite some time and basically restudy the whole
> hugetlb code again. What you are trying to achieve is not a simple "fix
> a test case" thing. You are trying to implement full featured giga pages
> suport. And as I've said this requires a deeper understanding of the
> current code and clean it up considerably wrt. giga pages. This is
> definitely desirable plan longterm and I would like to encourage you for
> that but it is not a simple project at the same time.
Okay, I will try to implement the full featured giga pages support. :)
But I feel confused at the "full featured". If the patch set can pass
all the giga pages tests in the libhugetlbfs, can we say it is "full
featured"? Or some one reviews this patch set, and say it is full
featured support for the giga pages.
Thanks
Huang Shijie
^ permalink raw reply
* [PATCH v2 2/2] firmware: arm_scpi: check the payload length in scpi_send_message
From: Jon Medhurst (Tixy) @ 2016-12-09 9:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161125005432.1205-3-martin.blumenstingl@googlemail.com>
On Fri, 2016-11-25 at 01:54 +0100, Martin Blumenstingl wrote:
> This adds a sanity check to ensure we're not writing data beyond the
> end of our rx_buf and tx_buf. Currently we are still far from reaching
> this limit, so this is a non-critical fix.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/firmware/arm_scpi.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
> index 8c183d8..78ea8c7 100644
> --- a/drivers/firmware/arm_scpi.c
> +++ b/drivers/firmware/arm_scpi.c
> @@ -538,6 +538,11 @@ static int scpi_send_message(u8 idx, void *tx_buf, unsigned int tx_len,
> scpi_info->num_chans;
> scpi_chan = scpi_info->channels + chan;
>
> + if (tx_len > scpi_chan->max_payload_len)
> + return -EINVAL;
> + if (rx_len > scpi_chan->max_payload_len)
> + return -EINVAL;
What is max_payload_len? I don't see it in anywhere in the kernel tree.
Also, why is the check needed? Surely having a channel not be able to
support the requirements of the SCPI protocol is a bit of a
design/configuration flaw of the system and shouldn't happen. If a check
is really needed perhaps it also warrants a WARN_ON or similar?
> +
> msg = get_scpi_xfer(scpi_chan);
> if (!msg)
> return -ENOMEM;
--
Tixy
^ permalink raw reply
* [PATCH v1 2/2] crypto: mediatek - add DT bindings documentation
From: Matthias Brugger @ 2016-12-09 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481188776.14860.26.camel@mtkswgap22>
On 08/12/16 10:19, Ryder Lee wrote:
> Hello,
>
> On Mon, 2016-12-05 at 11:18 +0100, Matthias Brugger wrote:
>>
>> On 05/12/16 08:01, Ryder Lee wrote:
>>> Add DT bindings documentation for the crypto driver
>>>
>>> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
>>> ---
>>> .../devicetree/bindings/crypto/mediatek-crypto.txt | 32 ++++++++++++++++++++++
>>> 1 file changed, 32 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
>>> new file mode 100644
>>> index 0000000..8b1db08
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
>>> @@ -0,0 +1,32 @@
>>> +MediaTek cryptographic accelerators
>>> +
>>> +Required properties:
>>> +- compatible: Should be "mediatek,mt7623-crypto"
>>
>> Do you know how big the difference is between the crypto engine for
>> mt7623/mt2701/mt8521p in comparison, let's say mt8173 or mt6797?
>> Do this SoCs have a crypot engine? If so and they are quite similar, we
>> might think of adding a mtk-crypto binding and add soc specific bindings.
>
> This engine is just available in mt7623/mt2701/mt8521p series SoCs and
> they have no difference.
>
> But there are still other crypto IPs in MTK, i think maybe we could use
> "mediatek,{IP name}-crypto? to distinguish them ?
>
Sounds good, thanks for the clarification.
Matthias
>> Regards,
>> Matthias
>>
>>> +- reg: Address and length of the register set for the device
>>> +- interrupts: Should contain the five crypto engines interrupts in numeric
>>> + order. These are global system and four descriptor rings.
>>> +- clocks: the clock used by the core
>>> +- clock-names: the names of the clock listed in the clocks property. These are
>>> + "ethif", "cryp"
>>> +- power-domains: Must contain a reference to the PM domain.
>>> +
>>> +
>>> +Optional properties:
>>> +- interrupt-parent: Should be the phandle for the interrupt controller
>>> + that services interrupts for this device
>>> +
>>> +
>>> +Example:
>>> + crypto: crypto at 1b240000 {
>>> + compatible = "mediatek,mt7623-crypto";
>>> + reg = <0 0x1b240000 0 0x20000>;
>>> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
>>> + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
>>> + <ðsys CLK_ETHSYS_CRYPTO>;
>>> + clock-names = "ethif","cryp";
>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
>>> + };
>>>
>
>
^ permalink raw reply
* [PATCH RFC] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
From: Maxime Ripard @ 2016-12-09 9:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65uTH_PD28KqAhhzkE5zhLt54GUb7xXNxxe0xHW0A+xjQ@mail.gmail.com>
On Wed, Dec 07, 2016 at 10:26:25AM +0800, Chen-Yu Tsai wrote:
> > Some panels require an exact frequency, some have a minimal frequency
> > but no maximum, some have a maximum frequency but no minimal, and I
> > guess most of them deviates by how much exactly they can take (and
> > possibly can take more easily a higher frequency, but are less
> > tolerant if you take a frequency lower than the nominal.
> >
> > And we cannot remove that check entirely, since some bridges will
> > report out of range frequencies for higher modes that we know we
> > cannot reach.
>
> I believe this should be handled by the bridge driver in the check
> callback?
This doesn't really have anything to do with the bridge itself, it's a
limitation on the encoder. For all we know, the bridge might be able
to operate at the higher resolutions without any issues if the encoder
was able to.
> The callback I'm changing is attached to the connector, which I
> think doesn't get used if you have a bridge instead. And this only
> checks the pre-registered display modes, such as those specified in
> simple-panel or EDID.
Geeee, I forgot to send that one (and thought I did)... I'll send that
patch next week, but basically, I was creating a mode_valid hook at
the encoder level, and moving the RGB mode_valid hook from the
connector to the encoder (since it really is an encoder limitation).
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [RFC PATCH net-next v3 1/2] macb: Add 1588 support in Cadence GEM.
From: Rafal Ozieblo @ 2016-12-09 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <07C910AB6AC6C345A093D5A08F5AF568CB74AF28@CHN-SV-EXMX03.mchp-main.com>
-----Original Message-----
> From: Andrei.Pistirica at microchip.com [mailto:Andrei.Pistirica at microchip.com]
> Sent: 8 grudnia 2016 15:42
> To: richardcochran at gmail.com
> Cc: netdev at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; davem at davemloft.net; nicolas.ferre at atmel.com; harinikatakamlinux at gmail.com; harini.katakam at xilinx.com; punnaia at xilinx.com; michals at xilinx.com; anirudh at xilinx.com; boris.brezillon at free-electrons.com; alexandre.belloni at free-electrons.com; tbultel at pixelsurmer.com; Rafal Ozieblo
> Subject: RE: [RFC PATCH net-next v3 1/2] macb: Add 1588 support in Cadence GEM.
>
>
>
> > -----Original Message-----
> > From: Richard Cochran [mailto:richardcochran at gmail.com]
> > Sent: Wednesday, December 07, 2016 11:04 PM
> > To: Andrei Pistirica - M16132
> > Cc: netdev at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> > kernel at lists.infradead.org; davem at davemloft.net;
> > nicolas.ferre at atmel.com; harinikatakamlinux at gmail.com;
> > harini.katakam at xilinx.com; punnaia at xilinx.com; michals at xilinx.com;
> > anirudh at xilinx.com; boris.brezillon at free-electrons.com;
> > alexandre.belloni at free-electrons.com; tbultel at pixelsurmer.com;
> > rafalo at cadence.com
> > Subject: Re: [RFC PATCH net-next v3 1/2] macb: Add 1588 support in
> > Cadence GEM.
> >
> > On Wed, Dec 07, 2016 at 08:39:09PM +0100, Richard Cochran wrote:
> > > > +static s32 gem_ptp_max_adj(unsigned int f_nom) {
> > > > + u64 adj;
> > > > +
> > > > + /* The 48 bits of seconds for the GEM overflows every:
> > > > + * 2^48/(365.25 * 24 * 60 *60) =~ 8 925 512 years (~= 9 mil years),
> > > > + * thus the maximum adjust frequency must not overflow CNS
> > register:
> > > > + *
> > > > + * addend = 10^9/nominal_freq
> > > > + * adj_max = +/- addend*ppb_max/10^9
> > > > + * max_ppb = (2^8-1)*nominal_freq-10^9
> > > > + */
> > > > + adj = f_nom;
> > > > + adj *= 0xffff;
> > > > + adj -= 1000000000ULL;
> > >
> > > What is this computation, and how does it relate to the comment?
>
> I considered the following simple equation: increment value at nominal frequency (which is 10^9/nominal frequency nsecs) + the maximum drift value (nsecs) <= maximum increment value@nominal frequency (which is 8bit:0xffff).
> If maximum drift is written as function of nominal frequency and maximum ppb, then the equation above yields that the maximum ppb is: (2^8 - 1) *nominal_frequency - 10^9. The equation is also simplified by the fact that the drift is written as ppm + 16bit_fractions and the increment value is written as nsec + 16bit_fractions.
>
> Rafal said that this value is hardcoded: 0x64E6, while Harini said: 250000000.
To clarify a little bit. In my reference code this value (0x64E6) was taken from our legacy code. It was used for testing only. I know it should be change to something more accurate. This is the reason why I asked how did you count it (250000000). According to our calculations this value depends on actual set period (incr_ns and incr_sub_ns) and min and max value we can set. The calculation were a little bit intricate, so we decided to leave it as it was.
>
> I need to dig into this...
>
> >
> > I am not sure what you meant, but it sounds like you are on the wrong track.
> > Let me explain...
>
> Thanks.
>
> >
> > The max_adj has nothing at all to do with the width of the time register.
> > Rather, it should reflect the maximum possible change in the tuning word.
> >
> > For example, with a nominal 8 ns period, the tuning word is 0x80000.
> > Looking at running the clock more slowly, the slowest possible word is
> > 0x00001, meaning a difference of 0x7FFFF. This implies an adjustment
> > of
> > 0x7FFFF/0x80000 or 999998092 ppb. Running more quickly, we can
> > already have 0x100000, twice as fast, or just under 2 billion ppb.
> >
> > You should consider the extreme cases to determine the most limited
> > (smallest) max_adj value:
> >
> > Case 1 - high frequency
> > ~~~~~~~~~~~~~~~~~~~~~~~
> >
> > With a nominal 1 ns period, we have the nominal tuning word 0x10000.
> > The smallest is 0x1 for a difference of 0xFFFF. This corresponds to
> > an adjustment of 0xFFFF/0x10000 = .9999847412109375 or 999984741 ppb.
> >
> > Case 2 - low frequency
> > ~~~~~~~~~~~~~~~~~~~~~~
> >
> > With a nominal 255 ns period, the nominal word is 0xFF0000, the
> > largest 0xFFFFFF, and the difference is 0xFFFF. This corresponds to
> > and adjustment of 0xFFFF/0xFF0000 = .0039215087890625 or 3921508 ppb.
> >
> > Since 3921508 ppb is a huge adjustment, you can simply use that as a
> > safe maximum, ignoring the actual input clock.
> >
> > Thanks,
> > Richard
> >
> >
>
> Regards,
> Andrei
>
Best regards,
Rafal Ozieblo | Firmware System Engineer,
phone nbr.: +48 32 5085469
www.cadence.com
^ permalink raw reply
* [RESEND-PATCH] ARM: EXYNOS: remove smp hook from machine descriptor
From: pankaj.dubey @ 2016-12-09 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161208173349.GA8522@kozik-lap>
Hi Krzysztof,
On Thursday 08 December 2016 11:03 PM, Krzysztof Kozlowski wrote:
> On Thu, Dec 08, 2016 at 08:32:15AM +0530, Pankaj Dubey wrote:
>> Use CPU_METHOD_OF_DECLARE() for smp_ops instead of using it
>> via machine descriptor.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> ---
>>
>> Resending as I missed to include samsung mailing list.
>>
>> arch/arm/boot/dts/exynos3250.dtsi | 1 +
>> arch/arm/boot/dts/exynos4210.dtsi | 1 +
>> arch/arm/boot/dts/exynos4212.dtsi | 1 +
>> arch/arm/boot/dts/exynos4412.dtsi | 1 +
>> arch/arm/boot/dts/exynos5250.dtsi | 1 +
>> arch/arm/boot/dts/exynos5260.dtsi | 1 +
>> arch/arm/boot/dts/exynos5410.dtsi | 1 +
>> arch/arm/boot/dts/exynos5420-cpus.dtsi | 1 +
>> arch/arm/boot/dts/exynos5422-cpus.dtsi | 1 +
>> arch/arm/boot/dts/exynos5440.dtsi | 1 +
>> arch/arm/mach-exynos/common.h | 2 --
>> arch/arm/mach-exynos/exynos.c | 1 -
>> arch/arm/mach-exynos/platsmp.c | 2 ++
>> 13 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>> index ba17ee1..f28f669 100644
>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -53,6 +53,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at 0 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
>> index 7f3a18c..6dfd98d 100644
>> --- a/arch/arm/boot/dts/exynos4210.dtsi
>> +++ b/arch/arm/boot/dts/exynos4210.dtsi
>> @@ -35,6 +35,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at 900 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
>> index 5389011..3e8982e 100644
>> --- a/arch/arm/boot/dts/exynos4212.dtsi
>> +++ b/arch/arm/boot/dts/exynos4212.dtsi
>> @@ -25,6 +25,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at A00 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
>> index 40beede..faf2fb8 100644
>> --- a/arch/arm/boot/dts/exynos4412.dtsi
>> +++ b/arch/arm/boot/dts/exynos4412.dtsi
>> @@ -25,6 +25,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at A00 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
>> index b6d7444..580897c 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -52,6 +52,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at 0 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
>> index 5818718..1af6e76 100644
>> --- a/arch/arm/boot/dts/exynos5260.dtsi
>> +++ b/arch/arm/boot/dts/exynos5260.dtsi
>> @@ -32,6 +32,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu at 0 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
>> index 2b6adaf..b092cdc 100644
>> --- a/arch/arm/boot/dts/exynos5410.dtsi
>> +++ b/arch/arm/boot/dts/exynos5410.dtsi
>> @@ -33,6 +33,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at 0 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
>> index 5c052d7..a587704 100644
>> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
>> @@ -24,6 +24,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at 0 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
>> index bf3c6f1..7fcdfd0 100644
>> --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
>> +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
>> @@ -23,6 +23,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu0: cpu at 100 {
>> device_type = "cpu";
>> diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
>> index 2a2e570..0a958e8 100644
>> --- a/arch/arm/boot/dts/exynos5440.dtsi
>> +++ b/arch/arm/boot/dts/exynos5440.dtsi
>> @@ -50,6 +50,7 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + enable-method = "samsung,exynos-smp";
>>
>> cpu at 0 {
>> device_type = "cpu";
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index fb12d11..051e1ab 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -143,8 +143,6 @@ static inline void exynos_pm_init(void) {}
>> extern void exynos_cpu_resume(void);
>> extern void exynos_cpu_resume_ns(void);
>>
>> -extern const struct smp_operations exynos_smp_ops;
>> -
>> extern void exynos_cpu_power_down(int cpu);
>> extern void exynos_cpu_power_up(int cpu);
>> extern int exynos_cpu_power_state(int cpu);
>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>> index fa08ef9..f0a766e 100644
>> --- a/arch/arm/mach-exynos/exynos.c
>> +++ b/arch/arm/mach-exynos/exynos.c
>> @@ -211,7 +211,6 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
>> /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
>> .l2c_aux_val = 0x3c400001,
>> .l2c_aux_mask = 0xc20fffff,
>> - .smp = smp_ops(exynos_smp_ops),
>> .map_io = exynos_init_io,
>> .init_early = exynos_firmware_init,
>> .init_irq = exynos_init_irq,
>> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
>> index 94405c7..43eec10 100644
>> --- a/arch/arm/mach-exynos/platsmp.c
>> +++ b/arch/arm/mach-exynos/platsmp.c
>> @@ -474,3 +474,5 @@ const struct smp_operations exynos_smp_ops __initconst = {
>> .cpu_die = exynos_cpu_die,
>> #endif
>> };
>> +
>> +CPU_METHOD_OF_DECLARE(exynos_smp, "samsung,exynos-smp", &exynos_smp_ops);
>
> Three issues:
> 1. This has to be documented. Checkpatch did not complain about it?
No it didn't.
> 2. I think this breaks the ABI with existing DTBs because now the
> enable-method of cpus becomes mandatory. But the
> Documentation/devicetree/bindings/arm/cpus.txt is saying that:
> "On ARM 32-bit systems this property is optional and can be one of"
>
I am not very sure that this is an ABI break, as other platforms (e.g
hisilicon,hip01-smp) also adopted this as some later stage and they also
removed smp hook support from their machine files when they adopted to
this enable-method in DTS files.
If we want to keep older DTBs keep working with new Kernel image, then I
need to drop patch from mach-exynos and keep smp_ops hook in machine
descriptor as it is to keep supporting older DTBs. I can see some
platforms have adopted this way as well.
Surely I will add new bindings details in
Documentation/devicetree/bindings/arm/cpus.txt file. I am not sure why
checkpatch did not complain about this?
> 3. Please split DTS changes to separate patches. This is, by the way,
> connected with #2 above: if there was no ABI break, then the DTS
> could go to separate branch easily.
>
Since I am not sure if this will considered as ABI break or not, I just
looked how this was handled in other platforms, I can see some platforms
have clubbed DTS change along with mach files, and some have done in
separate patch as well. So I will look for suggestion from you for this
how we can go for exynos platform?
Thanks,
Pankaj Dubey
> Best regards,
> Krzysztof
>
>
>
^ permalink raw reply
* [PATCH v4 6/7] IIO: add STM32 timer trigger driver
From: Lee Jones @ 2016-12-09 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5dcec09c-8b4b-4cc2-ce3f-fde86366ec05@linaro.org>
On Wed, 07 Dec 2016, Daniel Thompson wrote:
> On 07/12/16 11:00, Benjamin Gaignard wrote:
> > 2016-12-07 11:50 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> > > On Tue, 06 Dec 2016, Benjamin Gaignard wrote:
> > >
> > > > [snip]
> > > > > > +
> > > > > > +static const char * const triggers0[] = {
> > > > > > + TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers1[] = {
> > > > > > + TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers2[] = {
> > > > > > + TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers3[] = {
> > > > > > + TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers4[] = {
> > > > > > + TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers5[] = {
> > > > > > + TIM6_TRGO, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers6[] = {
> > > > > > + TIM7_TRGO, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers7[] = {
> > > > > > + TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers8[] = {
> > > > > > + TIM9_TRGO, TIM9_CH1, TIM9_CH2, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const triggers9[] = {
> > > > > > + TIM12_TRGO, TIM12_CH1, TIM12_CH2, NULL,
> > > > > > +};
> > > > > > +
> > > > > > +static const void *triggers_table[] = {
> > > > > > + triggers0,
> > > > > > + triggers1,
> > > > > > + triggers2,
> > > > > > + triggers3,
> > > > > > + triggers4,
> > > > > > + triggers5,
> > > > > > + triggers6,
> > > > > > + triggers7,
> > > > > > + triggers8,
> > > > > > + triggers9,
> > > > > > +};
> > > > >
> > > > > What about:
> > > > >
> > > > > static const char * const triggers[][] = {
> > > > > { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4, NULL },
> > > > > { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4, NULL },
> > > > > { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4, NULL },
> > > > > { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4, NULL },
> > > > > { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4, NULL },
> > > > > { TIM6_TRGO, NULL },
> > > > > { TIM7_TRGO, NULL },
> > > > > { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4, NULL },
> > > > > { TIM9_TRGO, TIM9_CH1, TIM9_CH2, NULL },
> > > > > { TIM12_TRGO, TIM12_CH1, TIM12_CH2, NULL }
> > > > > };
> > > >
> > > > I can't because the second dimension of the array isn't fix.
> > > > I could have between 2 and 6 elements per row... to create a dual dimension
> > > > array I would have to add NULL entries like that:
> > > >
> > > > #define MAX_TRIGGERS 6
> > > >
> > > > static const void *triggers_table[][MAX_TRIGGERS] = {
> > > > { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4, NULL,},
> > > > { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4, NULL,},
> > > > { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4, NULL,},
> > > > { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4, NULL,},
> > > > { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4, NULL,},
> > > > { TIM6_TRGO, NULL, NULL, NULL, NULL, NULL,},
> > > > { TIM7_TRGO, NULL, NULL, NULL, NULL, NULL,},
> > > > { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4, NULL,},
> > > > { TIM9_TRGO, TIM9_CH1, TIM9_CH2, NULL, NULL, NULL,},
> > > > { TIM12_TRGO, TIM12_CH1, TIM12_CH2, NULL, NULL, NULL,},
> > > > };
> > >
> > > It was just an idea, not a tested implementation.
> > >
> > > I don't understand why you have to pad with NULLs, but either way, it
> > > looks much better than before and saves lots of lines of code.
> >
> > I have tested it this morning and it works fine so I will include it in v5.
> > I use NULL as limit when iterate in the table and for table padding too.
>
> If the initializer is shorter than the array then the array will be
> implicitly zero/NULL padded. I don't think there is any need to type out all
> the NULLs (not even at -Wall).
+1. My point precisely.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH RFC] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
From: Maxime Ripard @ 2016-12-09 8:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7603150.D9x404uVey@avalon>
Moi,
On Wed, Dec 07, 2016 at 11:48:55AM +0200, Laurent Pinchart wrote:
> On Wednesday 07 Dec 2016 10:26:25 Chen-Yu Tsai wrote:
> > On Wed, Dec 7, 2016 at 1:29 AM, Maxime Ripard wrote:
> > > On Thu, Nov 24, 2016 at 07:22:31PM +0800, Chen-Yu Tsai wrote:
> > >> The panels shipped with Allwinner devices are very "generic", i.e.
> > >> they do not have model numbers or reliable sources of information
> > >> for the timings (that we know of) other than the fex files shipped
> > >> on them. The dot clock frequency provided in the fex files have all
> > >> been rounded to the nearest MHz, as that is the unit used in them.
> > >>
> > >> We were using the simple panel "urt,umsh-8596md-t" as a substitute
> > >> for the A13 Q8 tablets in the absence of a specific model for what
> > >> may be many different but otherwise timing compatible panels. This
> > >> was usable without any visual artifacts or side effects, until the
> > >> dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> > >> rgb: Validate the clock rate").
> > >>
> > >> The reason this check fails is because the dotclock frequency for
> > >> this model is 33.26 MHz, which is not achievable with our dot clock
> > >> hardware, and the rate returned by clk_round_rate deviates slightly,
> > >> causing the driver to reject the display mode.
> > >>
> > >> The LCD panels have some tolerance on the dot clock frequency, even
> > >> if it's not specified in their datasheets.
> > >>
> > >> This patch adds a 5% tolerence to the dot clock check.
> > >
> > > As we discussed already, I really believe this is just as arbitrary as
> > > the current behaviour.
> >
> > Yes. I agree. This patch is mainly to give something that works for
> > people who don't care about the details, and to get some feedback
> > from people that do.
> >
> > > Some panels require an exact frequency,
>
> There's no such thing as an exact frequency, there will always be some
> tolerance (and if your display controller can really generate an exact
> frequency I'd be very interested in that hardware :-)).
>
> This is something that has been bugging me for some time now. The problem has
> been mostly ignored, or worked around in different ways by different drivers.
> I'm afraid I have no generic solution available, but I think we should try to
> agree on a common behaviour.
>
> I don't believe it would be reasonable to request each panel to report a
> tolerance, as the value is most of the time not available from the
> documentation (when documentation is available). Worse, I'm pretty sure that
> most panels documented as fixed timing can actually accept a wide range of
> timings. The timings reported in the datasheet are just the nominal values.
>
> Panels that don't support multiple resolutions obviously require fixed active
> h/v values. Even if they can tolerate some departure from the nominal timings
> for the sync and porches lengths, it might not be very useful to support that
> as I don't expect the display controllers and encoders to be a limiting factor
> by not supporting the particular timings that a panel considers as nominal. On
> the other hand, departing from the nominal pixel clock frequency is needed as
> we can't achieve an exact match, and even possibly to have some control over
> the frame rate (although that might also require changing the sync and porches
> timings). Without specific information about panel tolerance, do we have any
> option other than picking an arbitrary value ?
If you consider only panels, yes, chances are the EE picked a panel
that has a decent chance to work (especially since most of the boards
we support are consumer electronics products, and people like to have
a panel that works on their tablet).
However, bridges are a different story, and provide on some SoCs modes
that are way out of reach for our pixel clock, which is why we had
that test in the first place.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [RFC PATCH net-next v3 1/2] macb: Add 1588 support in Cadence GEM.
From: Richard Cochran @ 2016-12-09 8:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFcVECJutEu2=POtAU=jX6E3-ZHsLXpOMMw+UJ0hcQgZ0n4ZVA@mail.gmail.com>
On Fri, Dec 09, 2016 at 11:07:23AM +0530, Harini Katakam wrote:
> I'm afraid I don't get why we are choosing the most limited max adj..
> Sorry if I'm missing something - could you please help me understand?
This max_adj is only important when the local clock offset is large
and user space chooses not to step the time value. In that case, user
space will want to run the clock as fast (or as slow) as possible in
order to catch up with the remote clock.
The driver must provide a max_adj that is always safe for user space
to apply via the clock_adjtime() system call.
HTH,
Richard
^ permalink raw reply
* [PATCH v5 1/7] MFD: add bindings for STM32 General Purpose Timer driver
From: Lee Jones @ 2016-12-09 8:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481199650-22484-2-git-send-email-benjamin.gaignard@st.com>
Sorry to do this Ben. Not much to do now though!
> Add bindings information for STM32 General Purpose Timer
>
> version 2:
> - rename stm32-mfd-timer to stm32-gptimer
> - only keep one compatible string
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../bindings/mfd/stm32-general-purpose-timer.txt | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
> new file mode 100644
> index 0000000..ce67755
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
> @@ -0,0 +1,39 @@
> +STM32 General Purpose Timer driver bindings
This is a great place to describe what we're *actually* trying to
achieve with this driver, and the worst place to use the term "general
purpose", since this IP is so much more than that.
"STM32 Timers
This IP provides 3 types of timer along with PWM functionality.
[...]"
... then go on to explain what the 3 types are and how they can be
used.
> +Required parameters:
> +- compatible: must be "st,stm32-gptimer"
I vehemently disagree that this entire IP is a GP Timer. It contains
GP timers, sure, but it also contains Advanced and Basic timers.
IMHO this compatible should be "st,stm32-timers".
And the file name of both this and the *.c file should reflect that
too.
Remainder looks nice.
> +- reg: Physical base address and length of the controller's
> + registers.
> +- clock-names: Set to "clk_int".
> +- clocks: Phandle to the clock used by the timer module.
> + For Clk properties, please refer to ../clock/clock-bindings.txt
> +
> +Optional parameters:
> +- resets: Phandle to the parent reset controller.
> + See ../reset/st,stm32-rcc.txt
> +
> +Optional subnodes:
> +- pwm: See ../pwm/pwm-stm32.txt
> +- timer: See ../iio/timer/stm32-timer-trigger.txt
> +
> +Example:
> + timers at 40010000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-gptimer";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm at 0 {
Out of interest, do you use the "@0", "@1" for anything now?
> + compatible = "st,stm32-pwm";
> + pinctrl-0 = <&pwm1_pins>;
> + pinctrl-names = "default";
> + };
> +
> + timer at 0 {
> + compatible = "st,stm32-timer-trigger";
> + reg = <0>;
> + };
> + };
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH RFC] drm/sun4i: rgb: Add 5% tolerance to dot clock frequency check
From: Maxime Ripard @ 2016-12-09 8:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87oa0nbldb.fsf@eliezer.anholt.net>
Hi Eric,
On Wed, Dec 07, 2016 at 11:16:32AM -0800, Eric Anholt wrote:
> Maxime Ripard <maxime.ripard@free-electrons.com> writes:
>
> > [ Unknown signature status ]
> > On Thu, Nov 24, 2016 at 07:22:31PM +0800, Chen-Yu Tsai wrote:
> >> The panels shipped with Allwinner devices are very "generic", i.e.
> >> they do not have model numbers or reliable sources of information
> >> for the timings (that we know of) other than the fex files shipped
> >> on them. The dot clock frequency provided in the fex files have all
> >> been rounded to the nearest MHz, as that is the unit used in them.
> >>
> >> We were using the simple panel "urt,umsh-8596md-t" as a substitute
> >> for the A13 Q8 tablets in the absence of a specific model for what
> >> may be many different but otherwise timing compatible panels. This
> >> was usable without any visual artifacts or side effects, until the
> >> dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> >> rgb: Validate the clock rate").
> >>
> >> The reason this check fails is because the dotclock frequency for
> >> this model is 33.26 MHz, which is not achievable with our dot clock
> >> hardware, and the rate returned by clk_round_rate deviates slightly,
> >> causing the driver to reject the display mode.
> >>
> >> The LCD panels have some tolerance on the dot clock frequency, even
> >> if it's not specified in their datasheets.
> >>
> >> This patch adds a 5% tolerence to the dot clock check.
> >
> > As we discussed already, I really believe this is just as arbitrary as
> > the current behaviour.
> >
> > Some panels require an exact frequency, some have a minimal frequency
> > but no maximum, some have a maximum frequency but no minimal, and I
> > guess most of them deviates by how much exactly they can take (and
> > possibly can take more easily a higher frequency, but are less
> > tolerant if you take a frequency lower than the nominal.
> >
> > And we cannot remove that check entirely, since some bridges will
> > report out of range frequencies for higher modes that we know we
> > cannot reach.
> >
> > We could just try to see if the screen pixel clock frequency is out of
> > the pixel clock range we can generate, but then we will loop back on
> > how much out of range is it exactly, and is it within the screen
> > tolerancy.
> >
> > We have an API to deal with the panel tolerancies in the DRM panel
> > framework, we can (and should) use it.
> >
> > I'm not sure how others usually deal with this though. I think I
> > remember Eric telling me that for the RPi they just adjusted the
> > timings a bit, but they only really had a single panel to deal with.
>
> For RPi, you just adjust the pixel clock of the panel's mode to be
> whatever the platform can support, and expand the blanking intervals to
> get the refresh rate back to desired. This is nothing like what the
> datasheet says, but it's not important what the datasheet says, it's
> important what makes the product work.
Ok, that was what I was recalling from our previous discussion on that
topic.
> Our clock driver looks for the best matching clock that's not over the
> target rate. This is somewhat unfortunate, as you end up slightly
> inflating your requested clocks so that a possible clock lands under
> that. I'd rather we chose the closest matching clock, but then people
> get worried about what if selected clock rate is 1% higher than expected
> (the answer is "nothing").
Whose feedback was that? Users?
> I think this patch is a fine solution, and the alternative would be to
> just drop the mode high/low check and say that if you're pairing a panel
> with some display hardware, it's up to you to make sure that the panel's
> mode actually scans out successfully. Then, since compatible strings
> are cheap, you can use a new one if necessary to attach better modes to
> the panel for a particular clock driver by adjusting your timings to get
> closer to the refresh rates you want.
That's one expectation we can have for panels, but we had that test
for bridges. On some SoCs, the pixel clock is pretty limited and can
only reach around 720p60 or 1080p30. If you have a monitor attached
that will return EDIDs, chances are that it will report modes that you
know have no chance to work.
This check was here to rule out those cases and prevent them from
showing up in the list of modes.
So we basically have two different things to care about. We want to be
tolerant so that most panels just work, but not too tolerant to rule
out modes that we know we can't reach. We're only covering the latter,
and we should take into account the former, but we definitely need
some kind of check.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v18 03/15] clocksource/drivers/arm_arch_timer: Improve printk relevant code
From: Fu Wei @ 2016-12-09 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481231430.5946.34.camel@perches.com>
Hi Joe,
On 9 December 2016 at 05:10, Joe Perches <joe@perches.com> wrote:
> On Fri, 2016-12-09 at 01:33 +0800, fu.wei at linaro.org wrote:
>> From: Fu Wei <fu.wei@linaro.org>
>>
>> This patch defines pr_fmt(fmt) for all pr_* functions,
>> then the pr_* doesn't need to add "arch_timer:" everytime.
>
> trivia:
>
>> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> []
>> @@ -966,7 +967,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
>>
>> ret = -EINVAL;
>> if (!irq) {
>> - pr_err("arch_timer: Frame missing %s irq",
>> + pr_err("Frame missing %s irq",
>> arch_timer_mem_use_virtual ? "virt" : "phys");
>> goto out;
>> }
>
> Missing terminating newline
>
> pr_err("Frame missing %s irq\n",
yes, you are right , will fix it. :-)
Thanks
--
Best regards,
Fu Wei
Software Engineer
Red Hat
^ permalink raw reply
* [PATCH v3 -next 2/2] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Maxime Ripard @ 2016-12-09 8:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161202150513.34691-2-icenowy@aosc.xyz>
On Fri, Dec 02, 2016 at 11:05:13PM +0800, Icenowy Zheng wrote:
> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC and a
> SDIO Wi-Fi chip by Allwinner (XR819).
>
> Add a device tree file for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 2/2] arm: dts: sun8i: reuse the uart1 node of iNet D978 rev2 board
From: Maxime Ripard @ 2016-12-09 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205184745.lfW8ji5w@smtp1m.mail.yandex.net>
On Mon, Dec 05, 2016 at 05:03:35PM +0800, Icenowy Zheng wrote:
>
> 2016?12?5? 16:50? Maxime Ripard <maxime.ripard@free-electrons.com>???
> >
> > On Fri, Dec 02, 2016 at 11:19:13PM +0800, Icenowy Zheng wrote:
> > > As a uart1 node is added into sun8i-reference-design-tablet.dtsi, simply
> > > use it in iNet D978 rev2 device tree.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >
> > I'd like to see more consolidation before that change is needed. If we
> > find more boards using that, it will make sense, but for a single
> > board it's not worth it.
>
> At least 2~3 Q8 A33 tablets in #linux-sunxi are found to have
> rtl8703as, which contains UART bluetooth. (including mine)
Still, I'm not fond of creating a default on such a low count sample
of (out-of-tree) DTs. Support and enable the bluetooth on more boards,
and then consolidate.
> In fact, what I want to do is to get the node ready-to-be-okay in Q8
> dts, so it can be enabled by either u-boot command or (theortically)
> Hans de Goede's q8-hardwaremgr, just like what is done at
> touchscreen node.
If your plan is to enable all the combinations possible accross the Q8
tablets and let the bootloader/user figure it all out, then it's not
going to happen, sorry.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] ARM: dts: sun8i-q8-common: enable bluetooth on SDIO Wi-Fi
From: Maxime Ripard @ 2016-12-09 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206080838.7523-1-icenowy@aosc.xyz>
On Tue, Dec 06, 2016 at 04:08:38PM +0800, Icenowy Zheng wrote:
> Some SDIO Wi-Fi chips (such as RTL8703AS) have a UART bluetooth, which
> has a dedicated enable pin (PL8 in the reference design).
>
> Enable the pin in the same way as the WLAN enable pins.
>
> Tested on an A33 Q8 tablet with RTL8703AS.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>
> This patch should be coupled with the uart1 node patch I send before:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-December/471997.html
>
> For RTL8703AS, the rtl8723bs bluetooth code is used, which can be retrieve from:
> https://github.com/lwfinger/rtl8723bs_bt
>
> arch/arm/boot/dts/sun8i-q8-common.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi
> index c676940..4aeb5bb 100644
> --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
> +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
> @@ -88,7 +88,7 @@
>
> &r_pio {
> wifi_pwrseq_pin_q8: wifi_pwrseq_pin at 0 {
> - pins = "PL6", "PL7", "PL11";
> + pins = "PL6", "PL7", "PL8", "PL11";
> function = "gpio_in";
> bias-pull-up;
> };
There's several things wrong here. The first one is that you rely
solely on the pinctrl state to maintain a reset line. This is very
fragile (especially since the GPIO pinctrl state are likely to go away
at some point), but it also means that if your driver wants to recover
from that situation at some point, it won't work.
The other one is that the bluetooth and wifi chips are two devices in
linux, and you assign that pin to the wrong device (wifi).
rfkill-gpio is made just for that, so please use it.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 3/3] clk: keystone: Add sci-clk driver support
From: Tero Kristo @ 2016-12-09 8:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161208211044.GI5423@codeaurora.org>
On 08/12/16 23:10, Stephen Boyd wrote:
> On 12/08, Tero Kristo wrote:
>> On 08/12/16 02:13, Stephen Boyd wrote:
>>> On 10/21, Tero Kristo wrote:
>>>> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
>>>> new file mode 100644
>>>> index 0000000..f6af5bd
>>>> --- /dev/null
>>>> +++ b/drivers/clk/keystone/sci-clk.c
>>
>>>
>>>> +
>>>> + handle = devm_ti_sci_get_handle(dev);
>>>> + if (IS_ERR(handle))
>>>> + return PTR_ERR(handle);
>>>> +
>>>> + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
>>>> + if (!provider)
>>>> + return -ENOMEM;
>>>> +
>>>> + provider->clocks = data;
>>>> +
>>>> + provider->sci = handle;
>>>> + provider->ops = &handle->ops.clk_ops;
>>>> + provider->dev = dev;
>>>> +
>>>> + ti_sci_init_clocks(provider);
>>>
>>> And if this fails?
>>
>> Yea this is kind of controversial. ti_sci_init_clocks() can fail if
>> any of the clocks registered will fail. I decided to have it this
>> way so that at least some clocks might work in failure cause, and
>> you might have a booting device instead of total lock-up.
>>
>> Obviously it could be done so that if any clock fails, we would
>> de-register all clocks at that point, but personally I think this is
>> a worse option.
>>
>> ti_sci_init_clocks could probably be modified to continue
>> registering clocks when a single clock fails though. Currently it
>> aborts at first failure.
>>
>
> That sounds like a better approach if we don't care about
> failures to register a clock. Returning a value from a function
> and not using it isn't really a great design.
>
> I worry that if we start returning errors from clk_hw_register()
> that something will go wrong though, so really I don't know why
> we want to ignore errors at all. Just for debugging a boot hang?
> Can't we use early console to at least see that this driver is
> failing to probe and debug that way?
Early console can be used to debug that, but it is kind of annoying to
recompile most of the kernel when you suddenly need to use it.
How about modifying the ti_sci_init_clocks func to print an error for
each failed clock?
If you insist on aborting the probe though if a single clock fails, I
can do that also.
-Tero
^ permalink raw reply
* [RESEND PATCH v2 0/7] drm/vc4: VEC (SDTV) output support
From: Boris Brezillon @ 2016-12-09 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <68783643.33021.1481268157922@email.1und1.de>
On Fri, 9 Dec 2016 08:22:37 +0100 (CET)
Stefan Wahren <stefan.wahren@i2se.com> wrote:
> Hi,
>
> > Boris Brezillon <boris.brezillon@free-electrons.com> hat am 2. Dezember 2016 um 14:48 geschrieben:
> >
> >
> > Sorry for the noise, but I forgot to Cc the DT maintainers.
> >
> > Here is the 2nd version of the VC4/VEC series.
> >
> > We still miss the two clock patches mentioned by Eric in the first
> > version to make the encoder work no matter the setting applied by the
> > bootloader.
>
> are there any advices to test this feature?
Apply these patches [1][2][3][4] in addition to this series, and you
should see the SDTV output when running modetest (this is what I used
to test/debug the driver).
This is the command I use to test the SDTV output in NTSC mode
modetest -s 39:720x480
>
> Is it possible to use an old Raspberry Pi B (256 MB RAM) for this?
I did most of my test on a RPi-2, but IIRC, Eric tested it on a RPi
(don't know which model).
>
> Thanks
>
> Stefan
[1]https://patchwork.kernel.org/patch/9442127/
[2]https://patchwork.kernel.org/patch/9456911/
[3]https://patchwork.kernel.org/patch/9456909/
[4]https://patchwork.kernel.org/patch/9456731/
^ permalink raw reply
* [RESEND PATCH v2 0/7] drm/vc4: VEC (SDTV) output support
From: Stefan Wahren @ 2016-12-09 7:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480686493-4813-1-git-send-email-boris.brezillon@free-electrons.com>
Hi,
> Boris Brezillon <boris.brezillon@free-electrons.com> hat am 2. Dezember 2016 um 14:48 geschrieben:
>
>
> Sorry for the noise, but I forgot to Cc the DT maintainers.
>
> Here is the 2nd version of the VC4/VEC series.
>
> We still miss the two clock patches mentioned by Eric in the first
> version to make the encoder work no matter the setting applied by the
> bootloader.
are there any advices to test this feature?
Is it possible to use an old Raspberry Pi B (256 MB RAM) for this?
Thanks
Stefan
^ permalink raw reply
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