* [PATCH linux v1 4/4] arm: dts: Add dt-binding to support seven segment display on zaius
From: Jaghathiswari Rankappagounder Natarajan @ 2016-12-14 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481702104-8617-1-git-send-email-jaghu@google.com>
Add clock, data and clear signal GPIO lines to control seven segment display on
zaius platform.
Signed-off-by: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
index 8ef4ece..ccb8147 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -43,6 +43,14 @@
gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>;
};
};
+
+ seven-seg-disp {
+ compatible = "seven-seg-gpio-dev";
+ refresh-interval-ms = "1000";
+ clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ clear-gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
+ };
};
&fmc {
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH linux v1 3/4] drivers: misc: Platform driver for seven segment display support
From: Jaghathiswari Rankappagounder Natarajan @ 2016-12-14 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481702104-8617-1-git-send-email-jaghu@google.com>
Platform device driver which provides an API for displaying on two
7-segment displays, and implements the required bit-banging.
The hardware assumed is 74HC164 wired to two 7-segment displays.
Signed-off-by: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
---
drivers/misc/Kconfig | 8 ++
drivers/misc/Makefile | 1 +
drivers/misc/seven_seg_gpio.c | 206 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 215 insertions(+)
create mode 100644 drivers/misc/seven_seg_gpio.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a21aec1..6508108 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -812,6 +812,14 @@ config PANEL_BOOT_MESSAGE
An empty message will only clear the display at driver init time. Any other
printf()-formatted message is valid with newline and escape codes.
+config SEVEN_SEGMENT_GPIO
+ tristate "Platform driver to update seven segment display"
+ depends on SEVEN_SEGMENT_DISPLAY
+ help
+ Platform device driver which provides an API for displaying on two
+ 7-segment displays, and implements the required bit-banging.
+ The hardware assumed is 74HC164 wired to two 7-segment displays.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index c2defbd..d9c0d20 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -58,3 +58,4 @@ obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
obj-$(CONFIG_SEVEN_SEGMENT_DISPLAY) += seven_seg_disp.o
obj-$(CONFIG_PANEL) += panel.o
+obj-$(CONFIG_SEVEN_SEGMENT_GPIO) += seven_seg_gpio.o
diff --git a/drivers/misc/seven_seg_gpio.c b/drivers/misc/seven_seg_gpio.c
new file mode 100644
index 0000000..3dcb903
--- /dev/null
+++ b/drivers/misc/seven_seg_gpio.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+#include <linux/jiffies.h>
+#include <linux/sizes.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+#include <linux/mutex.h>
+#include <linux/of_platform.h>
+#include <linux/gpio/consumer.h>
+
+#include "seven_seg_disp.h"
+
+#define DELAY_INTVL_US 1
+
+#define CLOCK_GPIO_NAME "clock"
+#define DATA_GPIO_NAME "data"
+#define CLEAR_GPIO_NAME "clear"
+
+struct seven_seg_gpio_info {
+ u16 curr_disp_value;
+ u16 refresh_interval;
+ struct timer_list update_timer;
+ struct gpio_desc *clock_gpio;
+ struct gpio_desc *data_gpio;
+ struct gpio_desc *clear_gpio;
+};
+
+static void update_seven_seg_gpio_data(struct device *dev, u16 data)
+{
+ struct platform_device *pdev;
+ struct seven_seg_gpio_info *gpio_info;
+
+ pdev = container_of(dev, struct platform_device, dev);
+ if (pdev == NULL) {
+ pr_err("invalid NULL platform_device\n");
+ return;
+ }
+
+ gpio_info = platform_get_drvdata(pdev);
+ if (gpio_info == NULL) {
+ pr_err("invalid NULL gpio_info\n");
+ return;
+ }
+
+ gpio_info->curr_disp_value = data;
+}
+
+static void clear_seven_seg_gpio_data(struct device *dev, u16 data)
+{
+ struct platform_device *pdev;
+ struct seven_seg_gpio_info *gpio_info;
+
+ pdev = container_of(dev, struct platform_device, dev);
+ if (pdev == NULL) {
+ pr_err("invalid NULL platform_device\n");
+ return;
+ }
+
+ gpio_info = platform_get_drvdata(pdev);
+ if (gpio_info == NULL) {
+ pr_err("invalid NULL gpio_info\n");
+ return;
+ }
+
+ gpio_info->curr_disp_value = 0;
+}
+
+static void send_seven_seg_gpio_data(u16 disp_data,
+ struct seven_seg_gpio_info *gpio_info)
+{
+ int i;
+
+ gpiod_set_value(gpio_info->clear_gpio, 0);
+ udelay(DELAY_INTVL_US);
+ gpiod_set_value(gpio_info->clear_gpio, 1);
+ udelay(DELAY_INTVL_US);
+
+ for (i = 0; i < 16; i++) {
+ if (disp_data & 0x01)
+ gpiod_set_value(gpio_info->data_gpio, 1);
+ else
+ gpiod_set_value(gpio_info->data_gpio, 0);
+
+ udelay(DELAY_INTVL_US);
+
+ gpiod_set_value(gpio_info->clock_gpio, 0);
+ udelay(DELAY_INTVL_US);
+ gpiod_set_value(gpio_info->clock_gpio, 1);
+ udelay(DELAY_INTVL_US);
+
+ disp_data >>= 1;
+ }
+}
+
+static void disp_refresh_timer_handler(unsigned long data)
+{
+ u16 disp_data;
+ struct seven_seg_gpio_info *gpio_info =
+ (struct seven_seg_gpio_info *)data;
+ disp_data = gpio_info->curr_disp_value;
+
+ send_seven_seg_gpio_data(disp_data, gpio_info);
+ mod_timer(&gpio_info->update_timer,
+ jiffies + msecs_to_jiffies(gpio_info->refresh_interval));
+}
+
+static const struct of_device_id of_seven_seg_gpio_match[] = {
+ { .compatible = "seven-seg-gpio-dev" },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_seven_seg_gpio_match);
+
+static int seven_seg_gpio_probe(struct platform_device *pdev)
+{
+ u16 interval;
+ int result;
+ struct seven_seg_gpio_info *gpio_info;
+ struct device *dev = &pdev->dev;
+ struct seven_seg_disp_dev *disp_dev;
+
+ gpio_info = devm_kzalloc(dev,
+ sizeof(struct seven_seg_gpio_info),
+ GFP_KERNEL);
+ if (gpio_info == NULL)
+ return -ENOMEM;
+
+ /* Requesting the clock gpio */
+ gpio_info->clock_gpio = devm_gpiod_get(dev, CLOCK_GPIO_NAME,
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(gpio_info->clock_gpio))
+ return PTR_ERR(gpio_info->clock_gpio);
+
+ /* Requesting the data gpio */
+ gpio_info->data_gpio = devm_gpiod_get(dev, DATA_GPIO_NAME,
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(gpio_info->data_gpio))
+ return PTR_ERR(gpio_info->data_gpio);
+
+ /* Requesting the clear gpio */
+ gpio_info->clear_gpio = devm_gpiod_get(dev, CLEAR_GPIO_NAME,
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(gpio_info->clear_gpio))
+ return PTR_ERR(gpio_info->clear_gpio);
+
+ result = of_property_read_u16(pdev->dev.of_node,
+ "refresh-interval-ms", &interval);
+ gpio_info->refresh_interval = result ? DEFAULT_REFRESH_INTERVAL_MS :
+ interval;
+
+ /* Start timer to update seven segment display every second */
+ setup_timer(&gpio_info->update_timer, disp_refresh_timer_handler,
+ (unsigned long)gpio_info);
+ result = mod_timer(&gpio_info->update_timer,
+ jiffies +
+ msecs_to_jiffies(gpio_info->refresh_interval));
+ if (result)
+ return result;
+
+ gpio_info->curr_disp_value = 0;
+
+ platform_set_drvdata(pdev, gpio_info);
+
+ disp_dev = devm_kzalloc(dev, sizeof(struct seven_seg_disp_dev),
+ GFP_KERNEL);
+ disp_dev->parent = *dev;
+ seven_seg_setup_cdev(disp_dev, &update_seven_seg_gpio_data);
+ return 0;
+}
+
+static int seven_seg_gpio_remove(struct platform_device *pdev)
+{
+ struct seven_seg_gpio_info *gpio_info = platform_get_drvdata(pdev);
+ struct seven_seg_disp_dev *disp_dev =
+ container_of(&pdev->dev,
+ struct seven_seg_disp_dev, parent);
+ seven_seg_rem_cdev(disp_dev);
+ del_timer_sync(&gpio_info->update_timer);
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+static struct platform_driver seven_seg_gpio_driver = {
+ .probe = seven_seg_gpio_probe,
+ .remove = seven_seg_gpio_remove,
+ .driver = {
+ .name = "seven-seg-gpio",
+ .of_match_table = of_seven_seg_gpio_match,
+ },
+};
+
+module_platform_driver(seven_seg_gpio_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
+MODULE_DESCRIPTION("Seven segment display driver using GPIO config");
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH linux v1 2/4] drivers: misc: Character device driver for seven segment display
From: Jaghathiswari Rankappagounder Natarajan @ 2016-12-14 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481702104-8617-1-git-send-email-jaghu@google.com>
Character device driver which implements the user-space
API for letting a user write to two 7-segment displays including
any conversion methods necessary to map the user input
to two 7-segment displays.
Signed-off-by: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
---
drivers/misc/Kconfig | 8 ++
drivers/misc/Makefile | 1 +
drivers/misc/seven_seg_disp.c | 197 ++++++++++++++++++++++++++++++++++++++++++
drivers/misc/seven_seg_disp.h | 34 ++++++++
4 files changed, 240 insertions(+)
create mode 100644 drivers/misc/seven_seg_disp.c
create mode 100644 drivers/misc/seven_seg_disp.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a216b46..a21aec1 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -791,6 +791,14 @@ config PANEL_CHANGE_MESSAGE
If you say 'Y' here, you'll be able to choose a message yourself. Otherwise,
say 'N' and keep the default message with the version.
+config SEVEN_SEGMENT_DISPLAY
+ tristate "Character driver for seven segment display support"
+ help
+ Character device driver which implements the user-space
+ API for letting a user write to two 7-segment displays including
+ any conversion methods necessary to map the user input
+ to two 7-segment displays.
+
config PANEL_BOOT_MESSAGE
depends on PANEL && PANEL_CHANGE_MESSAGE="y"
string "New initialization message"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b2fb6dbf..c2defbd 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -56,4 +56,5 @@ obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
+obj-$(CONFIG_SEVEN_SEGMENT_DISPLAY) += seven_seg_disp.o
obj-$(CONFIG_PANEL) += panel.o
diff --git a/drivers/misc/seven_seg_disp.c b/drivers/misc/seven_seg_disp.c
new file mode 100644
index 0000000..4daeac5
--- /dev/null
+++ b/drivers/misc/seven_seg_disp.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/kdev_t.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/ctype.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include "seven_seg_disp.h"
+
+#define LED_DOT 0x01
+
+/*
+ * 0 1 2 3 4 5 6 7 8 9 A B C D E F
+ * _ _ _ _ _ _ _ _ _ _ _ _
+ * | | | _| _| |_| |_ |_ | |_| |_| |_| |_ | _| |_ |_
+ * |_| | |_ _| | _| |_| | |_| | | | |_| |_ |_| |_ |
+ *
+ * data[7:1] = led[a:g]
+ */
+const u8 seven_seg_bits[] = {
+ 0xFC, 0x60, 0xDA, 0xF2, 0x66, 0xB6, 0xBE, 0xE0,
+ 0xFE, 0xF6, 0xEE, 0x3E, 0x9C, 0x7A, 0x9E, 0x8E
+ };
+
+/*
+ * 0 1 2 3 4 5 6 7 8 9 A B C D E F
+ * _ _ _ _ _
+ * | |_ |_| |_ _ _ _ _ _ _ _ |_ _| _| | |
+ * |_ |_ | | _| |_| |_| | |
+ *
+ * data[7:1] = led[a:g]
+ */
+const u8 special_seven_seg_bits[] = {
+ 0x00, 0x9C, 0x1E, 0xCE, 0x8E, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0xB6, 0x7A, 0x7A, 0xEC
+ };
+
+static dev_t seven_seg_devno;
+static struct class *seven_seg_disp_class;
+
+static int seven_seg_disp_open(struct inode *inode, struct file *filp)
+{
+ struct seven_seg_disp_dev *disp_dev;
+
+ disp_dev = container_of(inode->i_cdev,
+ struct seven_seg_disp_dev, cdev);
+ filp->private_data = disp_dev;
+ return 0;
+}
+
+static int seven_seg_disp_close(struct inode *inode, struct file *filp)
+{
+ filp->private_data = NULL;
+ return 0;
+}
+
+static ssize_t seven_seg_disp_read(struct file *filp, char __user *buf, size_t
+ len, loff_t *off)
+{
+ struct seven_seg_disp_dev *disp_dev = filp->private_data;
+
+ if (disp_dev->disp_data_valid)
+ return -EINVAL;
+
+ if (copy_to_user(buf, disp_dev->seven_seg_disp_data_array,
+ MAX_DISP_CHAR_SIZE) != 0) {
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static u16 convert_to_disp_data(char *buf)
+{
+ u8 low_display;
+ u8 high_display;
+ u16 led_value;
+
+ low_display = seven_seg_bits[hex_to_bin(buf[2])];
+
+ high_display = (buf[0] == '1') ?
+ special_seven_seg_bits[hex_to_bin(buf[1])] :
+ seven_seg_bits[hex_to_bin(buf[1])];
+
+ led_value = low_display | (high_display << 8);
+ if (buf[0] == '1')
+ led_value |= LED_DOT | (LED_DOT << 8);
+
+ return led_value;
+}
+
+static ssize_t seven_seg_disp_write(struct file *filp, const char __user *buf,
+ size_t len, loff_t *off)
+{
+ int length = len - 1;
+ int i;
+
+ struct seven_seg_disp_dev *disp_dev = filp->private_data;
+
+ if (length != MAX_DISP_CHAR_SIZE)
+ return -EINVAL;
+
+ if (copy_from_user(disp_dev->seven_seg_disp_data_array,
+ buf, length) != 0) {
+ return -EFAULT;
+ }
+
+ for (i = 0; i < MAX_DISP_CHAR_SIZE; i++) {
+ if (!isxdigit(disp_dev->seven_seg_disp_data_array[i]))
+ return -EINVAL;
+ }
+
+ disp_dev->current_seven_seg_disp_data = convert_to_disp_data(
+ disp_dev->seven_seg_disp_data_array);
+ disp_dev->disp_data_valid = true;
+ disp_dev->update_seven_seg_data(&disp_dev->parent,
+ disp_dev->current_seven_seg_disp_data);
+
+ return len;
+}
+
+static const struct file_operations seven_seg_disp_fops = {
+
+ .owner = THIS_MODULE,
+ .open = seven_seg_disp_open,
+ .release = seven_seg_disp_close,
+ .read = seven_seg_disp_read,
+ .write = seven_seg_disp_write
+};
+
+void seven_seg_rem_cdev(struct seven_seg_disp_dev *disp_dev)
+{
+ cdev_del(&disp_dev->cdev);
+ device_destroy(seven_seg_disp_class, seven_seg_devno);
+}
+
+int seven_seg_setup_cdev(struct seven_seg_disp_dev *disp_dev,
+ void (*update_disp_data)(struct device *, u16 data))
+{
+ struct device *dev;
+ int err;
+
+ dev = device_create(seven_seg_disp_class, &disp_dev->parent,
+ seven_seg_devno,
+ NULL, "seven_seg_disp_val");
+ if (dev == NULL)
+ return -1;
+ disp_dev->dev = dev;
+ disp_dev->update_seven_seg_data = update_disp_data;
+ disp_dev->disp_data_valid = false;
+
+ cdev_init(&disp_dev->cdev, &seven_seg_disp_fops);
+ err = cdev_add(&disp_dev->cdev, seven_seg_devno, 1);
+ if (err)
+ device_destroy(seven_seg_disp_class, seven_seg_devno);
+ return err;
+}
+
+static int __init seven_seg_disp_init(void)
+{
+ if (alloc_chrdev_region(&seven_seg_devno, 0, 1, "disp_state") < 0)
+ return -1;
+
+ seven_seg_disp_class = class_create(THIS_MODULE, "disp_state");
+ if (seven_seg_disp_class == NULL)
+ goto unreg_chrdev;
+
+unreg_chrdev:
+ unregister_chrdev_region(seven_seg_devno, 1);
+ return -1;
+}
+
+static void __exit seven_seg_disp_exit(void)
+{
+ class_destroy(seven_seg_disp_class);
+ unregister_chrdev_region(seven_seg_devno, 1);
+}
+
+module_init(seven_seg_disp_init);
+module_exit(seven_seg_disp_exit);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
+MODULE_DESCRIPTION("Seven segment display character driver");
diff --git a/drivers/misc/seven_seg_disp.h b/drivers/misc/seven_seg_disp.h
new file mode 100644
index 0000000..b0f93c5
--- /dev/null
+++ b/drivers/misc/seven_seg_disp.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef SEVEN_SEG_DISP_H
+#define SEVEN_SEG_DISP_H
+
+#include <linux/device.h>
+#include <linux/cdev.h>
+
+#define MAX_DISP_CHAR_SIZE 3
+
+#define DEFAULT_REFRESH_INTERVAL_MS 1000
+
+struct seven_seg_disp_dev {
+ bool disp_data_valid;
+ u16 current_seven_seg_disp_data;
+ char seven_seg_disp_data_array[MAX_DISP_CHAR_SIZE];
+ struct device parent;
+ struct device *dev;
+ struct cdev cdev;
+ void (*update_seven_seg_data)(struct device *, u16 data);
+};
+
+int seven_seg_setup_cdev(struct seven_seg_disp_dev *disp_dev,
+ void (*update_disp_data)(struct device *, u16 data));
+
+void seven_seg_rem_cdev(struct seven_seg_disp_dev *disp_dev);
+
+#endif
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH linux v1 1/4] Documentation: dt-bindings: Document bindings for seven segment display support
From: Jaghathiswari Rankappagounder Natarajan @ 2016-12-14 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481702104-8617-1-git-send-email-jaghu@google.com>
This binding provides interface for adding clock, data and clear signal GPIO
lines to control seven segment display.
Signed-off-by: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
---
.../devicetree/bindings/misc/seven-seg-gpio.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/seven-seg-gpio.txt
diff --git a/Documentation/devicetree/bindings/misc/seven-seg-gpio.txt b/Documentation/devicetree/bindings/misc/seven-seg-gpio.txt
new file mode 100644
index 0000000..9a4e255
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/seven-seg-gpio.txt
@@ -0,0 +1,27 @@
+This binding defines interface to add clock, data and clear GPIO lines required
+for seven segment display support.
+
+Required properties:
+- compatible : should be "seven-seg-gpio-dev".
+- clock-gpios : Should specify the GPIO pin connected to the Clock line on the
+ hardware.
+- data-gpios : Should specify the GPIO pin connected to Data line on the
+ hardware.
+- clear-gpios : Should specify the GPIO pin connected to Clear line on the
+ hardware.
+
+Optional properties:
+- refresh-interval-ms : The interval at which to refresh the display.
+ If this property is not present, the default value is 1000.
+
+Examples:
+
+#include <dt-bindings/gpio/gpio.h>
+
+seven-seg-disp {
+ compatible = "seven-seg-gpio-dev";
+ refresh-interval-ms = "1000";
+ clock-gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ data-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ clear-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+};
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH linux v1 0/4] Seven segment display support
From: Jaghathiswari Rankappagounder Natarajan @ 2016-12-14 7:55 UTC (permalink / raw)
To: linux-arm-kernel
This patchset includes:
Documentation for the binding which provides an interface for adding clock,
data and clear signal GPIO lines to control seven segment display.
The platform device driver provides an API for displaying on two 7-segment
displays, and implements the required bit-banging. The hardware assumed is
74HC164 wired to two 7-segment displays.
The character device driver implements the user-space API for letting a user
write to two 7-segment displays including any conversion methods necessary
to map the user input to two 7-segment displays.
Adding clock, data and clear signal GPIO lines in the devicetree to control
seven segment display on zaius platform.
The platform driver matches on the device tree node; the platform driver also
initializes the character device.
Tested that the seven segment display works properly by writing to the
character device file on a EVB AST2500 board which also has 74HC164 wired
to two 7-segment displays.
Jaghathiswari Rankappagounder Natarajan (4):
Documentation: dt-bindings: Document bindings for seven segment
display support
drivers: misc: Character device driver for seven segment display
drivers: misc: Platform driver for seven segment display support
arm: dts: Add dt-binding to support seven segment display on zaius
.../devicetree/bindings/misc/seven-seg-gpio.txt | 27 +++
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 8 +
drivers/misc/Kconfig | 16 ++
drivers/misc/Makefile | 2 +
drivers/misc/seven_seg_disp.c | 197 ++++++++++++++++++++
drivers/misc/seven_seg_disp.h | 34 ++++
drivers/misc/seven_seg_gpio.c | 206 +++++++++++++++++++++
7 files changed, 490 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/seven-seg-gpio.txt
create mode 100644 drivers/misc/seven_seg_disp.c
create mode 100644 drivers/misc/seven_seg_disp.h
create mode 100644 drivers/misc/seven_seg_gpio.c
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply
* [PATCH 5/5] Documentation: fsl-quadspi: Add fsl, ls1012a-qspi compatible string
From: Yao Yuan @ 2016-12-14 7:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_Jsq+jp_2m7D=Hv6TRa+1nQZhPis-0MPK5kOAWge_7RvN4Qg@mail.gmail.com>
On Thu, Dec 14, 2016 at 05:23:02PM +0800, Rob Herring wrote:
> On Mon, Dec 12, 2016 at 8:47 PM, Yao Yuan <yao.yuan@nxp.com> wrote:
> > On Thu, Dec 13, 2016 at 05:23:02PM +0800, Rob Herring wrote:
> >> On Thu, Dec 08, 2016 at 05:23:04PM +0800, Yuan Yao wrote:
> >> > From: Yuan Yao <yao.yuan@nxp.com>
> >>
> >> Same problem in this subject too.
> >>
> >> >
> >> > new compatible string: "fsl,ls1012a-qspi".
> >> >
> >> > Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
> >> > ---
> >> > Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
> >> > 1 file changed, 1 insertion(+)
> >>
> >> Acked-by: Rob Herring <robh@kernel.org>
> >
> > Thanks for your review.
> > And do you have any suggestion for this subject?
>
> The problem is you have a space in the compatible string: "fsl, ls1012a-qspi"
> rather than "fsl,ls1012a-qspi"
>
> Also, I prefer "dt/bindings: " as the beginning of binding patch subjects.
>
Ok, Get it.
Thanks for your comments.
I will send v2 soon.
^ permalink raw reply
* [PATCH v8 2/4] vcodec: mediatek: Add Mediatek JPEG Decoder Driver
From: Ricky Liang @ 2016-12-14 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481533621.13825.2.camel@mtksdaap41>
Hi Rick,
Can you upload patchset v9 to address the issue? Thanks!
On Mon, Dec 12, 2016 at 5:07 PM, Rick Chang <rick.chang@mediatek.com> wrote:
> Hi Ricky,
>
> Thanks for your feedback. We will fix the problem in another patch.
>
> On Mon, 2016-12-12 at 12:34 +0800, Ricky Liang wrote:
>> Hi Rick,
>>
>> On Wed, Nov 30, 2016 at 11:08 AM, Rick Chang <rick.chang@mediatek.com> wrote:
>> > Add v4l2 driver for Mediatek JPEG Decoder
>> >
>> > Signed-off-by: Rick Chang <rick.chang@mediatek.com>
>> > Signed-off-by: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
>>
>> <snip...>
>>
>> > +static bool mtk_jpeg_check_resolution_change(struct mtk_jpeg_ctx *ctx,
>> > + struct mtk_jpeg_dec_param *param)
>> > +{
>> > + struct mtk_jpeg_dev *jpeg = ctx->jpeg;
>> > + struct mtk_jpeg_q_data *q_data;
>> > +
>> > + q_data = &ctx->out_q;
>> > + if (q_data->w != param->pic_w || q_data->h != param->pic_h) {
>> > + v4l2_dbg(1, debug, &jpeg->v4l2_dev, "Picture size change\n");
>> > + return true;
>> > + }
>> > +
>> > + q_data = &ctx->cap_q;
>> > + if (q_data->fmt != mtk_jpeg_find_format(ctx, param->dst_fourcc,
>> > + MTK_JPEG_FMT_TYPE_CAPTURE)) {
>> > + v4l2_dbg(1, debug, &jpeg->v4l2_dev, "format change\n");
>> > + return true;
>> > + }
>> > + return false;
>>
>> <snip...>
>>
>> > +static void mtk_jpeg_device_run(void *priv)
>> > +{
>> > + struct mtk_jpeg_ctx *ctx = priv;
>> > + struct mtk_jpeg_dev *jpeg = ctx->jpeg;
>> > + struct vb2_buffer *src_buf, *dst_buf;
>> > + enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
>> > + unsigned long flags;
>> > + struct mtk_jpeg_src_buf *jpeg_src_buf;
>> > + struct mtk_jpeg_bs bs;
>> > + struct mtk_jpeg_fb fb;
>> > + int i;
>> > +
>> > + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
>> > + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
>> > + jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(src_buf);
>> > +
>> > + if (jpeg_src_buf->flags & MTK_JPEG_BUF_FLAGS_LAST_FRAME) {
>> > + for (i = 0; i < dst_buf->num_planes; i++)
>> > + vb2_set_plane_payload(dst_buf, i, 0);
>> > + buf_state = VB2_BUF_STATE_DONE;
>> > + goto dec_end;
>> > + }
>> > +
>> > + if (mtk_jpeg_check_resolution_change(ctx, &jpeg_src_buf->dec_param)) {
>> > + mtk_jpeg_queue_src_chg_event(ctx);
>> > + ctx->state = MTK_JPEG_SOURCE_CHANGE;
>> > + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
>> > + return;
>> > + }
>>
>> This only detects source change if multiple OUPUT buffers are queued.
>> It does not catch the source change in the following scenario:
>>
>> - OUPUT buffers for jpeg1 enqueued
>> - OUTPUT queue STREAMON
>> - userspace creates CAPTURE buffers
>> - CAPTURE buffers enqueued
>> - CAPTURE queue STREAMON
>> - decode
>> - OUTPUT queue STREAMOFF
>> - userspace recreates OUTPUT buffers for jpeg2
>> - OUTPUT buffers for jpeg2 enqueued
>> - OUTPUT queue STREAMON
>>
>> In the above sequence if jpeg2's decoded size is larger than jpeg1 the
>> function fails to detect that the existing CAPTURE buffers are not big
>> enough to hold the decoded data.
>>
>> A possible fix is to pass *dst_buf to
>> mtk_jpeg_check_resolution_change(), and check in the function that all
>> the dst_buf planes are large enough to hold the decoded data.
>>
>> > +
>> > + mtk_jpeg_set_dec_src(ctx, src_buf, &bs);
>> > + if (mtk_jpeg_set_dec_dst(ctx, &jpeg_src_buf->dec_param, dst_buf, &fb))
>> > + goto dec_end;
>> > +
>> > + spin_lock_irqsave(&jpeg->hw_lock, flags);
>> > + mtk_jpeg_dec_reset(jpeg->dec_reg_base);
>> > + mtk_jpeg_dec_set_config(jpeg->dec_reg_base,
>> > + &jpeg_src_buf->dec_param, &bs, &fb);
>> > +
>> > + mtk_jpeg_dec_start(jpeg->dec_reg_base);
>> > + spin_unlock_irqrestore(&jpeg->hw_lock, flags);
>> > + return;
>> > +
>> > +dec_end:
>> > + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
>> > + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
>> > + v4l2_m2m_buf_done(to_vb2_v4l2_buffer(src_buf), buf_state);
>> > + v4l2_m2m_buf_done(to_vb2_v4l2_buffer(dst_buf), buf_state);
>> > + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
>> > +}
>>
>> <snip...>
>
>
^ permalink raw reply
* [PATCH] Input: imx6ul_tsc - generalize the averaging property
From: Guy Shapiro @ 2016-12-14 7:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqJAdxrUGL5pjTPDkrXTsKJU-vL1Y4TpqhP79bESs9vR-g@mail.gmail.com>
On 13/12/2016 21:54, Rob Herring wrote:
> On Sun, Dec 11, 2016 at 1:06 AM, Guy Shapiro <guy.shapiro@mobi-wize.com> wrote:
>> Make the avarage-samples property a general touchscreen property
>> rather than imx6ul device specific.
>>
>> Signed-off-by: Guy Shapiro <guy.shapiro@mobi-wize.com>
>> ---
>> .../bindings/input/touchscreen/imx6ul_tsc.txt | 11 ++----
>> .../bindings/input/touchscreen/touchscreen.txt | 3 ++
>> drivers/input/touchscreen/imx6ul_tsc.c | 46 ++++++++++++++++------
>> 3 files changed, 41 insertions(+), 19 deletions(-)
> [...]
>
>> + switch (average_samples) {
>> + case 1:
>> + tsc->average_enable = false;
>> + tsc->average_select = 0; /* value unused; initialize anyway */
>> + break;
>> + case 4:
>> + tsc->average_enable = true;
>> + tsc->average_select = 0;
>> + break;
>> + case 8:
>> + tsc->average_enable = true;
>> + tsc->average_select = 1;
>> + break;
>> + case 16:
>> + tsc->average_enable = true;
>> + tsc->average_select = 2;
>> + break;
>> + case 32:
>> + tsc->average_enable = true;
>> + tsc->average_select = 3;
>> + break;
> This could be more efficiently written as
>
> tsc->average_select = log2(average_samples) - 2;
>
> Then enable if >=0.
Using '1' to indicate no averaging is more consistent then using '0'.
I think it is better to validate the values rather then round them.
What do you think about:
+ switch (average_samples) {
+ case 1:
+ tsc->average_enable = false;
+ tsc->average_select = 0; /* value unused; initialize
anyway */
+ break;
+ case 4:
+ case 8:
+ case 16:
+ case 32:
+ tsc->average_enable = true;
+ tsc->average_select = ilog2(average_samples) - 2;
+ break;
+ default:
+ dev_err(&pdev->dev,
+ "touchscreen-average-samples (%u) must be 1, 4,
8, 16 or 32\n",
+ average_samples);
Guy.
^ permalink raw reply
* [PATCH v3 1/4] mtd: lart: Rename partition defines to be prefixed with PART_
From: Boris Brezillon @ 2016-12-14 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161209233628.6642-2-f.fainelli@gmail.com>
On Fri, 9 Dec 2016 15:36:25 -0800
Florian Fainelli <f.fainelli@gmail.com> wrote:
> In preparation for defining KERNEL_START on ARM, rename KERNEL_START to
> PART_KERNEL_START, and to be consistent, do this for all
> partition-related constants.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---
> drivers/mtd/devices/lart.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mtd/devices/lart.c b/drivers/mtd/devices/lart.c
> index 82bd00af5cc3..268aae45b514 100644
> --- a/drivers/mtd/devices/lart.c
> +++ b/drivers/mtd/devices/lart.c
> @@ -75,18 +75,18 @@ static char module_name[] = "lart";
>
> /* blob */
> #define NUM_BLOB_BLOCKS FLASH_NUMBLOCKS_16m_PARAM
> -#define BLOB_START 0x00000000
> -#define BLOB_LEN (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
> +#define PART_BLOB_START 0x00000000
> +#define PART_BLOB_LEN (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
>
> /* kernel */
> #define NUM_KERNEL_BLOCKS 7
> -#define KERNEL_START (BLOB_START + BLOB_LEN)
> -#define KERNEL_LEN (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
> +#define PART_KERNEL_START (PART_BLOB_START + PART_BLOB_LEN)
> +#define PART_KERNEL_LEN (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
>
> /* initial ramdisk */
> #define NUM_INITRD_BLOCKS 24
> -#define INITRD_START (KERNEL_START + KERNEL_LEN)
> -#define INITRD_LEN (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
> +#define PART_INITRD_START (PART_KERNEL_START + PART_KERNEL_LEN)
> +#define PART_INITRD_LEN (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
>
> /*
> * See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
> @@ -587,20 +587,20 @@ static struct mtd_partition lart_partitions[] = {
> /* blob */
> {
> .name = "blob",
> - .offset = BLOB_START,
> - .size = BLOB_LEN,
> + .offset = PART_BLOB_START,
> + .size = PART_BLOB_LEN,
> },
> /* kernel */
> {
> .name = "kernel",
> - .offset = KERNEL_START, /* MTDPART_OFS_APPEND */
> - .size = KERNEL_LEN,
> + .offset = PART_KERNEL_START, /* MTDPART_OFS_APPEND */
> + .size = PART_KERNEL_LEN,
> },
> /* initial ramdisk / file system */
> {
> .name = "file system",
> - .offset = INITRD_START, /* MTDPART_OFS_APPEND */
> - .size = INITRD_LEN, /* MTDPART_SIZ_FULL */
> + .offset = PART_INITRD_START, /* MTDPART_OFS_APPEND */
> + .size = PART_INITRD_LEN, /* MTDPART_SIZ_FULL */
> }
> };
> #define NUM_PARTITIONS ARRAY_SIZE(lart_partitions)
^ permalink raw reply
* [PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
From: Moritz Fischer @ 2016-12-14 6:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214023553.9377-2-f.fainelli@gmail.com>
Hi Florian,
On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Register the TS-7300 FPGA manager device drivers which allows us to load
> bitstreams into the on-board Altera Cyclone II FPGA.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
> index 3b39ea353d30..acf72ea670ef 100644
> --- a/arch/arm/mach-ep93xx/ts72xx.c
> +++ b/arch/arm/mach-ep93xx/ts72xx.c
> @@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
> .phy_id = 1,
> };
>
> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
> +
> +/* Relative to EP93XX_CS1_PHYS_BASE */
> +#define TS73XX_FPGA_LOADER_BASE 0x03c00000
> +
> +static struct resource ts73xx_fpga_resources[] = {
> + {
> + .start = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
> + .end = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
> + .flags = IORESOURCE_MEM,
> + },
> +};
> +
> +static struct platform_device ts73xx_fpga_device = {
> + .name = "ts73xx-fpga-mgr",
> + .id = -1,
> + .resource = ts73xx_fpga_resources,
> + .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
> +};
> +
> +#endif
> +
> static void __init ts72xx_init_machine(void)
> {
> ep93xx_init_devices();
> @@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
> platform_device_register(&ts72xx_wdt_device);
>
> ep93xx_register_eth(&ts72xx_eth_data, 1);
> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
> + if (board_is_ts7300())
> + platform_device_register(&ts73xx_fpga_device);
> +#endif
> }
>
> MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
> --
> 2.9.3
>
I think this is backwards, shouldn't this be your [PATCH 2/2]?
Otherwise you're using
the driver before you added it.
Thanks,
Moritz
^ permalink raw reply
* [PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager
From: Moritz Fischer @ 2016-12-14 6:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214023553.9377-3-f.fainelli@gmail.com>
Hi Florian,
On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Add support for loading bitstreams on the Altera Cyclone II FPGA
> populated on the TS-7300 board. This is done through the configuration
> and data registers offered through a memory interface between the EP93xx
> SoC and the FPGA via an intermediate CPLD device.
>
> The EP93xx SoC on the TS-7300 does not have direct means of configuring
> the on-board FPGA other than by using the special memory mapped
> interface to the CPLD. No other entity on the system can control the
> FPGA bitstream.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> drivers/fpga/Kconfig | 7 ++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 171 insertions(+)
> create mode 100644 drivers/fpga/ts73xx-fpga.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ce861a2853a4..d9cbef60db80 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
> help
> FPGA manager driver support for Altera Arria10 SoCFPGA.
>
> +config FPGA_MGR_TS73XX
> + tristate "Technologic Systems TS-73xx SBC FPGA Manager"
> + depends on ARCH_EP93XX && MACH_TS72XX
> + help
> + FPGA manager driver support for the Altera Cyclone II FPGA
> + present on the TS-73xx SBC boards.
> +
> config FPGA_MGR_ZYNQ_FPGA
> tristate "Xilinx Zynq FPGA"
> depends on ARCH_ZYNQ || COMPILE_TEST
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 8df07bcf42a6..a1160169e6d9 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o
> # FPGA Manager Drivers
> obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
> obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
> +obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
> obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
>
> # FPGA Bridge Drivers
> diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
> new file mode 100644
> index 000000000000..38d78d8c6b1e
> --- /dev/null
> +++ b/drivers/fpga/ts73xx-fpga.c
> @@ -0,0 +1,163 @@
> +/*
> + * Technologic Systems TS-73xx SBC FPGA loader
> + *
> + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
> + *
> + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
> + * TS-7300, heavily based on load_fpga.c in their vendor tree.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/string.h>
> +#include <linux/iopoll.h>
> +#include <linux/fpga/fpga-mgr.h>
> +
> +#define TS73XX_FPGA_DATA_REG 0
> +#define TS73XX_FPGA_CONFIG_REG 1
> +
> +#define TS73XX_FPGA_WRITE_DONE 0x1
> +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
> +#define TS73XX_FPGA_RESET 0x2
> +#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
> +#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
> +#define TS73XX_FPGA_LOAD_OK 0x4
> +#define TS73XX_FPGA_CONFIG_LOAD 0x8
> +
> +struct ts73xx_fpga_priv {
> + void __iomem *io_base;
> + struct device *dev;
> +};
> +
> +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
> +{
> + return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
> + struct fpga_image_info *info,
> + const char *buf, size_t count)
> +{
> + struct ts73xx_fpga_priv *priv = mgr->priv;
> +
> + /* Reset the FPGA */
> + writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> + udelay(TS73XX_FPGA_RESET_LOW_DELAY);
> + writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> + udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
> +
> + return 0;
> +}
> +
> +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
> + size_t count)
> +{
> + struct ts73xx_fpga_priv *priv = mgr->priv;
> + size_t i = 0;
> + int ret;
> + u8 reg;
> +
> + while (count--) {
> + ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
> + reg, !(reg & TS73XX_FPGA_WRITE_DONE),
> + 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
> + if (ret < 0)
> + return ret;
> +
> + writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
> + i++;
> + }
> +
<snip>
> + usleep_range(1000, 2000);
> + reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> + reg |= TS73XX_FPGA_CONFIG_LOAD;
> + writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> + usleep_range(1000, 2000);
</snip>
Just to clarify is this block what triggers the actual write? I'm asking because
I'm wondering if in the current implementation the ts73xx_fpga_write() function
can be called multiple times in your implementation before you finally get to
the write complete callback.
> +
> + reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> + reg &= ~TS73XX_FPGA_CONFIG_LOAD;
> + writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +
> + return 0;
> +}
> +
> +static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
> + struct fpga_image_info *info)
> +{
> + struct ts73xx_fpga_priv *priv = mgr->priv;
> + u8 reg;
> +
> + reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> + if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static const struct fpga_manager_ops ts73xx_fpga_ops = {
> + .state = ts73xx_fpga_state,
> + .write_init = ts73xx_fpga_write_init,
> + .write = ts73xx_fpga_write,
> + .write_complete = ts73xx_fpga_write_complete,
> +};
> +
> +static int ts73xx_fpga_probe(struct platform_device *pdev)
> +{
> + struct device *kdev = &pdev->dev;
> + struct ts73xx_fpga_priv *priv;
> + struct resource *res;
> + int err;
> +
> + priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->dev = kdev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->io_base = devm_ioremap_resource(kdev, res);
> + if (IS_ERR(priv->io_base)) {
> + dev_err(kdev, "unable to remap registers\n");
> + return PTR_ERR(priv->io_base);
> + }
> +
> + err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
> + &ts73xx_fpga_ops, priv);
> + if (err) {
> + dev_err(kdev, "failed to register FPGA manager\n");
> + return err;
> + }
> +
> + return err;
> +}
> +
> +static int ts73xx_fpga_remove(struct platform_device *pdev)
> +{
> + fpga_mgr_unregister(&pdev->dev);
> +
> + return 0;
> +}
> +
> +static struct platform_driver ts73xx_fpga_driver = {
> + .driver = {
> + .name = "ts73xx-fpga-mgr",
> + },
> + .probe = ts73xx_fpga_probe,
> + .remove = ts73xx_fpga_remove,
> +};
> +module_platform_driver(ts73xx_fpga_driver);
> +
> +MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
> +MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.9.3
>
Thanks,
Moritz
^ permalink raw reply
* [PATCH v2] crypto: sun4i-ss: support the Security System PRNG
From: Corentin Labbe @ 2016-12-14 6:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214050551.GD9592@gondor.apana.org.au>
On Wed, Dec 14, 2016 at 01:05:51PM +0800, Herbert Xu wrote:
> On Tue, Dec 13, 2016 at 03:10:59PM +0100, Corentin Labbe wrote:
> >
> > I have found two solutions:
>
> No we already have algif_rng so let's not confuse things even
> further by making hwrng take PRNGs.
>
But algif_rng is not accessible from user space without any coding.
So no easy "random" data with some cat /dev/xxxx.
Clearly users of the 3 already intree hw_random PRNG will see that like a regresion.
Regards
Corentin Labbe
^ permalink raw reply
* [PATCH] ipmi: bt-bmc: Use a regmap for register access
From: Andrew Jeffery @ 2016-12-14 5:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACPK8XezqdO3HQBBtQmFLNEbG0Ykq1EppFE_B7CjARRqw-f1vQ@mail.gmail.com>
On Wed, 2016-12-14 at 11:59 +1030, Joel Stanley wrote:
> > On Tue, Dec 6, 2016 at 1:27 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> > The registers for the bt-bmc device live under the Aspeed LPC
> > controller. Devicetree bindings have recently been introduced for the
> > LPC controller where the "host" portion of the LPC register space is
> > described as a syscon device. Future devicetrees describing the bt-bmc
> > device should nest its node under the appropriate "simple-mfd", "syscon"
> > compatible node.
> >
> > This change allows the bt-bmc driver to function with both syscon and
> > non-syscon- based devicetree descriptions by always using a regmap for
> > register access, either retrieved from the parent syscon device or
> > instantiated if none exists.
> >
> > The patch has been tested on an OpenPOWER Palmetto machine, successfully
> > booting, rebooting and powering down the host.
> >
> > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > ?drivers/char/ipmi/Kconfig??|??1 +
> > ?drivers/char/ipmi/bt-bmc.c | 82 ++++++++++++++++++++++++++++++++++------------
> > ?2 files changed, 62 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
> > index 7f816655cbbf..b5d48d9af124 100644
> > --- a/drivers/char/ipmi/Kconfig
> > +++ b/drivers/char/ipmi/Kconfig
> > @@ -79,6 +79,7 @@ endif # IPMI_HANDLER
> >
> > ?config ASPEED_BT_IPMI_BMC
> > ????????depends on ARCH_ASPEED
>
> If you do a v2 of this series it would be great to add || COMPILE_TEST here.
>
> > +????????depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
> > ????????tristate "BT IPMI bmc driver"
> > ????????help
> > ??????????Provides a driver for the BT (Block Transfer) IPMI interface
> > diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> > index fc9e8891eae3..ca1e20f6c6c5 100644
> > --- a/drivers/char/ipmi/bt-bmc.c
> > +++ b/drivers/char/ipmi/bt-bmc.c
> > @@ -12,10 +12,13 @@
> > ?#include <linux/errno.h>
> > ?#include <linux/interrupt.h>
> > ?#include <linux/io.h>
> > +#include <linux/mfd/syscon.h>
> > ?#include <linux/miscdevice.h>
> > ?#include <linux/module.h>
> > +#include <linux/of.h>
> > ?#include <linux/platform_device.h>
> > ?#include <linux/poll.h>
> > +#include <linux/regmap.h>
> > ?#include <linux/sched.h>
> > ?#include <linux/timer.h>
> >
> > @@ -60,7 +63,8 @@
> > ?struct bt_bmc {
> > ????????struct device???????????dev;
> > ????????struct miscdevice???????miscdev;
> > -???????void __iomem????????????*base;
> > +???????struct regmap???????????*map;
> > +???????int?????????????????????offset;
> > ????????int?????????????????????irq;
> > ????????wait_queue_head_t???????queue;
> > ????????struct timer_list???????poll_timer;
> > @@ -69,14 +73,31 @@ struct bt_bmc {
> >
> > ?static atomic_t open_count = ATOMIC_INIT(0);
> >
> > +static struct regmap_config bt_regmap_cfg = {
>
> const?
Good point. Is it worth a v2?
>
> > +???????.reg_bits = 32,
> > +???????.val_bits = 32,
> > +???????.reg_stride = 4,
> > +};
> > +
> > ?static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
> > ?{
> > -???????return ioread8(bt_bmc->base + reg);
> > +???????uint32_t val = 0;
> > +???????int rc;
> > +
> > +???????rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val);
> > +???????WARN(rc != 0, "%s:%d: regmap_read() failed: %d\n",
> > +???????????????????????__FILE__, __LINE__, rc);
>
> Under what circumstances do we expect the read to fail?
By the regmap_read() implementation for MMIO it should never fail. If
it does, then we should tell someone about it.
>
> This isn't much cleaner, but I prefer it slightly:
>
> rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val);
> if (rc) {
> ???dev_warn(bt_bmc->dev, "read failed %d\n", rc);
> ???return rc;
> }
>
> return val;
bt_inb() currently returns a u8 type, and as such no caller performs
error checking. While your suggestion might seem slightly preferable,
it feels likely "slightly preferable" might fail to take into account
the cascading effect of changing the return type and testing for errors
at each of the (transitive) call-sites.
I think the additional code required makes your suggestion less
attractive given that the call should never fail.
If you decide you feel strongly about it I can make the change.
>
> > +
> > +???????return rc == 0 ? (u8) val : 0;
> > ?}
> >
> > ?static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
> > ?{
> > -???????iowrite8(data, bt_bmc->base + reg);
> > +???????int rc;
> > +
> > +???????rc = regmap_write(bt_bmc->map, bt_bmc->offset + reg, data);
> > +???????WARN(rc != 0, "%s:%d: regmap_write() failed: %d\n",
> > +???????????????????????__FILE__, __LINE__, rc);
> > ?}
> >
> > ?static void clr_rd_ptr(struct bt_bmc *bt_bmc)
> > @@ -367,14 +388,18 @@ static irqreturn_t bt_bmc_irq(int irq, void *arg)
> > ?{
> > ????????struct bt_bmc *bt_bmc = arg;
> > ????????u32 reg;
> > +???????int rc;
> > +
> > +???????rc = regmap_read(bt_bmc->map, bt_bmc->offset + BT_CR2, ®);
> > +???????if (rc)
> > +???????????????return IRQ_NONE;
> >
> > -???????reg = ioread32(bt_bmc->base + BT_CR2);
> > ????????reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY;
> > ????????if (!reg)
> > ????????????????return IRQ_NONE;
> >
> > ????????/* ack pending IRQs */
> > -???????iowrite32(reg, bt_bmc->base + BT_CR2);
> > +???????regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR2, reg);
> >
> > ????????wake_up(&bt_bmc->queue);
> > ????????return IRQ_HANDLED;
> > @@ -384,7 +409,6 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> > ?????????????????????????????struct platform_device *pdev)
> > ?{
> > ????????struct device *dev = &pdev->dev;
> > -???????u32 reg;
> > ????????int rc;
> >
> > ????????bt_bmc->irq = platform_get_irq(pdev, 0);
> > @@ -405,18 +429,17 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> > ?????????* will be cleared (along with B2H) when we can write the next
> > ?????????* message to the BT buffer
> > ?????????*/
> > -???????reg = ioread32(bt_bmc->base + BT_CR1);
> > -???????reg |= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY;
> > -???????iowrite32(reg, bt_bmc->base + BT_CR1);
> > +???????rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + BT_CR1,
> > +???????????????????????????????(BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY),
> > +???????????????????????????????(BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY));
>
> You could drop the ( ) around the flags if you want.
I think I wrote it this way when I was toying with different line-
wraps, but regardless I think they are a nice visual queue.
Andrew
>
> >
> > -???????return 0;
> > +???????return rc;
> > ?}
> >
> > ?static int bt_bmc_probe(struct platform_device *pdev)
> > ?{
> > ????????struct bt_bmc *bt_bmc;
> > ????????struct device *dev;
> > -???????struct resource *res;
> > ????????int rc;
> >
> > ????????if (!pdev || !pdev->dev.of_node)
> > @@ -431,10 +454,27 @@ static int bt_bmc_probe(struct platform_device *pdev)
> >
> > ????????dev_set_drvdata(&pdev->dev, bt_bmc);
> >
> > -???????res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > -???????bt_bmc->base = devm_ioremap_resource(&pdev->dev, res);
> > -???????if (IS_ERR(bt_bmc->base))
> > -???????????????return PTR_ERR(bt_bmc->base);
> > +???????bt_bmc->map = syscon_node_to_regmap(pdev->dev.parent->of_node);
> > +???????if (IS_ERR(bt_bmc->map)) {
> > +???????????????struct resource *res;
> > +???????????????void __iomem *base;
> > +
> > +???????????????/*
> > +????????????????* Assume it's not the MFD-based devicetree description, in
> > +????????????????* which case generate a regmap ourselves
> > +????????????????*/
> > +???????????????res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +???????????????base = devm_ioremap_resource(&pdev->dev, res);
> > +???????????????if (IS_ERR(base))
> > +???????????????????????return PTR_ERR(base);
> > +
> > +???????????????bt_bmc->map = devm_regmap_init_mmio(dev, base, &bt_regmap_cfg);
> > +???????????????bt_bmc->offset = 0;
> > +???????} else {
> > +???????????????rc = of_property_read_u32(dev->of_node, "reg", &bt_bmc->offset);
> > +???????????????if (rc)
> > +???????????????????????return rc;
> > +???????}
> >
> > ????????mutex_init(&bt_bmc->mutex);
> > ????????init_waitqueue_head(&bt_bmc->queue);
> > @@ -461,12 +501,12 @@ static int bt_bmc_probe(struct platform_device *pdev)
> > ????????????????add_timer(&bt_bmc->poll_timer);
> > ????????}
> >
> > -???????iowrite32((BT_IO_BASE << BT_CR0_IO_BASE) |
> > -?????????????????(BT_IRQ << BT_CR0_IRQ) |
> > -?????????????????BT_CR0_EN_CLR_SLV_RDP |
> > -?????????????????BT_CR0_EN_CLR_SLV_WRP |
> > -?????????????????BT_CR0_ENABLE_IBT,
> > -?????????????????bt_bmc->base + BT_CR0);
> > +???????regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
> > +????????????????????(BT_IO_BASE << BT_CR0_IO_BASE) |
> > +????????????????????(BT_IRQ << BT_CR0_IRQ) |
> > +????????????????????BT_CR0_EN_CLR_SLV_RDP |
> > +????????????????????BT_CR0_EN_CLR_SLV_WRP |
> > +????????????????????BT_CR0_ENABLE_IBT);
> >
> > ????????clr_b_busy(bt_bmc);
> >
> > --
> > 2.9.3
> >
-------------- next part --------------
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^ permalink raw reply
* [PATCH] drm/mediatek: Support UYVY and YUYV format for overlay
From: Bibby Hsieh @ 2016-12-14 5:14 UTC (permalink / raw)
To: linux-arm-kernel
MT8173 overlay can support UYVY and YUYV format,
we add the format in DRM driver.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 019b7ca..0a340f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -44,6 +44,8 @@
#define OVL_CON_CLRFMT_RGB888 (1 << 12)
#define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
#define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
+#define OVL_CON_CLRFMT_UYVY (4 << 12)
+#define OVL_CON_CLRFMT_YUYV (5 << 12)
#define OVL_CON_AEN BIT(8)
#define OVL_CON_ALPHA 0xff
@@ -161,6 +163,10 @@ static unsigned int ovl_fmt_convert(unsigned int fmt)
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
+ case DRM_FORMAT_YUYV:
+ return OVL_CON_CLRFMT_YUYV;
+ case DRM_FORMAT_UYVY:
+ return OVL_CON_CLRFMT_UYVY;
}
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index c461a23..b94c6ee 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -28,6 +28,8 @@
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_RGB565,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_UYVY,
};
static void mtk_plane_reset(struct drm_plane *plane)
--
1.9.1
^ permalink raw reply related
* [PATCH v2] crypto: sun4i-ss: support the Security System PRNG
From: Herbert Xu @ 2016-12-14 5:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213141059.GB10647@Red>
On Tue, Dec 13, 2016 at 03:10:59PM +0100, Corentin Labbe wrote:
>
> I have found two solutions:
No we already have algif_rng so let's not confuse things even
further by making hwrng take PRNGs.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH v7 3/5] drm: bridge: add support for TI ths8135
From: Archit Taneja @ 2016-12-14 5:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481623759-12786-4-git-send-email-bgolaszewski@baylibre.com>
On 12/13/2016 03:39 PM, Bartosz Golaszewski wrote:
> THS8135 is a configurable video DAC, but no configuration is actually
> necessary to make it work.
>
> For now use the dumb-vga-dac driver to support it.
Queued to drm-misc-next
Archit
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/gpu/drm/bridge/dumb-vga-dac.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c b/drivers/gpu/drm/bridge/dumb-vga-dac.c
> index e570698..86e9f9c 100644
> --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
> +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
> @@ -237,6 +237,7 @@ static int dumb_vga_remove(struct platform_device *pdev)
>
> static const struct of_device_id dumb_vga_match[] = {
> { .compatible = "dumb-vga-dac" },
> + { .compatible = "ti,ths8135" },
> {},
> };
> MODULE_DEVICE_TABLE(of, dumb_vga_match);
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v7 2/5] drm: bridge: add DT bindings for TI ths8135
From: Archit Taneja @ 2016-12-14 5:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481623759-12786-3-git-send-email-bgolaszewski@baylibre.com>
Hi,
On 12/13/2016 03:39 PM, Bartosz Golaszewski wrote:
> THS8135 is a configurable video DAC. Add DT bindings for this chip.
Queued to drm-misc-next
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/display/bridge/ti,ths8135.txt | 46 ++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt b/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
> new file mode 100644
> index 0000000..6ec1a88
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
> @@ -0,0 +1,46 @@
> +THS8135 Video DAC
> +-----------------
> +
> +This is the binding for Texas Instruments THS8135 Video DAC bridge.
> +
> +Required properties:
> +
> +- compatible: Must be "ti,ths8135"
> +
> +Required nodes:
> +
> +This device has two video ports. Their connections are modelled using the OF
> +graph bindings specified in Documentation/devicetree/bindings/graph.txt.
> +
> +- Video port 0 for RGB input
> +- Video port 1 for VGA output
> +
> +Example
> +-------
> +
> +vga-bridge {
> + compatible = "ti,ths8135";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> +
> + vga_bridge_in: endpoint {
> + remote-endpoint = <&lcdc_out_vga>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> +
> + vga_bridge_out: endpoint {
> + remote-endpoint = <&vga_con_in>;
> + };
> + };
> + };
> +};
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] media: platform: exynos4-is: constify v4l2_subdev_ops strcutures
From: Bhumika Goyal @ 2016-12-14 3:55 UTC (permalink / raw)
To: linux-arm-kernel
Check for v4l2_subdev_ops structures that are only passed as an
argument to the function v4l2_subdev_init. This argument is of type
const, so v4l2_subdev_ops structures having this property can also be
declared const.
Done using Coccinelle:
@r1 disable optional_qualifier @
identifier i;
position p;
@@
static struct v4l2_subdev_ops i at p = {...};
@ok1@
identifier r1.i;
position p;
@@
v4l2_subdev_init(...,&i at p)
@bad@
position p!={r1.p,ok1.p};
identifier r1.i;
@@
i at p
@depends on !bad disable optional_qualifier@
identifier r1.i;
@@
+const
struct v4l2_subdev_ops i;
Before and after size details:
text data bss dec hex filename
6743 152 20 6915 1b03 platform/exynos4-is/fimc-isp.o
6807 88 20 6915 1b03 platform/exynos4-is/fimc-isp.o
15653 392 36 16081 3ed1 platform/exynos4-is/fimc-lite.o
15717 308 36 16061 3ebd platform/exynos4-is/fimc-lite.o
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
---
drivers/media/platform/exynos4-is/fimc-isp.c | 2 +-
drivers/media/platform/exynos4-is/fimc-lite.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/exynos4-is/fimc-isp.c b/drivers/media/platform/exynos4-is/fimc-isp.c
index 8efe916..fd793d3 100644
--- a/drivers/media/platform/exynos4-is/fimc-isp.c
+++ b/drivers/media/platform/exynos4-is/fimc-isp.c
@@ -433,7 +433,7 @@ static void fimc_isp_subdev_unregistered(struct v4l2_subdev *sd)
.s_power = fimc_isp_subdev_s_power,
};
-static struct v4l2_subdev_ops fimc_is_subdev_ops = {
+static const struct v4l2_subdev_ops fimc_is_subdev_ops = {
.core = &fimc_is_core_ops,
.video = &fimc_is_subdev_video_ops,
.pad = &fimc_is_subdev_pad_ops,
diff --git a/drivers/media/platform/exynos4-is/fimc-lite.c b/drivers/media/platform/exynos4-is/fimc-lite.c
index b91abf1..18b6aaa 100644
--- a/drivers/media/platform/exynos4-is/fimc-lite.c
+++ b/drivers/media/platform/exynos4-is/fimc-lite.c
@@ -1361,7 +1361,7 @@ static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
.log_status = fimc_lite_log_status,
};
-static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
+static const struct v4l2_subdev_ops fimc_lite_subdev_ops = {
.core = &fimc_lite_core_ops,
.video = &fimc_lite_subdev_video_ops,
.pad = &fimc_lite_subdev_pad_ops,
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214023553.9377-1-f.fainelli@gmail.com>
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.
The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/fpga/Kconfig | 7 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 171 insertions(+)
create mode 100644 drivers/fpga/ts73xx-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2853a4..d9cbef60db80 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
help
FPGA manager driver support for Altera Arria10 SoCFPGA.
+config FPGA_MGR_TS73XX
+ tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+ depends on ARCH_EP93XX && MACH_TS72XX
+ help
+ FPGA manager driver support for the Altera Cyclone II FPGA
+ present on the TS-73xx SBC boards.
+
config FPGA_MGR_ZYNQ_FPGA
tristate "Xilinx Zynq FPGA"
depends on ARCH_ZYNQ || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bcf42a6..a1160169e6d9 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
# FPGA Bridge Drivers
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
new file mode 100644
index 000000000000..38d78d8c6b1e
--- /dev/null
+++ b/drivers/fpga/ts73xx-fpga.c
@@ -0,0 +1,163 @@
+/*
+ * Technologic Systems TS-73xx SBC FPGA loader
+ *
+ * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
+ * TS-7300, heavily based on load_fpga.c in their vendor tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/iopoll.h>
+#include <linux/fpga/fpga-mgr.h>
+
+#define TS73XX_FPGA_DATA_REG 0
+#define TS73XX_FPGA_CONFIG_REG 1
+
+#define TS73XX_FPGA_WRITE_DONE 0x1
+#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
+#define TS73XX_FPGA_RESET 0x2
+#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
+#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
+#define TS73XX_FPGA_LOAD_OK 0x4
+#define TS73XX_FPGA_CONFIG_LOAD 0x8
+
+struct ts73xx_fpga_priv {
+ void __iomem *io_base;
+ struct device *dev;
+};
+
+static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+
+ /* Reset the FPGA */
+ writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ udelay(TS73XX_FPGA_RESET_LOW_DELAY);
+ writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
+
+ return 0;
+}
+
+static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
+ size_t count)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+ size_t i = 0;
+ int ret;
+ u8 reg;
+
+ while (count--) {
+ ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
+ reg, !(reg & TS73XX_FPGA_WRITE_DONE),
+ 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
+ if (ret < 0)
+ return ret;
+
+ writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
+ i++;
+ }
+
+ usleep_range(1000, 2000);
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ reg |= TS73XX_FPGA_CONFIG_LOAD;
+ writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ usleep_range(1000, 2000);
+
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ reg &= ~TS73XX_FPGA_CONFIG_LOAD;
+ writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+
+ return 0;
+}
+
+static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+ u8 reg;
+
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static const struct fpga_manager_ops ts73xx_fpga_ops = {
+ .state = ts73xx_fpga_state,
+ .write_init = ts73xx_fpga_write_init,
+ .write = ts73xx_fpga_write,
+ .write_complete = ts73xx_fpga_write_complete,
+};
+
+static int ts73xx_fpga_probe(struct platform_device *pdev)
+{
+ struct device *kdev = &pdev->dev;
+ struct ts73xx_fpga_priv *priv;
+ struct resource *res;
+ int err;
+
+ priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = kdev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->io_base = devm_ioremap_resource(kdev, res);
+ if (IS_ERR(priv->io_base)) {
+ dev_err(kdev, "unable to remap registers\n");
+ return PTR_ERR(priv->io_base);
+ }
+
+ err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
+ &ts73xx_fpga_ops, priv);
+ if (err) {
+ dev_err(kdev, "failed to register FPGA manager\n");
+ return err;
+ }
+
+ return err;
+}
+
+static int ts73xx_fpga_remove(struct platform_device *pdev)
+{
+ fpga_mgr_unregister(&pdev->dev);
+
+ return 0;
+}
+
+static struct platform_driver ts73xx_fpga_driver = {
+ .driver = {
+ .name = "ts73xx-fpga-mgr",
+ },
+ .probe = ts73xx_fpga_probe,
+ .remove = ts73xx_fpga_remove,
+};
+module_platform_driver(ts73xx_fpga_driver);
+
+MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
+MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
+MODULE_LICENSE("GPL v2");
--
2.9.3
^ permalink raw reply related
* [PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
From: Florian Fainelli @ 2016-12-14 2:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214023553.9377-1-f.fainelli@gmail.com>
Register the TS-7300 FPGA manager device drivers which allows us to load
bitstreams into the on-board Altera Cyclone II FPGA.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 3b39ea353d30..acf72ea670ef 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
.phy_id = 1,
};
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+
+/* Relative to EP93XX_CS1_PHYS_BASE */
+#define TS73XX_FPGA_LOADER_BASE 0x03c00000
+
+static struct resource ts73xx_fpga_resources[] = {
+ {
+ .start = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
+ .end = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ts73xx_fpga_device = {
+ .name = "ts73xx-fpga-mgr",
+ .id = -1,
+ .resource = ts73xx_fpga_resources,
+ .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
+};
+
+#endif
+
static void __init ts72xx_init_machine(void)
{
ep93xx_init_devices();
@@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
platform_device_register(&ts72xx_wdt_device);
ep93xx_register_eth(&ts72xx_eth_data, 1);
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+ if (board_is_ts7300())
+ platform_device_register(&ts73xx_fpga_device);
+#endif
}
MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
--
2.9.3
^ permalink raw reply related
* [PATCH v3 0/2] FPGA: TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series adds support for loading bitstreams into the Altera Cyclone II
connected to an EP9302 on a TS-7300 board.
Changes in v3:
- fix write_init and write_complete signatures
Changes in v2:
- rebased against fpga/for-next
- added defines for configuration bits and delays
- added error mesage if ioremap() fails
- detailed how the configuration through CPLD is done
Florian Fainelli (2):
ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
FPGA: Add TS-7300 FPGA manager
arch/arm/mach-ep93xx/ts72xx.c | 26 +++++++
drivers/fpga/Kconfig | 7 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ts73xx-fpga.c | 163 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 197 insertions(+)
create mode 100644 drivers/fpga/ts73xx-fpga.c
--
2.9.3
^ permalink raw reply
* [PATCH v2 0/2] FPGA: TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214022845.5692-1-f.fainelli@gmail.com>
On 12/13/2016 06:28 PM, Florian Fainelli wrote:
> Hi all,
>
> This patch series adds support for loading bitstreams into the Altera Cyclone II
> connected to an EP9302 on a TS-7300 board.
>
> Changes in v2:
>
> - rebased against fpga/for-next
> - added defines for configuration bits and delays
> - added error mesage if ioremap() fails
> - detailed how the configuration through CPLD is done
I forgot to fix a function signature while rebasing, let me resubmit this.
>
> Florian Fainelli (2):
> ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
> FPGA: Add TS-7300 FPGA manager
>
> arch/arm/mach-ep93xx/ts72xx.c | 26 +++++++
> drivers/fpga/Kconfig | 7 ++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/ts73xx-fpga.c | 162 ++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 196 insertions(+)
> create mode 100644 drivers/fpga/ts73xx-fpga.c
>
--
Florian
^ permalink raw reply
* [PATCH v2 2/2] FPGA: Add TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214022845.5692-1-f.fainelli@gmail.com>
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.
The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/fpga/Kconfig | 7 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ts73xx-fpga.c | 162 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 170 insertions(+)
create mode 100644 drivers/fpga/ts73xx-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2853a4..d9cbef60db80 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
help
FPGA manager driver support for Altera Arria10 SoCFPGA.
+config FPGA_MGR_TS73XX
+ tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+ depends on ARCH_EP93XX && MACH_TS72XX
+ help
+ FPGA manager driver support for the Altera Cyclone II FPGA
+ present on the TS-73xx SBC boards.
+
config FPGA_MGR_ZYNQ_FPGA
tristate "Xilinx Zynq FPGA"
depends on ARCH_ZYNQ || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bcf42a6..a1160169e6d9 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
# FPGA Bridge Drivers
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
new file mode 100644
index 000000000000..c004be5954ae
--- /dev/null
+++ b/drivers/fpga/ts73xx-fpga.c
@@ -0,0 +1,162 @@
+/*
+ * Technologic Systems TS-73xx SBC FPGA loader
+ *
+ * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
+ * TS-7300, heavily based on load_fpga.c in their vendor tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/iopoll.h>
+#include <linux/fpga/fpga-mgr.h>
+
+#define TS73XX_FPGA_DATA_REG 0
+#define TS73XX_FPGA_CONFIG_REG 1
+
+#define TS73XX_FPGA_WRITE_DONE 0x1
+#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
+#define TS73XX_FPGA_RESET 0x2
+#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
+#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
+#define TS73XX_FPGA_LOAD_OK 0x4
+#define TS73XX_FPGA_CONFIG_LOAD 0x8
+
+struct ts73xx_fpga_priv {
+ void __iomem *io_base;
+ struct device *dev;
+};
+
+static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int ts73xx_fpga_write_init(struct fpga_manager *mgr, u32 flags,
+ const char *buf, size_t count)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+
+ /* Reset the FPGA */
+ writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ udelay(TS73XX_FPGA_RESET_LOW_DELAY);
+ writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
+
+ return 0;
+}
+
+static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
+ size_t count)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+ size_t i = 0;
+ int ret;
+ u8 reg;
+
+ while (count--) {
+ ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
+ reg, !(reg & TS73XX_FPGA_WRITE_DONE),
+ 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
+ if (ret < 0)
+ return ret;
+
+ writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
+ i++;
+ }
+
+ usleep_range(1000, 2000);
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ reg |= TS73XX_FPGA_CONFIG_LOAD;
+ writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ usleep_range(1000, 2000);
+
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ reg &= ~TS73XX_FPGA_CONFIG_LOAD;
+ writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+
+ return 0;
+}
+
+static int ts73xx_fpga_write_complete(struct fpga_manager *mgr, u32 flags)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+ u8 reg;
+
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static const struct fpga_manager_ops ts73xx_fpga_ops = {
+ .state = ts73xx_fpga_state,
+ .write_init = ts73xx_fpga_write_init,
+ .write = ts73xx_fpga_write,
+ .write_complete = ts73xx_fpga_write_complete,
+};
+
+static int ts73xx_fpga_probe(struct platform_device *pdev)
+{
+ struct device *kdev = &pdev->dev;
+ struct ts73xx_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ struct resource *res;
+ int err;
+
+ priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = kdev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->io_base = devm_ioremap_resource(kdev, res);
+ if (IS_ERR(priv->io_base)) {
+ dev_err(kdev, "unable to remap registers\n");
+ return PTR_ERR(priv->io_base);
+ }
+
+ err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
+ &ts73xx_fpga_ops, priv);
+ if (err) {
+ dev_err(kdev, "failed to register FPGA manager\n");
+ return err;
+ }
+
+ return err;
+}
+
+static int ts73xx_fpga_remove(struct platform_device *pdev)
+{
+ fpga_mgr_unregister(&pdev->dev);
+
+ return 0;
+}
+
+static struct platform_driver ts73xx_fpga_driver = {
+ .driver = {
+ .name = "ts73xx-fpga-mgr",
+ },
+ .probe = ts73xx_fpga_probe,
+ .remove = ts73xx_fpga_remove,
+};
+module_platform_driver(ts73xx_fpga_driver);
+
+MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
+MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
+MODULE_LICENSE("GPL v2");
--
2.9.3
^ permalink raw reply related
* [PATCH v2 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
From: Florian Fainelli @ 2016-12-14 2:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214022845.5692-1-f.fainelli@gmail.com>
Register the TS-7300 FPGA manager device drivers which allows us to load
bitstreams into the on-board Altera Cyclone II FPGA.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 3b39ea353d30..acf72ea670ef 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
.phy_id = 1,
};
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+
+/* Relative to EP93XX_CS1_PHYS_BASE */
+#define TS73XX_FPGA_LOADER_BASE 0x03c00000
+
+static struct resource ts73xx_fpga_resources[] = {
+ {
+ .start = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
+ .end = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ts73xx_fpga_device = {
+ .name = "ts73xx-fpga-mgr",
+ .id = -1,
+ .resource = ts73xx_fpga_resources,
+ .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
+};
+
+#endif
+
static void __init ts72xx_init_machine(void)
{
ep93xx_init_devices();
@@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
platform_device_register(&ts72xx_wdt_device);
ep93xx_register_eth(&ts72xx_eth_data, 1);
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+ if (board_is_ts7300())
+ platform_device_register(&ts73xx_fpga_device);
+#endif
}
MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
--
2.9.3
^ permalink raw reply related
* [PATCH v2 0/2] FPGA: TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series adds support for loading bitstreams into the Altera Cyclone II
connected to an EP9302 on a TS-7300 board.
Changes in v2:
- rebased against fpga/for-next
- added defines for configuration bits and delays
- added error mesage if ioremap() fails
- detailed how the configuration through CPLD is done
Florian Fainelli (2):
ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
FPGA: Add TS-7300 FPGA manager
arch/arm/mach-ep93xx/ts72xx.c | 26 +++++++
drivers/fpga/Kconfig | 7 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ts73xx-fpga.c | 162 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 196 insertions(+)
create mode 100644 drivers/fpga/ts73xx-fpga.c
--
2.9.3
^ permalink raw reply
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