* [PATCH 2/2] ARM: soft-reboot into same mode that we entered the kernel
From: Russell King @ 2016-12-14 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213113044.GC19985@leverpostej>
When we soft-reboot (eg, kexec) from one kernel into the next, we need
to ensure that we enter the new kernel in the same processor mode as
when we were entered, so that (eg) the new kernel can install its own
hypervisor - the old kernel's hypervisor will have been overwritten.
In order to do this, we need to pass a flag to cpu_reset() so it knows
what to do, and we need to modify the kernel's own hypervisor stub to
allow it to handle a soft-reboot.
As we are always guaranteed to install our own hypervisor if we're
entered in HYP32 mode, and KVM will have moved itself out of the way
on kexec/normal reboot, we can assume that our hypervisor is in place
when we want to kexec, so changing our hypervisor API should not be a
problem.
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/include/asm/proc-fns.h | 4 ++--
arch/arm/kernel/hyp-stub.S | 13 +++++++++++++
arch/arm/kernel/reboot.c | 7 +++++--
arch/arm/mm/proc-v7.S | 12 ++++++++----
4 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 8877ad5ffe10..f2e1af45bd6f 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -43,7 +43,7 @@ extern struct processor {
/*
* Special stuff for a reset
*/
- void (*reset)(unsigned long addr) __attribute__((noreturn));
+ void (*reset)(unsigned long addr, bool hvc) __attribute__((noreturn));
/*
* Idle the processor
*/
@@ -88,7 +88,7 @@ extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
#else
extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
#endif
-extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+extern void cpu_reset(unsigned long addr, bool hvc) __attribute__((noreturn));
/* These three are private to arch/arm/kernel/suspend.c */
extern void cpu_do_suspend(void *);
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index f3e9ba5fb642..82915231c6f8 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -24,6 +24,7 @@
#define HVC_GET_VECTORS 0
#define HVC_SET_VECTORS 1
+#define HVC_SOFT_RESTART 2
#ifndef ZIMAGE
/*
@@ -215,6 +216,10 @@ ENDPROC(__hyp_stub_install_secondary)
mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
b __hyp_stub_exit
+1: teq r0, #HVC_SOFT_RESTART
+ bne 1f
+ bx r3
+
1: mov r0, #-1
__hyp_stub_exit:
@@ -256,6 +261,14 @@ ENTRY(__hyp_set_vectors)
ret lr
ENDPROC(__hyp_set_vectors)
+ENTRY(__hyp_soft_restart)
+ mov r3, r0
+ mov r0, #HVC_SOFT_RESTART
+ __HVC(0)
+ mov r0, r3
+ ret lr
+ENDPROC(__hyp_soft_restart)
+
#ifndef ZIMAGE
.align 2
.L__boot_cpu_mode_offset:
diff --git a/arch/arm/kernel/reboot.c b/arch/arm/kernel/reboot.c
index 3fa867a2aae6..3b2aa9a9fe26 100644
--- a/arch/arm/kernel/reboot.c
+++ b/arch/arm/kernel/reboot.c
@@ -12,10 +12,11 @@
#include <asm/cacheflush.h>
#include <asm/idmap.h>
+#include <asm/virt.h>
#include "reboot.h"
-typedef void (*phys_reset_t)(unsigned long);
+typedef void (*phys_reset_t)(unsigned long, bool);
/*
* Function pointers to optional machine specific functions
@@ -51,7 +52,9 @@ static void __soft_restart(void *addr)
/* Switch to the identity mapping. */
phys_reset = (phys_reset_t)virt_to_idmap(cpu_reset);
- phys_reset((unsigned long)addr);
+
+ /* original stub should be restored by kvm */
+ phys_reset((unsigned long)addr, is_hyp_mode_available());
/* Should never get here. */
BUG();
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d00d52c9de3e..1846ca4255d0 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -53,11 +53,15 @@ ENDPROC(cpu_v7_proc_fin)
.align 5
.pushsection .idmap.text, "ax"
ENTRY(cpu_v7_reset)
- mrc p15, 0, r1, c1, c0, 0 @ ctrl register
- bic r1, r1, #0x1 @ ...............m
- THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
- mcr p15, 0, r1, c1, c0, 0 @ disable MMU
+ mrc p15, 0, r2, c1, c0, 0 @ ctrl register
+ bic r2, r2, #0x1 @ ...............m
+ THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
+ mcr p15, 0, r2, c1, c0, 0 @ disable MMU
isb
+#ifdef CONFIG_ARM_VIRT_EXT
+ teq r1, #0
+ bne __hyp_soft_restart
+#endif
bx r0
ENDPROC(cpu_v7_reset)
.popsection
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] ARM: hyp-stub: improve ABI
From: Russell King @ 2016-12-14 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213113044.GC19985@leverpostej>
Improve the hyp-stub ABI to allow it to do more than just get/set the
vectors. We follow the example in ARM64, where r0 is used as an opcode
with the other registers as an argument.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/kernel/hyp-stub.S | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 15d073ae5da2..f3e9ba5fb642 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -22,6 +22,9 @@
#include <asm/assembler.h>
#include <asm/virt.h>
+#define HVC_GET_VECTORS 0
+#define HVC_SET_VECTORS 1
+
#ifndef ZIMAGE
/*
* For the kernel proper, we need to find out the CPU boot mode long after
@@ -202,9 +205,19 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
ENDPROC(__hyp_stub_install_secondary)
__hyp_stub_do_trap:
- cmp r0, #-1
- mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR
- mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR
+ teq r0, #HVC_GET_VECTORS
+ bne 1f
+ mrc p15, 4, r0, c12, c0, 0 @ get HVBAR
+ b __hyp_stub_exit
+
+1: teq r0, #HVC_SET_VECTORS
+ bne 1f
+ mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
+ b __hyp_stub_exit
+
+1: mov r0, #-1
+
+__hyp_stub_exit:
__ERET
ENDPROC(__hyp_stub_do_trap)
@@ -231,10 +244,14 @@ ENDPROC(__hyp_stub_do_trap)
* initialisation entry point.
*/
ENTRY(__hyp_get_vectors)
- mov r0, #-1
+ mov r0, #HVC_GET_VECTORS
+ __HVC(0)
+ ret lr
ENDPROC(__hyp_get_vectors)
- @ fall through
+
ENTRY(__hyp_set_vectors)
+ mov r1, r0
+ mov r0, #HVC_SET_VECTORS
__HVC(0)
ret lr
ENDPROC(__hyp_set_vectors)
--
2.7.4
^ permalink raw reply related
* [RFC v2 PATCH 0/3] Fix dma_alloc_coherent() and friends for NOMMU
From: Vladimir Murzin @ 2016-12-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <552e7994-31ee-9ec8-4acd-8f37d1a157a4@arm.com>
On 13/12/16 18:32, Robin Murphy wrote:
> On 13/12/16 15:02, Vladimir Murzin wrote:
>> On 13/12/16 14:25, Robin Murphy wrote:
>>> On 13/12/16 14:14, Vladimir Murzin wrote:
>>>> On 13/12/16 14:07, Russell King - ARM Linux wrote:
>>>>> On Tue, Dec 13, 2016 at 01:45:01PM +0000, Vladimir Murzin wrote:
>>>>>> This patch set is trying to address the issue by providing region of
>>>>>> memory suitable for consistent DMA operations. It is supposed that such
>>>>>> region is marked by MPU as non-cacheable. Since we have MPU support in
>>>>>> Linux for R-class only and M-class setting MPU in bootloader, proposed
>>>>>> interface to advertise such memory is via "memdma=size at start" command
>>>>>> line option, to avoid clashing with normal memory (which usually comes
>>>>>> from dts) it'd be safer to use it together with "mem=" command line
>>>>>> option. Meanwhile, I'm open to suggestions for the better way telling
>>>>>> Linux of such memory.
>>>>>
>>>>> For those nommu systems where the MPU is not used, how do they allocate
>>>>> DMA memory without setting aside a chunk of memory?
>>>>>
>>>>> >From what I understand of the current nommu code, it would just use
>>>>> the normal page allocator for DMA memory allocation, so now requiring
>>>>> everything to fit the "nommu has mpu" case seems like it's going to
>>>>> break older nommu.
>>>>>
>>>>
>>>> Probably, it'd be better if we just fallback to dma-noop operations if there
>>>> is no dma region, i.e. assume that platform is coherent. We still need a way
>>>> to tell user that absence of such region can be reason of broken DMA.
>>>
>>> As I mentioned internally, I think it would be worth trying to use CMA
>>> for this, because dma_map_ops are already wired to try that first, and
>>> from what I can see it seems already set up to do precisely this via a
>>> "shared-dma-pool" reserved memory region (see rmem_cma_setup() in
>>> drivers/base/dma-contiguous.c) - mandating that for cached v7-M systems
>>> whilst letting cache-less/non-MPU systems automatically fall back to the
>>> normal page allocator in its absence would seem to solve all 3 cases.
>>
>> Unfortunately,
>>
>> config DMA_CMA
>> bool "DMA Contiguous Memory Allocator"
>> depends on HAVE_DMA_CONTIGUOUS && CMA
>> help
>> ...
>> config CMA
>> bool "Contiguous Memory Allocator"
>> depends on HAVE_MEMBLOCK && MMU
>> select MIGRATION
>>
>> and it blows up if I remove dependecy on MMU :(
>
> Ah yes, fair enough.
>
>> Another option would be drivers/base/dma-coherent.c, but, IIUC, in this case
>> memory is reserved per device exclusively, so I'm in doubt if tiny M-class can
>> afford that...
>
> I think as usual I managed to conflate the two - it was actually
> dma_alloc_from_coherent() I had in mind when I mentioned dma_map_ops. It
> does seem from 7bfa5ab6fa1b that dma-coherent *can* handle multiple
> devices per region, so it wouldn't appear to be too hard to implement a
> default coherent region (possibly specific to ARM_MPU) for all devices
> in a similar manner to the default contiguous region. Either way I do
> still think a reserved memory region in the DT is nicer and probably
> more robust than the command line parameter.
Ok, I'll look at this option in detail.
Thanks
Vladimir
>
> Robin.
>
>>> Other than the allocator issue, though, the rest of the refactoring does
>>> look nice.
>>
>> Thanks for going through it!
>>
>> Cheers
>> Vladimir
>
>
^ permalink raw reply
* [PATCH 1/2] arm64: Add enable/disable d-cache support for purgatory
From: Pratyush Anand @ 2016-12-14 10:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d8f354da-1e61-feaf-f76a-18e90361e98b@redhat.com>
On Wednesday 14 December 2016 03:08 PM, Pratyush Anand wrote:
>
>>
>> I would go as far as to generate the page tables at 'kexec -l' time,
>> and only if
>
> Ok..So you mean that I create a new section which will have page table
> entries mapping physicalmemory represented by remaining section, and
> then purgatory can just enable mmu with page table from that section,
> right? Seems doable. can do that.
I see a problem here. If we create page table as a new segment then,
how can we verify in purgatory that sha for page table is correct? We
need page table before sha verification start,and we can not rely the
page table created by first kernel until it's sha is verified. So a
chicken-egg problem.
I think, creating page table will just take fraction of second and
should be good even in purgatory, What do you say?
~Pratyush
^ permalink raw reply
* [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399
From: Xing Zheng @ 2016-12-14 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481710301-1454-1-git-send-email-zhengxing@rock-chips.com>
From: William wu <wulf@rock-chips.com>
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.
Signed-off-by: William wu <wulf@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++--------
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..228c764 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
- clock-names = "hclk_host0", "hclk_host0_arb";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
+ <&cru SCLK_USBPHY0_480M_SRC>;
+ clock-names = "hclk_host0", "hclk_host0_arb",
+ "usbphy0_480m";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
- clock-names = "hclk_host0", "hclk_host0_arb";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
+ <&cru SCLK_USBPHY0_480M_SRC>;
+ clock-names = "hclk_host0", "hclk_host0_arb",
+ "usbphy0_480m";
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
status = "disabled";
};
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c0000 0x0 0x20000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
- clock-names = "hclk_host1", "hclk_host1_arb";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
+ <&cru SCLK_USBPHY1_480M_SRC>;
+ clock-names = "hclk_host1", "hclk_host1_arb",
+ "usbphy1_480m";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e0000 0x0 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
- clock-names = "hclk_host1", "hclk_host1_arb";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
+ <&cru SCLK_USBPHY1_480M_SRC>;
+ clock-names = "hclk_host1", "hclk_host1_arb",
+ "usbphy1_480m";
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] clk: rockchip: rk3399: export 480M_SRC clocks id for usbphy0/usbphy1
From: Xing Zheng @ 2016-12-14 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481710301-1454-1-git-send-email-zhengxing@rock-chips.com>
This patch exports USBPHYx_480M_SRC clocks for usbphy.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..cf2af4c 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -411,9 +411,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
- GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
+ GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
- GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
+ GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
--
2.7.4
^ permalink raw reply related
* [PATCH 0/3] Add and export clk-480m clocks for ehci and ohci on RK3399
From: Xing Zheng @ 2016-12-14 10:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patches would like to fix the USB suspend block without
the clk-480m clock. Let's add and export them to control them.
Thanks.
William wu (1):
arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399
Xing Zheng (2):
clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clocks id for usbphy0/usbphy1
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++--------
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
include/dt-bindings/clock/rk3399-cru.h | 2 ++
3 files changed, 24 insertions(+), 10 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v7 1/5] ARM: dts: da850: rename the display node label
From: Tomi Valkeinen @ 2016-12-14 9:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481623759-12786-2-git-send-email-bgolaszewski@baylibre.com>
On 13/12/16 12:09, Bartosz Golaszewski wrote:
> The tilcdc node name is 'display' as per the ePAPR 1.1 recommendation.
> The label is also 'display', but change it to 'lcdc' to make it clear
> what the underlying hardware is.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> arch/arm/boot/dts/da850.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
> index 104155d..6b0ef3d 100644
> --- a/arch/arm/boot/dts/da850.dtsi
> +++ b/arch/arm/boot/dts/da850.dtsi
> @@ -458,7 +458,7 @@
> dma-names = "tx", "rx";
> };
>
> - display: display at 213000 {
> + lcdc: display at 213000 {
> compatible = "ti,da850-tilcdc";
> reg = <0x213000 0x1000>;
> interrupts = <52>;
>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tomi
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* [PATCH v7 4/5] ARM: dts: da850-lcdk: add the vga-bridge node
From: Tomi Valkeinen @ 2016-12-14 9:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481623759-12786-5-git-send-email-bgolaszewski@baylibre.com>
On 13/12/16 12:09, Bartosz Golaszewski wrote:
> Add the vga-bridge node to the board DT together with corresponding
> ports and vga connector. This allows to retrieve the edid info from
> the display automatically.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm/boot/dts/da850-lcdk.dts | 51 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tomi
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* [RFT PATCH] ARM64: dts: meson-gxbb: Add reserved memory zone and usable memory range
From: Neil Armstrong @ 2016-12-14 9:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <09bb78ed-c8ec-d21f-d464-16e55c481d4e@gmx.de>
On 12/12/2016 10:22 PM, Heinrich Schuchardt wrote:
> On 12/12/2016 11:18 AM, Neil Armstrong wrote:
>> The Amlogic Meson GXBB secure monitor uses part of the memory space, this
>> patch adds these reserved zones and redefines the usable memory range for
>> each boards.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 2 +-
>> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 21 +++++++++++++++++++++
>> .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 2 +-
>> arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +-
>> arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 +-
>> .../boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts | 2 +-
>> .../boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts | 2 +-
>> .../boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts | 2 +-
>> .../boot/dts/amlogic/meson-gxl-nexbox-a95x.dts | 2 +-
>> .../arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts | 2 +-
>> arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 +-
>> 11 files changed, 31 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
>> index 7a078be..ac40b2d 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
>> @@ -56,7 +56,7 @@
>>
>> memory at 0 {
>> device_type = "memory";
>> - reg = <0x0 0x0 0x0 0x80000000>;
>> + reg = <0x0 0x1000000 0x0 0x7f000000>;
>> };
>>
>> vddio_boot: regulator-vddio_boot {
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
>> index fc033c0..e085588 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
>> @@ -55,6 +55,27 @@
>> #address-cells = <2>;
>> #size-cells = <2>;
>>
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + secos: secos {
>> + reg = <0x0 0x05300000 0x0 0x2000000>;
>> + no-map;
>> + };
>
> Hello Neil,
>
> In
> https://github.com/hardkernel/linux/blob/odroidc2-3.14.y/arch/arm64/boot/dts/meson64_odroidc2.dts
> the secos region does not exist. In linux-next I find no reference to
> the secos label. Where is the consumer of the region defined?
>
>> +
>> + pstore: pstore {
>> + reg = <0x0 0x07300000 0x0 0x100000>;
>> + no-map;
>> + };
>
> In
> https://github.com/hardkernel/linux/blob/odroidc2-3.14.y/arch/arm64/boot/dts/amlogic/gxbb_skt.dts
> and other files pstore uses a different position
> (reg = <0x0 0x20000000 0x0 0x100000>;).
> Why are we moving this?
> Should this region be marked
> compatible = "ramoops"; ?
> Cf. Documentation/devicetree/bindings/reserved-memory/ramoops.txt.
>
> It would be nice if you could add a short description of each reserved
> area to the commit message.
>
> Regards
>
> Heinrich Schuchardt
>
>> +
>> + secmon: secmon {
>> + reg = <0x0 0x10000000 0x0 0x200000>;
>> + no-map;
>> + };
>> + };
>> +
>> cpus {
>> #address-cells = <0x2>;
>> #size-cells = <0x0>;
>
>
Hi Heinrich,
Thanks for testing and for the report,
we are still struggling into finding what are these zones and how to label them correctly.
We need to identify the zones on all boards, the patch I provided works on a non-odroid-c2 and gxm and gxl boards.
Neil
^ permalink raw reply
* [PATCH] arm64: mm: Fix NOMAP page initialization
From: Robert Richter @ 2016-12-14 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9168b603-04aa-4302-3197-00f17fb336bd@huawei.com>
On 12.12.16 17:53:02, Yisheng Xie wrote:
> It seems that memblock_is_memory() is also too strict for early_pfn_valid,
> so what about this patch, which use common pfn_valid as early_pfn_valid
> when CONFIG_HAVE_ARCH_PFN_VALID=y:
> ------------
> diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
> index 0f088f3..9d596f3 100644
> --- a/include/linux/mmzone.h
> +++ b/include/linux/mmzone.h
> @@ -1200,7 +1200,17 @@ static inline int pfn_present(unsigned long pfn)
> #define pfn_to_nid(pfn) (0)
> #endif
>
> +#ifdef CONFIG_HAVE_ARCH_PFN_VALID
> +static inline int early_pfn_valid(unsigned long pfn)
> +{
> + if (pfn_to_section_nr(pfn) >= NR_MEM_SECTIONS)
> + return 0;
> + return valid_section(__nr_to_section(pfn_to_section_nr(pfn)));
> +}
I sent a V2 patch that uses pfn_present(). This only initilizes
sections with memory.
-Robert
> +#define early_pfn_valid early_pfn_valid
> +#else
> #define early_pfn_valid(pfn) pfn_valid(pfn)
> +#endif
> void sparse_init(void);
> #else
> #define sparse_init() do {} while (0)
>
>
>
^ permalink raw reply
* [PATCH] arm/dts: ls1021a: Add dma-coherent property to usb3 node
From: Jerry Huang @ 2016-12-14 9:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479885324-5468-1-git-send-email-jerry.huang@nxp.com>
> -----Original Message-----
> From: Changming Huang [mailto:jerry.huang at nxp.com]
> Sent: Wednesday, November 23, 2016 3:15 PM
> To: robh+dt at kernel.org; mark.rutland at arm.com; linux at armlinux.org.uk
> Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org; Jerry Huang <jerry.huang@nxp.com>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>
> Subject: [PATCH] arm/dts: ls1021a: Add dma-coherent property to usb3 node
>
> This sets dma ops as coherent for usb 3.0 platform device
>
> Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> ---
> arch/arm/boot/dts/ls1021a.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 368e219..81fb4d9 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -627,6 +627,7 @@
> dr_mode = "host";
> snps,quirk-frame-length-adjustment = <0x20>;
> snps,dis_rxdet_inp3_quirk;
> + dma-coherent;
> };
>
> pcie at 3400000 {
> --
How about this property for usb? Any comment for it?
^ permalink raw reply
* [PATCH v2] arm64: mm: Fix NOMAP page initialization
From: Robert Richter @ 2016-12-14 9:42 UTC (permalink / raw)
To: linux-arm-kernel
On ThunderX systems with certain memory configurations we see the
following BUG_ON():
kernel BUG at mm/page_alloc.c:1848!
This happens for some configs with 64k page size enabled. The BUG_ON()
checks if start and end page of a memmap range belongs to the same
zone.
The BUG_ON() check fails if a memory zone contains NOMAP regions. In
this case the node information of those pages is not initialized. This
causes an inconsistency of the page links with wrong zone and node
information for that pages. NOMAP pages from node 1 still point to the
mem zone from node 0 and have the wrong nid assigned.
The reason for the mis-configuration is a change in pfn_valid() which
reports pages marked NOMAP as invalid:
68709f45385a arm64: only consider memblocks with NOMAP cleared for linear mapping
This causes pages marked as nomap being no longer reassigned to the
new zone in memmap_init_zone() by calling __init_single_pfn().
Fixing this by implementing an arm64 specific early_pfn_valid(). This
causes all pages of sections with memory including NOMAP ranges to be
initialized by __init_single_page() and ensures consistency of page
links to zone, node and section.
The HAVE_ARCH_PFN_VALID config option now requires an explicit
definiton of early_pfn_valid() in the same way as pfn_valid(). This
allows a customized implementation of early_pfn_valid() which
redirects to pfn_present() for arm64.
v2:
* Use pfn_present() instead of memblock_is_memory() to support also
non-memory NOMAP holes
Signed-off-by: Robert Richter <rrichter@cavium.com>
---
arch/arm/include/asm/page.h | 1 +
arch/arm64/include/asm/page.h | 2 ++
arch/arm64/mm/init.c | 12 ++++++++++++
include/linux/mmzone.h | 5 ++++-
4 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 4355f0ec44d6..79761bd55f94 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -158,6 +158,7 @@ typedef struct page *pgtable_t;
#ifdef CONFIG_HAVE_ARCH_PFN_VALID
extern int pfn_valid(unsigned long);
+#define early_pfn_valid(pfn) pfn_valid(pfn)
#endif
#include <asm/memory.h>
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 8472c6def5ef..17ceb7435ded 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -49,6 +49,8 @@ typedef struct page *pgtable_t;
#ifdef CONFIG_HAVE_ARCH_PFN_VALID
extern int pfn_valid(unsigned long);
+extern int early_pfn_valid(unsigned long);
+#define early_pfn_valid early_pfn_valid
#endif
#include <asm/memory.h>
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 212c4d1e2f26..bf1f5db11428 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -145,11 +145,23 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
#endif /* CONFIG_NUMA */
#ifdef CONFIG_HAVE_ARCH_PFN_VALID
+
int pfn_valid(unsigned long pfn)
{
return memblock_is_map_memory(pfn << PAGE_SHIFT);
}
EXPORT_SYMBOL(pfn_valid);
+
+/*
+ * We use pfn_present() here to make sure all pages of a section
+ * including NOMAP pages are initialized with __init_single_page().
+ */
+int early_pfn_valid(unsigned long pfn)
+{
+ return pfn_present(pfn);
+}
+EXPORT_SYMBOL(early_pfn_valid);
+
#endif
#ifndef CONFIG_SPARSEMEM
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 0f088f3a2fed..bedcf8a95881 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -1170,12 +1170,16 @@ static inline struct mem_section *__pfn_to_section(unsigned long pfn)
}
#ifndef CONFIG_HAVE_ARCH_PFN_VALID
+
static inline int pfn_valid(unsigned long pfn)
{
if (pfn_to_section_nr(pfn) >= NR_MEM_SECTIONS)
return 0;
return valid_section(__nr_to_section(pfn_to_section_nr(pfn)));
}
+
+#define early_pfn_valid(pfn) pfn_valid(pfn)
+
#endif
static inline int pfn_present(unsigned long pfn)
@@ -1200,7 +1204,6 @@ static inline int pfn_present(unsigned long pfn)
#define pfn_to_nid(pfn) (0)
#endif
-#define early_pfn_valid(pfn) pfn_valid(pfn)
void sparse_init(void);
#else
#define sparse_init() do {} while (0)
--
2.1.4
^ permalink raw reply related
* [PATCH 09/18] arm64: introduce binfmt_elf32.c
From: Yury Norov @ 2016-12-14 9:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205151018.GD14429@e104818-lin.cambridge.arm.com>
On Mon, Dec 05, 2016 at 03:10:19PM +0000, Catalin Marinas wrote:
> On Fri, Oct 21, 2016 at 11:33:08PM +0300, Yury Norov wrote:
> > As we support more than one compat formats, it looks more reasonable
> > to not use fs/compat_binfmt.c. Custom binfmt_elf32.c allows to move aarch32
> > specific definitions there and make code more maintainable and readable.
>
> Can you remind me why we need this patch (rather than using the default
> fs/compat_binfmt_elf.c which you include here anyway)?
https://patchwork.kernel.org/patch/8756121/
This is mostly to avoid runtime checks and hide some re-definitions
for aarch32 from ilp32, to avoid re-re-definition.
>
> > --- /dev/null
> > +++ b/arch/arm64/kernel/binfmt_elf32.c
> > @@ -0,0 +1,31 @@
> > +/*
> > + * Support for AArch32 Linux ELF binaries.
> > + */
> > +
> > +/* AArch32 EABI. */
> > +#define EF_ARM_EABI_MASK 0xff000000
> > +
> > +#define compat_start_thread compat_start_thread
> > +#define COMPAT_SET_PERSONALITY(ex) \
> > +do { \
> > + clear_thread_flag(TIF_32BIT_AARCH64); \
> > + set_thread_flag(TIF_32BIT); \
> > +} while (0)
>
> You introduce this here but it seems to still be present in asm/elf.h.
Hmm... Maybe chunk that delete it from asm/elf.h was dropped at some
rebase. Thank you for the catch. I'll check it again.
Yury
^ permalink raw reply
* [PATCH 1/2] arm64: Add enable/disable d-cache support for purgatory
From: Pratyush Anand @ 2016-12-14 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5838834D.90205@arm.com>
Hi James,
Thanks a lot for your review. Its helpful.
On Saturday 26 November 2016 12:00 AM, James Morse wrote:
> Hi Pratyush,
>
> (CC: Mark, mismatched memory attributes in paragraph 3?)
>
> On 22/11/16 04:32, Pratyush Anand wrote:
>> This patch adds support to enable/disable d-cache, which can be used for
>> faster purgatory sha256 verification.
>
> (I'm not clear why we want the sha256, but that is being discussed elsewhere on
> the thread)
>
>
>> We are supporting only 4K and 64K page sizes. This code will not work if a
>> hardware is not supporting at least one of these page sizes. Therefore,
>> D-cache is disabled by default and enabled only when "enable-dcache" is
>> passed to the kexec().
>
> I don't think the maybe-4K/maybe-64K/maybe-neither logic is needed. It would be
> a lot simpler to only support one page size, which should be 4K as that is what
> UEFI requires. (If there are CPUs that only support one size, I bet its 4K!)
Ok.. So, I will implement a new version after considering that 4K will
always be supported. If 4K is not supported by hw(which is very
unlikely) then there would be no d-cache enabling feature.
>
> I would go as far as to generate the page tables at 'kexec -l' time, and only if
Ok..So you mean that I create a new section which will have page table
entries mapping physicalmemory represented by remaining section, and
then purgatory can just enable mmu with page table from that section,
right? Seems doable. can do that.
> '/sys/firmware/efi' exists to indicate we booted via UEFI. (and therefore must
> support 4K pages). This would keep the purgatory code as simple as possible.
What about reading ID_AA64MMFR0_EL1 instead of /sys/firmware/efi? That
can also tell us that whether 4K is supported or not?
>
> I don't think the performance difference between 4K and 64K page sizes will be
> measurable, is purgatory really performance sensitive code?
I agree, implementing only 4K will make it very simple.
>
>
>> Since this is an identity mapped system, so VA_BITS will be same as max PA
>> bits supported. If VA_BITS <= 42 for 64K and <= 39 for 4K then only one
>> level of page table will be there with block descriptor entries.
>> Otherwise, For 4K mapping, TTBR points to level 0 lookups, which will have
>> only table entries pointing to a level 1 lookup. Level 1 will have only
>> block entries which will map 1GB block. For 64K mapping, TTBR points to
>> level 1 lookups, which will have only table entries pointing to a level 2
>> lookup. Level 2 will have only block entries which will map 512MB block. If
>
> This is more complexity to pick a VA size. Why not always use the maximum 48bit
> VA? The cost is negligible compared to having simpler (easier to review!)
> purgatory code.
>
> By always using 1GB blocks you may be creating aliases with mismatched attributes:
> * If kdump only reserves 128MB, your 1GB mapping will alias whatever else was
> in the same 1GB of address space. This could be a reserved region with some
> other memory attributes.
> * With kdump, we may have failed to park the other CPUs if they are executing
> with interrupts masked and haven't yet handled the smp_send_stop() IPI.
> * One of these other CPUs could be reading/writing in this area as it doesn't
> belong to the kdump reserved area, just happens to be in the same 1GB.
>
> I need to dig through the ARM-ARM to find out what happens next, but I'm pretty
> sure this is well into the "don't do that" territory.
>
>
> It would be much better to force the memory areas to be a multiple of 2MB and
> 2MB aligned, which will allow you to use 2M section mappings for memory, (but
> not the uart). This way we only map regions we had reserved and know are memory.
OK. So, 48 bit VA, 4K page size, 3 level page table with entries in 3rd
level representing 2M block size.
>
>
>> UART base address and RAM addresses are not at least 1GB and 512MB apart
>> for 4K and 64K respectively, then mapping result could be unpredictable. In
>> that case we need to support one more level of granularity, but until
>> someone needs that keep it like this only.
>>
>> We can not allocate dynamic memory in purgatory. Therefore we keep page
>> table allocation size fixed as (3 * MAX_PAGE_SIZE). (page_table) points to
>> first level (having only table entries) and (page_table + MAX_PAGE_SIZE)
>> points to table at next level (having block entries). If index for RAM
>> area and UART area in first table is not same, then we will need another
>> next level table which will be located at (page_table + 2 * MAX_PAGE_SIZE).
>
>
>> diff --git a/purgatory/arch/arm64/cache-asm.S b/purgatory/arch/arm64/cache-asm.S
>> new file mode 100644
>> index 000000000000..bef97ef48888
>> --- /dev/null
>> +++ b/purgatory/arch/arm64/cache-asm.S
>> @@ -0,0 +1,186 @@
>> +/*
>> + * Some of the routines have been copied from Linux Kernel, therefore
>> + * copying the license as well.
>> + *
>> + * Copyright (C) 2001 Deep Blue Solutions Ltd.
>> + * Copyright (C) 2012 ARM Ltd.
>> + * Copyright (C) 2015 Pratyush Anand <panand@redhat.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "cache.h"
>> +
>> +/*
>> + * dcache_line_size - get the minimum D-cache line size from the CTR register.
>> + */
>> + .macro dcache_line_size, reg, tmp
>> + mrs \tmp, ctr_el0 // read CTR
>> + ubfm \tmp, \tmp, #16, #19 // cache line size encoding
>> + mov \reg, #4 // bytes per word
>> + lsl \reg, \reg, \tmp // actual cache line size
>> + .endm
>> +
>> +/*
>> + * inval_cache_range(start, end)
>> + * - x0 - start - start address of region
>> + * - x1 - end - end address of region
>> + */
>> +.globl inval_cache_range
>> +inval_cache_range:
>> + dcache_line_size x2, x3
>> + sub x3, x2, #1
>> + tst x1, x3 // end cache line aligned?
>> + bic x1, x1, x3
>> + b.eq 1f
>> + dc civac, x1 // clean & invalidate D / U line
>> +1: tst x0, x3 // start cache line aligned?
>> + bic x0, x0, x3
>> + b.eq 2f
>> + dc civac, x0 // clean & invalidate D / U line
>> + b 3f
>> +2: dc ivac, x0 // invalidate D / U line
>> +3: add x0, x0, x2
>> + cmp x0, x1
>> + b.lo 2b
>> + dsb sy
>> + ret
>> +/*
>> + * flush_dcache_range(start, end)
>> + * - x0 - start - start address of region
>> + * - x1 - end - end address of region
>> + *
>> + */
>> +.globl flush_dcache_range
>> +flush_dcache_range:
>> + dcache_line_size x2, x3
>> + sub x3, x2, #1
>> + bic x0, x0, x3
>> +1: dc civac, x0 // clean & invalidate D line / unified line
>> + add x0, x0, x2
>> + cmp x0, x1
>> + b.lo 1b
>> + dsb sy
>> + ret
>> +
>> +/*
>> + * invalidate_tlbs_el1()
>> + */
>> +.globl invalidate_tlbs_el1
>> +invalidate_tlbs_el1:
>> + dsb nshst
>> + tlbi vmalle1
>> + dsb nsh
>> + isb
>> + ret
>> +
>> +/*
>> + * invalidate_tlbs_el2()
>> + */
>> +.globl invalidate_tlbs_el2
>> +invalidate_tlbs_el2:
>> + dsb nshst
>> + tlbi alle2
>> + dsb nsh
>> + isb
>> + ret
>> +
>> +/*
>> + * get_mm_feature_reg0_val - Get information about supported MM
>> + * features
>> + */
>> +.globl get_mm_feature_reg0_val
>> +get_mm_feature_reg0_val:
>> + mrs x0, ID_AA64MMFR0_EL1
>> + ret
>> +
>> +/*
>> + * get_current_el - Get information about current exception level
>> + */
>> +.globl get_current_el
>> +get_current_el:
>> + mrs x0, CurrentEL
>> + lsr x0, x0, #2
>> + ret
>> +
>> +/*
>> + * invalidate_icache - Invalidate I-cache
>> + */
>> +.globl invalidate_icache
>> +invalidate_icache:
>> + ic iallu
>> + dsb nsh
>> + isb
>> + ret
>> +
>> +/*
>> + * set_mair_tcr_ttbr_sctlr_el1(page_table, tcr_flags) - sets MAIR, TCR , TTBR and SCTLR registers
>> + * x0 - page_table - Page Table Base
>> + * x1 - tcr_flags - TCR Flags to be set
>> + */
>> +.globl set_mair_tcr_ttbr_sctlr_el1
>> +set_mair_tcr_ttbr_sctlr_el1:
>> + ldr x2, =MEMORY_ATTRIBUTES
>> + msr mair_el1, x2
>> + msr tcr_el1, x1
>> + msr ttbr0_el1, x0
>> + isb
>> + mrs x0, sctlr_el1
>> + ldr x3, =SCTLR_ELx_FLAGS
>> + orr x0, x0, x3
>> + msr sctlr_el1, x0
>> + isb
>> + ret
>> +
>> +/*
>> + * set_mair_tcr_ttbr_sctlr_el2(page_table, tcr_flags) - sets MAIR, TCR , TTBR and SCTLR registers
>> + * x0 - page_table - Page Table Base
>> + * x1 - tcr_flags - TCR Flags to be set
>> + */
>> +.globl set_mair_tcr_ttbr_sctlr_el2
>> +set_mair_tcr_ttbr_sctlr_el2:
>> + ldr x2, =MEMORY_ATTRIBUTES
>> + msr mair_el2, x2
>> + msr tcr_el2, x1
>> + msr ttbr0_el2, x0
>> + isb
>> + mrs x0, sctlr_el2
>> + ldr x3, =SCTLR_ELx_FLAGS
>> + orr x0, x0, x3
>> + msr sctlr_el2, x0
>> + isb
>> + ret
>> +
>> +/*
>> + * reset_sctlr_el1 - disables cache and mmu
>> + */
>> +.globl reset_sctlr_el1
>> +reset_sctlr_el1:
>> + mrs x0, sctlr_el1
>> + bic x0, x0, #SCTLR_ELx_C
>> + bic x0, x0, #SCTLR_ELx_M
>> + msr sctlr_el1, x0
>> + isb
>> + ret
>> +
>> +/*
>> + * reset_sctlr_el2 - disables cache and mmu
>> + */
>> +.globl reset_sctlr_el2
>> +reset_sctlr_el2:
>> + mrs x0, sctlr_el2
>> + bic x0, x0, #SCTLR_ELx_C
>> + bic x0, x0, #SCTLR_ELx_M
>> + msr sctlr_el2, x0
>> + isb
>> + ret
>> diff --git a/purgatory/arch/arm64/cache.c b/purgatory/arch/arm64/cache.c
>> new file mode 100644
>> index 000000000000..3c7e058ccf11
>> --- /dev/null
>> +++ b/purgatory/arch/arm64/cache.c
>> @@ -0,0 +1,330 @@
>> +/*
>> + * Copyright (C) 2015 Pratyush Anand <panand@redhat.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +/* We are supporting only 4K and 64K page sizes. This code will not work if
>> + * a hardware is not supporting at least one of these page sizes.
>> + * Therefore, D-cache is disabled by default and enabled only when
>> + * "enable-dcache" is passed to the kexec().
>> + * Since this is an identity mapped system, so VA_BITS will be same as max
>> + * PA bits supported. If VA_BITS <= 42 for 64K and <= 39 for 4K then only
>> + * one level of page table will be there with block descriptor entries.
>> + * Otherwise, For 4K mapping, TTBR points to level 0 lookups, which will
>> + * have only table entries pointing to a level 1 lookup. Level 1 will have
>> + * only block entries which will map 1GB block.For 64K mapping, TTBR points
>> + * to level 1 lookups, which will have only table entries pointing to a
>> + * level 2 lookup. Level 2 will have only block entries which will map
>> + * 512MB block. If UART base address and RAM addresses are not at least 1GB
>> + * and 512MB apart for 4K and 64K respectively, then mapping result could
>> + * be unpredictable. In that case we need to support one more level of
>> + * granularity, but until someone needs that keep it like this only.
>> + * We can not allocate dynamic memory in purgatory. Therefore we keep page
>> + * table allocation size fixed as (3 * MAX_PAGE_SIZE). (page_table) points
>> + * to first level (having only table entries) and (page_table +
>> + * MAX_PAGE_SIZE) points to table at next level (having block entries). If
>> + * index for RAM area and UART area in first table is not same, then we
>> + * will need another next level table which will be located at (page_table
>> + * + 2 * MAX_PAGE_SIZE).
>> + */
>> +
>> +#include <stdint.h>
>> +#include <string.h>
>> +#include <purgatory.h>
>> +#include "cache.h"
>> +
>> +static uint64_t page_shift;
>> +static uint64_t pgtable_level;
>> +static uint64_t va_bits;
>> +
>> +static uint64_t page_table[PAGE_TABLE_SIZE / sizeof(uint64_t)] __attribute__ ((aligned (MAX_PAGE_SIZE))) = { };
>> +static uint64_t page_table_used;
>> +
>> +#define PAGE_SIZE (1 << page_shift)
>> +/*
>> + * is_4k_page_supported - return true if 4k page is supported else
>> + * false
>> + */
>> +static int is_4k_page_supported(void)
>> +{
>> + return ((get_mm_feature_reg0_val() & ID_AA64MMFR0_TGRAN4_MASK) ==
>> + ID_AA64MMFR0_TGRAN4_SUPPORTED);
>> +}
>> +
>> +/*
>> + * is_64k_page_supported - return true if 64k page is supported else
>> + * false
>> + */
>> +static int is_64k_page_supported(void)
>> +{
>> + return ((get_mm_feature_reg0_val() & ID_AA64MMFR0_TGRAN64_MASK) ==
>> + ID_AA64MMFR0_TGRAN64_SUPPORTED);
>> +}
>> +
>> +/*
>> + * get_ips_bits - return supported IPS bits
>> + */
>> +static uint64_t get_ips_bits(void)
>> +{
>> + return ((get_mm_feature_reg0_val() & ID_AA64MMFR0_PARANGE_MASK) >>
>> + ID_AA64MMFR0_PARANGE_SHIFT);
>> +}
>> +
>> +/*
>> + * get_va_bits - return supported VA bits (For identity mapping VA = PA)
>> + */
>> +static uint64_t get_va_bits(void)
>> +{
>> + uint64_t ips = get_ips_bits();
>> +
>> + switch(ips) {
>> + case ID_AA64MMFR0_PARANGE_48:
>> + return 48;
>> + case ID_AA64MMFR0_PARANGE_44:
>> + return 44;
>> + case ID_AA64MMFR0_PARANGE_42:
>> + return 42;
>> + case ID_AA64MMFR0_PARANGE_40:
>> + return 40;
>> + case ID_AA64MMFR0_PARANGE_36:
>> + return 36;
>> + default:
>> + return 32;
>> + }
>> +}
>> +
>> +/*
>> + * get_section_shift - get block shift for supported page size
>> + */
>> +static uint64_t get_section_shift(void)
>> +{
>> + if (page_shift == 16)
>> + return 29;
>> + else if(page_shift == 12)
>> + return 30;
>> + else
>> + return 0;
>> +}
>> +
>> +/*
>> + * get_section_mask - get section mask for supported page size
>> + */
>> +static uint64_t get_section_mask(void)
>> +{
>> + if (page_shift == 16)
>> + return 0x1FFF;
>> + else if(page_shift == 12)
>> + return 0x1FF;
>> + else
>> + return 0;
>> +}
>> +
>> +/*
>> + * get_pgdir_shift - get pgdir shift for supported page size
>> + */
>> +static uint64_t get_pgdir_shift(void)
>> +{
>> + if (page_shift == 16)
>> + return 42;
>> + else if(page_shift == 12)
>> + return 39;
>> + else
>> + return 0;
>> +}
>> +
>> +/*
>> + * init_page_table - Initializes page table locations
>> + */
>> +
>> +static void init_page_table(void)
>> +{
>> + /*
>> + * Invalidate the page tables to avoid potential dirty cache lines
>> + * being evicted.
>> + */
>
> How do these lines get dirty? arm64_relocate_new_kernel() invalidated these
> pages to PoC before it copied the data. If they were speculatively fetched (I
> don't know the rules of when/how that happens) they may be wrong, but will be
> clean and not written back. If we change them in purgatory, you invalidate again
> from enable_mmu_dcache(). I don't think this is needed.
>
Had taken it from kernel arch/arm64/kernel/head.S.
But anyway, since this part will go to kexec code as you suggested, so
we will not need
it there for sure.
>
>> + inval_cache_range((uint64_t)page_table,
>> + (uint64_t)page_table + PAGE_TABLE_SIZE);
>> + memset(page_table, 0, PAGE_TABLE_SIZE);
>> +}
>> +/*
>> + * create_identity_mapping(start, end, flags)
>> + * start - start address
>> + * end - end address
>> + * flags - MMU Flags for Normal or Device type memory
>> + */
>> +static void create_identity_mapping(uint64_t start, uint64_t end,
>> + uint64_t flags)
>> +{
>> + uint32_t sec_shift, pgdir_shift, sec_mask;
>> + uint64_t desc, s1, e1, s2, e2;
>> + uint64_t *table2;
>> +
>> + s1 = start;
>> + e1 = end - 1;
>> +
>> + sec_shift = get_section_shift();
>> + if (pgtable_level == 1) {
>> + s1 >>= sec_shift;
>> + e1 >>= sec_shift;
>> + do {
>> + desc = s1 << sec_shift;
>> + desc |= flags;
>> + page_table[s1] = desc;
>> + s1++;
>> + } while (s1 <= e1);
>> + } else {
>> + pgdir_shift = get_pgdir_shift();
>> + sec_mask = get_section_mask();
>> + s1 >>= pgdir_shift;
>> + e1 >>= pgdir_shift;
>> + do {
>> + /*
>> + * If there is no table entry then write a new
>> + * entry else, use old entry
>> + */
>> + if (!page_table[s1]) {
>> + table2 = &page_table[(++page_table_used *
>> + MAX_PAGE_SIZE) /
>> + sizeof(uint64_t)];
>> + desc = (uint64_t)table2 | PMD_TYPE_TABLE;
>> + page_table[s1] = desc;
>> + } else {
>> + table2 = (uint64_t *)(page_table[s1] &
>> + ~PMD_TYPE_MASK);
>> + }
>> + s1++;
>> + s2 = start >> sec_shift;
>> + s2 &= sec_mask;
>> + e2 = (end - 1) >> sec_shift;
>> + e2 &= sec_mask;
>> + do {
>> + desc = s2 << sec_shift;
>> + desc |= flags;
>> + table2[s2] = desc;
>> + s2++;
>> + } while (s2 <= e2);
>> + } while (s1 <= e1);
>> + }
>> +}
>
> (I will need to come back to this ... it looks pretty complicated. If you mimic
> Linux's p?d/pte macros it will be more familiar and easier to read.)
Ok, will try to take definitions from head.S, as far as possible.
>
>
>> +
>> +/*
>> + * enable_mmu_dcache: Enable mmu and D-cache in sctlr_el1
>> + */
>> +static void enable_mmu_dcache(void)
>> +{
>> + uint64_t tcr_flags = TCR_FLAGS | TCR_T0SZ(va_bits);
>> +
>> + switch(page_shift) {
>> + case 16:
>> + tcr_flags |= TCR_TG0_64K;
>> + break;
>> + case 12:
>> + tcr_flags |= TCR_TG0_4K;
>> + break;
>> + default:
>> + printf("page shift not supported\n");
>> + return;
>> + }
>> + /*
>> + * Since the page tables have been populated with non-cacheable
>> + * accesses (MMU disabled), invalidate the page tables to remove
>> + * any speculatively loaded cache lines.
>> + */
>> + inval_cache_range((uint64_t)page_table,
>> + (uint64_t)page_table + PAGE_TABLE_SIZE);
>> +
>> + switch(get_current_el()) {
>> + case 2:
>> + invalidate_tlbs_el2();
>> + tcr_flags |= (get_ips_bits() << TCR_PS_EL2_SHIFT);
>> + set_mair_tcr_ttbr_sctlr_el2((uint64_t)page_table, tcr_flags);
>> + break;
>> + case 1:
>> + invalidate_tlbs_el1();
>> + tcr_flags |= (get_ips_bits() << TCR_IPS_EL1_SHIFT);
>> + set_mair_tcr_ttbr_sctlr_el1((uint64_t)page_table, tcr_flags);
>> + break;
>> + default:
>> + return;
>> + }
>
>> + invalidate_icache();
>
> What is this protecting against? We have executed instructions between here and
> setting the I+M bits in set_mair_tcr_ttbr_sctlr_el1(). (so it may be too late)
>
> arm64_relocate_new_kernel() already did 'ic iallu' before it branched into the
> purgatory code. No executable code has been changed or moved since then, so I
> don't think this is necessary.
OK.
>
>
>> +}
>> +
>> +/*
>> + * enable_dcache: Enable D-cache and set appropriate attributes
>> + * ram_start - Start address of RAM
>> + * ram_end - End address of RAM
>> + * uart_base - Base address of uart
>> + */
>> +int enable_dcache(uint64_t ram_start, uint64_t ram_end, uint64_t uart_base)
>> +{
>> + va_bits = get_va_bits();
>> +
>> + page_table_used = 0;
>> + if (is_64k_page_supported()) {
>> + page_shift = 16;
>> + if (va_bits <= 42)
>> + pgtable_level = 1;
>> + else
>> + pgtable_level = 2;
>> + } else if (is_4k_page_supported()) {
>> + page_shift = 12;
>> + if (va_bits <= 39)
>> + pgtable_level = 1;
>> + else
>> + pgtable_level = 2;
>> + } else {
>> + printf("Valid Page Granule not supported by hardware\n");
>> + return -1;
>> + }
>> + init_page_table();
>> + create_identity_mapping(ram_start, ram_end, MM_MMUFLAGS_NORMAL);
>> + printf("Normal identity mapping created from %lx to %lx\n",
>> + ram_start, ram_end);
>> + if (uart_base) {
>> + create_identity_mapping((uint64_t)uart_base,
>> + (uint64_t)uart_base + PAGE_SIZE,
>> + MM_MMUFLAGS_DEVICE);
>> + printf("Device identity mapping created from %lx to %lx\n",
>> + (uint64_t)uart_base,
>> + (uint64_t)uart_base + PAGE_SIZE);
>> + }
>> + enable_mmu_dcache();
>> + printf("Cache Enabled\n");
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * disable_dcache: Disable D-cache and flush RAM locations
>> + * ram_start - Start address of RAM
>> + * ram_end - End address of RAM
>> + */
>> +void disable_dcache(uint64_t ram_start, uint64_t ram_end)
>> +{
>> + switch(get_current_el()) {
>> + case 2:
>> + reset_sctlr_el2();
>> + break;
>> + case 1:
>> + reset_sctlr_el1();
>
> You have C code running between disabling the MMU and cleaning the cache. The
> compiler is allowed to move data on and off the stack in here, but after
> disabling the MMU it will see whatever was on the stack before we turned the MMU
> on. Any data written at the beginning of this function is left in the caches.
>
> I'm afraid this sort of stuff needs to be done in assembly!
All these routines are self coded in assembly even though they are called
from C, so should be safe I think. Anyway, I can keep all of them in
assembly as well.
>
>
>> + break;
>> + default:
>> + return;
>> + }
>> + invalidate_icache();
>> + flush_dcache_range(ram_start, ram_end);
>> + printf("Cache Disabled\n");
>> +}
>> diff --git a/purgatory/arch/arm64/cache.h b/purgatory/arch/arm64/cache.h
>> new file mode 100644
>> index 000000000000..c988020566e3
>> --- /dev/null
>> +++ b/purgatory/arch/arm64/cache.h
>> @@ -0,0 +1,79 @@
>> +#ifndef __CACHE_H__
>> +#define __CACHE_H__
>> +
>> +#define MT_DEVICE_NGNRNE 0
>> +#define MT_DEVICE_NGNRE 1
>> +#define MT_DEVICE_GRE 2
>> +#define MT_NORMAL_NC 3
>> +#define MT_NORMAL 4
>
> You only use two of these. I guess this is so the MAIR value matches the kernel?
OK, can remove others. Yes, they are matching with kernel.
>
>
>> +
>> +#ifndef __ASSEMBLER__
>> +
>> +#define MAX_PAGE_SIZE 0x10000
>> +#define PAGE_TABLE_SIZE (3 * MAX_PAGE_SIZE)
>> +#define ID_AA64MMFR0_TGRAN64_SHIFT 24
>> +#define ID_AA64MMFR0_TGRAN4_SHIFT 28
>> +#define ID_AA64MMFR0_TGRAN64_MASK (0xFUL << ID_AA64MMFR0_TGRAN64_SHIFT)
>> +#define ID_AA64MMFR0_TGRAN4_MASK (0xFUL << ID_AA64MMFR0_TGRAN4_SHIFT)
>> +#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
>> +#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
>> +#define ID_AA64MMFR0_PARANGE_SHIFT 0
>> +#define ID_AA64MMFR0_PARANGE_MASK (0xFUL << ID_AA64MMFR0_PARANGE_SHIFT)
>> +#define ID_AA64MMFR0_PARANGE_48 0x5
>> +#define ID_AA64MMFR0_PARANGE_44 0x4
>> +#define ID_AA64MMFR0_PARANGE_42 0x3
>> +#define ID_AA64MMFR0_PARANGE_40 0x2
>> +#define ID_AA64MMFR0_PARANGE_36 0x1
>> +#define ID_AA64MMFR0_PARANGE_32 0x0
>> +
>> +#define TCR_TG0_64K (1UL << 14)
>> +#define TCR_TG0_4K (0UL << 14)
>> +#define TCR_SHARED_NONE (0UL << 12)
>> +#define TCR_ORGN_WBWA (1UL << 10)
>> +#define TCR_IRGN_WBWA (1UL << 8)
>> +#define TCR_IPS_EL1_SHIFT 32
>> +#define TCR_PS_EL2_SHIFT 16
>> +#define TCR_T0SZ(x) ((unsigned long)(64 - (x)) << 0)
>> +#define TCR_FLAGS (TCR_SHARED_NONE | TCR_ORGN_WBWA | TCR_IRGN_WBWA)
>> +
>> +#define PMD_TYPE_SECT (1UL << 0)
>> +#define PMD_TYPE_TABLE (3UL << 0)
>> +#define PMD_TYPE_MASK 0x3
>> +#define PMD_SECT_AF (1UL << 10)
>> +#define PMD_ATTRINDX(t) ((unsigned long)(t) << 2)
>> +#define PMD_FLAGS_NORMAL (PMD_TYPE_SECT | PMD_SECT_AF)
>> +#define PMD_SECT_PXN (1UL << 53)
>> +#define PMD_SECT_UXN (1UL << 54)
>> +#define PMD_FLAGS_DEVICE (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_PXN | PMD_SECT_UXN)
>> +#define MM_MMUFLAGS_NORMAL PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS_NORMAL
>> +#define MM_MMUFLAGS_DEVICE PMD_ATTRINDX(MT_DEVICE_NGNRE) | PMD_FLAGS_DEVICE
>> +
>> +void disable_dcache(uint64_t ram_start, uint64_t ram_end);
>> +int enable_dcache(uint64_t ram_start, uint64_t ram_end, uint64_t uart_base);
>> +uint64_t get_mm_feature_reg0_val(void);
>> +void inval_cache_range(uint64_t start, uint64_t end);
>> +void flush_dcache_range(uint64_t start, uint64_t end);
>> +uint64_t get_current_el(void);
>> +void set_mair_tcr_ttbr_sctlr_el1(uint64_t page_table, uint64_t tcr_flags);
>> +void set_mair_tcr_ttbr_sctlr_el2(uint64_t page_table, uint64_t tcr_flags);
>> +void invalidate_tlbs_el1(void);
>> +void invalidate_tlbs_el2(void);
>> +void invalidate_icache(void);
>> +void reset_sctlr_el1(void);
>> +void reset_sctlr_el2(void);
>> +#else
>> +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \
>> + (0x04 << (MT_DEVICE_NGNRE*8)) | \
>> + (0x0C << (MT_DEVICE_GRE*8)) | \
>> + (0x44 << (MT_NORMAL_NC*8)) | \
>> + (0xFF << (MT_NORMAL*8)))
>
> Again, you only use two of these.
OK, will remove others.
>
>
>> +/* Common SCTLR_ELx flags. */
>> +#define SCTLR_ELx_I (1 << 12)
>> +#define SCTLR_ELx_C (1 << 2)
>> +#define SCTLR_ELx_M (1 << 0)
>> +
>> +#define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_I)
>> +
>> +#endif
>> +#endif
>>
~Pratyush
^ permalink raw reply
* [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33
From: Maxime Ripard @ 2016-12-14 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <306991481662454@web33j.yandex.ru>
On Wed, Dec 14, 2016 at 04:54:14AM +0800, Icenowy Zheng wrote:
>
>
> 13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote:
> >> ?The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
> >> ?be changeable by changing the rate of PLL_CPUX.
> >>
> >> ?Add CLK_SET_RATE_PARENT flag to this clock.
> >>
> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >
> > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Excuse me, have you merged this patch?
Yes, sorry, that's what I meant :)
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 2/2] arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA
From: Ard Biesheuvel @ 2016-12-14 9:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481706707-6211-1-git-send-email-ard.biesheuvel@linaro.org>
The NUMA code may get confused by the presence of NOMAP regions within
zones, resulting in spurious BUG() checks where the node id deviates
from the containing zone's node id.
Since the kernel has no business reasoning about node ids of pages it
does not own in the first place, enable CONFIG_HOLES_IN_ZONE to ensure
that such pages are disregarded.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 111742126897..0472afe64d55 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -614,6 +614,10 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
def_bool y
depends on NUMA
+config HOLES_IN_ZONE
+ def_bool y
+ depends on NUMA
+
source kernel/Kconfig.preempt
source kernel/Kconfig.hz
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] mm: don't dereference struct page fields of invalid pages
From: Ard Biesheuvel @ 2016-12-14 9:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481706707-6211-1-git-send-email-ard.biesheuvel@linaro.org>
The VM_BUG_ON() check in move_freepages() checks whether the node
id of a page matches the node id of its zone. However, it does this
before having checked whether the struct page pointer refers to a
valid struct page to begin with. This is guaranteed in most cases,
but may not be the case if CONFIG_HOLES_IN_ZONE=y.
So reorder the VM_BUG_ON() with the pfn_valid_within() check.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
mm/page_alloc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index f64e7bcb43b7..4e298e31fa86 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -1864,14 +1864,14 @@ int move_freepages(struct zone *zone,
#endif
for (page = start_page; page <= end_page;) {
- /* Make sure we are not inadvertently changing nodes */
- VM_BUG_ON_PAGE(page_to_nid(page) != zone_to_nid(zone), page);
-
if (!pfn_valid_within(page_to_pfn(page))) {
page++;
continue;
}
+ /* Make sure we are not inadvertently changing nodes */
+ VM_BUG_ON_PAGE(page_to_nid(page) != zone_to_nid(zone), page);
+
if (!PageBuddy(page)) {
page++;
continue;
--
2.7.4
^ permalink raw reply related
* [PATCH 0/2] arm64: numa: fix spurious BUG() on NOMAP regions
From: Ard Biesheuvel @ 2016-12-14 9:11 UTC (permalink / raw)
To: linux-arm-kernel
This fixes the issue reported by Robert Richter where the fact that
the node id of struct pages covered by NOMAP regions is not initialized,
triggering a VM_BUG_ON() in the mm code.
I know that this approach is the least preferred option by Robert, but it
has been used successfully in the downstream Linaro Enterprise kernel,
running on HiSilicon D05, which suffered from the same issue as Cavium
ThunderX where it was originally reported.
Given that the other proposed solutions either fail to solve the issue
completely, or cause regressions in other code (hibernate), I think this
issue is appropriate for merging now, and backported to -stable. If there
are performance concerns, we can try to improve on this solution, which
could include reverting patch #2 altogether, for all I care.
Patch #1 fixes a bug in the generic mm code where a struct page is
dereferenced before pfn_valid() is called. This should probably go to
stable regardless of where the arm64 discussion goes.
Patch #2 enables CONFIG_HOLES_IN_ZONE for arm64 numa, causing the kernel
to no longer assume that all pages in a zone have valid struct pages
associated with them.
Ard Biesheuvel (2):
mm: don't dereference struct page fields of invalid pages
arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA
arch/arm64/Kconfig | 4 ++++
mm/page_alloc.c | 6 +++---
2 files changed, 7 insertions(+), 3 deletions(-)
--
2.7.4
^ permalink raw reply
* mmc: core: complete/wait_for_completion performance
From: Jörg Krause @ 2016-12-14 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <123257138.400786.e58aee3b-9fc2-4b39-a030-c2409c5b92fc.open-xchange@email.1und1.de>
Hi Stefan,
On Wed, 2016-12-07 at 20:23 +0100, Stefan Wahren wrote:
> Hi J?rg,
>
> > J?rg Krause <joerg.krause@embedded.rocks> hat am 7. Dezember 2016
> > um 08:32
> > geschrieben:
> >
> >
> > Hit Stefan,
> >
> > On Sat, 2016-11-26 at 20:10 +0100, Stefan Wahren wrote:
> > > Hi J?rg,
> > >
> > > > J?rg Krause <joerg.krause@embedded.rocks> hat am 20. November
> > > > 2016
> > > > um 20:10
> > > > geschrieben:
> > > >
> > > >
> > > > On Sun, 2016-11-20 at 16:44 +0100, Stefan Wahren wrote:
> > > > > > J?rg Krause <joerg.krause@embedded.rocks> hat am 20.
> > > > > > November
> > > > > > 2016
> > > > > > um 15:42
> > > > > > geschrieben:
> > > > > >
> > > > > >
> > > > > > Hi Stefan,
> > > > > >
> > > > > > On Sun, 2016-11-20 at 14:28 +0100, Stefan Wahren wrote:
> > > > > > > Hi J?rg,
> > > > > > >
> > > > > > > > J?rg Krause <joerg.krause@embedded.rocks> hat am 20.
> > > > > > > > November
> > > > > > > > 2016
> > > > > > > > um 13:27
> > > > > > > > geschrieben:
> > > > > > > >
> > > > > > > >
> > > > > > > > Hi,
> > > > > > > >
> > > > > > > > I started the discussion on this mailing list in
> > > > > > > > another
> > > > > > > > thread
> > > > > > > > [1],
> > > > > > > > but I'd like to move it to a new thread, because it
> > > > > > > > might
> > > > > > > > be
> > > > > > > > mmc
> > > > > > > > specific.
> > > > > > > >
> > > > > > > > The issue is that I am noticed low wifi network
> > > > > > > > throughput
> > > > > > > > on
> > > > > > > > an
> > > > > > > > i.MX28
> > > > > > > > board with the mainline kernel (v4.7.10, about 6 Mbps)
> > > > > > > > compared
> > > > > > > > to
> > > > > > > > the
> > > > > > > > vendor kernel (Freescale v2.6.35.3, about 20 Mbps). The
> > > > > > > > wifi
> > > > > > > > chip
> > > > > > > > is
> > > > > > > > attached using the SDIO interface.
> > > > > > > >
> > > > > > > > I started investigation where the bottleneck in the
> > > > > > > > mainline
> > > > > > > > kernel?might come from. Therefore I checked that the
> > > > > > > > configs
> > > > > > > > and
> > > > > > > > settings for the interfaces and drivers are the same.
> > > > > > > > They
> > > > > > > > are.
> > > > > > >
> > > > > > > so you're not using the mxs_defconfig settings anymore?
> > > > > >
> > > > > > No, I changed the settings.
> > > > > >
> > > > >
> > > > > What happens to performance to if you change the following
> > > > > settings
> > > > > to the same
> > > > > like in mxs_defconfig?
> > > > >
> > > > > CONFIG_PREEMPT_VOLUNTARY=y
> > > > > CONFIG_DEFAULT_IOSCHED="noop"
> > > >
> > > > No much change at all. The time difference between complete()
> > > > and
> > > > wait_for_complete() decreases in best case to 110 us, but also
> > > > varies
> > > > to above 130 us.
> > >
> > > just a weird idea. Did you tried to add MMC_CAP_CMD23 into the
> > > caps
> > > [1]?
> > >
> > > [1] - http://lxr.free-electrons.com/source/drivers/mmc/host/mxs-m
> > > mc.c
> > > ?v=4.8#L642
> >
> > I tried, but it did not improved the timing or throughput. However,
> > many thanks for the input.
> >
> > J?rg
>
> did you try cyclictest [1]?
Not yet. Not sure what to measure and which values to compare here.
>
> Beside the time for a request the amount of requests for the complete
> iperf test
> would we interesting. Maybe there are retries.
>
> I'm still interested in your PIO mode patches for mxs-mmc even
> without clean up.
Actually, the patch does not implement a PIO mode, but drops DMA and
uses polling instead. I've attached the patch.
> [1] - https://git.kernel.org/cgit/utils/rt-tests/rt-tests.git/
Best regards
J?rg
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^ permalink raw reply
* [PATCH linux v1 4/4] arm: dts: Add dt-binding to support seven segment display on zaius
From: Joel Stanley @ 2016-12-14 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481702104-8617-5-git-send-email-jaghu@google.com>
Hello Jagha,
On Wed, Dec 14, 2016 at 6:25 PM, Jaghathiswari Rankappagounder
Natarajan <jaghu@google.com> wrote:
> Add clock, data and clear signal GPIO lines to control seven segment display on
> zaius platform.
>
> Signed-off-by: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
The Zaius device tree is not upstream. I suggest you submit it through
the Aspeed maintainer's tree (me!) for inclusion in the next merge
window.
For the time being, drop this patch from your series as it will not
apply to the upstream kernel.
As a general rule make sure you're basing the patches you send
upstream on a tag from an upstream tree. Linus' v4.9 tag would be the
best one at this point in time.
Cheers,
Joel
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> index 8ef4ece..ccb8147 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> @@ -43,6 +43,14 @@
> gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>;
> };
> };
> +
> + seven-seg-disp {
> + compatible = "seven-seg-gpio-dev";
> + refresh-interval-ms = "1000";
> + clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>;
> + data-gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
> + clear-gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
> + };
> };
>
> &fmc {
> --
> 2.8.0.rc3.226.g39d4020
>
^ permalink raw reply
* [PATCH linux v1 4/4] arm: dts: Add dt-binding to support seven segment display on zaius
From: Arnd Bergmann @ 2016-12-14 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3917905.e4iOqADnVQ@wuerfel>
On Wednesday, December 14, 2016 9:55:47 AM CET Arnd Bergmann wrote:
> According to your introductory mail, the interface is assumed to be
> a 74HC164. Should we use that ID in the compatible string?
>
> We can always add other strings later if we want to support multiple
> wire formats.
Actually, looking up 74hc164, that seems to be a gpio expander,
so maybe a more flexible way to do the same is to put a driver
for the expander into drivers/gpio/ and have the main driver
access the outputs of that using the gpiolib interface.
Arnd
^ permalink raw reply
* [PATCH] ARM: dts: dra72-evm-tps65917: Add voltage supplies to usb_phy, mmc, dss
From: Lokesh Vutla @ 2016-12-14 8:57 UTC (permalink / raw)
To: linux-arm-kernel
Commit 5d080aa30681 ("ARM: dts: dra72: Add separate dtsi for tps65917")
added a separate dtsi for dra72-evm-tps65917 moving all the voltage supplies
to this file. But it missed adding voltage supplies to usb_phy, mmc,
dss and deleted from dra72-evm-common.dtsi. Adding the voltage supply
phandles to these nodes in dra72-evm-tps65917.dtsi
Fixes: 5d080aa30681 ("ARM: dts: dra72: Add separate dtsi for tps65917")
Reported-by: Carlos Hernandez <ceh@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
Logs:
- DRA72-evm revC: http://pastebin.ubuntu.com/23627665/
- DRA72-evm revB: http://pastebin.ubuntu.com/23627658/
arch/arm/boot/dts/dra72-evm-tps65917.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
index ee6dac44edf1..e6df676886c0 100644
--- a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
@@ -132,3 +132,19 @@
ti,palmas-long-press-seconds = <6>;
};
};
+
+&usb2_phy1 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&dss {
+ vdda_video-supply = <&ldo5_reg>;
+};
+
+&mmc1 {
+ vmmc_aux-supply = <&ldo1_reg>;
+};
--
2.11.0
^ permalink raw reply related
* [PATCH linux v1 4/4] arm: dts: Add dt-binding to support seven segment display on zaius
From: Arnd Bergmann @ 2016-12-14 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481702104-8617-5-git-send-email-jaghu@google.com>
On Tuesday, December 13, 2016 11:55:04 PM CET Jaghathiswari Rankappagounder Natarajan wrote:
> Add clock, data and clear signal GPIO lines to control seven segment display on
> zaius platform.
>
> Signed-off-by: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> index 8ef4ece..ccb8147 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> @@ -43,6 +43,14 @@
> gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>;
> };
> };
> +
> + seven-seg-disp {
> + compatible = "seven-seg-gpio-dev";
> + refresh-interval-ms = "1000";
> + clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>;
> + data-gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
> + clear-gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
> + };
> };
According to your introductory mail, the interface is assumed to be
a 74HC164. Should we use that ID in the compatible string?
We can always add other strings later if we want to support multiple
wire formats.
Arnd
^ permalink raw reply
* [PATCH v9 4/4] vcodec: mediatek: Add Maintainers entry for Mediatek JPEG driver
From: Rick Chang @ 2016-12-14 8:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481702690-10476-1-git-send-email-rick.chang@mediatek.com>
Signed-off-by: Rick Chang <rick.chang@mediatek.com>
Signed-off-by: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
Signed-off-by: Bin Liu <bin.liu@mediatek.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 93e9f42..6f68fb6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7818,6 +7818,13 @@ L: netdev at vger.kernel.org
S: Maintained
F: drivers/net/ethernet/mediatek/
+MEDIATEK JPEG DRIVER
+M: Rick Chang <rick.chang@mediatek.com>
+M: Bin Liu <bin.liu@mediatek.com>
+S: Supported
+F: drivers/media/platform/mtk-jpeg/
+F: Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
+
MEDIATEK MEDIA DRIVER
M: Tiffany Lin <tiffany.lin@mediatek.com>
M: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
--
1.9.1
^ permalink raw reply related
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