* [PATCH v4 1/4] mtd: lart: Rename partition defines to be prefixed with PART_
From: Florian Fainelli @ 2016-12-26 20:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161226203842.19457-1-f.fainelli@gmail.com>
In preparation for defining KERNEL_START on ARM, rename KERNEL_START to
PART_KERNEL_START, and to be consistent, do this for all
partition-related constants.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/mtd/devices/lart.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/devices/lart.c b/drivers/mtd/devices/lart.c
index 82bd00af5cc3..268aae45b514 100644
--- a/drivers/mtd/devices/lart.c
+++ b/drivers/mtd/devices/lart.c
@@ -75,18 +75,18 @@ static char module_name[] = "lart";
/* blob */
#define NUM_BLOB_BLOCKS FLASH_NUMBLOCKS_16m_PARAM
-#define BLOB_START 0x00000000
-#define BLOB_LEN (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
+#define PART_BLOB_START 0x00000000
+#define PART_BLOB_LEN (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
/* kernel */
#define NUM_KERNEL_BLOCKS 7
-#define KERNEL_START (BLOB_START + BLOB_LEN)
-#define KERNEL_LEN (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
+#define PART_KERNEL_START (PART_BLOB_START + PART_BLOB_LEN)
+#define PART_KERNEL_LEN (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
/* initial ramdisk */
#define NUM_INITRD_BLOCKS 24
-#define INITRD_START (KERNEL_START + KERNEL_LEN)
-#define INITRD_LEN (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
+#define PART_INITRD_START (PART_KERNEL_START + PART_KERNEL_LEN)
+#define PART_INITRD_LEN (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
/*
* See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
@@ -587,20 +587,20 @@ static struct mtd_partition lart_partitions[] = {
/* blob */
{
.name = "blob",
- .offset = BLOB_START,
- .size = BLOB_LEN,
+ .offset = PART_BLOB_START,
+ .size = PART_BLOB_LEN,
},
/* kernel */
{
.name = "kernel",
- .offset = KERNEL_START, /* MTDPART_OFS_APPEND */
- .size = KERNEL_LEN,
+ .offset = PART_KERNEL_START, /* MTDPART_OFS_APPEND */
+ .size = PART_KERNEL_LEN,
},
/* initial ramdisk / file system */
{
.name = "file system",
- .offset = INITRD_START, /* MTDPART_OFS_APPEND */
- .size = INITRD_LEN, /* MTDPART_SIZ_FULL */
+ .offset = PART_INITRD_START, /* MTDPART_OFS_APPEND */
+ .size = PART_INITRD_LEN, /* MTDPART_SIZ_FULL */
}
};
#define NUM_PARTITIONS ARRAY_SIZE(lart_partitions)
--
2.9.3
^ permalink raw reply related
* [PATCH v4 2/4] ARM: Define KERNEL_START and KERNEL_END
From: Florian Fainelli @ 2016-12-26 20:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161226203842.19457-1-f.fainelli@gmail.com>
In preparation for adding CONFIG_DEBUG_VIRTUAL support, define a set of
common constants: KERNEL_START and KERNEL_END which abstract
CONFIG_XIP_KERNEL vs. !CONFIG_XIP_KERNEL. Update the code where
relevant.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/include/asm/memory.h | 7 +++++++
arch/arm/mm/init.c | 7 ++-----
arch/arm/mm/mmu.c | 6 +-----
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 76cbd9c674df..bee7511c5098 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -111,6 +111,13 @@
#endif /* !CONFIG_MMU */
+#ifdef CONFIG_XIP_KERNEL
+#define KERNEL_START _sdata
+#else
+#define KERNEL_START _stext
+#endif
+#define KERNEL_END _end
+
/*
* We fix the TCM memories max 32 KiB ITCM resp DTCM at these
* locations
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 370581aeb871..c87d0d5b65f2 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -230,11 +230,8 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
void __init arm_memblock_init(const struct machine_desc *mdesc)
{
/* Register the kernel text, kernel data and initrd with memblock. */
-#ifdef CONFIG_XIP_KERNEL
- memblock_reserve(__pa(_sdata), _end - _sdata);
-#else
- memblock_reserve(__pa(_stext), _end - _stext);
-#endif
+ memblock_reserve(__pa(KERNEL_START), _end - KERNEL_START);
+
#ifdef CONFIG_BLK_DEV_INITRD
/* FDT scan will populate initrd_start */
if (initrd_start && !phys_initrd_size) {
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4001dd15818d..f0fd1a2db036 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1437,11 +1437,7 @@ static void __init kmap_init(void)
static void __init map_lowmem(void)
{
struct memblock_region *reg;
-#ifdef CONFIG_XIP_KERNEL
- phys_addr_t kernel_x_start = round_down(__pa(_sdata), SECTION_SIZE);
-#else
- phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
-#endif
+ phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
/* Map all the lowmem memory banks. */
--
2.9.3
^ permalink raw reply related
* [PATCH v4 3/4] ARM: Add support for CONFIG_DEBUG_VIRTUAL
From: Florian Fainelli @ 2016-12-26 20:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161226203842.19457-1-f.fainelli@gmail.com>
x86 has an option: CONFIG_DEBUG_VIRTUAL to do additional checks on
virt_to_phys calls. The goal is to catch users who are calling
virt_to_phys on non-linear addresses immediately. This includes caller
using __virt_to_phys() on image addresses instead of __pa_symbol(). This
is a generally useful debug feature to spot bad code (particulary in
drivers).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/memory.h | 16 +++++++++++--
arch/arm/mm/Makefile | 1 +
arch/arm/mm/physaddr.c | 55 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 71 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mm/physaddr.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b5d529fdffab..5e66173c5787 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2,6 +2,7 @@ config ARM
bool
default y
select ARCH_CLOCKSOURCE_DATA
+ select ARCH_HAS_DEBUG_VIRTUAL
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index bee7511c5098..d90300193adf 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -213,7 +213,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
: "r" (x), "I" (__PV_BITS_31_24) \
: "cc")
-static inline phys_addr_t __virt_to_phys(unsigned long x)
+static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x)
{
phys_addr_t t;
@@ -245,7 +245,7 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
#define PHYS_OFFSET PLAT_PHYS_OFFSET
#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
-static inline phys_addr_t __virt_to_phys(unsigned long x)
+static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x)
{
return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET;
}
@@ -261,6 +261,16 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \
PHYS_PFN_OFFSET)
+#define __pa_symbol_nodebug(x) __virt_to_phys_nodebug((x))
+
+#ifdef CONFIG_DEBUG_VIRTUAL
+extern phys_addr_t __virt_to_phys(unsigned long x);
+extern phys_addr_t __phys_addr_symbol(unsigned long x);
+#else
+#define __virt_to_phys(x) __virt_to_phys_nodebug(x)
+#define __phys_addr_symbol(x) __pa_symbol_nodebug(x)
+#endif
+
/*
* These are *only* valid on the kernel direct mapped RAM memory.
* Note: Drivers should NOT use these. They are the wrong
@@ -283,9 +293,11 @@ static inline void *phys_to_virt(phys_addr_t x)
* Drivers should NOT use these either.
*/
#define __pa(x) __virt_to_phys((unsigned long)(x))
+#define __pa_symbol(x) __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0))
#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
#define pfn_to_kaddr(pfn) __va((phys_addr_t)(pfn) << PAGE_SHIFT)
+
extern long long arch_phys_to_idmap_offset;
/*
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index e8698241ece9..b3dea80715b4 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -14,6 +14,7 @@ endif
obj-$(CONFIG_ARM_PTDUMP) += dump.o
obj-$(CONFIG_MODULES) += proc-syms.o
+obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
obj-$(CONFIG_HIGHMEM) += highmem.o
diff --git a/arch/arm/mm/physaddr.c b/arch/arm/mm/physaddr.c
new file mode 100644
index 000000000000..f10bdcbcb155
--- /dev/null
+++ b/arch/arm/mm/physaddr.c
@@ -0,0 +1,55 @@
+#include <linux/bug.h>
+#include <linux/export.h>
+#include <linux/types.h>
+#include <linux/mmdebug.h>
+#include <linux/mm.h>
+
+#include <asm/sections.h>
+#include <asm/memory.h>
+#include <asm/fixmap.h>
+#include <asm/dma.h>
+
+#include "mm.h"
+
+static inline bool __virt_addr_valid(unsigned long x)
+{
+ /* high_memory does not get immediately defined, and there
+ * are early callers of __pa() against PAGE_OFFSET
+ */
+ if (!high_memory && x >= PAGE_OFFSET)
+ return true;
+
+ if (high_memory && x >= PAGE_OFFSET && x < (unsigned long)high_memory)
+ return true;
+
+ /* ARM uses the default per-CPU allocation routing which forces us to
+ * have an explicit check here to avoid a false positive
+ */
+ if (x == MAX_DMA_ADDRESS)
+ return true;
+
+ return false;
+}
+
+phys_addr_t __virt_to_phys(unsigned long x)
+{
+ WARN(!__virt_addr_valid(x),
+ "virt_to_phys used for non-linear address: %pK (%pS)\n",
+ (void *)x,
+ (void *)x);
+
+ return __virt_to_phys_nodebug(x);
+}
+EXPORT_SYMBOL(__virt_to_phys);
+
+phys_addr_t __phys_addr_symbol(unsigned long x)
+{
+ /* This is bounds checking against the kernel image only.
+ * __pa_symbol should only be used on kernel symbol addresses.
+ */
+ VIRTUAL_BUG_ON(x < (unsigned long)KERNEL_START ||
+ x > (unsigned long)KERNEL_END);
+
+ return __pa_symbol_nodebug(x);
+}
+EXPORT_SYMBOL(__phys_addr_symbol);
--
2.9.3
^ permalink raw reply related
* [PATCH v4 4/4] ARM: treewide: Replace uses of virt_to_phys with __pa_symbol
From: Florian Fainelli @ 2016-12-26 20:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161226203842.19457-1-f.fainelli@gmail.com>
All low-level PM/SMP code using virt_to_phys() should actually use
__pa_symbol() against kernel symbols. Update code where relevant to move
away from virt_to_phys().
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/common/mcpm_entry.c | 12 ++++++------
arch/arm/mach-alpine/platsmp.c | 2 +-
arch/arm/mach-axxia/platsmp.c | 2 +-
arch/arm/mach-bcm/bcm63xx_smp.c | 2 +-
arch/arm/mach-bcm/platsmp-brcmstb.c | 2 +-
arch/arm/mach-bcm/platsmp.c | 4 ++--
arch/arm/mach-berlin/platsmp.c | 2 +-
arch/arm/mach-exynos/firmware.c | 4 ++--
arch/arm/mach-exynos/mcpm-exynos.c | 2 +-
arch/arm/mach-exynos/platsmp.c | 4 ++--
arch/arm/mach-exynos/pm.c | 6 +++---
arch/arm/mach-exynos/suspend.c | 6 +++---
arch/arm/mach-hisi/platmcpm.c | 2 +-
arch/arm/mach-hisi/platsmp.c | 6 +++---
arch/arm/mach-imx/platsmp.c | 2 +-
arch/arm/mach-imx/pm-imx6.c | 2 +-
arch/arm/mach-imx/src.c | 2 +-
arch/arm/mach-mediatek/platsmp.c | 2 +-
arch/arm/mach-mvebu/pm.c | 2 +-
arch/arm/mach-mvebu/pmsu.c | 2 +-
arch/arm/mach-mvebu/system-controller.c | 2 +-
arch/arm/mach-omap2/control.c | 8 ++++----
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 8 ++++----
arch/arm/mach-omap2/omap-smp.c | 4 ++--
arch/arm/mach-prima2/platsmp.c | 2 +-
arch/arm/mach-prima2/pm.c | 2 +-
arch/arm/mach-pxa/palmz72.c | 2 +-
arch/arm/mach-pxa/pxa25x.c | 2 +-
arch/arm/mach-pxa/pxa27x.c | 2 +-
arch/arm/mach-pxa/pxa3xx.c | 2 +-
arch/arm/mach-realview/platsmp-dt.c | 2 +-
arch/arm/mach-rockchip/platsmp.c | 4 ++--
arch/arm/mach-rockchip/pm.c | 2 +-
arch/arm/mach-s3c24xx/mach-jive.c | 2 +-
arch/arm/mach-s3c24xx/pm-s3c2410.c | 2 +-
arch/arm/mach-s3c24xx/pm-s3c2416.c | 2 +-
arch/arm/mach-s3c64xx/pm.c | 2 +-
arch/arm/mach-s5pv210/pm.c | 2 +-
arch/arm/mach-sa1100/pm.c | 2 +-
arch/arm/mach-shmobile/platsmp-apmu.c | 6 +++---
arch/arm/mach-shmobile/platsmp-scu.c | 4 ++--
arch/arm/mach-socfpga/platsmp.c | 4 ++--
arch/arm/mach-spear/platsmp.c | 2 +-
arch/arm/mach-sti/platsmp.c | 2 +-
arch/arm/mach-sunxi/platsmp.c | 4 ++--
arch/arm/mach-tango/platsmp.c | 2 +-
arch/arm/mach-tango/pm.c | 2 +-
arch/arm/mach-tegra/reset.c | 4 ++--
arch/arm/mach-ux500/platsmp.c | 2 +-
arch/arm/mach-vexpress/dcscb.c | 2 +-
arch/arm/mach-vexpress/platsmp.c | 2 +-
arch/arm/mach-vexpress/tc2_pm.c | 4 ++--
arch/arm/mach-zx/platsmp.c | 4 ++--
arch/arm/mach-zynq/platsmp.c | 2 +-
54 files changed, 84 insertions(+), 84 deletions(-)
diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
index a923524d1040..cf062472e07b 100644
--- a/arch/arm/common/mcpm_entry.c
+++ b/arch/arm/common/mcpm_entry.c
@@ -144,7 +144,7 @@ extern unsigned long mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr)
{
- unsigned long val = ptr ? virt_to_phys(ptr) : 0;
+ unsigned long val = ptr ? __pa_symbol(ptr) : 0;
mcpm_entry_vectors[cluster][cpu] = val;
sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
}
@@ -299,8 +299,8 @@ void mcpm_cpu_power_down(void)
* the kernel as if the power_up method just had deasserted reset
* on the CPU.
*/
- phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
- phys_reset(virt_to_phys(mcpm_entry_point));
+ phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+ phys_reset(__pa_symbol(mcpm_entry_point));
/* should never get here */
BUG();
@@ -388,8 +388,8 @@ static int __init nocache_trampoline(unsigned long _arg)
__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
__mcpm_cpu_down(cpu, cluster);
- phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
- phys_reset(virt_to_phys(mcpm_entry_point));
+ phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+ phys_reset(__pa_symbol(mcpm_entry_point));
BUG();
}
@@ -449,7 +449,7 @@ int __init mcpm_sync_init(
sync_cache_w(&mcpm_sync);
if (power_up_setup) {
- mcpm_power_up_setup_phys = virt_to_phys(power_up_setup);
+ mcpm_power_up_setup_phys = __pa_symbol(power_up_setup);
sync_cache_w(&mcpm_power_up_setup_phys);
}
diff --git a/arch/arm/mach-alpine/platsmp.c b/arch/arm/mach-alpine/platsmp.c
index dd77ea25e7ca..6dc6d491f88a 100644
--- a/arch/arm/mach-alpine/platsmp.c
+++ b/arch/arm/mach-alpine/platsmp.c
@@ -27,7 +27,7 @@ static int alpine_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
phys_addr_t addr;
- addr = virt_to_phys(secondary_startup);
+ addr = __pa_symbol(secondary_startup);
if (addr > (phys_addr_t)(uint32_t)(-1)) {
pr_err("FAIL: resume address over 32bit (%pa)", &addr);
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
index ffbd71d45008..502e3df69f69 100644
--- a/arch/arm/mach-axxia/platsmp.c
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -25,7 +25,7 @@
static void write_release_addr(u32 release_phys)
{
u32 *virt = (u32 *) phys_to_virt(release_phys);
- writel_relaxed(virt_to_phys(secondary_startup), virt);
+ writel_relaxed(__pa_symbol(secondary_startup), virt);
/* Make sure this store is visible to other CPUs */
smp_wmb();
__cpuc_flush_dcache_area(virt, sizeof(u32));
diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c
index 9b6727ed68cd..f5fb10b4376f 100644
--- a/arch/arm/mach-bcm/bcm63xx_smp.c
+++ b/arch/arm/mach-bcm/bcm63xx_smp.c
@@ -135,7 +135,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
}
/* Write the secondary init routine to the BootLUT reset vector */
- val = virt_to_phys(secondary_startup);
+ val = __pa_symbol(secondary_startup);
writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
/* Power up the core, will jump straight to its reset vector when we
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index 40dc8448445e..12379960e982 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -151,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
* Set the reset vector to point to the secondary_startup
* routine
*/
- cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
+ cpu_set_boot_addr(cpu, __pa_symbol(secondary_startup));
/* Unhalt the cpu */
cpu_rst_cfg_set(cpu, 0);
diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
index 3ac3a9bc663c..582886d0d02f 100644
--- a/arch/arm/mach-bcm/platsmp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -116,7 +116,7 @@ static int nsp_write_lut(unsigned int cpu)
return -ENOMEM;
}
- secondary_startup_phy = virt_to_phys(secondary_startup);
+ secondary_startup_phy = __pa_symbol(secondary_startup);
BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
writel_relaxed(secondary_startup_phy, sku_rom_lut);
@@ -189,7 +189,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Secondary cores will start in secondary_startup(),
* defined in "arch/arm/kernel/head.S"
*/
- boot_func = virt_to_phys(secondary_startup);
+ boot_func = __pa_symbol(secondary_startup);
BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
BUG_ON(boot_func > (phys_addr_t)U32_MAX);
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
index 93f90688db18..1167b0ed92c8 100644
--- a/arch/arm/mach-berlin/platsmp.c
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -92,7 +92,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
* Write the secondary startup address into the SW reset address
* vector. This is used by boot_inst.
*/
- writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
+ writel(__pa_symbol(secondary_startup), vectors_base + SW_RESET_ADDR);
iounmap(vectors_base);
unmap_scu:
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index fd6da5419b51..e81a78b125d9 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -41,7 +41,7 @@ static int exynos_do_idle(unsigned long mode)
case FW_DO_IDLE_AFTR:
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_save_cp15();
- writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
+ writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
sysram_ns_base_addr + 0x24);
writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
if (soc_is_exynos3250()) {
@@ -135,7 +135,7 @@ static int exynos_suspend(void)
exynos_save_cp15();
writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
- writel(virt_to_phys(exynos_cpu_resume_ns),
+ writel(__pa_symbol(exynos_cpu_resume_ns),
sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
return cpu_suspend(0, exynos_cpu_suspend);
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index f086bf615b29..214a9cfa92e9 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -221,7 +221,7 @@ static void exynos_mcpm_setup_entry_point(void)
*/
__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
- __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+ __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
}
static struct syscore_ops exynos_mcpm_syscore_ops = {
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 98ffe1e62ad5..9f4949f7ed88 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -353,7 +353,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
smp_rmb();
- boot_addr = virt_to_phys(exynos4_secondary_startup);
+ boot_addr = __pa_symbol(exynos4_secondary_startup);
ret = exynos_set_boot_addr(core_id, boot_addr);
if (ret)
@@ -443,7 +443,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
mpidr = cpu_logical_map(i);
core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
- boot_addr = virt_to_phys(exynos4_secondary_startup);
+ boot_addr = __pa_symbol(exynos4_secondary_startup);
ret = exynos_set_boot_addr(core_id, boot_addr);
if (ret)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 487295f4a56b..1a7e5b5d08d8 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -132,7 +132,7 @@ static void exynos_set_wakeupmask(long mask)
static void exynos_cpu_set_boot_vector(long flags)
{
- writel_relaxed(virt_to_phys(exynos_cpu_resume),
+ writel_relaxed(__pa_symbol(exynos_cpu_resume),
exynos_boot_vector_addr());
writel_relaxed(flags, exynos_boot_vector_flag());
}
@@ -238,7 +238,7 @@ static int exynos_cpu0_enter_aftr(void)
abort:
if (cpu_online(1)) {
- unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
+ unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
/*
* Set the boot vector to something non-zero
@@ -330,7 +330,7 @@ static int exynos_cpu1_powerdown(void)
static void exynos_pre_enter_aftr(void)
{
- unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
+ unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
(void)exynos_set_boot_addr(1, boot_addr);
}
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 06332f626565..97765be2cc12 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -344,7 +344,7 @@ static void exynos_pm_prepare(void)
exynos_pm_enter_sleep_mode();
/* ensure at least INFORM0 has the resume address */
- pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+ pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos3250_pm_prepare(void)
@@ -361,7 +361,7 @@ static void exynos3250_pm_prepare(void)
exynos_pm_enter_sleep_mode();
/* ensure at least INFORM0 has the resume address */
- pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+ pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos5420_pm_prepare(void)
@@ -386,7 +386,7 @@ static void exynos5420_pm_prepare(void)
/* ensure at least INFORM0 has the resume address */
if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
- pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+ pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
tmp &= ~EXYNOS5_USE_RETENTION;
diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
index 4b653a8cb75c..a6c117622d67 100644
--- a/arch/arm/mach-hisi/platmcpm.c
+++ b/arch/arm/mach-hisi/platmcpm.c
@@ -327,7 +327,7 @@ static int __init hip04_smp_init(void)
*/
writel_relaxed(hip04_boot_method[0], relocation);
writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
- writel_relaxed(virt_to_phys(secondary_startup), relocation + 8);
+ writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
writel_relaxed(0, relocation + 12);
iounmap(relocation);
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index e1d67648d5d0..91bb02dec20f 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -28,7 +28,7 @@ void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
cpu = cpu_logical_map(cpu);
if (!cpu || !ctrl_base)
return;
- writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
+ writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
}
int hi3xxx_get_cpu_jump(int cpu)
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
phys_addr_t jumpaddr;
- jumpaddr = virt_to_phys(secondary_startup);
+ jumpaddr = __pa_symbol(secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct device_node *node;
- jumpaddr = virt_to_phys(secondary_startup);
+ jumpaddr = __pa_symbol(secondary_startup);
hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 711dbbd5badd..c2d1b329fba1 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -117,7 +117,7 @@ static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
dcfg_base = of_iomap(np, 0);
BUG_ON(!dcfg_base);
- paddr = virt_to_phys(secondary_startup);
+ paddr = __pa_symbol(secondary_startup);
writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
iounmap(dcfg_base);
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 1515e498d348..e61b1d1027e1 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -499,7 +499,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
memset(suspend_ocram_base, 0, sizeof(*pm_info));
pm_info = suspend_ocram_base;
pm_info->pbase = ocram_pbase;
- pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+ pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
pm_info->pm_info_size = sizeof(*pm_info);
/*
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 70b083fe934a..495d85d0fe7e 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -99,7 +99,7 @@ void imx_enable_cpu(int cpu, bool enable)
void imx_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
- writel_relaxed(virt_to_phys(jump_addr),
+ writel_relaxed(__pa_symbol(jump_addr),
src_base + SRC_GPR1 + cpu * 8);
}
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index b821e34474b6..726eb69bb655 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -122,7 +122,7 @@ static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
* write the address of slave startup address into the system-wide
* jump register
*/
- writel_relaxed(virt_to_phys(secondary_startup_arm),
+ writel_relaxed(__pa_symbol(secondary_startup_arm),
mtk_smp_base + mtk_smp_info->jump_reg);
}
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index 2990c5269b18..c487be61d6d8 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -110,7 +110,7 @@ static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
{
phys_addr_t resume_pc;
- resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
+ resume_pc = __pa_symbol(armada_370_xp_cpu_resume);
/*
* The bootloader expects the first two words to be a magic
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index f39bd51bce18..27a78c80e5b1 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -112,7 +112,7 @@ static const struct of_device_id of_pmsu_table[] = {
void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
{
- writel(virt_to_phys(boot_addr), pmsu_mp_base +
+ writel(__pa_symbol(boot_addr), pmsu_mp_base +
PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
}
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 76cbc82a7407..04d9ebe6a90a 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -153,7 +153,7 @@ void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
if (of_machine_is_compatible("marvell,armada375"))
mvebu_armada375_smp_wa_init();
- writel(virt_to_phys(boot_addr), system_controller_base +
+ writel(__pa_symbol(boot_addr), system_controller_base +
mvebu_sc->resume_boot_addr);
}
#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1662071bb2cc..bd8089ff929f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -315,15 +315,15 @@ void omap3_save_scratchpad_contents(void)
scratchpad_contents.boot_config_ptr = 0x0;
if (cpu_is_omap3630())
scratchpad_contents.public_restore_ptr =
- virt_to_phys(omap3_restore_3630);
+ __pa_symbol(omap3_restore_3630);
else if (omap_rev() != OMAP3430_REV_ES3_0 &&
omap_rev() != OMAP3430_REV_ES3_1 &&
omap_rev() != OMAP3430_REV_ES3_1_2)
scratchpad_contents.public_restore_ptr =
- virt_to_phys(omap3_restore);
+ __pa_symbol(omap3_restore);
else
scratchpad_contents.public_restore_ptr =
- virt_to_phys(omap3_restore_es3);
+ __pa_symbol(omap3_restore_es3);
if (omap_type() == OMAP2_DEVICE_TYPE_GP)
scratchpad_contents.secure_ram_restore_ptr = 0x0;
@@ -395,7 +395,7 @@ void omap3_save_scratchpad_contents(void)
sdrc_block_contents.flags = 0x0;
sdrc_block_contents.block_size = 0x0;
- arm_context_addr = virt_to_phys(omap3_arm_context);
+ arm_context_addr = __pa_symbol(omap3_arm_context);
/* Copy all the contents to the scratchpad location */
scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index ad982465efd0..d1e03c03219e 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -273,7 +273,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
cpu_clear_prev_logic_pwrst(cpu);
pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
- set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
+ set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
omap_pm_ops.scu_prepare(cpu, power_state);
l2x0_pwrst_prepare(cpu, save_state);
@@ -325,7 +325,7 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
- set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
+ set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
omap_pm_ops.scu_prepare(cpu, power_state);
/*
@@ -459,9 +459,9 @@ void __init omap4_mpuss_early_init(void)
sar_base = omap4_get_sar_ram_base();
if (cpu_is_omap443x())
- startup_pa = virt_to_phys(omap4_secondary_startup);
+ startup_pa = __pa_symbol(omap4_secondary_startup);
else
- startup_pa = virt_to_phys(omap4460_secondary_startup);
+ startup_pa = __pa_symbol(omap4460_secondary_startup);
writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
}
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index b4de3da6dffa..003353b0b794 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -316,9 +316,9 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
* A barrier is added to ensure that write buffer is drained
*/
if (omap_secure_apis_support())
- omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
+ omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));
else
- writel_relaxed(virt_to_phys(cfg.startup_addr),
+ writel_relaxed(__pa_symbol(cfg.startup_addr),
base + OMAP_AUX_CORE_BOOT_1);
}
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 0875b99add18..75ef5d4be554 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -65,7 +65,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
* waiting for. This would wake up the secondary core from WFE
*/
#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
- __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
+ __raw_writel(__pa_symbol(sirfsoc_secondary_startup),
clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 83e94c95e314..b0bcf1ff02dd 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -54,7 +54,7 @@ static void sirfsoc_set_sleep_mode(u32 mode)
static int sirfsoc_pre_suspend_power_off(void)
{
- u32 wakeup_entry = virt_to_phys(cpu_resume);
+ u32 wakeup_entry = __pa_symbol(cpu_resume);
sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
SIRFSOC_PWRC_SCRATCH_PAD1);
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 9c308de158c6..29630061e700 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -249,7 +249,7 @@ static int palmz72_pm_suspend(void)
store_ptr = *PALMZ72_SAVE_DWORD;
/* Setting PSPR to a proper value */
- PSPR = virt_to_phys(&palmz72_resume_info);
+ PSPR = __pa_symbol(&palmz72_resume_info);
return 0;
}
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 12b94357fbc1..d16ffcab0e45 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -85,7 +85,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
static int pxa25x_cpu_pm_prepare(void)
{
/* set resume return address */
- PSPR = virt_to_phys(cpu_resume);
+ PSPR = __pa_symbol(cpu_resume);
return 0;
}
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index c0185c5c5a08..9b69be4e9fe3 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -168,7 +168,7 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state)
static int pxa27x_cpu_pm_prepare(void)
{
/* set resume return address */
- PSPR = virt_to_phys(cpu_resume);
+ PSPR = __pa_symbol(cpu_resume);
return 0;
}
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 87acc96388c7..0cc9f124c9ac 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -123,7 +123,7 @@ static void pxa3xx_cpu_pm_suspend(void)
PSPR = 0x5c014000;
/* overwrite with the resume address */
- *p = virt_to_phys(cpu_resume);
+ *p = __pa_symbol(cpu_resume);
cpu_suspend(0, pxa3xx_finish_suspend);
diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-realview/platsmp-dt.c
index 70ca99eb52c6..c242423bf8db 100644
--- a/arch/arm/mach-realview/platsmp-dt.c
+++ b/arch/arm/mach-realview/platsmp-dt.c
@@ -76,7 +76,7 @@ static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
}
/* Put the boot address in this magic register */
regmap_write(map, REALVIEW_SYS_FLAGSSET_OFFSET,
- virt_to_phys(versatile_secondary_startup));
+ __pa_symbol(versatile_secondary_startup));
}
static const struct smp_operations realview_dt_smp_ops __initconst = {
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 4d827a069d49..3abafdbdd7f4 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -156,7 +156,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
mdelay(1); /* ensure the cpus other than cpu0 to startup */
- writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
+ writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev();
}
@@ -195,7 +195,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
}
/* set the boot function for the sram code */
- rockchip_boot_fn = virt_to_phys(secondary_startup);
+ rockchip_boot_fn = __pa_symbol(secondary_startup);
/* copy the trampoline to sram, that runs during startup of the core */
memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index bee8c8051929..0592534e0b88 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -62,7 +62,7 @@ static inline u32 rk3288_l2_config(void)
static void rk3288_config_bootdata(void)
{
rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
- rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+ rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
rkpm_bootdata_l2ctlr_f = 1;
rkpm_bootdata_l2ctlr = rk3288_l2_config();
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 7d99fe8f6157..4f2ffca88e6c 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -483,7 +483,7 @@ static int jive_pm_suspend(void)
* correct address to resume from. */
__raw_writel(0x2BED, S3C2412_INFORM0);
- __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+ __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
return 0;
}
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 20e481d8a33a..a4588daeddb0 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -45,7 +45,7 @@ static void s3c2410_pm_prepare(void)
{
/* ensure at least GSTATUS3 has the resume address */
- __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
+ __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index c0e328e37bd6..b5bbf0d5985c 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
* correct address to resume from.
*/
__raw_writel(0x2BED, S3C2412_INFORM0);
- __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+ __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
}
static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 59d91b83b03d..945a9d1e1a71 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -304,7 +304,7 @@ static void s3c64xx_pm_prepare(void)
wake_irqs, ARRAY_SIZE(wake_irqs));
/* store address of resume. */
- __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
+ __raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
/* ensure previous wakeup state is cleared before sleeping */
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 21b4b13c5ab7..2d5f08015e34 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -69,7 +69,7 @@ static void s5pv210_pm_prepare(void)
__raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
/* ensure at least INFORM0 has the resume address */
- __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
+ __raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0);
tmp = __raw_readl(S5P_SLEEP_CFG);
tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 34853d5dfda2..9a7079f565bd 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -73,7 +73,7 @@ static int sa11x0_pm_enter(suspend_state_t state)
RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
/* set resume return address */
- PSPR = virt_to_phys(cpu_resume);
+ PSPR = __pa_symbol(cpu_resume);
/* go zzz */
cpu_suspend(0, sa1100_finish_suspend);
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 0c6bb458b7a4..71729b8d1900 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -171,7 +171,7 @@ static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
static void __init shmobile_smp_apmu_setup_boot(void)
{
/* install boot code shared by all CPUs */
- shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+ shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
}
void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
@@ -185,7 +185,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/* For this particular CPU register boot vector */
- shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
+ shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
return apmu_wrap(cpu, apmu_power_on);
}
@@ -301,7 +301,7 @@ int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
#if defined(CONFIG_SUSPEND)
static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
{
- shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0);
+ shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
shmobile_smp_apmu_cpu_shutdown(cpu);
cpu_do_idle(); /* WFI selects Core Standby */
return 1;
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
index d1ecaf37d142..f1a1efde4beb 100644
--- a/arch/arm/mach-shmobile/platsmp-scu.c
+++ b/arch/arm/mach-shmobile/platsmp-scu.c
@@ -24,7 +24,7 @@ static void __iomem *shmobile_scu_base;
static int shmobile_scu_cpu_prepare(unsigned int cpu)
{
/* For this particular CPU register SCU SMP boot vector */
- shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
+ shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_scu),
shmobile_scu_base_phys);
return 0;
}
@@ -33,7 +33,7 @@ void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
unsigned int max_cpus)
{
/* install boot code shared by all CPUs */
- shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+ shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
/* enable SCU and cache coherency on booting CPU */
shmobile_scu_base_phys = scu_base_phys;
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 07945748b571..0ee76772b507 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
- writel(virt_to_phys(secondary_startup),
+ writel(__pa_symbol(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
flush_cache_all();
@@ -63,7 +63,7 @@ static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle
SOCFPGA_A10_RSTMGR_MODMPURST);
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
- writel(virt_to_phys(secondary_startup),
+ writel(__pa_symbol(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
flush_cache_all();
diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
index 8d1e2d551786..39038a03836a 100644
--- a/arch/arm/mach-spear/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -117,7 +117,7 @@ static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
* (presently it is in SRAM). The BootMonitor waits until it receives a
* soft interrupt, and then the secondary CPU branches to this address.
*/
- __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
+ __raw_writel(__pa_symbol(spear13xx_secondary_startup), SYS_LOCATION);
}
const struct smp_operations spear13xx_smp_ops __initconst = {
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
index ea5a2277ee46..231f19e17436 100644
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -103,7 +103,7 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
u32 __iomem *cpu_strt_ptr;
u32 release_phys;
int cpu;
- unsigned long entry_pa = virt_to_phys(sti_secondary_startup);
+ unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 6642267812c9..8fb5088464db 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -80,7 +80,7 @@ static int sun6i_smp_boot_secondary(unsigned int cpu,
spin_lock(&cpu_lock);
/* Set CPU boot address */
- writel(virt_to_phys(secondary_startup),
+ writel(__pa_symbol(secondary_startup),
cpucfg_membase + CPUCFG_PRIVATE0_REG);
/* Assert the CPU core in reset */
@@ -162,7 +162,7 @@ static int sun8i_smp_boot_secondary(unsigned int cpu,
spin_lock(&cpu_lock);
/* Set CPU boot address */
- writel(virt_to_phys(secondary_startup),
+ writel(__pa_symbol(secondary_startup),
cpucfg_membase + CPUCFG_PRIVATE0_REG);
/* Assert the CPU core in reset */
diff --git a/arch/arm/mach-tango/platsmp.c b/arch/arm/mach-tango/platsmp.c
index 98c62a4a8623..2f0c6c050fed 100644
--- a/arch/arm/mach-tango/platsmp.c
+++ b/arch/arm/mach-tango/platsmp.c
@@ -5,7 +5,7 @@
static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- tango_set_aux_boot_addr(virt_to_phys(secondary_startup));
+ tango_set_aux_boot_addr(__pa_symbol(secondary_startup));
tango_start_aux_core(cpu);
return 0;
}
diff --git a/arch/arm/mach-tango/pm.c b/arch/arm/mach-tango/pm.c
index b05c6d6f99d0..406c0814eb6e 100644
--- a/arch/arm/mach-tango/pm.c
+++ b/arch/arm/mach-tango/pm.c
@@ -5,7 +5,7 @@
static int tango_pm_powerdown(unsigned long arg)
{
- tango_suspend(virt_to_phys(cpu_resume));
+ tango_suspend(__pa_symbol(cpu_resume));
return -EIO; /* tango_suspend has failed */
}
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 6fd9db54887e..dc558892753c 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -94,14 +94,14 @@ void __init tegra_cpu_reset_handler_init(void)
__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
*((u32 *)cpu_possible_mask);
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
- virt_to_phys((void *)secondary_startup);
+ __pa_symbol((void *)secondary_startup);
#endif
#ifdef CONFIG_PM_SLEEP
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
TEGRA_IRAM_LPx_RESUME_AREA;
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
- virt_to_phys((void *)tegra_resume);
+ __pa_symbol((void *)tegra_resume);
#endif
tegra_cpu_reset_handler_enable();
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 8f2f615ff958..8c8f26389067 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -54,7 +54,7 @@ static void wakeup_secondary(void)
* backup ram register at offset 0x1FF0, which is what boot rom code
* is waiting for. This will wake up the secondary core from WFE.
*/
- writel(virt_to_phys(secondary_startup),
+ writel(__pa_symbol(secondary_startup),
backupram + UX500_CPU1_JUMPADDR_OFFSET);
writel(0xA1FEED01,
backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 5cedcf572104..ee2a0faafaa1 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -166,7 +166,7 @@ static int __init dcscb_init(void)
* Future entries into the kernel can now go
* through the cluster entry vectors.
*/
- vexpress_flags_set(virt_to_phys(mcpm_entry_point));
+ vexpress_flags_set(__pa_symbol(mcpm_entry_point));
return 0;
}
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 8b8d0724f6c6..575588633a36 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -61,7 +61,7 @@ static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
+ vexpress_flags_set(__pa_symbol(versatile_secondary_startup));
}
const struct smp_operations vexpress_smp_dt_ops __initconst = {
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index 1aa4ccece69f..9b5f3c427086 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -54,7 +54,7 @@ static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
return -EINVAL;
ve_spc_set_resume_addr(cluster, cpu,
- virt_to_phys(mcpm_entry_point));
+ __pa_symbol(mcpm_entry_point));
ve_spc_cpu_wakeup_irq(cluster, cpu, true);
return 0;
}
@@ -159,7 +159,7 @@ static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
{
- ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
+ ve_spc_set_resume_addr(cluster, cpu, __pa_symbol(mcpm_entry_point));
}
static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
diff --git a/arch/arm/mach-zx/platsmp.c b/arch/arm/mach-zx/platsmp.c
index 0297f92084e0..afb9a82dedc3 100644
--- a/arch/arm/mach-zx/platsmp.c
+++ b/arch/arm/mach-zx/platsmp.c
@@ -76,7 +76,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(virt_to_phys(zx_secondary_startup),
+ __raw_writel(__pa_symbol(zx_secondary_startup),
aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
iounmap(aonsysctrl_base);
@@ -94,7 +94,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
/* Map the first 4 KB IRAM for suspend usage */
sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
- zx_secondary_startup_pa = virt_to_phys(zx_secondary_startup);
+ zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
}
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 7cd9865bdeb7..caa6d5fe9078 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -89,7 +89,7 @@ EXPORT_SYMBOL(zynq_cpun_start);
static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
+ return zynq_cpun_start(__pa_symbol(secondary_startup), cpu);
}
/*
--
2.9.3
^ permalink raw reply related
* mmc: core: complete/wait_for_completion performance
From: Stefan Wahren @ 2016-12-26 23:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481882798.31185.3.camel@embedded.rocks>
Hi J?rg,
> J?rg Krause <joerg.krause@embedded.rocks> hat am 16. Dezember 2016 um 11:06 geschrieben:
>
>
> Hi Stefan,
>
> On Thu, 2016-12-15 at 19:51 +0100, Stefan Wahren wrote:
> > Hi J?rg,
> >
> > > J?rg Krause <joerg.krause@embedded.rocks> hat am 15. Dezember 2016
> > > um 14:50 geschrieben:
> > >
> > >
> > > Hi Stefan,
> > >
> > > On Wed, 2016-12-14 at 19:57 +0100, Stefan Wahren wrote:
> > > > Hi J?rg,
> > > >
> > >
> > > [snip]
> > >
> > > > > >
> > > > > > did you try cyclictest [1]?
> > > > >
> > > > > Not yet. Not sure what to measure and which values to compare
> > > > > here.
> > > >
> > > > i tought you have the vendor kernel and the mainline kernel
> > > > available
> > > > for your platform.
> > > >
> > > > So you could compare the both kernels.
> > >
> > > Yes, that's right. I will have a look at this tool.
> > >
> > > > >
> > > > > >
> > > > > > Beside the time for a request the amount of requests for the
> > > > > > complete
> > > > > > iperf test
> > > > > > would we interesting. Maybe there are retries.
> > > > > >
> > > > > > I'm still interested in your PIO mode patches for mxs-mmc
> > > > > > even
> > > > > > without clean up.
> > > > >
> > > > > Actually, the patch does not implement a PIO mode, but drops
> > > > > DMA
> > > > > and
> > > > > uses polling instead. I've attached the patch.
> > > >
> > > > Thanks. I applied it, but unfortunately this breaks SD card
> > > > support
> > > > for my Duckbill and the kernel isn't able to mount the rootfs:
> > > >
> > > > [ 2.267073] mxs-mmc 80010000.ssp: initialized
> > > > [ 2.272624] mxs-mmc 80010000.ssp: AC command error 0xffffff92
> > >
> > > Sorry, I messed up the branches. I attached the correct patch which
> > > is
> > > working for me on Linux v4.9.
> >
> > i tested the second version but there isn't any performance gain with
> > the patch.
>
> In the vendor kernel the polling is used only for small chunks of <=
> 1024 bytes to save the context switches when using DMA. This patch does
> not use DMA at all, but only polling.
also the vendor kernel uses polling for AC and BC commands. I tried this approach (use polling for AC/BC/BCR commands and DMA for all ADTC commands) [1] on Duckbill with SD card but the resulting read and write performance stays the same. Maybe you want to give it a try with Wifi over SDIO.
Here are some read performance values with Duckbill (Kernel 4.8, class 10 microSD card):
dd if=/dev/mmcblk0p2 of=/dev/null
64260+0 records in
64260+0 records out
32901120 bytes (33 MB) copied, 1.68618 s, 19.5 MB/s
>
> As I said before, I guess the limitation in the mxs-mmc driver is the
> time needed to return the mmc request to the mmc core driver.
I don't think this is the problem. I added some GPIO handling into mxs-mmc driver and i couldn't see any big delay between the mmc requests with a logic analyzer.
>
> I have a Cubietruck with the same wifi chipset as on my i.MX28 target
> where I get ~20Mbps throughput. Furthermore, I've found a benchmark on
> a NXP thread [1] measuring about 30Mbps for an i.MX6 target and a
> similiar wifi chip.
>
> Looking at the sunxi-mmc driver shows that it calls mmc_request_done()
> in an interrupt context and does not use the dmaengine driver at all.
>
> For now, I would drop the polling mode and look how to optimize the
> control flow between the DMA controller and the MMC host.
> Unfortunately, this will need some time...
I also rebased an old patch from Shawn Guo [2] with pre_req and post_req support, tried to call the DMA channel callback from the interrupt context instead of scheduling the tasklet within the DMA engine driver and implement CMD23 support [3]. But none of them show any measurable performance improvement.
Btw here are some really performance critical kernel config parameter which really needs to be disabled:
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_PROVE_RCU is not set
[1] - https://github.com/lategoodbye/linux-mxs-power/commit/beb341ed948ae9b8afe7378cff6b9d50144fd0b9
[2] - https://github.com/lategoodbye/linux-mxs-power/commit/e96b28e8730ccfcfecb7ec286102bc6969aa1ee0
[3] - https://github.com/lategoodbye/linux-mxs-power/commit/e53a3c9169a63eb61f9e67ff88724972acf312a9
^ permalink raw reply
* [PATCH] DTS: MCCMON6: IMX: Provide support for iMX6Q based Liebherr mccmon6 board
From: Lukasz Majewski @ 2016-12-26 23:19 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
---
MCCMON6 board support depends on following patches:
1. "video: backlight: pwm_bl: Initialize fb_bl_on[x] and use_count during pwm_backlight_probe()"
http://patchwork.ozlabs.org/patch/708844/
2. "pwm: imx: Provide atomic operation for IMX PWM driver"
http://patchwork.ozlabs.org/patch/708847/ - http://patchwork.ozlabs.org/patch/708843/
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-mccmon6.dts | 469 ++++++++++++++++++++++++++++++++++++
2 files changed, 470 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-mccmon6.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c558ba7..7ce1080 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -382,6 +382,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-icore-rqs.dtb \
+ imx6q-mccmon6.dtb \
imx6q-marsboard.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts
new file mode 100644
index 0000000..7445d01
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
@@ -0,0 +1,469 @@
+/*
+ * Copyright 2016
+ *
+ * Author: Lukasz Majewski <l.majewski@majess.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Monitor6 i.MX6 Quad Board";
+ compatible = "mccmon6", "fsl,imx6q";
+
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+
+ ethernet0 {
+ status = "okay";
+ };
+
+ backlight_lvds: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_display>;
+ pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100 101 102 103 104 105 106 107 108 109
+ 110 111 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127 128 129
+ 130 131 132 133 134 135 136 137 138 139
+ 140 141 142 143 144 145 146 147 148 149
+ 150 151 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167 168 169
+ 170 171 172 173 174 175 176 177 178 179
+ 180 181 182 183 184 185 186 187 188 189
+ 190 191 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207 208 209
+ 210 211 212 213 214 215 216 217 218 219
+ 220 221 222 223 224 225 226 227 228 229
+ 230 231 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247 248 249
+ 250 251 252 253 254 255>;
+ default-brightness-level = <50>;
+ enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_lvds: regulator-lvds {
+ compatible = "regulator-fixed";
+ regulator-name = "lvds_ppen";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel-lvds0 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic: pfuze100 at 08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ imx6q-mccmon6 {
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
+ >;
+ };
+
+ pinctrl_weim_cs0: weimcs0grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_nor: weimnorgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+ MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+ MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+ MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+ MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+ MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+ MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+ MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+ MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+ MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+ MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+ MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+ MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+ MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+ MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+ MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+ MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+ MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+ MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+ MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+ MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3cs {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
+ >;
+ };
+ pinctrl_ecspi3_flwp: ecspi3flwp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_display: dispgrp {
+ fsl,pins = <
+ /* BLEN_OUT */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ /* LVDS_PPEN_OUT */
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 27 0>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x08000000 0x08000000>;
+ status = "okay";
+
+ nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x02000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ use-advanced-sector-protection;
+ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+ 0x0000c000 0x1404a38e 0x00000000>;
+ };
+};
+
+&ecspi3 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 24 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
+ status = "okay";
+
+ flash: s25sl032p at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl032p", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+};
+
+&pwm2 {
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
--
2.1.4
^ permalink raw reply related
* [PATCH] PCI: exynos: refactor exynos pcie driver
From: Jaehoon Chung @ 2016-12-27 1:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5860E6F7.2090703@samsung.com>
Dear Alim,
On 12/26/2016 06:46 PM, Alim Akhtar wrote:
> Hello Jaehoon
>
> On 12/26/2016 02:32 PM, Jaehoon Chung wrote:
>> Hi Pankaj,
>>
>> On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
>>> From: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>>
>>> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
>>> This patch does refactoring of Exynos PCIe driver to extend support
>>> for other Exynos SoC.
>>>
>>> Following are the main changes done via this patch:
>>> 1) It adds separate structs for memory, clock resources.
>>> 2) It add exynos_pcie_ops struct which will allow us to support the
>>> differences in resources in different Exynos SoC.
>>
>> It's nice to me for reusing this file.
>> but after considering too many times, i decided not to use this file.
>>
>> I'm not sure what block base is..actually this pci-exynos.c is really black-box.
>> (No one maintains this file, even Samsung didn't care.)
>> Who is using this?
>> If Someone can share the information about exynos5440, i can refactor everything.
>> Otherwise, there are two solution..
>>
>> One is "adding the new pci-exynos.c" likes pci-exynos5433.c
>> Other is "refactor this file" under assuming the each register's usage.
>>
> Its alway good to reuse code as far as possible.
> I am yet to see the details of 5440, but since people are now going to support more Exynos variants, in my opinion, instead of adding pci-exynos5433.c, you can rename current pci-exynos.c to something like pci-exynos5440.c (only in case its too much changes needed to support 5433/exynos7) and lets have a common pci-exynos.c where we can add exynos7/5433 and others SoCs, AFAIK at least exynos7 and 5433 has similar pci controller.
Yes, It's always good to reuse. but as you know, current pci-exynos.c file is really specific for only exynos5440.
I will try to check about combining.
>> I want to use the PHY generic Framework for EXYNOS PCIe.
>>
> I don't think you have an option here, you should use generic PHY APIs, otherwise phy drive should go to drivers/misc.
> Other thoughts are welcome.
Why go to drivers/misc? There is driver/phy/ for PHY generic Framework.
If i will touch this file, then i will put our phy-exynos-pcie file under driver/phy/ .
I already sent the patch for this. Could you check them?
http://patchwork.ozlabs.org/patch/708738/
http://patchwork.ozlabs.org/patch/708742/
Best Regards,
Jaehoon Chung
>
>> If you or other guys really want to use the pci-exynos.c for other exynos,
>> I will rework with PHY generic framework. Then i will resend the my patches as V2.
>>
>> One more thing..Does anyone know what the usage of block base is?
>> Can i use that register as "syscon"?
>>
>> Best Regards,
>> Jaehoon Chung
>>
>>>
>>> No functional change intended.
>>>
>>> Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>>> ---
>>> This patch set is prepared on top of Krzysztof's for-next and
>>> PCIe driver cleanup patch [1] by Jaehoon Chung.
>>>
>>> [1]: https://lkml.org/lkml/2016/12/19/44
>>>
>>>
>>> drivers/pci/host/pci-exynos.c | 346 ++++++++++++++++++++++++++----------------
>>> 1 file changed, 217 insertions(+), 129 deletions(-)
>>>
>>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
>>> index 33562cf..2dc54f7 100644
>>> --- a/drivers/pci/host/pci-exynos.c
>>> +++ b/drivers/pci/host/pci-exynos.c
>>> @@ -17,6 +17,7 @@
>>> #include <linux/interrupt.h>
>>> #include <linux/kernel.h>
>>> #include <linux/init.h>
>>> +#include <linux/of_device.h>
>>> #include <linux/of_gpio.h>
>>> #include <linux/pci.h>
>>> #include <linux/platform_device.h>
>>> @@ -28,16 +29,6 @@
>>>
>>> #define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
>>>
>>> -struct exynos_pcie {
>>> - struct pcie_port pp;
>>> - void __iomem *elbi_base; /* DT 0th resource */
>>> - void __iomem *phy_base; /* DT 1st resource */
>>> - void __iomem *block_base; /* DT 2nd resource */
>>> - int reset_gpio;
>>> - struct clk *clk;
>>> - struct clk *bus_clk;
>>> -};
>>> -
>>> /* PCIe ELBI registers */
>>> #define PCIE_IRQ_PULSE 0x000
>>> #define IRQ_INTA_ASSERT BIT(0)
>>> @@ -102,6 +93,122 @@ struct exynos_pcie {
>>> #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>>> #define PCIE_PHY_TRSV3_LVCC 0x31c
>>>
>>> +struct exynos_pcie_mem_res {
>>> + void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
>>> + void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
>>> + void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL */
>>> +};
>>> +
>>> +struct exynos_pcie_clk_res {
>>> + struct clk *clk;
>>> + struct clk *bus_clk;
>>> +};
>>> +
>>> +struct exynos_pcie {
>>> + struct pcie_port pp;
>>> + struct exynos_pcie_mem_res *mem_res;
>>> + struct exynos_pcie_clk_res *clk_res;
>>> + const struct exynos_pcie_ops *ops;
>>> + int reset_gpio;
>>> +};
>>> +
>>> +struct exynos_pcie_ops {
>>> + int (*get_mem_resources)(struct platform_device *pdev,
>>> + struct exynos_pcie *ep);
>>> + int (*get_clk_resources)(struct exynos_pcie *ep);
>>> + int (*init_clk_resources)(struct exynos_pcie *ep);
>>> + void (*deinit_clk_resources)(struct exynos_pcie *ep);
>>> +};
>>> +
>>> +static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>>> + struct exynos_pcie *ep)
>>> +{
>>> + struct resource *res;
>>> + struct device *dev = ep->pp.dev;
>>> +
>>> + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
>>> + if (!ep->mem_res)
>>> + return -ENOMEM;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + ep->mem_res->elbi_base = devm_ioremap_resource(dev, res);
>>> + if (IS_ERR(ep->mem_res->elbi_base))
>>> + return PTR_ERR(ep->mem_res->elbi_base);
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>> + ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>>> + if (IS_ERR(ep->mem_res->phy_base))
>>> + return PTR_ERR(ep->mem_res->phy_base);
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>>> + ep->mem_res->block_base = devm_ioremap_resource(dev, res);
>>> + if (IS_ERR(ep->mem_res->block_base))
>>> + return PTR_ERR(ep->mem_res->block_base);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep)
>>> +{
>>> + struct device *dev = ep->pp.dev;
>>> +
>>> + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
>>> + if (!ep->clk_res)
>>> + return -ENOMEM;
>>> +
>>> + ep->clk_res->clk = devm_clk_get(dev, "pcie");
>>> + if (IS_ERR(ep->clk_res->clk)) {
>>> + dev_err(dev, "Failed to get pcie rc clock\n");
>>> + return PTR_ERR(ep->clk_res->clk);
>>> + }
>>> +
>>> + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
>>> + if (IS_ERR(ep->clk_res->bus_clk)) {
>>> + dev_err(dev, "Failed to get pcie bus clock\n");
>>> + return PTR_ERR(ep->clk_res->bus_clk);
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
>>> +{
>>> + struct device *dev = ep->pp.dev;
>>> + int ret;
>>> +
>>> + ret = clk_prepare_enable(ep->clk_res->clk);
>>> + if (ret) {
>>> + dev_err(dev, "cannot enable pcie rc clock");
>>> + return ret;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(ep->clk_res->bus_clk);
>>> + if (ret) {
>>> + dev_err(dev, "cannot enable pcie bus clock");
>>> + goto err_bus_clk;
>>> + }
>>> +
>>> + return 0;
>>> +
>>> +err_bus_clk:
>>> + clk_disable_unprepare(ep->clk_res->clk);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep)
>>> +{
>>> + clk_disable_unprepare(ep->clk_res->bus_clk);
>>> + clk_disable_unprepare(ep->clk_res->clk);
>>> +}
>>> +
>>> +static const struct exynos_pcie_ops exynos5440_pcie_ops = {
>>> + .get_mem_resources = exynos5440_pcie_get_mem_resources,
>>> + .get_clk_resources = exynos5440_pcie_get_clk_resources,
>>> + .init_clk_resources = exynos5440_pcie_init_clk_resources,
>>> + .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
>>> +};
>>> +
>>> static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
>>> {
>>> writel(val, base + reg);
>>> @@ -116,155 +223,155 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
>>> {
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC);
>>> if (on)
>>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>>> else
>>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
>>> }
>>>
>>> static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
>>> {
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC);
>>> if (on)
>>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>>> else
>>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
>>> }
>>>
>>> static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
>>> {
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>>> val &= ~PCIE_CORE_RESET_ENABLE;
>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_PWR_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET);
>>> }
>>>
>>> static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
>>> {
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>>> val |= PCIE_CORE_RESET_ENABLE;
>>>
>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
>>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_MAC_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
>>> }
>>>
>>> static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
>>> {
>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_MAC_RESET);
>>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_GLOBAL_RESET);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_MAC_RESET);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_GLOBAL_RESET);
>>> }
>>>
>>> static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
>>> {
>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_GLOBAL_RESET);
>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_PWR_RESET);
>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_COMMON_RESET);
>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_CMN_REG);
>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSVREG_RESET);
>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSV_RESET);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_GLOBAL_RESET);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_CMN_REG);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSVREG_RESET);
>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSV_RESET);
>>> }
>>>
>>> static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
>>> {
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
>>> val &= ~PCIE_PHY_COMMON_PD_CMN;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
>>> val &= ~PCIE_PHY_TRSV0_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
>>> val &= ~PCIE_PHY_TRSV1_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
>>> val &= ~PCIE_PHY_TRSV2_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
>>> val &= ~PCIE_PHY_TRSV3_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>> }
>>>
>>> static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
>>> {
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
>>> val |= PCIE_PHY_COMMON_PD_CMN;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
>>> val |= PCIE_PHY_TRSV0_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
>>> val |= PCIE_PHY_TRSV1_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
>>> val |= PCIE_PHY_TRSV2_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>
>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
>>> val |= PCIE_PHY_TRSV3_PD_TSV;
>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>> }
>>>
>>> static void exynos_pcie_init_phy(struct exynos_pcie *ep)
>>> {
>>> /* DCC feedback control off */
>>> - exynos_pcie_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>>>
>>> /* set TX/RX impedance */
>>> - exynos_pcie_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>>>
>>> /* set 50Mhz PHY clock */
>>> - exynos_pcie_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>>> - exynos_pcie_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>>>
>>> /* set TX Differential output for lane 0 */
>>> - exynos_pcie_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>>>
>>> /* set TX Pre-emphasis Level Control for lane 0 to minimum */
>>> - exynos_pcie_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>>>
>>> /* set RX clock and data recovery bandwidth */
>>> - exynos_pcie_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>>>
>>> /* change TX Pre-emphasis Level Control for lanes */
>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>>>
>>> /* set LVCC */
>>> - exynos_pcie_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>>> }
>>>
>>> static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
>>> @@ -295,25 +402,27 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>>> exynos_pcie_init_phy(exynos_pcie);
>>>
>>> /* pulse for common reset */
>>> - exynos_pcie_writel(exynos_pcie->block_base, 1, PCIE_PHY_COMMON_RESET);
>>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
>>> + PCIE_PHY_COMMON_RESET);
>>> udelay(500);
>>> - exynos_pcie_writel(exynos_pcie->block_base, 0, PCIE_PHY_COMMON_RESET);
>>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
>>> + PCIE_PHY_COMMON_RESET);
>>>
>>> exynos_pcie_deassert_core_reset(exynos_pcie);
>>> dw_pcie_setup_rc(pp);
>>> exynos_pcie_assert_reset(exynos_pcie);
>>>
>>> /* assert LTSSM enable */
>>> - exynos_pcie_writel(exynos_pcie->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
>>> - PCIE_APP_LTSSM_ENABLE);
>>> + exynos_pcie_writel(exynos_pcie->mem_res->elbi_base,
>>> + PCIE_ELBI_LTSSM_ENABLE, PCIE_APP_LTSSM_ENABLE);
>>>
>>> /* check if the link is up or not */
>>> if (!dw_pcie_wait_for_link(pp))
>>> return 0;
>>>
>>> - while (exynos_pcie_readl(exynos_pcie->phy_base,
>>> + while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>>> PCIE_PHY_PLL_LOCKED) == 0) {
>>> - val = exynos_pcie_readl(exynos_pcie->block_base,
>>> + val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
>>> PCIE_PHY_PLL_LOCKED);
>>> dev_info(dev, "PLL Locked: 0x%x\n", val);
>>> }
>>> @@ -325,8 +434,8 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
>>> {
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
>>> }
>>>
>>> static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>>> @@ -336,7 +445,7 @@ static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>>> /* enable INTX interrupt */
>>> val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
>>> IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
>>> }
>>>
>>> static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
>>> @@ -363,9 +472,9 @@ static void exynos_pcie_msi_init(struct exynos_pcie *ep)
>>> dw_pcie_msi_init(pp);
>>>
>>> /* enable MSI interrupt */
>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_EN_LEVEL);
>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL);
>>> val |= IRQ_MSI_ENABLE;
>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>>> }
>>>
>>> static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
>>> @@ -425,7 +534,8 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
>>> struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
>>> u32 val;
>>>
>>> - val = exynos_pcie_readl(exynos_pcie->elbi_base, PCIE_ELBI_RDLH_LINKUP);
>>> + val = exynos_pcie_readl(exynos_pcie->mem_res->elbi_base,
>>> + PCIE_ELBI_RDLH_LINKUP);
>>> if (val == PCIE_ELBI_LTSSM_ENABLE)
>>> return 1;
>>>
>>> @@ -503,7 +613,6 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>> struct exynos_pcie *exynos_pcie;
>>> struct pcie_port *pp;
>>> struct device_node *np = dev->of_node;
>>> - struct resource *res;
>>> int ret;
>>>
>>> exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
>>> @@ -513,59 +622,37 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>> pp = &exynos_pcie->pp;
>>> pp->dev = dev;
>>>
>>> - exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>> -
>>> - exynos_pcie->clk = devm_clk_get(dev, "pcie");
>>> - if (IS_ERR(exynos_pcie->clk)) {
>>> - dev_err(dev, "Failed to get pcie rc clock\n");
>>> - return PTR_ERR(exynos_pcie->clk);
>>> - }
>>> - ret = clk_prepare_enable(exynos_pcie->clk);
>>> - if (ret)
>>> - return ret;
>>> + exynos_pcie->ops = (const struct exynos_pcie_ops *)
>>> + of_device_get_match_data(dev);
>>>
>>> - exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
>>> - if (IS_ERR(exynos_pcie->bus_clk)) {
>>> - dev_err(dev, "Failed to get pcie bus clock\n");
>>> - ret = PTR_ERR(exynos_pcie->bus_clk);
>>> - goto fail_clk;
>>> - }
>>> - ret = clk_prepare_enable(exynos_pcie->bus_clk);
>>> - if (ret)
>>> - goto fail_clk;
>>> + exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>>
>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> - exynos_pcie->elbi_base = devm_ioremap_resource(dev, res);
>>> - if (IS_ERR(exynos_pcie->elbi_base)) {
>>> - ret = PTR_ERR(exynos_pcie->elbi_base);
>>> - goto fail_bus_clk;
>>> + if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>>> + ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>>> + if (ret)
>>> + return ret;
>>> }
>>>
>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>> - exynos_pcie->phy_base = devm_ioremap_resource(dev, res);
>>> - if (IS_ERR(exynos_pcie->phy_base)) {
>>> - ret = PTR_ERR(exynos_pcie->phy_base);
>>> - goto fail_bus_clk;
>>> - }
>>> + if (exynos_pcie->ops && exynos_pcie->ops->get_clk_resources) {
>>> + ret = exynos_pcie->ops->get_clk_resources(exynos_pcie);
>>> + if (ret)
>>> + return ret;
>>>
>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>>> - exynos_pcie->block_base = devm_ioremap_resource(dev, res);
>>> - if (IS_ERR(exynos_pcie->block_base)) {
>>> - ret = PTR_ERR(exynos_pcie->block_base);
>>> - goto fail_bus_clk;
>>> + ret = exynos_pcie->ops->init_clk_resources(exynos_pcie);
>>> + if (ret)
>>> + return ret;
>>> }
>>>
>>> ret = exynos_add_pcie_port(exynos_pcie, pdev);
>>> if (ret < 0)
>>> - goto fail_bus_clk;
>>> + goto fail_probe;
>>>
>>> platform_set_drvdata(pdev, exynos_pcie);
>>> return 0;
>>>
>>> -fail_bus_clk:
>>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>>> -fail_clk:
>>> - clk_disable_unprepare(exynos_pcie->clk);
>>> +fail_probe:
>>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>> return ret;
>>> }
>>>
>>> @@ -573,14 +660,15 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev)
>>> {
>>> struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
>>>
>>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>>> - clk_disable_unprepare(exynos_pcie->clk);
>>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>>
>>> return 0;
>>> }
>>>
>>> static const struct of_device_id exynos_pcie_of_match[] = {
>>> - { .compatible = "samsung,exynos5440-pcie", },
>>> + { .compatible = "samsung,exynos5440-pcie",
>>> + .data = &exynos5440_pcie_ops },
>>> {},
>>> };
>>>
>>>
>>
>>
>>
>
>
^ permalink raw reply
* [PATCH] PCI: exynos: refactor exynos pcie driver
From: Jaehoon Chung @ 2016-12-27 1:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000201d25f86$6ee20bd0$4ca62370$@gmail.com>
Dear Jingoo,
On 12/26/2016 11:43 PM, Jingoo Han wrote:
> Jaehoon Chung wtote:
>>
>> Hi Pankaj,
>>
>> On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
>>> From: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>>
>>> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
>>> This patch does refactoring of Exynos PCIe driver to extend support
>>> for other Exynos SoC.
>>>
>>> Following are the main changes done via this patch:
>>> 1) It adds separate structs for memory, clock resources.
>>> 2) It add exynos_pcie_ops struct which will allow us to support the
>>> differences in resources in different Exynos SoC.
>>
>> It's nice to me for reusing this file.
>> but after considering too many times, i decided not to use this file.
>>
>> I'm not sure what block base is..actually this pci-exynos.c is really
>> black-box.
>> (No one maintains this file, even Samsung didn't care.)
>> Who is using this?
>> If Someone can share the information about exynos5440, i can refactor
>> everything.
>> Otherwise, there are two solution..
>>
>> One is "adding the new pci-exynos.c" likes pci-exynos5433.c
>
> As Bjorn mentioned earlier, I agree with this option.
>
>> Other is "refactor this file" under assuming the each register's usage.
>
> But, if possible, I prefer this option.
> I am not sure that it cannot make the code dirty.
> Maybe, you need to discuss with hardware design engineers.
>
>>
>> I want to use the PHY generic Framework for EXYNOS PCIe.
>>
>> If you or other guys really want to use the pci-exynos.c for other exynos,
>> I will rework with PHY generic framework. Then i will resend the my
>> patches as V2.
>
> When I submitted the pci-exynos.c, there was no PHY generic framework.
> But, currently, using PHY generic framework is mandatory, as other PCIe host
> driver did.
> I think that we should use PHY generic framework for new SoCs.
>
>>
>> One more thing..Does anyone know what the usage of block base is?
>> Can i use that register as "syscon"?
>
> 'Block' is very specific registers for 5440.
> Other Exynos SoCs do not use that registers.
> Actually, it is not the same with 'syscon'.
> But, you can assume 'block' as 'syscon'.
Great! I want to know it. Then i will refactor this file for all other Exynos SoCs.
And Could you check my RFC patches? Maybe i missed your email in my RFC patches.
https://lkml.org/lkml/2016/12/26/6
Best Regards,
Jaehoon Chung
>
> Best regards,
> Jingoo Han
>
>>
>> Best Regards,
>> Jaehoon Chung
>>
> [.....]
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
^ permalink raw reply
* [PATCH v2] ARM: dts: sunxi: Add num-cs for A20 spi nodes
From: Chen-Yu Tsai @ 2016-12-27 2:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161226174748.17544-1-manu@bidouilliste.com>
Hi,
On Tue, Dec 27, 2016 at 1:47 AM, Emmanuel Vadot <manu@bidouilliste.com> wrote:
> The spi0 controller on the A20 have up to 4 CS (Chip Select) while the
> others three only have 1.
> Add the num-cs property to each node.
> The current driver doesn't read this property but this is useful for
> downstream user of DTS (FreeBSD for example).
>
> Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
> ---
>
> Changes in v2:
> * Explain that driver doesn't support this but that it is useful
> for downstream users of DTS.
>
> arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 94cf5a1c7172..ed21982c81cb 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -871,6 +871,7 @@
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> + num-cs = 4;
The numbers need to be enclosed in angle brackets.
ChenYu
> };
>
> spi1: spi at 01c06000 {
> @@ -885,6 +886,7 @@
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> + num-cs = 1;
> };
>
> emac: ethernet at 01c0b000 {
> @@ -1037,6 +1039,7 @@
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> + num-cs = 1;
> };
>
> ahci: sata at 01c18000 {
> @@ -1079,6 +1082,7 @@
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> + num-cs = 1;
> };
>
> pio: pinctrl at 01c20800 {
> --
> 2.11.0
>
^ permalink raw reply
* [PATCH] PCI: exynos: refactor exynos pcie driver
From: Alim Akhtar @ 2016-12-27 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <79b89c49-a9de-3daa-9afa-b8f36304a226@samsung.com>
On 12/27/2016 06:39 AM, Jaehoon Chung wrote:
> Dear Alim,
>
> On 12/26/2016 06:46 PM, Alim Akhtar wrote:
>> Hello Jaehoon
>>
>> On 12/26/2016 02:32 PM, Jaehoon Chung wrote:
>>> Hi Pankaj,
>>>
>>> On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
>>>> From: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>>>
>>>> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
>>>> This patch does refactoring of Exynos PCIe driver to extend support
>>>> for other Exynos SoC.
>>>>
>>>> Following are the main changes done via this patch:
>>>> 1) It adds separate structs for memory, clock resources.
>>>> 2) It add exynos_pcie_ops struct which will allow us to support the
>>>> differences in resources in different Exynos SoC.
>>>
>>> It's nice to me for reusing this file.
>>> but after considering too many times, i decided not to use this file.
>>>
>>> I'm not sure what block base is..actually this pci-exynos.c is really black-box.
>>> (No one maintains this file, even Samsung didn't care.)
>>> Who is using this?
>>> If Someone can share the information about exynos5440, i can refactor everything.
>>> Otherwise, there are two solution..
>>>
>>> One is "adding the new pci-exynos.c" likes pci-exynos5433.c
>>> Other is "refactor this file" under assuming the each register's usage.
>>>
>> Its alway good to reuse code as far as possible.
>> I am yet to see the details of 5440, but since people are now going to support more Exynos variants, in my opinion, instead of adding pci-exynos5433.c, you can rename current pci-exynos.c to something like pci-exynos5440.c (only in case its too much changes needed to support 5433/exynos7) and lets have a common pci-exynos.c where we can add exynos7/5433 and others SoCs, AFAIK at least exynos7 and 5433 has similar pci controller.
>
> Yes, It's always good to reuse. but as you know, current pci-exynos.c file is really specific for only exynos5440.
> I will try to check about combining.
>
>>> I want to use the PHY generic Framework for EXYNOS PCIe.
>>>
>> I don't think you have an option here, you should use generic PHY APIs, otherwise phy drive should go to drivers/misc.
>> Other thoughts are welcome.
>
> Why go to drivers/misc? There is driver/phy/ for PHY generic Framework.
> If i will touch this file, then i will put our phy-exynos-pcie file under driver/phy/ .
> I already sent the patch for this. Could you check them?
>
My point was, if you are not going to use generic PHY APIs, then phy
driver should go into drivers/misc. Anyway as you said you have already
posted patches with generic phy framework, I will take a look.
> http://patchwork.ozlabs.org/patch/708738/
> http://patchwork.ozlabs.org/patch/708742/
>
Thanks.
> Best Regards,
> Jaehoon Chung
>
>>
>>> If you or other guys really want to use the pci-exynos.c for other exynos,
>>> I will rework with PHY generic framework. Then i will resend the my patches as V2.
>>>
>>> One more thing..Does anyone know what the usage of block base is?
>>> Can i use that register as "syscon"?
>>>
>>> Best Regards,
>>> Jaehoon Chung
>>>
>>>>
>>>> No functional change intended.
>>>>
>>>> Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>>>> ---
>>>> This patch set is prepared on top of Krzysztof's for-next and
>>>> PCIe driver cleanup patch [1] by Jaehoon Chung.
>>>>
>>>> [1]: https://lkml.org/lkml/2016/12/19/44
>>>>
>>>>
>>>> drivers/pci/host/pci-exynos.c | 346 ++++++++++++++++++++++++++----------------
>>>> 1 file changed, 217 insertions(+), 129 deletions(-)
>>>>
>>>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
>>>> index 33562cf..2dc54f7 100644
>>>> --- a/drivers/pci/host/pci-exynos.c
>>>> +++ b/drivers/pci/host/pci-exynos.c
>>>> @@ -17,6 +17,7 @@
>>>> #include <linux/interrupt.h>
>>>> #include <linux/kernel.h>
>>>> #include <linux/init.h>
>>>> +#include <linux/of_device.h>
>>>> #include <linux/of_gpio.h>
>>>> #include <linux/pci.h>
>>>> #include <linux/platform_device.h>
>>>> @@ -28,16 +29,6 @@
>>>>
>>>> #define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
>>>>
>>>> -struct exynos_pcie {
>>>> - struct pcie_port pp;
>>>> - void __iomem *elbi_base; /* DT 0th resource */
>>>> - void __iomem *phy_base; /* DT 1st resource */
>>>> - void __iomem *block_base; /* DT 2nd resource */
>>>> - int reset_gpio;
>>>> - struct clk *clk;
>>>> - struct clk *bus_clk;
>>>> -};
>>>> -
>>>> /* PCIe ELBI registers */
>>>> #define PCIE_IRQ_PULSE 0x000
>>>> #define IRQ_INTA_ASSERT BIT(0)
>>>> @@ -102,6 +93,122 @@ struct exynos_pcie {
>>>> #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>>>> #define PCIE_PHY_TRSV3_LVCC 0x31c
>>>>
>>>> +struct exynos_pcie_mem_res {
>>>> + void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
>>>> + void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
>>>> + void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL */
>>>> +};
>>>> +
>>>> +struct exynos_pcie_clk_res {
>>>> + struct clk *clk;
>>>> + struct clk *bus_clk;
>>>> +};
>>>> +
>>>> +struct exynos_pcie {
>>>> + struct pcie_port pp;
>>>> + struct exynos_pcie_mem_res *mem_res;
>>>> + struct exynos_pcie_clk_res *clk_res;
>>>> + const struct exynos_pcie_ops *ops;
>>>> + int reset_gpio;
>>>> +};
>>>> +
>>>> +struct exynos_pcie_ops {
>>>> + int (*get_mem_resources)(struct platform_device *pdev,
>>>> + struct exynos_pcie *ep);
>>>> + int (*get_clk_resources)(struct exynos_pcie *ep);
>>>> + int (*init_clk_resources)(struct exynos_pcie *ep);
>>>> + void (*deinit_clk_resources)(struct exynos_pcie *ep);
>>>> +};
>>>> +
>>>> +static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>>>> + struct exynos_pcie *ep)
>>>> +{
>>>> + struct resource *res;
>>>> + struct device *dev = ep->pp.dev;
>>>> +
>>>> + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
>>>> + if (!ep->mem_res)
>>>> + return -ENOMEM;
>>>> +
>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>> + ep->mem_res->elbi_base = devm_ioremap_resource(dev, res);
>>>> + if (IS_ERR(ep->mem_res->elbi_base))
>>>> + return PTR_ERR(ep->mem_res->elbi_base);
>>>> +
>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>>> + ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>>>> + if (IS_ERR(ep->mem_res->phy_base))
>>>> + return PTR_ERR(ep->mem_res->phy_base);
>>>> +
>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>>>> + ep->mem_res->block_base = devm_ioremap_resource(dev, res);
>>>> + if (IS_ERR(ep->mem_res->block_base))
>>>> + return PTR_ERR(ep->mem_res->block_base);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep)
>>>> +{
>>>> + struct device *dev = ep->pp.dev;
>>>> +
>>>> + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
>>>> + if (!ep->clk_res)
>>>> + return -ENOMEM;
>>>> +
>>>> + ep->clk_res->clk = devm_clk_get(dev, "pcie");
>>>> + if (IS_ERR(ep->clk_res->clk)) {
>>>> + dev_err(dev, "Failed to get pcie rc clock\n");
>>>> + return PTR_ERR(ep->clk_res->clk);
>>>> + }
>>>> +
>>>> + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
>>>> + if (IS_ERR(ep->clk_res->bus_clk)) {
>>>> + dev_err(dev, "Failed to get pcie bus clock\n");
>>>> + return PTR_ERR(ep->clk_res->bus_clk);
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
>>>> +{
>>>> + struct device *dev = ep->pp.dev;
>>>> + int ret;
>>>> +
>>>> + ret = clk_prepare_enable(ep->clk_res->clk);
>>>> + if (ret) {
>>>> + dev_err(dev, "cannot enable pcie rc clock");
>>>> + return ret;
>>>> + }
>>>> +
>>>> + ret = clk_prepare_enable(ep->clk_res->bus_clk);
>>>> + if (ret) {
>>>> + dev_err(dev, "cannot enable pcie bus clock");
>>>> + goto err_bus_clk;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +
>>>> +err_bus_clk:
>>>> + clk_disable_unprepare(ep->clk_res->clk);
>>>> +
>>>> + return ret;
>>>> +}
>>>> +
>>>> +static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep)
>>>> +{
>>>> + clk_disable_unprepare(ep->clk_res->bus_clk);
>>>> + clk_disable_unprepare(ep->clk_res->clk);
>>>> +}
>>>> +
>>>> +static const struct exynos_pcie_ops exynos5440_pcie_ops = {
>>>> + .get_mem_resources = exynos5440_pcie_get_mem_resources,
>>>> + .get_clk_resources = exynos5440_pcie_get_clk_resources,
>>>> + .init_clk_resources = exynos5440_pcie_init_clk_resources,
>>>> + .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
>>>> +};
>>>> +
>>>> static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
>>>> {
>>>> writel(val, base + reg);
>>>> @@ -116,155 +223,155 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
>>>> {
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC);
>>>> if (on)
>>>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>>>> else
>>>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
>>>> }
>>>>
>>>> static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
>>>> {
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC);
>>>> if (on)
>>>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>>>> else
>>>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
>>>> }
>>>>
>>>> static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
>>>> {
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>>>> val &= ~PCIE_CORE_RESET_ENABLE;
>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_PWR_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET);
>>>> }
>>>>
>>>> static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
>>>> {
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>>>> val |= PCIE_CORE_RESET_ENABLE;
>>>>
>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
>>>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_MAC_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
>>>> }
>>>>
>>>> static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
>>>> {
>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_MAC_RESET);
>>>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_GLOBAL_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_MAC_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_GLOBAL_RESET);
>>>> }
>>>>
>>>> static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
>>>> {
>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_GLOBAL_RESET);
>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_PWR_RESET);
>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_COMMON_RESET);
>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_CMN_REG);
>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSVREG_RESET);
>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSV_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_GLOBAL_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_CMN_REG);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSVREG_RESET);
>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSV_RESET);
>>>> }
>>>>
>>>> static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
>>>> {
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
>>>> val &= ~PCIE_PHY_COMMON_PD_CMN;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
>>>> val &= ~PCIE_PHY_TRSV0_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
>>>> val &= ~PCIE_PHY_TRSV1_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
>>>> val &= ~PCIE_PHY_TRSV2_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
>>>> val &= ~PCIE_PHY_TRSV3_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>> }
>>>>
>>>> static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
>>>> {
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
>>>> val |= PCIE_PHY_COMMON_PD_CMN;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
>>>> val |= PCIE_PHY_TRSV0_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
>>>> val |= PCIE_PHY_TRSV1_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
>>>> val |= PCIE_PHY_TRSV2_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>>
>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
>>>> val |= PCIE_PHY_TRSV3_PD_TSV;
>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>> }
>>>>
>>>> static void exynos_pcie_init_phy(struct exynos_pcie *ep)
>>>> {
>>>> /* DCC feedback control off */
>>>> - exynos_pcie_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>>>>
>>>> /* set TX/RX impedance */
>>>> - exynos_pcie_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>>>>
>>>> /* set 50Mhz PHY clock */
>>>> - exynos_pcie_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>>>> - exynos_pcie_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>>>>
>>>> /* set TX Differential output for lane 0 */
>>>> - exynos_pcie_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>>>>
>>>> /* set TX Pre-emphasis Level Control for lane 0 to minimum */
>>>> - exynos_pcie_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>>>>
>>>> /* set RX clock and data recovery bandwidth */
>>>> - exynos_pcie_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>>>>
>>>> /* change TX Pre-emphasis Level Control for lanes */
>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>>>>
>>>> /* set LVCC */
>>>> - exynos_pcie_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>>>> }
>>>>
>>>> static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
>>>> @@ -295,25 +402,27 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>>>> exynos_pcie_init_phy(exynos_pcie);
>>>>
>>>> /* pulse for common reset */
>>>> - exynos_pcie_writel(exynos_pcie->block_base, 1, PCIE_PHY_COMMON_RESET);
>>>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
>>>> + PCIE_PHY_COMMON_RESET);
>>>> udelay(500);
>>>> - exynos_pcie_writel(exynos_pcie->block_base, 0, PCIE_PHY_COMMON_RESET);
>>>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
>>>> + PCIE_PHY_COMMON_RESET);
>>>>
>>>> exynos_pcie_deassert_core_reset(exynos_pcie);
>>>> dw_pcie_setup_rc(pp);
>>>> exynos_pcie_assert_reset(exynos_pcie);
>>>>
>>>> /* assert LTSSM enable */
>>>> - exynos_pcie_writel(exynos_pcie->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
>>>> - PCIE_APP_LTSSM_ENABLE);
>>>> + exynos_pcie_writel(exynos_pcie->mem_res->elbi_base,
>>>> + PCIE_ELBI_LTSSM_ENABLE, PCIE_APP_LTSSM_ENABLE);
>>>>
>>>> /* check if the link is up or not */
>>>> if (!dw_pcie_wait_for_link(pp))
>>>> return 0;
>>>>
>>>> - while (exynos_pcie_readl(exynos_pcie->phy_base,
>>>> + while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>>>> PCIE_PHY_PLL_LOCKED) == 0) {
>>>> - val = exynos_pcie_readl(exynos_pcie->block_base,
>>>> + val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
>>>> PCIE_PHY_PLL_LOCKED);
>>>> dev_info(dev, "PLL Locked: 0x%x\n", val);
>>>> }
>>>> @@ -325,8 +434,8 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
>>>> {
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
>>>> }
>>>>
>>>> static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>>>> @@ -336,7 +445,7 @@ static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>>>> /* enable INTX interrupt */
>>>> val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
>>>> IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
>>>> }
>>>>
>>>> static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
>>>> @@ -363,9 +472,9 @@ static void exynos_pcie_msi_init(struct exynos_pcie *ep)
>>>> dw_pcie_msi_init(pp);
>>>>
>>>> /* enable MSI interrupt */
>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_EN_LEVEL);
>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL);
>>>> val |= IRQ_MSI_ENABLE;
>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>>>> }
>>>>
>>>> static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
>>>> @@ -425,7 +534,8 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
>>>> struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
>>>> u32 val;
>>>>
>>>> - val = exynos_pcie_readl(exynos_pcie->elbi_base, PCIE_ELBI_RDLH_LINKUP);
>>>> + val = exynos_pcie_readl(exynos_pcie->mem_res->elbi_base,
>>>> + PCIE_ELBI_RDLH_LINKUP);
>>>> if (val == PCIE_ELBI_LTSSM_ENABLE)
>>>> return 1;
>>>>
>>>> @@ -503,7 +613,6 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>>> struct exynos_pcie *exynos_pcie;
>>>> struct pcie_port *pp;
>>>> struct device_node *np = dev->of_node;
>>>> - struct resource *res;
>>>> int ret;
>>>>
>>>> exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
>>>> @@ -513,59 +622,37 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>>> pp = &exynos_pcie->pp;
>>>> pp->dev = dev;
>>>>
>>>> - exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>>> -
>>>> - exynos_pcie->clk = devm_clk_get(dev, "pcie");
>>>> - if (IS_ERR(exynos_pcie->clk)) {
>>>> - dev_err(dev, "Failed to get pcie rc clock\n");
>>>> - return PTR_ERR(exynos_pcie->clk);
>>>> - }
>>>> - ret = clk_prepare_enable(exynos_pcie->clk);
>>>> - if (ret)
>>>> - return ret;
>>>> + exynos_pcie->ops = (const struct exynos_pcie_ops *)
>>>> + of_device_get_match_data(dev);
>>>>
>>>> - exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
>>>> - if (IS_ERR(exynos_pcie->bus_clk)) {
>>>> - dev_err(dev, "Failed to get pcie bus clock\n");
>>>> - ret = PTR_ERR(exynos_pcie->bus_clk);
>>>> - goto fail_clk;
>>>> - }
>>>> - ret = clk_prepare_enable(exynos_pcie->bus_clk);
>>>> - if (ret)
>>>> - goto fail_clk;
>>>> + exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>>>
>>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>> - exynos_pcie->elbi_base = devm_ioremap_resource(dev, res);
>>>> - if (IS_ERR(exynos_pcie->elbi_base)) {
>>>> - ret = PTR_ERR(exynos_pcie->elbi_base);
>>>> - goto fail_bus_clk;
>>>> + if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>>>> + ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>>>> + if (ret)
>>>> + return ret;
>>>> }
>>>>
>>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>>> - exynos_pcie->phy_base = devm_ioremap_resource(dev, res);
>>>> - if (IS_ERR(exynos_pcie->phy_base)) {
>>>> - ret = PTR_ERR(exynos_pcie->phy_base);
>>>> - goto fail_bus_clk;
>>>> - }
>>>> + if (exynos_pcie->ops && exynos_pcie->ops->get_clk_resources) {
>>>> + ret = exynos_pcie->ops->get_clk_resources(exynos_pcie);
>>>> + if (ret)
>>>> + return ret;
>>>>
>>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>>>> - exynos_pcie->block_base = devm_ioremap_resource(dev, res);
>>>> - if (IS_ERR(exynos_pcie->block_base)) {
>>>> - ret = PTR_ERR(exynos_pcie->block_base);
>>>> - goto fail_bus_clk;
>>>> + ret = exynos_pcie->ops->init_clk_resources(exynos_pcie);
>>>> + if (ret)
>>>> + return ret;
>>>> }
>>>>
>>>> ret = exynos_add_pcie_port(exynos_pcie, pdev);
>>>> if (ret < 0)
>>>> - goto fail_bus_clk;
>>>> + goto fail_probe;
>>>>
>>>> platform_set_drvdata(pdev, exynos_pcie);
>>>> return 0;
>>>>
>>>> -fail_bus_clk:
>>>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>>>> -fail_clk:
>>>> - clk_disable_unprepare(exynos_pcie->clk);
>>>> +fail_probe:
>>>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>>>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>>> return ret;
>>>> }
>>>>
>>>> @@ -573,14 +660,15 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev)
>>>> {
>>>> struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
>>>>
>>>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>>>> - clk_disable_unprepare(exynos_pcie->clk);
>>>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>>>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>>>
>>>> return 0;
>>>> }
>>>>
>>>> static const struct of_device_id exynos_pcie_of_match[] = {
>>>> - { .compatible = "samsung,exynos5440-pcie", },
>>>> + { .compatible = "samsung,exynos5440-pcie",
>>>> + .data = &exynos5440_pcie_ops },
>>>> {},
>>>> };
>>>>
>>>>
>>>
>>>
>>>
>>
>>
>
>
>
^ permalink raw reply
* [PATCH] PCI: exynos: refactor exynos pcie driver
From: Jaehoon Chung @ 2016-12-27 2:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5861CE23.9060202@samsung.com>
On 12/27/2016 11:12 AM, Alim Akhtar wrote:
>
>
> On 12/27/2016 06:39 AM, Jaehoon Chung wrote:
>> Dear Alim,
>>
>> On 12/26/2016 06:46 PM, Alim Akhtar wrote:
>>> Hello Jaehoon
>>>
>>> On 12/26/2016 02:32 PM, Jaehoon Chung wrote:
>>>> Hi Pankaj,
>>>>
>>>> On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
>>>>> From: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>>>>
>>>>> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
>>>>> This patch does refactoring of Exynos PCIe driver to extend support
>>>>> for other Exynos SoC.
>>>>>
>>>>> Following are the main changes done via this patch:
>>>>> 1) It adds separate structs for memory, clock resources.
>>>>> 2) It add exynos_pcie_ops struct which will allow us to support the
>>>>> differences in resources in different Exynos SoC.
>>>>
>>>> It's nice to me for reusing this file.
>>>> but after considering too many times, i decided not to use this file.
>>>>
>>>> I'm not sure what block base is..actually this pci-exynos.c is really black-box.
>>>> (No one maintains this file, even Samsung didn't care.)
>>>> Who is using this?
>>>> If Someone can share the information about exynos5440, i can refactor everything.
>>>> Otherwise, there are two solution..
>>>>
>>>> One is "adding the new pci-exynos.c" likes pci-exynos5433.c
>>>> Other is "refactor this file" under assuming the each register's usage.
>>>>
>>> Its alway good to reuse code as far as possible.
>>> I am yet to see the details of 5440, but since people are now going to support more Exynos variants, in my opinion, instead of adding pci-exynos5433.c, you can rename current pci-exynos.c to something like pci-exynos5440.c (only in case its too much changes needed to support 5433/exynos7) and lets have a common pci-exynos.c where we can add exynos7/5433 and others SoCs, AFAIK at least exynos7 and 5433 has similar pci controller.
>>
>> Yes, It's always good to reuse. but as you know, current pci-exynos.c file is really specific for only exynos5440.
>> I will try to check about combining.
>>
>>>> I want to use the PHY generic Framework for EXYNOS PCIe.
>>>>
>>> I don't think you have an option here, you should use generic PHY APIs, otherwise phy drive should go to drivers/misc.
>>> Other thoughts are welcome.
>>
>> Why go to drivers/misc? There is driver/phy/ for PHY generic Framework.
>> If i will touch this file, then i will put our phy-exynos-pcie file under driver/phy/ .
>> I already sent the patch for this. Could you check them?
>>
> My point was, if you are not going to use generic PHY APIs, then phy driver should go into drivers/misc. Anyway as you said you have already posted patches with generic phy framework, I will take a look.
Ah. Right..And i'm doing the refactoring to reuse the current pci-exynos.c.
Maybe..Today or Tomorrow..I will send the patches..At that time, could you also check them?
Any comments might be helpful to me! :)
Best Regards,
Jaehoon Chung
>> http://patchwork.ozlabs.org/patch/708738/
>> http://patchwork.ozlabs.org/patch/708742/
>>
> Thanks.
>
>> Best Regards,
>> Jaehoon Chung
>>
>>>
>>>> If you or other guys really want to use the pci-exynos.c for other exynos,
>>>> I will rework with PHY generic framework. Then i will resend the my patches as V2.
>>>>
>>>> One more thing..Does anyone know what the usage of block base is?
>>>> Can i use that register as "syscon"?
>>>>
>>>> Best Regards,
>>>> Jaehoon Chung
>>>>
>>>>>
>>>>> No functional change intended.
>>>>>
>>>>> Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>>>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>>>>> ---
>>>>> This patch set is prepared on top of Krzysztof's for-next and
>>>>> PCIe driver cleanup patch [1] by Jaehoon Chung.
>>>>>
>>>>> [1]: https://lkml.org/lkml/2016/12/19/44
>>>>>
>>>>>
>>>>> drivers/pci/host/pci-exynos.c | 346 ++++++++++++++++++++++++++----------------
>>>>> 1 file changed, 217 insertions(+), 129 deletions(-)
>>>>>
>>>>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
>>>>> index 33562cf..2dc54f7 100644
>>>>> --- a/drivers/pci/host/pci-exynos.c
>>>>> +++ b/drivers/pci/host/pci-exynos.c
>>>>> @@ -17,6 +17,7 @@
>>>>> #include <linux/interrupt.h>
>>>>> #include <linux/kernel.h>
>>>>> #include <linux/init.h>
>>>>> +#include <linux/of_device.h>
>>>>> #include <linux/of_gpio.h>
>>>>> #include <linux/pci.h>
>>>>> #include <linux/platform_device.h>
>>>>> @@ -28,16 +29,6 @@
>>>>>
>>>>> #define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
>>>>>
>>>>> -struct exynos_pcie {
>>>>> - struct pcie_port pp;
>>>>> - void __iomem *elbi_base; /* DT 0th resource */
>>>>> - void __iomem *phy_base; /* DT 1st resource */
>>>>> - void __iomem *block_base; /* DT 2nd resource */
>>>>> - int reset_gpio;
>>>>> - struct clk *clk;
>>>>> - struct clk *bus_clk;
>>>>> -};
>>>>> -
>>>>> /* PCIe ELBI registers */
>>>>> #define PCIE_IRQ_PULSE 0x000
>>>>> #define IRQ_INTA_ASSERT BIT(0)
>>>>> @@ -102,6 +93,122 @@ struct exynos_pcie {
>>>>> #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>>>>> #define PCIE_PHY_TRSV3_LVCC 0x31c
>>>>>
>>>>> +struct exynos_pcie_mem_res {
>>>>> + void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
>>>>> + void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
>>>>> + void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL */
>>>>> +};
>>>>> +
>>>>> +struct exynos_pcie_clk_res {
>>>>> + struct clk *clk;
>>>>> + struct clk *bus_clk;
>>>>> +};
>>>>> +
>>>>> +struct exynos_pcie {
>>>>> + struct pcie_port pp;
>>>>> + struct exynos_pcie_mem_res *mem_res;
>>>>> + struct exynos_pcie_clk_res *clk_res;
>>>>> + const struct exynos_pcie_ops *ops;
>>>>> + int reset_gpio;
>>>>> +};
>>>>> +
>>>>> +struct exynos_pcie_ops {
>>>>> + int (*get_mem_resources)(struct platform_device *pdev,
>>>>> + struct exynos_pcie *ep);
>>>>> + int (*get_clk_resources)(struct exynos_pcie *ep);
>>>>> + int (*init_clk_resources)(struct exynos_pcie *ep);
>>>>> + void (*deinit_clk_resources)(struct exynos_pcie *ep);
>>>>> +};
>>>>> +
>>>>> +static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>>>>> + struct exynos_pcie *ep)
>>>>> +{
>>>>> + struct resource *res;
>>>>> + struct device *dev = ep->pp.dev;
>>>>> +
>>>>> + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
>>>>> + if (!ep->mem_res)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>> + ep->mem_res->elbi_base = devm_ioremap_resource(dev, res);
>>>>> + if (IS_ERR(ep->mem_res->elbi_base))
>>>>> + return PTR_ERR(ep->mem_res->elbi_base);
>>>>> +
>>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>>>> + ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>>>>> + if (IS_ERR(ep->mem_res->phy_base))
>>>>> + return PTR_ERR(ep->mem_res->phy_base);
>>>>> +
>>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>>>>> + ep->mem_res->block_base = devm_ioremap_resource(dev, res);
>>>>> + if (IS_ERR(ep->mem_res->block_base))
>>>>> + return PTR_ERR(ep->mem_res->block_base);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep)
>>>>> +{
>>>>> + struct device *dev = ep->pp.dev;
>>>>> +
>>>>> + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
>>>>> + if (!ep->clk_res)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + ep->clk_res->clk = devm_clk_get(dev, "pcie");
>>>>> + if (IS_ERR(ep->clk_res->clk)) {
>>>>> + dev_err(dev, "Failed to get pcie rc clock\n");
>>>>> + return PTR_ERR(ep->clk_res->clk);
>>>>> + }
>>>>> +
>>>>> + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
>>>>> + if (IS_ERR(ep->clk_res->bus_clk)) {
>>>>> + dev_err(dev, "Failed to get pcie bus clock\n");
>>>>> + return PTR_ERR(ep->clk_res->bus_clk);
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
>>>>> +{
>>>>> + struct device *dev = ep->pp.dev;
>>>>> + int ret;
>>>>> +
>>>>> + ret = clk_prepare_enable(ep->clk_res->clk);
>>>>> + if (ret) {
>>>>> + dev_err(dev, "cannot enable pcie rc clock");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = clk_prepare_enable(ep->clk_res->bus_clk);
>>>>> + if (ret) {
>>>>> + dev_err(dev, "cannot enable pcie bus clock");
>>>>> + goto err_bus_clk;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +
>>>>> +err_bus_clk:
>>>>> + clk_disable_unprepare(ep->clk_res->clk);
>>>>> +
>>>>> + return ret;
>>>>> +}
>>>>> +
>>>>> +static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep)
>>>>> +{
>>>>> + clk_disable_unprepare(ep->clk_res->bus_clk);
>>>>> + clk_disable_unprepare(ep->clk_res->clk);
>>>>> +}
>>>>> +
>>>>> +static const struct exynos_pcie_ops exynos5440_pcie_ops = {
>>>>> + .get_mem_resources = exynos5440_pcie_get_mem_resources,
>>>>> + .get_clk_resources = exynos5440_pcie_get_clk_resources,
>>>>> + .init_clk_resources = exynos5440_pcie_init_clk_resources,
>>>>> + .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
>>>>> +};
>>>>> +
>>>>> static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
>>>>> {
>>>>> writel(val, base + reg);
>>>>> @@ -116,155 +223,155 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
>>>>> {
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
>>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC);
>>>>> if (on)
>>>>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>>>>> else
>>>>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
>>>>> {
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
>>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC);
>>>>> if (on)
>>>>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>>>>> else
>>>>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
>>>>> {
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>>>>> val &= ~PCIE_CORE_RESET_ENABLE;
>>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_PWR_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
>>>>> {
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>>>>> val |= PCIE_CORE_RESET_ENABLE;
>>>>>
>>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
>>>>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_MAC_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
>>>>> {
>>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_MAC_RESET);
>>>>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_GLOBAL_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_MAC_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_GLOBAL_RESET);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
>>>>> {
>>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_GLOBAL_RESET);
>>>>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_PWR_RESET);
>>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_COMMON_RESET);
>>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_CMN_REG);
>>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSVREG_RESET);
>>>>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSV_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_GLOBAL_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_CMN_REG);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSVREG_RESET);
>>>>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSV_RESET);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
>>>>> {
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
>>>>> val &= ~PCIE_PHY_COMMON_PD_CMN;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
>>>>> val &= ~PCIE_PHY_TRSV0_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
>>>>> val &= ~PCIE_PHY_TRSV1_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
>>>>> val &= ~PCIE_PHY_TRSV2_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
>>>>> val &= ~PCIE_PHY_TRSV3_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
>>>>> {
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
>>>>> val |= PCIE_PHY_COMMON_PD_CMN;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
>>>>> val |= PCIE_PHY_TRSV0_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
>>>>> val |= PCIE_PHY_TRSV1_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
>>>>> val |= PCIE_PHY_TRSV2_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
>>>>>
>>>>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>>>>> + val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
>>>>> val |= PCIE_PHY_TRSV3_PD_TSV;
>>>>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_init_phy(struct exynos_pcie *ep)
>>>>> {
>>>>> /* DCC feedback control off */
>>>>> - exynos_pcie_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>>>>>
>>>>> /* set TX/RX impedance */
>>>>> - exynos_pcie_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>>>>>
>>>>> /* set 50Mhz PHY clock */
>>>>> - exynos_pcie_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>>>>>
>>>>> /* set TX Differential output for lane 0 */
>>>>> - exynos_pcie_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>>>>>
>>>>> /* set TX Pre-emphasis Level Control for lane 0 to minimum */
>>>>> - exynos_pcie_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>>>>>
>>>>> /* set RX clock and data recovery bandwidth */
>>>>> - exynos_pcie_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>>>>>
>>>>> /* change TX Pre-emphasis Level Control for lanes */
>>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>>>>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>>>>>
>>>>> /* set LVCC */
>>>>> - exynos_pcie_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>>>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>>>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>>>>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>>>>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
>>>>> @@ -295,25 +402,27 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>>>>> exynos_pcie_init_phy(exynos_pcie);
>>>>>
>>>>> /* pulse for common reset */
>>>>> - exynos_pcie_writel(exynos_pcie->block_base, 1, PCIE_PHY_COMMON_RESET);
>>>>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
>>>>> + PCIE_PHY_COMMON_RESET);
>>>>> udelay(500);
>>>>> - exynos_pcie_writel(exynos_pcie->block_base, 0, PCIE_PHY_COMMON_RESET);
>>>>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
>>>>> + PCIE_PHY_COMMON_RESET);
>>>>>
>>>>> exynos_pcie_deassert_core_reset(exynos_pcie);
>>>>> dw_pcie_setup_rc(pp);
>>>>> exynos_pcie_assert_reset(exynos_pcie);
>>>>>
>>>>> /* assert LTSSM enable */
>>>>> - exynos_pcie_writel(exynos_pcie->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
>>>>> - PCIE_APP_LTSSM_ENABLE);
>>>>> + exynos_pcie_writel(exynos_pcie->mem_res->elbi_base,
>>>>> + PCIE_ELBI_LTSSM_ENABLE, PCIE_APP_LTSSM_ENABLE);
>>>>>
>>>>> /* check if the link is up or not */
>>>>> if (!dw_pcie_wait_for_link(pp))
>>>>> return 0;
>>>>>
>>>>> - while (exynos_pcie_readl(exynos_pcie->phy_base,
>>>>> + while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>>>>> PCIE_PHY_PLL_LOCKED) == 0) {
>>>>> - val = exynos_pcie_readl(exynos_pcie->block_base,
>>>>> + val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
>>>>> PCIE_PHY_PLL_LOCKED);
>>>>> dev_info(dev, "PLL Locked: 0x%x\n", val);
>>>>> }
>>>>> @@ -325,8 +434,8 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
>>>>> {
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
>>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
>>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>>>>> @@ -336,7 +445,7 @@ static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>>>>> /* enable INTX interrupt */
>>>>> val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
>>>>> IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
>>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
>>>>> }
>>>>>
>>>>> static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
>>>>> @@ -363,9 +472,9 @@ static void exynos_pcie_msi_init(struct exynos_pcie *ep)
>>>>> dw_pcie_msi_init(pp);
>>>>>
>>>>> /* enable MSI interrupt */
>>>>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_EN_LEVEL);
>>>>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL);
>>>>> val |= IRQ_MSI_ENABLE;
>>>>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>>>>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>>>>> }
>>>>>
>>>>> static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
>>>>> @@ -425,7 +534,8 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
>>>>> struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
>>>>> u32 val;
>>>>>
>>>>> - val = exynos_pcie_readl(exynos_pcie->elbi_base, PCIE_ELBI_RDLH_LINKUP);
>>>>> + val = exynos_pcie_readl(exynos_pcie->mem_res->elbi_base,
>>>>> + PCIE_ELBI_RDLH_LINKUP);
>>>>> if (val == PCIE_ELBI_LTSSM_ENABLE)
>>>>> return 1;
>>>>>
>>>>> @@ -503,7 +613,6 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>>>> struct exynos_pcie *exynos_pcie;
>>>>> struct pcie_port *pp;
>>>>> struct device_node *np = dev->of_node;
>>>>> - struct resource *res;
>>>>> int ret;
>>>>>
>>>>> exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
>>>>> @@ -513,59 +622,37 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>>>> pp = &exynos_pcie->pp;
>>>>> pp->dev = dev;
>>>>>
>>>>> - exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>>>> -
>>>>> - exynos_pcie->clk = devm_clk_get(dev, "pcie");
>>>>> - if (IS_ERR(exynos_pcie->clk)) {
>>>>> - dev_err(dev, "Failed to get pcie rc clock\n");
>>>>> - return PTR_ERR(exynos_pcie->clk);
>>>>> - }
>>>>> - ret = clk_prepare_enable(exynos_pcie->clk);
>>>>> - if (ret)
>>>>> - return ret;
>>>>> + exynos_pcie->ops = (const struct exynos_pcie_ops *)
>>>>> + of_device_get_match_data(dev);
>>>>>
>>>>> - exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
>>>>> - if (IS_ERR(exynos_pcie->bus_clk)) {
>>>>> - dev_err(dev, "Failed to get pcie bus clock\n");
>>>>> - ret = PTR_ERR(exynos_pcie->bus_clk);
>>>>> - goto fail_clk;
>>>>> - }
>>>>> - ret = clk_prepare_enable(exynos_pcie->bus_clk);
>>>>> - if (ret)
>>>>> - goto fail_clk;
>>>>> + exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>>>>
>>>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>> - exynos_pcie->elbi_base = devm_ioremap_resource(dev, res);
>>>>> - if (IS_ERR(exynos_pcie->elbi_base)) {
>>>>> - ret = PTR_ERR(exynos_pcie->elbi_base);
>>>>> - goto fail_bus_clk;
>>>>> + if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>>>>> + ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> }
>>>>>
>>>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>>>> - exynos_pcie->phy_base = devm_ioremap_resource(dev, res);
>>>>> - if (IS_ERR(exynos_pcie->phy_base)) {
>>>>> - ret = PTR_ERR(exynos_pcie->phy_base);
>>>>> - goto fail_bus_clk;
>>>>> - }
>>>>> + if (exynos_pcie->ops && exynos_pcie->ops->get_clk_resources) {
>>>>> + ret = exynos_pcie->ops->get_clk_resources(exynos_pcie);
>>>>> + if (ret)
>>>>> + return ret;
>>>>>
>>>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>>>>> - exynos_pcie->block_base = devm_ioremap_resource(dev, res);
>>>>> - if (IS_ERR(exynos_pcie->block_base)) {
>>>>> - ret = PTR_ERR(exynos_pcie->block_base);
>>>>> - goto fail_bus_clk;
>>>>> + ret = exynos_pcie->ops->init_clk_resources(exynos_pcie);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> }
>>>>>
>>>>> ret = exynos_add_pcie_port(exynos_pcie, pdev);
>>>>> if (ret < 0)
>>>>> - goto fail_bus_clk;
>>>>> + goto fail_probe;
>>>>>
>>>>> platform_set_drvdata(pdev, exynos_pcie);
>>>>> return 0;
>>>>>
>>>>> -fail_bus_clk:
>>>>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>>>>> -fail_clk:
>>>>> - clk_disable_unprepare(exynos_pcie->clk);
>>>>> +fail_probe:
>>>>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>>>>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>>>> return ret;
>>>>> }
>>>>>
>>>>> @@ -573,14 +660,15 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev)
>>>>> {
>>>>> struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
>>>>>
>>>>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>>>>> - clk_disable_unprepare(exynos_pcie->clk);
>>>>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>>>>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>>>>
>>>>> return 0;
>>>>> }
>>>>>
>>>>> static const struct of_device_id exynos_pcie_of_match[] = {
>>>>> - { .compatible = "samsung,exynos5440-pcie", },
>>>>> + { .compatible = "samsung,exynos5440-pcie",
>>>>> + .data = &exynos5440_pcie_ops },
>>>>> {},
>>>>> };
>>>>>
>>>>>
>>>>
>>>>
>>>>
>>>
>>>
>>
>>
>>
>
>
^ permalink raw reply
* [PATCH] PCI: exynos: refactor exynos pcie driver
From: Pankaj Dubey @ 2016-12-27 3:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <003f01d25d4b$96875e70$c3961b50$@gmail.com>
Hi Jingoo,
On 24 December 2016 at 00:07, Jingoo Han <jingoohan1@gmail.com> wrote:
> On Friday, December 23, 2016 5:56 AM, Pankaj Dubey wrote:
>>
>> From: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>
>> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
>> This patch does refactoring of Exynos PCIe driver to extend support
>> for other Exynos SoC.
>>
>> Following are the main changes done via this patch:
>> 1) It adds separate structs for memory, clock resources.
>
> What is the reason to separate structs for these?
> Please add the reason to this commit message.
> It will be helpful.
>
As we know current driver only supports exynos5440 specific PCIe controller,
We also know for sure that different variant of Exynos SoC will have different
hardware resources such as iomem, clks, regmap handles etc. for PCIe
controller, so our intention behind separating these resources was to make
exynos_pcie struct simple instead of making it complex. All data structs will be
shared by all Exynos SoCs but different exynos_pcie_ops will give them freedom
to use them as per SoC need.
We have refactored current driver in such a way that, even with very minimal
information about exynos5440 we can add support for new SoC's PCIe controller
with maximum core reuse.
>> 2) It add exynos_pcie_ops struct which will allow us to support the
>> differences in resources in different Exynos SoC.
>
Thanks for review. Please let us know if you have any other concern, and it
would be great if you can review this patch more thoroughly.
Thanks,
Pankaj
> Good. I have no objection.
>
> Best regards,
> Jingoo Han
>
>>
>> No functional change intended.
>>
>> Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> ---
>> This patch set is prepared on top of Krzysztof's for-next and
>> PCIe driver cleanup patch [1] by Jaehoon Chung.
>>
>> [1]: https://lkml.org/lkml/2016/12/19/44
>>
>>
>> drivers/pci/host/pci-exynos.c | 346 ++++++++++++++++++++++++++-----------
>> -----
>> 1 file changed, 217 insertions(+), 129 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
>> index 33562cf..2dc54f7 100644
>> --- a/drivers/pci/host/pci-exynos.c
>> +++ b/drivers/pci/host/pci-exynos.c
>> @@ -17,6 +17,7 @@
>> #include <linux/interrupt.h>
>> #include <linux/kernel.h>
>> #include <linux/init.h>
>> +#include <linux/of_device.h>
>> #include <linux/of_gpio.h>
>> #include <linux/pci.h>
>> #include <linux/platform_device.h>
>> @@ -28,16 +29,6 @@
>>
>> #define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
>>
>> -struct exynos_pcie {
>> - struct pcie_port pp;
>> - void __iomem *elbi_base; /* DT 0th resource */
>> - void __iomem *phy_base; /* DT 1st resource */
>> - void __iomem *block_base; /* DT 2nd resource */
>> - int reset_gpio;
>> - struct clk *clk;
>> - struct clk *bus_clk;
>> -};
>> -
>> /* PCIe ELBI registers */
>> #define PCIE_IRQ_PULSE 0x000
>> #define IRQ_INTA_ASSERT BIT(0)
>> @@ -102,6 +93,122 @@ struct exynos_pcie {
>> #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>> #define PCIE_PHY_TRSV3_LVCC 0x31c
>>
>> +struct exynos_pcie_mem_res {
>> + void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
>> + void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
>> + void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL
>> */
>> +};
>> +
>> +struct exynos_pcie_clk_res {
>> + struct clk *clk;
>> + struct clk *bus_clk;
>> +};
>> +
>> +struct exynos_pcie {
>> + struct pcie_port pp;
>> + struct exynos_pcie_mem_res *mem_res;
>> + struct exynos_pcie_clk_res *clk_res;
>> + const struct exynos_pcie_ops *ops;
>> + int reset_gpio;
>> +};
>> +
>> +struct exynos_pcie_ops {
>> + int (*get_mem_resources)(struct platform_device *pdev,
>> + struct exynos_pcie *ep);
>> + int (*get_clk_resources)(struct exynos_pcie *ep);
>> + int (*init_clk_resources)(struct exynos_pcie *ep);
>> + void (*deinit_clk_resources)(struct exynos_pcie *ep);
>> +};
>> +
>> +static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>> + struct exynos_pcie *ep)
>> +{
>> + struct resource *res;
>> + struct device *dev = ep->pp.dev;
>> +
>> + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
>> + if (!ep->mem_res)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + ep->mem_res->elbi_base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(ep->mem_res->elbi_base))
>> + return PTR_ERR(ep->mem_res->elbi_base);
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> + ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(ep->mem_res->phy_base))
>> + return PTR_ERR(ep->mem_res->phy_base);
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>> + ep->mem_res->block_base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(ep->mem_res->block_base))
>> + return PTR_ERR(ep->mem_res->block_base);
>> +
>> + return 0;
>> +}
>> +
>> +static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep)
>> +{
>> + struct device *dev = ep->pp.dev;
>> +
>> + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
>> + if (!ep->clk_res)
>> + return -ENOMEM;
>> +
>> + ep->clk_res->clk = devm_clk_get(dev, "pcie");
>> + if (IS_ERR(ep->clk_res->clk)) {
>> + dev_err(dev, "Failed to get pcie rc clock\n");
>> + return PTR_ERR(ep->clk_res->clk);
>> + }
>> +
>> + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
>> + if (IS_ERR(ep->clk_res->bus_clk)) {
>> + dev_err(dev, "Failed to get pcie bus clock\n");
>> + return PTR_ERR(ep->clk_res->bus_clk);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
>> +{
>> + struct device *dev = ep->pp.dev;
>> + int ret;
>> +
>> + ret = clk_prepare_enable(ep->clk_res->clk);
>> + if (ret) {
>> + dev_err(dev, "cannot enable pcie rc clock");
>> + return ret;
>> + }
>> +
>> + ret = clk_prepare_enable(ep->clk_res->bus_clk);
>> + if (ret) {
>> + dev_err(dev, "cannot enable pcie bus clock");
>> + goto err_bus_clk;
>> + }
>> +
>> + return 0;
>> +
>> +err_bus_clk:
>> + clk_disable_unprepare(ep->clk_res->clk);
>> +
>> + return ret;
>> +}
>> +
>> +static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep)
>> +{
>> + clk_disable_unprepare(ep->clk_res->bus_clk);
>> + clk_disable_unprepare(ep->clk_res->clk);
>> +}
>> +
>> +static const struct exynos_pcie_ops exynos5440_pcie_ops = {
>> + .get_mem_resources = exynos5440_pcie_get_mem_resources,
>> + .get_clk_resources = exynos5440_pcie_get_clk_resources,
>> + .init_clk_resources = exynos5440_pcie_init_clk_resources,
>> + .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
>> +};
>> +
>> static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
>> {
>> writel(val, base + reg);
>> @@ -116,155 +223,155 @@ static void exynos_pcie_sideband_dbi_w_mode(struct
>> exynos_pcie *ep, bool on)
>> {
>> u32 val;
>>
>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
>> + val = exynos_pcie_readl(ep->mem_res->elbi_base,
>> PCIE_ELBI_SLV_AWMISC);
>> if (on)
>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>> else
>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, val,
>> PCIE_ELBI_SLV_AWMISC);
>> }
>>
>> static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool
>> on)
>> {
>> u32 val;
>>
>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
>> + val = exynos_pcie_readl(ep->mem_res->elbi_base,
>> PCIE_ELBI_SLV_ARMISC);
>> if (on)
>> val |= PCIE_ELBI_SLV_DBI_ENABLE;
>> else
>> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, val,
>> PCIE_ELBI_SLV_ARMISC);
>> }
>>
>> static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
>> {
>> u32 val;
>>
>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>> val &= ~PCIE_CORE_RESET_ENABLE;
>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_PWR_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET);
>> }
>>
>> static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
>> {
>> u32 val;
>>
>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
>> val |= PCIE_CORE_RESET_ENABLE;
>>
>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_MAC_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
>> + exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
>> }
>>
>> static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
>> {
>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_MAC_RESET);
>> - exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_GLOBAL_RESET);
>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_MAC_RESET);
>> + exynos_pcie_writel(ep->mem_res->block_base, 1,
>> PCIE_PHY_GLOBAL_RESET);
>> }
>>
>> static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
>> {
>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_GLOBAL_RESET);
>> - exynos_pcie_writel(ep->elbi_base, 1, PCIE_PWR_RESET);
>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_COMMON_RESET);
>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_CMN_REG);
>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSVREG_RESET);
>> - exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSV_RESET);
>> + exynos_pcie_writel(ep->mem_res->block_base, 0,
>> PCIE_PHY_GLOBAL_RESET);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET);
>> + exynos_pcie_writel(ep->mem_res->block_base, 0,
>> PCIE_PHY_COMMON_RESET);
>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_CMN_REG);
>> + exynos_pcie_writel(ep->mem_res->block_base, 0,
>> PCIE_PHY_TRSVREG_RESET);
>> + exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSV_RESET);
>> }
>>
>> static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
>> {
>> u32 val;
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_COMMON_POWER);
>> val &= ~PCIE_PHY_COMMON_PD_CMN;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_COMMON_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV0_POWER);
>> val &= ~PCIE_PHY_TRSV0_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV0_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV1_POWER);
>> val &= ~PCIE_PHY_TRSV1_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV1_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV2_POWER);
>> val &= ~PCIE_PHY_TRSV2_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV2_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV3_POWER);
>> val &= ~PCIE_PHY_TRSV3_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV3_POWER);
>> }
>>
>> static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
>> {
>> u32 val;
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_COMMON_POWER);
>> val |= PCIE_PHY_COMMON_PD_CMN;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_COMMON_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV0_POWER);
>> val |= PCIE_PHY_TRSV0_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV0_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV1_POWER);
>> val |= PCIE_PHY_TRSV1_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV1_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV2_POWER);
>> val |= PCIE_PHY_TRSV2_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV2_POWER);
>>
>> - val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>> + val = exynos_pcie_readl(ep->mem_res->phy_base,
>> PCIE_PHY_TRSV3_POWER);
>> val |= PCIE_PHY_TRSV3_PD_TSV;
>> - exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>> + exynos_pcie_writel(ep->mem_res->phy_base, val,
>> PCIE_PHY_TRSV3_POWER);
>> }
>>
>> static void exynos_pcie_init_phy(struct exynos_pcie *ep)
>> {
>> /* DCC feedback control off */
>> - exynos_pcie_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x29,
>> PCIE_PHY_DCC_FEEDBACK);
>>
>> /* set TX/RX impedance */
>> - exynos_pcie_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>>
>> /* set 50Mhz PHY clock */
>> - exynos_pcie_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>> - exynos_pcie_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>>
>> /* set TX Differential output for lane 0 */
>> - exynos_pcie_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x7f,
>> PCIE_PHY_TRSV0_DRV_LVL);
>>
>> /* set TX Pre-emphasis Level Control for lane 0 to minimum */
>> - exynos_pcie_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x0,
>> PCIE_PHY_TRSV0_EMP_LVL);
>>
>> /* set RX clock and data recovery bandwidth */
>> - exynos_pcie_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>> - exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82,
>> PCIE_PHY_TRSV0_RXCDR);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82,
>> PCIE_PHY_TRSV1_RXCDR);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82,
>> PCIE_PHY_TRSV2_RXCDR);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x82,
>> PCIE_PHY_TRSV3_RXCDR);
>>
>> /* change TX Pre-emphasis Level Control for lanes */
>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>> - exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39,
>> PCIE_PHY_TRSV0_EMP_LVL);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39,
>> PCIE_PHY_TRSV1_EMP_LVL);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39,
>> PCIE_PHY_TRSV2_EMP_LVL);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x39,
>> PCIE_PHY_TRSV3_EMP_LVL);
>>
>> /* set LVCC */
>> - exynos_pcie_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>> - exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0x20,
>> PCIE_PHY_TRSV0_LVCC);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0,
>> PCIE_PHY_TRSV1_LVCC);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0,
>> PCIE_PHY_TRSV2_LVCC);
>> + exynos_pcie_writel(ep->mem_res->phy_base, 0xa0,
>> PCIE_PHY_TRSV3_LVCC);
>> }
>>
>> static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
>> @@ -295,25 +402,27 @@ static int exynos_pcie_establish_link(struct
>> exynos_pcie *exynos_pcie)
>> exynos_pcie_init_phy(exynos_pcie);
>>
>> /* pulse for common reset */
>> - exynos_pcie_writel(exynos_pcie->block_base, 1,
>> PCIE_PHY_COMMON_RESET);
>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
>> + PCIE_PHY_COMMON_RESET);
>> udelay(500);
>> - exynos_pcie_writel(exynos_pcie->block_base, 0,
>> PCIE_PHY_COMMON_RESET);
>> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
>> + PCIE_PHY_COMMON_RESET);
>>
>> exynos_pcie_deassert_core_reset(exynos_pcie);
>> dw_pcie_setup_rc(pp);
>> exynos_pcie_assert_reset(exynos_pcie);
>>
>> /* assert LTSSM enable */
>> - exynos_pcie_writel(exynos_pcie->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
>> - PCIE_APP_LTSSM_ENABLE);
>> + exynos_pcie_writel(exynos_pcie->mem_res->elbi_base,
>> + PCIE_ELBI_LTSSM_ENABLE, PCIE_APP_LTSSM_ENABLE);
>>
>> /* check if the link is up or not */
>> if (!dw_pcie_wait_for_link(pp))
>> return 0;
>>
>> - while (exynos_pcie_readl(exynos_pcie->phy_base,
>> + while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>> PCIE_PHY_PLL_LOCKED) == 0) {
>> - val = exynos_pcie_readl(exynos_pcie->block_base,
>> + val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
>> PCIE_PHY_PLL_LOCKED);
>> dev_info(dev, "PLL Locked: 0x%x\n", val);
>> }
>> @@ -325,8 +434,8 @@ static void exynos_pcie_clear_irq_pulse(struct
>> exynos_pcie *ep)
>> {
>> u32 val;
>>
>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
>> }
>>
>> static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>> @@ -336,7 +445,7 @@ static void exynos_pcie_enable_irq_pulse(struct
>> exynos_pcie *ep)
>> /* enable INTX interrupt */
>> val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
>> IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
>> }
>>
>> static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
>> @@ -363,9 +472,9 @@ static void exynos_pcie_msi_init(struct exynos_pcie
>> *ep)
>> dw_pcie_msi_init(pp);
>>
>> /* enable MSI interrupt */
>> - val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_EN_LEVEL);
>> + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL);
>> val |= IRQ_MSI_ENABLE;
>> - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
>> }
>>
>> static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
>> @@ -425,7 +534,8 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
>> struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
>> u32 val;
>>
>> - val = exynos_pcie_readl(exynos_pcie->elbi_base,
>> PCIE_ELBI_RDLH_LINKUP);
>> + val = exynos_pcie_readl(exynos_pcie->mem_res->elbi_base,
>> + PCIE_ELBI_RDLH_LINKUP);
>> if (val == PCIE_ELBI_LTSSM_ENABLE)
>> return 1;
>>
>> @@ -503,7 +613,6 @@ static int __init exynos_pcie_probe(struct
>> platform_device *pdev)
>> struct exynos_pcie *exynos_pcie;
>> struct pcie_port *pp;
>> struct device_node *np = dev->of_node;
>> - struct resource *res;
>> int ret;
>>
>> exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
>> @@ -513,59 +622,37 @@ static int __init exynos_pcie_probe(struct
>> platform_device *pdev)
>> pp = &exynos_pcie->pp;
>> pp->dev = dev;
>>
>> - exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>> -
>> - exynos_pcie->clk = devm_clk_get(dev, "pcie");
>> - if (IS_ERR(exynos_pcie->clk)) {
>> - dev_err(dev, "Failed to get pcie rc clock\n");
>> - return PTR_ERR(exynos_pcie->clk);
>> - }
>> - ret = clk_prepare_enable(exynos_pcie->clk);
>> - if (ret)
>> - return ret;
>> + exynos_pcie->ops = (const struct exynos_pcie_ops *)
>> + of_device_get_match_data(dev);
>>
>> - exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
>> - if (IS_ERR(exynos_pcie->bus_clk)) {
>> - dev_err(dev, "Failed to get pcie bus clock\n");
>> - ret = PTR_ERR(exynos_pcie->bus_clk);
>> - goto fail_clk;
>> - }
>> - ret = clk_prepare_enable(exynos_pcie->bus_clk);
>> - if (ret)
>> - goto fail_clk;
>> + exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>
>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> - exynos_pcie->elbi_base = devm_ioremap_resource(dev, res);
>> - if (IS_ERR(exynos_pcie->elbi_base)) {
>> - ret = PTR_ERR(exynos_pcie->elbi_base);
>> - goto fail_bus_clk;
>> + if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>> + ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>> + if (ret)
>> + return ret;
>> }
>>
>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> - exynos_pcie->phy_base = devm_ioremap_resource(dev, res);
>> - if (IS_ERR(exynos_pcie->phy_base)) {
>> - ret = PTR_ERR(exynos_pcie->phy_base);
>> - goto fail_bus_clk;
>> - }
>> + if (exynos_pcie->ops && exynos_pcie->ops->get_clk_resources) {
>> + ret = exynos_pcie->ops->get_clk_resources(exynos_pcie);
>> + if (ret)
>> + return ret;
>>
>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>> - exynos_pcie->block_base = devm_ioremap_resource(dev, res);
>> - if (IS_ERR(exynos_pcie->block_base)) {
>> - ret = PTR_ERR(exynos_pcie->block_base);
>> - goto fail_bus_clk;
>> + ret = exynos_pcie->ops->init_clk_resources(exynos_pcie);
>> + if (ret)
>> + return ret;
>> }
>>
>> ret = exynos_add_pcie_port(exynos_pcie, pdev);
>> if (ret < 0)
>> - goto fail_bus_clk;
>> + goto fail_probe;
>>
>> platform_set_drvdata(pdev, exynos_pcie);
>> return 0;
>>
>> -fail_bus_clk:
>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>> -fail_clk:
>> - clk_disable_unprepare(exynos_pcie->clk);
>> +fail_probe:
>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>> return ret;
>> }
>>
>> @@ -573,14 +660,15 @@ static int __exit exynos_pcie_remove(struct
>> platform_device *pdev)
>> {
>> struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
>>
>> - clk_disable_unprepare(exynos_pcie->bus_clk);
>> - clk_disable_unprepare(exynos_pcie->clk);
>> + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>> + exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>
>> return 0;
>> }
>>
>> static const struct of_device_id exynos_pcie_of_match[] = {
>> - { .compatible = "samsung,exynos5440-pcie", },
>> + { .compatible = "samsung,exynos5440-pcie",
>> + .data = &exynos5440_pcie_ops },
>> {},
>> };
>>
>> --
>> 2.7.4
>
>
> --
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> the body of a message to majordomo at vger.kernel.org
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^ permalink raw reply
* [PATCH v18 0/4] Mediatek MT8173 CMDQ support
From: HS Liao @ 2016-12-27 3:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This is Mediatek MT8173 Command Queue(CMDQ) driver. The CMDQ is used
to help write registers with critical time limitation, such as
updating display configuration during the vblank. It controls Global
Command Engine (GCE) hardware to achieve this requirement.
These patches have a build dependency on top of v4.10-rc1.
Changes since v17:
- rebase to v4.10-rc1
Best regards,
HS Liao
HS Liao (4):
dt-bindings: soc: Add documentation for the MediaTek GCE unit
mailbox: mediatek: Add Mediatek CMDQ driver
arm64: dts: mt8173: Add GCE node
soc: mediatek: Add Mediatek CMDQ helper
.../devicetree/bindings/mailbox/mtk-gce.txt | 43 ++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 +
drivers/mailbox/Kconfig | 10 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/mtk-cmdq-mailbox.c | 632 +++++++++++++++++++++
drivers/soc/mediatek/Kconfig | 11 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-cmdq-helper.c | 310 ++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 75 +++
include/linux/soc/mediatek/mtk-cmdq.h | 174 ++++++
10 files changed, 1268 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/mtk-gce.txt
create mode 100644 drivers/mailbox/mtk-cmdq-mailbox.c
create mode 100644 drivers/soc/mediatek/mtk-cmdq-helper.c
create mode 100644 include/linux/mailbox/mtk-cmdq-mailbox.h
create mode 100644 include/linux/soc/mediatek/mtk-cmdq.h
--
1.9.1
^ permalink raw reply
* [PATCH v18 1/4] dt-bindings: soc: Add documentation for the MediaTek GCE unit
From: HS Liao @ 2016-12-27 3:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482809961-31930-1-git-send-email-hs.liao@mediatek.com>
This adds documentation for the MediaTek Global Command Engine (GCE) unit
found in MT8173 SoCs.
Signed-off-by: HS Liao <hs.liao@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/mailbox/mtk-gce.txt | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/mtk-gce.txt
diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
new file mode 100644
index 0000000..d2d3ccb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -0,0 +1,43 @@
+MediaTek GCE
+===============
+
+The Global Command Engine (GCE) is used to help read/write registers with
+critical time limitation, such as updating display configuration during the
+vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
+
+CMDQ driver uses mailbox framework for communication. Please refer to
+mailbox.txt for generic information about mailbox device-tree bindings.
+
+Required properties:
+- compatible: Must be "mediatek,mt8173-gce"
+- reg: Address range of the GCE unit
+- interrupts: The interrupt signal from the GCE block
+- clock: Clocks according to the common clock binding
+- clock-names: Must be "gce" to stand for GCE clock
+- #mbox-cells: Should be 2
+
+Required properties for a client device:
+- mboxes: client use mailbox to communicate with GCE, it should have this
+ property and list of phandle, mailbox channel specifiers, and atomic
+ execution flag.
+
+Example:
+
+ gce: gce at 10212000 {
+ compatible = "mediatek,mt8173-gce";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+
+ #mbox-cells = <2>;
+ };
+
+Example for a client device:
+
+ mmsys: clock-controller at 14000000 {
+ compatible = "mediatek,mt8173-mmsys";
+ mboxes = <&gce 0 1 /* main display with atomic execution */
+ &gce 1 1>; /* sub display with atomic execution */
+ ...
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v18 2/4] mailbox: mediatek: Add Mediatek CMDQ driver
From: HS Liao @ 2016-12-27 3:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482809961-31930-1-git-send-email-hs.liao@mediatek.com>
This patch is first version of Mediatek Command Queue(CMDQ) driver. The
CMDQ is used to help write registers with critical time limitation,
such as updating display configuration during the vblank. It controls
Global Command Engine (GCE) hardware to achieve this requirement.
Currently, CMDQ only supports display related hardwares, but we expect
it can be extended to other hardwares for future requirements.
Signed-off-by: HS Liao <hs.liao@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
---
drivers/mailbox/Kconfig | 10 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/mtk-cmdq-mailbox.c | 632 +++++++++++++++++++++++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 75 ++++
4 files changed, 719 insertions(+)
create mode 100644 drivers/mailbox/mtk-cmdq-mailbox.c
create mode 100644 include/linux/mailbox/mtk-cmdq-mailbox.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index ceff415..9108dd4 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -152,4 +152,14 @@ config BCM_PDC_MBOX
Mailbox implementation for the Broadcom PDC ring manager,
which provides access to various offload engines on Broadcom
SoCs. Say Y here if you want to use the Broadcom PDC.
+
+config MTK_CMDQ_MBOX
+ bool "MediaTek CMDQ Mailbox Support"
+ depends on ARM64 && ( ARCH_MEDIATEK || COMPILE_TEST )
+ select MTK_INFRACFG
+ help
+ Say yes here to add support for the MediaTek Command Queue (CMDQ)
+ mailbox driver. The CMDQ is used to help read/write registers with
+ critical time limitation, such as updating display configuration
+ during the vblank.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 7dde4f6..fad8965 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -31,3 +31,5 @@ obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
+
+obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
new file mode 100644
index 0000000..8771e57
--- /dev/null
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -0,0 +1,632 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+
+#define CMDQ_THR_MAX_COUNT 3 /* main, sub, general(misc) */
+#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
+#define CMDQ_TIMEOUT_MS 1000
+#define CMDQ_IRQ_MASK 0xffff
+#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
+
+#define CMDQ_CURR_IRQ_STATUS 0x10
+#define CMDQ_THR_SLOT_CYCLES 0x30
+
+#define CMDQ_THR_BASE 0x100
+#define CMDQ_THR_SIZE 0x80
+#define CMDQ_THR_WARM_RESET 0x00
+#define CMDQ_THR_ENABLE_TASK 0x04
+#define CMDQ_THR_SUSPEND_TASK 0x08
+#define CMDQ_THR_CURR_STATUS 0x0c
+#define CMDQ_THR_IRQ_STATUS 0x10
+#define CMDQ_THR_IRQ_ENABLE 0x14
+#define CMDQ_THR_CURR_ADDR 0x20
+#define CMDQ_THR_END_ADDR 0x24
+#define CMDQ_THR_WAIT_TOKEN 0x30
+
+#define CMDQ_THR_ENABLED 0x1
+#define CMDQ_THR_DISABLED 0x0
+#define CMDQ_THR_SUSPEND 0x1
+#define CMDQ_THR_RESUME 0x0
+#define CMDQ_THR_STATUS_SUSPENDED BIT(1)
+#define CMDQ_THR_DO_WARM_RESET BIT(0)
+#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
+#define CMDQ_THR_IRQ_DONE 0x1
+#define CMDQ_THR_IRQ_ERROR 0x12
+#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
+#define CMDQ_THR_IS_WAITING BIT(31)
+
+#define CMDQ_JUMP_BY_OFFSET 0x10000000
+#define CMDQ_JUMP_BY_PA 0x10000001
+
+struct cmdq_thread {
+ struct mbox_chan *chan;
+ void __iomem *base;
+ struct list_head task_busy_list;
+ struct timer_list timeout;
+ bool atomic_exec;
+};
+
+struct cmdq_task {
+ struct cmdq *cmdq;
+ struct list_head list_entry;
+ dma_addr_t pa_base;
+ struct cmdq_thread *thread;
+ struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
+};
+
+struct cmdq_clk_release {
+ struct cmdq *cmdq;
+ struct work_struct release_work;
+};
+
+struct cmdq {
+ struct mbox_controller mbox;
+ void __iomem *base;
+ u32 irq;
+ struct workqueue_struct *clk_release_wq;
+ struct cmdq_thread thread[CMDQ_THR_MAX_COUNT];
+ struct clk *clock;
+ bool suspended;
+};
+
+static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
+{
+ u32 status;
+
+ writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
+
+ /* If already disabled, treat as suspended successful. */
+ if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
+ return 0;
+
+ if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
+ status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
+ dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
+ (u32)(thread->base - cmdq->base));
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static void cmdq_thread_resume(struct cmdq_thread *thread)
+{
+ writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
+}
+
+static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
+{
+ u32 warm_reset;
+
+ writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
+ if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
+ warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
+ 0, 10)) {
+ dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
+ (u32)(thread->base - cmdq->base));
+ return -EFAULT;
+ }
+ writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
+ return 0;
+}
+
+static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
+{
+ cmdq_thread_reset(cmdq, thread);
+ writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
+}
+
+/* notify GCE to re-fetch commands by setting GCE thread PC */
+static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
+{
+ writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
+ thread->base + CMDQ_THR_CURR_ADDR);
+}
+
+static void cmdq_task_insert_into_thread(struct cmdq_task *task)
+{
+ struct device *dev = task->cmdq->mbox.dev;
+ struct cmdq_thread *thread = task->thread;
+ struct cmdq_task *prev_task = list_last_entry(
+ &thread->task_busy_list, typeof(*task), list_entry);
+ u64 *prev_task_base = prev_task->pkt->va_base;
+
+ /* let previous task jump to this task */
+ dma_sync_single_for_cpu(dev, prev_task->pa_base,
+ prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
+ prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
+ (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
+ dma_sync_single_for_device(dev, prev_task->pa_base,
+ prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
+
+ cmdq_thread_invalidate_fetched_data(thread);
+}
+
+static bool cmdq_command_is_wfe(u64 cmd)
+{
+ u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
+ u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
+ u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0xffffffff;
+
+ return ((cmd & wfe_mask) == (wfe_op | wfe_option));
+}
+
+/* we assume tasks in the same display GCE thread are waiting the same event. */
+static void cmdq_task_remove_wfe(struct cmdq_task *task)
+{
+ struct device *dev = task->cmdq->mbox.dev;
+ u64 *base = task->pkt->va_base;
+ int i;
+
+ dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
+ DMA_TO_DEVICE);
+ for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
+ if (cmdq_command_is_wfe(base[i]))
+ base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
+ CMDQ_JUMP_PASS;
+ dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
+ DMA_TO_DEVICE);
+}
+
+static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
+{
+ return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
+}
+
+static void cmdq_thread_wait_end(struct cmdq_thread *thread,
+ unsigned long end_pa)
+{
+ struct device *dev = thread->chan->mbox->dev;
+ unsigned long curr_pa;
+
+ if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
+ curr_pa, curr_pa == end_pa, 1, 20))
+ dev_err(dev, "GCE thread cannot run to end.\n");
+}
+
+static void cmdq_task_exec(struct cmdq_pkt *pkt, struct cmdq_thread *thread)
+{
+ struct cmdq *cmdq;
+ struct cmdq_task *task;
+ unsigned long curr_pa, end_pa, flags;
+
+ cmdq = dev_get_drvdata(thread->chan->mbox->dev);
+
+ /* Client should not flush new tasks if suspended. */
+ WARN_ON(cmdq->suspended);
+
+ task = kzalloc(sizeof(*task), GFP_ATOMIC);
+ task->cmdq = cmdq;
+ INIT_LIST_HEAD(&task->list_entry);
+ task->pa_base = dma_map_single(cmdq->mbox.dev, pkt->va_base,
+ pkt->cmd_buf_size, DMA_TO_DEVICE);
+ task->thread = thread;
+ task->pkt = pkt;
+
+ if (list_empty(&thread->task_busy_list)) {
+ /*
+ * Unlock for clk prepare (sleeping function).
+ * This is safe since clk_prepare_enable has internal locks.
+ */
+ spin_unlock_irqrestore(&thread->chan->lock, flags);
+ WARN_ON(clk_prepare_enable(cmdq->clock) < 0);
+ spin_lock_irqsave(&thread->chan->lock, flags);
+
+ WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
+
+ writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
+ writel(task->pa_base + pkt->cmd_buf_size,
+ thread->base + CMDQ_THR_END_ADDR);
+ writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
+ writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
+
+ mod_timer(&thread->timeout,
+ jiffies + msecs_to_jiffies(CMDQ_TIMEOUT_MS));
+ } else {
+ WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+ curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
+ end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
+
+ /*
+ * Atomic execution should remove the following wfe, i.e. only
+ * wait event at first task, and prevent to pause when running.
+ */
+ if (thread->atomic_exec) {
+ /* GCE is executing if command is not WFE */
+ if (!cmdq_thread_is_in_wfe(thread)) {
+ cmdq_thread_resume(thread);
+ cmdq_thread_wait_end(thread, end_pa);
+ WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+ /* set to this task directly */
+ writel(task->pa_base,
+ thread->base + CMDQ_THR_CURR_ADDR);
+ } else {
+ cmdq_task_insert_into_thread(task);
+ cmdq_task_remove_wfe(task);
+ smp_mb(); /* modify jump before enable thread */
+ }
+ } else {
+ /* check boundary */
+ if (curr_pa == end_pa - CMDQ_INST_SIZE ||
+ curr_pa == end_pa) {
+ /* set to this task directly */
+ writel(task->pa_base,
+ thread->base + CMDQ_THR_CURR_ADDR);
+ } else {
+ cmdq_task_insert_into_thread(task);
+ smp_mb(); /* modify jump before enable thread */
+ }
+ }
+ writel(task->pa_base + pkt->cmd_buf_size,
+ thread->base + CMDQ_THR_END_ADDR);
+ cmdq_thread_resume(thread);
+ }
+ list_move_tail(&task->list_entry, &thread->task_busy_list);
+}
+
+static void cmdq_task_exec_done(struct cmdq_task *task, bool err)
+{
+ struct device *dev = task->cmdq->mbox.dev;
+ struct cmdq_cb_data cmdq_cb_data;
+
+ dma_unmap_single(dev, task->pa_base, task->pkt->cmd_buf_size,
+ DMA_TO_DEVICE);
+ if (task->pkt->cb.cb) {
+ cmdq_cb_data.err = err;
+ cmdq_cb_data.data = task->pkt->cb.data;
+ task->pkt->cb.cb(cmdq_cb_data);
+ }
+ list_del(&task->list_entry);
+}
+
+static void cmdq_task_handle_error(struct cmdq_task *task)
+{
+ struct cmdq_thread *thread = task->thread;
+ struct cmdq_task *next_task;
+
+ dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
+ WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
+ next_task = list_first_entry_or_null(&thread->task_busy_list,
+ struct cmdq_task, list_entry);
+ if (next_task)
+ writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
+ cmdq_thread_resume(thread);
+}
+
+static void cmdq_clk_release_work(struct work_struct *work_item)
+{
+ struct cmdq_clk_release *clk_release = container_of(work_item,
+ struct cmdq_clk_release, release_work);
+ struct cmdq *cmdq = clk_release->cmdq;
+
+ clk_disable_unprepare(cmdq->clock);
+ kfree(clk_release);
+}
+
+static void cmdq_clk_release_schedule(struct cmdq *cmdq)
+{
+ struct cmdq_clk_release *clk_release;
+
+ clk_release = kmalloc(sizeof(*clk_release), GFP_ATOMIC);
+ clk_release->cmdq = cmdq;
+ INIT_WORK(&clk_release->release_work, cmdq_clk_release_work);
+ queue_work(cmdq->clk_release_wq, &clk_release->release_work);
+}
+
+static void cmdq_thread_irq_handler(struct cmdq *cmdq,
+ struct cmdq_thread *thread)
+{
+ struct cmdq_task *task, *tmp, *curr_task = NULL;
+ u32 curr_pa, irq_flag, task_end_pa;
+ bool err;
+
+ irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
+ writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
+
+ /*
+ * When ISR call this function, another CPU core could run
+ * "release task" right before we acquire the spin lock, and thus
+ * reset / disable this GCE thread, so we need to check the enable
+ * bit of this GCE thread.
+ */
+ if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
+ return;
+
+ if (irq_flag & CMDQ_THR_IRQ_ERROR)
+ err = true;
+ else if (irq_flag & CMDQ_THR_IRQ_DONE)
+ err = false;
+ else
+ return;
+
+ curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
+
+ list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
+ list_entry) {
+ task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
+ if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
+ curr_task = task;
+
+ if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
+ cmdq_task_exec_done(task, false);
+ kfree(task);
+ } else if (err) {
+ cmdq_task_exec_done(task, true);
+ cmdq_task_handle_error(curr_task);
+ kfree(task);
+ }
+
+ if (curr_task)
+ break;
+ }
+
+ if (list_empty(&thread->task_busy_list)) {
+ cmdq_thread_disable(cmdq, thread);
+ cmdq_clk_release_schedule(cmdq);
+ } else {
+ mod_timer(&thread->timeout,
+ jiffies + msecs_to_jiffies(CMDQ_TIMEOUT_MS));
+ }
+}
+
+static irqreturn_t cmdq_irq_handler(int irq, void *dev)
+{
+ struct cmdq *cmdq = dev;
+ unsigned long irq_status, flags = 0L;
+ int bit;
+
+ irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
+ if (!(irq_status ^ CMDQ_IRQ_MASK))
+ return IRQ_NONE;
+
+ for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {
+ struct cmdq_thread *thread = &cmdq->thread[bit];
+
+ spin_lock_irqsave(&thread->chan->lock, flags);
+ cmdq_thread_irq_handler(cmdq, thread);
+ spin_unlock_irqrestore(&thread->chan->lock, flags);
+ }
+ return IRQ_HANDLED;
+}
+
+static void cmdq_thread_handle_timeout(unsigned long data)
+{
+ struct cmdq_thread *thread = (struct cmdq_thread *)data;
+ struct cmdq *cmdq = container_of(thread->chan->mbox, struct cmdq, mbox);
+ struct cmdq_task *task, *tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&thread->chan->lock, flags);
+ WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+
+ /*
+ * Although IRQ is disabled, GCE continues to execute.
+ * It may have pending IRQ before GCE thread is suspended,
+ * so check this condition again.
+ */
+ cmdq_thread_irq_handler(cmdq, thread);
+
+ if (list_empty(&thread->task_busy_list)) {
+ cmdq_thread_resume(thread);
+ spin_unlock_irqrestore(&thread->chan->lock, flags);
+ return;
+ }
+
+ dev_err(cmdq->mbox.dev, "timeout\n");
+ list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
+ list_entry) {
+ cmdq_task_exec_done(task, true);
+ kfree(task);
+ }
+
+ cmdq_thread_resume(thread);
+ cmdq_thread_disable(cmdq, thread);
+ cmdq_clk_release_schedule(cmdq);
+ spin_unlock_irqrestore(&thread->chan->lock, flags);
+}
+
+static int cmdq_suspend(struct device *dev)
+{
+ struct cmdq *cmdq = dev_get_drvdata(dev);
+ struct cmdq_thread *thread;
+ int i;
+ bool task_running = false;
+
+ cmdq->suspended = true;
+
+ for (i = 0; i < ARRAY_SIZE(cmdq->thread); i++) {
+ thread = &cmdq->thread[i];
+ if (!list_empty(&thread->task_busy_list)) {
+ task_running = true;
+ break;
+ }
+ }
+
+ if (task_running)
+ dev_warn(dev, "exist running task(s) in suspend\n");
+
+ flush_workqueue(cmdq->clk_release_wq);
+ return 0;
+}
+
+static int cmdq_resume(struct device *dev)
+{
+ struct cmdq *cmdq = dev_get_drvdata(dev);
+
+ cmdq->suspended = false;
+ return 0;
+}
+
+static int cmdq_remove(struct platform_device *pdev)
+{
+ struct cmdq *cmdq = platform_get_drvdata(pdev);
+
+ destroy_workqueue(cmdq->clk_release_wq);
+ mbox_controller_unregister(&cmdq->mbox);
+ return 0;
+}
+
+static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+ cmdq_task_exec(data, chan->con_priv);
+ return 0;
+}
+
+static int cmdq_mbox_startup(struct mbox_chan *chan)
+{
+ return 0;
+}
+
+static void cmdq_mbox_shutdown(struct mbox_chan *chan)
+{
+}
+
+static bool cmdq_mbox_last_tx_done(struct mbox_chan *chan)
+{
+ return true;
+}
+
+static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
+ .send_data = cmdq_mbox_send_data,
+ .startup = cmdq_mbox_startup,
+ .shutdown = cmdq_mbox_shutdown,
+ .last_tx_done = cmdq_mbox_last_tx_done,
+};
+
+static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
+ const struct of_phandle_args *sp)
+{
+ int ind = sp->args[0];
+ struct cmdq_thread *thread;
+
+ if (ind >= mbox->num_chans)
+ return ERR_PTR(-EINVAL);
+
+ thread = mbox->chans[ind].con_priv;
+ thread->atomic_exec = (sp->args[1] != 0);
+ thread->chan = &mbox->chans[ind];
+
+ return &mbox->chans[ind];
+}
+
+static int cmdq_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct cmdq *cmdq;
+ int err, i;
+
+ cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
+ if (!cmdq)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ cmdq->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(cmdq->base)) {
+ dev_err(dev, "failed to ioremap gce\n");
+ return PTR_ERR(cmdq->base);
+ }
+
+ cmdq->irq = platform_get_irq(pdev, 0);
+ if (!cmdq->irq) {
+ dev_err(dev, "failed to get irq\n");
+ return -EINVAL;
+ }
+ err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
+ "mtk_cmdq", cmdq);
+ if (err < 0) {
+ dev_err(dev, "failed to register ISR (%d)\n", err);
+ return err;
+ }
+
+ dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
+ dev, cmdq->base, cmdq->irq);
+
+ cmdq->clock = devm_clk_get(dev, "gce");
+ if (IS_ERR(cmdq->clock)) {
+ dev_err(dev, "failed to get gce clk\n");
+ return PTR_ERR(cmdq->clock);
+ }
+
+ cmdq->mbox.dev = dev;
+ cmdq->mbox.chans = devm_kcalloc(dev, CMDQ_THR_MAX_COUNT,
+ sizeof(*cmdq->mbox.chans), GFP_KERNEL);
+ if (!cmdq->mbox.chans)
+ return -ENOMEM;
+
+ cmdq->mbox.num_chans = CMDQ_THR_MAX_COUNT;
+ cmdq->mbox.ops = &cmdq_mbox_chan_ops;
+ cmdq->mbox.of_xlate = cmdq_xlate;
+
+ /* make use of TXDONE_BY_ACK */
+ cmdq->mbox.txdone_irq = false;
+ cmdq->mbox.txdone_poll = false;
+
+ for (i = 0; i < ARRAY_SIZE(cmdq->thread); i++) {
+ cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
+ CMDQ_THR_SIZE * i;
+ INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
+ init_timer(&cmdq->thread[i].timeout);
+ cmdq->thread[i].timeout.function = cmdq_thread_handle_timeout;
+ cmdq->thread[i].timeout.data = (unsigned long)&cmdq->thread[i];
+ cmdq->mbox.chans[i].con_priv = &cmdq->thread[i];
+ }
+
+ err = mbox_controller_register(&cmdq->mbox);
+ if (err < 0) {
+ dev_err(dev, "failed to register mailbox: %d\n", err);
+ return err;
+ }
+
+ cmdq->clk_release_wq = alloc_ordered_workqueue(
+ "%s", WQ_MEM_RECLAIM | WQ_HIGHPRI,
+ "cmdq_clk_release");
+
+ platform_set_drvdata(pdev, cmdq);
+
+ return 0;
+}
+
+static const struct dev_pm_ops cmdq_pm_ops = {
+ .suspend = cmdq_suspend,
+ .resume = cmdq_resume,
+};
+
+static const struct of_device_id cmdq_of_ids[] = {
+ {.compatible = "mediatek,mt8173-gce",},
+ {}
+};
+
+static struct platform_driver cmdq_drv = {
+ .probe = cmdq_probe,
+ .remove = cmdq_remove,
+ .driver = {
+ .name = "mtk_cmdq",
+ .pm = &cmdq_pm_ops,
+ .of_match_table = cmdq_of_ids,
+ }
+};
+
+builtin_platform_driver(cmdq_drv);
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
new file mode 100644
index 0000000..3433c64
--- /dev/null
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MTK_CMDQ_MAILBOX_H__
+#define __MTK_CMDQ_MAILBOX_H__
+
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
+#define CMDQ_OP_CODE_SHIFT 24
+#define CMDQ_JUMP_PASS CMDQ_INST_SIZE
+
+#define CMDQ_WFE_UPDATE BIT(31)
+#define CMDQ_WFE_WAIT BIT(15)
+#define CMDQ_WFE_WAIT_VALUE 0x1
+
+/*
+ * CMDQ_CODE_MASK:
+ * set write mask
+ * format: op mask
+ * CMDQ_CODE_WRITE:
+ * write value into target register
+ * format: op subsys address value
+ * CMDQ_CODE_JUMP:
+ * jump by offset
+ * format: op offset
+ * CMDQ_CODE_WFE:
+ * wait for event and clear
+ * it is just clear if no wait
+ * format: [wait] op event update:1 to_wait:1 wait:1
+ * [clear] op event update:1 to_wait:0 wait:0
+ * CMDQ_CODE_EOC:
+ * end of command
+ * format: op irq_flag
+ */
+enum cmdq_code {
+ CMDQ_CODE_MASK = 0x02,
+ CMDQ_CODE_WRITE = 0x04,
+ CMDQ_CODE_JUMP = 0x10,
+ CMDQ_CODE_WFE = 0x20,
+ CMDQ_CODE_EOC = 0x40,
+};
+
+struct cmdq_cb_data {
+ bool err;
+ void *data;
+};
+
+typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data);
+
+struct cmdq_task_cb {
+ cmdq_async_flush_cb cb;
+ void *data;
+};
+
+struct cmdq_pkt {
+ void *va_base;
+ size_t cmd_buf_size; /* command occupied size */
+ size_t buf_size; /* real buffer size */
+ struct cmdq_task_cb cb;
+};
+
+#endif /* __MTK_CMDQ_MAILBOX_H__ */
--
1.9.1
^ permalink raw reply related
* [PATCH v18 3/4] arm64: dts: mt8173: Add GCE node
From: HS Liao @ 2016-12-27 3:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482809961-31930-1-git-send-email-hs.liao@mediatek.com>
This patch adds the device node of the GCE hardware for CMDQ module.
Signed-off-by: HS Liao <hs.liao@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 12e7027..9f93447 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -422,6 +422,16 @@
status = "disabled";
};
+ gce: gce at 10212000 {
+ compatible = "mediatek,mt8173-gce";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+
+ #mbox-cells = <2>;
+ };
+
mipi_tx0: mipi-dphy at 10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
--
1.9.1
^ permalink raw reply related
* [PATCH v18 4/4] soc: mediatek: Add Mediatek CMDQ helper
From: HS Liao @ 2016-12-27 3:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482809961-31930-1-git-send-email-hs.liao@mediatek.com>
Add Mediatek CMDQ helper to create CMDQ packet and assemble GCE op code.
Signed-off-by: HS Liao <hs.liao@mediatek.com>
---
drivers/soc/mediatek/Kconfig | 11 ++
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-cmdq-helper.c | 310 +++++++++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 174 ++++++++++++++++++
4 files changed, 496 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-cmdq-helper.c
create mode 100644 include/linux/soc/mediatek/mtk-cmdq.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 609bb34..726c09a 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -1,6 +1,17 @@
#
# MediaTek SoC drivers
#
+config MTK_CMDQ
+ bool "MediaTek CMDQ Support"
+ depends on ARM64 && ( ARCH_MEDIATEK || COMPILE_TEST )
+ select MTK_CMDQ_MBOX
+ select MTK_INFRACFG
+ help
+ Say yes here to add support for the MediaTek Command Queue (CMDQ)
+ driver. The CMDQ is used to help read/write registers with critical
+ time limitation, such as updating display configuration during the
+ vblank.
+
config MTK_INFRACFG
bool "MediaTek INFRACFG Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 12998b0..64ce5ee 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
new file mode 100644
index 0000000..7809e65
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/completion.h>
+#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#define CMDQ_SUBSYS_SHIFT 16
+#define CMDQ_ARG_A_WRITE_MASK 0xffff
+#define CMDQ_WRITE_ENABLE_MASK BIT(0)
+#define CMDQ_EOC_IRQ_EN BIT(0)
+#define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
+ << 32 | CMDQ_EOC_IRQ_EN)
+
+struct cmdq_subsys {
+ u32 base;
+ int id;
+};
+
+static const struct cmdq_subsys gce_subsys[] = {
+ {0x1400, 1},
+ {0x1401, 2},
+ {0x1402, 3},
+};
+
+static int cmdq_subsys_base_to_id(u32 base)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gce_subsys); i++)
+ if (gce_subsys[i].base == base)
+ return gce_subsys[i].id;
+ return -EFAULT;
+}
+
+static int cmdq_pkt_realloc_cmd_buffer(struct cmdq_pkt *pkt, size_t size)
+{
+ void *new_buf;
+
+ new_buf = krealloc(pkt->va_base, size, GFP_KERNEL | __GFP_ZERO);
+ if (!new_buf)
+ return -ENOMEM;
+ pkt->va_base = new_buf;
+ pkt->buf_size = size;
+ return 0;
+}
+
+struct cmdq_base *cmdq_register_device(struct device *dev)
+{
+ struct cmdq_base *cmdq_base;
+ struct resource res;
+ int subsys;
+ u32 base;
+
+ if (of_address_to_resource(dev->of_node, 0, &res))
+ return NULL;
+ base = (u32)res.start;
+
+ subsys = cmdq_subsys_base_to_id(base >> 16);
+ if (subsys < 0)
+ return NULL;
+
+ cmdq_base = devm_kmalloc(dev, sizeof(*cmdq_base), GFP_KERNEL);
+ if (!cmdq_base)
+ return NULL;
+ cmdq_base->subsys = subsys;
+ cmdq_base->base = base;
+
+ return cmdq_base;
+}
+EXPORT_SYMBOL(cmdq_register_device);
+
+struct cmdq_client *cmdq_mbox_create(struct device *dev, int index)
+{
+ struct cmdq_client *client;
+
+ client = kzalloc(sizeof(*client), GFP_KERNEL);
+ client->client.dev = dev;
+ client->client.tx_block = false;
+ client->chan = mbox_request_channel(&client->client, index);
+ return client;
+}
+EXPORT_SYMBOL(cmdq_mbox_create);
+
+void cmdq_mbox_destroy(struct cmdq_client *client)
+{
+ mbox_free_channel(client->chan);
+ kfree(client);
+}
+EXPORT_SYMBOL(cmdq_mbox_destroy);
+
+int cmdq_pkt_create(struct cmdq_pkt **pkt_ptr)
+{
+ struct cmdq_pkt *pkt;
+ int err;
+
+ pkt = kzalloc(sizeof(*pkt), GFP_KERNEL);
+ if (!pkt)
+ return -ENOMEM;
+ err = cmdq_pkt_realloc_cmd_buffer(pkt, PAGE_SIZE);
+ if (err < 0) {
+ kfree(pkt);
+ return err;
+ }
+ *pkt_ptr = pkt;
+ return 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_create);
+
+void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
+{
+ kfree(pkt->va_base);
+ kfree(pkt);
+}
+EXPORT_SYMBOL(cmdq_pkt_destroy);
+
+static bool cmdq_pkt_is_finalized(struct cmdq_pkt *pkt)
+{
+ u64 *expect_eoc;
+
+ if (pkt->cmd_buf_size < CMDQ_INST_SIZE << 1)
+ return false;
+
+ expect_eoc = pkt->va_base + pkt->cmd_buf_size - (CMDQ_INST_SIZE << 1);
+ if (*expect_eoc == CMDQ_EOC_CMD)
+ return true;
+
+ return false;
+}
+
+static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
+ u32 arg_a, u32 arg_b)
+{
+ u64 *cmd_ptr;
+ int err;
+
+ if (WARN_ON(cmdq_pkt_is_finalized(pkt)))
+ return -EBUSY;
+ if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
+ err = cmdq_pkt_realloc_cmd_buffer(pkt, pkt->buf_size << 1);
+ if (err < 0)
+ return err;
+ }
+ cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
+ (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
+ pkt->cmd_buf_size += CMDQ_INST_SIZE;
+ return 0;
+}
+
+int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, struct cmdq_base *base,
+ u32 offset)
+{
+ u32 arg_a = ((base->base + offset) & CMDQ_ARG_A_WRITE_MASK) |
+ (base->subsys << CMDQ_SUBSYS_SHIFT);
+ return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
+}
+EXPORT_SYMBOL(cmdq_pkt_write);
+
+int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
+ struct cmdq_base *base, u32 offset, u32 mask)
+{
+ u32 offset_mask = offset;
+ int err;
+
+ if (mask != 0xffffffff) {
+ err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
+ if (err < 0)
+ return err;
+ offset_mask |= CMDQ_WRITE_ENABLE_MASK;
+ }
+ return cmdq_pkt_write(pkt, value, base, offset_mask);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_mask);
+
+static const u32 cmdq_event_value[CMDQ_MAX_EVENT] = {
+ /* Display start of frame(SOF) events */
+ [CMDQ_EVENT_DISP_OVL0_SOF] = 11,
+ [CMDQ_EVENT_DISP_OVL1_SOF] = 12,
+ [CMDQ_EVENT_DISP_RDMA0_SOF] = 13,
+ [CMDQ_EVENT_DISP_RDMA1_SOF] = 14,
+ [CMDQ_EVENT_DISP_RDMA2_SOF] = 15,
+ [CMDQ_EVENT_DISP_WDMA0_SOF] = 16,
+ [CMDQ_EVENT_DISP_WDMA1_SOF] = 17,
+ /* Display end of frame(EOF) events */
+ [CMDQ_EVENT_DISP_OVL0_EOF] = 39,
+ [CMDQ_EVENT_DISP_OVL1_EOF] = 40,
+ [CMDQ_EVENT_DISP_RDMA0_EOF] = 41,
+ [CMDQ_EVENT_DISP_RDMA1_EOF] = 42,
+ [CMDQ_EVENT_DISP_RDMA2_EOF] = 43,
+ [CMDQ_EVENT_DISP_WDMA0_EOF] = 44,
+ [CMDQ_EVENT_DISP_WDMA1_EOF] = 45,
+ /* Mutex end of frame(EOF) events */
+ [CMDQ_EVENT_MUTEX0_STREAM_EOF] = 53,
+ [CMDQ_EVENT_MUTEX1_STREAM_EOF] = 54,
+ [CMDQ_EVENT_MUTEX2_STREAM_EOF] = 55,
+ [CMDQ_EVENT_MUTEX3_STREAM_EOF] = 56,
+ [CMDQ_EVENT_MUTEX4_STREAM_EOF] = 57,
+ /* Display underrun events */
+ [CMDQ_EVENT_DISP_RDMA0_UNDERRUN] = 63,
+ [CMDQ_EVENT_DISP_RDMA1_UNDERRUN] = 64,
+ [CMDQ_EVENT_DISP_RDMA2_UNDERRUN] = 65,
+};
+
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, enum cmdq_event event)
+{
+ u32 arg_b;
+
+ if (event >= CMDQ_MAX_EVENT || event < 0)
+ return -EINVAL;
+
+ /*
+ * WFE arg_b
+ * bit 0-11: wait value
+ * bit 15: 1 - wait, 0 - no wait
+ * bit 16-27: update value
+ * bit 31: 1 - update, 0 - no update
+ */
+ arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
+ return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE,
+ cmdq_event_value[event], arg_b);
+}
+EXPORT_SYMBOL(cmdq_pkt_wfe);
+
+int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, enum cmdq_event event)
+{
+ if (event >= CMDQ_MAX_EVENT || event < 0)
+ return -EINVAL;
+
+ return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE,
+ cmdq_event_value[event], CMDQ_WFE_UPDATE);
+}
+EXPORT_SYMBOL(cmdq_pkt_clear_event);
+
+static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
+{
+ int err;
+
+ if (cmdq_pkt_is_finalized(pkt))
+ return 0;
+
+ /* insert EOC and generate IRQ for each command iteration */
+ err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN);
+ if (err < 0)
+ return err;
+
+ /* JUMP to end */
+ err = cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+int cmdq_pkt_flush_async(struct cmdq_client *client, struct cmdq_pkt *pkt,
+ cmdq_async_flush_cb cb, void *data)
+{
+ int err;
+
+ err = cmdq_pkt_finalize(pkt);
+ if (err < 0)
+ return err;
+
+ pkt->cb.cb = cb;
+ pkt->cb.data = data;
+
+ mbox_send_message(client->chan, pkt);
+ /* We can send next packet immediately, so just call txdone. */
+ mbox_client_txdone(client->chan, 0);
+
+ return 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_flush_async);
+
+struct cmdq_flush_completion {
+ struct completion cmplt;
+ bool err;
+};
+
+static void cmdq_pkt_flush_cb(struct cmdq_cb_data data)
+{
+ struct cmdq_flush_completion *cmplt = data.data;
+
+ cmplt->err = data.err;
+ complete(&cmplt->cmplt);
+}
+
+int cmdq_pkt_flush(struct cmdq_client *client, struct cmdq_pkt *pkt)
+{
+ struct cmdq_flush_completion cmplt;
+ int err;
+
+ init_completion(&cmplt.cmplt);
+ err = cmdq_pkt_flush_async(client, pkt, cmdq_pkt_flush_cb, &cmplt);
+ if (err < 0)
+ return err;
+ wait_for_completion(&cmplt.cmplt);
+ return cmplt.err ? -EFAULT : 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_flush);
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
new file mode 100644
index 0000000..5b35d73
--- /dev/null
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MTK_CMDQ_H__
+#define __MTK_CMDQ_H__
+
+#include <linux/mailbox_client.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+
+/* display events in command queue(CMDQ) */
+enum cmdq_event {
+ /* Display start of frame(SOF) events */
+ CMDQ_EVENT_DISP_OVL0_SOF,
+ CMDQ_EVENT_DISP_OVL1_SOF,
+ CMDQ_EVENT_DISP_RDMA0_SOF,
+ CMDQ_EVENT_DISP_RDMA1_SOF,
+ CMDQ_EVENT_DISP_RDMA2_SOF,
+ CMDQ_EVENT_DISP_WDMA0_SOF,
+ CMDQ_EVENT_DISP_WDMA1_SOF,
+ /* Display end of frame(EOF) events */
+ CMDQ_EVENT_DISP_OVL0_EOF,
+ CMDQ_EVENT_DISP_OVL1_EOF,
+ CMDQ_EVENT_DISP_RDMA0_EOF,
+ CMDQ_EVENT_DISP_RDMA1_EOF,
+ CMDQ_EVENT_DISP_RDMA2_EOF,
+ CMDQ_EVENT_DISP_WDMA0_EOF,
+ CMDQ_EVENT_DISP_WDMA1_EOF,
+ /* Mutex end of frame(EOF) events */
+ CMDQ_EVENT_MUTEX0_STREAM_EOF,
+ CMDQ_EVENT_MUTEX1_STREAM_EOF,
+ CMDQ_EVENT_MUTEX2_STREAM_EOF,
+ CMDQ_EVENT_MUTEX3_STREAM_EOF,
+ CMDQ_EVENT_MUTEX4_STREAM_EOF,
+ /* Display underrun events */
+ CMDQ_EVENT_DISP_RDMA0_UNDERRUN,
+ CMDQ_EVENT_DISP_RDMA1_UNDERRUN,
+ CMDQ_EVENT_DISP_RDMA2_UNDERRUN,
+ /* Keep this at the end */
+ CMDQ_MAX_EVENT,
+};
+
+struct cmdq_pkt;
+
+struct cmdq_base {
+ int subsys;
+ u32 base;
+};
+
+struct cmdq_client {
+ struct mbox_client client;
+ struct mbox_chan *chan;
+};
+
+/**
+ * cmdq_register_device() - register device which needs CMDQ
+ * @dev: device for CMDQ to access its registers
+ *
+ * Return: cmdq_base pointer or NULL for failed
+ */
+struct cmdq_base *cmdq_register_device(struct device *dev);
+
+/**
+ * cmdq_mbox_create() - create CMDQ mailbox client and channel
+ * @dev: device of CMDQ mailbox client
+ * @index: index of CMDQ mailbox channel
+ *
+ * Return: CMDQ mailbox client pointer
+ */
+struct cmdq_client *cmdq_mbox_create(struct device *dev, int index);
+
+/**
+ * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
+ * @client: the CMDQ mailbox client
+ */
+void cmdq_mbox_destroy(struct cmdq_client *client);
+
+/**
+ * cmdq_pkt_create() - create a CMDQ packet
+ * @pkt_ptr: CMDQ packet pointer to retrieve cmdq_pkt
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_create(struct cmdq_pkt **pkt_ptr);
+
+/**
+ * cmdq_pkt_destroy() - destroy the CMDQ packet
+ * @pkt: the CMDQ packet
+ */
+void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
+
+/**
+ * cmdq_pkt_write() - append write command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @value: the specified target register value
+ * @base: the CMDQ base
+ * @offset: register offset from module base
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value,
+ struct cmdq_base *base, u32 offset);
+
+/**
+ * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @value: the specified target register value
+ * @base: the CMDQ base
+ * @offset: register offset from module base
+ * @mask: the specified target register mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
+ struct cmdq_base *base, u32 offset, u32 mask);
+
+/**
+ * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @event: the desired event type to "wait and CLEAR"
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, enum cmdq_event event);
+
+/**
+ * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @event: the desired event to be cleared
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, enum cmdq_event event);
+
+/**
+ * cmdq_pkt_flush() - trigger CMDQ to execute the CMDQ packet
+ * @client: the CMDQ mailbox client
+ * @pkt: the CMDQ packet
+ *
+ * Return: 0 for success; else the error code is returned
+ *
+ * Trigger CMDQ to execute the CMDQ packet. Note that this is a
+ * synchronous flush function. When the function returned, the recorded
+ * commands have been done.
+ */
+int cmdq_pkt_flush(struct cmdq_client *client, struct cmdq_pkt *pkt);
+
+/**
+ * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
+ * packet and call back at the end of done packet
+ * @client: the CMDQ mailbox client
+ * @pkt: the CMDQ packet
+ * @cb: called at the end of done packet
+ * @data: this data will pass back to cb
+ *
+ * Return: 0 for success; else the error code is returned
+ *
+ * Trigger CMDQ to asynchronously execute the CMDQ packet and call back
+ * at the end of done packet. Note that this is an ASYNC function. When the
+ * function returned, it may or may not be finished.
+ */
+int cmdq_pkt_flush_async(struct cmdq_client *client, struct cmdq_pkt *pkt,
+ cmdq_async_flush_cb cb, void *data);
+
+#endif /* __MTK_CMDQ_H__ */
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 1/7] PF driver modified to enable HW filter support, changes works in backward compatibility mode Enable required things in Makefile Enable LZ4 dependecy inside config file
From: Sunil Kovvuri @ 2016-12-27 4:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DM5PR07MB28428EE7B1679FAEC78103AD8D960@DM5PR07MB2842.namprd07.prod.outlook.com>
>> #define NIC_MAX_RSS_HASH_BITS 8
>> #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
>> +#define NIC_TNS_RSS_IDR_TBL_SIZE 5
>
> So you want to use only 5 queues per VF when TNS is enabled, is it ??
> There are 4096 RSS indices in total, for each VF you can use max 32.
> I guess you wanted to set no of hash bits to 5 instead of table size.
>
> SATHA>>> We enabled 8 queues for VF. Yes Macro name misleads it has to be hash bits, will change this in next version
No, I am not referring to any discrepancy in naming the macro.
If you check your code
- hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
+ hw->rss_ind_tbl_size = veb_enabled ? NIC_TNS_RSS_IDR_TBL_SIZE :
+ NIC_MAX_RSS_IDR_TBL_SIZE;
You are setting RSS table size to 5, i.e RSS hash bits will be set to 2.
Hence only 4 queues (not even 5 as i mentioned earlier). Please check
'nicvf_rss_init' you will understand what i am saying.
Have you tested and observed pkts in all 8 queues ?
^ permalink raw reply
* [PATCH] PCI: exynos: refactor exynos pcie driver
From: Pankaj Dubey @ 2016-12-27 4:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e1f37a59-b633-7b9d-cc79-dbbb00a24cda@samsung.com>
Hi Jaehoon,
On 26 December 2016 at 14:32, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi Pankaj,
>
> On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
>> From: Niyas Ahmed S T <niyas.ahmed@samsung.com>
>>
>> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
>> This patch does refactoring of Exynos PCIe driver to extend support
>> for other Exynos SoC.
>>
>> Following are the main changes done via this patch:
>> 1) It adds separate structs for memory, clock resources.
>> 2) It add exynos_pcie_ops struct which will allow us to support the
>> differences in resources in different Exynos SoC.
>
> It's nice to me for reusing this file.
> but after considering too many times, i decided not to use this file.
>
It would be better if we redesign/modify existing driver to support new single
driver for all Exynos SoC.
For this we can have internal discussion and design it so that it
becomes suitable
for other Exynos SoC PCIe controllers.
> I'm not sure what block base is..actually this pci-exynos.c is really black-box.
I saw Jingoo already explained about block base, so it may or may not be used in
other exynos. If it is used they can reuse this variable and related
code, if not the
implementation of exynos_pcie_ops hooks should be written in such a way that
ignores (do not initializes/uses) block_base.
> (No one maintains this file, even Samsung didn't care.)
> Who is using this?
I feel now we we (you and me) will care for it, at least we have use
case for this now :)
> If Someone can share the information about exynos5440, i can refactor everything.
> Otherwise, there are two solution..
>
We also do not have access to exynos5440 hardware, but we do have access
to exynos5440 UM, so we can see some details of these SFRs. Based on
our understanding
we refactored this code for making it more suitable for other SoC.
Regarding phy_base and block_base as they are phy related it need to
be replaced with phy driver, so for this we can reuse your RFC patch
of pcie-phy. Even phy driver design should be
such that it can support multiple Exynos SoC PCIe-Phy.
> One is "adding the new pci-exynos.c" likes pci-exynos5433.c
I know exynos5433 and exynos7 SoC have similar PCIe controller, although they
may share comparatively less similarity with exynos5440. If start
adding new file for
each SoC we may end of lot of code duplication.
> Other is "refactor this file" under assuming the each register's usage.
>
IMHO, this would be good design decision.
We have separate various resources of exynos_pcie struct such as iomem
and clks for
the timebeing, and these resources can be managed via exynos_pcie_ops
which can have different implementation for different SoCs, we have
freedom to handle these resources per SoC. If some SoCs share similar
PCIe controller h/w design, code will be reused.
> I want to use the PHY generic Framework for EXYNOS PCIe.
>
> If you or other guys really want to use the pci-exynos.c for other exynos,
> I will rework with PHY generic framework. Then i will resend the my patches as V2.
>
> One more thing..Does anyone know what the usage of block base is?
> Can i use that register as "syscon"?
>
I think this is not exactly syscon, as it only be used in pcie-phy,
so we can use this as child device of phy-device.
> Best Regards,
> Jaehoon Chung
>
Thanks,
Pankaj Dubey
^ permalink raw reply
* [PATCH v2] watchdog: constify watchdog_info structures
From: Baruch Siach @ 2016-12-27 5:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482771911-13548-1-git-send-email-bhumirks@gmail.com>
Hi Bhumika Goyal,
On Mon, Dec 26, 2016 at 10:35:11PM +0530, Bhumika Goyal wrote:
> Declare watchdog_info structures as const as they are only stored in the
> info field of watchdog_device structures. This field is of type const
> struct watchdog_info *, so watchdog_info structures having this property
> can be declared const too.
> Done using Coccinelle:
>
> @r1 disable optional_qualifier@
> identifier i;
> position p;
> @@
> static struct watchdog_info i at p={...};
>
> @ok@
> identifier r1.i;
> position p;
> struct watchdog_device obj;
> @@
> obj.info=&i at p;
>
> @bad@
> position p!={r1.p,ok.p};
> identifier r1.i;
> @@
> i at p
>
> @depends on !bad disable optional_qualifier@
> identifier r1.i;
> @@
> +const
> struct watchdog_info i;
>
> Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
For digicolor_wdt.c:
Acked-by: Baruch Siach <baruch@tkos.co.il>
Thanks,
baruch
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply
* [PATCH 1/3 v2] iio: adc: add device tree bindings for Qualcomm PM8xxx ADCs
From: Bjorn Andersson @ 2016-12-27 5:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481842089-13999-1-git-send-email-linus.walleij@linaro.org>
On Thu 15 Dec 14:48 PST 2016, Linus Walleij wrote:
Sorry for taking so long time to give this a test.
> ---
> .../bindings/iio/adc/qcom,pm8xxx-xoadc.txt | 160 +++++++++++++++++++++
> 1 file changed, 160 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
[..]
> +
> +- reg: should contain the ADC base address in the PMIC, typically
> + 0x197.
xoadc-ref is "required" by the code (setting 2.2V on the dummy regulator
returned in its absence will fail), so it should be mentioned here.
On 8064 pm8921_l14 seems to be our reference, which is 1.8V.
[..]
> +
> +- qcom,ratiometric:
> + Value type: <empty>
> + Definition: Channel calibration type. If this property is specified
> + VADC will use the VDD reference (1.8V) and GND for channel
> + calibration. If the property is not found, the channel will be
> + calibrated with the 0.625V and 1.25V reference channels, also
> + known as an absolute calibration.
So if I specify this property the reference should be 1.8V and if I
specify qcom,ratiometric-ref I will override this? Also, the
implementation requires that qcom,ratiometric-ref is specified if the
boolean property is used.
Am I missing something or should we just squash them?
> +
> +- qcom,ratiometric-ref:
> + Value type: <u32>
> + Definition: The reference voltage pair when using ratiometric
> + calibration:
> + 0 = XO_IN/XOADC_GND
> + 1 = PMIC_IN/XOADC_GND
> + 2 = PMIC_IN/BMS_CSP
> + 3 (invalid)
> + 4 = XOADC_GND/XOADC_GND
> + 5 = XOADC_VREF/XOADC_GND
> +
> +Example:
> +
> +xoadc: xoadc at 197 {
> + compatible = "qcom,pm8058-adc";
> + reg = <0x197>;
> + interrupt-parent = <&pm8058>;
> + interrupts = <76 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
xoadc-ref-supply = <>;
> +
> + vcoin {
As the node has a "reg" you need to add @0 on these.
> + reg = <0x00>;
> + };
Regards,
Bjorn
^ permalink raw reply
* [PATCH v4 0/4] clk: rockchip: support clk controller for rk3328 SoC
From: Elaine Zhang @ 2016-12-27 6:32 UTC (permalink / raw)
To: linux-arm-kernel
Changes in v4:
dropping the "rockchip,cru" and "syscon" properties for bindings of rk3328
adjust the pacth 3 and 4 order.
move pll_rk3328 to patch 3.
Changes in v3:
fix up the pll type pll_rk3328 description and use.
Changes in v2:
add bindings for rk3328 clock controller
Elaine Zhang (4):
clk: rockchip: add dt-binding header for rk3328
dt-bindings: add bindings for rk3328 clock controller
clk: rockchip: add new pll-type for rk3328
clk: rockchip: add clock controller for rk3328
.../bindings/clock/rockchip,rk3328-cru.txt | 57 ++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-pll.c | 16 +-
drivers/clk/rockchip/clk-rk3328.c | 1068 ++++++++++++++++++++
drivers/clk/rockchip/clk.h | 23 +
include/dt-bindings/clock/rk3328-cru.h | 403 ++++++++
6 files changed, 1565 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
create mode 100644 drivers/clk/rockchip/clk-rk3328.c
create mode 100644 include/dt-bindings/clock/rk3328-cru.h
--
1.9.1
^ permalink raw reply
* [PATCH v4 1/4] clk: rockchip: add dt-binding header for rk3328
From: Elaine Zhang @ 2016-12-27 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482820373-10186-1-git-send-email-zhangqing@rock-chips.com>
Add the dt-bindings header for the rk3328, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3328.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
include/dt-bindings/clock/rk3328-cru.h | 403 +++++++++++++++++++++++++++++++++
1 file changed, 403 insertions(+)
create mode 100644 include/dt-bindings/clock/rk3328-cru.h
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
new file mode 100644
index 000000000000..545ed7541316
--- /dev/null
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Elaine <zhangqing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_GPLL 4
+#define PLL_NPLL 5
+#define ARMCLK 6
+
+/* sclk gates (special clocks) */
+#define SCLK_RTC32K 30
+#define SCLK_SDMMC_EXT 31
+#define SCLK_SPI 32
+#define SCLK_SDMMC 33
+#define SCLK_SDIO 34
+#define SCLK_EMMC 35
+#define SCLK_TSADC 36
+#define SCLK_SARADC 37
+#define SCLK_UART0 38
+#define SCLK_UART1 39
+#define SCLK_UART2 40
+#define SCLK_I2S0 41
+#define SCLK_I2S1 42
+#define SCLK_I2S2 43
+#define SCLK_I2S1_OUT 44
+#define SCLK_I2S2_OUT 45
+#define SCLK_SPDIF 46
+#define SCLK_TIMER0 47
+#define SCLK_TIMER1 48
+#define SCLK_TIMER2 49
+#define SCLK_TIMER3 50
+#define SCLK_TIMER4 51
+#define SCLK_TIMER5 52
+#define SCLK_WIFI 53
+#define SCLK_CIF_OUT 54
+#define SCLK_I2C0 55
+#define SCLK_I2C1 56
+#define SCLK_I2C2 57
+#define SCLK_I2C3 58
+#define SCLK_CRYPTO 59
+#define SCLK_PWM 60
+#define SCLK_PDM 61
+#define SCLK_EFUSE 62
+#define SCLK_OTP 63
+#define SCLK_DDRCLK 64
+#define SCLK_VDEC_CABAC 65
+#define SCLK_VDEC_CORE 66
+#define SCLK_VENC_DSP 67
+#define SCLK_VENC_CORE 68
+#define SCLK_RGA 69
+#define SCLK_HDMI_SFC 70
+#define SCLK_HDMI_CEC 71
+#define SCLK_USB3_REF 72
+#define SCLK_USB3_SUSPEND 73
+#define SCLK_SDMMC_DRV 74
+#define SCLK_SDIO_DRV 75
+#define SCLK_EMMC_DRV 76
+#define SCLK_SDMMC_EXT_DRV 77
+#define SCLK_SDMMC_SAMPLE 78
+#define SCLK_SDIO_SAMPLE 79
+#define SCLK_EMMC_SAMPLE 80
+#define SCLK_SDMMC_EXT_SAMPLE 81
+#define SCLK_VOP 82
+#define SCLK_MAC2PHY_RXTX 83
+#define SCLK_MAC2PHY_SRC 84
+#define SCLK_MAC2PHY_REF 85
+#define SCLK_MAC2PHY_OUT 86
+#define SCLK_MAC2IO_RX 87
+#define SCLK_MAC2IO_TX 88
+#define SCLK_MAC2IO_REFOUT 89
+#define SCLK_MAC2IO_REF 90
+#define SCLK_MAC2IO_OUT 91
+#define SCLK_TSP 92
+#define SCLK_HSADC_TSP 93
+#define SCLK_USB3PHY_REF 94
+#define SCLK_REF_USB3OTG 95
+#define SCLK_USB3OTG_REF 96
+#define SCLK_USB3OTG_SUSPEND 97
+#define SCLK_REF_USB3OTG_SRC 98
+#define SCLK_MAC2IO_SRC 99
+
+/* dclk gates */
+#define DCLK_LCDC 180
+#define DCLK_HDMIPHY 181
+#define HDMIPHY 182
+#define USB480M 183
+#define DCLK_LCDC_SRC 184
+
+/* aclk gates */
+#define ACLK_AXISRAM 190
+#define ACLK_VOP_PRE 191
+#define ACLK_USB3OTG 192
+#define ACLK_RGA_PRE 193
+#define ACLK_DMAC 194
+#define ACLK_GPU 195
+#define ACLK_BUS_PRE 196
+#define ACLK_PERI_PRE 197
+#define ACLK_RKVDEC_PRE 198
+#define ACLK_RKVDEC 199
+#define ACLK_RKVENC 200
+#define ACLK_VPU_PRE 201
+#define ACLK_VIO_PRE 202
+#define ACLK_VPU 203
+#define ACLK_VIO 204
+#define ACLK_VOP 205
+#define ACLK_GMAC 206
+#define ACLK_H265 207
+#define ACLK_H264 208
+#define ACLK_MAC2PHY 209
+#define ACLK_MAC2IO 210
+#define ACLK_DCF 211
+#define ACLK_TSP 212
+#define ACLK_PERI 213
+#define ACLK_RGA 214
+#define ACLK_IEP 215
+#define ACLK_CIF 216
+#define ACLK_HDCP 217
+
+/* pclk gates */
+#define PCLK_GPIO0 300
+#define PCLK_GPIO1 301
+#define PCLK_GPIO2 302
+#define PCLK_GPIO3 303
+#define PCLK_GRF 304
+#define PCLK_I2C0 305
+#define PCLK_I2C1 306
+#define PCLK_I2C2 307
+#define PCLK_I2C3 308
+#define PCLK_SPI 309
+#define PCLK_UART0 310
+#define PCLK_UART1 311
+#define PCLK_UART2 312
+#define PCLK_TSADC 313
+#define PCLK_PWM 314
+#define PCLK_TIMER 315
+#define PCLK_BUS_PRE 316
+#define PCLK_PERI_PRE 317
+#define PCLK_HDMI_CTRL 318
+#define PCLK_HDMI_PHY 319
+#define PCLK_GMAC 320
+#define PCLK_H265 321
+#define PCLK_MAC2PHY 322
+#define PCLK_MAC2IO 323
+#define PCLK_USB3PHY_OTG 324
+#define PCLK_USB3PHY_PIPE 325
+#define PCLK_USB3_GRF 326
+#define PCLK_USB2_GRF 327
+#define PCLK_HDMIPHY 328
+#define PCLK_DDR 329
+#define PCLK_PERI 330
+#define PCLK_HDMI 331
+#define PCLK_HDCP 332
+#define PCLK_DCF 333
+#define PCLK_SARADC 334
+
+/* hclk gates */
+#define HCLK_PERI 408
+#define HCLK_TSP 409
+#define HCLK_GMAC 410
+#define HCLK_I2S0_8CH 411
+#define HCLK_I2S1_8CH 413
+#define HCLK_I2S2_2CH 413
+#define HCLK_SPDIF_8CH 414
+#define HCLK_VOP 415
+#define HCLK_NANDC 416
+#define HCLK_SDMMC 417
+#define HCLK_SDIO 418
+#define HCLK_EMMC 419
+#define HCLK_SDMMC_EXT 420
+#define HCLK_RKVDEC_PRE 421
+#define HCLK_RKVDEC 422
+#define HCLK_RKVENC 423
+#define HCLK_VPU_PRE 424
+#define HCLK_VIO_PRE 425
+#define HCLK_VPU 426
+#define HCLK_VIO 427
+#define HCLK_BUS_PRE 428
+#define HCLK_PERI_PRE 429
+#define HCLK_H264 430
+#define HCLK_CIF 431
+#define HCLK_OTG_PMU 432
+#define HCLK_OTG 433
+#define HCLK_HOST0 434
+#define HCLK_HOST0_ARB 435
+#define HCLK_CRYPTO_MST 436
+#define HCLK_CRYPTO_SLV 437
+#define HCLK_PDM 438
+#define HCLK_IEP 439
+#define HCLK_RGA 440
+#define HCLK_HDCP 441
+
+#define CLK_NR_CLKS (HCLK_HDCP + 1)
+
+#define SCLK_MAC2IO 0
+#define SCLK_MAC2PHY 1
+
+#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+#define SRST_TOPDBG 12
+#define SRST_CORE_NIU 13
+#define SRST_STRC_A 14
+#define SRST_L2C 15
+
+#define SRST_A53_GIC 18
+#define SRST_DAP 19
+#define SRST_PMU_P 21
+#define SRST_EFUSE 22
+#define SRST_BUSSYS_H 23
+#define SRST_BUSSYS_P 24
+#define SRST_SPDIF 25
+#define SRST_INTMEM 26
+#define SRST_ROM 27
+#define SRST_GPIO0 28
+#define SRST_GPIO1 29
+#define SRST_GPIO2 30
+#define SRST_GPIO3 31
+
+#define SRST_I2S0 32
+#define SRST_I2S1 33
+#define SRST_I2S2 34
+#define SRST_I2S0_H 35
+#define SRST_I2S1_H 36
+#define SRST_I2S2_H 37
+#define SRST_UART0 38
+#define SRST_UART1 39
+#define SRST_UART2 40
+#define SRST_UART0_P 41
+#define SRST_UART1_P 42
+#define SRST_UART2_P 43
+#define SRST_I2C0 44
+#define SRST_I2C1 45
+#define SRST_I2C2 46
+#define SRST_I2C3 47
+
+#define SRST_I2C0_P 48
+#define SRST_I2C1_P 49
+#define SRST_I2C2_P 50
+#define SRST_I2C3_P 51
+#define SRST_EFUSE_SE_P 52
+#define SRST_EFUSE_NS_P 53
+#define SRST_PWM0 54
+#define SRST_PWM0_P 55
+#define SRST_DMA 56
+#define SRST_TSP_A 57
+#define SRST_TSP_H 58
+#define SRST_TSP 59
+#define SRST_TSP_HSADC 60
+#define SRST_DCF_A 61
+#define SRST_DCF_P 62
+
+#define SRST_SCR 64
+#define SRST_SPI 65
+#define SRST_TSADC 66
+#define SRST_TSADC_P 67
+#define SRST_CRYPTO 68
+#define SRST_SGRF 69
+#define SRST_GRF 70
+#define SRST_USB_GRF 71
+#define SRST_TIMER_6CH_P 72
+#define SRST_TIMER0 73
+#define SRST_TIMER1 74
+#define SRST_TIMER2 75
+#define SRST_TIMER3 76
+#define SRST_TIMER4 77
+#define SRST_TIMER5 78
+#define SRST_USB3GRF 79
+
+#define SRST_PHYNIU 80
+#define SRST_HDMIPHY 81
+#define SRST_VDAC 82
+#define SRST_ACODEC_p 83
+#define SRST_SARADC 85
+#define SRST_SARADC_P 86
+#define SRST_GRF_DDR 87
+#define SRST_DFIMON 88
+#define SRST_MSCH 89
+#define SRST_DDRMSCH 91
+#define SRST_DDRCTRL 92
+#define SRST_DDRCTRL_P 93
+#define SRST_DDRPHY 94
+#define SRST_DDRPHY_P 95
+
+#define SRST_GMAC_NIU_A 96
+#define SRST_GMAC_NIU_P 97
+#define SRST_GMAC2PHY_A 98
+#define SRST_GMAC2IO_A 99
+#define SRST_MACPHY 100
+#define SRST_OTP_PHY 101
+#define SRST_GPU_A 102
+#define SRST_GPU_NIU_A 103
+#define SRST_SDMMCEXT 104
+#define SRST_PERIPH_NIU_A 105
+#define SRST_PERIHP_NIU_H 106
+#define SRST_PERIHP_P 107
+#define SRST_PERIPHSYS_H 108
+#define SRST_MMC0 109
+#define SRST_SDIO 110
+#define SRST_EMMC 111
+
+#define SRST_USB2OTG_H 112
+#define SRST_USB2OTG 113
+#define SRST_USB2OTG_ADP 114
+#define SRST_USB2HOST_H 115
+#define SRST_USB2HOST_ARB 116
+#define SRST_USB2HOST_AUX 117
+#define SRST_USB2HOST_EHCIPHY 118
+#define SRST_USB2HOST_UTMI 119
+#define SRST_USB3OTG 120
+#define SRST_USBPOR 121
+#define SRST_USB2OTG_UTMI 122
+#define SRST_USB2HOST_PHY_UTMI 123
+#define SRST_USB3OTG_UTMI 124
+#define SRST_USB3PHY_U2 125
+#define SRST_USB3PHY_U3 126
+#define SRST_USB3PHY_PIPE 127
+
+#define SRST_VIO_A 128
+#define SRST_VIO_BUS_H 129
+#define SRST_VIO_H2P_H 130
+#define SRST_VIO_ARBI_H 131
+#define SRST_VOP_NIU_A 132
+#define SRST_VOP_A 133
+#define SRST_VOP_H 134
+#define SRST_VOP_D 135
+#define SRST_RGA 136
+#define SRST_RGA_NIU_A 137
+#define SRST_RGA_A 138
+#define SRST_RGA_H 139
+#define SRST_IEP_A 140
+#define SRST_IEP_H 141
+#define SRST_HDMI 142
+#define SRST_HDMI_P 143
+
+#define SRST_HDCP_A 144
+#define SRST_HDCP 145
+#define SRST_HDCP_H 146
+#define SRST_CIF_A 147
+#define SRST_CIF_H 148
+#define SRST_CIF_P 149
+#define SRST_OTP_P 150
+#define SRST_OTP_SBPI 151
+#define SRST_OTP_USER 152
+#define SRST_DDRCTRL_A 153
+#define SRST_DDRSTDY_P 154
+#define SRST_DDRSTDY 155
+#define SRST_PDM_H 156
+#define SRST_PDM 157
+#define SRST_USB3PHY_OTG_P 158
+#define SRST_USB3PHY_PIPE_P 159
+
+#define SRST_VCODEC_A 160
+#define SRST_VCODEC_NIU_A 161
+#define SRST_VCODEC_H 162
+#define SRST_VCODEC_NIU_H 163
+#define SRST_VDEC_A 164
+#define SRST_VDEC_NIU_A 165
+#define SRST_VDEC_H 166
+#define SRST_VDEC_NIU_H 167
+#define SRST_VDEC_CORE 168
+#define SRST_VDEC_CABAC 169
+#define SRST_DDRPHYDIV 175
+
+#define SRST_RKVENC_NIU_A 176
+#define SRST_RKVENC_NIU_H 177
+#define SRST_RKVENC_H265_A 178
+#define SRST_RKVENC_H265_P 179
+#define SRST_RKVENC_H265_CORE 180
+#define SRST_RKVENC_H265_DSP 181
+#define SRST_RKVENC_H264_A 182
+#define SRST_RKVENC_H264_H 183
+#define SRST_RKVENC_INTMEM 184
+
+#endif
--
1.9.1
^ permalink raw reply related
* [PATCH v4 2/4] dt-bindings: add bindings for rk3328 clock controller
From: Elaine Zhang @ 2016-12-27 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482820373-10186-1-git-send-email-zhangqing@rock-chips.com>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Changes in v4:
dropping the "rockchip,cru" and "syscon" properties for bindings of rk3328
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
.../bindings/clock/rockchip,rk3328-cru.txt | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
new file mode 100644
index 000000000000..e71c675ba5da
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
@@ -0,0 +1,57 @@
+* Rockchip RK3328 Clock and Reset Unit
+
+The RK3328 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3328-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+ - "phy_50m_out" - output clock of the pll in the mac phy
+
+Example: Clock controller node:
+
+ cru: clock-controller at ff440000 {
+ compatible = "rockchip,rk3328-cru";
+ reg = <0x0 0xff440000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial at ff120000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff120000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART0>;
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v4 3/4] clk: rockchip: add new pll-type for rk3328
From: Elaine Zhang @ 2016-12-27 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482820373-10186-1-git-send-email-zhangqing@rock-chips.com>
The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask, the rk3328 soc
pll mode only one bit(rk3036 soc have two bits)
so these should be independent and separate from
the series of rk3328s.
Changes in v4:
adjust the pacth 3 and 4 order.
move pll_rk3328 to patch 3.
Changes in v3:
fix up the pll type pll_rk3328 description and use
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-pll.c | 16 +++++++++++++---
drivers/clk/rockchip/clk.h | 1 +
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 6ed605776abd..eec51893a7e6 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -29,6 +29,7 @@
#define PLL_MODE_SLOW 0x0
#define PLL_MODE_NORM 0x1
#define PLL_MODE_DEEP 0x2
+#define PLL_RK3328_MODE_MASK 0x1
struct rockchip_clk_pll {
struct clk_hw hw;
@@ -848,7 +849,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
struct clk *pll_clk, *mux_clk;
char pll_name[20];
- if (num_parents != 2) {
+ if ((pll_type != pll_rk3328 && num_parents != 2) ||
+ (pll_type == pll_rk3328 && num_parents != 1)) {
pr_err("%s: needs two parent clocks\n", __func__);
return ERR_PTR(-EINVAL);
}
@@ -865,13 +867,17 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
pll_mux = &pll->pll_mux;
pll_mux->reg = ctx->reg_base + mode_offset;
pll_mux->shift = mode_shift;
- pll_mux->mask = PLL_MODE_MASK;
+ if (pll_type == pll_rk3328)
+ pll_mux->mask = PLL_RK3328_MODE_MASK;
+ else
+ pll_mux->mask = PLL_MODE_MASK;
pll_mux->flags = 0;
pll_mux->lock = &ctx->lock;
pll_mux->hw.init = &init;
if (pll_type == pll_rk3036 ||
pll_type == pll_rk3066 ||
+ pll_type == pll_rk3328 ||
pll_type == pll_rk3399)
pll_mux->flags |= CLK_MUX_HIWORD_MASK;
@@ -884,7 +890,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
init.flags = CLK_SET_RATE_PARENT;
init.ops = pll->pll_mux_ops;
init.parent_names = pll_parents;
- init.num_parents = ARRAY_SIZE(pll_parents);
+ if (pll_type == pll_rk3328)
+ init.num_parents = 2;
+ else
+ init.num_parents = ARRAY_SIZE(pll_parents);
mux_clk = clk_register(NULL, &pll_mux->hw);
if (IS_ERR(mux_clk))
@@ -918,6 +927,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
switch (pll_type) {
case pll_rk3036:
+ case pll_rk3328:
if (!pll->rate_table || IS_ERR(ctx->grf))
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
else
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index d67eecc4ade9..06acb7e0911f 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -130,6 +130,7 @@
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
+ pll_rk3328,
pll_rk3399,
};
--
1.9.1
^ permalink raw reply related
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