* [PATCH] ARM: imx_v6_v7_defconfig: Select wireless extensions option
From: Fabio Estevam @ 2016-12-31 17:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
Select CONFIG_CFG80211_WEXT so that wireless can work out of the box
when using userspace tools such as 'iwconfig'.
Generated by manually selecting CONFIG_CFG80211_WEXT and
then running:
make savedefconfig
cp defconfig arch/arm/configs/imx_v6_v7_defconfig
, which results in additional cleanup.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/configs/imx_v6_v7_defconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index cbe7faf..eaba3b1 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -79,6 +79,7 @@ CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_LL=y
CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
@@ -174,7 +175,6 @@ CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
CONFIG_SERIO_SERPORT=m
# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_FSL_LPUART=y
@@ -194,11 +194,11 @@ CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MC9S08DZ60=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_STMPE=y
-CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_IMX=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_IIO_HWMON=y
CONFIG_THERMAL=y
--
2.7.4
^ permalink raw reply related
* [PATCH v5 3/4] clk: rockchip: add new pll-type for rk3328
From: Heiko Stuebner @ 2016-12-31 12:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482979511-6847-4-git-send-email-zhangqing@rock-chips.com>
Am Donnerstag, 29. Dezember 2016, 10:45:10 CET schrieb Elaine Zhang:
> The rk3328's pll and clock are similar with rk3036's,
> it different with pll_mode_mask, the rk3328 soc
> pll mode only one bit(rk3036 soc have two bits)
> so these should be independent and separate from
> the series of rk3328s.
>
> Changes in v4:
> adjust the pacth 3 and 4 order.
> move pll_rk3328 to patch 3.
> Changes in v3:
> fix up the pll type pll_rk3328 description and use
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
applied to my clk-branch for 4.11
The clock controller itself also looks good now, I'll just give Rob or someone
else a bit of time for eventual comments after new years :-)
Heiko
^ permalink raw reply
* [PATCH] drivers: remoteproc: constify rproc_ops structures
From: Bhumika Goyal @ 2016-12-31 10:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230120655.GB9118@builder>
On Fri, Dec 30, 2016 at 5:36 PM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> On Sat 17 Dec 03:29 PST 2016, Bhumika Goyal wrote:
>
>> Declare rproc_ops structures as const as they are only passed as an
>> argument to the function rproc_alloc. This argument is of type const, so
>> rproc_ops structures having this property can be declared const too.
>> Done using Coccinelle:
>>
>> @r1 disable optional_qualifier @
>> identifier i;
>> position p;
>> @@
>> static struct rproc_ops i at p = {...};
>>
>> @ok1@
>> identifier r1.i;
>> position p;
>> @@
>> rproc_alloc(...,&i at p,...)
>>
>> @bad@
>> position p!={r1.p,ok1.p};
>> identifier r1.i;
>> @@
>> i at p
>>
>> @depends on !bad disable optional_qualifier@
>> identifier r1.i;
>> @@
>> +const
>> struct rproc_ops i;
>>
>> File sizes before:
>> text data bss dec hex filename
>> 1258 416 0 1674 68a remoteproc/omap_remoteproc.o
>> 2402 240 0 2642 a52 remoteproc/st_remoteproc.o
>> 2064 272 0 2336 920 remoteproc/st_slim_rproc.o
>> 2160 240 0 2400 960 remoteproc/wkup_m3_rproc.o
>>
>> File sizes after:
>> text data bss dec hex filename
>> 1297 368 0 1665 681 remoteproc/omap_remoteproc.o
>> 2434 192 0 2626 a42 remoteproc/st_remoteproc.o
>> 2112 240 0 2352 930 remoteproc/st_slim_rproc.o
>> 2200 192 0 2392 958 remoteproc/wkup_m3_rproc.o
>>
>> Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
>
> Thanks Bhumika, this looks good.
>
> But as Suman already asked. Is there any reason why da8xx_remoteproc.c
> did not get updated? It looks like the same change would apply there.
>
>
The reason I did not sent a patch for that driver is because the .o
file is not obtained. This is output I get when I try to compile the
da8xx_remoteproc.o file.
drivers/remoteproc/da8xx_remoteproc.c:22:72: fatal error:
mach/clock.h: No such file or directory
#include <mach/clock.h> /* for davinci_clk_reset_assert/deassert() */
^
compilation terminated.
make[1]: *** [drivers/remoteproc/da8xx_remoteproc.o] Error 1
make: *** [drivers/remoteproc/da8xx_remoteproc.o] Error 2
I also tried running the commands make.cross ARCH=arm allyesconfig;
make.cross ARCH=arm drivers/remoteproc/da8xx_remoteproc.o but still
the error remains the same.
Could you please suggest me what to do in this case?
Thanks,
Bhumika
> Unless I'm missing something, please update the patch and I'll be happy
> to apply it.
>
> Regards,
> Bjorn
^ permalink raw reply
* How should we handle variable address space sizes (Re: [RFC 3/4] x86/mm: define TASK_SIZE as current->mm->task_size)
From: Andy Lutomirski @ 2016-12-31 2:11 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Dec 30, 2016 at 7:56 AM, Dmitry Safonov <dsafonov@virtuozzo.com> wrote:
> Keep task's virtual address space size as mm_struct field which
> exists for a long time - it's initialized in setup_new_exec()
> depending on the new task's personality.
> This way TASK_SIZE will always be the same as current->mm->task_size.
> Previously, there could be an issue about different values of
> TASK_SIZE and current->mm->task_size: e.g, a 32-bit process can unset
> ADDR_LIMIT_3GB personality (with personality syscall) and
> so TASK_SIZE will be 4Gb, which is larger than mm->task_size = 3Gb.
> As TASK_SIZE *and* current->mm->task_size are used both in code
> frequently, this difference creates a subtle situations, for example:
> one can mmap addresses > 3Gb, but they will be hidden in
> /proc/pid/pagemap as it checks mm->task_size.
> I've moved initialization of mm->task_size earlier in setup_new_exec()
> as arch_pick_mmap_layout() initializes mmap_legacy_base with
> TASK_UNMAPPED_BASE, which depends on TASK_SIZE.
I don't like this patch so much because I think that we should figure
out how this will all work in the long run first. I've added some
more people to the thread because other arches have similar issues and
because x86 is about to get considerably more complicated (choices
include 3GB, 4GB, 47-bit, and 56-bit (the latter IIRC)).
Here are a few of my thoughts on the matter. This isn't all that well
thought out:
The address space limit, especially if CRIU is in play, isn't really a
hard limit. For example, you could allocate high memory then lower
the limit. Similarly, I see no reason that an x32 program should be
forbidden from mapping some high addresses or, similarly, that an i386
program can't (if it really wanted to) do a 64-bit mmap() and get a
high address.
On that note, can we just *delete* the task_size check from pagemap?
It's been there since the very beginning:
commit 85863e475e59afb027b0113290e3796ee6020b7d
Author: Matt Mackall <mpm@selenic.com>
Date: Mon Feb 4 22:29:04 2008 -0800
maps4: add /proc/pid/pagemap interface
and there's no explanation for why it's needed.
So maybe we should have a *number* (not a bit) that indicates the
maximum address that mmap() will return unless an override is in use.
Since common practice seems to be to stick this in the personality
field, we may need some fancy encoding. Executing a setuid binary
needs to reset to the default, and personality handles that.
We should also probably come up with a reasonable set of getters and
setters for CRIU and otherwise. I can think of the following
questions that might be asked:
- What is the highest currently mapped VA? (/proc can already answer
this. If needed, a prctl could be added, too. Using /proc is a bit
tricky due to out-of-range "gate areas", e.g. the x86 vsyscall page.)
- What is the highest address that mmap() will return without being
forced? On x86 and sparc, this could plausbly be extra complicated
because there are multiple "mmap()" syscalls (32-bit vs 64-bit), so an
i386 process could theoretically have a limit of 2^47-1, for example.
I doubt this matters much. I'm also not sure whether this should be
per-task or per-mm. I can see legitimate use cases to set this to
unusual numbers. For example, some x86 program could want 2^51-1
because it wants that many high bits free, even though this doesn't
correspond to any particular hardware paging mode. This probably
wants a getter and a setter.
- What is the highest address that the hardware is capable of? (By
this, I mean with the kernel's adjustments applied. x86_64 is
currently capable of 2^47-1, but we artificially cap it to 2^47-4097
due to Intel having screwed up SYSRET.) This is just TASK_SIZE_MAX.
I'm not sure we need a getter or a setter, since it doesn't seem all
that useful to know.
We still need to see if there should be some way for an ELF binary to
be tagged with its maximum supported virtual address. If we do this,
I would suggest an ELF note as a straw-man initial proposal. ELF
notes are nice because I think they can be generated cleanly from C or
asm without modifying binutils.
I wouldn't mind seeing TASK_SIZE go away completely in the long run,
since it's not clearly defined what it does. Also, it's worth noting
that, in the absence of userspace making assumptions, no limit is
needed at all. A 32-bit or x32 program should *automatically* get a
limited address simply by virtue of making an mmap() syscall with the
32-bit or x32 ABI.
Thoughts?
P.S. If we add an ELF note saying "supports 57 bits", I think we
should also add an ELF note saying "doesn't use vsyscalls", but that's
a bit off topic.
P.P.S. We can efficiently turn vsyscalls off per process. I even have
code for it. It's a bit tricky and abuses some paging bits, but it
works.
^ permalink raw reply
* [RFC 1/4] mm: remove unused TASK_SIZE_OF()
From: Andy Lutomirski @ 2016-12-31 1:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230155634.8692-2-dsafonov@virtuozzo.com>
On Fri, Dec 30, 2016 at 7:56 AM, Dmitry Safonov <dsafonov@virtuozzo.com> wrote:
> All users of TASK_SIZE_OF(tsk) have migrated to mm->task_size or
> TASK_SIZE_MAX since:
> commit d696ca016d57 ("x86/fsgsbase/64: Use TASK_SIZE_MAX for
> FSBASE/GSBASE upper limits"),
> commit a06db751c321 ("pagemap: check permissions and capabilities at
> open time"),
I like this.
Reviewed-by: Andy Lutomirski <luto@kernel.org> # for x86
^ permalink raw reply
* [v2, 1/4] ARM: davinci: da8xx-dt: Add ti-aemif lookup for clock matching
From: David Lechner @ 2016-12-31 0:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160810110032.29295-2-kbeldan@baylibre.com>
On 08/10/2016 06:00 AM, Karl Beldan wrote:
> Many davinci boards (da830 and da850 families) don't have their clocks
> in DT yet and won't be successful in getting an unnamed aemif clock
> without explicitly registering them via clk_lookups, failing the
> ti-aemif memory driver probe.
>
> The current aemif lookup entry resolving to the same clock:
> 'CLK(NULL, "aemif", &aemif_clk)'
> remains, as it is currently used (davinci_nand is getting a named clock
> "aemif").
>
> This change will allow to switch from the mach-davinci aemif code to
> the ti-aemif memory driver.
>
> Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
> ---
FYI, I can't boot LEGO MINDSTORMS EV3 (AM1908) with a v4.9 mainline
kernel. I did a git bisect and traced it down to this patch. I'm
guessing that simply reverting it will break other things.
The problem is that &aemif_clk is a node in a linked list and points to
itself, which creates an infinite loop when looking up the usb clocks
that are later in the list.
I thought there was a patch to fix this properly from one of the Bay
Libre guys to fix this already, but I can't seem to find it at the
moment. When it is found, it would be good to have it applied to the 4.9
stable and 4.10 mainline trees.
> arch/arm/mach-davinci/da850.c | 1 +
> arch/arm/mach-davinci/da8xx-dt.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
> index 2398862..3477d30 100644
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -485,6 +485,7 @@ static struct clk_lookup da850_clks[] = {
> CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
> CLK("da830-mmc.0", NULL, &mmcsd0_clk),
> CLK("da830-mmc.1", NULL, &mmcsd1_clk),
> + CLK("ti-aemif", NULL, &aemif_clk),
> CLK(NULL, "aemif", &aemif_clk),
> CLK(NULL, "usb11", &usb11_clk),
> CLK(NULL, "usb20", &usb20_clk),
> diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
> index ca99711..c9f7e92 100644
> --- a/arch/arm/mach-davinci/da8xx-dt.c
> +++ b/arch/arm/mach-davinci/da8xx-dt.c
> @@ -37,6 +37,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
> OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1",
> NULL),
> OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
> + OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL),
> {}
> };
>
>
^ permalink raw reply
* [PATCH v6 6/8] IIO: add STM32 timer trigger driver
From: Jonathan Cameron @ 2016-12-30 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481292919-26587-7-git-send-email-benjamin.gaignard@st.com>
On 09/12/16 14:15, Benjamin Gaignard wrote:
> Timers IPs can be used to generate triggers for other IPs like
> DAC, ADC or other timers.
> Each trigger may result of timer internals signals like counter enable,
> reset or edge, this configuration could be done through "master_mode"
> device attribute.
>
> A timer device could be triggered by other timers, we use the trigger
> name and is_stm32_iio_timer_trigger() function to distinguish them
> and configure IP input switch.
>
> Timer may also decide on which event (edge, level) they could
> be activated by a trigger, this configuration is done by writing in
> "slave_mode" device attribute.
>
> Since triggers could also be used by DAC or ADC their names are defined
> in include/ nux/iio/timer/stm32-timer-trigger.h so those IPs will be able
> to configure themselves in valid_trigger function
>
> Trigger have a "sampling_frequency" attribute which allow to configure
> timer sampling frequency without using PWM interface
>
> version 5:
> - simplify tables of triggers
> - only create an IIO device when needed
>
> version 4:
> - get triggers configuration from "reg" in DT
> - add tables of triggers
> - sampling frequency is enable/disable when writing in trigger
> sampling_frequency attribute
> - no more use of interruptions
>
> version 3:
> - change compatible to "st,stm32-timer-trigger"
> - fix attributes access right
> - use string instead of int for master_mode and slave_mode
> - document device attributes in sysfs-bus-iio-timer-stm32
>
> version 2:
> - keep only one compatible
> - use st,input-triggers-names and st,output-triggers-names
> to know which triggers are accepted and/or create by the device
Firstly, sorry it has taken me so long to get back to this.
I'm still not keen on this use of iio_device elements just to act as
glue between triggers. I think we need to work out a more light weight
way to do this. As you are only using them for validation and to provide
somewhere to hang the control attibutes off, there is nothing stopping us
moving that over to the iio_trigger instead which would avoid the messy
duality going on here.
I might still be missing something though!
You would only I think need 3 attributes
parrent_trigger
and something like your master_mode and slave_mode attributes.
The parrent_trigger would need some validation etc, but if we keep it
within this driver initially that won't be hard to do. Checking the device
parent matches will do most of it.
Jonathan
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 55 +++
> drivers/iio/Kconfig | 2 +-
> drivers/iio/Makefile | 1 +
> drivers/iio/timer/Kconfig | 13 +
> drivers/iio/timer/Makefile | 1 +
> drivers/iio/timer/stm32-timer-trigger.c | 466 +++++++++++++++++++++
> drivers/iio/trigger/Kconfig | 1 -
> include/linux/iio/timer/stm32-timer-trigger.h | 62 +++
> 8 files changed, 599 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
> create mode 100644 drivers/iio/timer/Kconfig
> create mode 100644 drivers/iio/timer/Makefile
> create mode 100644 drivers/iio/timer/stm32-timer-trigger.c
> create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
> new file mode 100644
> index 0000000..26583dd
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
> @@ -0,0 +1,55 @@
> +What: /sys/bus/iio/devices/iio:deviceX/master_mode_available
> +KernelVersion: 4.10
> +Contact: benjamin.gaignard at st.com
> +Description:
> + Reading returns the list possible master modes which are:
> + - "reset" : The UG bit from the TIMx_EGR register is used as trigger output (TRGO).
> + - "enable" : The Counter Enable signal CNT_EN is used as trigger output.
> + - "update" : The update event is selected as trigger output.
> + For instance a master timer can then be used as a prescaler for a slave timer.
> + - "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set.
> + - "OC1REF" : OC1REF signal is used as trigger output.
> + - "OC2REF" : OC2REF signal is used as trigger output.
> + - "OC3REF" : OC3REF signal is used as trigger output.
> + - "OC4REF" : OC4REF signal is used as trigger output.
> +
> +What: /sys/bus/iio/devices/iio:deviceX/master_mode
> +KernelVersion: 4.10
> +Contact: benjamin.gaignard at st.com
> +Description:
> + Reading returns the current master modes.
> + Writing set the master mode
> +
> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode_available
> +KernelVersion: 4.10
> +Contact: benjamin.gaignard at st.com
> +Description:
> + Reading returns the list possible slave modes which are:
> + - "disabled" : The prescaler is clocked directly by the internal clock.
> + - "encoder_1" : Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
> + - "encoder_2" : Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
> + - "encoder_3" : Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
> + on the level of the other input.
> + - "reset" : Rising edge of the selected trigger input reinitializes the counter
> + and generates an update of the registers.
> + - "gated" : The counter clock is enabled when the trigger input is high.
> + The counter stops (but is not reset) as soon as the trigger becomes low.
> + Both start and stop of the counter are controlled.
> + - "trigger" : The counter starts at a rising edge of the trigger TRGI (but it is not
> + reset). Only the start of the counter is controlled.
> + - "external_clock": Rising edges of the selected trigger (TRGI) clock the counter.
> +
> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode
> +KernelVersion: 4.10
> +Contact: benjamin.gaignard at st.com
> +Description:
> + Reading returns the current slave mode.
> + Writing set the slave mode
> +
> +What: /sys/bus/iio/devices/triggerX/sampling_frequency
> +KernelVersion: 4.10
> +Contact: benjamin.gaignard at st.com
> +Description:
> + Reading returns the current sampling frequency.
> + Writing an value different of 0 set and start sampling.
> + Writing 0 stop sampling.
> diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
> index 6743b18..2de2a80 100644
> --- a/drivers/iio/Kconfig
> +++ b/drivers/iio/Kconfig
> @@ -90,5 +90,5 @@ source "drivers/iio/potentiometer/Kconfig"
> source "drivers/iio/pressure/Kconfig"
> source "drivers/iio/proximity/Kconfig"
> source "drivers/iio/temperature/Kconfig"
> -
> +source "drivers/iio/timer/Kconfig"
> endif # IIO
> diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
> index 87e4c43..b797c08 100644
> --- a/drivers/iio/Makefile
> +++ b/drivers/iio/Makefile
> @@ -32,4 +32,5 @@ obj-y += potentiometer/
> obj-y += pressure/
> obj-y += proximity/
> obj-y += temperature/
> +obj-y += timer/
> obj-y += trigger/
> diff --git a/drivers/iio/timer/Kconfig b/drivers/iio/timer/Kconfig
> new file mode 100644
> index 0000000..e3c21f2
> --- /dev/null
> +++ b/drivers/iio/timer/Kconfig
> @@ -0,0 +1,13 @@
> +#
> +# Timers drivers
> +
> +menu "Timers"
> +
> +config IIO_STM32_TIMER_TRIGGER
> + tristate "STM32 Timer Trigger"
> + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST
> + select IIO_TRIGGERED_EVENT
> + help
> + Select this option to enable STM32 Timer Trigger
> +
> +endmenu
> diff --git a/drivers/iio/timer/Makefile b/drivers/iio/timer/Makefile
> new file mode 100644
> index 0000000..4ad95ec9
> --- /dev/null
> +++ b/drivers/iio/timer/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_IIO_STM32_TIMER_TRIGGER) += stm32-timer-trigger.o
> diff --git a/drivers/iio/timer/stm32-timer-trigger.c b/drivers/iio/timer/stm32-timer-trigger.c
> new file mode 100644
> index 0000000..8d16e8f
> --- /dev/null
> +++ b/drivers/iio/timer/stm32-timer-trigger.c
> @@ -0,0 +1,466 @@
> +/*
> + * Copyright (C) STMicroelectronics 2016
> + *
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/iio/iio.h>
> +#include <linux/iio/sysfs.h>
> +#include <linux/iio/timer/stm32-timer-trigger.h>
> +#include <linux/iio/trigger.h>
> +#include <linux/iio/triggered_event.h>
> +#include <linux/interrupt.h>
> +#include <linux/mfd/stm32-timers.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#define MAX_TRIGGERS 6
> +#define MAX_VALIDS 5
> +
> +/* List the triggers created by each timer */
> +static const void *triggers_table[][MAX_TRIGGERS] = {
> + { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
> + { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
> + { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
> + { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
> + { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
> + { TIM6_TRGO,},
> + { TIM7_TRGO,},
> + { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
> + { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
> + { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
> +};
> +
> +/* List the triggers accepted by each timer */
> +static const void *valids_table[][MAX_VALIDS] = {
> + { TIM5_TRGO, TIM2_TRGO, TIM4_TRGO, TIM3_TRGO,},
> + { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
> + { TIM1_TRGO, TIM8_TRGO, TIM5_TRGO, TIM4_TRGO,},
> + { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
> + { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
> + { }, /* timer 6 */
> + { }, /* timer 7 */
> + { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
> + { TIM2_TRGO, TIM3_TRGO,},
> + { TIM4_TRGO, TIM5_TRGO,},
> +};
> +
> +struct stm32_timer_trigger {
> + struct device *dev;
> + struct regmap *regmap;
> + struct clk *clk;
> + u32 max_arr;
> + const void *triggers;
> + const void *valids;
> +};
> +
> +static int stm32_timer_start(struct stm32_timer_trigger *priv,
> + unsigned int frequency)
> +{
> + unsigned long long prd, div;
> + int prescaler = 0;
> + u32 ccer, cr1;
> +
> + /* Period and prescaler values depends of clock rate */
> + div = (unsigned long long)clk_get_rate(priv->clk);
> +
> + do_div(div, frequency);
> +
> + prd = div;
> +
> + /*
> + * Increase prescaler value until we get a result that fit
> + * with auto reload register maximum value.
> + */
> + while (div > priv->max_arr) {
> + prescaler++;
> + div = prd;
> + do_div(div, (prescaler + 1));
> + }
> + prd = div;
> +
> + if (prescaler > MAX_TIM_PSC) {
> + dev_err(priv->dev, "prescaler exceeds the maximum value\n");
> + return -EINVAL;
> + }
> +
> + /* Check if nobody else use the timer */
> + regmap_read(priv->regmap, TIM_CCER, &ccer);
> + if (ccer & TIM_CCER_CCXE)
> + return -EBUSY;
> +
> + regmap_read(priv->regmap, TIM_CR1, &cr1);
> + if (!(cr1 & TIM_CR1_CEN))
> + clk_enable(priv->clk);
> +
> + regmap_write(priv->regmap, TIM_PSC, prescaler);
> + regmap_write(priv->regmap, TIM_ARR, prd - 1);
> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
> +
> + /* Force master mode to update mode */
> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
> +
> + /* Make sure that registers are updated */
> + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
> +
> + /* Enable controller */
> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
> +
> + return 0;
> +}
> +
> +static void stm32_timer_stop(struct stm32_timer_trigger *priv)
> +{
> + u32 ccer, cr1;
> +
> + regmap_read(priv->regmap, TIM_CCER, &ccer);
> + if (ccer & TIM_CCER_CCXE)
> + return;
> +
> + regmap_read(priv->regmap, TIM_CR1, &cr1);
> + if (cr1 & TIM_CR1_CEN)
> + clk_disable(priv->clk);
> +
> + /* Stop timer */
> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
> + regmap_write(priv->regmap, TIM_PSC, 0);
> + regmap_write(priv->regmap, TIM_ARR, 0);
> +}
> +
> +static ssize_t stm32_tt_store_frequency(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t len)
> +{
> + struct iio_trigger *trig = to_iio_trigger(dev);
> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
> + unsigned int freq;
> + int ret;
> +
> + ret = kstrtouint(buf, 10, &freq);
> + if (ret)
> + return ret;
> +
> + if (freq == 0) {
> + stm32_timer_stop(priv);
> + } else {
> + ret = stm32_timer_start(priv, freq);
> + if (ret)
> + return ret;
> + }
> +
> + return len;
> +}
> +
> +static ssize_t stm32_tt_read_frequency(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct iio_trigger *trig = to_iio_trigger(dev);
> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
> + u32 psc, arr, cr1;
> + unsigned long long freq = 0;
> +
> + regmap_read(priv->regmap, TIM_CR1, &cr1);
> + regmap_read(priv->regmap, TIM_PSC, &psc);
> + regmap_read(priv->regmap, TIM_ARR, &arr);
> +
> + if (psc && arr && (cr1 & TIM_CR1_CEN)) {
> + freq = (unsigned long long)clk_get_rate(priv->clk);
> + do_div(freq, psc);
> + do_div(freq, arr);
> + }
> +
> + return sprintf(buf, "%d\n", (unsigned int)freq);
> +}
> +
> +static IIO_DEV_ATTR_SAMP_FREQ(0660,
> + stm32_tt_read_frequency,
> + stm32_tt_store_frequency);
> +
> +static struct attribute *stm32_trigger_attrs[] = {
> + &iio_dev_attr_sampling_frequency.dev_attr.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group stm32_trigger_attr_group = {
> + .attrs = stm32_trigger_attrs,
> +};
> +
> +static const struct attribute_group *stm32_trigger_attr_groups[] = {
> + &stm32_trigger_attr_group,
> + NULL,
> +};
> +
> +static char *master_mode_table[] = {
> + "reset",
> + "enable",
> + "update",
> + "compare_pulse",
> + "OC1REF",
> + "OC2REF",
> + "OC3REF",
> + "OC4REF"
> +};
> +
> +static ssize_t stm32_tt_show_master_mode(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
> + u32 cr2;
> +
> + regmap_read(priv->regmap, TIM_CR2, &cr2);
> + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
> +
> + return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
> +}
> +
> +static ssize_t stm32_tt_store_master_mode(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t len)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
> + if (!strncmp(master_mode_table[i], buf,
> + strlen(master_mode_table[i]))) {
> + regmap_update_bits(priv->regmap, TIM_CR2,
> + TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
> + return len;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +static IIO_CONST_ATTR(master_mode_available,
> + "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
> +
> +static IIO_DEVICE_ATTR(master_mode, 0660,
> + stm32_tt_show_master_mode,
> + stm32_tt_store_master_mode,
> + 0);
> +
> +static char *slave_mode_table[] = {
> + "disabled",
> + "encoder_1",
> + "encoder_2",
> + "encoder_3",
> + "reset",
> + "gated",
> + "trigger",
> + "external_clock",
> +};
> +
> +static ssize_t stm32_tt_show_slave_mode(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
> + u32 smcr;
> +
> + regmap_read(priv->regmap, TIM_SMCR, &smcr);
> + smcr &= TIM_SMCR_SMS;
> +
> + return snprintf(buf, PAGE_SIZE, "%s\n", slave_mode_table[smcr]);
> +}
> +
> +static ssize_t stm32_tt_store_slave_mode(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t len)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(slave_mode_table); i++) {
> + if (!strncmp(slave_mode_table[i], buf,
> + strlen(slave_mode_table[i]))) {
> + regmap_update_bits(priv->regmap,
> + TIM_SMCR, TIM_SMCR_SMS, i);
> + return len;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +static IIO_CONST_ATTR(slave_mode_available,
> +"disabled encoder_1 encoder_2 encoder_3 reset gated trigger external_clock");
> +
> +static IIO_DEVICE_ATTR(slave_mode, 0660,
> + stm32_tt_show_slave_mode,
> + stm32_tt_store_slave_mode,
> + 0);
> +
> +static struct attribute *stm32_timer_attrs[] = {
> + &iio_dev_attr_master_mode.dev_attr.attr,
> + &iio_const_attr_master_mode_available.dev_attr.attr,
> + &iio_dev_attr_slave_mode.dev_attr.attr,
> + &iio_const_attr_slave_mode_available.dev_attr.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group stm32_timer_attr_group = {
> + .attrs = stm32_timer_attrs,
> +};
> +
> +static const struct iio_trigger_ops timer_trigger_ops = {
> + .owner = THIS_MODULE,
> +};
> +
> +static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
> +{
> + int ret;
> + const char * const *cur = priv->triggers;
> +
> + while (cur && *cur) {
> + struct iio_trigger *trig;
> +
> + trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
> + if (!trig)
> + return -ENOMEM;
> +
> + trig->dev.parent = priv->dev->parent;
> + trig->ops = &timer_trigger_ops;
> + trig->dev.groups = stm32_trigger_attr_groups;
> + iio_trigger_set_drvdata(trig, priv);
> +
> + ret = devm_iio_trigger_register(priv->dev, trig);
> + if (ret)
> + return ret;
> + cur++;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * is_stm32_timer_trigger
> + * @trig: trigger to be checked
> + *
> + * return true if the trigger is a valid stm32 iio timer trigger
> + * either return false
> + */
> +bool is_stm32_timer_trigger(struct iio_trigger *trig)
> +{
> + return (trig->ops == &timer_trigger_ops);
> +}
> +EXPORT_SYMBOL(is_stm32_timer_trigger);
> +
> +static int stm32_validate_trigger(struct iio_dev *indio_dev,
> + struct iio_trigger *trig)
> +{
> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
> + const char * const *cur = priv->valids;
> + unsigned int i = 0;
> +
> + if (!is_stm32_timer_trigger(trig))
> + return -EINVAL;
> +
> + while (cur && *cur) {
> + if (!strncmp(trig->name, *cur, strlen(trig->name))) {
> + regmap_update_bits(priv->regmap,
> + TIM_SMCR, TIM_SMCR_TS,
> + i << TIM_SMCR_TS_SHIFT);
> + return 0;
> + }
> + cur++;
> + i++;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static const struct iio_info stm32_trigger_info = {
> + .driver_module = THIS_MODULE,
> + .validate_trigger = stm32_validate_trigger,
> + .attrs = &stm32_timer_attr_group,
> +};
> +
> +static struct stm32_timer_trigger *stm32_setup_iio_device(struct device *dev)
> +{
> + struct iio_dev *indio_dev;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(dev,
> + sizeof(struct stm32_timer_trigger));
> + if (!indio_dev)
> + return NULL;
> +
> + indio_dev->name = dev_name(dev);
> + indio_dev->dev.parent = dev;
> + indio_dev->info = &stm32_trigger_info;
> + indio_dev->modes = INDIO_EVENT_TRIGGERED;
> + indio_dev->num_channels = 0;
> + indio_dev->dev.of_node = dev->of_node;
> +
> + ret = devm_iio_device_register(dev, indio_dev);
> + if (ret)
> + return NULL;
> +
> + return iio_priv(indio_dev);
> +}
> +
> +static int stm32_timer_trigger_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct stm32_timer_trigger *priv;
> + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
> + unsigned int index;
> + int ret;
> +
> + if (of_property_read_u32(dev->of_node, "reg", &index))
> + return -EINVAL;
> +
> + if (index >= ARRAY_SIZE(triggers_table))
> + return -EINVAL;
> +
> + /* Create an IIO device only if we have triggers to be validated */
> + if (*valids_table[index])
> + priv = stm32_setup_iio_device(dev);
I still don't like this. Really feels like we shouldn't be creating an
iio device with all the bagage that carries just to allow us to do the
trigger trees. We ought to have a much more light weight solution for this
functionality - we aren't typically even using the interrupt tree stuff
that the triggers for devices are all really about.
A simpler approach of allowing each trigger the option of a parent seems like
it would be cleaner. Could be done entirely within this driver in the first
instance. Basically it would just look like your master and slave attributes
but have those under triggerX not iio:deviceX.
We can work out how to make it more generic later - including perhaps the
option to trigger from triggers outside this driver, using some parallel
infrastructure to the device triggering.
> + else
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->dev = dev;
> + priv->regmap = ddata->regmap;
> + priv->clk = ddata->clk;
> + priv->max_arr = ddata->max_arr;
> + priv->triggers = triggers_table[index];
> + priv->valids = valids_table[index];
> +
> + ret = stm32_setup_iio_triggers(priv);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32_trig_of_match[] = {
> + { .compatible = "st,stm32-timer-trigger", },
> + { /* end node */ },
> +};
> +MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
> +
> +static struct platform_driver stm32_timer_trigger_driver = {
> + .probe = stm32_timer_trigger_probe,
> + .driver = {
> + .name = "stm32-timer-trigger",
> + .of_match_table = stm32_trig_of_match,
> + },
> +};
> +module_platform_driver(stm32_timer_trigger_driver);
> +
> +MODULE_ALIAS("platform: stm32-timer-trigger");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig
> index 809b2e7..f2af4fe 100644
> --- a/drivers/iio/trigger/Kconfig
> +++ b/drivers/iio/trigger/Kconfig
> @@ -46,5 +46,4 @@ config IIO_SYSFS_TRIGGER
>
> To compile this driver as a module, choose M here: the
> module will be called iio-trig-sysfs.
> -
Clean this up.
> endmenu
> diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h
> new file mode 100644
> index 0000000..55535ae
> --- /dev/null
> +++ b/include/linux/iio/timer/stm32-timer-trigger.h
> @@ -0,0 +1,62 @@
> +/*
> + * Copyright (C) STMicroelectronics 2016
> + *
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef _STM32_TIMER_TRIGGER_H_
> +#define _STM32_TIMER_TRIGGER_H_
> +
> +#define TIM1_TRGO "tim1_trgo"
> +#define TIM1_CH1 "tim1_ch1"
> +#define TIM1_CH2 "tim1_ch2"
> +#define TIM1_CH3 "tim1_ch3"
> +#define TIM1_CH4 "tim1_ch4"
> +
> +#define TIM2_TRGO "tim2_trgo"
> +#define TIM2_CH1 "tim2_ch1"
> +#define TIM2_CH2 "tim2_ch2"
> +#define TIM2_CH3 "tim2_ch3"
> +#define TIM2_CH4 "tim2_ch4"
> +
> +#define TIM3_TRGO "tim3_trgo"
> +#define TIM3_CH1 "tim3_ch1"
> +#define TIM3_CH2 "tim3_ch2"
> +#define TIM3_CH3 "tim3_ch3"
> +#define TIM3_CH4 "tim3_ch4"
> +
> +#define TIM4_TRGO "tim4_trgo"
> +#define TIM4_CH1 "tim4_ch1"
> +#define TIM4_CH2 "tim4_ch2"
> +#define TIM4_CH3 "tim4_ch3"
> +#define TIM4_CH4 "tim4_ch4"
> +
> +#define TIM5_TRGO "tim5_trgo"
> +#define TIM5_CH1 "tim5_ch1"
> +#define TIM5_CH2 "tim5_ch2"
> +#define TIM5_CH3 "tim5_ch3"
> +#define TIM5_CH4 "tim5_ch4"
> +
> +#define TIM6_TRGO "tim6_trgo"
> +
> +#define TIM7_TRGO "tim7_trgo"
> +
> +#define TIM8_TRGO "tim8_trgo"
> +#define TIM8_CH1 "tim8_ch1"
> +#define TIM8_CH2 "tim8_ch2"
> +#define TIM8_CH3 "tim8_ch3"
> +#define TIM8_CH4 "tim8_ch4"
> +
> +#define TIM9_TRGO "tim9_trgo"
> +#define TIM9_CH1 "tim9_ch1"
> +#define TIM9_CH2 "tim9_ch2"
> +
> +#define TIM12_TRGO "tim12_trgo"
> +#define TIM12_CH1 "tim12_ch1"
> +#define TIM12_CH2 "tim12_ch2"
> +
> +bool is_stm32_timer_trigger(struct iio_trigger *trig);
> +
> +#endif
>
^ permalink raw reply
* [GIT PULL] omap fixes for v4.10-rc cycle
From: Tony Lindgren @ 2016-12-30 21:10 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.10/fixes-rc1
for you to fetch changes up to 1a38de880992764d4bd5bccbd306b87d860e377d:
ARM: dts: am572x-idk: Add gpios property to control PCIE_RESETn (2016-12-30 10:59:56 -0800)
----------------------------------------------------------------
Fist set of fixes for omaps for v4.10-rc cycle, mostly
to deal with various regressions noticed during the merge
window and to fix various device tree configurations for
boards. Also included is removal of mach-omap2/gpio.c that
is now dead code with device tree based booting that should
be OK for the early -rc cycle:
- A series of fixes to add empty chosen node to fix regressions
caused for bootloaders that don't create chosen node as the
decompressor needs the chosen node to merge command line and
ATAGs into it
- Fix missing logicpd-som-lv-37xx-devkit.dtb entry in Makefile
- Fix regression for am437x timers
- Fix wrong strcat for non-NULL terminated string
- A series of changes to fix tps65217 interrupts to not use
defines as we don't do that for interrupts
- Two patches to fix USB VBUS detection on am57xx-idk and force it
to peripheral mode until dwc3 role detection is working
- Add missing dra72-evm-tps65917 missing voltage supplies
accidentally left out of an earlier patch
- Fix n900 eMMC detection when booted on qemu
- Remove unwanted pr_err on failed memory allocation for
prm_common.c
- Remove legacy mach-omap2/gpio.c that now is dead code
since we boot mach-omap2 in device tree only mode
- Fix am572x-idk pcie1 by adding the missing gpio reset pin
----------------------------------------------------------------
Adam Ford (1):
ARM: dts: omap3: Add DTS for Logic PD SOM-LV 37xx Dev Kit
Grygorii Strashko (2):
ARM: OMAP2+: Remove legacy gpio code
ARM: omap2+: am437x: rollback to use omap3_gptimer_timer_init()
Javier Martinez Canillas (9):
ARM: dts: omap2: Add an empty chosen node to top level DTSI
ARM: dts: omap3: Add an empty chosen node to top level DTSI
ARM: dts: omap4: Add an empty chosen node to top level DTSI
ARM: dts: omap5: Add an empty chosen node to top level DTSI
ARM: dts: am33xx: Add an empty chosen node to top level DTSI
ARM: dts: am4372: Add an empty chosen node to top level DTSI
ARM: dts: dm814x: Add an empty chosen node to top level DTSI
ARM: dts: dm816x: Add an empty chosen node to top level DTSI
ARM: dts: dra7: Add an empty chosen node to top level DTSI
Kishon Vijay Abraham I (1):
ARM: dts: am572x-idk: Add gpios property to control PCIE_RESETn
Lokesh Vutla (1):
ARM: dts: dra72-evm-tps65917: Add voltage supplies to usb_phy, mmc, dss
Maninder Singh (1):
ARM: omap2+: fixing wrong strcat for Non-NULL terminated string
Markus Elfring (1):
ARM: OMAP2+: PRM: Delete an error message for a failed memory allocation
Milo Kim (4):
ARM: dts: am335x: Fix the interrupt name of TPS65217
dt-bindings: mfd: Remove TPS65217 interrupts
dt-bindings: power/supply: Update TPS65217 properties
dt-bindings: input: Specify the interrupt number of TPS65217 power button
Pali Roh?r (1):
ARM: dts: n900: Mark eMMC slot with no-sdio and no-sd flags
Roger Quadros (2):
ARM: dts: am57xx-idk: Support VBUS detection on USB2 port
ARM: dts: am57xx-idk: Put USB2 port in peripheral mode
Tony Lindgren (1):
Merge branch 'omap-for-v4.10/legacy' into omap-for-v4.10/fixes
.../bindings/input/tps65218-pwrbutton.txt | 4 +-
.../bindings/power/supply/tps65217_charger.txt | 7 +-
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/am335x-bone-common.dtsi | 8 +-
arch/arm/boot/dts/am33xx.dtsi | 1 +
arch/arm/boot/dts/am4372.dtsi | 1 +
arch/arm/boot/dts/am571x-idk.dts | 10 +-
arch/arm/boot/dts/am572x-idk.dts | 14 +-
arch/arm/boot/dts/am57xx-idk-common.dtsi | 9 +-
arch/arm/boot/dts/dm814x.dtsi | 1 +
arch/arm/boot/dts/dm816x.dtsi | 1 +
arch/arm/boot/dts/dra7.dtsi | 1 +
arch/arm/boot/dts/dra72-evm-tps65917.dtsi | 16 +++
arch/arm/boot/dts/omap2.dtsi | 1 +
arch/arm/boot/dts/omap3-n900.dts | 2 +
arch/arm/boot/dts/omap3.dtsi | 1 +
arch/arm/boot/dts/omap4.dtsi | 1 +
arch/arm/boot/dts/omap5.dtsi | 1 +
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/board-generic.c | 2 +-
arch/arm/mach-omap2/gpio.c | 160 ---------------------
arch/arm/mach-omap2/omap_hwmod.c | 8 +-
arch/arm/mach-omap2/omap_hwmod_common_data.h | 4 -
arch/arm/mach-omap2/prm_common.c | 4 +-
arch/arm/mach-omap2/timer.c | 9 +-
include/dt-bindings/mfd/tps65217.h | 26 ----
26 files changed, 74 insertions(+), 221 deletions(-)
delete mode 100644 arch/arm/mach-omap2/gpio.c
delete mode 100644 include/dt-bindings/mfd/tps65217.h
^ permalink raw reply
* [PATCH v6 2/8] MFD: add STM32 Timers driver
From: Jonathan Cameron @ 2016-12-30 20:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481292919-26587-3-git-send-email-benjamin.gaignard@st.com>
On 09/12/16 14:15, Benjamin Gaignard wrote:
> This hardware block could at used at same time for PWM generation
> and IIO timers.
> PWM and IIO timer configuration are mixed in the same registers
> so we need a multi fonction driver to be able to share those registers.
fonction -> function
>
> version 6:
> - rename files to stm32-timers
> - rename functions to stm32_timers_xxx
>
> version 5:
> - fix Lee comments about detect function
> - add missing dependency on REGMAP_MMIO
>
> version 4:
> - add a function to detect Auto Reload Register (ARR) size
> - rename the structure shared with other drivers
>
> version 2:
> - rename driver "stm32-gptimer" to be align with SoC documentation
> - only keep one compatible
> - use of_platform_populate() instead of devm_mfd_add_devices()
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> drivers/mfd/Kconfig | 11 ++++++
> drivers/mfd/Makefile | 2 +
> drivers/mfd/stm32-timers.c | 80 ++++++++++++++++++++++++++++++++++++++++
> include/linux/mfd/stm32-timers.h | 71 +++++++++++++++++++++++++++++++++++
> 4 files changed, 164 insertions(+)
> create mode 100644 drivers/mfd/stm32-timers.c
> create mode 100644 include/linux/mfd/stm32-timers.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index c6df644..4ec1906 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1607,6 +1607,17 @@ config MFD_STW481X
> in various ST Microelectronics and ST-Ericsson embedded
> Nomadik series.
>
> +config MFD_STM32_TIMERS
> + tristate "Support for STM32 Timers"
> + depends on (ARCH_STM32 && OF) || COMPILE_TEST
> + select MFD_CORE
> + select REGMAP
> + select REGMAP_MMIO
> + help
> + Select this option to enable STM32 timers driver used
> + for PWM and IIO Timer. This driver allow to share the
> + registers between the others drivers.
> +
> menu "Multimedia Capabilities Port drivers"
> depends on ARCH_SA1100
>
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 9834e66..11a52f8 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
>
> obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> +
> +obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o
> diff --git a/drivers/mfd/stm32-timers.c b/drivers/mfd/stm32-timers.c
> new file mode 100644
> index 0000000..68d115e
> --- /dev/null
> +++ b/drivers/mfd/stm32-timers.c
> @@ -0,0 +1,80 @@
> +/*
> + * Copyright (C) STMicroelectronics 2016
> + *
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/mfd/stm32-timers.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/reset.h>
> +
> +static const struct regmap_config stm32_timers_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = sizeof(u32),
> + .max_register = 0x400,
> +};
> +
> +static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
> +{
> + /*
> + * Only the available bits will be written so when readback
> + * we get the maximum value of auto reload register
> + */
> + regmap_write(ddata->regmap, TIM_ARR, ~0L);
> + regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
> + regmap_write(ddata->regmap, TIM_ARR, 0x0);
> +}
> +
> +static int stm32_timers_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct stm32_timers *ddata;
> + struct resource *res;
> + void __iomem *mmio;
> +
> + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
> + if (!ddata)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(mmio))
> + return PTR_ERR(mmio);
> +
> + ddata->regmap = devm_regmap_init_mmio_clk(dev, "clk_int", mmio,
> + &stm32_timers_regmap_cfg);
> + if (IS_ERR(ddata->regmap))
> + return PTR_ERR(ddata->regmap);
> +
> + ddata->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(ddata->clk))
> + return PTR_ERR(ddata->clk);
> +
> + stm32_timers_get_arr_size(ddata);
> +
> + platform_set_drvdata(pdev, ddata);
> +
> + return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
> +}
> +
> +static const struct of_device_id stm32_timers_of_match[] = {
> + { .compatible = "st,stm32-timers", },
> + { /* end node */ },
> +};
> +MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
> +
> +static struct platform_driver stm32_timers_driver = {
> + .probe = stm32_timers_probe,
> + .driver = {
> + .name = "stm32-timers",
> + .of_match_table = stm32_timers_of_match,
> + },
> +};
> +module_platform_driver(stm32_timers_driver);
> +
> +MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
> new file mode 100644
> index 0000000..d030004
> --- /dev/null
> +++ b/include/linux/mfd/stm32-timers.h
> @@ -0,0 +1,71 @@
> +/*
> + * Copyright (C) STMicroelectronics 2016
> + *
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef _LINUX_STM32_GPTIMER_H_
> +#define _LINUX_STM32_GPTIMER_H_
> +
> +#include <linux/clk.h>
> +#include <linux/regmap.h>
> +
> +#define TIM_CR1 0x00 /* Control Register 1 */
> +#define TIM_CR2 0x04 /* Control Register 2 */
> +#define TIM_SMCR 0x08 /* Slave mode control reg */
> +#define TIM_DIER 0x0C /* DMA/interrupt register */
> +#define TIM_SR 0x10 /* Status register */
> +#define TIM_EGR 0x14 /* Event Generation Reg */
> +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
> +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
> +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
> +#define TIM_PSC 0x28 /* Prescaler */
> +#define TIM_ARR 0x2c /* Auto-Reload Register */
> +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
> +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
> +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
> +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
> +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
> +
> +#define TIM_CR1_CEN BIT(0) /* Counter Enable */
> +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> +#define TIM_DIER_UIE BIT(0) /* Update interrupt */
> +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
> +#define TIM_EGR_UG BIT(0) /* Update Generation */
> +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
> +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
> +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
> +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
> +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
> +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
> +#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
> +#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
> +#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
> +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
> +#define TIM_BDTR_BKE BIT(12) /* Break input enable */
> +#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
> +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
> +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
> +#define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19))
> +#define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23))
> +#define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */
> +#define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */
> +
> +#define MAX_TIM_PSC 0xFFFF
> +#define TIM_CR2_MMS_SHIFT 4
> +#define TIM_SMCR_TS_SHIFT 4
> +#define TIM_BDTR_BKF_MASK 0xF
> +#define TIM_BDTR_BKF_SHIFT 16
> +#define TIM_BDTR_BK2F_SHIFT 20
> +
> +struct stm32_timers {
> + struct clk *clk;
> + struct regmap *regmap;
> + u32 max_arr;
> +};
> +#endif
>
^ permalink raw reply
* [PATCH v2 3/4] ARM64: dts: exynos5433: use macros for pinctrl configuration on Exynos5433
From: Andi Shyti @ 2016-12-30 20:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdaz9AyFJs1Th_SVexqKaP-=iPF0G-1YXOCoSmrQH8ZHDA@mail.gmail.com>
Hi Linus,
> > Use the macros defined in include/dt-bindings/pinctrl/samsung.h
> > instead of hardcoded values.
> >
> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>
> These look fine, but that this and the other DTS patch through ARM SoC.
>
> If you also need the headerfile patch (patch 2) to go through ARM SoC
> that is fine,
> I can take it out of pinctrl if you want.
yes, sure... no problem from my side :)
Thanks,
Andi
^ permalink raw reply
* Linux fails to start secondary cores when system resumes from Suspend-to-RAM
From: Pavel Machek @ 2016-12-30 20:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4dc90086-180d-df9a-297f-6f4680de7bdd@free.fr>
Hi!
On Thu 2016-12-29 15:27:12, Mason wrote:
> On Thu, Dec 15, 2016 at 11:18 PM, Mason wrote:
>
> > However, while Linux successfully starts the secondary cores when
> > the system first boots, it fails when the system resumes from "S3".
>
> Oh boy...
>
> Turns out the firmware was, in fact, (upon resume) stomping over parts
> of the Linux memory image in RAM, triggering all kinds of "interesting"
> nasal demons when Linux ran (or, more accurately, limped).
Well... firmware is always fun :-). Good that it got solved...
Pavel
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* [linux-sunxi] [PATCH 1/2] drivers: pinctrl: add driver for Allwinner H5 SoC
From: Tony Lindgren @ 2016-12-30 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYQhfid3VRcaj=7as_+Zg=pX3Svp9FJ_W_Ft8nVuoZqKQ@mail.gmail.com>
* Linus Walleij <linus.walleij@linaro.org> [161230 04:56]:
> On Mon, Dec 26, 2016 at 3:33 PM, Andr? Przywara <andre.przywara@arm.com> wrote:
>
> > So while this patch technically looks correct, I was wondering if we
> > should really explore the possibility of making the whole of sunxi
> > pinctrl DT controlled.
> > I brought this up a while ago, but people weren't overly enthusiastic
> > about it, though their argument weren't really convincing to me[1].
> >
> > So:
> > As this "driver" here is basically a table linking GPIO bit settings
> > (the actual mux value) to names and every pin we care about needs to be
> > enumerated in the DT anyway, why not just add something like:
> > allwinner,pinmux = <4>;
> > to each pin(group) in the DT and get rid of this "driver" file here
> > entirely?
>
> I'm open to that if you can use pinctrl-single which is in the kernel
> for this purpose only, and is used with both OMAPs and HiSilicon.
>
> It recently was improved and will be improved more in this cycle,
> see for example:
> commit 42124bc598f64f84b3335d5a058304207695b84f
> pinctrl: Introduce generic #pinctrl-cells and pinctrl_parse_index_with_args
>
> > (...) Also I guess the common sunxi
> > pinctrl driver code needs some significant rework.
>
> I would guess is just needs replacing with pinctrl-single in that case.
And if pinctrl-single won't work then it is now also be easier to make
hardware specific drivers too using #pinctrl-cells + GENERIC_PINCTRL_GROUPS +
GENERIC_PINMUX_FUNCTIONS.
Regards,
Tony
^ permalink raw reply
* [PATCH] trace: extend trace_clock to support arch_arm clock counter
From: Stephen Boyd @ 2016-12-30 19:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161220170458.GM10132@arm.com>
On 12/20, Will Deacon wrote:
> On Thu, Dec 15, 2016 at 06:46:09PM +0530, Srinivas Ramana wrote:
> > On 12/12/2016 04:12 PM, Will Deacon wrote:
> > >On Mon, Dec 12, 2016 at 10:31:52AM +0530, Srinivas Ramana wrote:
> > >>On 12/06/2016 05:43 PM, Will Deacon wrote:
> > >>>Does this mean we need a way to expose the frequency to userspace, too?
> > >>
> > >>Not really. The CNTFRQ_EL0 of timer subsystem holds the clock frequency of
> > >>system timer and is available to EL0.
> > >
> > >Experience shows that CNTFRQ_EL0 is often unreliable, and the frequency
> > >can be overridden by the device-tree. There are also systems where the
> > >counter stops ticking across suspend. Whilst both of these can be considered
> > >"broken", I suspect we want runtime buy-in from the arch-timer driver
> > >before registering this trace_clock.
> >
> > Agree. It doesnt seem like architecture mandates initializing this.
> > For those systems where tick would stop, if not arch counter, i assume there
> > is some counter which falls in 'always ON' domain without which they cant
> > keep track of time.
>
> We just need to avoid exposing this trace clock if the frequency was
> provided by firmware.
>
We would need to know the frequency if we wanted to convert the
counter values into seconds. In our case, we don't really care to
do that. All we want to do is compare events in the ftrace log
with events in other hw subsystem logs. If we have the raw
counter value there then it makes it simple to compare the two
and debug problems. Now that isn't to say that it would be useful
to convert the counter value into seconds, but it doesn't look to
be a prerequisite of registering the trace clock.
If we want to expose the counter frequency to userspace we could
make a sysfs attribute for that and have userspace rely on it
instead of CNTFRQ_EL0. Or if we can make CNTFRQ_EL0 accesses trap
(forgive me for not looking at the ARM ARM right now) we can
emulate it based on the DT property.
And for systems where the counter stops during suspend, I imagine
the only problem would be tracing across suspend would show a
clock that doesn't keep counting while suspended. sched_clock()
already exhibits that behavior, so I'm not sure we've lost
anything here.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 2/3 v2] iio: adc: break out common code from SPMI VADC
From: Jonathan Cameron @ 2016-12-30 19:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481842105-14047-1-git-send-email-linus.walleij@linaro.org>
On 15/12/16 22:48, Linus Walleij wrote:
> The SPMI VADC and the earlier XOADC share a subset of
> common code, so to be able to use the same code in both
> drivers, we break out a separate file with the common code,
> prefix exported functions that are no longer static with
> qcom_* and bake an object qcom-vadc.o that contains both
> files: qcom-vadc-common.o and qcom-spmi-vadc.o.
>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-arm-msm at vger.kernel.org
> Cc: Ivan T. Ivanov <iivanov.xz@gmail.com>
> Cc: Andy Gross <andy.gross@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Looks superficially fine, but I'm guessing will need a respin
as we have a fair bit of new stuff (and a couple of fixes) going
through this driver at the moment.
All but the two fixes I posted a few mins ago are in my testing
branch and should go to Greg once I have confirmed testing on
those two fixes.
Jonathan
> ---
> ChangeLog v1->v2:
> - No changes just reposting
> ---
> drivers/iio/adc/Makefile | 3 +-
> drivers/iio/adc/qcom-spmi-vadc.c | 95 +++-----------------------------------
> drivers/iio/adc/qcom-vadc-common.c | 38 +++++++++++++++
> drivers/iio/adc/qcom-vadc-common.h | 69 +++++++++++++++++++++++++++
> 4 files changed, 116 insertions(+), 89 deletions(-)
> create mode 100644 drivers/iio/adc/qcom-vadc-common.c
> create mode 100644 drivers/iio/adc/qcom-vadc-common.h
>
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index 7a40c04c311f..f9468d228b1e 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -38,7 +38,8 @@ obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
> -obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
> +qcom-vadc-y := qcom-vadc-common.o
> +obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-vadc.o qcom-spmi-vadc.o
> obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
> obj-$(CONFIG_STX104) += stx104.o
> obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
> diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
> index c2babe50a0d8..74d21afa34a9 100644
> --- a/drivers/iio/adc/qcom-spmi-vadc.c
> +++ b/drivers/iio/adc/qcom-spmi-vadc.c
> @@ -28,6 +28,8 @@
>
> #include <dt-bindings/iio/qcom,spmi-vadc.h>
>
> +#include "qcom-vadc-common.h"
> +
> /* VADC register and bit definitions */
> #define VADC_REVISION2 0x1
> #define VADC_REVISION2_SUPPORTED_VADC 1
> @@ -75,69 +77,9 @@
>
> #define VADC_DATA 0x60 /* 16 bits */
>
> -#define VADC_CONV_TIME_MIN_US 2000
> -#define VADC_CONV_TIME_MAX_US 2100
> -
> -/* Min ADC code represents 0V */
> -#define VADC_MIN_ADC_CODE 0x6000
> -/* Max ADC code represents full-scale range of 1.8V */
> -#define VADC_MAX_ADC_CODE 0xa800
> -
> -#define VADC_ABSOLUTE_RANGE_UV 625000
> -#define VADC_RATIOMETRIC_RANGE_UV 1800000
> -
> -#define VADC_DEF_PRESCALING 0 /* 1:1 */
> -#define VADC_DEF_DECIMATION 0 /* 512 */
> -#define VADC_DEF_HW_SETTLE_TIME 0 /* 0 us */
> -#define VADC_DEF_AVG_SAMPLES 0 /* 1 sample */
> -#define VADC_DEF_CALIB_TYPE VADC_CALIB_ABSOLUTE
> -
> -#define VADC_DECIMATION_MIN 512
> -#define VADC_DECIMATION_MAX 4096
> -
> -#define VADC_HW_SETTLE_DELAY_MAX 10000
> -#define VADC_AVG_SAMPLES_MAX 512
> -
> -#define KELVINMIL_CELSIUSMIL 273150
> -
> #define VADC_CHAN_MIN VADC_USBIN
> #define VADC_CHAN_MAX VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM
>
> -/*
> - * VADC_CALIB_ABSOLUTE: uses the 625mV and 1.25V as reference channels.
> - * VADC_CALIB_RATIOMETRIC: uses the reference voltage (1.8V) and GND for
> - * calibration.
> - */
> -enum vadc_calibration {
> - VADC_CALIB_ABSOLUTE = 0,
> - VADC_CALIB_RATIOMETRIC
> -};
> -
> -/**
> - * struct vadc_linear_graph - Represent ADC characteristics.
> - * @dy: numerator slope to calculate the gain.
> - * @dx: denominator slope to calculate the gain.
> - * @gnd: A/D word of the ground reference used for the channel.
> - *
> - * Each ADC device has different offset and gain parameters which are
> - * computed to calibrate the device.
> - */
> -struct vadc_linear_graph {
> - s32 dy;
> - s32 dx;
> - s32 gnd;
> -};
> -
> -/**
> - * struct vadc_prescale_ratio - Represent scaling ratio for ADC input.
> - * @num: the inverse numerator of the gain applied to the input channel.
> - * @den: the inverse denominator of the gain applied to the input channel.
> - */
> -struct vadc_prescale_ratio {
> - u32 num;
> - u32 den;
> -};
> -
> /**
> * struct vadc_channel_prop - VADC channel property.
> * @channel: channel number, refer to the channel list.
> @@ -471,33 +413,10 @@ static int vadc_measure_ref_points(struct vadc_priv *vadc)
> static s32 vadc_calibrate(struct vadc_priv *vadc,
> const struct vadc_channel_prop *prop, u16 adc_code)
> {
> - const struct vadc_prescale_ratio *prescale;
> - s64 voltage;
> -
> - voltage = adc_code - vadc->graph[prop->calibration].gnd;
> - voltage *= vadc->graph[prop->calibration].dx;
> - voltage = div64_s64(voltage, vadc->graph[prop->calibration].dy);
> -
> - if (prop->calibration == VADC_CALIB_ABSOLUTE)
> - voltage += vadc->graph[prop->calibration].dx;
> -
> - if (voltage < 0)
> - voltage = 0;
> -
> - prescale = &vadc_prescale_ratios[prop->prescale];
> -
> - voltage = voltage * prescale->den;
> -
> - return div64_s64(voltage, prescale->num);
> -}
> -
> -static int vadc_decimation_from_dt(u32 value)
> -{
> - if (!is_power_of_2(value) || value < VADC_DECIMATION_MIN ||
> - value > VADC_DECIMATION_MAX)
> - return -EINVAL;
> -
> - return __ffs64(value / VADC_DECIMATION_MIN);
> + return qcom_vadc_calibrate(&vadc_prescale_ratios[prop->prescale],
> + &vadc->graph[prop->calibration],
> + (prop->calibration == VADC_CALIB_ABSOLUTE),
> + adc_code);
> }
>
> static int vadc_prescaling_from_dt(u32 num, u32 den)
> @@ -752,7 +671,7 @@ static int vadc_get_dt_channel_data(struct device *dev,
>
> ret = of_property_read_u32(node, "qcom,decimation", &value);
> if (!ret) {
> - ret = vadc_decimation_from_dt(value);
> + ret = qcom_vadc_decimation_from_dt(value);
> if (ret < 0) {
> dev_err(dev, "%02x invalid decimation %d\n",
> chan, value);
> diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c
> new file mode 100644
> index 000000000000..f67fc5e2a702
> --- /dev/null
> +++ b/drivers/iio/adc/qcom-vadc-common.c
> @@ -0,0 +1,38 @@
> +#include <linux/kernel.h>
> +#include <linux/bitops.h>
> +#include <linux/math64.h>
> +#include <linux/log2.h>
> +#include <linux/err.h>
> +
> +#include "qcom-vadc-common.h"
> +
> +s32 qcom_vadc_calibrate(const struct vadc_prescale_ratio *prescale,
> + const struct vadc_linear_graph *graph,
> + bool absolute,
> + u16 adc_code)
> +{
> + s64 voltage;
> +
> + voltage = adc_code - graph->gnd;
> + voltage *= graph->dx;
> + voltage = div64_s64(voltage, graph->dy);
> +
> + if (absolute)
> + voltage += graph->dx;
> +
> + if (voltage < 0)
> + voltage = 0;
> +
> + voltage = voltage * prescale->den;
> +
> + return div64_s64(voltage, prescale->num);
> +}
> +
> +int qcom_vadc_decimation_from_dt(u32 value)
> +{
> + if (!is_power_of_2(value) || value < VADC_DECIMATION_MIN ||
> + value > VADC_DECIMATION_MAX)
> + return -EINVAL;
> +
> + return __ffs64(value / VADC_DECIMATION_MIN);
> +}
> diff --git a/drivers/iio/adc/qcom-vadc-common.h b/drivers/iio/adc/qcom-vadc-common.h
> new file mode 100644
> index 000000000000..b41cb501eef8
> --- /dev/null
> +++ b/drivers/iio/adc/qcom-vadc-common.h
> @@ -0,0 +1,69 @@
> +/*
> + * Code shared between the different Qualcomm PMIC voltage ADCs
> + */
> +
> +#define VADC_CONV_TIME_MIN_US 2000
> +#define VADC_CONV_TIME_MAX_US 2100
> +
> +/* Min ADC code represents 0V */
> +#define VADC_MIN_ADC_CODE 0x6000
> +/* Max ADC code represents full-scale range of 1.8V */
> +#define VADC_MAX_ADC_CODE 0xa800
> +
> +#define VADC_ABSOLUTE_RANGE_UV 625000
> +#define VADC_RATIOMETRIC_RANGE_UV 1800000
> +
> +#define VADC_DEF_PRESCALING 0 /* 1:1 */
> +#define VADC_DEF_DECIMATION 0 /* 512 */
> +#define VADC_DEF_HW_SETTLE_TIME 0 /* 0 us */
> +#define VADC_DEF_AVG_SAMPLES 0 /* 1 sample */
> +#define VADC_DEF_CALIB_TYPE VADC_CALIB_ABSOLUTE
> +
> +#define VADC_DECIMATION_MIN 512
> +#define VADC_DECIMATION_MAX 4096
> +
> +#define VADC_HW_SETTLE_DELAY_MAX 10000
> +#define VADC_AVG_SAMPLES_MAX 512
> +
> +#define KELVINMIL_CELSIUSMIL 273150
> +
> +/*
> + * VADC_CALIB_ABSOLUTE: uses the 625mV and 1.25V as reference channels.
> + * VADC_CALIB_RATIOMETRIC: uses the reference voltage (1.8V) and GND for
> + * calibration.
> + */
> +enum vadc_calibration {
> + VADC_CALIB_ABSOLUTE = 0,
> + VADC_CALIB_RATIOMETRIC
> +};
> +
> +/**
> + * struct vadc_linear_graph - Represent ADC characteristics.
> + * @dy: numerator slope to calculate the gain.
> + * @dx: denominator slope to calculate the gain.
> + * @gnd: A/D word of the ground reference used for the channel.
> + *
> + * Each ADC device has different offset and gain parameters which are
> + * computed to calibrate the device.
> + */
> +struct vadc_linear_graph {
> + s32 dy;
> + s32 dx;
> + s32 gnd;
> +};
> +
> +/**
> + * struct vadc_prescale_ratio - Represent scaling ratio for ADC input.
> + * @num: the inverse numerator of the gain applied to the input channel.
> + * @den: the inverse denominator of the gain applied to the input channel.
> + */
> +struct vadc_prescale_ratio {
> + u32 num;
> + u32 den;
> +};
> +
> +s32 qcom_vadc_calibrate(const struct vadc_prescale_ratio *prescale,
> + const struct vadc_linear_graph *graph,
> + bool absolute,
> + u16 adc_code);
> +int qcom_vadc_decimation_from_dt(u32 value);
>
^ permalink raw reply
* [PATCH] ARM: dts: am572x-idk: Add gpios property to control PCIE_RESETn
From: Tony Lindgren @ 2016-12-30 19:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483085240-16102-1-git-send-email-kishon@ti.com>
* Kishon Vijay Abraham I <kishon@ti.com> [161230 00:08]:
> Add 'gpios' property to pcie1 dt node and populate it with
> GPIO3_23 in order to drive PCIE_RESETn high.
>
> This gets PCIe cards to be detected in AM572X IDK board.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> arch/arm/boot/dts/am572x-idk.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
> index 27d9149..1540f7a 100644
> --- a/arch/arm/boot/dts/am572x-idk.dts
> +++ b/arch/arm/boot/dts/am572x-idk.dts
> @@ -87,3 +87,7 @@
> &sn65hvs882 {
> load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
> };
> +
> +&pcie1 {
> + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
> +};
I'll apply this into omap-for-v4.10/fixes thanks.
Tony
^ permalink raw reply
* [PATCH] ARM: dts: imx: Remove unexistant property
From: Fabio Estevam @ 2016-12-30 18:42 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
Property 'anatop-enable-bit' does not exist, so just remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 1 -
arch/arm/boot/dts/imx7s.dtsi | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 39845a7..e601328 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -534,7 +534,6 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
- anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 8ff2cbdd..8db1eb9 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -509,7 +509,6 @@
anatop-min-bit-val = <8>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1200000>;
- anatop-enable-bit = <31>;
};
};
--
2.7.4
^ permalink raw reply related
* [RFC PATCH] sched: Remove set_task_state()
From: Davidlohr Bueso @ 2016-12-30 18:17 UTC (permalink / raw)
To: linux-arm-kernel
This is a nasty interface and setting the state of a foreign task
must not be done. While as of be628be0956 (bcache: Make gc wakeup
sane, remove set_task_state()) everyone in the kernel calls
set_task_state() with current, allowing the helper to be removed.
However, as the comment indicates, it is still around for those
archs where computing current is more expensive than using a pointer,
at least in theory.
Of all the callers, if any, it's the locking bits that would care
most about this -- ie: we end up passing a tsk pointer to a lot of
the lock slowpath, and setting ->state on that. The following numbers
are based on two tests: a custom ad-hoc microbenchmark that just
measures latencies (for ~65 million calls) between get_task_state()
vs get_current_state().
Secondly for a higher overview, an unlink microbenchmark was used,
which pounds on a single file with open, close,unlink combos with
increasing thread counts (up to 4x ncpus). While the workload is
quite unrealistic, it does contend a lot on the inode mutex or now
rwsem. With the archs I had access to, the differences are as follows:
== 1. arm64 ==
0000000000002784 <set_task_state>:
2784: f9000c1f str xzr, [x0,#24]
0000000000002790 <set_current_state>:
2790: d5384100 mrs x0, sp_el0
2794: f9000c1f str xzr, [x0,#24]
Avg runtime set_task_state(): 2648 msecs
Avg runtime set_current_state(): 2686 msecs
vanilla dirty
Hmean unlink1-processes-2 8146.94 ( 0.00%) 9564.74 ( 17.40%)
Hmean unlink1-processes-5 9627.49 ( 0.00%) 8935.47 ( -7.19%)
Hmean unlink1-processes-8 9148.07 ( 0.00%) 8867.29 ( -3.07%)
Hmean unlink1-processes-12 9168.15 ( 0.00%) 8952.79 ( -2.35%)
Hmean unlink1-processes-21 9067.45 ( 0.00%) 9246.20 ( 1.97%)
Hmean unlink1-processes-30 9310.21 ( 0.00%) 8831.77 ( -5.14%)
Hmean unlink1-processes-48 9100.57 ( 0.00%) 9084.36 ( -0.18%)
Hmean unlink1-processes-79 9022.37 ( 0.00%) 8178.66 ( -9.35%)
Hmean unlink1-processes-110 8940.33 ( 0.00%) 8186.77 ( -8.43%)
Hmean unlink1-processes-141 9001.95 ( 0.00%) 8429.08 ( -6.36%)
Hmean unlink1-processes-172 8990.60 ( 0.00%) 8059.33 (-10.36%)
Hmean unlink1-processes-203 8456.43 ( 0.00%) 8065.69 ( -4.62%)
Hmean unlink1-processes-234 9020.57 ( 0.00%) 8495.15 ( -5.82%)
Hmean unlink1-processes-265 8849.48 ( 0.00%) 8123.47 ( -8.20%)
Hmean unlink1-processes-296 8890.80 ( 0.00%) 8272.24 ( -6.96%)
Hmean unlink1-processes-327 8637.74 ( 0.00%) 8377.55 ( -3.01%)
Hmean unlink1-processes-358 8690.21 ( 0.00%) 8492.25 ( -2.28%)
Hmean unlink1-processes-384 8687.64 ( 0.00%) 8510.68 ( -2.04%)
== 2. x86-64 ==
0000000000002cc0 <set_task_state>:
2cc1: 48 c7 47 08 00 00 00 movq $0x0,0x8(%rdi)
2cc9: 48 89 e5 mov %rsp,%rbp
0000000000002cd0 <set_current_state>:
2cd1: 65 48 8b 04 25 00 00 mov %gs:0x0,%rax
2cda: 48 89 e5 mov %rsp,%rbp
2cdd: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax)
Avg runtime set_task_state(): 601 msecs
Avg runtime set_current_state(): 552 msecs
vanilla dirty
Hmean unlink1-processes-2 36089.26 ( 0.00%) 38977.33 ( 8.00%)
Hmean unlink1-processes-5 28555.01 ( 0.00%) 29832.55 ( 4.28%)
Hmean unlink1-processes-8 37323.75 ( 0.00%) 44974.57 ( 20.50%)
Hmean unlink1-processes-12 43571.88 ( 0.00%) 44283.01 ( 1.63%)
Hmean unlink1-processes-21 34431.52 ( 0.00%) 38284.45 ( 11.19%)
Hmean unlink1-processes-30 34813.26 ( 0.00%) 37975.17 ( 9.08%)
Hmean unlink1-processes-48 37048.90 ( 0.00%) 39862.78 ( 7.59%)
Hmean unlink1-processes-79 35630.01 ( 0.00%) 36855.30 ( 3.44%)
Hmean unlink1-processes-110 36115.85 ( 0.00%) 39843.91 ( 10.32%)
Hmean unlink1-processes-141 32546.96 ( 0.00%) 35418.52 ( 8.82%)
Hmean unlink1-processes-172 34674.79 ( 0.00%) 36899.21 ( 6.42%)
Hmean unlink1-processes-203 37303.11 ( 0.00%) 36393.04 ( -2.44%)
Hmean unlink1-processes-224 35712.13 ( 0.00%) 36685.96 ( 2.73%)
== 3. ppc64le ==
Avg runtime set_task_state(): 938 msecs
Avg runtime set_current_state: 940 msecs
vanilla dirty
Hmean unlink1-processes-2 19269.19 ( 0.00%) 30704.50 ( 59.35%)
Hmean unlink1-processes-5 20106.15 ( 0.00%) 21804.15 ( 8.45%)
Hmean unlink1-processes-8 17496.97 ( 0.00%) 17243.28 ( -1.45%)
Hmean unlink1-processes-12 14224.15 ( 0.00%) 17240.21 ( 21.20%)
Hmean unlink1-processes-21 14155.66 ( 0.00%) 15681.23 ( 10.78%)
Hmean unlink1-processes-30 14450.70 ( 0.00%) 15995.83 ( 10.69%)
Hmean unlink1-processes-48 16945.57 ( 0.00%) 16370.42 ( -3.39%)
Hmean unlink1-processes-79 15788.39 ( 0.00%) 14639.27 ( -7.28%)
Hmean unlink1-processes-110 14268.48 ( 0.00%) 14377.40 ( 0.76%)
Hmean unlink1-processes-141 14023.65 ( 0.00%) 16271.69 ( 16.03%)
Hmean unlink1-processes-172 13417.62 ( 0.00%) 16067.55 ( 19.75%)
Hmean unlink1-processes-203 15293.08 ( 0.00%) 15440.40 ( 0.96%)
Hmean unlink1-processes-234 13719.32 ( 0.00%) 16190.74 ( 18.01%)
Hmean unlink1-processes-265 16400.97 ( 0.00%) 16115.22 ( -1.74%)
Hmean unlink1-processes-296 14388.60 ( 0.00%) 16216.13 ( 12.70%)
Hmean unlink1-processes-320 15771.85 ( 0.00%) 15905.96 ( 0.85%)
Unsurprisingly, the big looser is arm64, due to the masking of sp_el0.
otoh, x86-64 (known to be fast for get_current()/this_cpu_read_stable()
caching) and ppc64 (with paca) show similar improvements in the unlink
microbenches. x86's write latencies delta is similar to the opposite of
arm64: 50ms vs -40ms, respectively. The small delta for ppc64 (2ms), does
not represent the gains on the unlink runs. In the case of x86, there was
a decent amount of variation in the latency runs, but always within a 20
to 50ms increase), ppc was more constant.
So, do we want to get rid of the interface (and improve performance on
other archs) at the expense of arm64? Can arm64 do better?
Applies against v4.10-rc1.
Signed-off-by: Davidlohr Bueso <dbueso@suse.de>
---
arch/um/drivers/random.c | 2 +-
drivers/md/dm-bufio.c | 2 +-
drivers/md/dm-crypt.c | 4 ++--
drivers/md/persistent-data/dm-block-manager.c | 4 ++--
.../staging/lustre/lnet/libcfs/linux/linux-debug.c | 2 +-
drivers/tty/tty_ldsem.c | 10 ++++----
include/linux/sched.h | 27 +---------------------
kernel/exit.c | 4 ++--
kernel/locking/mutex.c | 8 +++----
kernel/locking/rwsem-spinlock.c | 8 +++----
kernel/locking/rwsem-xadd.c | 4 ++--
kernel/locking/semaphore.c | 2 +-
12 files changed, 26 insertions(+), 51 deletions(-)
diff --git a/arch/um/drivers/random.c b/arch/um/drivers/random.c
index 05523f14d7b2..57f03050c850 100644
--- a/arch/um/drivers/random.c
+++ b/arch/um/drivers/random.c
@@ -76,7 +76,7 @@ static ssize_t rng_dev_read (struct file *filp, char __user *buf, size_t size,
add_sigio_fd(random_fd);
add_wait_queue(&host_read_wait, &wait);
- set_task_state(current, TASK_INTERRUPTIBLE);
+ set_current_state(TASK_INTERRUPTIBLE);
schedule();
remove_wait_queue(&host_read_wait, &wait);
diff --git a/drivers/md/dm-bufio.c b/drivers/md/dm-bufio.c
index 84d2f0e4c754..d36d427a9efb 100644
--- a/drivers/md/dm-bufio.c
+++ b/drivers/md/dm-bufio.c
@@ -794,7 +794,7 @@ static void __wait_for_free_buffer(struct dm_bufio_client *c)
DECLARE_WAITQUEUE(wait, current);
add_wait_queue(&c->free_buffer_wait, &wait);
- set_task_state(current, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
dm_bufio_unlock(c);
io_schedule();
diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
index 7c6c57216bf2..96692d13a6e4 100644
--- a/drivers/md/dm-crypt.c
+++ b/drivers/md/dm-crypt.c
@@ -1210,14 +1210,14 @@ static int dmcrypt_write(void *data)
spin_unlock_irq(&cc->write_thread_wait.lock);
if (unlikely(kthread_should_stop())) {
- set_task_state(current, TASK_RUNNING);
+ set_current_state(TASK_RUNNING);
remove_wait_queue(&cc->write_thread_wait, &wait);
break;
}
schedule();
- set_task_state(current, TASK_RUNNING);
+ set_current_state(TASK_RUNNING);
spin_lock_irq(&cc->write_thread_wait.lock);
__remove_wait_queue(&cc->write_thread_wait, &wait);
goto continue_locked;
diff --git a/drivers/md/persistent-data/dm-block-manager.c b/drivers/md/persistent-data/dm-block-manager.c
index a6dde7cab458..758d90cc2733 100644
--- a/drivers/md/persistent-data/dm-block-manager.c
+++ b/drivers/md/persistent-data/dm-block-manager.c
@@ -120,7 +120,7 @@ static int __check_holder(struct block_lock *lock)
static void __wait(struct waiter *w)
{
for (;;) {
- set_task_state(current, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
if (!w->task)
break;
@@ -128,7 +128,7 @@ static void __wait(struct waiter *w)
schedule();
}
- set_task_state(current, TASK_RUNNING);
+ set_current_state(TASK_RUNNING);
}
static void __wake_waiter(struct waiter *w)
diff --git a/drivers/staging/lustre/lnet/libcfs/linux/linux-debug.c b/drivers/staging/lustre/lnet/libcfs/linux/linux-debug.c
index 39a72e3f0c18..7035356e56b3 100644
--- a/drivers/staging/lustre/lnet/libcfs/linux/linux-debug.c
+++ b/drivers/staging/lustre/lnet/libcfs/linux/linux-debug.c
@@ -107,7 +107,7 @@ void __noreturn lbug_with_loc(struct libcfs_debug_msg_data *msgdata)
libcfs_debug_dumplog();
if (libcfs_panic_on_lbug)
panic("LBUG");
- set_task_state(current, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
while (1)
schedule();
}
diff --git a/drivers/tty/tty_ldsem.c b/drivers/tty/tty_ldsem.c
index 1bf8ed13f827..c94bc0eef85d 100644
--- a/drivers/tty/tty_ldsem.c
+++ b/drivers/tty/tty_ldsem.c
@@ -232,7 +232,7 @@ down_read_failed(struct ld_semaphore *sem, long count, long timeout)
/* wait to be given the lock */
for (;;) {
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
if (!waiter.task)
break;
@@ -241,7 +241,7 @@ down_read_failed(struct ld_semaphore *sem, long count, long timeout)
timeout = schedule_timeout(timeout);
}
- __set_task_state(tsk, TASK_RUNNING);
+ __set_current_state(TASK_RUNNING);
if (!timeout) {
/* lock timed out but check if this task was just
@@ -291,14 +291,14 @@ down_write_failed(struct ld_semaphore *sem, long count, long timeout)
waiter.task = tsk;
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
for (;;) {
if (!timeout)
break;
raw_spin_unlock_irq(&sem->wait_lock);
timeout = schedule_timeout(timeout);
raw_spin_lock_irq(&sem->wait_lock);
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
locked = writer_trylock(sem);
if (locked)
break;
@@ -309,7 +309,7 @@ down_write_failed(struct ld_semaphore *sem, long count, long timeout)
list_del(&waiter.list);
raw_spin_unlock_irq(&sem->wait_lock);
- __set_task_state(tsk, TASK_RUNNING);
+ __set_current_state(TASK_RUNNING);
/* lock wait may have timed out */
if (!locked)
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 4d1905245c7a..8edf16d82f8c 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -227,7 +227,7 @@ extern void proc_sched_set_task(struct task_struct *p);
extern char ___assert_task_state[1 - 2*!!(
sizeof(TASK_STATE_TO_CHAR_STR)-1 != ilog2(TASK_STATE_MAX)+1)];
-/* Convenience macros for the sake of set_task_state */
+/* Convenience macros for the sake of set_current_state */
#define TASK_KILLABLE (TASK_WAKEKILL | TASK_UNINTERRUPTIBLE)
#define TASK_STOPPED (TASK_WAKEKILL | __TASK_STOPPED)
#define TASK_TRACED (TASK_WAKEKILL | __TASK_TRACED)
@@ -254,17 +254,6 @@ extern char ___assert_task_state[1 - 2*!!(
#ifdef CONFIG_DEBUG_ATOMIC_SLEEP
-#define __set_task_state(tsk, state_value) \
- do { \
- (tsk)->task_state_change = _THIS_IP_; \
- (tsk)->state = (state_value); \
- } while (0)
-#define set_task_state(tsk, state_value) \
- do { \
- (tsk)->task_state_change = _THIS_IP_; \
- smp_store_mb((tsk)->state, (state_value)); \
- } while (0)
-
#define __set_current_state(state_value) \
do { \
current->task_state_change = _THIS_IP_; \
@@ -277,20 +266,6 @@ extern char ___assert_task_state[1 - 2*!!(
} while (0)
#else
-
-/*
- * @tsk had better be current, or you get to keep the pieces.
- *
- * The only reason is that computing current can be more expensive than
- * using a pointer that's already available.
- *
- * Therefore, see set_current_state().
- */
-#define __set_task_state(tsk, state_value) \
- do { (tsk)->state = (state_value); } while (0)
-#define set_task_state(tsk, state_value) \
- smp_store_mb((tsk)->state, (state_value))
-
/*
* set_current_state() includes a barrier so that the write of current->state
* is correctly serialised wrt the caller's subsequent test of whether to
diff --git a/kernel/exit.c b/kernel/exit.c
index 8f14b866f9f6..184add6f4bfa 100644
--- a/kernel/exit.c
+++ b/kernel/exit.c
@@ -501,12 +501,12 @@ static void exit_mm(struct task_struct *tsk)
complete(&core_state->startup);
for (;;) {
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
if (!self.task) /* see coredump_finish() */
break;
freezable_schedule();
}
- __set_task_state(tsk, TASK_RUNNING);
+ __set_current_state(TASK_RUNNING);
down_read(&mm->mmap_sem);
}
atomic_inc(&mm->mm_count);
diff --git a/kernel/locking/mutex.c b/kernel/locking/mutex.c
index 9b349619f431..821c1d115974 100644
--- a/kernel/locking/mutex.c
+++ b/kernel/locking/mutex.c
@@ -667,7 +667,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
lock_contended(&lock->dep_map, ip);
- set_task_state(task, state);
+ set_current_state(state);
for (;;) {
/*
* Once we hold wait_lock, we're serialized against
@@ -702,7 +702,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
__mutex_set_flag(lock, MUTEX_FLAG_HANDOFF);
}
- set_task_state(task, state);
+ set_current_state(state);
/*
* Here we order against unlock; we must either see it change
* state back to RUNNING and fall through the next schedule(),
@@ -716,7 +716,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
}
spin_lock_mutex(&lock->wait_lock, flags);
acquired:
- __set_task_state(task, TASK_RUNNING);
+ __set_current_state(TASK_RUNNING);
mutex_remove_waiter(lock, &waiter, task);
if (likely(list_empty(&lock->wait_list)))
@@ -736,7 +736,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
return 0;
err:
- __set_task_state(task, TASK_RUNNING);
+ __set_current_state(TASK_RUNNING);
mutex_remove_waiter(lock, &waiter, task);
spin_unlock_mutex(&lock->wait_lock, flags);
debug_mutex_free_waiter(&waiter);
diff --git a/kernel/locking/rwsem-spinlock.c b/kernel/locking/rwsem-spinlock.c
index 1591f6b3539f..f3c1c0734da6 100644
--- a/kernel/locking/rwsem-spinlock.c
+++ b/kernel/locking/rwsem-spinlock.c
@@ -141,7 +141,7 @@ void __sched __down_read(struct rw_semaphore *sem)
}
tsk = current;
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
/* set up my own style of waitqueue */
waiter.task = tsk;
@@ -158,10 +158,10 @@ void __sched __down_read(struct rw_semaphore *sem)
if (!waiter.task)
break;
schedule();
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
}
- __set_task_state(tsk, TASK_RUNNING);
+ __set_current_state(TASK_RUNNING);
out:
;
}
@@ -220,7 +220,7 @@ int __sched __down_write_common(struct rw_semaphore *sem, int state)
ret = -EINTR;
goto out;
}
- set_task_state(tsk, state);
+ set_current_state(state);
raw_spin_unlock_irqrestore(&sem->wait_lock, flags);
schedule();
raw_spin_lock_irqsave(&sem->wait_lock, flags);
diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index 631506004f9e..45a6afeed2c2 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -254,13 +254,13 @@ struct rw_semaphore __sched *rwsem_down_read_failed(struct rw_semaphore *sem)
/* wait to be given the lock */
while (true) {
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ set_current_state(TASK_UNINTERRUPTIBLE);
if (!waiter.task)
break;
schedule();
}
- __set_task_state(tsk, TASK_RUNNING);
+ __set_current_state(TASK_RUNNING);
return sem;
}
EXPORT_SYMBOL(rwsem_down_read_failed);
diff --git a/kernel/locking/semaphore.c b/kernel/locking/semaphore.c
index b8120abe594b..2f8cdb712b63 100644
--- a/kernel/locking/semaphore.c
+++ b/kernel/locking/semaphore.c
@@ -216,7 +216,7 @@ static inline int __sched __down_common(struct semaphore *sem, long state,
goto interrupted;
if (unlikely(timeout <= 0))
goto timed_out;
- __set_task_state(task, state);
+ __set_current_state(state);
raw_spin_unlock_irq(&sem->lock);
timeout = schedule_timeout(timeout);
raw_spin_lock_irq(&sem->lock);
--
2.6.6
^ permalink raw reply related
* [PATCH 10/20] gpio: pca953x: Add optional reset gpio control
From: Steve Longerbeam @ 2016-12-30 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZG2j4_LwP8KUVBTOtXma75YvYtC6CW1QqYwOm-MOZgHg@mail.gmail.com>
Hi Linus, Lothar,
On 12/30/2016 05:17 AM, Linus Walleij wrote:
> On Thu, Dec 29, 2016 at 11:27 PM, Steve Longerbeam
> <slongerbeam@gmail.com> wrote:
>
>> Add optional reset-gpios pin control. If present, de-assert the
>> specified reset gpio pin to bring the chip out of reset.
>>
>> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Alexandre Courbot <gnurou@gmail.com>
>> Cc: linux-gpio at vger.kernel.org
>> Cc: linux-kernel at vger.kernel.org
> This seems like a separate patch from the other 19 patches so please send it
> separately so I can handle logistics easier in the future.
Ok, I'll send the next version separately.
>
>
>> @@ -133,6 +134,7 @@ struct pca953x_chip {
>> const char *const *names;
>> unsigned long driver_data;
>> struct regulator *regulator;
>> + struct gpio_desc *reset_gpio;
> Why do you even keep this around in the device state container?
>
> As you only use it in the probe() function, use a local variable.
>
> The descriptor will be free():ed by the devm infrastructure anyways.
I think my reasoning for putting the gpio handle into the device
struct was for possibly using it for run-time reset control at some
point. But that could be done later if needed, so I'll go ahead and
make it local.
>> + /* see if we need to de-assert a reset pin */
>> + chip->reset_gpio = devm_gpiod_get_optional(&client->dev,
>> + "reset",
>> + GPIOD_OUT_LOW);
>> + if (IS_ERR(chip->reset_gpio)) {
>> + dev_err(&client->dev, "request for reset pin failed\n");
>> + return PTR_ERR(chip->reset_gpio);
>> + }
> Nice.
>
>> + if (chip->reset_gpio) {
>> + /* bring chip out of reset */
>> + dev_info(&client->dev, "releasing reset\n");
>> + gpiod_set_value(chip->reset_gpio, 0);
>> + }
> Is this really needed given that you set it low in the
> devm_gpiod_get_optional()?
Yep, this is left over from a previous iteration, but it isn't needed now.
I'll remove it.
Steve
^ permalink raw reply
* [PATCH v2] mfd: mc13xxx: Set the irq type.
From: Fabio Estevam @ 2016-12-30 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483112613-18092-1-git-send-email-lilja.magnus@gmail.com>
On Fri, Dec 30, 2016 at 1:43 PM, Magnus Lilja <lilja.magnus@gmail.com> wrote:
> Commit 10f9edaeaa30 ("mfd: mc13xxx: Use regmap irq framework for
> interrupts") removed the passing of the IRQF_TRIGGER_HIGH flag when
> registering the interrupt.
> This commit fixes that problem by setting the IRQF_TRIGGER_HIGH flag in
> case no irq type is set via irqd framework (e.g. device tree). In the
> latter case the irq flag from irqd is used.
>
> Tested on i.MX31 PDK hardware.
>
> Fixes: 10f9edaeaa30 ("mfd: mc13xxx: Use regmap irq framework for interrupts")
> Cc: <stable@vger.kernel.org> # 3.18.x
> Cc: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH v3] ARM: dts: imx6: Disable "weim" node in the dtsi files
From: Joshua Clayton @ 2016-12-30 17:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483092543-14233-1-git-send-email-festevam@gmail.com>
Thanks Fabio.
On 12/30/2016 02:09 AM, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> Commit 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to
> dtsi's") causes the following probe error when the weim node is not
> present on the board dts (such as imx6q-sabresd):
>
> imx-weim 21b8000.weim: Invalid 'ranges' configuration
> imx-weim: probe of 21b8000.weim failed with error -22
>
> There is no need to always enable the "weim" node on mx6. Do the same
> as in the other i.MX dtsi files where "weim" is disabled and only gets
> enabled on a per dts basis.
>
> All the imx6 weim dts users explicitily provide 'status = "okay"', so
> this change has no impact on current imx6 weim users.
>
> If a board does not use the weim driver it will not describe its 'ranges'
> property, so simply disable the 'weim' node in the imx6 dtsi files to
> avoid such probe error message.
>
> Fixes: 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to dtsi's")
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
> Changes since v2:
> - Fix the error message by disabling weim at dtsi level.
>
> arch/arm/boot/dts/imx6qdl.dtsi | 1 +
> arch/arm/boot/dts/imx6sl.dtsi | 1 +
> arch/arm/boot/dts/imx6sx.dtsi | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index 53e6e63..89b834f 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -1100,6 +1100,7 @@
> interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
> fsl,weim-cs-gpr = <&gpr>;
> + status = "disabled";
> };
>
> ocotp: ocotp at 021bc000 {
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index 4fd6de2..19cbd87 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -900,6 +900,7 @@
> reg = <0x021b8000 0x4000>;
> interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
> fsl,weim-cs-gpr = <&gpr>;
> + status = "disabled";
> };
>
> ocotp: ocotp at 021bc000 {
> diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> index 076a30f..10f3330 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -977,6 +977,7 @@
> interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
> fsl,weim-cs-gpr = <&gpr>;
> + status = "disabled";
> };
>
> ocotp: ocotp at 021bc000 {
I like this solution much better!
Joshua
^ permalink raw reply
* [RFC 1/4] mm: remove unused TASK_SIZE_OF()
From: Dmitry Safonov @ 2016-12-30 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230155634.8692-1-dsafonov@virtuozzo.com>
All users of TASK_SIZE_OF(tsk) have migrated to mm->task_size or
TASK_SIZE_MAX since:
commit d696ca016d57 ("x86/fsgsbase/64: Use TASK_SIZE_MAX for
FSBASE/GSBASE upper limits"),
commit a06db751c321 ("pagemap: check permissions and capabilities at
open time"),
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Helge Deller <deller@gmx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-mips at linux-mips.org
Cc: linux-parisc at vger.kernel.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-s390 at vger.kernel.org
Cc: sparclinux at vger.kernel.org
Signed-off-by: Dmitry Safonov <dsafonov@virtuozzo.com>
---
arch/arm64/include/asm/memory.h | 2 --
arch/mips/include/asm/processor.h | 3 ---
arch/parisc/include/asm/processor.h | 3 +--
arch/powerpc/include/asm/processor.h | 3 +--
arch/s390/include/asm/processor.h | 3 +--
arch/sparc/include/asm/processor_64.h | 3 ---
arch/x86/include/asm/processor.h | 2 --
include/linux/sched.h | 4 ----
8 files changed, 3 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index bfe632808d77..329bb4fd543c 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -80,8 +80,6 @@
#define TASK_SIZE_32 UL(0x100000000)
#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
TASK_SIZE_32 : TASK_SIZE_64)
-#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
- TASK_SIZE_32 : TASK_SIZE_64)
#else
#define TASK_SIZE TASK_SIZE_64
#endif /* CONFIG_COMPAT */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 95b8c471f572..c2827a5507d4 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -73,9 +73,6 @@ extern unsigned int vced_count, vcei_count;
#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
#define STACK_TOP_MAX TASK_SIZE64
-#define TASK_SIZE_OF(tsk) \
- (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
-
#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
#endif
diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index a3661ee6b060..8b51ddae8e4a 100644
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -32,8 +32,7 @@
#define HAVE_ARCH_PICK_MMAP_LAYOUT
-#define TASK_SIZE_OF(tsk) ((tsk)->thread.task_size)
-#define TASK_SIZE TASK_SIZE_OF(current)
+#define TASK_SIZE (current->thread.task_size)
#define TASK_UNMAPPED_BASE (current->thread.map_base)
#define DEFAULT_TASK_SIZE32 (0xFFF00000UL)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1ba814436c73..04e575ead590 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -111,9 +111,8 @@ void release_thread(struct task_struct *);
*/
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
-#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
+#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
TASK_SIZE_USER32 : TASK_SIZE_USER64)
-#define TASK_SIZE TASK_SIZE_OF(current)
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 6bca916a5ba0..c53e8e2a51ac 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -89,10 +89,9 @@ extern void execve_tail(void);
* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
*/
-#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
(1UL << 30) : (1UL << 41))
-#define TASK_SIZE TASK_SIZE_OF(current)
+#define TASK_SIZE (current->mm->context.asce_limit)
#define TASK_MAX_SIZE (1UL << 53)
#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm/processor_64.h
index 6448cfc8292f..6ce1a75d7a24 100644
--- a/arch/sparc/include/asm/processor_64.h
+++ b/arch/sparc/include/asm/processor_64.h
@@ -36,9 +36,6 @@
#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
#endif
-#define TASK_SIZE_OF(tsk) \
- (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
- (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
#define TASK_SIZE \
(test_thread_flag(TIF_32BIT) ? \
(1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index eaf100508c36..090a860b792a 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -819,8 +819,6 @@ static inline void spin_lock_prefetch(const void *x)
#define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
IA32_PAGE_OFFSET : TASK_SIZE_MAX)
-#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
- IA32_PAGE_OFFSET : TASK_SIZE_MAX)
#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX TASK_SIZE_MAX
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 4d1905245c7a..7a2e2f3f38a3 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -3610,10 +3610,6 @@ static inline void inc_syscw(struct task_struct *tsk)
}
#endif
-#ifndef TASK_SIZE_OF
-#define TASK_SIZE_OF(tsk) TASK_SIZE
-#endif
-
#ifdef CONFIG_MEMCG
extern void mm_update_next_owner(struct mm_struct *mm);
#else
--
2.11.0
^ permalink raw reply related
* [RFC 0/4] x86: keep TASK_SIZE in sync with mm->task_size
From: Dmitry Safonov @ 2016-12-30 15:56 UTC (permalink / raw)
To: linux-arm-kernel
At this moment, we have following task_size-related things:
- TASK_SIZE_OF() macro, which is unused;
- current->mm->task_size which is used in half and TASK_SIZE() macro
which is used in the other half of code
- TIF_ADDR32, which is used to detect 32-bit address space and is
x86-specific, where some other arches misused TIF_32BIT
- personality ADDR_LIMIT_32BIT, which is used on arm/alpha
- ADDR_LIMIT_3GB, which is x86-specific and can be used to change
running task's TASK_SIZE 3GB <-> 4GB
This patches set removes unused definition of TASK_SIZE_OF (1),
defines TASK_SIZE macro as current->mm->task_size (3).
I would suggest define TASK_SIZE this way in generic version,
but currently I test it only on x86.
It also frees thread info flag (2) and adds arch_prctl()
on x86_64 to get/set current virtual address space size - as
it's needed by now only for CRIU, hide it under CHECKPOINT_RESTORE
config.
Hope those patches will help to clean task_size-related code
at least a bit (and helps me to restore vaddr limits).
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: x86 at kernel.org
Dmitry Safonov (4):
mm: remove unused TASK_SIZE_OF()
x86/thread_info: kill TIF_ADDR32 in favour of ADDR_LIMIT_32BIT
x86/mm: define TASK_SIZE as current->mm->task_size
x86/arch_prctl: add ARCH_{GET,SET}_TASK_SIZE
arch/arm64/include/asm/memory.h | 2 --
arch/mips/include/asm/processor.h | 3 ---
arch/parisc/include/asm/processor.h | 3 +--
arch/powerpc/include/asm/processor.h | 3 +--
arch/s390/include/asm/processor.h | 3 +--
arch/sparc/include/asm/processor_64.h | 3 ---
arch/x86/include/asm/elf.h | 7 +++++--
arch/x86/include/asm/processor.h | 19 +++++++++----------
arch/x86/include/asm/thread_info.h | 4 +---
arch/x86/include/uapi/asm/prctl.h | 3 +++
arch/x86/kernel/process_64.c | 17 +++++++++++++++--
arch/x86/kernel/sys_x86_64.c | 4 ++--
arch/x86/um/asm/segment.h | 2 +-
arch/x86/xen/mmu.c | 4 ++--
fs/exec.c | 17 +++++++++++------
include/linux/sched.h | 4 ----
16 files changed, 52 insertions(+), 46 deletions(-)
--
2.11.0
^ permalink raw reply
* [GIT PULL] ARM: exynos: Late mach/soc for v4.10
From: Krzysztof Kozlowski @ 2016-12-30 15:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482003132-8844-1-git-send-email-krzk@kernel.org>
On Sat, Dec 17, 2016 at 09:32:12PM +0200, Krzysztof Kozlowski wrote:
> Hi,
>
>
> After our discussions about not-breaking out-of-tree DTB with SCU
> change in DeviceTree, I prepared an updated pull request without
> the questioned changes.
>
> Ten days ago I prepared a tag, pushed it... and apparently forgot to send pull
> request. At least, I don't have such email in my outbox. Dunno.
>
> So let's send it now, better late then never. With just few commits (without
> the DT SCU changes). These were sitting in the next for very long.
>
Any comments on this? I guess it won't come as late-late-4.10, so can
you pull it for v4.11?
Best regards,
Krzysztof
> Best regards,
> Krzysztof
>
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-soc-4.10-2
>
> for you to fetch changes up to da6b21e97e39d42f90ab490ce7b54a0fe2c3fe35:
>
> ARM: Drop fixed 200 Hz timer requirement from Samsung platforms (2016-12-07 18:42:11 +0200)
>
> ----------------------------------------------------------------
> Samsung mach/soc update for v4.10:
> 1. Minor cleanup in smp_operations.
> 2. Another step in switching s3c24xx to new DMA API.
> 3. Drop fixed requirement for HZ=200 on Samsung platforms.
>
> ----------------------------------------------------------------
> Krzysztof Kozlowski (1):
> ARM: Drop fixed 200 Hz timer requirement from Samsung platforms
>
> Pankaj Dubey (1):
> ARM: EXYNOS: Remove smp_init_cpus hook from platsmp.c
>
> Sylwester Nawrocki (1):
> ARM: S3C24XX: Add DMA slave maps for remaining s3c24xx SoCs
>
> arch/arm/Kconfig | 3 +-
> arch/arm/mach-exynos/platsmp.c | 31 -----------------
> arch/arm/mach-s3c24xx/common.c | 76 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 77 insertions(+), 33 deletions(-)
^ permalink raw reply
* [PATCH v2] mfd: mc13xxx: Set the irq type.
From: Magnus Lilja @ 2016-12-30 15:43 UTC (permalink / raw)
To: linux-arm-kernel
Commit 10f9edaeaa30 ("mfd: mc13xxx: Use regmap irq framework for
interrupts") removed the passing of the IRQF_TRIGGER_HIGH flag when
registering the interrupt.
This commit fixes that problem by setting the IRQF_TRIGGER_HIGH flag in
case no irq type is set via irqd framework (e.g. device tree). In the
latter case the irq flag from irqd is used.
Tested on i.MX31 PDK hardware.
Fixes: 10f9edaeaa30 ("mfd: mc13xxx: Use regmap irq framework for interrupts")
Cc: <stable@vger.kernel.org> # 3.18.x
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
---
Changes from v1 (which was part of a patch series):
- Now uses irqd_-functions to check if irq type is defined
- Added Fixes: and Cc: to stable kernel.
drivers/mfd/mc13xxx-core.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index d7f54e4..e1757ea 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -15,6 +15,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
+#include <linux/irq.h>
#include "mc13xxx.h"
@@ -410,6 +411,7 @@ int mc13xxx_common_init(struct device *dev)
struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
u32 revision;
int i, ret;
+ unsigned int flags;
mc13xxx->dev = dev;
@@ -440,7 +442,11 @@ int mc13xxx_common_init(struct device *dev)
mc13xxx->irq_chip.irqs = mc13xxx->irqs;
mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
- ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
+ flags = irqd_get_trigger_type(irq_get_irq_data(mc13xxx->irq));
+ flags = (flags == IRQ_TYPE_NONE) ? IRQF_TRIGGER_HIGH : flags;
+
+ ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq,
+ IRQF_ONESHOT | flags,
0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
if (ret)
return ret;
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] mmc: sdhci-iproc: Increase max_blk_size for bcm2835
From: Stefan Wahren @ 2016-12-30 15:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483111474-29907-1-git-send-email-stefan.wahren@i2se.com>
According to the BCM2835 datasheet the maximum block size for the
eMMC module is restricted to the internal data FIFO which is 1024 byte.
But this is still an improvement to the default of 512 byte.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
drivers/mmc/host/sdhci-iproc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
index 30b3fdf..3275d49 100644
--- a/drivers/mmc/host/sdhci-iproc.c
+++ b/drivers/mmc/host/sdhci-iproc.c
@@ -218,7 +218,9 @@ static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
static const struct sdhci_iproc_data bcm2835_data = {
.pdata = &sdhci_bcm2835_pltfm_data,
- .caps = SDHCI_CAN_VDD_330 |
+ .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
+ & SDHCI_MAX_BLOCK_MASK) |
+ SDHCI_CAN_VDD_330 |
SDHCI_CAN_DO_HISPD,
.caps1 = SDHCI_DRIVER_TYPE_A |
SDHCI_DRIVER_TYPE_C,
--
1.7.9.5
^ permalink raw reply related
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