* [PATCH] arm64/dts/ls2080a-rdb: remove disable status of pca9547
From: Shawn Guo @ 2017-01-02 9:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482213787-27814-1-git-send-email-meng.yi@nxp.com>
On Tue, Dec 20, 2016 at 02:03:07PM +0800, Meng Yi wrote:
> pca9547 won't probed since its status property is disabled.
> while there are devices connected to it, we need remove status
> property to let ds3232 and adt7461 probed correctly.
>
> Signed-off-by: Meng Yi <meng.yi@nxp.com>
Changed subject prefix to 'arm64: dts: ls2080a-rdb: ', and applied the
patch.
Shawn
^ permalink raw reply
* [BISECTED] v4.9: OMAP MMC regression
From: Peter Ujfalusi @ 2017-01-02 9:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161222205843.md4uggwyegcfuk3j@raspberrypi-2.musicnaut.iki.fi>
On 12/22/2016 10:58 PM, Aaro Koskinen wrote:
> Hi,
>
> On Sun, Dec 18, 2016 at 12:01:21AM +0200, Aaro Koskinen wrote:
>> OMAP MMC is silently missing when booting v4.9 on Nokia 770 (OMAP1).
>>
>> Bisected to:
>>
>> commit 2d1a9a946faebfedd660a1f1c2b90984fff41f91
>> Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
>> Date: Wed Jul 20 11:50:29 2016 +0300
>>
>> dmaengine: omap-dma: Dynamically allocate memory for lch_map
>>
>> Reveting the commit makes MMC to appear and work again...
>
> This commit basically reduces dma_requests count to 17 (from 127)
> on OMAP1.
>
> This cannot be correct, since OMAP1 MMC is using requests (from
> omap1_init_mmc):
>
> rx_req = 22;
> tx_req = 21;
> [...]
> rx_req = 55;
> tx_req = 54;
>
> MMC probe will fail because omap_dma_filter_fn() will fail during
> dma_request_chan().
>
> I think 2d1a9a946faebfedd660a1f1c2b90984fff41f91 should be reverted.
> I cannot anymore boot my 770 with >= 4.9 kernel.
I rather fix this instead of reverting the commit, I will send a patch
today for this.
--
P?ter
^ permalink raw reply
* [PATCH] mtd: nand: Update dependency of IFC for LS1021A
From: Boris Brezillon @ 2017-01-02 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201612291704.0tMw9Uis%fengguang.wu@intel.com>
Hi Alison,
On Thu, 29 Dec 2016 17:52:37 +0800
kbuild test robot <lkp@intel.com> wrote:
> Hi Alison,
>
> [auto build test WARNING on mtd/master]
> [also build test WARNING on v4.10-rc1 next-20161224]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Alison-Wang/mtd-nand-Update-dependency-of-IFC-for-LS1021A/20161229-125233
> base: git://git.infradead.org/linux-mtd.git master
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
> reproduce:
> wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm
>
> All warnings (new ones prefixed by >>):
>
> warning: (MTD_NAND_FSL_IFC) selects FSL_IFC which has unmet direct dependencies (MEMORY && (FSL_SOC || ARCH_LAYERSCAPE))
Do you have another patch adding the '||?SOC_LS1021A' dependency on
FSL_IFC? If so, please send both patches in the same series.
Thanks,
Boris
^ permalink raw reply
* [PATCH 3/8] ARM: dts: armada-388-clearfog: Utilize new DSA binding
From: Neil Armstrong @ 2017-01-02 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102022249.10657-4-f.fainelli@gmail.com>
Hi Florian,
On 01/02/2017 03:22 AM, Florian Fainelli wrote:
> Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net:
> dsa: Document new binding"). The legacy binding node is kept included, but is
> marked disabled.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/boot/dts/armada-388-clearfog.dts | 65 +++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
> index 71ce201c903e..35207aa1f4ec 100644
> --- a/arch/arm/boot/dts/armada-388-clearfog.dts
> +++ b/arch/arm/boot/dts/armada-388-clearfog.dts
> @@ -351,6 +351,8 @@
> };
>
> dsa at 0 {
> + status = "okay";
I think you wanted "disabled" here !
> +
> compatible = "marvell,dsa";
> dsa,ethernet = <ð1>;
> dsa,mii-bus = <&mdio>;
> @@ -444,3 +446,66 @@
> status = "disabled";
> };
> };
[...]
Neil
^ permalink raw reply
* [PATCH v4 1/4] ARM: da850: fix infinite loop in clk_set_rate()
From: Sekhar Nori @ 2017-01-02 8:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481124138-27337-2-git-send-email-bgolaszewski@baylibre.com>
On Wednesday 07 December 2016 08:52 PM, Bartosz Golaszewski wrote:
> The aemif clock is added twice to the lookup table in da850.c. This
> breaks the children list of pll0_sysclk3 as we're using the same list
> links in struct clk. When calling clk_set_rate(), we get stuck in
> propagate_rate().
>
> Create a separate clock for nand, inheriting the rate of the aemif
> clock and retrieve it in the davinci_nand module.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Applied to fixes branch. The prefix for mach-davinci patches is "ARM:
davinci: ...". I fixed it up when applying. Please take care for future.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v6 6/8] IIO: add STM32 timer trigger driver
From: Benjamin Gaignard @ 2017-01-02 8:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <70f15b07-55d9-bd0d-25c7-712363e30974@kernel.org>
2016-12-30 22:12 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
> On 09/12/16 14:15, Benjamin Gaignard wrote:
>> Timers IPs can be used to generate triggers for other IPs like
>> DAC, ADC or other timers.
>> Each trigger may result of timer internals signals like counter enable,
>> reset or edge, this configuration could be done through "master_mode"
>> device attribute.
>>
>> A timer device could be triggered by other timers, we use the trigger
>> name and is_stm32_iio_timer_trigger() function to distinguish them
>> and configure IP input switch.
>>
>> Timer may also decide on which event (edge, level) they could
>> be activated by a trigger, this configuration is done by writing in
>> "slave_mode" device attribute.
>>
>> Since triggers could also be used by DAC or ADC their names are defined
>> in include/ nux/iio/timer/stm32-timer-trigger.h so those IPs will be able
>> to configure themselves in valid_trigger function
>>
>> Trigger have a "sampling_frequency" attribute which allow to configure
>> timer sampling frequency without using PWM interface
>>
>> version 5:
>> - simplify tables of triggers
>> - only create an IIO device when needed
>>
>> version 4:
>> - get triggers configuration from "reg" in DT
>> - add tables of triggers
>> - sampling frequency is enable/disable when writing in trigger
>> sampling_frequency attribute
>> - no more use of interruptions
>>
>> version 3:
>> - change compatible to "st,stm32-timer-trigger"
>> - fix attributes access right
>> - use string instead of int for master_mode and slave_mode
>> - document device attributes in sysfs-bus-iio-timer-stm32
>>
>> version 2:
>> - keep only one compatible
>> - use st,input-triggers-names and st,output-triggers-names
>> to know which triggers are accepted and/or create by the device
> Firstly, sorry it has taken me so long to get back to this.
>
> I'm still not keen on this use of iio_device elements just to act as
> glue between triggers. I think we need to work out a more light weight
> way to do this. As you are only using them for validation and to provide
> somewhere to hang the control attibutes off, there is nothing stopping us
> moving that over to the iio_trigger instead which would avoid the messy
> duality going on here.
I have add an iio_device because each hardware can generate multiple
triggers (up to 5: trgo, ch 1...4) and slave_mode attribute will impact all the
triggers of a device. For me it was making sense to centralize that in an
iio_device rather than having an attribute "shared" (from hardware
point of view)
on multiple triggers.
Since master_mode attribute is only used by trgo and not impact ch1...4
triggers I will move it to trigger instead of the iio_device.
I also wanted to be able to connect triggers on a iio_device as I
could do for an
ADC with a command like 'echo "tim1_trgo" > iio_deviceX/trigger/current_trigger'
If I change that to parent_trigger attribute it change this behavior
and I will have to
duplicated what is done in iio_trigger_write_current() to find and
validate triggers.
> I might still be missing something though!
>
> You would only I think need 3 attributes
>
> parrent_trigger
> and something like your master_mode and slave_mode attributes.
>
> The parrent_trigger would need some validation etc, but if we keep it
> within this driver initially that won't be hard to do. Checking the device
> parent matches will do most of it.
>
> Jonathan
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 55 +++
>> drivers/iio/Kconfig | 2 +-
>> drivers/iio/Makefile | 1 +
>> drivers/iio/timer/Kconfig | 13 +
>> drivers/iio/timer/Makefile | 1 +
>> drivers/iio/timer/stm32-timer-trigger.c | 466 +++++++++++++++++++++
>> drivers/iio/trigger/Kconfig | 1 -
>> include/linux/iio/timer/stm32-timer-trigger.h | 62 +++
>> 8 files changed, 599 insertions(+), 2 deletions(-)
>> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>> create mode 100644 drivers/iio/timer/Kconfig
>> create mode 100644 drivers/iio/timer/Makefile
>> create mode 100644 drivers/iio/timer/stm32-timer-trigger.c
>> create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>> new file mode 100644
>> index 0000000..26583dd
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>> @@ -0,0 +1,55 @@
>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode_available
>> +KernelVersion: 4.10
>> +Contact: benjamin.gaignard at st.com
>> +Description:
>> + Reading returns the list possible master modes which are:
>> + - "reset" : The UG bit from the TIMx_EGR register is used as trigger output (TRGO).
>> + - "enable" : The Counter Enable signal CNT_EN is used as trigger output.
>> + - "update" : The update event is selected as trigger output.
>> + For instance a master timer can then be used as a prescaler for a slave timer.
>> + - "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set.
>> + - "OC1REF" : OC1REF signal is used as trigger output.
>> + - "OC2REF" : OC2REF signal is used as trigger output.
>> + - "OC3REF" : OC3REF signal is used as trigger output.
>> + - "OC4REF" : OC4REF signal is used as trigger output.
>> +
>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode
>> +KernelVersion: 4.10
>> +Contact: benjamin.gaignard at st.com
>> +Description:
>> + Reading returns the current master modes.
>> + Writing set the master mode
>> +
>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode_available
>> +KernelVersion: 4.10
>> +Contact: benjamin.gaignard at st.com
>> +Description:
>> + Reading returns the list possible slave modes which are:
>> + - "disabled" : The prescaler is clocked directly by the internal clock.
>> + - "encoder_1" : Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
>> + - "encoder_2" : Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
>> + - "encoder_3" : Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
>> + on the level of the other input.
>> + - "reset" : Rising edge of the selected trigger input reinitializes the counter
>> + and generates an update of the registers.
>> + - "gated" : The counter clock is enabled when the trigger input is high.
>> + The counter stops (but is not reset) as soon as the trigger becomes low.
>> + Both start and stop of the counter are controlled.
>> + - "trigger" : The counter starts at a rising edge of the trigger TRGI (but it is not
>> + reset). Only the start of the counter is controlled.
>> + - "external_clock": Rising edges of the selected trigger (TRGI) clock the counter.
>> +
>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode
>> +KernelVersion: 4.10
>> +Contact: benjamin.gaignard at st.com
>> +Description:
>> + Reading returns the current slave mode.
>> + Writing set the slave mode
>> +
>> +What: /sys/bus/iio/devices/triggerX/sampling_frequency
>> +KernelVersion: 4.10
>> +Contact: benjamin.gaignard at st.com
>> +Description:
>> + Reading returns the current sampling frequency.
>> + Writing an value different of 0 set and start sampling.
>> + Writing 0 stop sampling.
>> diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
>> index 6743b18..2de2a80 100644
>> --- a/drivers/iio/Kconfig
>> +++ b/drivers/iio/Kconfig
>> @@ -90,5 +90,5 @@ source "drivers/iio/potentiometer/Kconfig"
>> source "drivers/iio/pressure/Kconfig"
>> source "drivers/iio/proximity/Kconfig"
>> source "drivers/iio/temperature/Kconfig"
>> -
>> +source "drivers/iio/timer/Kconfig"
>> endif # IIO
>> diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
>> index 87e4c43..b797c08 100644
>> --- a/drivers/iio/Makefile
>> +++ b/drivers/iio/Makefile
>> @@ -32,4 +32,5 @@ obj-y += potentiometer/
>> obj-y += pressure/
>> obj-y += proximity/
>> obj-y += temperature/
>> +obj-y += timer/
>> obj-y += trigger/
>> diff --git a/drivers/iio/timer/Kconfig b/drivers/iio/timer/Kconfig
>> new file mode 100644
>> index 0000000..e3c21f2
>> --- /dev/null
>> +++ b/drivers/iio/timer/Kconfig
>> @@ -0,0 +1,13 @@
>> +#
>> +# Timers drivers
>> +
>> +menu "Timers"
>> +
>> +config IIO_STM32_TIMER_TRIGGER
>> + tristate "STM32 Timer Trigger"
>> + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST
>> + select IIO_TRIGGERED_EVENT
>> + help
>> + Select this option to enable STM32 Timer Trigger
>> +
>> +endmenu
>> diff --git a/drivers/iio/timer/Makefile b/drivers/iio/timer/Makefile
>> new file mode 100644
>> index 0000000..4ad95ec9
>> --- /dev/null
>> +++ b/drivers/iio/timer/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_IIO_STM32_TIMER_TRIGGER) += stm32-timer-trigger.o
>> diff --git a/drivers/iio/timer/stm32-timer-trigger.c b/drivers/iio/timer/stm32-timer-trigger.c
>> new file mode 100644
>> index 0000000..8d16e8f
>> --- /dev/null
>> +++ b/drivers/iio/timer/stm32-timer-trigger.c
>> @@ -0,0 +1,466 @@
>> +/*
>> + * Copyright (C) STMicroelectronics 2016
>> + *
>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>> + *
>> + * License terms: GNU General Public License (GPL), version 2
>> + */
>> +
>> +#include <linux/iio/iio.h>
>> +#include <linux/iio/sysfs.h>
>> +#include <linux/iio/timer/stm32-timer-trigger.h>
>> +#include <linux/iio/trigger.h>
>> +#include <linux/iio/triggered_event.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/mfd/stm32-timers.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define MAX_TRIGGERS 6
>> +#define MAX_VALIDS 5
>> +
>> +/* List the triggers created by each timer */
>> +static const void *triggers_table[][MAX_TRIGGERS] = {
>> + { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
>> + { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
>> + { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
>> + { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
>> + { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
>> + { TIM6_TRGO,},
>> + { TIM7_TRGO,},
>> + { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
>> + { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
>> + { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
>> +};
>> +
>> +/* List the triggers accepted by each timer */
>> +static const void *valids_table[][MAX_VALIDS] = {
>> + { TIM5_TRGO, TIM2_TRGO, TIM4_TRGO, TIM3_TRGO,},
>> + { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
>> + { TIM1_TRGO, TIM8_TRGO, TIM5_TRGO, TIM4_TRGO,},
>> + { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
>> + { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
>> + { }, /* timer 6 */
>> + { }, /* timer 7 */
>> + { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
>> + { TIM2_TRGO, TIM3_TRGO,},
>> + { TIM4_TRGO, TIM5_TRGO,},
>> +};
>> +
>> +struct stm32_timer_trigger {
>> + struct device *dev;
>> + struct regmap *regmap;
>> + struct clk *clk;
>> + u32 max_arr;
>> + const void *triggers;
>> + const void *valids;
>> +};
>> +
>> +static int stm32_timer_start(struct stm32_timer_trigger *priv,
>> + unsigned int frequency)
>> +{
>> + unsigned long long prd, div;
>> + int prescaler = 0;
>> + u32 ccer, cr1;
>> +
>> + /* Period and prescaler values depends of clock rate */
>> + div = (unsigned long long)clk_get_rate(priv->clk);
>> +
>> + do_div(div, frequency);
>> +
>> + prd = div;
>> +
>> + /*
>> + * Increase prescaler value until we get a result that fit
>> + * with auto reload register maximum value.
>> + */
>> + while (div > priv->max_arr) {
>> + prescaler++;
>> + div = prd;
>> + do_div(div, (prescaler + 1));
>> + }
>> + prd = div;
>> +
>> + if (prescaler > MAX_TIM_PSC) {
>> + dev_err(priv->dev, "prescaler exceeds the maximum value\n");
>> + return -EINVAL;
>> + }
>> +
>> + /* Check if nobody else use the timer */
>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>> + if (ccer & TIM_CCER_CCXE)
>> + return -EBUSY;
>> +
>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>> + if (!(cr1 & TIM_CR1_CEN))
>> + clk_enable(priv->clk);
>> +
>> + regmap_write(priv->regmap, TIM_PSC, prescaler);
>> + regmap_write(priv->regmap, TIM_ARR, prd - 1);
>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
>> +
>> + /* Force master mode to update mode */
>> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
>> +
>> + /* Make sure that registers are updated */
>> + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
>> +
>> + /* Enable controller */
>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
>> +
>> + return 0;
>> +}
>> +
>> +static void stm32_timer_stop(struct stm32_timer_trigger *priv)
>> +{
>> + u32 ccer, cr1;
>> +
>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>> + if (ccer & TIM_CCER_CCXE)
>> + return;
>> +
>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>> + if (cr1 & TIM_CR1_CEN)
>> + clk_disable(priv->clk);
>> +
>> + /* Stop timer */
>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
>> + regmap_write(priv->regmap, TIM_PSC, 0);
>> + regmap_write(priv->regmap, TIM_ARR, 0);
>> +}
>> +
>> +static ssize_t stm32_tt_store_frequency(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + struct iio_trigger *trig = to_iio_trigger(dev);
>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>> + unsigned int freq;
>> + int ret;
>> +
>> + ret = kstrtouint(buf, 10, &freq);
>> + if (ret)
>> + return ret;
>> +
>> + if (freq == 0) {
>> + stm32_timer_stop(priv);
>> + } else {
>> + ret = stm32_timer_start(priv, freq);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return len;
>> +}
>> +
>> +static ssize_t stm32_tt_read_frequency(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct iio_trigger *trig = to_iio_trigger(dev);
>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>> + u32 psc, arr, cr1;
>> + unsigned long long freq = 0;
>> +
>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>> + regmap_read(priv->regmap, TIM_PSC, &psc);
>> + regmap_read(priv->regmap, TIM_ARR, &arr);
>> +
>> + if (psc && arr && (cr1 & TIM_CR1_CEN)) {
>> + freq = (unsigned long long)clk_get_rate(priv->clk);
>> + do_div(freq, psc);
>> + do_div(freq, arr);
>> + }
>> +
>> + return sprintf(buf, "%d\n", (unsigned int)freq);
>> +}
>> +
>> +static IIO_DEV_ATTR_SAMP_FREQ(0660,
>> + stm32_tt_read_frequency,
>> + stm32_tt_store_frequency);
>> +
>> +static struct attribute *stm32_trigger_attrs[] = {
>> + &iio_dev_attr_sampling_frequency.dev_attr.attr,
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group stm32_trigger_attr_group = {
>> + .attrs = stm32_trigger_attrs,
>> +};
>> +
>> +static const struct attribute_group *stm32_trigger_attr_groups[] = {
>> + &stm32_trigger_attr_group,
>> + NULL,
>> +};
>> +
>> +static char *master_mode_table[] = {
>> + "reset",
>> + "enable",
>> + "update",
>> + "compare_pulse",
>> + "OC1REF",
>> + "OC2REF",
>> + "OC3REF",
>> + "OC4REF"
>> +};
>> +
>> +static ssize_t stm32_tt_show_master_mode(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>> + u32 cr2;
>> +
>> + regmap_read(priv->regmap, TIM_CR2, &cr2);
>> + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
>> +
>> + return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
>> +}
>> +
>> +static ssize_t stm32_tt_store_master_mode(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
>> + if (!strncmp(master_mode_table[i], buf,
>> + strlen(master_mode_table[i]))) {
>> + regmap_update_bits(priv->regmap, TIM_CR2,
>> + TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
>> + return len;
>> + }
>> + }
>> +
>> + return -EINVAL;
>> +}
>> +
>> +static IIO_CONST_ATTR(master_mode_available,
>> + "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
>> +
>> +static IIO_DEVICE_ATTR(master_mode, 0660,
>> + stm32_tt_show_master_mode,
>> + stm32_tt_store_master_mode,
>> + 0);
>> +
>> +static char *slave_mode_table[] = {
>> + "disabled",
>> + "encoder_1",
>> + "encoder_2",
>> + "encoder_3",
>> + "reset",
>> + "gated",
>> + "trigger",
>> + "external_clock",
>> +};
>> +
>> +static ssize_t stm32_tt_show_slave_mode(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>> + u32 smcr;
>> +
>> + regmap_read(priv->regmap, TIM_SMCR, &smcr);
>> + smcr &= TIM_SMCR_SMS;
>> +
>> + return snprintf(buf, PAGE_SIZE, "%s\n", slave_mode_table[smcr]);
>> +}
>> +
>> +static ssize_t stm32_tt_store_slave_mode(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(slave_mode_table); i++) {
>> + if (!strncmp(slave_mode_table[i], buf,
>> + strlen(slave_mode_table[i]))) {
>> + regmap_update_bits(priv->regmap,
>> + TIM_SMCR, TIM_SMCR_SMS, i);
>> + return len;
>> + }
>> + }
>> +
>> + return -EINVAL;
>> +}
>> +
>> +static IIO_CONST_ATTR(slave_mode_available,
>> +"disabled encoder_1 encoder_2 encoder_3 reset gated trigger external_clock");
>> +
>> +static IIO_DEVICE_ATTR(slave_mode, 0660,
>> + stm32_tt_show_slave_mode,
>> + stm32_tt_store_slave_mode,
>> + 0);
>> +
>> +static struct attribute *stm32_timer_attrs[] = {
>> + &iio_dev_attr_master_mode.dev_attr.attr,
>> + &iio_const_attr_master_mode_available.dev_attr.attr,
>> + &iio_dev_attr_slave_mode.dev_attr.attr,
>> + &iio_const_attr_slave_mode_available.dev_attr.attr,
>> + NULL,
>> +};
>> +
>> +static const struct attribute_group stm32_timer_attr_group = {
>> + .attrs = stm32_timer_attrs,
>> +};
>> +
>> +static const struct iio_trigger_ops timer_trigger_ops = {
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
>> +{
>> + int ret;
>> + const char * const *cur = priv->triggers;
>> +
>> + while (cur && *cur) {
>> + struct iio_trigger *trig;
>> +
>> + trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
>> + if (!trig)
>> + return -ENOMEM;
>> +
>> + trig->dev.parent = priv->dev->parent;
>> + trig->ops = &timer_trigger_ops;
>> + trig->dev.groups = stm32_trigger_attr_groups;
>> + iio_trigger_set_drvdata(trig, priv);
>> +
>> + ret = devm_iio_trigger_register(priv->dev, trig);
>> + if (ret)
>> + return ret;
>> + cur++;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * is_stm32_timer_trigger
>> + * @trig: trigger to be checked
>> + *
>> + * return true if the trigger is a valid stm32 iio timer trigger
>> + * either return false
>> + */
>> +bool is_stm32_timer_trigger(struct iio_trigger *trig)
>> +{
>> + return (trig->ops == &timer_trigger_ops);
>> +}
>> +EXPORT_SYMBOL(is_stm32_timer_trigger);
>> +
>> +static int stm32_validate_trigger(struct iio_dev *indio_dev,
>> + struct iio_trigger *trig)
>> +{
>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>> + const char * const *cur = priv->valids;
>> + unsigned int i = 0;
>> +
>> + if (!is_stm32_timer_trigger(trig))
>> + return -EINVAL;
>> +
>> + while (cur && *cur) {
>> + if (!strncmp(trig->name, *cur, strlen(trig->name))) {
>> + regmap_update_bits(priv->regmap,
>> + TIM_SMCR, TIM_SMCR_TS,
>> + i << TIM_SMCR_TS_SHIFT);
>> + return 0;
>> + }
>> + cur++;
>> + i++;
>> + }
>> +
>> + return -EINVAL;
>> +}
>> +
>> +static const struct iio_info stm32_trigger_info = {
>> + .driver_module = THIS_MODULE,
>> + .validate_trigger = stm32_validate_trigger,
>> + .attrs = &stm32_timer_attr_group,
>> +};
>> +
>> +static struct stm32_timer_trigger *stm32_setup_iio_device(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev;
>> + int ret;
>> +
>> + indio_dev = devm_iio_device_alloc(dev,
>> + sizeof(struct stm32_timer_trigger));
>> + if (!indio_dev)
>> + return NULL;
>> +
>> + indio_dev->name = dev_name(dev);
>> + indio_dev->dev.parent = dev;
>> + indio_dev->info = &stm32_trigger_info;
>> + indio_dev->modes = INDIO_EVENT_TRIGGERED;
>> + indio_dev->num_channels = 0;
>> + indio_dev->dev.of_node = dev->of_node;
>> +
>> + ret = devm_iio_device_register(dev, indio_dev);
>> + if (ret)
>> + return NULL;
>> +
>> + return iio_priv(indio_dev);
>> +}
>> +
>> +static int stm32_timer_trigger_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct stm32_timer_trigger *priv;
>> + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
>> + unsigned int index;
>> + int ret;
>> +
>> + if (of_property_read_u32(dev->of_node, "reg", &index))
>> + return -EINVAL;
>> +
>> + if (index >= ARRAY_SIZE(triggers_table))
>> + return -EINVAL;
>> +
>> + /* Create an IIO device only if we have triggers to be validated */
>> + if (*valids_table[index])
>> + priv = stm32_setup_iio_device(dev);
>
> I still don't like this. Really feels like we shouldn't be creating an
> iio device with all the bagage that carries just to allow us to do the
> trigger trees. We ought to have a much more light weight solution for this
> functionality - we aren't typically even using the interrupt tree stuff
> that the triggers for devices are all really about.
>
> A simpler approach of allowing each trigger the option of a parent seems like
> it would be cleaner. Could be done entirely within this driver in the first
> instance. Basically it would just look like your master and slave attributes
> but have those under triggerX not iio:deviceX.
>
> We can work out how to make it more generic later - including perhaps the
> option to trigger from triggers outside this driver, using some parallel
> infrastructure to the device triggering.
>
>
>> + else
>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> +
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + priv->dev = dev;
>> + priv->regmap = ddata->regmap;
>> + priv->clk = ddata->clk;
>> + priv->max_arr = ddata->max_arr;
>> + priv->triggers = triggers_table[index];
>> + priv->valids = valids_table[index];
>> +
>> + ret = stm32_setup_iio_triggers(priv);
>> + if (ret)
>> + return ret;
>> +
>> + platform_set_drvdata(pdev, priv);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id stm32_trig_of_match[] = {
>> + { .compatible = "st,stm32-timer-trigger", },
>> + { /* end node */ },
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
>> +
>> +static struct platform_driver stm32_timer_trigger_driver = {
>> + .probe = stm32_timer_trigger_probe,
>> + .driver = {
>> + .name = "stm32-timer-trigger",
>> + .of_match_table = stm32_trig_of_match,
>> + },
>> +};
>> +module_platform_driver(stm32_timer_trigger_driver);
>> +
>> +MODULE_ALIAS("platform: stm32-timer-trigger");
>> +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig
>> index 809b2e7..f2af4fe 100644
>> --- a/drivers/iio/trigger/Kconfig
>> +++ b/drivers/iio/trigger/Kconfig
>> @@ -46,5 +46,4 @@ config IIO_SYSFS_TRIGGER
>>
>> To compile this driver as a module, choose M here: the
>> module will be called iio-trig-sysfs.
>> -
> Clean this up.
ok
>> endmenu
>> diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h
>> new file mode 100644
>> index 0000000..55535ae
>> --- /dev/null
>> +++ b/include/linux/iio/timer/stm32-timer-trigger.h
>> @@ -0,0 +1,62 @@
>> +/*
>> + * Copyright (C) STMicroelectronics 2016
>> + *
>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>> + *
>> + * License terms: GNU General Public License (GPL), version 2
>> + */
>> +
>> +#ifndef _STM32_TIMER_TRIGGER_H_
>> +#define _STM32_TIMER_TRIGGER_H_
>> +
>> +#define TIM1_TRGO "tim1_trgo"
>> +#define TIM1_CH1 "tim1_ch1"
>> +#define TIM1_CH2 "tim1_ch2"
>> +#define TIM1_CH3 "tim1_ch3"
>> +#define TIM1_CH4 "tim1_ch4"
>> +
>> +#define TIM2_TRGO "tim2_trgo"
>> +#define TIM2_CH1 "tim2_ch1"
>> +#define TIM2_CH2 "tim2_ch2"
>> +#define TIM2_CH3 "tim2_ch3"
>> +#define TIM2_CH4 "tim2_ch4"
>> +
>> +#define TIM3_TRGO "tim3_trgo"
>> +#define TIM3_CH1 "tim3_ch1"
>> +#define TIM3_CH2 "tim3_ch2"
>> +#define TIM3_CH3 "tim3_ch3"
>> +#define TIM3_CH4 "tim3_ch4"
>> +
>> +#define TIM4_TRGO "tim4_trgo"
>> +#define TIM4_CH1 "tim4_ch1"
>> +#define TIM4_CH2 "tim4_ch2"
>> +#define TIM4_CH3 "tim4_ch3"
>> +#define TIM4_CH4 "tim4_ch4"
>> +
>> +#define TIM5_TRGO "tim5_trgo"
>> +#define TIM5_CH1 "tim5_ch1"
>> +#define TIM5_CH2 "tim5_ch2"
>> +#define TIM5_CH3 "tim5_ch3"
>> +#define TIM5_CH4 "tim5_ch4"
>> +
>> +#define TIM6_TRGO "tim6_trgo"
>> +
>> +#define TIM7_TRGO "tim7_trgo"
>> +
>> +#define TIM8_TRGO "tim8_trgo"
>> +#define TIM8_CH1 "tim8_ch1"
>> +#define TIM8_CH2 "tim8_ch2"
>> +#define TIM8_CH3 "tim8_ch3"
>> +#define TIM8_CH4 "tim8_ch4"
>> +
>> +#define TIM9_TRGO "tim9_trgo"
>> +#define TIM9_CH1 "tim9_ch1"
>> +#define TIM9_CH2 "tim9_ch2"
>> +
>> +#define TIM12_TRGO "tim12_trgo"
>> +#define TIM12_CH1 "tim12_ch1"
>> +#define TIM12_CH2 "tim12_ch2"
>> +
>> +bool is_stm32_timer_trigger(struct iio_trigger *trig);
>> +
>> +#endif
>>
>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [RFC, PATCHv2 29/29] mm, x86: introduce RLIMIT_VADDR
From: Arnd Bergmann @ 2017-01-02 8:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161227015413.187403-30-kirill.shutemov@linux.intel.com>
On Tuesday, December 27, 2016 4:54:13 AM CET Kirill A. Shutemov wrote:
> This patch introduces new rlimit resource to manage maximum virtual
> address available to userspace to map.
>
> On x86, 5-level paging enables 56-bit userspace virtual address space.
> Not all user space is ready to handle wide addresses. It's known that
> at least some JIT compilers use high bit in pointers to encode their
> information. It collides with valid pointers with 5-level paging and
> leads to crashes.
>
> The patch aims to address this compatibility issue.
>
> MM would use min(RLIMIT_VADDR, TASK_SIZE) as upper limit of virtual
> address available to map by userspace.
>
> The default hard limit will be RLIM_INFINITY, which basically means that
> TASK_SIZE limits available address space.
>
> The soft limit will also be RLIM_INFINITY everywhere, but the machine
> with 5-level paging enabled. In this case, soft limit would be
> (1UL << 47) - PAGE_SIZE. It?s current x86-64 TASK_SIZE_MAX with 4-level
> paging which known to be safe
>
> New rlimit resource would follow usual semantics with regards to
> inheritance: preserved on fork(2) and exec(2). This has potential to
> break application if limits set too wide or too narrow, but this is not
> uncommon for other resources (consider RLIMIT_DATA or RLIMIT_AS).
>
> As with other resources you can set the limit lower than current usage.
> It would affect only future virtual address space allocations.
>
> Use-cases for new rlimit:
>
> - Bumping the soft limit to RLIM_INFINITY, allows current process all
> its children to use addresses above 47-bits.
>
> - Bumping the soft limit to RLIM_INFINITY after fork(2), but before
> exec(2) allows the child to use addresses above 47-bits.
>
> - Lowering the hard limit to 47-bits would prevent current process all
> its children to use addresses above 47-bits, unless a process has
> CAP_SYS_RESOURCES.
>
> - It?s also can be handy to lower hard or soft limit to arbitrary
> address. User-mode emulation in QEMU may lower the limit to 32-bit
> to emulate 32-bit machine on 64-bit host.
>
> TODO:
> - port to non-x86;
>
> Not-yet-signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> Cc: linux-api at vger.kernel.org
This seems to nicely address the same problem on arm64, which has
run into the same issue due to the various page table formats
that can currently be chosen at compile time.
I don't see how this interacts with the existing
PER_LINUX32/PER_LINUX32_3GB personality flags, but I assume you have
either already thought of that, or we can come up with a good way
to define what happens when conflicting settings are applied.
The two reasonable ways I can think of are to either use the
minimum of the two limits, or to make the personality syscall
set the soft rlimit and use whatever limit was last set.
Arnd
^ permalink raw reply
* [PATCH] pinctrl: qcom: msm8660: rename some SDC1->SDC4
From: Linus Walleij @ 2017-01-02 8:42 UTC (permalink / raw)
To: linux-arm-kernel
These four pins are for SDC4, not SDC1. They are grouped for
SDC4 later in the file so this must be a typo.
Cc: Bj?rn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-msm8660.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c
index 5591d093bf78..bb71dd1e6279 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
@@ -193,9 +193,9 @@ static const struct pinctrl_pin_desc msm8660_pins[] = {
PINCTRL_PIN(171, "GPIO_171"),
PINCTRL_PIN(172, "GPIO_172"),
- PINCTRL_PIN(173, "SDC1_CLK"),
- PINCTRL_PIN(174, "SDC1_CMD"),
- PINCTRL_PIN(175, "SDC1_DATA"),
+ PINCTRL_PIN(173, "SDC4_CLK"),
+ PINCTRL_PIN(174, "SDC4_CMD"),
+ PINCTRL_PIN(175, "SDC4_DATA"),
PINCTRL_PIN(176, "SDC3_CLK"),
PINCTRL_PIN(177, "SDC3_CMD"),
PINCTRL_PIN(178, "SDC3_DATA"),
--
2.9.3
^ permalink raw reply related
* [PATCH 28/37] ARM: dts: imx6ul-geam: Correct license text
From: Michael Trimarchi @ 2017-01-02 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214235746.7108-29-alexandre.belloni@free-electrons.com>
On Thu, Dec 15, 2016 at 12:57:37AM +0100, Alexandre Belloni wrote:
> The license test has been mangled at some point then copy pasted across
> multiple files. Restore it to what it should be.
> Note that this is not intended as a license change.
>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Matteo Lisi <matteo.lisi@engicam.com>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
> ---
> arch/arm/boot/dts/imx6ul-geam-kit.dts | 10 +++++-----
> arch/arm/boot/dts/imx6ul-geam.dtsi | 10 +++++-----
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6ul-geam-kit.dts b/arch/arm/boot/dts/imx6ul-geam-kit.dts
> index 4c4af76143e3..142e60cab65f 100644
> --- a/arch/arm/boot/dts/imx6ul-geam-kit.dts
> +++ b/arch/arm/boot/dts/imx6ul-geam-kit.dts
> @@ -11,17 +11,17 @@
> * modify it under the terms of the GNU General Public License
> * version 2 as published by the Free Software Foundation.
> *
> - * This file is distributed in the hope that it will be useful
> + * This file is distributed in the hope that it will be useful,
> * but WITHOUT ANY WARRANTY; without even the implied warranty of
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * Or, alternatively
> + * Or, alternatively,
> *
> * b) Permission is hereby granted, free of charge, to any person
> * obtaining a copy of this software and associated documentation
> * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use
> + * restriction, including without limitation the rights to use,
> * copy, modify, merge, publish, distribute, sublicense, and/or
> * sell copies of the Software, and to permit persons to whom the
> * Software is furnished to do so, subject to the following
> @@ -30,11 +30,11 @@
> * The above copyright notice and this permission notice shall be
> * included in all copies or substantial portions of the Software.
> *
> - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> diff --git a/arch/arm/boot/dts/imx6ul-geam.dtsi b/arch/arm/boot/dts/imx6ul-geam.dtsi
> index 64eb9ed59b9c..940aef67313b 100644
> --- a/arch/arm/boot/dts/imx6ul-geam.dtsi
> +++ b/arch/arm/boot/dts/imx6ul-geam.dtsi
> @@ -11,17 +11,17 @@
> * modify it under the terms of the GNU General Public License
> * version 2 as published by the Free Software Foundation.
> *
> - * This file is distributed in the hope that it will be useful
> + * This file is distributed in the hope that it will be useful,
> * but WITHOUT ANY WARRANTY; without even the implied warranty of
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * Or, alternatively
> + * Or, alternatively,
> *
> * b) Permission is hereby granted, free of charge, to any person
> * obtaining a copy of this software and associated documentation
> * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use
> + * restriction, including without limitation the rights to use,
> * copy, modify, merge, publish, distribute, sublicense, and/or
> * sell copies of the Software, and to permit persons to whom the
> * Software is furnished to do so, subject to the following
> @@ -30,11 +30,11 @@
> * The above copyright notice and this permission notice shall be
> * included in all copies or substantial portions of the Software.
> *
> - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> --
> 2.10.2
>
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply
* [PATCH 23/37] ARM: dts: imx6q-icore-rqs: Correct license text
From: Michael Trimarchi @ 2017-01-02 8:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214235746.7108-24-alexandre.belloni@free-electrons.com>
On Thu, Dec 15, 2016 at 12:57:32AM +0100, Alexandre Belloni wrote:
> The license test has been mangled at some point then copy pasted across
> multiple files. Restore it to what it should be.
> Note that this is not intended as a license change.
>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> arch/arm/boot/dts/imx6q-icore-rqs.dts | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
> diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts
> index 005318865f66..45be9745c0e6 100644
> --- a/arch/arm/boot/dts/imx6q-icore-rqs.dts
> +++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts
> @@ -10,17 +10,17 @@
> * modify it under the terms of the GNU General Public License
> * version 2 as published by the Free Software Foundation.
> *
> - * This file is distributed in the hope that it will be useful
> + * This file is distributed in the hope that it will be useful,
> * but WITHOUT ANY WARRANTY; without even the implied warranty of
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * Or, alternatively
> + * Or, alternatively,
> *
> * b) Permission is hereby granted, free of charge, to any person
> * obtaining a copy of this software and associated documentation
> * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use
> + * restriction, including without limitation the rights to use,
> * copy, modify, merge, publish, distribute, sublicense, and/or
> * sell copies of the Software, and to permit persons to whom the
> * Software is furnished to do so, subject to the following
> @@ -29,11 +29,11 @@
> * The above copyright notice and this permission notice shall be
> * included in all copies or substantial portions of the Software.
> *
> - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> --
> 2.10.2
>
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply
* [PATCH 16/37] ARM: dts: imx6qdl-icore-rqs: Correct license text
From: Michael Trimarchi @ 2017-01-02 8:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214235746.7108-17-alexandre.belloni@free-electrons.com>
On Thu, Dec 15, 2016 at 12:57:25AM +0100, Alexandre Belloni wrote:
> The license test has been mangled at some point then copy pasted across
> multiple files. Restore it to what it should be.
> Note that this is not intended as a license change.
>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Uwe Kleine-K?nig <uwe@kleine-koenig.org>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
> diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
> index d5c3aa88adbe..ed60d72b06b9 100644
> --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
> @@ -10,17 +10,17 @@
> * modify it under the terms of the GNU General Public License
> * version 2 as published by the Free Software Foundation.
> *
> - * This file is distributed in the hope that it will be useful
> + * This file is distributed in the hope that it will be useful,
> * but WITHOUT ANY WARRANTY; without even the implied warranty of
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * Or, alternatively
> + * Or, alternatively,
> *
> * b) Permission is hereby granted, free of charge, to any person
> * obtaining a copy of this software and associated documentation
> * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use
> + * restriction, including without limitation the rights to use,
> * copy, modify, merge, publish, distribute, sublicense, and/or
> * sell copies of the Software, and to permit persons to whom the
> * Software is furnished to do so, subject to the following
> @@ -29,11 +29,11 @@
> * The above copyright notice and this permission notice shall be
> * included in all copies or substantial portions of the Software.
> *
> - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> --
> 2.10.2
>
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply
* [3/3] ARM: da850: Add ti, da830-uart compatible for serial ports
From: Sekhar Nori @ 2017-01-02 8:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2982bdd0-0997-f4a7-71c3-9d232237cc23@ti.com>
On Thursday 22 December 2016 09:36 PM, Franklin S Cooper Jr wrote:
>
>
> On 12/20/2016 02:23 PM, David Lechner wrote:
>> TI DA8xx/OMAPL13x/AM17xx/AM18xx SoCs have extra UART registers beyond
>
> Similar comment about adding Keystone SoCs to the list of SoCs.
>
>> the standard 8250 registers, so we need a new compatible string to
>> indicate this. Also, at least one of these registers uses the full 32
>> bits, so we need to specify reg-io-width in addition to reg-shift.
>>
>> "ns16550a" is left in the compatible specification since it does work
>> as long as the bootloader configures the SoC UART power management
>> registers.
>>
>> Signed-off-by: David Lechner <david@lechnology.com>
>> ---
>> arch/arm/boot/dts/da850.dtsi | 9 ++++++---
>
> Similar changes should be made to the various Keystone dtsi files.
That will be a different patch though since the two changes will go
through different trees. And I strongly suspect David does not have
access to a keystone board. So it will have to be done by someone at TI.
Thanks,
Sekhar
^ permalink raw reply
* [v2, 1/4] ARM: davinci: da8xx-dt: Add ti-aemif lookup for clock matching
From: Sekhar Nori @ 2017-01-02 8:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <33cf2e96-6551-df6a-8a30-bf2c3aeabfee@lechnology.com>
On Saturday 31 December 2016 06:22 AM, David Lechner wrote:
> On 08/10/2016 06:00 AM, Karl Beldan wrote:
>> Many davinci boards (da830 and da850 families) don't have their clocks
>> in DT yet and won't be successful in getting an unnamed aemif clock
>> without explicitly registering them via clk_lookups, failing the
>> ti-aemif memory driver probe.
>>
>> The current aemif lookup entry resolving to the same clock:
>> 'CLK(NULL, "aemif", &aemif_clk)'
>> remains, as it is currently used (davinci_nand is getting a named clock
>> "aemif").
>>
>> This change will allow to switch from the mach-davinci aemif code to
>> the ti-aemif memory driver.
>>
>> Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
>> ---
>
> FYI, I can't boot LEGO MINDSTORMS EV3 (AM1908) with a v4.9 mainline
> kernel. I did a git bisect and traced it down to this patch. I'm
> guessing that simply reverting it will break other things.
>
> The problem is that &aemif_clk is a node in a linked list and points to
> itself, which creates an infinite loop when looking up the usb clocks
> that are later in the list.
>
> I thought there was a patch to fix this properly from one of the Bay
> Libre guys to fix this already, but I can't seem to find it at the
> moment. When it is found, it would be good to have it applied to the 4.9
> stable and 4.10 mainline trees.
Yes, a patch was submitted. It is pending in my queue since I need to do
a few experiments myself to determine if its the best solution possible.
Thanks for the heads-up on need to mark it for v4.9 stable. Will do.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v3 1/3] ARM: dts: imx6: Add Savageboard common file
From: Milo Kim @ 2017-01-02 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102074422.GH20956@dragon>
On 01/02/2017 04:44 PM, Shawn Guo wrote:
> On Mon, Jan 02, 2017 at 04:31:07PM +0900, Milo Kim wrote:
>>
>> On 01/02/2017 03:52 PM, Shawn Guo wrote:
>>>> + panel {
>>>> + compatible = "avic, tm097tdh02", "hannstar,hsd100pxn1";
>>> "avic, tm097tdh02" is an undocumented compatible.
>>>
>>
>> AVIC TM097TDH02 panel is compatible with Hannstar HSD100PXN1, so I
>> reuse it. It's the same rule as the usage of imx6q I2C controller.
>>
>> i2c2: i2c at 021a4000 {
>> compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
>> };
>
> Forgot to ask, is the "avic" Shanghai AVIC Optoelectronics Co., Ltd. as
> documented in vendor-prefixes.txt?
Yes, right.
Best regards,
Milo
^ permalink raw reply
* [PATCH v3 1/3] ARM: dts: imx6: Add Savageboard common file
From: Milo Kim @ 2017-01-02 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102074155.GG20956@dragon>
On 01/02/2017 04:41 PM, Shawn Guo wrote:
> On Mon, Jan 02, 2017 at 04:31:07PM +0900, Milo Kim wrote:
>>
>> On 01/02/2017 03:52 PM, Shawn Guo wrote:
>>>> + panel {
>>>> + compatible = "avic, tm097tdh02", "hannstar,hsd100pxn1";
>>> "avic, tm097tdh02" is an undocumented compatible.
>>>
>>
>> AVIC TM097TDH02 panel is compatible with Hannstar HSD100PXN1, so I
>> reuse it. It's the same rule as the usage of imx6q I2C controller.
>>
>> i2c2: i2c at 021a4000 {
>> compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
>> };
>
> Okay. Drop the space in the middle of the compatible.
Thanks for all your feedback. Please let me submit the v4 later.
Best regards,
Milo
^ permalink raw reply
* [PATCH v3 1/3] ARM: dts: imx6: Add Savageboard common file
From: Shawn Guo @ 2017-01-02 7:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <450d89c7-7459-6369-3a07-cc60d70de0db@gmail.com>
On Mon, Jan 02, 2017 at 04:31:07PM +0900, Milo Kim wrote:
>
> On 01/02/2017 03:52 PM, Shawn Guo wrote:
> >>+ panel {
> >>+ compatible = "avic, tm097tdh02", "hannstar,hsd100pxn1";
> >"avic, tm097tdh02" is an undocumented compatible.
> >
>
> AVIC TM097TDH02 panel is compatible with Hannstar HSD100PXN1, so I
> reuse it. It's the same rule as the usage of imx6q I2C controller.
>
> i2c2: i2c at 021a4000 {
> compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
> };
Forgot to ask, is the "avic" Shanghai AVIC Optoelectronics Co., Ltd. as
documented in vendor-prefixes.txt?
Shawn
^ permalink raw reply
* [PATCH v3 1/3] ARM: dts: imx6: Add Savageboard common file
From: Shawn Guo @ 2017-01-02 7:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <450d89c7-7459-6369-3a07-cc60d70de0db@gmail.com>
On Mon, Jan 02, 2017 at 04:31:07PM +0900, Milo Kim wrote:
>
> On 01/02/2017 03:52 PM, Shawn Guo wrote:
> >>+ panel {
> >>+ compatible = "avic, tm097tdh02", "hannstar,hsd100pxn1";
> >"avic, tm097tdh02" is an undocumented compatible.
> >
>
> AVIC TM097TDH02 panel is compatible with Hannstar HSD100PXN1, so I
> reuse it. It's the same rule as the usage of imx6q I2C controller.
>
> i2c2: i2c at 021a4000 {
> compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
> };
Okay. Drop the space in the middle of the compatible.
Shawn
^ permalink raw reply
* [PATCH v3 2/3] ARM: dts: imx6: Support Savageboard dual
From: Milo Kim @ 2017-01-02 7:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102070302.GD20956@dragon>
On 01/02/2017 04:03 PM, Shawn Guo wrote:
>> + model = "Poslab SavageBoard Dual";
>> + compatible = "poslab,imx6dl-savageboard", "fsl,imx6dl";
> It seems that 'poslab' should be added to
> Documentation/devicetree/bindings/vendor-prefixes.txt
Ah, right. Thanks for the review!
Best regards,
Milo
^ permalink raw reply
* [PATCH v3 1/3] ARM: dts: imx6: Add Savageboard common file
From: Milo Kim @ 2017-01-02 7:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102065239.GC20956@dragon>
On 01/02/2017 03:52 PM, Shawn Guo wrote:
>> + panel {
>> + compatible = "avic, tm097tdh02", "hannstar,hsd100pxn1";
> "avic, tm097tdh02" is an undocumented compatible.
>
AVIC TM097TDH02 panel is compatible with Hannstar HSD100PXN1, so I reuse
it. It's the same rule as the usage of imx6q I2C controller.
i2c2: i2c at 021a4000 {
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
};
Best regards,
Milo
^ permalink raw reply
* [PATCH] ARM: imx: remove unused device definitions
From: Shawn Guo @ 2017-01-02 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161216090533.2195228-1-arnd@arndb.de>
On Fri, Dec 16, 2016 at 10:05:08AM +0100, Arnd Bergmann wrote:
> I stumbled over these during build testing, they are evidently
> not referenced anywhere any more.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Applied, thanks.
^ permalink raw reply
* [PATCH] mtd: nand: fsmc: remove stale non-DT probe path
From: Viresh Kumar @ 2017-01-02 7:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482060895-26838-1-git-send-email-linus.walleij@linaro.org>
On 18-12-16, 12:34, Linus Walleij wrote:
> The FSMC driver has an execution path and a header file in
> <linux/mtd/fsmc.h> that serves to support passing in platform
> data through board files, albeit no upstream users of this
> mechanism exist.
>
> The header file also contains function headers for functions that
> do not exist in the kernel.
>
> Delete this and move the platform data struct, parsing and
> handling into the driver, assume we are using OF and make the
> driver depend on OF, remove the ifdefs making that optional.
>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vipin Kumar <vipin.kumar@st.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/mtd/nand/Kconfig | 1 +
> drivers/mtd/nand/fsmc_nand.c | 153 ++++++++++++++++++++++++++++++++++++------
> include/linux/mtd/fsmc.h | 156 -------------------------------------------
> 3 files changed, 133 insertions(+), 177 deletions(-)
> delete mode 100644 include/linux/mtd/fsmc.h
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* [PATCH] cpufreq: s3c64xx: remove incorrect __init annotation
From: Viresh Kumar @ 2017-01-02 7:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161216090625.2235668-1-arnd@arndb.de>
On 16-12-16, 10:06, Arnd Bergmann wrote:
> s3c64xx_cpufreq_config_regulator is incorrectly annotated
> as __init, since the caller is also not init:
>
> WARNING: vmlinux.o(.text+0x92fe1c): Section mismatch in reference from the function s3c64xx_cpufreq_driver_init() to the function .init.text:s3c64xx_cpufreq_config_regulator()
>
> With modern gcc versions, the function gets inline, so we don't
> see the warning, this only happens with gcc-4.6 and older.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/cpufreq/s3c64xx-cpufreq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/s3c64xx-cpufreq.c b/drivers/cpufreq/s3c64xx-cpufreq.c
> index 176e84cc3991..0cb9040eca49 100644
> --- a/drivers/cpufreq/s3c64xx-cpufreq.c
> +++ b/drivers/cpufreq/s3c64xx-cpufreq.c
> @@ -107,7 +107,7 @@ static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
> }
>
> #ifdef CONFIG_REGULATOR
> -static void __init s3c64xx_cpufreq_config_regulator(void)
> +static void s3c64xx_cpufreq_config_regulator(void)
> {
> int count, v, i, found;
> struct cpufreq_frequency_table *freq;
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* [PATCH v3 2/3] ARM: dts: imx6: Support Savageboard dual
From: Shawn Guo @ 2017-01-02 7:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161209010436.7994-3-woogyom.kim@gmail.com>
On Fri, Dec 09, 2016 at 10:04:35AM +0900, Milo Kim wrote:
> Common savageboard DT file is used for board support.
> Specify this dtb file for i.MX6Q build.
>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6dl-savageboard.dts | 50 ++++++++++++++++++++++++++++++++
> 2 files changed, 51 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6dl-savageboard.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index c558ba7..64660c7 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -348,6 +348,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6dl-sabreauto.dtb \
> imx6dl-sabrelite.dtb \
> imx6dl-sabresd.dtb \
> + imx6dl-savageboard.dtb \
> imx6dl-ts4900.dtb \
> imx6dl-tx6dl-comtft.dtb \
> imx6dl-tx6s-8034.dtb \
> diff --git a/arch/arm/boot/dts/imx6dl-savageboard.dts b/arch/arm/boot/dts/imx6dl-savageboard.dts
> new file mode 100644
> index 0000000..2cac30d
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-savageboard.dts
> @@ -0,0 +1,50 @@
> +/*
> + * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-savageboard.dtsi"
> +
> +/ {
> + model = "Poslab SavageBoard Dual";
> + compatible = "poslab,imx6dl-savageboard", "fsl,imx6dl";
It seems that 'poslab' should be added to
Documentation/devicetree/bindings/vendor-prefixes.txt.
Shawn
> +};
> --
> 2.9.3
>
^ permalink raw reply
* [RFC 1/4] mm: remove unused TASK_SIZE_OF()
From: Heiko Carstens @ 2017-01-02 6:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230155634.8692-2-dsafonov@virtuozzo.com>
On Fri, Dec 30, 2016 at 06:56:31PM +0300, Dmitry Safonov wrote:
> All users of TASK_SIZE_OF(tsk) have migrated to mm->task_size or
> TASK_SIZE_MAX since:
> commit d696ca016d57 ("x86/fsgsbase/64: Use TASK_SIZE_MAX for
> FSBASE/GSBASE upper limits"),
> commit a06db751c321 ("pagemap: check permissions and capabilities at
> open time"),
>
> Signed-off-by: Dmitry Safonov <dsafonov@virtuozzo.com>
> ---
...
> diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
> index 6bca916a5ba0..c53e8e2a51ac 100644
> --- a/arch/s390/include/asm/processor.h
> +++ b/arch/s390/include/asm/processor.h
> @@ -89,10 +89,9 @@ extern void execve_tail(void);
> * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
> */
>
> -#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
> #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
> (1UL << 30) : (1UL << 41))
> -#define TASK_SIZE TASK_SIZE_OF(current)
> +#define TASK_SIZE (current->mm->context.asce_limit)
> #define TASK_MAX_SIZE (1UL << 53)
>
> #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
FWIW, for the s390 part:
Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com>
^ permalink raw reply
* [PATCH v3 1/3] ARM: dts: imx6: Add Savageboard common file
From: Shawn Guo @ 2017-01-02 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161209010436.7994-2-woogyom.kim@gmail.com>
On Fri, Dec 09, 2016 at 10:04:34AM +0900, Milo Kim wrote:
> * Memory
> memblock for DDR3 1GB
>
> * Regulator
> 3.3V for panel and backlight.
>
> * Display
> Enable HDMI and LVDS panel. Savageboard supports AVIC TM097TDH02 panel
> which is compatible with Hannstar HSD100PXN1, so reuse it.
>
> * Clock
> The commit d28be499c45e6 is applied to support LVDS and HDMI output
> simultaneously.
>
> * Pinmux
> eMMC, ethernet, HDMI, I2C, power button, PWM, SD card and UART.
>
> * Others
> Enable ethernet, UART1 debug, USB host, USDHC3 for microSD card and
> USDHC4 for built-in eMMC storage.
>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
> ---
> arch/arm/boot/dts/imx6qdl-savageboard.dtsi | 262 +++++++++++++++++++++++++++++
> 1 file changed, 262 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-savageboard.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi
> new file mode 100644
> index 0000000..a7a7e1d
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi
> @@ -0,0 +1,262 @@
> +/*
> + * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
The copyright text needs to be corrected as below.
https://patchwork.kernel.org/patch/9475057/
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + memory at 10000000 {
> + device_type = "memory";
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + backlight: panel_bl {
The node name should be as generic as possible, while label name can be
specific. That said, the following one should be better.
panel_bl: backlight
> + compatible = "pwm-backlight";
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <4>;
> + power-supply = <®_3p3v>;
> + pwms = <&pwm1 0 10000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> + power {
> + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
> + label = "Power Button";
> + linux,code = <KEY_POWER>;
> + wakeup-source;
> + };
> + };
> +
> + panel {
> + compatible = "avic, tm097tdh02", "hannstar,hsd100pxn1";
"avic, tm097tdh02" is an undocumented compatible.
> + backlight = <&backlight>;
> + power-supply = <®_3p3v>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&lvds0_out>;
> + };
> + };
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +};
> +
> +&clks {
> + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
> + <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> +};
> +
> +&fec {
> + phy-mode = "rgmii";
> + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + status = "okay";
> +};
> +
> +&hdmi {
> + ddc-i2c-bus = <&i2c2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi_tx_cec>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +};
> +
> +&ldb {
> + status = "okay";
> +
> + lvds-channel at 0 {
> + reg = <0>;
> + status = "okay";
> +
> + port at 4 {
> + reg = <4>;
> +
> + lvds0_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> +};
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + status = "okay";
> +};
> +
> +/* SD card */
> +&usdhc3 {
> + bus-width = <4>;
> + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sd>;
> + status = "okay";
> +};
> +
> +/* eMMC */
> +&usdhc4 {
> + bus-width = <8>;
> + keep-power-in-suspend;
> + no-1-8-v;
> + non-removable;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_emmc>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_emmc: emmcgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
> + /* PHY reset */
> + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
> + >;
> + };
> +
> + pinctrl_hdmi_tx_cec: hdmitxcecgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpiokeysgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1
> + >;
> + };
The pinctrl entries are well sorted alphabetically except this one.
Shawn
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_sd: sdgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + /* CD pin */
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + >;
> + };
> +};
> --
> 2.9.3
>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox