* [PATCH] DTS: MCCMON6: IMX: Provide support for iMX6Q based Liebherr mccmon6 board
From: Lukasz Majewski @ 2017-01-02 14:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <610d3784-ee2e-c213-2a8c-6db6d7af578b@mentor.com>
Hi Vladimir,
Thank you for review. Comments without my remarks have been applied
already.
> Hello Lukasz,
>
> On 12/27/2016 01:19 AM, Lukasz Majewski wrote:
> > Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
>
> please add a commit message with a short description of the change.
>
> Also change subject line to "ARM: dts: imx6q: Add mccmon6 board
> support".
>
> > ---
> > MCCMON6 board support depends on following patches:
> >
> > 1. "video: backlight: pwm_bl: Initialize fb_bl_on[x] and use_count
> > during pwm_backlight_probe()"
> > http://patchwork.ozlabs.org/patch/708844/
> >
> > 2. "pwm: imx: Provide atomic operation for IMX PWM driver"
> > http://patchwork.ozlabs.org/patch/708847/ -
> > http://patchwork.ozlabs.org/patch/708843/
> >
> >
> > ---
> > arch/arm/boot/dts/Makefile | 1 +
> > arch/arm/boot/dts/imx6q-mccmon6.dts | 469
> > ++++++++++++++++++++++++++++++++++++ 2 files changed, 470
> > insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-mccmon6.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index c558ba7..7ce1080 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -382,6 +382,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> > imx6q-h100.dtb \
> > imx6q-hummingboard.dtb \
> > imx6q-icore-rqs.dtb \
> > + imx6q-mccmon6.dtb \
> > imx6q-marsboard.dtb \
>
> Please add a new line preserving alphabetical order.
>
> > imx6q-nitrogen6x.dtb \
> > imx6q-nitrogen6_max.dtb \
> > diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts
> > b/arch/arm/boot/dts/imx6q-mccmon6.dts new file mode 100644
> > index 0000000..7445d01
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
> > @@ -0,0 +1,469 @@
> > +/*
> > + * Copyright 2016
>
> Copyright holder is missing.
>
> > + *
> > + * Author: Lukasz Majewski <l.majewski@majess.pl>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > modify
> > + * it under the terms of the GNU General Public License version 2
> > as
> > + * published by the Free Software Foundation.
> > + *
> > + */
>
> Please add an empty line here to improve readability.
>
> > +/dts-v1/;
>
> Please add an empty line here to improve readability.
>
> > +#include "imx6q.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pwm/pwm.h>
> > +
> > +/ {
> > + model = "Monitor6 i.MX6 Quad Board";
>
> Missing hardware vendor name.
>
> > + compatible = "mccmon6", "fsl,imx6q";
>
> Missing hardware vendor prefix before "mccmon6".
"lwn,mccmon6" ?
>
> > +
> > + memory {
> > + reg = <0x10000000 0x80000000>;
> > + };
> > +
> > + ethernet0 {
> > + status = "okay";
> > + };
>
> It looks like a useless device node, you have a description of &fec
> already.
>
> > +
> > + backlight_lvds: backlight {
> > + compatible = "pwm-backlight";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_display>;
>
> I would recommend to rename "pinctrl_display" to "pinctrl_backlight".
>
> > + pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
>
> This should work when extension to the i.MX PWM driver is merged.
Yes. The PWM -> apply is an ongoing work. But without the PMW patch the
board is also fully operational (with reversed PWM :-) )
>
> > + brightness-levels = < 0 1 2 3 4 5 6
> > 7 8 9
> > + 10 11 12 13 14 15 16
> > 17 18 19
> > + 20 21 22 23 24 25 26
> > 27 28 29
> > + 30 31 32 33 34 35 36
> > 37 38 39
> > + 40 41 42 43 44 45 46
> > 47 48 49
> > + 50 51 52 53 54 55 56
> > 57 58 59
> > + 60 61 62 63 64 65 66
> > 67 68 69
> > + 70 71 72 73 74 75 76
> > 77 78 79
> > + 80 81 82 83 84 85 86
> > 87 88 89
> > + 90 91 92 93 94 95 96
> > 97 98 99
> > + 100 101 102 103 104 105 106
> > 107 108 109
> > + 110 111 112 113 114 115 116
> > 117 118 119
> > + 120 121 122 123 124 125 126
> > 127 128 129
> > + 130 131 132 133 134 135 136
> > 137 138 139
> > + 140 141 142 143 144 145 146
> > 147 148 149
> > + 150 151 152 153 154 155 156
> > 157 158 159
> > + 160 161 162 163 164 165 166
> > 167 168 169
> > + 170 171 172 173 174 175 176
> > 177 178 179
> > + 180 181 182 183 184 185 186
> > 187 188 189
> > + 190 191 192 193 194 195 196
> > 197 198 199
> > + 200 201 202 203 204 205 206
> > 207 208 209
> > + 210 211 212 213 214 215 216
> > 217 218 219
> > + 220 221 222 223 224 225 226
> > 227 228 229
> > + 230 231 232 233 234 235 236
> > 237 238 239
> > + 240 241 242 243 244 245 246
> > 247 248 249
> > + 250 251 252 253 254 255>;
>
> I'm not sure that actually need such a long list of brightness levels.
Such brightness-level property is so verbose on purpose - in this board
we need fine brightness adjustment (harsh environment operation).
>
> > + default-brightness-level = <50>;
> > + enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
> > + };
> > +
> > + reg_lvds: regulator-lvds {
> > + compatible = "regulator-fixed";
> > + regulator-name = "lvds_ppen";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-boot-on;
> > + gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > +
> > + panel-lvds0 {
> > + compatible = "innolux,g121x1-l03";
> > + backlight = <&backlight_lvds>;
> > + power-supply = <®_lvds>;
> > +
> > + port {
> > + panel_in_lvds0: endpoint {
> > + remote-endpoint = <&lvds0_out>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&i2c1 {
> > + clock-frequency = <100000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c1>;
> > + status = "okay";
> > +};
> > +
> > +&i2c2 {
> > + clock-frequency = <100000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c2>;
> > + status = "okay";
> > +
> > + pmic: pfuze100 at 08 {
> > + compatible = "fsl,pfuze100";
> > + reg = <0x08>;
> > +
> > + regulators {
> > + sw1a_reg: sw1ab {
> > + regulator-min-microvolt = <300000>;
> > + regulator-max-microvolt =
> > <1875000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-ramp-delay = <6250>;
> > + };
> > +
> > + sw1c_reg: sw1c {
> > + regulator-min-microvolt = <300000>;
> > + regulator-max-microvolt =
> > <1875000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-ramp-delay = <6250>;
> > + };
> > +
> > + sw2_reg: sw2 {
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt =
> > <3950000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + sw3a_reg: sw3a {
> > + regulator-min-microvolt = <400000>;
> > + regulator-max-microvolt =
> > <1975000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + sw3b_reg: sw3b {
> > + regulator-min-microvolt = <400000>;
> > + regulator-max-microvolt =
> > <1975000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + sw4_reg: sw4 {
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt =
> > <3300000>;
> > + };
> > +
> > + swbst_reg: swbst {
> > + regulator-min-microvolt =
> > <5000000>;
> > + regulator-max-microvolt =
> > <5150000>;
> > + };
> > +
> > + snvs_reg: vsnvs {
> > + regulator-min-microvolt =
> > <1000000>;
> > + regulator-max-microvolt =
> > <3000000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + vref_reg: vrefddr {
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + vgen1_reg: vgen1 {
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt =
> > <1550000>;
> > + };
> > +
> > + vgen2_reg: vgen2 {
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt =
> > <1550000>;
> > + };
> > +
> > + vgen3_reg: vgen3 {
> > + regulator-min-microvolt =
> > <1800000>;
> > + regulator-max-microvolt =
> > <3300000>;
> > + };
> > +
> > + vgen4_reg: vgen4 {
> > + regulator-min-microvolt =
> > <1800000>;
> > + regulator-max-microvolt =
> > <3300000>;
> > + regulator-always-on;
> > + };
> > +
> > + vgen5_reg: vgen5 {
> > + regulator-min-microvolt =
> > <1800000>;
> > + regulator-max-microvolt =
> > <3300000>;
> > + regulator-always-on;
> > + };
> > +
> > + vgen6_reg: vgen6 {
> > + regulator-min-microvolt =
> > <1800000>;
> > + regulator-max-microvolt =
> > <3300000>;
> > + regulator-always-on;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&iomuxc {
> > + pinctrl-names = "default";
> > +
> > + imx6q-mccmon6 {
> > +
>
> Please drop the empty line above.
>
> > + pinctrl_enet: enetgrp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> > +
> > MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> > +
> > MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> > + MX6QDL_PAD_GPIO_16__ENET_REF_CLK
> > 0x4001b0a8
> > +
> > MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
> > + >;
> > + };
> > +
> > + pinctrl_i2c1: i2c1grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> > +
> > MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> > + >;
> > + };
> > +
> > + pinctrl_i2c2: i2c2grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> > +
> > MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> > + >;
> > + };
> > +
> > + pinctrl_uart1: uart1grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> > +
> > MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2: usdhc2grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> > +
> > MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> > +
> > MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> > +
> > MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> > +
> > MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> > +
> > MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> > + >;
> > + };
> > +
> > + pinctrl_usdhc3: usdhc3grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> > +
> > MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> > +
> > MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> > +
> > MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> > +
> > MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> > +
> > MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> > +
> > MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> > +
> > MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> > +
> > MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> > +
> > MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> > +
> > MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
> > + >;
> > + };
> > +
> > + pinctrl_weim_cs0: weimcs0grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
> > + >;
> > + };
> > +
> > + pinctrl_weim_nor: weimnorgrp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
> > +
> > MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
> > +
> > MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
> > +
> > MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
> > +
> > MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
> > +
> > MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
> > +
> > MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
> > +v4.9-release-devel-fast
> > MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
> > +
> > MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
> > +
> > MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
> > +
> > MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
> > +
> > MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
> > +
> > MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
> > + >;
> > + };
> > +
> > + pinctrl_ecspi3: ecspi3grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
> > +
> > MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
> > +
> > MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
> > + >;
> > + };
> > +
> > + pinctrl_ecspi3_cs: ecspi3cs {
> > + fsl,pins = <
> > + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24
> > 0x80000000
> > + >;
> > + };
> > + pinctrl_ecspi3_flwp: ecspi3flwp {
> > + fsl,pins = <
> > + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27
> > 0x80000000
> > + >;
> > + };
> > +
> > + pinctrl_uart4: uart4grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> > +
> > MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> > +
> > MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
> > +
> > MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
> > + >;
> > + };
> > +
> > + pinctrl_display: dispgrp {
> > + fsl,pins = <
> > + /* BLEN_OUT */
> > + MX6QDL_PAD_GPIO_2__GPIO1_IO02
> > 0x1b0b0
> > + /* LVDS_PPEN_OUT */
> > + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19
> > 0x1b0b0
>
> This GPIO should be moved to a pinctrl group of regulator-lvds device
> node.
You mean to provide separate:
pinctrl_reg_lvds: req_lvds_grp {
fsl,pins = <
/* LVDS_PPEN_OUT */
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19
>;
and then
reg_lvds: regulator-lvds {
compatible = "regulator-fixed";
regulator-name = "lvds_ppen";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_lvds>;
gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
>
> > + >;
> > + };
> > +
> > + pinctrl_pwm2: pwm2grp {
> > + fsl,pins = <
> > +
> > MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> > + >;
> > + };
>
> Please sort out all pinctrl_* nodes alphabetically.
>
> > + };
> > +};
> > +
> > +&fec {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_enet>;
> > + phy-mode = "rgmii";
> > + phy-reset-gpios = <&gpio1 27 0>;
>
> GPIO1_27 has no pad configuration in pinctrl_enet.
>
> > + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
> > + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "okay";
> > +};
> > +
> > +&uart1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart1>;
>
> Should you add "uart-has-rtscts" property?
This is a simple "console" uart without rts/cts, so this property is
not needed.
>
> > + status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usdhc2>;
> > + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
>
> bus-width = <4>;
>
> You should consider to add the GPIO1_4 into pinctrl_usdhc2 group.
Added.
>
> > + status = "okay";
> > +};
> > +
> > +&usdhc3 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usdhc3>;
> > + bus-width = <8>;
> > + status = "okay";
>
> No "cd-gpios" property, should you add "non-removable" property then?
Yes, this is the eMMC memory.
>
> > +};
> > +
> > +&weim {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > + ranges = <0 0 0x08000000 0x08000000>;
> > + status = "okay";
> > +
> > + nor at 0,0 {
> > + compatible = "cfi-flash";
> > + reg = <0 0 0x02000000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + bank-width = <2>;
> > + use-advanced-sector-protection;
> > + fsl,weim-cs-timing = <0x00620081 0x00000001
> > 0x1c022000
> > + 0x0000c000 0x1404a38e 0x00000000>;
> > + };
> > +};
> > +
> > +&ecspi3 {
> > + fsl,spi-num-chipselects = <1>;
>
> This property is obsoleted, please remove it.
>
> > + cs-gpios = <&gpio4 24 0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs
> > &pinctrl_ecspi3_flwp>;
> > + status = "okay";
> > +
> > + flash: s25sl032p at 0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "spansion,s25sl032p", "jedec,spi-nor";
> > + spi-max-frequency = <40000000>;
> > + reg = <0>;
> > + };
> > +};
> > +
> > +&uart4 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart4>;
> > + status = "okay";
>
> Should you add "uart-has-rtscts" property?
Yes, this uart supports rts/cts flow controll
>
> > +};
> > +
> > +&ldb {
> > + status = "okay";
> > +
> > + lvds0: lvds-channel at 0 {
> > + fsl,data-mapping = "spwg";
> > + fsl,data-width = <24>;
> > + status = "okay";
> > +
> > + port at 4 {
> > + reg = <4>;
> > +
> > + lvds0_out: endpoint {
> > + remote-endpoint =
> > <&panel_in_lvds0>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&pwm2 {
> > + #pwm-cells = <3>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pwm2>;
> > + status = "okay";
> > +};
> >
>
> Please sort out all device nodes but &iomuxc alphabetically:
>
> * iomuxc
> * ecspi3
> * fec
> * i2c1
> * i2c2
> * ldb
> * pwm2
> * uart1
> * uart4
> * usdhc2
> * usdhc3
> * weim
Ok.
>
> --
> With best wishes,
> Vladimir
Best regards,
?ukasz Majewski
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^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Nicolas Ferre @ 2017-01-02 14:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102113155.GA16373@localhost.localdomain>
Le 02/01/2017 ? 12:31, Richard Cochran a ?crit :
> On Mon, Jan 02, 2017 at 09:36:10AM +0000, Rafal Ozieblo wrote:
>> According Cadence Hardware team:
>> "It is just that some customers prefer to have the time in the descriptors as that is provided per frame.
>> The registers are simply overwritten when a new event frame is transmitted/received and so software could miss it."
>> The question is are you sure that you read timestamp for current frame? (not for the next frame).
>
> AFAICT, having the time stamp in the descriptor is not universally
> supported. Looking at the Xilinx Zynq 7000 TRM, I can't find any
> mention of this.
This is why I proposed to address options incrementally: without
timestamp support in descriptor (this patch series), then adding this
feature in another patch series.
Rafal, this is why Andrei noted that the case covered by this series is
not adapted to GEM-GXL and doesn't address the "timestamp in descriptor"
case.
> This Cadence IP core is a complete disaster.
Well, it evolved and propose several options to different SoC
integrators. This is not something unusual...
I suspect as well that some other network adapters have the same
weakness concerning PTP timestamp in single register as the early
revisions of this IP.
> Unless someone can tell us how this IP works in all of its
> incarnations, this series is going nowhere.
We're already as v4 (thanks to your fruitful contributions BTW) for this
series and will try to add features for other IP options & revisions
incrementally.
I suspect that Rafal tend to jump too quickly to the latest IP revisions
and add more options to this series: let's not try to pour too much
things into this code right now.
FYI, Andrei will be back online next week.
Regards,
--
Nicolas Ferre
^ permalink raw reply
* [PATCH] ARM: dts: armada388-clearfog: fix SPI flash #size-cells
From: Russell King @ 2017-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
The SPI flash #size-cells is specified in the binding documentation to
have value 1, but we were setting it to zero. This wasn't causing any
problem as we do not list any partitions, but it's worth specifying
correctly if we're going to specify it at all.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 71ce201c903e..3e7c3a6237c3 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -437,7 +437,7 @@
spi-flash at 0 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 0/9] ARM: dts: armada388: Introduce Clearfog Base DT
From: Russell King @ 2017-01-02 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO41M-0007xc-Id@rmk-PC.armlinux.org.uk>
This patch series, based upon the previously submitted fix for the SPI
flash, reworks the Clearfog DT files to add support for the SolidRun
Clearfog Base platform.
The conventional model is now known as the "Clearfog Pro" module, which
has the DSA switch and two PCIe sockets. The base model is a smaller
board without the DSA switch, replacing it with a second copper gigabit
port, and only one PCIe socket.
We retain the original DT file (named armada-388-clearfog.dtb) for
compatibility with existing installations - not only the filename,
but also the board name exposed in userspace.
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/armada-388-clearfog-base.dts | 94 ++++++
arch/arm/boot/dts/armada-388-clearfog-pro.dts | 55 ++++
arch/arm/boot/dts/armada-388-clearfog.dts | 364 ++++-----------------
arch/arm/boot/dts/armada-388-clearfog.dtsi | 310 ++++++++++++++++++
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 21 ++
6 files changed, 548 insertions(+), 298 deletions(-)
create mode 100644 arch/arm/boot/dts/armada-388-clearfog-base.dts
create mode 100644 arch/arm/boot/dts/armada-388-clearfog-pro.dts
create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dtsi
^ permalink raw reply
* [PATCH 1/9] ARM: dts: armada388-clearfog: move SPI flash into microsom
From: Russell King @ 2017-01-02 14:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
The optional SPI flash is fitted to the microsom, not the clearfog
board, so it should be specified in the microsom DTS include file.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 14 ++------------
arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 14 ++++++++++++++
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 3e7c3a6237c3..3980d05f5ece 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -423,9 +423,8 @@
&spi1 {
/*
- * We don't seem to have the W25Q32 on the
- * A1 Rev 2.0 boards, so disable SPI.
- * CS0: W25Q32 (doesn't appear to be present)
+ * Add SPI CS pins for clearfog:
+ * CS0: W25Q32 (not populated on uSOM)
* CS1:
* CS2: mikrobus
*/
@@ -434,13 +433,4 @@
&mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
-
- spi-flash at 0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "w25q32", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <3000000>;
- status = "disabled";
- };
};
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 8c9842237b60..8a84fe3e9c28 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -126,3 +126,17 @@
};
};
+
+&spi1 {
+ /* The microsom has an optional W25Q32 on board, connected to CS0 */
+ pinctrl-0 = <&spi1_pins>;
+
+ w25q32: spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "w25q32", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+ status = "disabled";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/9] ARM: dts: armada388-clearfog: move sdhci pinctrl node to microsom
From: Russell King @ 2017-01-02 14:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Move the SDHCI pinctrl node to the microsom file - the microsom can have
optional eMMC support which uses these same pinctrl settings, so it is
sensible to have these here.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 8 +-------
arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 7 +++++++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 3980d05f5ece..9bf399dd1786 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -257,12 +257,6 @@
marvell,pins = "mpp20";
marvell,function = "gpio";
};
- clearfog_sdhci_pins: clearfog-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
clearfog_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp55";
marvell,function = "spi1";
@@ -300,7 +294,7 @@
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
- pinctrl-0 = <&clearfog_sdhci_pins
+ pinctrl-0 = <µsom_sdhci_pins
&clearfog_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 8a84fe3e9c28..6608657b9994 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -99,6 +99,13 @@
marvell,pins = "mpp45";
marvell,function = "ref";
};
+ /* Optional eMMC */
+ microsom_sdhci_pins: microsom-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28",
+ "mpp37", "mpp38",
+ "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
};
rtc at a3800 {
--
2.7.4
^ permalink raw reply related
* [PATCH 3/9] ARM: dts: armada388-clearfog: split clearfog DTS file
From: Russell King @ 2017-01-02 14:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
There are two versions of the clearfog - a base and a pro model. The
base model has an additional PHY on eth1, replacing the DSA switch on
the pro model. MPP assignments are slightly different. The base model
also omits the second PCIe, and footprint for a PIC microcontroller.
In order to cater for these differences, move all the existing clearfog
support to a dtsi file before starting to modify it, to make the
following changes more clear.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 378 +------------------------
arch/arm/boot/dts/armada-388-clearfog.dtsi | 425 +++++++++++++++++++++++++++++
2 files changed, 427 insertions(+), 376 deletions(-)
create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dtsi
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 9bf399dd1786..c5f2ca5f6144 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -1,5 +1,5 @@
/*
- * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
+ * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2015 Russell King
*
@@ -47,384 +47,10 @@
*/
/dts-v1/;
-#include "armada-388.dtsi"
-#include "armada-38x-solidrun-microsom.dtsi"
+#include "armada-388-clearfog.dtsi"
/ {
model = "SolidRun Clearfog A1";
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
-
- aliases {
- /* So that mvebu u-boot can update the MAC addresses */
- ethernet1 = ð0;
- ethernet2 = ð1;
- ethernet3 = ð2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- soc {
- internal-regs {
- ethernet at 30000 {
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <1>;
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet at 34000 {
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <3>;
- bm,pool-short = <1>;
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- i2c at 11000 {
- /* Is there anything on this? */
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /*
- * PCA9655 GPIO expander, up to 1MHz clock.
- * 0-CON3 CLKREQ#
- * 1-CON3 PERST#
- * 2-CON2 PERST#
- * 3-CON3 W_DISABLE
- * 4-CON2 CLKREQ#
- * 5-USB3 overcurrent
- * 6-USB3 power
- * 7-CON2 W_DISABLE
- * 8-JP4 P1
- * 9-JP4 P4
- * 10-JP4 P5
- * 11-m.2 DEVSLP
- * 12-SFP_LOS
- * 13-SFP_TX_FAULT
- * 14-SFP_TX_DISABLE
- * 15-SFP_MOD_DEF0
- */
- expander0: gpio-expander at 20 {
- /*
- * This is how it should be:
- * compatible = "onnn,pca9655",
- * "nxp,pca9555";
- * but you can't do this because of
- * the way I2C works.
- */
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
-
- pcie1_0_clkreq {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie1.0-clkreq";
- };
- pcie1_0_w_disable {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie1.0-w-disable";
- };
- pcie2_0_clkreq {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie2.0-clkreq";
- };
- pcie2_0_w_disable {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie2.0-w-disable";
- };
- usb3_ilimit {
- gpio-hog;
- gpios = <5 GPIO_ACTIVE_LOW>;
- input;
- line-name = "usb3-current-limit";
- };
- usb3_power {
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb3-power";
- };
- m2_devslp {
- gpio-hog;
- gpios = <11 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "m.2 devslp";
- };
- sfp_los {
- /* SFP loss of signal */
- gpio-hog;
- gpios = <12 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-los";
- };
- sfp_tx_fault {
- /* SFP laser fault */
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-tx-fault";
- };
- sfp_tx_disable {
- /* SFP transmit disable */
- gpio-hog;
- gpios = <14 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "sfp-tx-disable";
- };
- sfp_mod_def0 {
- /* SFP module present */
- gpio-hog;
- gpios = <15 GPIO_ACTIVE_LOW>;
- input;
- line-name = "sfp-mod-def0";
- };
- };
-
- /* The MCP3021 is 100kHz clock only */
- mikrobus_adc: mcp3021 at 4c {
- compatible = "microchip,mcp3021";
- reg = <0x4c>;
- };
-
- /* Also something at 0x64 */
- };
-
- i2c at 11100 {
- /*
- * Routed to SFP, mikrobus, and PCIe.
- * SFP limits this to 100kHz, and requires
- * an AT24C01A/02/04 with address pins tied
- * low, which takes addresses 0x50 and 0x51.
- * Mikrobus doesn't specify beyond an I2C
- * bus being present.
- * PCIe uses ARP to assign addresses, or
- * 0x63-0x64.
- */
- clock-frequency = <100000>;
- pinctrl-0 = <&clearfog_i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- pinctrl at 18000 {
- clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
- marvell,pins = "mpp46";
- marvell,function = "ref";
- };
- clearfog_dsa0_pins: clearfog-dsa0-pins {
- marvell,pins = "mpp23", "mpp41";
- marvell,function = "gpio";
- };
- clearfog_i2c1_pins: i2c1-pins {
- /* SFP, PCIe, mSATA, mikrobus */
- marvell,pins = "mpp26", "mpp27";
- marvell,function = "i2c1";
- };
- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
- clearfog_spi1_cs_pins: spi1-cs-pins {
- marvell,pins = "mpp55";
- marvell,function = "spi1";
- };
- mikro_pins: mikro-pins {
- /* int: mpp22 rst: mpp29 */
- marvell,pins = "mpp22", "mpp29";
- marvell,function = "gpio";
- };
- mikro_spi_pins: mikro-spi-pins {
- marvell,pins = "mpp43";
- marvell,function = "spi1";
- };
- mikro_uart_pins: mikro-uart-pins {
- marvell,pins = "mpp24", "mpp25";
- marvell,function = "ua1";
- };
- rear_button_pins: rear-button-pins {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- };
-
- sata at a8000 {
- /* pinctrl? */
- status = "okay";
- };
-
- sata at e0000 {
- /* pinctrl? */
- status = "okay";
- };
-
- sdhci at d8000 {
- bus-width = <4>;
- cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- pinctrl-0 = <µsom_sdhci_pins
- &clearfog_sdhci_cd_pins>;
- pinctrl-names = "default";
- status = "okay";
- vmmc = <®_3p3v>;
- wp-inverted;
- };
-
- serial at 12100 {
- /* mikrobus uart */
- pinctrl-0 = <&mikro_uart_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- usb at 58000 {
- /* CON3, nearest power. */
- status = "okay";
- };
-
- usb3 at f0000 {
- /* CON2, nearest CPU, USB2 only. */
- status = "okay";
- };
-
- usb3 at f8000 {
- /* CON7 */
- status = "okay";
- };
- };
-
- pcie-controller {
- status = "okay";
- /*
- * The two PCIe units are accessible through
- * the mini-PCIe connectors on the board.
- */
- pcie at 2,0 {
- /* Port 1, Lane 0. CON3, nearest power. */
- reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
- pcie at 3,0 {
- /* Port 2, Lane 0. CON2, nearest CPU. */
- reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
- };
- };
-
- dsa at 0 {
- compatible = "marvell,dsa";
- dsa,ethernet = <ð1>;
- dsa,mii-bus = <&mdio>;
- pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
- pinctrl-names = "default";
- #address-cells = <2>;
- #size-cells = <0>;
-
- switch at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4 0>;
-
- port at 0 {
- reg = <0>;
- label = "lan5";
- };
-
- port at 1 {
- reg = <1>;
- label = "lan4";
- };
-
- port at 2 {
- reg = <2>;
- label = "lan3";
- };
-
- port at 3 {
- reg = <3>;
- label = "lan2";
- };
-
- port at 4 {
- reg = <4>;
- label = "lan1";
- };
-
- port at 5 {
- reg = <5>;
- label = "cpu";
- };
-
- port at 6 {
- /* 88E1512 external phy */
- reg = <6>;
- label = "lan6";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&rear_button_pins>;
- pinctrl-names = "default";
-
- button_0 {
- /* The rear SW3 button */
- label = "Rear Button";
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- linux,can-disable;
- linux,code = <BTN_0>;
- };
- };
-};
-
-&spi1 {
- /*
- * Add SPI CS pins for clearfog:
- * CS0: W25Q32 (not populated on uSOM)
- * CS1:
- * CS2: mikrobus
- */
- pinctrl-0 = <&spi1_pins
- &clearfog_spi1_cs_pins
- &mikro_spi_pins>;
- pinctrl-names = "default";
- status = "okay";
};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
new file mode 100644
index 000000000000..59438777287a
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -0,0 +1,425 @@
+/*
+ * Device Tree include file for SolidRun Clearfog 88F6828 based boards
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
+
+/ {
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ ethernet2 = ð1;
+ ethernet3 = ð2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ soc {
+ internal-regs {
+ ethernet at 30000 {
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ bm,pool-short = <1>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet at 34000 {
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <3>;
+ bm,pool-short = <1>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ i2c at 11000 {
+ /* Is there anything on this? */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander at 20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ sfp_los {
+ /* SFP loss of signal */
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "sfp-los";
+ };
+ sfp_tx_fault {
+ /* SFP laser fault */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "sfp-tx-fault";
+ };
+ sfp_tx_disable {
+ /* SFP transmit disable */
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "sfp-tx-disable";
+ };
+ sfp_mod_def0 {
+ /* SFP module present */
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "sfp-mod-def0";
+ };
+ };
+
+ /* The MCP3021 is 100kHz clock only */
+ mikrobus_adc: mcp3021 at 4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+
+ /* Also something at 0x64 */
+ };
+
+ i2c at 11100 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ pinctrl at 18000 {
+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "ref";
+ };
+ clearfog_dsa0_pins: clearfog-dsa0-pins {
+ marvell,pins = "mpp23", "mpp41";
+ marvell,function = "gpio";
+ };
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+ };
+
+ sata at a8000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sata at e0000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sdhci at d8000 {
+ bus-width = <4>;
+ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-0 = <µsom_sdhci_pins
+ &clearfog_sdhci_cd_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc = <®_3p3v>;
+ wp-inverted;
+ };
+
+ serial at 12100 {
+ /* mikrobus uart */
+ pinctrl-0 = <&mikro_uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ usb at 58000 {
+ /* CON3, nearest power. */
+ status = "okay";
+ };
+
+ usb3 at f0000 {
+ /* CON2, nearest CPU, USB2 only. */
+ status = "okay";
+ };
+
+ usb3 at f8000 {
+ /* CON7 */
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * the mini-PCIe connectors on the board.
+ */
+ pcie at 2,0 {
+ /* Port 1, Lane 0. CON3, nearest power. */
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ pcie at 3,0 {
+ /* Port 2, Lane 0. CON2, nearest CPU. */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
+ dsa at 0 {
+ compatible = "marvell,dsa";
+ dsa,ethernet = <ð1>;
+ dsa,mii-bus = <&mdio>;
+ pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ switch at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4 0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan5";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan4";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "lan1";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ };
+
+ port at 6 {
+ /* 88E1512 external phy */
+ reg = <6>;
+ label = "lan6";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
+};
+
+&spi1 {
+ /*
+ * Add SPI CS pins for clearfog:
+ * CS0: W25Q32 (not populated on uSOM)
+ * CS1:
+ * CS2: mikrobus
+ */
+ pinctrl-0 = <&spi1_pins
+ &clearfog_spi1_cs_pins
+ &mikro_spi_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 4/9] ARM: dts: armada388-clearfog: move DSA switch
From: Russell King @ 2017-01-02 14:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Move the DSA switch configuration to the clearfog .dts file as this is
only present on the pro models.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 75 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/armada-388-clearfog.dtsi | 69 ---------------------------
2 files changed, 75 insertions(+), 69 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index c5f2ca5f6144..a1176d23a444 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -53,4 +53,79 @@
model = "SolidRun Clearfog A1";
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
+
+ dsa at 0 {
+ compatible = "marvell,dsa";
+ dsa,ethernet = <ð1>;
+ dsa,mii-bus = <&mdio>;
+ pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ switch at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4 0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan5";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan4";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "lan1";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ };
+
+ port at 6 {
+ /* 88E1512 external phy */
+ reg = <6>;
+ label = "lan6";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+ð1 {
+ /* ethernet at 30000 */
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&pinctrl {
+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "ref";
+ };
+ clearfog_dsa0_pins: clearfog-dsa0-pins {
+ marvell,pins = "mpp23", "mpp41";
+ marvell,function = "gpio";
+ };
};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 59438777287a..fb02997a52a1 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -77,11 +77,6 @@
bm,pool-long = <2>;
bm,pool-short = <1>;
status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
};
ethernet at 34000 {
@@ -235,14 +230,6 @@
};
pinctrl at 18000 {
- clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
- marvell,pins = "mpp46";
- marvell,function = "ref";
- };
- clearfog_dsa0_pins: clearfog-dsa0-pins {
- marvell,pins = "mpp23", "mpp41";
- marvell,function = "gpio";
- };
clearfog_i2c1_pins: i2c1-pins {
/* SFP, PCIe, mSATA, mikrobus */
marvell,pins = "mpp26", "mpp27";
@@ -339,62 +326,6 @@
};
};
- dsa at 0 {
- compatible = "marvell,dsa";
- dsa,ethernet = <ð1>;
- dsa,mii-bus = <&mdio>;
- pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
- pinctrl-names = "default";
- #address-cells = <2>;
- #size-cells = <0>;
-
- switch at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4 0>;
-
- port at 0 {
- reg = <0>;
- label = "lan5";
- };
-
- port at 1 {
- reg = <1>;
- label = "lan4";
- };
-
- port at 2 {
- reg = <2>;
- label = "lan3";
- };
-
- port at 3 {
- reg = <3>;
- label = "lan2";
- };
-
- port at 4 {
- reg = <4>;
- label = "lan1";
- };
-
- port at 5 {
- reg = <5>;
- label = "cpu";
- };
-
- port at 6 {
- /* 88E1512 external phy */
- reg = <6>;
- label = "lan6";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;
--
2.7.4
^ permalink raw reply related
* [PATCH 5/9] ARM: dts: armada388-clearfog: move second PCIe port
From: Russell King @ 2017-01-02 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Move the second PCIe port to the clearfog .dts file as this is only
present on the pro models.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 51 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/armada-388-clearfog.dtsi | 28 ++--------------
2 files changed, 54 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index a1176d23a444..1ee953112d23 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -54,6 +54,23 @@
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
+ soc {
+ internal-regs {
+ usb3 at f0000 {
+ /* CON2, nearest CPU, USB2 only. */
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ pcie at 3,0 {
+ /* Port 2, Lane 0. CON2, nearest CPU. */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
dsa at 0 {
compatible = "marvell,dsa";
dsa,ethernet = <ð1>;
@@ -119,6 +136,40 @@
};
};
+&expander0 {
+ /*
+ * PCA9655 GPIO expander:
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+};
+
&pinctrl {
clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
marvell,pins = "mpp46";
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index fb02997a52a1..ef4fbc6db7cf 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -103,12 +103,12 @@
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
* 1-CON3 PERST#
- * 2-CON2 PERST#
+ * 2-
* 3-CON3 W_DISABLE
- * 4-CON2 CLKREQ#
+ * 4-
* 5-USB3 overcurrent
* 6-USB3 power
- * 7-CON2 W_DISABLE
+ * 7-
* 8-JP4 P1
* 9-JP4 P4
* 10-JP4 P5
@@ -143,18 +143,6 @@
output-low;
line-name = "pcie1.0-w-disable";
};
- pcie2_0_clkreq {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie2.0-clkreq";
- };
- pcie2_0_w_disable {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie2.0-w-disable";
- };
usb3_ilimit {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
@@ -296,11 +284,6 @@
status = "okay";
};
- usb3 at f0000 {
- /* CON2, nearest CPU, USB2 only. */
- status = "okay";
- };
-
usb3 at f8000 {
/* CON7 */
status = "okay";
@@ -318,11 +301,6 @@
reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
- pcie at 3,0 {
- /* Port 2, Lane 0. CON2, nearest CPU. */
- reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 6/9] ARM: dts: armada388-clearfog: move SPI CS1
From: Russell King @ 2017-01-02 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Move the SPI CS1 configuration to the clearfog .dts file as this is only
present on pro models.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 14 ++++++++++++++
arch/arm/boot/dts/armada-388-clearfog.dtsi | 10 ++--------
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 1ee953112d23..b56ce4a32519 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -179,4 +179,18 @@
marvell,pins = "mpp23", "mpp41";
marvell,function = "gpio";
};
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+};
+
+&spi1 {
+ /*
+ * Add SPI CS pins for clearfog:
+ * CS0: W25Q32 (not populated on uSOM)
+ * CS1:
+ * CS2: mikrobus
+ */
+ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index ef4fbc6db7cf..30b75379377a 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -227,10 +227,6 @@
marvell,pins = "mpp20";
marvell,function = "gpio";
};
- clearfog_spi1_cs_pins: spi1-cs-pins {
- marvell,pins = "mpp55";
- marvell,function = "spi1";
- };
mikro_pins: mikro-pins {
/* int: mpp22 rst: mpp29 */
marvell,pins = "mpp22", "mpp29";
@@ -323,12 +319,10 @@
/*
* Add SPI CS pins for clearfog:
* CS0: W25Q32 (not populated on uSOM)
- * CS1:
+ * CS1: PIC microcontroller (Pro models)
* CS2: mikrobus
*/
- pinctrl-0 = <&spi1_pins
- &clearfog_spi1_cs_pins
- &mikro_spi_pins>;
+ pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 7/9] ARM: dts: armada388-clearfog: move rear button
From: Russell King @ 2017-01-02 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Move the rear button support into the clearfog pro support file.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 18 ++++++++++++++++++
arch/arm/boot/dts/armada-388-clearfog.dtsi | 18 ------------------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index b56ce4a32519..51887b85dba4 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -126,6 +126,20 @@
};
};
};
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
};
ð1 {
@@ -183,6 +197,10 @@
marvell,pins = "mpp55";
marvell,function = "spi1";
};
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
};
&spi1 {
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 30b75379377a..770d4bff6884 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -240,10 +240,6 @@
marvell,pins = "mpp24", "mpp25";
marvell,function = "ua1";
};
- rear_button_pins: rear-button-pins {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
};
sata at a8000 {
@@ -299,20 +295,6 @@
};
};
};
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&rear_button_pins>;
- pinctrl-names = "default";
-
- button_0 {
- /* The rear SW3 button */
- label = "Rear Button";
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- linux,can-disable;
- linux,code = <BTN_0>;
- };
- };
};
&spi1 {
--
2.7.4
^ permalink raw reply related
* [PATCH 8/9] ARM: dts: armada388-clearfog: add base model DTS file
From: Russell King @ 2017-01-02 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Add the DTS file to describe the clearfog base model.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-388-clearfog-base.dts | 94 ++++++++++++++++++++++++++
2 files changed, 95 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-388-clearfog-base.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c558ba75cbcc..22d2ca2b52ec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -921,6 +921,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \
armada-388-clearfog.dtb \
+ armada-388-clearfog-base.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \
armada-388-rd.dtb
diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts
new file mode 100644
index 000000000000..f86e1876fb38
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
@@ -0,0 +1,94 @@
+/*
+ * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-388-clearfog.dtsi"
+
+/ {
+ model = "SolidRun Clearfog Base A1";
+ compatible = "solidrun,clearfog-base-a1",
+ "solidrun,clearfog-a1", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
+};
+
+ð1 {
+ phy = <&phy1>;
+};
+
+&mdio {
+ phy1: ethernet-phy at 1 {
+ /*
+ * Annoyingly, the marvell phy driver configures the LED
+ * register, rather than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x101e>;
+ reg = <1>;
+ };
+};
+
+&pinctrl {
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 9/9] ARM: dts: armada388-clearfog: add pro model DTS file
From: Russell King @ 2017-01-02 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Add the DTS file to describe the clearfog pro model - we update the
platform name and compatible string compared to the original version.
The original version remains for compatibility for the time being as
the name of the file has become established, and the machine name
and/or compatible may be used by userspace.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-388-clearfog-pro.dts | 55 +++++++++++++++++++++++++++
2 files changed, 56 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-388-clearfog-pro.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 22d2ca2b52ec..8cf288f8b84f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -922,6 +922,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-linksys-cobra.dtb \
armada-388-clearfog.dtb \
armada-388-clearfog-base.dtb \
+ armada-388-clearfog-pro.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \
armada-388-rd.dtb
diff --git a/arch/arm/boot/dts/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/armada-388-clearfog-pro.dts
new file mode 100644
index 000000000000..e0c630a4d92c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-clearfog-pro.dts
@@ -0,0 +1,55 @@
+/*
+ * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "armada-388-clearfog.dts"
+
+/ {
+ model = "SolidRun Clearfog Pro A1";
+ compatible = "solidrun,clearfog-pro-a1",
+ "solidrun,clearfog-a1", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 15/20] ARM/hw_breakpoint: Convert to hotplug state machine
From: Russell King - ARM Linux @ 2017-01-02 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkda2gdjM--LSoJTL0dvqyw796w1hMSAhUQwv9X0EPzJHig@mail.gmail.com>
On Mon, Jan 02, 2017 at 03:34:32PM +0100, Linus Walleij wrote:
> in the first line of arch_hw_breakpoint_init() in
> arch/arm/kernel/hw_breakpoint.c
>
> I suspect that is not an accepable solution ...
>
> It hangs at PC is at write_wb_reg+0x20c/0x330
> Which is c03101dc, and looks like this in objdump -d:
>
> c031020c: ee001eba mcr 14, 0, r1, cr0, cr10, {5}
> c0310210: eaffffb3 b c03100e4 <write_wb_reg+0x114>
... and this is several instructions after the address you mention above.
Presumably c03101dc is accessing a higher numbered register?
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH 0/5] ARM: dts: armada388: rework clearfog's .dtsi references
From: Russell King @ 2017-01-02 15:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO454-00083C-Tj@rmk-PC.armlinux.org.uk>
This patch series, based upon the previous series adding Clearfog Base
support, reworks the clearfog .dtsi file to reference nodes by label
rather than by path.
Not everything is moved - just those which had labels at the time the
patches were created.
arch/arm/boot/dts/armada-388-clearfog-base.dts | 15 +
arch/arm/boot/dts/armada-388-clearfog.dtsi | 353 ++++++++++-----------
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 113 ++++---
3 files changed, 245 insertions(+), 236 deletions(-)
^ permalink raw reply
* [RFC v2 PATCH 1/3] ARM: NOMMU: introduce dma operations for noMMU
From: Benjamin Gaignard @ 2017-01-02 15:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481636704-18948-2-git-send-email-vladimir.murzin@arm.com>
Hello Vladimir,
I have tested your patch on my setup (stm32f4: no MMU, no MPU) where
I'm writing display driver.
This driver use dma_alloc_wc() and dma_mmap_wc() for frame buffer
allocation and mmapping.
In dma-mapping-nommu.c you haven't implement dma_map_ops.mmap so
obviously my driver
doesn't work with your code.
In current implementation it is buggy too but I submit a patch to fix
that problem:
http://www.armlinux.org.uk/developer/patches/viewpatch.php?id=8633/1
Could it be possible for you to include mmap support in dma-mapping-nommu.c ?
Regards,
Benjamin
2016-12-13 14:45 GMT+01:00 Vladimir Murzin <vladimir.murzin@arm.com>:
> R/M classes of cpus can have momory covered by MPU which in turn might
> configure RAM as Normal i.e. bufferable and cacheable. It breaks
> dma_alloc_coherent() and friends, since data can stuck in caches now
> or be buffered.
>
> This patch introduces the way to specify region of memory (via
> "memdma=size at start" command line option) suitable for consistent DMA
> operations. It is supposed that such region is marked by MPU as
> non-cacheable.
>
> For configuration without cache support (like Cortex-M3/M4) dma
> operations are forced to be coherent and wired with dma-noop. Such
> decision is made based on cacheid global variable. In case cpu
> supports caches and no coherent memory region is given - dma is
> disallowed.
>
> Reported-by: Alexandre Torgue <alexandre.torgue@st.com>
> Reported-by: Andras Szemzo <sza@esh.hu>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm/include/asm/dma-mapping.h | 3 +-
> arch/arm/mm/Makefile | 5 +-
> arch/arm/mm/dma-mapping-nommu.c | 262 ++++++++++++++++++++++++++++++++++++
> arch/arm/mm/mm.h | 3 +
> arch/arm/mm/nommu.c | 6 +
> 5 files changed, 275 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/mm/dma-mapping-nommu.c
>
> diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
> index bf02dbd..559faad 100644
> --- a/arch/arm/include/asm/dma-mapping.h
> +++ b/arch/arm/include/asm/dma-mapping.h
> @@ -20,7 +20,8 @@ static inline struct dma_map_ops *__generic_dma_ops(struct device *dev)
> {
> if (dev && dev->archdata.dma_ops)
> return dev->archdata.dma_ops;
> - return &arm_dma_ops;
> +
> + return IS_ENABLED(CONFIG_MMU) ? &arm_dma_ops : &dma_noop_ops;
> }
>
> static inline struct dma_map_ops *get_dma_ops(struct device *dev)
> diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
> index 2ac7988..5796357 100644
> --- a/arch/arm/mm/Makefile
> +++ b/arch/arm/mm/Makefile
> @@ -2,9 +2,8 @@
> # Makefile for the linux arm-specific parts of the memory manager.
> #
>
> -obj-y := dma-mapping.o extable.o fault.o init.o \
> - iomap.o
> -
> +obj-y := extable.o fault.o init.o iomap.o
> +obj-y += dma-mapping$(MMUEXT).o
> obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \
> mmap.o pgd.o mmu.o pageattr.o
>
> diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c
> new file mode 100644
> index 0000000..f92d98a
> --- /dev/null
> +++ b/arch/arm/mm/dma-mapping-nommu.c
> @@ -0,0 +1,262 @@
> +/*
> + * Based on linux/arch/arm/mm/dma-mapping.c
> + *
> + * Copyright (C) 2000-2004 Russell King
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * DMA uncached mapping support.
> + */
> +
> +#include <linux/export.h>
> +#include <linux/mm.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/scatterlist.h>
> +#include <linux/genalloc.h>
> +
> +#include <asm/cachetype.h>
> +#include <asm/cacheflush.h>
> +#include <asm/outercache.h>
> +
> +#include "dma.h"
> +
> +unsigned long dma_start __initdata;
> +unsigned long dma_size __initdata;
> +
> +static struct gen_pool *dma_pool;
> +
> +static void *arm_nommu_dma_alloc(struct device *dev, size_t size,
> + dma_addr_t *dma_handle, gfp_t gfp,
> + unsigned long attrs)
> +{
> + void *ptr;
> +
> + if (!dma_pool)
> + return NULL;
> +
> + ptr = (void *)gen_pool_alloc(dma_pool, size);
> + if (ptr) {
> + *dma_handle = __pa(ptr);
> + dmac_flush_range(ptr, ptr + size);
> + outer_flush_range(__pa(ptr), __pa(ptr) + size);
> + }
> +
> + return ptr;
> +}
> +
> +static void arm_nommu_dma_free(struct device *dev, size_t size,
> + void *cpu_addr, dma_addr_t dma_addr,
> + unsigned long attrs)
> +{
> + gen_pool_free(dma_pool, (unsigned long)cpu_addr, size);
> +}
> +
> +static void __dma_page_cpu_to_dev(dma_addr_t handle, size_t size,
> + enum dma_data_direction dir)
> +{
> + dmac_map_area(__va(handle), size, dir);
> +
> + if (dir == DMA_FROM_DEVICE)
> + outer_inv_range(handle, handle + size);
> + else
> + outer_clean_range(handle, handle + size);
> +}
> +
> +static void __dma_page_dev_to_cpu(dma_addr_t handle, size_t size,
> + enum dma_data_direction dir)
> +{
> + if (dir != DMA_TO_DEVICE) {
> + outer_inv_range(handle, handle + size);
> + dmac_unmap_area(__va(handle), size, dir);
> + }
> +}
> +
> +static dma_addr_t arm_nommu_dma_map_page(struct device *dev, struct page *page,
> + unsigned long offset, size_t size,
> + enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + dma_addr_t handle = page_to_phys(page) + offset;
> +
> + __dma_page_cpu_to_dev(handle, size, dir);
> +
> + return handle;
> +}
> +
> +static void arm_nommu_dma_unmap_page(struct device *dev, dma_addr_t handle,
> + size_t size, enum dma_data_direction dir, unsigned long attrs)
> +{
> + __dma_page_dev_to_cpu(handle, size, dir);
> +}
> +
> +
> +static int arm_nommu_dma_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
> + enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + int i;
> + struct scatterlist *sg;
> +
> + for_each_sg(sgl, sg, nents, i) {
> + sg_dma_address(sg) = sg_phys(sg);
> + sg_dma_len(sg) = sg->length;
> + __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
> + }
> +
> + return nents;
> +}
> +
> +static void arm_nommu_dma_unmap_sg(struct device *dev, struct scatterlist *sgl, int nents,
> + enum dma_data_direction dir, unsigned long attrs)
> +{
> + struct scatterlist *sg;
> + int i;
> +
> + for_each_sg(sgl, sg, nents, i)
> + __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
> +}
> +
> +static void arm_nommu_dma_sync_single_for_device(struct device *dev,
> + dma_addr_t handle, size_t size, enum dma_data_direction dir)
> +{
> + __dma_page_cpu_to_dev(handle, size, dir);
> +}
> +
> +static void arm_nommu_dma_sync_single_for_cpu(struct device *dev,
> + dma_addr_t handle, size_t size, enum dma_data_direction dir)
> +{
> + __dma_page_cpu_to_dev(handle, size, dir);
> +}
> +
> +static void arm_nommu_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
> + int nents, enum dma_data_direction dir)
> +{
> + struct scatterlist *sg;
> + int i;
> +
> + for_each_sg(sgl, sg, nents, i)
> + __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
> +}
> +
> +static void arm_nommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
> + int nents, enum dma_data_direction dir)
> +{
> + struct scatterlist *sg;
> + int i;
> +
> + for_each_sg(sgl, sg, nents, i)
> + __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
> +}
> +
> +struct dma_map_ops arm_nommu_dma_ops = {
> + .alloc = arm_nommu_dma_alloc,
> + .free = arm_nommu_dma_free,
> + .map_page = arm_nommu_dma_map_page,
> + .unmap_page = arm_nommu_dma_unmap_page,
> + .map_sg = arm_nommu_dma_map_sg,
> + .unmap_sg = arm_nommu_dma_unmap_sg,
> + .sync_single_for_device = arm_nommu_dma_sync_single_for_device,
> + .sync_single_for_cpu = arm_nommu_dma_sync_single_for_cpu,
> + .sync_sg_for_device = arm_nommu_dma_sync_sg_for_device,
> + .sync_sg_for_cpu = arm_nommu_dma_sync_sg_for_cpu,
> +};
> +EXPORT_SYMBOL(arm_nommu_dma_ops);
> +
> +static struct dma_map_ops *arm_nommu_get_dma_map_ops(bool coherent)
> +{
> + return coherent ? &dma_noop_ops : &arm_nommu_dma_ops;
> +}
> +
> +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> + const struct iommu_ops *iommu, bool coherent)
> +{
> + struct dma_map_ops *dma_ops;
> +
> + /*
> + * Cahe support for v7m is optional, so can be treated as
> + * coherent if no cache has been detected.
> + */
> + dev->archdata.dma_coherent = (cacheid) ? coherent : true;
> +
> + dma_ops = arm_nommu_get_dma_map_ops(dev->archdata.dma_coherent);
> +
> + set_dma_ops(dev, dma_ops);
> +}
> +
> +void arch_teardown_dma_ops(struct device *dev)
> +{
> +}
> +
> +int dma_supported(struct device *dev, u64 mask)
> +{
> + if (cacheid && !dma_pool)
> + return 0;
> +
> + return 1;
> +}
> +
> +EXPORT_SYMBOL(dma_supported);
> +
> +#define PREALLOC_DMA_DEBUG_ENTRIES 4096
> +
> +static int __init dma_debug_do_init(void)
> +{
> + dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
> + return 0;
> +}
> +core_initcall(dma_debug_do_init);
> +
> +/*
> + * Initialise the coherent pool for DMA allocations.
> + */
> +static int __init dma_pool_init(void)
> +{
> + int ret;
> +
> + if (cacheid && !dma_size) {
> + pr_warn("DMA: coherent memory region has not been given.\n");
> + return 0;
> + }
> +
> + dma_pool = gen_pool_create(PAGE_SHIFT, -1);
> +
> + if (!dma_pool)
> + goto out;
> +
> + ret = gen_pool_add_virt(dma_pool, (unsigned long)dma_start, (unsigned long)dma_start,
> + dma_size, -1);
> + if (ret)
> + goto destroy_genpool;
> +
> + gen_pool_set_algo(dma_pool, gen_pool_first_fit_order_align, NULL);
> +
> + pr_info("DMA: coherent memory region 0x%lx - 0x%lx (%lu KiB)\n",
> + dma_start, dma_start + dma_size, dma_size >> 10);
> +
> + return 0;
> +
> +destroy_genpool:
> + gen_pool_destroy(dma_pool);
> + dma_pool = NULL;
> +out:
> + pr_err("DMA: failed to allocate coherent memory region\n");
> + return -ENOMEM;
> +}
> +
> +postcore_initcall(dma_pool_init);
> +
> +/* "memdma=<size>@<address>" parsing. */
> +static int __init early_memdma(char *p)
> +{
> + if (!p)
> + return -EINVAL;
> +
> + dma_size = memparse(p, &p);
> + if (*p == '@')
> + dma_start = memparse(p + 1, &p);
> +
> + return 0;
> +}
> +early_param("memdma", early_memdma);
> diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
> index ce727d4..18eb869 100644
> --- a/arch/arm/mm/mm.h
> +++ b/arch/arm/mm/mm.h
> @@ -97,3 +97,6 @@ struct static_vm {
> void dma_contiguous_remap(void);
>
> unsigned long __clear_cr(unsigned long mask);
> +
> +extern unsigned long dma_start __initdata;
> +extern unsigned long dma_size __initdata;
> diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
> index 681cec8..5827e54 100644
> --- a/arch/arm/mm/nommu.c
> +++ b/arch/arm/mm/nommu.c
> @@ -303,6 +303,12 @@ void __init sanity_check_meminfo(void)
> end = memblock_end_of_DRAM();
> high_memory = __va(end - 1) + 1;
> memblock_set_current_limit(end);
> +
> + if (dma_size &&
> + memblock_overlaps_region(&memblock.memory, dma_start, dma_size)) {
> + pr_crit("DMA: coherent memory region overlaps with main memory.\n");
> + dma_size = 0;
> + }
> }
>
> /*
> --
> 1.7.9.5
>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 1/5] ARM: dts: armada388-clearfog: add phy reset gpio-hog
From: Russell King @ 2017-01-02 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO4UH-0008SR-GW@rmk-PC.armlinux.org.uk>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog-base.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts
index f86e1876fb38..da788ea40717 100644
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
@@ -74,7 +74,17 @@
phy = <&phy1>;
};
+&gpio0 {
+ phy1_reset {
+ gpio-hog;
+ gpios = <19 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "phy1-reset";
+ };
+};
+
&mdio {
+ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>;
phy1: ethernet-phy at 1 {
/*
* Annoyingly, the marvell phy driver configures the LED
@@ -87,6 +97,11 @@
};
&pinctrl {
+ /* phy1 reset */
+ clearfog_phy_pins: clearfog-phy-pins {
+ marvell,pins = "mpp19";
+ marvell,function = "gpio";
+ };
rear_button_pins: rear-button-pins {
marvell,pins = "mpp44";
marvell,function = "gpio";
--
2.7.4
^ permalink raw reply related
* [PATCH 2/5] ARM: dts: armada388-clearfog: move device specific pinctrl nodes
From: Russell King @ 2017-01-02 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO4UH-0008SR-GW@rmk-PC.armlinux.org.uk>
Move the device specific pinctrl nodes over to use the label form to
reference the pin mux controller, rather than replicating the device
node path.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dtsi | 50 +++++++++++-----------
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 27 ++++++------
2 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 770d4bff6884..7946400b4bf2 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -217,31 +217,6 @@
status = "okay";
};
- pinctrl at 18000 {
- clearfog_i2c1_pins: i2c1-pins {
- /* SFP, PCIe, mSATA, mikrobus */
- marvell,pins = "mpp26", "mpp27";
- marvell,function = "i2c1";
- };
- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
- mikro_pins: mikro-pins {
- /* int: mpp22 rst: mpp29 */
- marvell,pins = "mpp22", "mpp29";
- marvell,function = "gpio";
- };
- mikro_spi_pins: mikro-spi-pins {
- marvell,pins = "mpp43";
- marvell,function = "spi1";
- };
- mikro_uart_pins: mikro-uart-pins {
- marvell,pins = "mpp24", "mpp25";
- marvell,function = "ua1";
- };
- };
-
sata at a8000 {
/* pinctrl? */
status = "okay";
@@ -297,6 +272,31 @@
};
};
+&pinctrl {
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+};
+
&spi1 {
/*
* Add SPI CS pins for clearfog:
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 6608657b9994..e397421d1531 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -94,20 +94,6 @@
};
};
- pinctrl at 18000 {
- microsom_phy_clk_pins: microsom-phy-clk-pins {
- marvell,pins = "mpp45";
- marvell,function = "ref";
- };
- /* Optional eMMC */
- microsom_sdhci_pins: microsom-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
- };
-
rtc at a3800 {
/*
* If the rtc doesn't work, run "date reset"
@@ -134,6 +120,19 @@
};
};
+&pinctrl {
+ microsom_phy_clk_pins: microsom-phy-clk-pins {
+ marvell,pins = "mpp45";
+ marvell,function = "ref";
+ };
+ /* Optional eMMC */
+ microsom_sdhci_pins: microsom-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28", "mpp37",
+ "mpp38", "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
+};
+
&spi1 {
/* The microsom has an optional W25Q32 on board, connected to CS0 */
pinctrl-0 = <&spi1_pins>;
--
2.7.4
^ permalink raw reply related
* [PATCH 3/5] ARM: dts: armada388-clearfog: move I2C nodes
From: Russell King @ 2017-01-02 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO4UH-0008SR-GW@rmk-PC.armlinux.org.uk>
Move the I2C nodes over to use the label form to reference the I2C
controllers, rather than replicating the device node path.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dtsi | 245 ++++++++++++++---------------
1 file changed, 120 insertions(+), 125 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 7946400b4bf2..eeb845bbe3f3 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -92,131 +92,6 @@
};
};
- i2c at 11000 {
- /* Is there anything on this? */
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /*
- * PCA9655 GPIO expander, up to 1MHz clock.
- * 0-CON3 CLKREQ#
- * 1-CON3 PERST#
- * 2-
- * 3-CON3 W_DISABLE
- * 4-
- * 5-USB3 overcurrent
- * 6-USB3 power
- * 7-
- * 8-JP4 P1
- * 9-JP4 P4
- * 10-JP4 P5
- * 11-m.2 DEVSLP
- * 12-SFP_LOS
- * 13-SFP_TX_FAULT
- * 14-SFP_TX_DISABLE
- * 15-SFP_MOD_DEF0
- */
- expander0: gpio-expander at 20 {
- /*
- * This is how it should be:
- * compatible = "onnn,pca9655",
- * "nxp,pca9555";
- * but you can't do this because of
- * the way I2C works.
- */
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
-
- pcie1_0_clkreq {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie1.0-clkreq";
- };
- pcie1_0_w_disable {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie1.0-w-disable";
- };
- usb3_ilimit {
- gpio-hog;
- gpios = <5 GPIO_ACTIVE_LOW>;
- input;
- line-name = "usb3-current-limit";
- };
- usb3_power {
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb3-power";
- };
- m2_devslp {
- gpio-hog;
- gpios = <11 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "m.2 devslp";
- };
- sfp_los {
- /* SFP loss of signal */
- gpio-hog;
- gpios = <12 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-los";
- };
- sfp_tx_fault {
- /* SFP laser fault */
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-tx-fault";
- };
- sfp_tx_disable {
- /* SFP transmit disable */
- gpio-hog;
- gpios = <14 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "sfp-tx-disable";
- };
- sfp_mod_def0 {
- /* SFP module present */
- gpio-hog;
- gpios = <15 GPIO_ACTIVE_LOW>;
- input;
- line-name = "sfp-mod-def0";
- };
- };
-
- /* The MCP3021 is 100kHz clock only */
- mikrobus_adc: mcp3021 at 4c {
- compatible = "microchip,mcp3021";
- reg = <0x4c>;
- };
-
- /* Also something at 0x64 */
- };
-
- i2c at 11100 {
- /*
- * Routed to SFP, mikrobus, and PCIe.
- * SFP limits this to 100kHz, and requires
- * an AT24C01A/02/04 with address pins tied
- * low, which takes addresses 0x50 and 0x51.
- * Mikrobus doesn't specify beyond an I2C
- * bus being present.
- * PCIe uses ARP to assign addresses, or
- * 0x63-0x64.
- */
- clock-frequency = <100000>;
- pinctrl-0 = <&clearfog_i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
sata at a8000 {
/* pinctrl? */
status = "okay";
@@ -272,6 +147,126 @@
};
};
+&i2c0 {
+ /* Is there anything on this? */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-
+ * 3-CON3 W_DISABLE
+ * 4-
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander at 20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655", "nxp,pca9555";
+ * but you can't do this because of the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ sfp_los {
+ /* SFP loss of signal */
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "sfp-los";
+ };
+ sfp_tx_fault {
+ /* SFP laser fault */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "sfp-tx-fault";
+ };
+ sfp_tx_disable {
+ /* SFP transmit disable */
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "sfp-tx-disable";
+ };
+ sfp_mod_def0 {
+ /* SFP module present */
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "sfp-mod-def0";
+ };
+ };
+
+ /* The MCP3021 is 100kHz clock only */
+ mikrobus_adc: mcp3021 at 4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+
+ /* Also something at 0x64 */
+};
+
+&i2c1 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
+ * address pins tied low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C bus being present.
+ * PCIe uses ARP to assign addresses, or 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&pinctrl {
clearfog_i2c1_pins: i2c1-pins {
/* SFP, PCIe, mSATA, mikrobus */
--
2.7.4
^ permalink raw reply related
* [PATCH 4/5] ARM: dts: armada388-clearfog: move ethernet related nodes
From: Russell King @ 2017-01-02 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO4UH-0008SR-GW@rmk-PC.armlinux.org.uk>
Move the ethernet, buffer manager, and mdio nodes over to use label form
to reference the devices rather than replicating the device path.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dtsi | 44 +++++++------
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 76 +++++++++++-----------
2 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index eeb845bbe3f3..6149699eefc2 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -71,27 +71,6 @@
soc {
internal-regs {
- ethernet at 30000 {
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <1>;
- status = "okay";
- };
-
- ethernet at 34000 {
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <3>;
- bm,pool-short = <1>;
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
sata at a8000 {
/* pinctrl? */
status = "okay";
@@ -147,6 +126,29 @@
};
};
+ð1 {
+ /* ethernet at 30000 */
+ bm,pool-long = <2>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+ð2 {
+ /* ethernet at 34000 */
+ bm,pool-long = <3>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ phy-mode = "sgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
&i2c0 {
/* Is there anything on this? */
clock-frequency = <100000>;
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index e397421d1531..681962a6395b 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -62,38 +62,6 @@
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
- ethernet at 70000 {
- pinctrl-0 = <&ge0_rgmii_pins>;
- pinctrl-names = "default";
- phy = <&phy_dedicated>;
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- status = "okay";
- };
-
- mdio at 72004 {
- /*
- * Add the phy clock here, so the phy can be
- * accessed to read its IDs prior to binding
- * with the driver.
- */
- pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
- pinctrl-names = "default";
-
- phy_dedicated: ethernet-phy at 0 {
- /*
- * Annoyingly, the marvell phy driver
- * configures the LED register, rather
- * than preserving reset-loaded setting.
- * We undo that rubbish here.
- */
- marvell,reg-init = <3 16 0 0x101e>;
- reg = <0>;
- };
- };
-
rtc at a3800 {
/*
* If the rtc doesn't work, run "date reset"
@@ -107,16 +75,46 @@
pinctrl-names = "default";
status = "okay";
};
-
- bm at c8000 {
- status = "okay";
- };
};
+ };
+};
- bm-bppi {
- status = "okay";
- };
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+ð0 {
+ /* ethernet at 70000 */
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy_dedicated>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ status = "okay";
+};
+
+&mdio {
+ /*
+ * Add the phy clock here, so the phy can be accessed to read its
+ * IDs prior to binding with the driver.
+ */
+ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
+ pinctrl-names = "default";
+ phy_dedicated: ethernet-phy at 0 {
+ /*
+ * Annoyingly, the marvell phy driver configures the LED
+ * register, rather than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x101e>;
+ reg = <0>;
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 5/5] ARM: dts: armada388-clearfog: move uart nodes
From: Russell King @ 2017-01-02 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO4UH-0008SR-GW@rmk-PC.armlinux.org.uk>
Move the uart nodes over to use the label form to reference the serial
devices, rather than replicating the device node path.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dtsi | 14 +++++++-------
arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 12 ++++++------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 6149699eefc2..0f5938bede53 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -93,13 +93,6 @@
wp-inverted;
};
- serial at 12100 {
- /* mikrobus uart */
- pinctrl-0 = <&mikro_uart_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
usb at 58000 {
/* CON3, nearest power. */
status = "okay";
@@ -305,3 +298,10 @@
pinctrl-names = "default";
status = "okay";
};
+
+&uart1 {
+ /* mikrobus uart */
+ pinctrl-0 = <&mikro_uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 681962a6395b..458884ff4c8c 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -69,12 +69,6 @@
*/
status = "okay";
};
-
- serial at 12000 {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
};
};
};
@@ -144,3 +138,9 @@
status = "disabled";
};
};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH] crypto: picoxcell - Fix module autoload for non-OF registration
From: Javier Martinez Canillas @ 2017-01-02 15:38 UTC (permalink / raw)
To: linux-arm-kernel
If the driver is built as a module, autoload won't work because the module
alias information is not filled. So user-space can't match the registered
device with the corresponding module if the device isn't registered via OF.
Export the module alias information using the MODULE_DEVICE_TABLE() macro.
Before this patch:
$ modinfo drivers/crypto/picoxcell_crypto.ko | grep alias
alias: of:N*T*Cpicochip,spacc-l2C*
alias: of:N*T*Cpicochip,spacc-l2
alias: of:N*T*Cpicochip,spacc-ipsecC*
alias: of:N*T*Cpicochip,spacc-ipsec
After this patch:
$ modinfo drivers/crypto/picoxcell_crypto.ko | grep alias
alias: of:N*T*Cpicochip,spacc-l2C*
alias: of:N*T*Cpicochip,spacc-l2
alias: of:N*T*Cpicochip,spacc-ipsecC*
alias: of:N*T*Cpicochip,spacc-ipsec
alias: platform:picochip,spacc-l2
alias: platform:picochip,spacc-ipsec
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
drivers/crypto/picoxcell_crypto.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/picoxcell_crypto.c b/drivers/crypto/picoxcell_crypto.c
index 47576098831f..64449b7c00af 100644
--- a/drivers/crypto/picoxcell_crypto.c
+++ b/drivers/crypto/picoxcell_crypto.c
@@ -1808,6 +1808,7 @@ static const struct platform_device_id spacc_id_table[] = {
{ "picochip,spacc-l2", },
{ }
};
+MODULE_DEVICE_TABLE(platform, spacc_id_table);
static struct platform_driver spacc_driver = {
.probe = spacc_probe,
--
2.7.4
^ permalink raw reply related
* [GIT PULL] ARM: exynos: Late mach/soc for v4.10
From: Krzysztof Kozlowski @ 2017-01-02 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5b0e55c8-01db-3f02-3526-2f71f4a73d88@samsung.com>
On Mon, Jan 02, 2017 at 10:20:21AM +0100, Sylwester Nawrocki wrote:
> On 12/30/2016 04:53 PM, Krzysztof Kozlowski wrote:
> >
> > Any comments on this? I guess it won't come as late-late-4.10, so can
> > you pull it for v4.11?
>
> >> Sylwester Nawrocki (1):
> >> ARM: S3C24XX: Add DMA slave maps for remaining s3c24xx SoCs
>
> We need this patch in v4.10 to avoid possible I2S and MMC regressions
> on selected s3c24xx SoC, since the DMA clients are already modified.
> If the patch goes in only for v4.11 it would be good to mark it for
> inclusion in v4.10 stable kernels.
You didn't mention any strict dependencies when sending this patch...
What do you mean by "needing patch in v4.10"? Is the code already
not bisectable? Already broken?
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2 2/3] dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdma
From: Appana Durga Kedareswara Rao @ 2017-01-02 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <45807619-bf6a-0174-c102-12c03aeb575c@synopsys.com>
Hi Jose Miguel Abreu,
Thanks for the review...
[snip]...
>
> I just noticed there is a write to XILINX_DMA_REG_FRMSTORE which, by the
> description in the VDMA databook, allows to modify the total number of
> framebuffers.
>
> Does it correct this situation: Lets assume VDMA has 10 framebuffers in HW and
> user only submits 5 descriptors. Then vsize will be programmed and VDMA will
> start. The VDMA will start in fb 1, then 2, ... until 5 its all ok. But then after the fb
> 5 the VDMA will jump to fb 6, this fb will have no address because the user only
> submitted 5 addresses so VDMA will try to write to location 0x0 of system mem
> (if using S2MM channel). ?
>
> If so then there is no race condition, but the HW image that I have does not
> have this register enabled so I was getting this result (memory corruption
> because not all framebuffers had addresses set).
Thanks for the explanation.
Agree the issue that you mentioned won't come when XILINX_DMA_REG_FRMSTORE
(C_ENABLE_DEBUG_INFO_5 and C_ENABLE_DEBUG_INFO_13) Register is enabled in the IP.
But this register won't get enabled with the default IP configuration (C_ENABLE_DEBUG_INFO_5 and C_ENABLE_DEBUG_INFO_13).
When user is not enabled XILINX_DMA_REG_FRMSTORE in the h/w and submits frames less than h/w capable.
The solution that I am thinking is to throw an error in the driver saying that either enable the
num frame store feature in the IP or submit the frames up to h/w capable what do you think???
Regards,
Kedar.
>
> Best regards,
> Jose Miguel Abreu
>
> >
> > Regards,
> > Kedar.
> >
> >> Best regards,
> >> Jose Miguel Abreu
> >>
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Richard Cochran @ 2017-01-02 16:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFcVECLg-hXvfgwRW-fxi+N0k=7pTaEMhS5EMXV9_OO+xGRUqA@mail.gmail.com>
On Mon, Jan 02, 2017 at 05:13:34PM +0530, Harini Katakam wrote:
> From the revision history of Cadence spec, all versions starting
> r1p02 have ability to include timestamp in descriptors.
So why not add code to read the version, hm?
> For previous versions the event register is the only option.
And is it true that the regsiters do not latch the time stamp?
If so, then the IP core is more than useless.
Thanks,
Richard
^ permalink raw reply
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