* [PATCH] serial: mxs-auart: support CMSPAR termios cflag
From: Stefan Wahren @ 2017-01-03 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161212072101.9909-1-weo@reccoware.de>
Hi Wolfgang,
> If CMSPAR is set in the c_cflag of termios, "stick" parity is enabled.
you can have my
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
for this version 2 from 12.12.2016.
But in order to increase the chance that your patch get merged, please
resend your patch:
* with the correct version in your subject line
* not during the merge window
* with my Acked-by
* with a copy to linux-serial at vger.kernel.org
Thanks
Stefan
^ permalink raw reply
* [PATCH v6 6/8] IIO: add STM32 timer trigger driver
From: Benjamin Gaignard @ 2017-01-03 9:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c46e6e59-b5b6-39e6-d6f4-5ca4539f746c@kernel.org>
2017-01-02 19:22 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
> On 02/01/17 08:46, Benjamin Gaignard wrote:
>> 2016-12-30 22:12 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
>>> On 09/12/16 14:15, Benjamin Gaignard wrote:
>>>> Timers IPs can be used to generate triggers for other IPs like
>>>> DAC, ADC or other timers.
>>>> Each trigger may result of timer internals signals like counter enable,
>>>> reset or edge, this configuration could be done through "master_mode"
>>>> device attribute.
>>>>
>>>> A timer device could be triggered by other timers, we use the trigger
>>>> name and is_stm32_iio_timer_trigger() function to distinguish them
>>>> and configure IP input switch.
>>>>
>>>> Timer may also decide on which event (edge, level) they could
>>>> be activated by a trigger, this configuration is done by writing in
>>>> "slave_mode" device attribute.
>>>>
>>>> Since triggers could also be used by DAC or ADC their names are defined
>>>> in include/ nux/iio/timer/stm32-timer-trigger.h so those IPs will be able
>>>> to configure themselves in valid_trigger function
>>>>
>>>> Trigger have a "sampling_frequency" attribute which allow to configure
>>>> timer sampling frequency without using PWM interface
>>>>
>>>> version 5:
>>>> - simplify tables of triggers
>>>> - only create an IIO device when needed
>>>>
>>>> version 4:
>>>> - get triggers configuration from "reg" in DT
>>>> - add tables of triggers
>>>> - sampling frequency is enable/disable when writing in trigger
>>>> sampling_frequency attribute
>>>> - no more use of interruptions
>>>>
>>>> version 3:
>>>> - change compatible to "st,stm32-timer-trigger"
>>>> - fix attributes access right
>>>> - use string instead of int for master_mode and slave_mode
>>>> - document device attributes in sysfs-bus-iio-timer-stm32
>>>>
>>>> version 2:
>>>> - keep only one compatible
>>>> - use st,input-triggers-names and st,output-triggers-names
>>>> to know which triggers are accepted and/or create by the device
>>> Firstly, sorry it has taken me so long to get back to this.
>>>
>>> I'm still not keen on this use of iio_device elements just to act as
>>> glue between triggers. I think we need to work out a more light weight
>>> way to do this. As you are only using them for validation and to provide
>>> somewhere to hang the control attibutes off, there is nothing stopping us
>>> moving that over to the iio_trigger instead which would avoid the messy
>>> duality going on here.
>>
>> I have add an iio_device because each hardware can generate multiple
>> triggers (up to 5: trgo, ch 1...4) and slave_mode attribute will impact all the
>> triggers of a device. For me it was making sense to centralize that in an
>> iio_device rather than having an attribute "shared" (from hardware
>> point of view)
>> on multiple triggers.
>> Since master_mode attribute is only used by trgo and not impact ch1...4
>> triggers I will move it to trigger instead of the iio_device.
>>
>> I also wanted to be able to connect triggers on a iio_device as I
>> could do for an
>> ADC with a command like 'echo "tim1_trgo" > iio_deviceX/trigger/current_trigger'
> This is interesting, but with a bit of refactoring I would think it would
> be possible to share some of that code thus allowing non IIO devices to
> bind to triggers. Ultimately I want to be able to bind a trigger to
> a trigger - I appreciate here the topology is more limited than that
> so some complexity comes in.
>
> My gut feeling is that representing that topology explicitly is hard
> to do in a remotely general way, but lets try it and see.
> We run into this sort of interdependency issue between different bits of
> the hardware all the time. Setting a value somewhere effects the configuration
> elsewhere - often the best plan is to just let that happen and leave it up to
> userspace to check for changes if it cares.
okay
>> If I change that to parent_trigger attribute it change this behavior
>> and I will have to
>> duplicated what is done in iio_trigger_write_current() to find and
>> validate triggers.
> I get the reasoning, but we still end up with something represented
> by an IIO device that isn't providing any channels at all. It's simply
> using some of the infrastructure. To my mind it is 'something else'
> and should be represented as such. I have no problem at all with
> you registering additional elements in /sysfs/bus/iio/ to represent
> these shared elements - we already have drivers that do that to
> provide some centralized infrastructure (e.g. the sysfs-trigger)
My hardware block are timers maybe I can add a channel type "IIO_TIMER"
and declare a channel with info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ)
so I will be able to write/read sampling frequency on IIO device.
> I'm worried about the scope spread we get for an IIO device otherwise.
> They serve a well defined purpose at the moment, and that isn't what
> is happening here.
>
> So my gut feeling is we are better deliberately not representing the
> inter dependence and claiming all triggers we are creating are
> independent. That way we can have a nice generic infrastructure
> that will work in all cases (be it pushing the sanity checking to
> userspace).
>
> So each trigger has direct access to what controls it. Changing anything
> can effect other triggers in weird ways.
>
> I'm finding it hard to see anything else generalizing sufficiently
> as we'll always get cases where we can't represent the topology without
> diving into the complexity of something like the media controller
> framework.
>
> Jonathan
>>
>>> I might still be missing something though!
>>>
>>> You would only I think need 3 attributes
>>>
>>> parrent_trigger
>>> and something like your master_mode and slave_mode attributes.
>>>
>>> The parrent_trigger would need some validation etc, but if we keep it
>>> within this driver initially that won't be hard to do. Checking the device
>>> parent matches will do most of it.
>>>
>>> Jonathan
>>>>
>>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>> ---
>>>> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 55 +++
>>>> drivers/iio/Kconfig | 2 +-
>>>> drivers/iio/Makefile | 1 +
>>>> drivers/iio/timer/Kconfig | 13 +
>>>> drivers/iio/timer/Makefile | 1 +
>>>> drivers/iio/timer/stm32-timer-trigger.c | 466 +++++++++++++++++++++
>>>> drivers/iio/trigger/Kconfig | 1 -
>>>> include/linux/iio/timer/stm32-timer-trigger.h | 62 +++
>>>> 8 files changed, 599 insertions(+), 2 deletions(-)
>>>> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>> create mode 100644 drivers/iio/timer/Kconfig
>>>> create mode 100644 drivers/iio/timer/Makefile
>>>> create mode 100644 drivers/iio/timer/stm32-timer-trigger.c
>>>> create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
>>>>
>>>> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>> new file mode 100644
>>>> index 0000000..26583dd
>>>> --- /dev/null
>>>> +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>> @@ -0,0 +1,55 @@
>>>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode_available
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the list possible master modes which are:
>>>> + - "reset" : The UG bit from the TIMx_EGR register is used as trigger output (TRGO).
>>>> + - "enable" : The Counter Enable signal CNT_EN is used as trigger output.
>>>> + - "update" : The update event is selected as trigger output.
>>>> + For instance a master timer can then be used as a prescaler for a slave timer.
>>>> + - "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set.
>>>> + - "OC1REF" : OC1REF signal is used as trigger output.
>>>> + - "OC2REF" : OC2REF signal is used as trigger output.
>>>> + - "OC3REF" : OC3REF signal is used as trigger output.
>>>> + - "OC4REF" : OC4REF signal is used as trigger output.
>>>> +
>>>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the current master modes.
>>>> + Writing set the master mode
>>>> +
>>>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode_available
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the list possible slave modes which are:
>>>> + - "disabled" : The prescaler is clocked directly by the internal clock.
>>>> + - "encoder_1" : Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
>>>> + - "encoder_2" : Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
>>>> + - "encoder_3" : Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
>>>> + on the level of the other input.
>>>> + - "reset" : Rising edge of the selected trigger input reinitializes the counter
>>>> + and generates an update of the registers.
>>>> + - "gated" : The counter clock is enabled when the trigger input is high.
>>>> + The counter stops (but is not reset) as soon as the trigger becomes low.
>>>> + Both start and stop of the counter are controlled.
>>>> + - "trigger" : The counter starts at a rising edge of the trigger TRGI (but it is not
>>>> + reset). Only the start of the counter is controlled.
>>>> + - "external_clock": Rising edges of the selected trigger (TRGI) clock the counter.
>>>> +
>>>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the current slave mode.
>>>> + Writing set the slave mode
>>>> +
>>>> +What: /sys/bus/iio/devices/triggerX/sampling_frequency
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the current sampling frequency.
>>>> + Writing an value different of 0 set and start sampling.
>>>> + Writing 0 stop sampling.
>>>> diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
>>>> index 6743b18..2de2a80 100644
>>>> --- a/drivers/iio/Kconfig
>>>> +++ b/drivers/iio/Kconfig
>>>> @@ -90,5 +90,5 @@ source "drivers/iio/potentiometer/Kconfig"
>>>> source "drivers/iio/pressure/Kconfig"
>>>> source "drivers/iio/proximity/Kconfig"
>>>> source "drivers/iio/temperature/Kconfig"
>>>> -
>>>> +source "drivers/iio/timer/Kconfig"
>>>> endif # IIO
>>>> diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
>>>> index 87e4c43..b797c08 100644
>>>> --- a/drivers/iio/Makefile
>>>> +++ b/drivers/iio/Makefile
>>>> @@ -32,4 +32,5 @@ obj-y += potentiometer/
>>>> obj-y += pressure/
>>>> obj-y += proximity/
>>>> obj-y += temperature/
>>>> +obj-y += timer/
>>>> obj-y += trigger/
>>>> diff --git a/drivers/iio/timer/Kconfig b/drivers/iio/timer/Kconfig
>>>> new file mode 100644
>>>> index 0000000..e3c21f2
>>>> --- /dev/null
>>>> +++ b/drivers/iio/timer/Kconfig
>>>> @@ -0,0 +1,13 @@
>>>> +#
>>>> +# Timers drivers
>>>> +
>>>> +menu "Timers"
>>>> +
>>>> +config IIO_STM32_TIMER_TRIGGER
>>>> + tristate "STM32 Timer Trigger"
>>>> + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST
>>>> + select IIO_TRIGGERED_EVENT
>>>> + help
>>>> + Select this option to enable STM32 Timer Trigger
>>>> +
>>>> +endmenu
>>>> diff --git a/drivers/iio/timer/Makefile b/drivers/iio/timer/Makefile
>>>> new file mode 100644
>>>> index 0000000..4ad95ec9
>>>> --- /dev/null
>>>> +++ b/drivers/iio/timer/Makefile
>>>> @@ -0,0 +1 @@
>>>> +obj-$(CONFIG_IIO_STM32_TIMER_TRIGGER) += stm32-timer-trigger.o
>>>> diff --git a/drivers/iio/timer/stm32-timer-trigger.c b/drivers/iio/timer/stm32-timer-trigger.c
>>>> new file mode 100644
>>>> index 0000000..8d16e8f
>>>> --- /dev/null
>>>> +++ b/drivers/iio/timer/stm32-timer-trigger.c
>>>> @@ -0,0 +1,466 @@
>>>> +/*
>>>> + * Copyright (C) STMicroelectronics 2016
>>>> + *
>>>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>> + *
>>>> + * License terms: GNU General Public License (GPL), version 2
>>>> + */
>>>> +
>>>> +#include <linux/iio/iio.h>
>>>> +#include <linux/iio/sysfs.h>
>>>> +#include <linux/iio/timer/stm32-timer-trigger.h>
>>>> +#include <linux/iio/trigger.h>
>>>> +#include <linux/iio/triggered_event.h>
>>>> +#include <linux/interrupt.h>
>>>> +#include <linux/mfd/stm32-timers.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/platform_device.h>
>>>> +
>>>> +#define MAX_TRIGGERS 6
>>>> +#define MAX_VALIDS 5
>>>> +
>>>> +/* List the triggers created by each timer */
>>>> +static const void *triggers_table[][MAX_TRIGGERS] = {
>>>> + { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
>>>> + { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
>>>> + { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
>>>> + { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
>>>> + { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
>>>> + { TIM6_TRGO,},
>>>> + { TIM7_TRGO,},
>>>> + { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
>>>> + { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
>>>> + { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
>>>> +};
>>>> +
>>>> +/* List the triggers accepted by each timer */
>>>> +static const void *valids_table[][MAX_VALIDS] = {
>>>> + { TIM5_TRGO, TIM2_TRGO, TIM4_TRGO, TIM3_TRGO,},
>>>> + { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
>>>> + { TIM1_TRGO, TIM8_TRGO, TIM5_TRGO, TIM4_TRGO,},
>>>> + { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
>>>> + { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
>>>> + { }, /* timer 6 */
>>>> + { }, /* timer 7 */
>>>> + { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
>>>> + { TIM2_TRGO, TIM3_TRGO,},
>>>> + { TIM4_TRGO, TIM5_TRGO,},
>>>> +};
>>>> +
>>>> +struct stm32_timer_trigger {
>>>> + struct device *dev;
>>>> + struct regmap *regmap;
>>>> + struct clk *clk;
>>>> + u32 max_arr;
>>>> + const void *triggers;
>>>> + const void *valids;
>>>> +};
>>>> +
>>>> +static int stm32_timer_start(struct stm32_timer_trigger *priv,
>>>> + unsigned int frequency)
>>>> +{
>>>> + unsigned long long prd, div;
>>>> + int prescaler = 0;
>>>> + u32 ccer, cr1;
>>>> +
>>>> + /* Period and prescaler values depends of clock rate */
>>>> + div = (unsigned long long)clk_get_rate(priv->clk);
>>>> +
>>>> + do_div(div, frequency);
>>>> +
>>>> + prd = div;
>>>> +
>>>> + /*
>>>> + * Increase prescaler value until we get a result that fit
>>>> + * with auto reload register maximum value.
>>>> + */
>>>> + while (div > priv->max_arr) {
>>>> + prescaler++;
>>>> + div = prd;
>>>> + do_div(div, (prescaler + 1));
>>>> + }
>>>> + prd = div;
>>>> +
>>>> + if (prescaler > MAX_TIM_PSC) {
>>>> + dev_err(priv->dev, "prescaler exceeds the maximum value\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + /* Check if nobody else use the timer */
>>>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>>>> + if (ccer & TIM_CCER_CCXE)
>>>> + return -EBUSY;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>> + if (!(cr1 & TIM_CR1_CEN))
>>>> + clk_enable(priv->clk);
>>>> +
>>>> + regmap_write(priv->regmap, TIM_PSC, prescaler);
>>>> + regmap_write(priv->regmap, TIM_ARR, prd - 1);
>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
>>>> +
>>>> + /* Force master mode to update mode */
>>>> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
>>>> +
>>>> + /* Make sure that registers are updated */
>>>> + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
>>>> +
>>>> + /* Enable controller */
>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static void stm32_timer_stop(struct stm32_timer_trigger *priv)
>>>> +{
>>>> + u32 ccer, cr1;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>>>> + if (ccer & TIM_CCER_CCXE)
>>>> + return;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>> + if (cr1 & TIM_CR1_CEN)
>>>> + clk_disable(priv->clk);
>>>> +
>>>> + /* Stop timer */
>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
>>>> + regmap_write(priv->regmap, TIM_PSC, 0);
>>>> + regmap_write(priv->regmap, TIM_ARR, 0);
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_store_frequency(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + const char *buf, size_t len)
>>>> +{
>>>> + struct iio_trigger *trig = to_iio_trigger(dev);
>>>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>>>> + unsigned int freq;
>>>> + int ret;
>>>> +
>>>> + ret = kstrtouint(buf, 10, &freq);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + if (freq == 0) {
>>>> + stm32_timer_stop(priv);
>>>> + } else {
>>>> + ret = stm32_timer_start(priv, freq);
>>>> + if (ret)
>>>> + return ret;
>>>> + }
>>>> +
>>>> + return len;
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_read_frequency(struct device *dev,
>>>> + struct device_attribute *attr, char *buf)
>>>> +{
>>>> + struct iio_trigger *trig = to_iio_trigger(dev);
>>>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>>>> + u32 psc, arr, cr1;
>>>> + unsigned long long freq = 0;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>> + regmap_read(priv->regmap, TIM_PSC, &psc);
>>>> + regmap_read(priv->regmap, TIM_ARR, &arr);
>>>> +
>>>> + if (psc && arr && (cr1 & TIM_CR1_CEN)) {
>>>> + freq = (unsigned long long)clk_get_rate(priv->clk);
>>>> + do_div(freq, psc);
>>>> + do_div(freq, arr);
>>>> + }
>>>> +
>>>> + return sprintf(buf, "%d\n", (unsigned int)freq);
>>>> +}
>>>> +
>>>> +static IIO_DEV_ATTR_SAMP_FREQ(0660,
>>>> + stm32_tt_read_frequency,
>>>> + stm32_tt_store_frequency);
>>>> +
>>>> +static struct attribute *stm32_trigger_attrs[] = {
>>>> + &iio_dev_attr_sampling_frequency.dev_attr.attr,
>>>> + NULL,
>>>> +};
>>>> +
>>>> +static const struct attribute_group stm32_trigger_attr_group = {
>>>> + .attrs = stm32_trigger_attrs,
>>>> +};
>>>> +
>>>> +static const struct attribute_group *stm32_trigger_attr_groups[] = {
>>>> + &stm32_trigger_attr_group,
>>>> + NULL,
>>>> +};
>>>> +
>>>> +static char *master_mode_table[] = {
>>>> + "reset",
>>>> + "enable",
>>>> + "update",
>>>> + "compare_pulse",
>>>> + "OC1REF",
>>>> + "OC2REF",
>>>> + "OC3REF",
>>>> + "OC4REF"
>>>> +};
>>>> +
>>>> +static ssize_t stm32_tt_show_master_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + char *buf)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + u32 cr2;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR2, &cr2);
>>>> + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
>>>> +
>>>> + return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_store_master_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + const char *buf, size_t len)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + int i;
>>>> +
>>>> + for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
>>>> + if (!strncmp(master_mode_table[i], buf,
>>>> + strlen(master_mode_table[i]))) {
>>>> + regmap_update_bits(priv->regmap, TIM_CR2,
>>>> + TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
>>>> + return len;
>>>> + }
>>>> + }
>>>> +
>>>> + return -EINVAL;
>>>> +}
>>>> +
>>>> +static IIO_CONST_ATTR(master_mode_available,
>>>> + "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
>>>> +
>>>> +static IIO_DEVICE_ATTR(master_mode, 0660,
>>>> + stm32_tt_show_master_mode,
>>>> + stm32_tt_store_master_mode,
>>>> + 0);
>>>> +
>>>> +static char *slave_mode_table[] = {
>>>> + "disabled",
>>>> + "encoder_1",
>>>> + "encoder_2",
>>>> + "encoder_3",
>>>> + "reset",
>>>> + "gated",
>>>> + "trigger",
>>>> + "external_clock",
>>>> +};
>>>> +
>>>> +static ssize_t stm32_tt_show_slave_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + char *buf)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + u32 smcr;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_SMCR, &smcr);
>>>> + smcr &= TIM_SMCR_SMS;
>>>> +
>>>> + return snprintf(buf, PAGE_SIZE, "%s\n", slave_mode_table[smcr]);
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_store_slave_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + const char *buf, size_t len)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + int i;
>>>> +
>>>> + for (i = 0; i < ARRAY_SIZE(slave_mode_table); i++) {
>>>> + if (!strncmp(slave_mode_table[i], buf,
>>>> + strlen(slave_mode_table[i]))) {
>>>> + regmap_update_bits(priv->regmap,
>>>> + TIM_SMCR, TIM_SMCR_SMS, i);
>>>> + return len;
>>>> + }
>>>> + }
>>>> +
>>>> + return -EINVAL;
>>>> +}
>>>> +
>>>> +static IIO_CONST_ATTR(slave_mode_available,
>>>> +"disabled encoder_1 encoder_2 encoder_3 reset gated trigger external_clock");
>>>> +
>>>> +static IIO_DEVICE_ATTR(slave_mode, 0660,
>>>> + stm32_tt_show_slave_mode,
>>>> + stm32_tt_store_slave_mode,
>>>> + 0);
>>>> +
>>>> +static struct attribute *stm32_timer_attrs[] = {
>>>> + &iio_dev_attr_master_mode.dev_attr.attr,
>>>> + &iio_const_attr_master_mode_available.dev_attr.attr,
>>>> + &iio_dev_attr_slave_mode.dev_attr.attr,
>>>> + &iio_const_attr_slave_mode_available.dev_attr.attr,
>>>> + NULL,
>>>> +};
>>>> +
>>>> +static const struct attribute_group stm32_timer_attr_group = {
>>>> + .attrs = stm32_timer_attrs,
>>>> +};
>>>> +
>>>> +static const struct iio_trigger_ops timer_trigger_ops = {
>>>> + .owner = THIS_MODULE,
>>>> +};
>>>> +
>>>> +static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
>>>> +{
>>>> + int ret;
>>>> + const char * const *cur = priv->triggers;
>>>> +
>>>> + while (cur && *cur) {
>>>> + struct iio_trigger *trig;
>>>> +
>>>> + trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
>>>> + if (!trig)
>>>> + return -ENOMEM;
>>>> +
>>>> + trig->dev.parent = priv->dev->parent;
>>>> + trig->ops = &timer_trigger_ops;
>>>> + trig->dev.groups = stm32_trigger_attr_groups;
>>>> + iio_trigger_set_drvdata(trig, priv);
>>>> +
>>>> + ret = devm_iio_trigger_register(priv->dev, trig);
>>>> + if (ret)
>>>> + return ret;
>>>> + cur++;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +/**
>>>> + * is_stm32_timer_trigger
>>>> + * @trig: trigger to be checked
>>>> + *
>>>> + * return true if the trigger is a valid stm32 iio timer trigger
>>>> + * either return false
>>>> + */
>>>> +bool is_stm32_timer_trigger(struct iio_trigger *trig)
>>>> +{
>>>> + return (trig->ops == &timer_trigger_ops);
>>>> +}
>>>> +EXPORT_SYMBOL(is_stm32_timer_trigger);
>>>> +
>>>> +static int stm32_validate_trigger(struct iio_dev *indio_dev,
>>>> + struct iio_trigger *trig)
>>>> +{
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + const char * const *cur = priv->valids;
>>>> + unsigned int i = 0;
>>>> +
>>>> + if (!is_stm32_timer_trigger(trig))
>>>> + return -EINVAL;
>>>> +
>>>> + while (cur && *cur) {
>>>> + if (!strncmp(trig->name, *cur, strlen(trig->name))) {
>>>> + regmap_update_bits(priv->regmap,
>>>> + TIM_SMCR, TIM_SMCR_TS,
>>>> + i << TIM_SMCR_TS_SHIFT);
>>>> + return 0;
>>>> + }
>>>> + cur++;
>>>> + i++;
>>>> + }
>>>> +
>>>> + return -EINVAL;
>>>> +}
>>>> +
>>>> +static const struct iio_info stm32_trigger_info = {
>>>> + .driver_module = THIS_MODULE,
>>>> + .validate_trigger = stm32_validate_trigger,
>>>> + .attrs = &stm32_timer_attr_group,
>>>> +};
>>>> +
>>>> +static struct stm32_timer_trigger *stm32_setup_iio_device(struct device *dev)
>>>> +{
>>>> + struct iio_dev *indio_dev;
>>>> + int ret;
>>>> +
>>>> + indio_dev = devm_iio_device_alloc(dev,
>>>> + sizeof(struct stm32_timer_trigger));
>>>> + if (!indio_dev)
>>>> + return NULL;
>>>> +
>>>> + indio_dev->name = dev_name(dev);
>>>> + indio_dev->dev.parent = dev;
>>>> + indio_dev->info = &stm32_trigger_info;
>>>> + indio_dev->modes = INDIO_EVENT_TRIGGERED;
>>>> + indio_dev->num_channels = 0;
>>>> + indio_dev->dev.of_node = dev->of_node;
>>>> +
>>>> + ret = devm_iio_device_register(dev, indio_dev);
>>>> + if (ret)
>>>> + return NULL;
>>>> +
>>>> + return iio_priv(indio_dev);
>>>> +}
>>>> +
>>>> +static int stm32_timer_trigger_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct device *dev = &pdev->dev;
>>>> + struct stm32_timer_trigger *priv;
>>>> + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
>>>> + unsigned int index;
>>>> + int ret;
>>>> +
>>>> + if (of_property_read_u32(dev->of_node, "reg", &index))
>>>> + return -EINVAL;
>>>> +
>>>> + if (index >= ARRAY_SIZE(triggers_table))
>>>> + return -EINVAL;
>>>> +
>>>> + /* Create an IIO device only if we have triggers to be validated */
>>>> + if (*valids_table[index])
>>>> + priv = stm32_setup_iio_device(dev);
>>>
>>> I still don't like this. Really feels like we shouldn't be creating an
>>> iio device with all the bagage that carries just to allow us to do the
>>> trigger trees. We ought to have a much more light weight solution for this
>>> functionality - we aren't typically even using the interrupt tree stuff
>>> that the triggers for devices are all really about.
>>>
>>> A simpler approach of allowing each trigger the option of a parent seems like
>>> it would be cleaner. Could be done entirely within this driver in the first
>>> instance. Basically it would just look like your master and slave attributes
>>> but have those under triggerX not iio:deviceX.
>>>
>>> We can work out how to make it more generic later - including perhaps the
>>> option to trigger from triggers outside this driver, using some parallel
>>> infrastructure to the device triggering.
>>>
>>>
>>>> + else
>>>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>>>> +
>>>> + if (!priv)
>>>> + return -ENOMEM;
>>>> +
>>>> + priv->dev = dev;
>>>> + priv->regmap = ddata->regmap;
>>>> + priv->clk = ddata->clk;
>>>> + priv->max_arr = ddata->max_arr;
>>>> + priv->triggers = triggers_table[index];
>>>> + priv->valids = valids_table[index];
>>>> +
>>>> + ret = stm32_setup_iio_triggers(priv);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + platform_set_drvdata(pdev, priv);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static const struct of_device_id stm32_trig_of_match[] = {
>>>> + { .compatible = "st,stm32-timer-trigger", },
>>>> + { /* end node */ },
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
>>>> +
>>>> +static struct platform_driver stm32_timer_trigger_driver = {
>>>> + .probe = stm32_timer_trigger_probe,
>>>> + .driver = {
>>>> + .name = "stm32-timer-trigger",
>>>> + .of_match_table = stm32_trig_of_match,
>>>> + },
>>>> +};
>>>> +module_platform_driver(stm32_timer_trigger_driver);
>>>> +
>>>> +MODULE_ALIAS("platform: stm32-timer-trigger");
>>>> +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
>>>> +MODULE_LICENSE("GPL v2");
>>>> diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig
>>>> index 809b2e7..f2af4fe 100644
>>>> --- a/drivers/iio/trigger/Kconfig
>>>> +++ b/drivers/iio/trigger/Kconfig
>>>> @@ -46,5 +46,4 @@ config IIO_SYSFS_TRIGGER
>>>>
>>>> To compile this driver as a module, choose M here: the
>>>> module will be called iio-trig-sysfs.
>>>> -
>>> Clean this up.
>>
>> ok
>>
>>>> endmenu
>>>> diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h
>>>> new file mode 100644
>>>> index 0000000..55535ae
>>>> --- /dev/null
>>>> +++ b/include/linux/iio/timer/stm32-timer-trigger.h
>>>> @@ -0,0 +1,62 @@
>>>> +/*
>>>> + * Copyright (C) STMicroelectronics 2016
>>>> + *
>>>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>> + *
>>>> + * License terms: GNU General Public License (GPL), version 2
>>>> + */
>>>> +
>>>> +#ifndef _STM32_TIMER_TRIGGER_H_
>>>> +#define _STM32_TIMER_TRIGGER_H_
>>>> +
>>>> +#define TIM1_TRGO "tim1_trgo"
>>>> +#define TIM1_CH1 "tim1_ch1"
>>>> +#define TIM1_CH2 "tim1_ch2"
>>>> +#define TIM1_CH3 "tim1_ch3"
>>>> +#define TIM1_CH4 "tim1_ch4"
>>>> +
>>>> +#define TIM2_TRGO "tim2_trgo"
>>>> +#define TIM2_CH1 "tim2_ch1"
>>>> +#define TIM2_CH2 "tim2_ch2"
>>>> +#define TIM2_CH3 "tim2_ch3"
>>>> +#define TIM2_CH4 "tim2_ch4"
>>>> +
>>>> +#define TIM3_TRGO "tim3_trgo"
>>>> +#define TIM3_CH1 "tim3_ch1"
>>>> +#define TIM3_CH2 "tim3_ch2"
>>>> +#define TIM3_CH3 "tim3_ch3"
>>>> +#define TIM3_CH4 "tim3_ch4"
>>>> +
>>>> +#define TIM4_TRGO "tim4_trgo"
>>>> +#define TIM4_CH1 "tim4_ch1"
>>>> +#define TIM4_CH2 "tim4_ch2"
>>>> +#define TIM4_CH3 "tim4_ch3"
>>>> +#define TIM4_CH4 "tim4_ch4"
>>>> +
>>>> +#define TIM5_TRGO "tim5_trgo"
>>>> +#define TIM5_CH1 "tim5_ch1"
>>>> +#define TIM5_CH2 "tim5_ch2"
>>>> +#define TIM5_CH3 "tim5_ch3"
>>>> +#define TIM5_CH4 "tim5_ch4"
>>>> +
>>>> +#define TIM6_TRGO "tim6_trgo"
>>>> +
>>>> +#define TIM7_TRGO "tim7_trgo"
>>>> +
>>>> +#define TIM8_TRGO "tim8_trgo"
>>>> +#define TIM8_CH1 "tim8_ch1"
>>>> +#define TIM8_CH2 "tim8_ch2"
>>>> +#define TIM8_CH3 "tim8_ch3"
>>>> +#define TIM8_CH4 "tim8_ch4"
>>>> +
>>>> +#define TIM9_TRGO "tim9_trgo"
>>>> +#define TIM9_CH1 "tim9_ch1"
>>>> +#define TIM9_CH2 "tim9_ch2"
>>>> +
>>>> +#define TIM12_TRGO "tim12_trgo"
>>>> +#define TIM12_CH1 "tim12_ch1"
>>>> +#define TIM12_CH2 "tim12_ch2"
>>>> +
>>>> +bool is_stm32_timer_trigger(struct iio_trigger *trig);
>>>> +
>>>> +#endif
>>>>
>>>
>>
>>
>>
>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH] drm/meson: Fix plane atomic check when no crtc for the plane
From: Neil Armstrong @ 2017-01-03 9:20 UTC (permalink / raw)
To: linux-arm-kernel
When no CRTC is associated with the plane, the meson_plane_atomic_check()
call breaks the kernel with an Oops.
Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index 4942ca0..7890e30 100644
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -51,6 +51,9 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
struct drm_crtc_state *crtc_state;
struct drm_rect clip = { 0, };
+ if (!state->crtc)
+ return 0;
+
crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
--
1.9.1
^ permalink raw reply related
* [PATCH] ARM: davinci_all_defconfig: enable dumb vga-dac drm bridge
From: Sekhar Nori @ 2017-01-03 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480065182-7095-1-git-send-email-bgolaszewski@baylibre.com>
On Friday 25 November 2016 02:43 PM, Bartosz Golaszewski wrote:
> This enables the dumb-vga-dac driver by default for davinci boards.
>
> The driver is needed for tilcdc support on da850-lcdk board.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> arch/arm/configs/davinci_all_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
> index b5e978f..ab1bf18 100644
> --- a/arch/arm/configs/davinci_all_defconfig
> +++ b/arch/arm/configs/davinci_all_defconfig
> @@ -127,6 +127,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_REGULATOR_TPS6507X=y
> CONFIG_DRM=m
> CONFIG_DRM_TILCDC=m
> +CONFIG_DRM_BRIDGE=y
DRM_BRIDGE is a 'def_bool y'. So no need to explicitly enable it. And
actually it will get dropped with the next savedefconfig refresh anyway.
Applying this patch with this line dropped.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v2 1/2] mtd: ifc: Update dependency of IFC for LS1021A
From: Alison Wang @ 2017-01-03 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103100439.6e7360c6@bbrezillon>
Ok, I see. Thanks.
Best Regards,
Alison Wang
> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon at free-electrons.com]
> Sent: Tuesday, January 03, 2017 5:05 PM
> To: Alison Wang <b18965@freescale.com>
> Cc: marek.vasut at gmail.com; cyrille.pitchen at atmel.com; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> mtd at lists.infradead.org; dwmw2 at infradead.org;
> computersforpeace at gmail.com; Alison Wang <alison.wang@nxp.com>
> Subject: Re: [PATCH v2 1/2] mtd: ifc: Update dependency of IFC for
> LS1021A
>
> Hi Alison,
>
> The subject prefix should be "memory: " and not "mtd: ifc: ".
>
> Looks good otherwise.
>
> No need to resend, I can fix that when applying.
>
> Regards,
>
> Boris
>
> On Tue, 3 Jan 2017 10:41:05 +0800
> Alison Wang <b18965@freescale.com> wrote:
>
> > As Freescale/NXP IFC controller is available on LS1021A, the
> > dependency for LS1021A is added.
> >
> > Signed-off-by: Alison Wang <alison.wang@nxp.com>
> > ---
> > Changes in v2:
> > - New patch
> >
> > drivers/memory/Kconfig | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index
> > ec80e35..fff8345 100644
> > --- a/drivers/memory/Kconfig
> > +++ b/drivers/memory/Kconfig
> > @@ -115,7 +115,7 @@ config FSL_CORENET_CF
> >
> > config FSL_IFC
> > bool
> > - depends on FSL_SOC || ARCH_LAYERSCAPE
> > + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
> >
> > config JZ4780_NEMC
> > bool "Ingenic JZ4780 SoC NEMC driver"
^ permalink raw reply
* [PATCH 1/4] mmc: mediatek: Fix CMD6 timeout issue
From: Yong Mao @ 2017-01-03 9:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPDyKFosQkxaFAKo0dm0TajgXqKG7XqRM1tTqR2vTsHzVrocfQ@mail.gmail.com>
On Thu, 2016-12-01 at 10:51 +0100, Ulf Hansson wrote:
> On 8 November 2016 at 07:08, Yong Mao <yong.mao@mediatek.com> wrote:
> > From: yong mao <yong.mao@mediatek.com>
> >
> > When initializing EMMC, after switch to HS400,
> > it will issue CMD6 to change ext_csd, if first CMD6 got CRC
> > error, the repeat CMD6 may get timeout, that's
> > because SDCBSY was cleared by msdc_reset_hw()
>
> Sorry for the delay!
>
> We have recently been re-working the sequence for how to deal more
> properly with CMD6 in the mmc core.
>
> The changes done so far should mostly concern switches to HS and HS
> DDR, but I think you should run a re-test to make sure you still hit
> the same problems.
>
Happy New Year!
The issue we met is not only just for CMD6, but also for other R1B CMD.
Your new changes does not cover all of these cases.
We would like to make error handle in the core layer to deal with these
issues.
I had submitted a new path ([PATCH v2] Fix CMD6 timeout issue) to you,
please help to review it.
Thanks.
> >
> > Signed-off-by: Yong Mao <yong.mao@mediatek.com>
> > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
> > ---
> > drivers/mmc/host/mtk-sd.c | 77 ++++++++++++++++++++++++++++++---------------
> > 1 file changed, 51 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> > index 84e9afc..b29683b 100644
> > --- a/drivers/mmc/host/mtk-sd.c
> > +++ b/drivers/mmc/host/mtk-sd.c
> > @@ -826,6 +826,15 @@ static bool msdc_cmd_done(struct msdc_host *host, int events,
> > return true;
> > }
> >
> > +static int msdc_card_busy(struct mmc_host *mmc)
> > +{
> > + struct msdc_host *host = mmc_priv(mmc);
> > + u32 status = readl(host->base + MSDC_PS);
> > +
> > + /* check if data0 is low */
> > + return !(status & BIT(16));
> > +}
> > +
> > /* It is the core layer's responsibility to ensure card status
> > * is correct before issue a request. but host design do below
> > * checks recommended.
>
> Hmm. Why?
>
> I think you should rely on the mmc core to invoke the ->card_busy()
> ops instead. The core knows better when it's needed.
>
> Perhaps that may also resolve some of these issues for you!?
In my latest patch, msdc_card_busy will not be used in mtk-sd.c
directly. It only can be invoked by ->card_busy() in the mmc core.
>
> > @@ -835,10 +844,20 @@ static inline bool msdc_cmd_is_ready(struct msdc_host *host,
> > {
> > /* The max busy time we can endure is 20ms */
> > unsigned long tmo = jiffies + msecs_to_jiffies(20);
> > + u32 count = 0;
> > +
> > + if (in_interrupt()) {
> > + while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
> > + (count < 1000)) {
> > + udelay(1);
> > + count++;
>
> This seems like a bad idea, "busy-wait" in irq context is never a good idea.
Thanks. The modification here is not for the current issue.
I will submit a new patch to discuss with you.
> > + }
> > + } else {
> > + while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
> > + time_before(jiffies, tmo))
> > + cpu_relax();
> > + }
> >
> > - while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
> > - time_before(jiffies, tmo))
> > - cpu_relax();
> > if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
> > dev_err(host->dev, "CMD bus busy detected\n");
> > host->error |= REQ_CMD_BUSY;
> > @@ -846,17 +865,35 @@ static inline bool msdc_cmd_is_ready(struct msdc_host *host,
> > return false;
> > }
> >
> > - if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
> > - tmo = jiffies + msecs_to_jiffies(20);
> > - /* R1B or with data, should check SDCBUSY */
> > - while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
> > - time_before(jiffies, tmo))
> > - cpu_relax();
> > - if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
> > - dev_err(host->dev, "Controller busy detected\n");
> > - host->error |= REQ_CMD_BUSY;
> > - msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
> > - return false;
> > + if (cmd->opcode != MMC_SEND_STATUS) {
> > + count = 0;
> > + /* Consider that CMD6 crc error before card was init done,
> > + * mmc_retune() will return directly as host->card is null.
> > + * and CMD6 will retry 3 times, must ensure card is in transfer
> > + * state when retry.
> > + */
> > + tmo = jiffies + msecs_to_jiffies(60 * 1000);
> > + while (1) {
> > + if (msdc_card_busy(host->mmc)) {
> > + if (in_interrupt()) {
> > + udelay(1);
> > + count++;
> > + } else {
> > + msleep_interruptible(10);
> > + }
> > + } else {
> > + break;
> > + }
> > + /* Timeout if the device never
> > + * leaves the program state.
> > + */
> > + if (count > 1000 || time_after(jiffies, tmo)) {
> > + pr_err("%s: Card stuck in programming state! %s\n",
> > + mmc_hostname(host->mmc), __func__);
> > + host->error |= REQ_CMD_BUSY;
> > + msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
> > + return false;
> > + }
>
> This hole new code is a hack, that shouldn't be needed in the host driver.
>
> I think we need to investigate and fix the issue in the mmc core
> layer, to make this work for your host driver. That instead of doing a
> work around in the host.
>
I had already make some modification on the mmc core to resolve these
issues in the latest patch.
> > }
> > }
> > return true;
> > @@ -1070,18 +1107,6 @@ static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
> > return ret;
> > }
> >
> > -static int msdc_card_busy(struct mmc_host *mmc)
> > -{
> > - struct msdc_host *host = mmc_priv(mmc);
> > - u32 status = readl(host->base + MSDC_PS);
> > -
> > - /* check if any pin between dat[0:3] is low */
> > - if (((status >> 16) & 0xf) != 0xf)
> > - return 1;
> > -
> > - return 0;
> > -}
> > -
> > static void msdc_request_timeout(struct work_struct *work)
> > {
> > struct msdc_host *host = container_of(work, struct msdc_host,
> > --
> > 1.7.9.5
> >
>
> Kind regards
> Uffe
^ permalink raw reply
* [PATCH] mtd: nand: lpc32xx: fix invalid error handling of a requested irq
From: Boris Brezillon @ 2017-01-03 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205014710.2015-1-vz@mleia.com>
Hi Vladimir
On Mon, 5 Dec 2016 03:47:10 +0200
Vladimir Zapolskiy <vz@mleia.com> wrote:
> Semantics of NR_IRQS is different on machines with SPARSE_IRQ option
> disabled or enabled, in the latter case IRQs are allocated starting
> at least from the value specified by NR_IRQS and going upwards, so
> the check of (irq >= NR_IRQ) to decide about an error code returned by
> platform_get_irq() is completely invalid, don't attempt to overrule
> irq subsystem in the driver.
>
> The change fixes LPC32xx NAND MLC driver initialization on boot.
Do you need to backport this fix to stable releases? If that's the
case, I'll add the Cc: stable tag when applying.
Thanks,
Boris
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> drivers/mtd/nand/lpc32xx_mlc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/lpc32xx_mlc.c b/drivers/mtd/nand/lpc32xx_mlc.c
> index 8523881..bc6e49a 100644
> --- a/drivers/mtd/nand/lpc32xx_mlc.c
> +++ b/drivers/mtd/nand/lpc32xx_mlc.c
> @@ -776,7 +776,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
> init_completion(&host->comp_controller);
>
> host->irq = platform_get_irq(pdev, 0);
> - if ((host->irq < 0) || (host->irq >= NR_IRQS)) {
> + if (host->irq < 0) {
> dev_err(&pdev->dev, "failed to get platform irq\n");
> res = -EINVAL;
> goto err_exit3;
^ permalink raw reply
* [PATCH v6 0/5] davinci: VPIF: add DT support
From: Laurent Pinchart @ 2017-01-03 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4a03b56e-1e01-8b2c-c2a1-1b72d30f103a@ti.com>
Hi Sekhar,
On Tuesday 03 Jan 2017 14:33:00 Sekhar Nori wrote:
> On Friday 16 December 2016 03:17 PM, Hans Verkuil wrote:
> > On 07/12/16 19:30, Kevin Hilman wrote:
> >> Prepare the groundwork for adding DT support for davinci VPIF drivers.
> >> This series does some fixups/cleanups and then adds the DT binding and
> >> DT compatible string matching for DT probing.
> >>
> >> The controversial part from previous versions around async subdev
> >> parsing, and specifically hard-coding the input/output routing of
> >> subdevs, has been left out of this series. That part can be done as a
> >> follow-on step after agreement has been reached on the path forward.
> >> With this version, platforms can still use the VPIF capture/display
> >> drivers, but must provide platform_data for the subdevs and subdev
> >> routing.
> >>
> >> Tested video capture to memory on da850-lcdk board using composite
> >> input.
> >
> > Other than the comment for the first patch this series looks good.
> >
> > So once that's addressed I'll queue it up for 4.11.
>
> Can you provide an immutable commit (as it will reach v4.11) with with
> this series applied? I have some platform changes to queue for v4.11
> that depend on the driver updates.
I don't think that's possible, given that Mauro rewrites all patches when
handling pull requests to prepend [media] to the subject line and to add his
SoB. Only Mauro can thus provide a stable branch, Hans can't.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH v2 1/2] mtd: ifc: Update dependency of IFC for LS1021A
From: Boris Brezillon @ 2017-01-03 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483411266-45875-1-git-send-email-b18965@freescale.com>
Hi Alison,
The subject prefix should be "memory: " and not "mtd: ifc: ".
Looks good otherwise.
No need to resend, I can fix that when applying.
Regards,
Boris
On Tue, 3 Jan 2017 10:41:05 +0800
Alison Wang <b18965@freescale.com> wrote:
> As Freescale/NXP IFC controller is available on LS1021A, the dependency
> for LS1021A is added.
>
> Signed-off-by: Alison Wang <alison.wang@nxp.com>
> ---
> Changes in v2:
> - New patch
>
> drivers/memory/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> index ec80e35..fff8345 100644
> --- a/drivers/memory/Kconfig
> +++ b/drivers/memory/Kconfig
> @@ -115,7 +115,7 @@ config FSL_CORENET_CF
>
> config FSL_IFC
> bool
> - depends on FSL_SOC || ARCH_LAYERSCAPE
> + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
>
> config JZ4780_NEMC
> bool "Ingenic JZ4780 SoC NEMC driver"
^ permalink raw reply
* [PATCH] ARM: davinci_all_defconfig: enable dumb vga-dac drm bridge
From: Bartosz Golaszewski @ 2017-01-03 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480065182-7095-1-git-send-email-bgolaszewski@baylibre.com>
2016-11-25 10:13 GMT+01:00 Bartosz Golaszewski <bgolaszewski@baylibre.com>:
> This enables the dumb-vga-dac driver by default for davinci boards.
>
> The driver is needed for tilcdc support on da850-lcdk board.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> arch/arm/configs/davinci_all_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
> index b5e978f..ab1bf18 100644
> --- a/arch/arm/configs/davinci_all_defconfig
> +++ b/arch/arm/configs/davinci_all_defconfig
> @@ -127,6 +127,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_REGULATOR_TPS6507X=y
> CONFIG_DRM=m
> CONFIG_DRM_TILCDC=m
> +CONFIG_DRM_BRIDGE=y
> +CONFIG_DRM_DUMB_VGA_DAC=m
> CONFIG_FB=y
> CONFIG_FIRMWARE_EDID=y
> CONFIG_FB_DA8XX=y
> --
> 2.9.3
>
Hi Sekhar,
ping for this patch - it's been stuck on the list since November. I
suppose it got lost in your queue.
Thanks,
Bartosz
^ permalink raw reply
* [PATCH v6 0/5] davinci: VPIF: add DT support
From: Sekhar Nori @ 2017-01-03 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d4b0501a-f83a-c8b1-e460-1ba50f68cca7@xs4all.nl>
Hi Hans,
On Friday 16 December 2016 03:17 PM, Hans Verkuil wrote:
> On 07/12/16 19:30, Kevin Hilman wrote:
>> Prepare the groundwork for adding DT support for davinci VPIF drivers.
>> This series does some fixups/cleanups and then adds the DT binding and
>> DT compatible string matching for DT probing.
>>
>> The controversial part from previous versions around async subdev
>> parsing, and specifically hard-coding the input/output routing of
>> subdevs, has been left out of this series. That part can be done as a
>> follow-on step after agreement has been reached on the path forward.
>> With this version, platforms can still use the VPIF capture/display
>> drivers, but must provide platform_data for the subdevs and subdev
>> routing.
>>
>> Tested video capture to memory on da850-lcdk board using composite
>> input.
>
> Other than the comment for the first patch this series looks good.
>
> So once that's addressed I'll queue it up for 4.11.
Can you provide an immutable commit (as it will reach v4.11) with with
this series applied? I have some platform changes to queue for v4.11
that depend on the driver updates.
Thanks,
Sekhar
^ permalink raw reply
* [v2, 1/4] ARM: davinci: da8xx-dt: Add ti-aemif lookup for clock matching
From: Sekhar Nori @ 2017-01-03 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <72eb6441-6463-abd8-65e6-06772b925999@ti.com>
On Monday 02 January 2017 01:34 PM, Sekhar Nori wrote:
> On Saturday 31 December 2016 06:22 AM, David Lechner wrote:
>> On 08/10/2016 06:00 AM, Karl Beldan wrote:
>>> Many davinci boards (da830 and da850 families) don't have their clocks
>>> in DT yet and won't be successful in getting an unnamed aemif clock
>>> without explicitly registering them via clk_lookups, failing the
>>> ti-aemif memory driver probe.
>>>
>>> The current aemif lookup entry resolving to the same clock:
>>> 'CLK(NULL, "aemif", &aemif_clk)'
>>> remains, as it is currently used (davinci_nand is getting a named clock
>>> "aemif").
>>>
>>> This change will allow to switch from the mach-davinci aemif code to
>>> the ti-aemif memory driver.
>>>
>>> Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
>>> ---
>>
>> FYI, I can't boot LEGO MINDSTORMS EV3 (AM1908) with a v4.9 mainline
>> kernel. I did a git bisect and traced it down to this patch. I'm
>> guessing that simply reverting it will break other things.
>>
>> The problem is that &aemif_clk is a node in a linked list and points to
>> itself, which creates an infinite loop when looking up the usb clocks
>> that are later in the list.
>>
>> I thought there was a patch to fix this properly from one of the Bay
>> Libre guys to fix this already, but I can't seem to find it at the
>> moment. When it is found, it would be good to have it applied to the 4.9
>> stable and 4.10 mainline trees.
>
> Yes, a patch was submitted. It is pending in my queue since I need to do
> a few experiments myself to determine if its the best solution possible.
> Thanks for the heads-up on need to mark it for v4.9 stable. Will do.
The master branch of my tree should have the patch included. If you can
test and confirm it works fine on the lego platform, it will be great.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v2 3/4] ARM: davinci: da8xx: add pdata-quirks, use for VPIF capture
From: Sekhar Nori @ 2017-01-03 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207193137.27947-4-khilman@baylibre.com>
Hi Kevin,
On Thursday 08 December 2016 01:01 AM, Kevin Hilman wrote:
> Add pdata-quirks for da8xx DT platforms, which adds the legacy platform
> data for vpif_capture driver.
>
> Passing legacy platform_data is required until the V4L2 framework, and
> subdevice drivers (such as the tvp514x) grow a way of selecting input
> and output routing (c.f. V4L2 s_routing API)
>
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
> ---
> arch/arm/mach-davinci/Makefile | 2 +-
> arch/arm/mach-davinci/da8xx-dt.c | 2 +
> arch/arm/mach-davinci/include/mach/common.h | 4 +
> arch/arm/mach-davinci/pdata-quirks.c | 155 ++++++++++++++++++++++++++++
> 4 files changed, 162 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-davinci/pdata-quirks.c
Can you please split this to separate addition of pdata quirks from
adding vpif capture support. I think it is fine to have a pre-patch
adding support for pdata quirks with just the sentinel included.
>
> diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
> index da4c336b4637..90d2e6e4d913 100644
> --- a/arch/arm/mach-davinci/Makefile
> +++ b/arch/arm/mach-davinci/Makefile
> @@ -21,7 +21,7 @@ obj-$(CONFIG_AINTC) += irq.o
> obj-$(CONFIG_CP_INTC) += cp_intc.o
>
> # Board specific
> -obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o
> +obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
> obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
> obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
> obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
> diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
> index c9f7e9274aa8..69c8099de9f5 100644
> --- a/arch/arm/mach-davinci/da8xx-dt.c
> +++ b/arch/arm/mach-davinci/da8xx-dt.c
> @@ -38,6 +38,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
> NULL),
> OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
> OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL),
> + OF_DEV_AUXDATA("ti,da850-vpif", 0x01e17000, "vpif", NULL),
> {}
> };
>
> @@ -46,6 +47,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
> static void __init da850_init_machine(void)
> {
> of_platform_default_populate(NULL, da850_auxdata_lookup, NULL);
> + pdata_quirks_init();
> }
>
> static const char *const da850_boards_compat[] __initconst = {
> diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
> index 0b3c169758ed..1fd4cd2d1c23 100644
> --- a/arch/arm/mach-davinci/include/mach/common.h
> +++ b/arch/arm/mach-davinci/include/mach/common.h
> @@ -102,6 +102,10 @@ int davinci_pm_init(void);
> static inline int davinci_pm_init(void) { return 0; }
> #endif
>
> +#ifdef CONFIG_MACH_DA8XX_DT
> +extern void __init pdata_quirks_init(void);
I noticed that checkpatch complains about the extern (with strict
warnings turned on). I think its better to drop it. I know you probably
added it to be consistent with other declarations in the file.
> +#endif
> +
> #define SRAM_SIZE SZ_128K
>
> #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
> diff --git a/arch/arm/mach-davinci/pdata-quirks.c b/arch/arm/mach-davinci/pdata-quirks.c
> new file mode 100644
> index 000000000000..a186513edf7e
> --- /dev/null
> +++ b/arch/arm/mach-davinci/pdata-quirks.c
> @@ -0,0 +1,155 @@
> +/*
> + * Legacy platform_data quirks
> + *
> + * Copyright (C) 2016 BayLibre, Inc
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/kernel.h>
> +#include <linux/of_platform.h>
> +
> +#include <media/i2c/tvp514x.h>
> +
> +#include <mach/common.h>
> +#include <mach/da8xx.h>
> +#include <mach/mux.h>
The mux.h include can be dropped after you dropped the muxing from this
patch.
> +
> +struct pdata_init {
> + const char *compatible;
> + void (*fn)(void);
> +};
> +
> +#if IS_ENABLED(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE)
> +
> +#define TVP5147_CH0 "tvp514x-0"
> +#define TVP5147_CH1 "tvp514x-1"
> +
> +/* VPIF capture configuration */
> +static struct tvp514x_platform_data tvp5146_pdata = {
> + .clk_polarity = 0,
> + .hs_polarity = 1,
> + .vs_polarity = 1,
> +};
> +
> +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
> +
> +static const struct vpif_input da850_ch0_inputs[] = {
> + {
> + .input = {
> + .index = 0,
> + .name = "Composite",
> + .type = V4L2_INPUT_TYPE_CAMERA,
> + .capabilities = V4L2_IN_CAP_STD,
> + .std = TVP514X_STD_ALL,
> + },
> + .input_route = INPUT_CVBS_VI2B,
> + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
> + .subdev_name = TVP5147_CH0,
> + },
> +};
> +
> +static const struct vpif_input da850_ch1_inputs[] = {
> + {
> + .input = {
> + .index = 0,
> + .name = "S-Video",
> + .type = V4L2_INPUT_TYPE_CAMERA,
> + .capabilities = V4L2_IN_CAP_STD,
> + .std = TVP514X_STD_ALL,
> + },
> + .input_route = INPUT_SVIDEO_VI2C_VI1C,
> + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
> + .subdev_name = TVP5147_CH1,
> + },
> +};
> +
> +static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
> + {
> + .name = TVP5147_CH0,
> + .board_info = {
> + I2C_BOARD_INFO("tvp5146", 0x5d),
> + .platform_data = &tvp5146_pdata,
> + },
> + },
> + {
> + .name = TVP5147_CH1,
> + .board_info = {
> + I2C_BOARD_INFO("tvp5146", 0x5c),
> + .platform_data = &tvp5146_pdata,
> + },
> + },
> +};
> +
> +static struct vpif_capture_config da850_vpif_capture_config = {
> + .subdev_info = da850_vpif_capture_sdev_info,
> + .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
> + .chan_config[0] = {
> + .inputs = da850_ch0_inputs,
> + .input_count = ARRAY_SIZE(da850_ch0_inputs),
> + .vpif_if = {
> + .if_type = VPIF_IF_BT656,
> + .hd_pol = 1,
> + .vd_pol = 1,
> + .fid_pol = 0,
> + },
> + },
> + .chan_config[1] = {
> + .inputs = da850_ch1_inputs,
> + .input_count = ARRAY_SIZE(da850_ch1_inputs),
> + .vpif_if = {
> + .if_type = VPIF_IF_BT656,
> + .hd_pol = 1,
> + .vd_pol = 1,
> + .fid_pol = 0,
> + },
> + },
> + .card_name = "DA850/OMAP-L138 Video Capture",
> +};
> +
> +static void __init da850_vpif_legacy_init(void)
> +{
> + int ret;
> +
> + /* LCDK doesn't have the 2nd TVP514x on CH1 */
> + if (of_machine_is_compatible("ti,da850-lcdk"))
> + da850_vpif_capture_config.subdev_count = 1;
> +
> + /* EVM (UI card) uses i2c adapter 1 (not default: zero) */
> + if (of_machine_is_compatible("ti,da850-evm"))
> + da850_vpif_capture_config.i2c_adapter_id = 1;
> +
> + ret = da850_register_vpif_capture(&da850_vpif_capture_config);
> + if (ret)
> + pr_warn("%s: VPIF capture setup failed: %d\n",
> + __func__, ret);
> +}
> +#endif
> +
> +static void pdata_quirks_check(struct pdata_init *quirks)
This function can be marked __init too.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v2 2/2] mmc: mediatek: correct the implementation of msdc_card_busy
From: Yong Mao @ 2017-01-03 8:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483433397-11756-1-git-send-email-yong.mao@mediatek.com>
From: yong mao <yong.mao@mediatek.com>
msdc_card_busy only need check if the data0 is low.
In sdio data1 irq mode, data1 may be low because of interruption.
Signed-off-by: Yong Mao <yong.mao@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 10ef2ae..80ba034 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1074,11 +1074,8 @@ static int msdc_card_busy(struct mmc_host *mmc)
struct msdc_host *host = mmc_priv(mmc);
u32 status = readl(host->base + MSDC_PS);
- /* check if any pin between dat[0:3] is low */
- if (((status >> 16) & 0xf) != 0xf)
- return 1;
-
- return 0;
+ /* only check if data0 is low */
+ return !(status & BIT(16));
}
static void msdc_request_timeout(struct work_struct *work)
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 1/2] mmc: core: Fix CMD6 timeout issue
From: Yong Mao @ 2017-01-03 8:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483433397-11756-1-git-send-email-yong.mao@mediatek.com>
From: yong mao <yong.mao@mediatek.com>
When initializing EMMC, after switch to HS400,
it will issue CMD6 to change ext_csd,
if first CMD6 got CRC error,
the repeat CMD6 may get timeout,
that's because card is not back to transfer state immediately.
For resolving this issue, it need check if card is busy
before sending repeat CMD6.
Not only CMD6 here has this issue, but also other R1B CMD has
the same issue.
Signed-off-by: Yong Mao <yong.mao@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
---
drivers/mmc/core/core.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 1076b9d..8674dbb 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -566,6 +566,25 @@ void mmc_wait_for_req_done(struct mmc_host *host, struct mmc_request *mrq)
mmc_retune_recheck(host);
+ /*
+ * If a R1B CMD such as CMD6 occur CRC error,
+ * it will retry 3 times here.
+ * But before retrying, it must ensure card is in
+ * transfer state.
+ * Otherwise, the next retried CMD will got TMO error.
+ */
+ if (mmc_resp_type(cmd) == MMC_RSP_R1B && host->ops->card_busy) {
+ int tries = 500; /* Wait aprox 500ms at maximum */
+
+ while (host->ops->card_busy(host) && --tries)
+ mmc_delay(1);
+
+ if (tries == 0) {
+ cmd->error = -EBUSY;
+ break;
+ }
+ }
+
pr_debug("%s: req failed (CMD%u): %d, retrying...\n",
mmc_hostname(host), cmd->opcode, cmd->error);
cmd->retries--;
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2] Fix CMD6 timeout issue
From: Yong Mao @ 2017-01-03 8:49 UTC (permalink / raw)
To: linux-arm-kernel
yong mao (2):
mmc: core: Fix CMD6 timeout issue
mmc: mediatek: correct the implementation of msdc_card_busy
drivers/mmc/core/core.c | 19 +++++++++++++++++++
drivers/mmc/host/mtk-sd.c | 7 ++-----
2 files changed, 21 insertions(+), 5 deletions(-)
--
1.8.1.1.dirty
^ permalink raw reply
* [PATCH v1] mtd: nand: tango: Update DT binding description
From: Boris Brezillon @ 2017-01-03 8:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <24522cc9-9d9a-980d-8cd2-18fb0de19a5f@sigmadesigns.com>
On Tue, 3 Jan 2017 09:34:59 +0100
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> wrote:
> On 29/12/2016 19:23, Boris Brezillon wrote:
> > On Mon, 19 Dec 2016 15:30:12 +0100
> > Marc Gonzalez <marc_gonzalez@sigmadesigns.com> wrote:
> >
> >> Visually separate register ranges (address/size pairs) in reg prop.
> >> Change DMA channel name, for consistency with other drivers.
> >>
> >> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
> >> ---
> >> Documentation/devicetree/bindings/mtd/tango-nand.txt | 6 +++---
> >> drivers/mtd/nand/tango_nand.c | 2 +-
> >> 2 files changed, 4 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mtd/tango-nand.txt b/Documentation/devicetree/bindings/mtd/tango-nand.txt
> >> index ad5a02f2ac8c..cd1bf2ac9055 100644
> >> --- a/Documentation/devicetree/bindings/mtd/tango-nand.txt
> >> +++ b/Documentation/devicetree/bindings/mtd/tango-nand.txt
> >> @@ -5,7 +5,7 @@ Required properties:
> >> - compatible: "sigma,smp8758-nand"
> >> - reg: address/size of nfc_reg, nfc_mem, and pbus_reg
> >> - dmas: reference to the DMA channel used by the controller
> >> -- dma-names: "nfc_sbox"
> >> +- dma-names: "rxtx"
> >
> > You probably want to fix the driver accordingly ;-).
>
> I'm confused...
>
> Did you miss the change (below) to drivers/mtd/nand/tango_nand.c
> fixing the driver as well as the documentation?
Indeed, I missed it. The patch is fine, I'll queue it for 4.10-rcX.
Sorry for the noise.
BTW, I heard you had some fixes for 4.10. Feel free to send them.
Regards,
Boris
^ permalink raw reply
* [PATCH v6 05/14] ACPI: platform-msi: retrieve dev id from IORT
From: Tomasz Nowicki @ 2017-01-03 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483363905-2806-6-git-send-email-hanjun.guo@linaro.org>
On 02.01.2017 14:31, Hanjun Guo wrote:
> For devices connecting to ITS, it needs dev id to identify
> itself, and this dev id is represented in the IORT table in
> named componant node [1] for platform devices, so in this
> patch we will scan the IORT to retrieve device's dev id.
>
> Introduce iort_pmsi_get_dev_id() with pointer dev passed
> in for that purpose.
>
> [1]: https://static.docs.arm.com/den0049/b/DEN0049B_IO_Remapping_Table.pdf
>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> Tested-by: Sinan Kaya <okaya@codeaurora.org>
> Tested-by: Majun <majun258@huawei.com>
> Tested-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Tomasz Nowicki <tn@semihalf.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> ---
> drivers/acpi/arm64/iort.c | 26 ++++++++++++++++++++++++++
> drivers/irqchip/irq-gic-v3-its-platform-msi.c | 4 +++-
> include/linux/acpi_iort.h | 8 ++++++++
> 3 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index 174e983..ab7bae7 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -444,6 +444,32 @@ u32 iort_msi_map_rid(struct device *dev, u32 req_id)
> }
>
> /**
> + * iort_pmsi_get_dev_id() - Get the device id for a device
> + * @dev: The device for which the mapping is to be done.
> + * @dev_id: The device ID found.
> + *
> + * Returns: 0 for successful find a dev id, errors otherwise
> + */
> +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
> +{
> + struct acpi_iort_node *node;
> +
> + if (!iort_table)
> + return -ENODEV;
> +
> + node = iort_find_dev_node(dev);
> + if (!node) {
> + dev_err(dev, "can't find related IORT node\n");
> + return -ENODEV;
> + }
> +
> + if(!iort_node_get_id(node, dev_id, IORT_MSI_TYPE, 0))
> + return -ENODEV;
> +
> + return 0;
> +}
> +
> +/**
Giving that you are extending this to NC->
SMMU->ITS case in later patch, we can use existing helpers from iort.c,
like that:
+/**
+ * iort_pmsi_get_dev_id() - Get the device id for a device
+ * @dev: The device for which the mapping is to be done.
+ * @dev_id: The device ID found.
+ *
+ * Returns: 0 for successful find a dev id, errors otherwise
+ */
+int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
+{
+ struct acpi_iort_node *node;
+
+ node = iort_find_dev_node(dev);
+ if (!node)
+ return -ENODEV;
+
+ if (!iort_node_map_rid(node, 0, dev_id, IORT_MSI_TYPE))
+ return -ENODEV;
+
+ return 0;
+}
Correct me if I am wrong.
Tomasz
^ permalink raw reply
* [PATCHv2 3/8] rtc: add STM32 RTC driver
From: Amelie DELAUNAY @ 2017-01-03 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161216190848.GB8879@linaro.org>
Hi Mathieu,
Thanks for reviewing,
On 12/16/2016 08:08 PM, Mathieu Poirier wrote:
> On Fri, Dec 16, 2016 at 09:50:52AM +0100, Amelie Delaunay wrote:
>> This patch adds support for the STM32 RTC.
>>
>> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
>> ---
>> drivers/rtc/Kconfig | 11 +
>> drivers/rtc/Makefile | 1 +
>> drivers/rtc/rtc-stm32.c | 776 ++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 788 insertions(+)
>> create mode 100644 drivers/rtc/rtc-stm32.c
>>
>> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
>> index e859d14..11eb28a 100644
>> --- a/drivers/rtc/Kconfig
>> +++ b/drivers/rtc/Kconfig
>> @@ -1706,6 +1706,17 @@ config RTC_DRV_PIC32
>> This driver can also be built as a module. If so, the module
>> will be called rtc-pic32
>>
>> +config RTC_DRV_STM32
>> + tristate "STM32 RTC"
>> + select REGMAP_MMIO
>> + depends on ARCH_STM32 || COMPILE_TEST
>> + help
>> + If you say yes here you get support for the STM32 On-Chip
>> + Real Time Clock.
>> +
>> + This driver can also be built as a module, if so, the module
>> + will be called "rtc-stm32".
>> +
>> comment "HID Sensor RTC drivers"
>>
>> config RTC_DRV_HID_SENSOR_TIME
>> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
>> index 1ac694a..87bd9cc 100644
>> --- a/drivers/rtc/Makefile
>> +++ b/drivers/rtc/Makefile
>> @@ -144,6 +144,7 @@ obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o
>> obj-$(CONFIG_RTC_DRV_SPEAR) += rtc-spear.o
>> obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
>> obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
>> +obj-$(CONFIG_RTC_DRV_STM32) += rtc-stm32.o
>> obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o
>> obj-$(CONFIG_RTC_DRV_ST_LPC) += rtc-st-lpc.o
>> obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
>> diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c
>> new file mode 100644
>> index 0000000..6ce0f5a
>> --- /dev/null
>> +++ b/drivers/rtc/rtc-stm32.c
>> @@ -0,0 +1,776 @@
>> +/*
>> + * Copyright (C) Amelie Delaunay 2016
>> + * Author: Amelie Delaunay <amelie.delaunay@st.com>
>> + * License terms: GNU General Public License (GPL), version 2
>> + */
>> +
>> +#include <linux/bcd.h>
>> +#include <linux/clk.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/ioport.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/rtc.h>
>> +#include <linux/spinlock.h>
>> +
>> +#define DRIVER_NAME "stm32_rtc"
>> +
>> +/* STM32 RTC registers */
>> +#define STM32_RTC_TR 0x00
>> +#define STM32_RTC_DR 0x04
>> +#define STM32_RTC_CR 0x08
>> +#define STM32_RTC_ISR 0x0C
>> +#define STM32_RTC_PRER 0x10
>> +#define STM32_RTC_ALRMAR 0x1C
>> +#define STM32_RTC_WPR 0x24
>> +
>> +/* STM32_RTC_TR bit fields */
>> +#define STM32_RTC_TR_SEC_SHIFT 0
>> +#define STM32_RTC_TR_SEC GENMASK(6, 0)
>> +#define STM32_RTC_TR_MIN_SHIFT 8
>> +#define STM32_RTC_TR_MIN GENMASK(14, 8)
>> +#define STM32_RTC_TR_HOUR_SHIFT 16
>> +#define STM32_RTC_TR_HOUR GENMASK(21, 16)
>> +
>> +/* STM32_RTC_DR bit fields */
>> +#define STM32_RTC_DR_DATE_SHIFT 0
>> +#define STM32_RTC_DR_DATE GENMASK(5, 0)
>> +#define STM32_RTC_DR_MONTH_SHIFT 8
>> +#define STM32_RTC_DR_MONTH GENMASK(12, 8)
>> +#define STM32_RTC_DR_WDAY_SHIFT 13
>> +#define STM32_RTC_DR_WDAY GENMASK(15, 13)
>> +#define STM32_RTC_DR_YEAR_SHIFT 16
>> +#define STM32_RTC_DR_YEAR GENMASK(23, 16)
>> +
>> +/* STM32_RTC_CR bit fields */
>> +#define STM32_RTC_CR_FMT BIT(6)
>> +#define STM32_RTC_CR_ALRAE BIT(8)
>> +#define STM32_RTC_CR_ALRAIE BIT(12)
>> +
>> +/* STM32_RTC_ISR bit fields */
>> +#define STM32_RTC_ISR_ALRAWF BIT(0)
>> +#define STM32_RTC_ISR_INITS BIT(4)
>> +#define STM32_RTC_ISR_RSF BIT(5)
>> +#define STM32_RTC_ISR_INITF BIT(6)
>> +#define STM32_RTC_ISR_INIT BIT(7)
>> +#define STM32_RTC_ISR_ALRAF BIT(8)
>> +
>> +/* STM32_RTC_PRER bit fields */
>> +#define STM32_RTC_PRER_PRED_S_SHIFT 0
>> +#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
>> +#define STM32_RTC_PRER_PRED_A_SHIFT 16
>> +#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
>> +
>> +/* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
>> +#define STM32_RTC_ALRMXR_SEC_SHIFT 0
>> +#define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)
>> +#define STM32_RTC_ALRMXR_SEC_MASK BIT(7)
>> +#define STM32_RTC_ALRMXR_MIN_SHIFT 8
>> +#define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)
>> +#define STM32_RTC_ALRMXR_MIN_MASK BIT(15)
>> +#define STM32_RTC_ALRMXR_HOUR_SHIFT 16
>> +#define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)
>> +#define STM32_RTC_ALRMXR_PM BIT(22)
>> +#define STM32_RTC_ALRMXR_HOUR_MASK BIT(23)
>> +#define STM32_RTC_ALRMXR_DATE_SHIFT 24
>> +#define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)
>> +#define STM32_RTC_ALRMXR_WDSEL BIT(30)
>> +#define STM32_RTC_ALRMXR_WDAY_SHIFT 24
>> +#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
>> +#define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
>> +
>> +/* STM32_RTC_WPR key constants */
>> +#define RTC_WPR_1ST_KEY 0xCA
>> +#define RTC_WPR_2ND_KEY 0x53
>> +#define RTC_WPR_WRONG_KEY 0xFF
>> +
>> +/*
>> + * RTC registers are protected agains parasitic write access.
>> + * PWR_CR_DBP bit must be set to enable write access to RTC registers.
>> + */
>> +/* STM32_PWR_CR */
>> +#define PWR_CR 0x00
>> +/* STM32_PWR_CR bit field */
>> +#define PWR_CR_DBP BIT(8)
>> +
>> +static struct regmap *dbp;
>> +
>> +struct stm32_rtc {
>> + struct rtc_device *rtc_dev;
>> + void __iomem *base;
>> + struct clk *ck_rtc;
>> + spinlock_t lock; /* Protects registers accesses */
>> + int irq_alarm;
>> +};
>> +
>> +static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
>> +{
>> + writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + STM32_RTC_WPR);
>> + writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + STM32_RTC_WPR);
>> +}
>> +
>> +static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
>> +{
>> + writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + STM32_RTC_WPR);
>> +}
>> +
>> +static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
>> +{
>> + unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
>> +
>> + if (!(isr & STM32_RTC_ISR_INITF)) {
>> + isr |= STM32_RTC_ISR_INIT;
>> + writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
>> +
>> + /*
>> + * It takes around 2 ck_rtc clock cycles to enter in
>> + * initialization phase mode (and have INITF flag set). As
>> + * slowest ck_rtc frequency may be 32kHz and highest should be
>> + * 1MHz, we poll every 10 us with a timeout of 100ms.
>> + */
>> + return readl_relaxed_poll_timeout_atomic(
>> + rtc->base + STM32_RTC_ISR,
>> + isr, (isr & STM32_RTC_ISR_INITF),
>> + 10, 100000);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
>> +{
>> + unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
>> +
>> + isr &= ~STM32_RTC_ISR_INIT;
>> + writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
>> +}
>> +
>> +static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
>> +{
>> + unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
>> +
>> + isr &= ~STM32_RTC_ISR_RSF;
>> + writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
>> +
>> + /*
>> + * Wait for RSF to be set to ensure the calendar registers are
>> + * synchronised, it takes around 2 ck_rtc clock cycles
>> + */
>> + return readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
>> + isr,
>> + (isr & STM32_RTC_ISR_RSF),
>> + 10, 100000);
>> +}
>> +
>> +static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
>> +{
>> + struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
>> + unsigned int isr, cr;
>> +
>> + mutex_lock(&rtc->rtc_dev->ops_lock);
>> +
>> + isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
>> + cr = readl_relaxed(rtc->base + STM32_RTC_CR);
>> +
>> + if ((isr & STM32_RTC_ISR_ALRAF) &&
>> + (cr & STM32_RTC_CR_ALRAIE)) {
>> + /* Alarm A flag - Alarm interrupt */
>> + dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
>> +
>> + /* Pass event to the kernel */
>> + rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
>> +
>> + /* Clear event flag, otherwise new events won't be received */
>> + writel_relaxed(isr & ~STM32_RTC_ISR_ALRAF,
>> + rtc->base + STM32_RTC_ISR);
>> + }
>> +
>> + mutex_unlock(&rtc->rtc_dev->ops_lock);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +/* Convert rtc_time structure from bin to bcd format */
>> +static void tm2bcd(struct rtc_time *tm)
>> +{
>> + tm->tm_sec = bin2bcd(tm->tm_sec);
>> + tm->tm_min = bin2bcd(tm->tm_min);
>> + tm->tm_hour = bin2bcd(tm->tm_hour);
>> +
>> + tm->tm_mday = bin2bcd(tm->tm_mday);
>> + tm->tm_mon = bin2bcd(tm->tm_mon + 1);
>> + tm->tm_year = bin2bcd(tm->tm_year - 100);
>> + /*
>> + * Number of days since Sunday
>> + * - on kernel side, 0=Sunday...6=Saturday
>> + * - on rtc side, 0=invalid,1=Monday...7=Sunday
>> + */
>> + tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
>> +}
>> +
>> +/* Convert rtc_time structure from bcd to bin format */
>> +static void bcd2tm(struct rtc_time *tm)
>> +{
>> + tm->tm_sec = bcd2bin(tm->tm_sec);
>> + tm->tm_min = bcd2bin(tm->tm_min);
>> + tm->tm_hour = bcd2bin(tm->tm_hour);
>> +
>> + tm->tm_mday = bcd2bin(tm->tm_mday);
>> + tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
>> + tm->tm_year = bcd2bin(tm->tm_year) + 100;
>> + /*
>> + * Number of days since Sunday
>> + * - on kernel side, 0=Sunday...6=Saturday
>> + * - on rtc side, 0=invalid,1=Monday...7=Sunday
>> + */
>> + tm->tm_wday %= 7;
>> +}
>> +
>> +static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
>> +{
>> + struct stm32_rtc *rtc = dev_get_drvdata(dev);
>> + unsigned int tr, dr;
>> + unsigned long irqflags;
>> +
>> + spin_lock_irqsave(&rtc->lock, irqflags);
>> +
>> + /* Time and Date in BCD format */
>> + tr = readl_relaxed(rtc->base + STM32_RTC_TR);
>> + dr = readl_relaxed(rtc->base + STM32_RTC_DR);
>> +
>> + spin_unlock_irqrestore(&rtc->lock, irqflags);
>> +
>> + tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
>> + tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
>> + tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
>> +
>> + tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
>> + tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
>> + tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
>> + tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
>> +
>> + /* We don't report tm_yday and tm_isdst */
>> +
>> + bcd2tm(tm);
>> +
>> + if (rtc_valid_tm(tm) < 0) {
>> + dev_err(dev, "%s: rtc_time is not valid.\n", __func__);
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
>> +{
>> + struct stm32_rtc *rtc = dev_get_drvdata(dev);
>> + unsigned int tr, dr;
>> + unsigned long irqflags;
>> + int ret = 0;
>> +
>> + if (rtc_valid_tm(tm) < 0) {
>> + dev_err(dev, "%s: rtc_time is not valid.\n", __func__);
>> + return -EINVAL;
>> + }
>> +
>> + tm2bcd(tm);
>> +
>> + /* Time in BCD format */
>> + tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
>> + ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
>> + ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
>> +
>> + /* Date in BCD format */
>> + dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
>> + ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
>> + ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
>> + ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
>> +
>> + spin_lock_irqsave(&rtc->lock, irqflags);
>> +
>> + stm32_rtc_wpr_unlock(rtc);
>> +
>> + ret = stm32_rtc_enter_init_mode(rtc);
>> + if (ret) {
>> + dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
>> + goto end;
>> + }
>> +
>> + writel_relaxed(tr, rtc->base + STM32_RTC_TR);
>> + writel_relaxed(dr, rtc->base + STM32_RTC_DR);
>> +
>> + stm32_rtc_exit_init_mode(rtc);
>> +
>> + ret = stm32_rtc_wait_sync(rtc);
>> +end:
>> + stm32_rtc_wpr_lock(rtc);
>> +
>> + spin_unlock_irqrestore(&rtc->lock, irqflags);
>> +
>> + return ret;
>> +}
>> +
>> +static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
>> +{
>> + struct stm32_rtc *rtc = dev_get_drvdata(dev);
>> + struct rtc_time *tm = &alrm->time;
>> + unsigned int alrmar, cr, isr;
>> + unsigned long irqflags;
>> +
>> + spin_lock_irqsave(&rtc->lock, irqflags);
>> +
>> + alrmar = readl_relaxed(rtc->base + STM32_RTC_ALRMAR);
>> + cr = readl_relaxed(rtc->base + STM32_RTC_CR);
>> + isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
>> +
>> + spin_unlock_irqrestore(&rtc->lock, irqflags);
>> +
>> + if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
>> + /*
>> + * Date/day doesn't matter in Alarm comparison so alarm
>> + * triggers every day
>> + */
>> + tm->tm_mday = -1;
>> + tm->tm_wday = -1;
>> + } else {
>> + if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
>> + /* Alarm is set to a day of week */
>> + tm->tm_mday = -1;
>> + tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
>> + STM32_RTC_ALRMXR_WDAY_SHIFT;
>> + tm->tm_wday %= 7;
>> + } else {
>> + /* Alarm is set to a day of month */
>> + tm->tm_wday = -1;
>> + tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
>> + STM32_RTC_ALRMXR_DATE_SHIFT;
>> + }
>> + }
>> +
>> + if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
>> + /* Hours don't matter in Alarm comparison */
>> + tm->tm_hour = -1;
>> + } else {
>> + tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
>> + STM32_RTC_ALRMXR_HOUR_SHIFT;
>> + if (alrmar & STM32_RTC_ALRMXR_PM)
>> + tm->tm_hour += 12;
>> + }
>> +
>> + if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
>> + /* Minutes don't matter in Alarm comparison */
>> + tm->tm_min = -1;
>> + } else {
>> + tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
>> + STM32_RTC_ALRMXR_MIN_SHIFT;
>> + }
>> +
>> + if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
>> + /* Seconds don't matter in Alarm comparison */
>> + tm->tm_sec = -1;
>> + } else {
>> + tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
>> + STM32_RTC_ALRMXR_SEC_SHIFT;
>> + }
>> +
>> + bcd2tm(tm);
>> +
>> + alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
>> + alrm->pending = (isr & STM32_RTC_ISR_ALRAF) ? 1 : 0;
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
>> +{
>> + struct stm32_rtc *rtc = dev_get_drvdata(dev);
>> + unsigned long irqflags;
>> + unsigned int isr, cr;
>> +
>> + spin_lock_irqsave(&rtc->lock, irqflags);
>> +
>> + cr = readl_relaxed(rtc->base + STM32_RTC_CR);
>> +
>> + stm32_rtc_wpr_unlock(rtc);
>> +
>> + /* We expose Alarm A to the kernel */
>> + if (enabled)
>> + cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
>> + else
>> + cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
>> + writel_relaxed(cr, rtc->base + STM32_RTC_CR);
>> +
>> + /* Clear event irqflags, otherwise new events won't be received */
>> + isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
>> + isr &= ~STM32_RTC_ISR_ALRAF;
>> + writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
>> +
>> + stm32_rtc_wpr_lock(rtc);
>> +
>> + spin_unlock_irqrestore(&rtc->lock, irqflags);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
>> +{
>> + unsigned int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
>> + unsigned int dr = readl_relaxed(rtc->base + STM32_RTC_DR);
>> + unsigned int tr = readl_relaxed(rtc->base + STM32_RTC_TR);
>> +
>> + cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
>> + cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
>> + cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
>> + cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
>> + cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
>> + cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
>> +
>> + /*
>> + * Assuming current date is M-D-Y H:M:S.
>> + * RTC alarm can't be set on a specific month and year.
>> + * So the valid alarm range is:
>> + * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
>> + * with a specific case for December...
>> + */
>> + if ((((tm->tm_year > cur_year) &&
>> + (tm->tm_mon == 0x1) && (cur_mon == 0x12)) ||
>> + ((tm->tm_year == cur_year) &&
>> + (tm->tm_mon <= cur_mon + 1))) &&
>> + ((tm->tm_mday < cur_day) ||
>> + ((tm->tm_mday == cur_day) &&
>> + ((tm->tm_hour < cur_hour) ||
>> + ((tm->tm_hour == cur_hour) && (tm->tm_min < cur_min)) ||
>> + ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) &&
>> + (tm->tm_sec <= cur_sec))))))
>> + return 0;
>> +
>> + return -EINVAL;
>> +}
>> +
>> +static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
>> +{
>> + struct stm32_rtc *rtc = dev_get_drvdata(dev);
>> + struct rtc_time *tm = &alrm->time;
>> + unsigned long irqflags;
>> + unsigned int cr, isr, alrmar;
>> + int ret = 0;
>> +
>> + if (rtc_valid_tm(tm)) {
>> + dev_err(dev, "Alarm time not valid.\n");
>> + return -EINVAL;
>> + }
>> +
>> + tm2bcd(tm);
>> +
>> + /*
>> + * RTC alarm can't be set on a specific date, unless this date is
>> + * up to the same day of month next month.
>> + */
>> + if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
>> + dev_err(dev, "Alarm can be set only on upcoming month.\n");
>> + return -EINVAL;
>> + }
>> +
>> + spin_lock_irqsave(&rtc->lock, irqflags);
>> +
>> + stm32_rtc_wpr_unlock(rtc);
>> +
>> + /* Disable Alarm */
>> + cr = readl_relaxed(rtc->base + STM32_RTC_CR);
>> + cr &= ~STM32_RTC_CR_ALRAE;
>> + writel_relaxed(cr, rtc->base + STM32_RTC_CR);
>> +
>> + /*
>> + * Poll Alarm write flag to be sure that Alarm update is allowed: it
>> + * takes around 2 ck_rtc clock cycles
>> + */
>> + ret = readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
>> + isr,
>> + (isr & STM32_RTC_ISR_ALRAWF),
>> + 10, 100000);
>> +
>> + if (ret) {
>> + dev_err(dev, "Alarm update not allowed\n");
>> + goto end;
>> + }
>> +
>> + alrmar = 0;
>> + /* tm_year and tm_mon are not used because not supported by RTC */
>> + alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
>> + STM32_RTC_ALRMXR_DATE;
>> + /* 24-hour format */
>> + alrmar &= ~STM32_RTC_ALRMXR_PM;
>> + alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
>> + STM32_RTC_ALRMXR_HOUR;
>> + alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
>> + STM32_RTC_ALRMXR_MIN;
>> + alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
>> + STM32_RTC_ALRMXR_SEC;
>
> All this work on alrmar is done while the spinlock is held. If I'm not
> mistaking nothing prevents you from doing that processing before taking the
> spinlock.
>
Yes, I'll move alrmar processing above, just before taking the spinlock.
>> +
>> + /* Write to Alarm register */
>> + writel_relaxed(alrmar, rtc->base + STM32_RTC_ALRMAR);
>> +
>> + if (alrm->enabled)
>> + stm32_rtc_alarm_irq_enable(dev, 1);
>> + else
>> + stm32_rtc_alarm_irq_enable(dev, 0);
>> +
>> +end:
>> + stm32_rtc_wpr_lock(rtc);
>> +
>> + spin_unlock_irqrestore(&rtc->lock, irqflags);
>> +
>> + return ret;
>> +}
>> +
>> +static const struct rtc_class_ops stm32_rtc_ops = {
>> + .read_time = stm32_rtc_read_time,
>> + .set_time = stm32_rtc_set_time,
>> + .read_alarm = stm32_rtc_read_alarm,
>> + .set_alarm = stm32_rtc_set_alarm,
>> + .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
>> +};
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id stm32_rtc_of_match[] = {
>> + { .compatible = "st,stm32-rtc" },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
>> +#endif
>> +
>> +static int stm32_rtc_init(struct platform_device *pdev,
>> + struct stm32_rtc *rtc)
>> +{
>> + unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
>> + unsigned int rate;
>> + unsigned long irqflags;
>> + int ret = 0;
>> +
>> + rate = clk_get_rate(rtc->ck_rtc);
>> +
>> + /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
>> + pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
>> + pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
>> +
>> + for (pred_a = pred_a_max; pred_a >= 0; pred_a--) {
>> + pred_s = (rate / (pred_a + 1)) - 1;
>> +
>> + if (((pred_s + 1) * (pred_a + 1)) == rate)
>> + break;
>> + }
>> +
>> + /*
>> + * Can't find a 1Hz, so give priority to RTC power consumption
>> + * by choosing the higher possible value for prediv_a
>> + */
>> + if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) {
>> + pred_a = pred_a_max;
>> + pred_s = (rate / (pred_a + 1)) - 1;
>> +
>> + dev_warn(&pdev->dev, "ck_rtc is %s\n",
>> + (rate - ((pred_a + 1) * (pred_s + 1)) < 0) ?
>> + "fast" : "slow");
>> + }
>> +
>> + spin_lock_irqsave(&rtc->lock, irqflags);
>> +
>> + stm32_rtc_wpr_unlock(rtc);
>> +
>> + ret = stm32_rtc_enter_init_mode(rtc);
>> + if (ret) {
>> + dev_err(&pdev->dev,
>> + "Can't enter in init mode. Prescaler config failed.\n");
>> + goto end;
>> + }
>> +
>> + prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
>> + writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
>> + prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
>> + writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
>> +
>> + /* Force 24h time format */
>> + cr = readl_relaxed(rtc->base + STM32_RTC_CR);
>> + cr &= ~STM32_RTC_CR_FMT;
>> + writel_relaxed(cr, rtc->base + STM32_RTC_CR);
>> +
>> + stm32_rtc_exit_init_mode(rtc);
>> +
>> + ret = stm32_rtc_wait_sync(rtc);
>> +end:
>> + stm32_rtc_wpr_lock(rtc);
>> +
>> + spin_unlock_irqrestore(&rtc->lock, irqflags);
>> +
>> + return ret;
>> +}
>> +
>> +static int stm32_rtc_probe(struct platform_device *pdev)
>> +{
>> + struct stm32_rtc *rtc;
>> + struct resource *res;
>> + int ret;
>> +
>> + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
>> + if (!rtc)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + rtc->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(rtc->base))
>> + return PTR_ERR(rtc->base);
>> +
>> + dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "st,syscfg");
>> + if (IS_ERR(dbp)) {
>> + dev_err(&pdev->dev, "no st,syscfg\n");
>> + return PTR_ERR(dbp);
>> + }
>> +
>> + spin_lock_init(&rtc->lock);
>> +
>> + rtc->ck_rtc = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(rtc->ck_rtc)) {
>> + dev_err(&pdev->dev, "no ck_rtc clock");
>> + return PTR_ERR(rtc->ck_rtc);
>> + }
>> +
>> + ret = clk_prepare_enable(rtc->ck_rtc);
>> + if (ret)
>> + return ret;
>> +
>> + regmap_update_bits(dbp, PWR_CR, PWR_CR_DBP, PWR_CR_DBP);
>> +
>> + /*
>> + * After a system reset, RTC_ISR.INITS flag can be read to check if
>> + * the calendar has been initalized or not. INITS flag is reset by a
>> + * power-on reset (no vbat, no power-supply). It is not reset if
>> + * ck_rtc parent clock has changed (so RTC prescalers need to be
>> + * changed). That's why we cannot rely on this flag to know if RTC
>> + * init has to be done.
>> + */
>> + ret = stm32_rtc_init(pdev, rtc);
>> + if (ret)
>> + goto err;
>> +
>> + rtc->irq_alarm = platform_get_irq(pdev, 0);
>> + if (rtc->irq_alarm <= 0) {
>> + dev_err(&pdev->dev, "no alarm irq\n");
>> + ret = -ENOENT;
>
> Function platform_get_irq() returns a wealth of error codes that are lost here.
> Doing 'ret = rtc->irq_alarm;' would prevent that from happening.
>
OK
>> + goto err;
>> + }
>> +
>> + platform_set_drvdata(pdev, rtc);
>> +
>> + ret = device_init_wakeup(&pdev->dev, true);
>> + if (ret)
>> + dev_warn(&pdev->dev,
>> + "alarm won't be able to wake up the system");
>> +
>> + rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
>> + &stm32_rtc_ops, THIS_MODULE);
>> + if (IS_ERR(rtc->rtc_dev)) {
>> + ret = PTR_ERR(rtc->rtc_dev);
>> + dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
>> + ret);
>> + goto err;
>> + }
>> +
>> + /* Handle RTC alarm interrupts */
>> + ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
>> + stm32_rtc_alarm_irq,
>> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>> + pdev->name, rtc);
>> + if (ret) {
>> + dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
>> + rtc->irq_alarm);
>> + goto err;
>> + }
>> +
>> + /*
>> + * If INITS flag is reset (calendar year field set to 0x00), calendar
>> + * must be initialized
>> + */
>> + if (!(readl_relaxed(rtc->base + STM32_RTC_ISR) & STM32_RTC_ISR_INITS))
>> + dev_warn(&pdev->dev, "Date/Time must be initialized\n");
>> +
>> + return 0;
>> +err:
>> + clk_disable_unprepare(rtc->ck_rtc);
>> +
>> + regmap_update_bits(dbp, PWR_CR, PWR_CR_DBP, ~PWR_CR_DBP);
>> +
>> + device_init_wakeup(&pdev->dev, false);
>> +
>> + return ret;
>> +}
>> +
>> +static int __exit stm32_rtc_remove(struct platform_device *pdev)
>> +{
>> + struct stm32_rtc *rtc = platform_get_drvdata(pdev);
>> + unsigned int cr;
>> +
>> + /* Disable interrupts */
>> + stm32_rtc_wpr_unlock(rtc);
>> + cr = readl_relaxed(rtc->base + STM32_RTC_CR);
>> + cr &= ~STM32_RTC_CR_ALRAIE;
>> + writel_relaxed(cr, rtc->base + STM32_RTC_CR);
>> + stm32_rtc_wpr_lock(rtc);
>> +
>> + clk_disable_unprepare(rtc->ck_rtc);
>> +
>> + /* Enable backup domain write protection */
>> + regmap_update_bits(dbp, PWR_CR, PWR_CR_DBP, ~PWR_CR_DBP);
>> +
>> + device_init_wakeup(&pdev->dev, false);
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int stm32_rtc_suspend(struct device *dev)
>> +{
>> + struct stm32_rtc *rtc = dev_get_drvdata(dev);
>> +
>> + if (device_may_wakeup(dev))
>> + return enable_irq_wake(rtc->irq_alarm);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_rtc_resume(struct device *dev)
>> +{
>> + struct stm32_rtc *rtc = dev_get_drvdata(dev);
>> + int ret = 0;
>> +
>> + ret = stm32_rtc_wait_sync(rtc);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (device_may_wakeup(dev))
>> + return disable_irq_wake(rtc->irq_alarm);
>> +
>> + return ret;
>> +}
>> +#endif
>> +
>> +static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops,
>> + stm32_rtc_suspend, stm32_rtc_resume);
>> +
>> +static struct platform_driver stm32_rtc_driver = {
>> + .probe = stm32_rtc_probe,
>> + .remove = stm32_rtc_remove,
>> + .driver = {
>> + .name = DRIVER_NAME,
>> + .pm = &stm32_rtc_pm_ops,
>> + .of_match_table = stm32_rtc_of_match,
>> + },
>> +};
>> +
>> +module_platform_driver(stm32_rtc_driver);
>> +
>> +MODULE_ALIAS("platform:" DRIVER_NAME);
>> +MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
>> +MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 1.9.1
>>
Happy New Year!
Amelie
^ permalink raw reply
* [PATCH] pinctrl: amd: fix compilation warning
From: Shah, Nehal-bakulchandra @ 2017-01-03 8:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103082119.11958-1-linus.walleij@linaro.org>
Thanks Linus for fixing this.
Nehal
-----Original Message-----
From: Linus Walleij [mailto:linus.walleij at linaro.org]
Sent: Tuesday, January 3, 2017 1:51 PM
To: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Cc: linux-gpio at vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>; S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com>; Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com>
Subject: [PATCH] pinctrl: amd: fix compilation warning
3bfd44306c65 ("pinctrl: amd: Add support for additional GPIO") created the following warning:
drivers/pinctrl/pinctrl-amd.c: In function 'amd_gpio_dbg_show':
drivers/pinctrl/pinctrl-amd.c:210:3: warning: 'pin_num' may be used uninitialized in this function [-Wmaybe-uninitialized]
for (; i < pin_num; i++) {
^
drivers/pinctrl/pinctrl-amd.c:172:21: warning: 'i' may be used uninitialized in this function [-Wmaybe-uninitialized]
unsigned int bank, i, pin_num;
^
Fix this by adding a guarding default case for illegal bank numbers.
Cc: S-k Shyam-sundar <Shyam-sundar.S-k@amd.com>
Cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-amd.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 47b17100410e..c2203699f1ab 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -206,6 +206,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
i = 192;
pin_num = AMD_GPIO_PINS_BANK3 + i;
break;
+ default:
+ /* Illegal bank number, ignore */
+ continue;
}
for (; i < pin_num; i++) {
seq_printf(s, "pin%d\t", i);
--
2.9.3
^ permalink raw reply
* [PATCH v1] mtd: nand: tango: Update DT binding description
From: Marc Gonzalez @ 2017-01-03 8:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161229192302.5c94ecdb@bbrezillon>
On 29/12/2016 19:23, Boris Brezillon wrote:
> On Mon, 19 Dec 2016 15:30:12 +0100
> Marc Gonzalez <marc_gonzalez@sigmadesigns.com> wrote:
>
>> Visually separate register ranges (address/size pairs) in reg prop.
>> Change DMA channel name, for consistency with other drivers.
>>
>> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
>> ---
>> Documentation/devicetree/bindings/mtd/tango-nand.txt | 6 +++---
>> drivers/mtd/nand/tango_nand.c | 2 +-
>> 2 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/tango-nand.txt b/Documentation/devicetree/bindings/mtd/tango-nand.txt
>> index ad5a02f2ac8c..cd1bf2ac9055 100644
>> --- a/Documentation/devicetree/bindings/mtd/tango-nand.txt
>> +++ b/Documentation/devicetree/bindings/mtd/tango-nand.txt
>> @@ -5,7 +5,7 @@ Required properties:
>> - compatible: "sigma,smp8758-nand"
>> - reg: address/size of nfc_reg, nfc_mem, and pbus_reg
>> - dmas: reference to the DMA channel used by the controller
>> -- dma-names: "nfc_sbox"
>> +- dma-names: "rxtx"
>
> You probably want to fix the driver accordingly ;-).
I'm confused...
Did you miss the change (below) to drivers/mtd/nand/tango_nand.c
fixing the driver as well as the documentation?
>> - clocks: reference to the system clock
>> - #address-cells: <1>
>> - #size-cells: <0>
>> @@ -17,9 +17,9 @@ Example:
>>
>> nandc: nand-controller at 2c000 {
>> compatible = "sigma,smp8758-nand";
>> - reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;
>> + reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
>> dmas = <&dma0 3>;
>> - dma-names = "nfc_sbox";
>> + dma-names = "rxtx";
>> clocks = <&clkgen SYS_CLK>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> diff --git a/drivers/mtd/nand/tango_nand.c b/drivers/mtd/nand/tango_nand.c
>> index cc23db64f0ca..51dc88d6b8da 100644
>> --- a/drivers/mtd/nand/tango_nand.c
>> +++ b/drivers/mtd/nand/tango_nand.c
>> @@ -629,7 +629,7 @@ static int tango_nand_probe(struct platform_device *pdev)
>> if (IS_ERR(clk))
>> return PTR_ERR(clk);
>>
>> - nfc->chan = dma_request_chan(&pdev->dev, "nfc_sbox");
>> + nfc->chan = dma_request_chan(&pdev->dev, "rxtx");
>> if (IS_ERR(nfc->chan))
>> return PTR_ERR(nfc->chan);
>>
^ permalink raw reply
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-03 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483430237-26823-4-git-send-email-jcsing.lee@samsung.com>
On Tue, Jan 3, 2017 at 9:57 AM, Jaechul Lee <jcsing.lee@samsung.com> wrote:
> From: Andi Shyti <andi.shyti@samsung.com>
>
> Currently tm2e dts includes tm2 but there are some differences
> between the two boards and tm2 has some properties that tm2e
> doesn't have.
>
> That's why it's important to keep the two dts files independent
> and put all the commonalities in a tm2-common.dtsi file.
>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
> 3 files changed, 1049 insertions(+), 1032 deletions(-)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
I would like to see here the rename and diff from it. Not entire delta
(deletions and addons). It is not possible to compare it... I think
git supports it by default with similarity of 50%.
Best regards,
Krzysztof
^ permalink raw reply
* [GIT PULL] i.MX fixes for 4.10
From: Shawn Guo @ 2017-01-03 8:26 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88:
Linux 4.10-rc2 (2017-01-01 14:31:53 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-fixes-4.10
for you to fetch changes up to 116dad7d4339d0965169df8a864fc829f684794d:
ARM: dts: imx6: Disable "weim" node in the dtsi files (2017-01-03 10:59:07 +0800)
----------------------------------------------------------------
i.MX fixes for 4.10:
- A format fix for vf610-zii-dev-rev-b.dts, which has a very odd line
due to misses a newline.
- A fix to imx-weim bus error seen on board which doesn't actually use
the bus.
- A fix for imx6qdl-nitrogen6x board which has conflicting usage of
pad NANDF_CS2.
- A cleanup on i.MX1 machine to remove .map_io callback, which also
fixes a compiling error for NOMMU build.
- Fix AVIC base address in i.MX31 device tree source. The problem was
shadowed by the AVIC driver, which takes the correct base address
from a SoC specific header file.
----------------------------------------------------------------
Andreas F?rber (1):
ARM: dts: vf610-zii-dev-rev-b: Add missing newline
Fabio Estevam (1):
ARM: dts: imx6: Disable "weim" node in the dtsi files
Gary Bisson (1):
ARM: dts: imx6qdl-nitrogen6x: remove duplicate iomux entry
Vladimir Murzin (1):
ARM: i.MX: remove map_io callback
Vladimir Zapolskiy (1):
ARM: dts: imx31: fix AVIC base address
arch/arm/boot/dts/imx31.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 1 -
arch/arm/boot/dts/imx6qdl.dtsi | 1 +
arch/arm/boot/dts/imx6sl.dtsi | 1 +
arch/arm/boot/dts/imx6sx.dtsi | 1 +
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 3 ++-
arch/arm/mach-imx/mach-imx1.c | 1 -
7 files changed, 7 insertions(+), 5 deletions(-)
^ permalink raw reply
* [PATCH v2 3/4] ARM64: dts: exynos5433: use macros for pinctrl configuration on Exynos5433
From: Linus Walleij @ 2017-01-03 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230151724.5wlp4hbphasmw3rg@kozik-lap>
On Fri, Dec 30, 2016 at 4:17 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Fri, Dec 30, 2016 at 02:32:39PM +0100, Linus Walleij wrote:
>> On Fri, Dec 30, 2016 at 5:14 AM, Andi Shyti <andi.shyti@samsung.com> wrote:
>>
>> > Use the macros defined in include/dt-bindings/pinctrl/samsung.h
>> > instead of hardcoded values.
>> >
>> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>>
>> These look fine, but that this and the other DTS patch through ARM SoC.
>>
>> If you also need the headerfile patch (patch 2) to go through ARM SoC
>> that is fine,
>> I can take it out of pinctrl if you want.
>
> Yes, I need the header. It would be much appreciated if you could
> provide a tag or stable branch with it.
Nah better just merge that patch into the ARM SoC tree only.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I'll remove it from the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] pinctrl: amd: fix compilation warning
From: Linus Walleij @ 2017-01-03 8:21 UTC (permalink / raw)
To: linux-arm-kernel
3bfd44306c65 ("pinctrl: amd: Add support for additional GPIO")
created the following warning:
drivers/pinctrl/pinctrl-amd.c: In function 'amd_gpio_dbg_show':
drivers/pinctrl/pinctrl-amd.c:210:3: warning: 'pin_num' may be used uninitialized in this function [-Wmaybe-uninitialized]
for (; i < pin_num; i++) {
^
drivers/pinctrl/pinctrl-amd.c:172:21: warning: 'i' may be used uninitialized in this function [-Wmaybe-uninitialized]
unsigned int bank, i, pin_num;
^
Fix this by adding a guarding default case for illegal
bank numbers.
Cc: S-k Shyam-sundar <Shyam-sundar.S-k@amd.com>
Cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-amd.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 47b17100410e..c2203699f1ab 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -206,6 +206,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
i = 192;
pin_num = AMD_GPIO_PINS_BANK3 + i;
break;
+ default:
+ /* Illegal bank number, ignore */
+ continue;
}
for (; i < pin_num; i++) {
seq_printf(s, "pin%d\t", i);
--
2.9.3
^ permalink raw reply related
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