* [PATCH v3 1/2] Doc: devicetree: bindings: Add vendor prefix entry - lwn
From: Lukasz Majewski @ 2017-01-03 10:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds entry for LWN - the Liebherr-Werk Nenzing GmbH company to
vendor-prefixes.txt file.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes for v3:
- Update to v4.10-rc2
Changes for v2:
- New patch
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 16d3b5e..8e2abcb 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -164,6 +164,7 @@ lg LG Corporation
linux Linux-specific binding
lltc Linear Technology Corporation
lsi LSI Corp. (LSI Logic)
+lwn Liebherr-Werk Nenzing GmbH
macnica Macnica Americas
marvell Marvell Technology Group Ltd.
maxim Maxim Integrated Products
--
2.1.4
^ permalink raw reply related
* [GIT PULL] arm64: dts: vexpress: fixes for v4.10
From: Sudeep Holla @ 2017-01-03 10:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC Team,
Please pull !
Regards,
Sudeep
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git
tags/juno-fixes-4.10
for you to fetch changes up to 1dff32d7df7ff5d80194ebce7ab5755b32564e13:
arm64: dts: vexpress: Support GICC_DIR operations (2016-12-30 15:31:24
+0000)
----------------------------------------------------------------
ARMv8 Juno/VExpress fixes for v4.10
A simple fix to extend GICv2 CPU interface registers from 4K to 8K
on AEMv8 FVP/RTSM models in order to support split priority drop and
interrupt deactivation.
----------------------------------------------------------------
Sudeep Holla (1):
arm64: dts: vexpress: Support GICC_DIR operations
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply
* [GIT PULL] ARM: dts: vexpress: fixes for v4.10
From: Sudeep Holla @ 2017-01-03 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC Team,
Please pull !
Regards,
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git
tags/vexpress-fixes-4.10
for you to fetch changes up to 368400e242dc04963ca5ff0b70654f1470344a0a:
ARM: dts: vexpress: Support GICC_DIR operations (2016-12-30 14:54:30
+0000)
----------------------------------------------------------------
ARMv7 VExpress fixes for v4.10
A simple fix to extend GICv2 CPU interface registers from 4K to 8K
on VExpress TC1 and TC2 platforms in order to support split priority
drop and interrupt deactivation.
----------------------------------------------------------------
Christoffer Dall (1):
ARM: dts: vexpress: Support GICC_DIR operations
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Richard Cochran @ 2017-01-03 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFcVECK1vt7Hu4tgSZ2+kKpMxoT-wpikMDq65HaxRv-EMgobHA@mail.gmail.com>
On Tue, Jan 03, 2017 at 10:36:11AM +0530, Harini Katakam wrote:
> I understand that it is not accurate - it is an initial version.
Why do you say, "it is an initial version?"
The Atmel device has this IP core burned in. The core is hopelessly
broken, and it cannot be fixed in SW either, so what is your point?
Thanks,
Richard
^ permalink raw reply
* [GIT PULL] firmware: SCPI: fixes for v4.10
From: Sudeep Holla @ 2017-01-03 10:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC Team,
Please pull !
Regards,
Sudeep
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git
tags/scpi-fixes-4.10
for you to fetch changes up to a766347b15c01507db9bf01f9b7021be5a776691:
firmware: arm_scpi: fix reading sensor values on pre-1.0 SCPI
firmwares (2016-12-30 14:53:36 +0000)
----------------------------------------------------------------
SCPI fix for v4.10
A simple fix for reading only lower 32-bit sensor values on pre-1.0 SCPI
firmwares so that upper 32-bit (garbage) value is discarded properly.
----------------------------------------------------------------
Martin Blumenstingl (1):
firmware: arm_scpi: fix reading sensor values on pre-1.0 SCPI
firmwares
drivers/firmware/arm_scpi.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
^ permalink raw reply
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-03 10:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJKOXPeEE1VwAUSAOpfyX+t58zKeAT1fe3ybp0BoQiiDBb4Uqg@mail.gmail.com>
> >> > Currently tm2e dts includes tm2 but there are some differences
> >> > between the two boards and tm2 has some properties that tm2e
> >> > doesn't have.
> >> >
> >> > That's why it's important to keep the two dts files independent
> >> > and put all the commonalities in a tm2-common.dtsi file.
> >> >
> >> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> >> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> >> > ---
> >> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
> >> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
> >> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> >>
> >> I would like to see here the rename and diff from it. Not entire delta
> >> (deletions and addons). It is not possible to compare it... I think
> >> git supports it by default with similarity of 50%.
> >
> > I understand, it's indeed quite cryptic to understand. But all
> > the diff algorithms (patience, minimal, histogram, myers) give
> > the same result. I don't know how to make it better.
> >
> > I could split this patch, but this also means breaking tm2's
> > functionality, which looks worse.
> >
> > Please tell me if you know a better way for generating the patch.
>
> git format-patch -M95%?
Same thing with all M values.
Because exynos5433-tm2.dts results modified, while
exynos5433-tm2-common.dtsi is new. Even though I did:
1. mv exynos5433-tm2.dts exynos5433-tm2-common.dtsi
2. copied pieces from exynos5433-tm2-common.dtsi to a new
exynos5433-tm2.dts
Andi
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Richard Cochran @ 2017-01-03 10:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFcVECK1vt7Hu4tgSZ2+kKpMxoT-wpikMDq65HaxRv-EMgobHA@mail.gmail.com>
On Tue, Jan 03, 2017 at 10:36:11AM +0530, Harini Katakam wrote:
> I understand that it is not accurate - it is an initial version.
No, it is not inaccurate at all, it is WRONG.
This means that time stamps will be randomly associated with PTP
network packets. To the application, the protocol will appear to
work, but the time stamp information (and thus the synchronization)
will be wrong.
To me, this is unacceptable, and I will push back on this driver
getting merged.
[ In contrast, the descriptor based approach would be ok, afaict. ]
Thanks,
Richard
^ permalink raw reply
* [PATCH] mtd: nand: lpc32xx: fix invalid error handling of a requested irq
From: Vladimir Zapolskiy @ 2017-01-03 10:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103101259.0ec123df@bbrezillon>
Hi Boris,
On 01/03/2017 11:12 AM, Boris Brezillon wrote:
> Hi Vladimir
>
> On Mon, 5 Dec 2016 03:47:10 +0200
> Vladimir Zapolskiy <vz@mleia.com> wrote:
>
>> Semantics of NR_IRQS is different on machines with SPARSE_IRQ option
>> disabled or enabled, in the latter case IRQs are allocated starting
>> at least from the value specified by NR_IRQS and going upwards, so
>> the check of (irq >= NR_IRQ) to decide about an error code returned by
>> platform_get_irq() is completely invalid, don't attempt to overrule
>> irq subsystem in the driver.
>>
>> The change fixes LPC32xx NAND MLC driver initialization on boot.
>
> Do you need to backport this fix to stable releases? If that's the
> case, I'll add the Cc: stable tag when applying.
that will be great if you can add
Cc: stable at kernel.org # v4.7+
Please feel free to add also the tag
Fixes: 8cb17b5ed017 ("irqchip: Add LPC32xx interrupt controller driver")
--
With best wishes,
Vladimir
^ permalink raw reply
* [RFC PATCH] sched: Remove set_task_state()
From: Mark Rutland @ 2017-01-03 10:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483121873-21528-1-git-send-email-dave@stgolabs.net>
On Fri, Dec 30, 2016 at 10:17:53AM -0800, Davidlohr Bueso wrote:
> Secondly for a higher overview, an unlink microbenchmark was used,
> which pounds on a single file with open, close,unlink combos with
> increasing thread counts (up to 4x ncpus). While the workload is
> quite unrealistic, it does contend a lot on the inode mutex or now
> rwsem. With the archs I had access to, the differences are as follows:
>
> == 1. arm64 ==
>
> 0000000000002784 <set_task_state>:
> 2784: f9000c1f str xzr, [x0,#24]
>
> 0000000000002790 <set_current_state>:
> 2790: d5384100 mrs x0, sp_el0
> 2794: f9000c1f str xzr, [x0,#24]
>
> Avg runtime set_task_state(): 2648 msecs
> Avg runtime set_current_state(): 2686 msecs
> Unsurprisingly, the big looser is arm64, due to the masking of sp_el0.
> otoh, x86-64 (known to be fast for get_current()/this_cpu_read_stable()
> caching) and ppc64 (with paca) show similar improvements in the unlink
> microbenches. x86's write latencies delta is similar to the opposite of
> arm64: 50ms vs -40ms, respectively. The small delta for ppc64 (2ms), does
> not represent the gains on the unlink runs. In the case of x86, there was
> a decent amount of variation in the latency runs, but always within a 20
> to 50ms increase), ppc was more constant.
>
> So, do we want to get rid of the interface (and improve performance on
> other archs) at the expense of arm64? Can arm64 do better?
We can defineitely do better; the asm constraints in read_sysreg() are
overly pessimistic for get_current().
Does the below help?
Thanks,
Mark.
---->8----
diff --git a/arch/arm64/include/asm/current.h b/arch/arm64/include/asm/current.h
index f2bcbe2..c9ba5ac 100644
--- a/arch/arm64/include/asm/current.h
+++ b/arch/arm64/include/asm/current.h
@@ -11,7 +11,11 @@
static __always_inline struct task_struct *get_current(void)
{
- return (struct task_struct *)read_sysreg(sp_el0);
+ struct task_struct *tsk;
+
+ asm ("mrs %0, sp_el0" : "=r" (tsk));
+
+ return tsk;
}
#define current get_current()
^ permalink raw reply related
* [PATCH v5 0/6] arm64: arch_timer: Add workaround for hisilicon-161601 erratum
From: Hanjun Guo @ 2017-01-03 10:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482476669-15596-1-git-send-email-dingtianhong@huawei.com>
Hi Ding,
On 2016/12/23 15:04, Ding Tianhong wrote:
> Erratum Hisilicon-161601 says that the ARM generic timer counter "has the
> potential to contain an erroneous value when the timer value changes".
> Accesses to TVAL (both read and write) are also affected due to the implicit counter
> read. Accesses to CVAL are not affected.
>
> The workaround is to reread the system count registers until the value of the second
> read is larger than the first one by less than 32, the system counter can be guaranteed
> not to return wrong value twice by back-to-back read and the error value is always larger
> than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
>
> v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601.
> Significant rework based on feedback, including seperate the fsl erratum a008585
> to another patch, update the erratum name and remove unwanted code.
>
> v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
> and make the #define __fsl_a008585_read_reg to be private to the .c file instead of
> being globally visible. After discussion with Marc and Will, a consensus decision was
> made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,
> and make some generic name more specific, export timer_unstable_counter_workaround
> for module access.
>
> Significant rework based on feedback, including fix some alignment problem, make the
> #define __hisi_161601_read_reg to be private to the .c file instead of being globally
> visible, add more accurate annotation and modify a bit of logical format to enable
> arch_timer_read_ool_enabled, remove the kernel commandline parameter
> clocksource.arm_arch_timer.hisilicon-161601.
>
> Introduce a generic aquick framework for erratum in ACPI mode.
>
> v4: rename the quirk handler parameter to make it more generic, and
> avoid break loop when handling the quirk becasue it need to
> support multi quirks handler.
>
> update some data structures for acpi mode.
>
> v5: Adapt the new kernel-parameters.txt for latest kernel version.
> Set the retries of reread system counter to 50, because it is possible
> that some interrupts may lead to more than twice read errors and break the loop,
> it will trigger the warning, so we set the number of retries far beyond the number of
> iterations the loop has been observed to take.
>
> Ding Tianhong (4):
> arm64: arch_timer: Add device tree binding for hisilicon-161601
> erratum
> arm64: arch_timer: Introduce a generic erratum handing mechanism for
> fsl-a008585
> arm64: arch_timer: Work around Erratum Hisilicon-161601
> arm64: arch timer: Add timer erratum property for Hip05-d02 and
> Hip06-d03
>
> Hanjun Guo (2):
> arm64: arch_timer: apci: Introduce a generic aquirk framework for
> erratum
> arm64: arch_timer: acpi: add hisi timer errata data
Since the ACPI code is conflict with Fuwei's GTDT patch set, let's split this patch
set into two parts, one is the DT based code, and the other is the ACPI part,
I will rebase ACPI code on top of Fuwei's patch set so please go upstream first.
Thanks
Hanjun
^ permalink raw reply
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-03 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103095842.h3hl64amje4qv4ts@gangnam.samsung>
On Tue, Jan 3, 2017 at 11:58 AM, Andi Shyti <andi.shyti@samsung.com> wrote:
> Hi Krzysztof,
>
>> > Currently tm2e dts includes tm2 but there are some differences
>> > between the two boards and tm2 has some properties that tm2e
>> > doesn't have.
>> >
>> > That's why it's important to keep the two dts files independent
>> > and put all the commonalities in a tm2-common.dtsi file.
>> >
>> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
>> > ---
>> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
>> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
>> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
>> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
>> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>>
>> I would like to see here the rename and diff from it. Not entire delta
>> (deletions and addons). It is not possible to compare it... I think
>> git supports it by default with similarity of 50%.
>
> I understand, it's indeed quite cryptic to understand. But all
> the diff algorithms (patience, minimal, histogram, myers) give
> the same result. I don't know how to make it better.
>
> I could split this patch, but this also means breaking tm2's
> functionality, which looks worse.
>
> Please tell me if you know a better way for generating the patch.
git format-patch -M95%?
Krzysztof
^ permalink raw reply
* [PATCH v1] mtd: nand: tango: Reset pbus to raw mode in probe
From: Marc Gonzalez @ 2017-01-03 10:01 UTC (permalink / raw)
To: linux-arm-kernel
Linux should not expect the boot loader to properly configure the
peripheral bus "pad mode", so reset PBUS_PAD_MODE to raw.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
---
drivers/mtd/nand/tango_nand.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/tango_nand.c b/drivers/mtd/nand/tango_nand.c
index d370c0382808..2456640fe4d5 100644
--- a/drivers/mtd/nand/tango_nand.c
+++ b/drivers/mtd/nand/tango_nand.c
@@ -644,6 +644,8 @@ static int tango_nand_probe(struct platform_device *pdev)
if (IS_ERR(nfc->pbus_base))
return PTR_ERR(nfc->pbus_base);
+ writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
+
clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-03 9:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJKOXPev9m07_dQWAvJ+=MKnbT0TFERKOtjWUDU+WXdGAiRyDA@mail.gmail.com>
Hi Krzysztof,
> > Currently tm2e dts includes tm2 but there are some differences
> > between the two boards and tm2 has some properties that tm2e
> > doesn't have.
> >
> > That's why it's important to keep the two dts files independent
> > and put all the commonalities in a tm2-common.dtsi file.
> >
> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> > ---
> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>
> I would like to see here the rename and diff from it. Not entire delta
> (deletions and addons). It is not possible to compare it... I think
> git supports it by default with similarity of 50%.
I understand, it's indeed quite cryptic to understand. But all
the diff algorithms (patience, minimal, histogram, myers) give
the same result. I don't know how to make it better.
I could split this patch, but this also means breaking tm2's
functionality, which looks worse.
Please tell me if you know a better way for generating the patch.
Thanks,
Andi
^ permalink raw reply
* [PATCH v4] arm64: Add DTS support for FSL's LS1012A SoC
From: Harninder Rai @ 2017-01-03 9:57 UTC (permalink / raw)
To: linux-arm-kernel
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.
Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:
- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.
- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.
- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.
- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
Changes in v4: Incorporated Shawn's comments
- Convert "regulator_3p3v: regulator" to "reg_3p3v: regulator-3p3v"
- Add "status = "disabled"" property in sata and duart nodes
Changes in v3: Incorporated Leo's comments
- Change PPI interrupts to IRQ_TYPE_LEVEL_LOW and
- SPI interrupts to IRQ_TYPE_LEVEL_HIGH
Changes in v2: Incorporated Shawn's comments
- Brief introduction of the SoC in commit message
- Alphabetic ordering of labeled nodes
- Better naming to be used for regulator node
- Make timer node's comments more readable
- Sort nodes with unit-address in order of the address
arch/arm64/boot/dts/freescale/Makefile | 3 +
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 115 ++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 128 +++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 59 +++++
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 247 +++++++++++++++++++++
5 files changed, 552 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6602718..39db645 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,3 +1,6 @@
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000..a619f64
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -0,0 +1,115 @@
+/*
+ * Device Tree file for Freescale LS1012A Freedom Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A Freedom Board";
+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <25000000>;
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ codec: sgtl5000 at a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ VDDA-supply = <®_1p8v>;
+ VDDIO-supply = <®_1p8v>;
+ clocks = <&sys_mclk>;
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
new file mode 100644
index 0000000..14a67f1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -0,0 +1,128 @@
+/*
+ * Device Tree file for Freescale LS1012A QDS Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A QDS Board";
+ compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <24576000>;
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9547 at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ codec: sgtl5000 at a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ clocks = <&sys_mclk>;
+ };
+ };
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
new file mode 100644
index 0000000..62c5c71
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -0,0 +1,59 @@
+/*
+ * Device Tree file for Freescale LS1012A RDB Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A RDB Board";
+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
new file mode 100644
index 0000000..cffebb4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -0,0 +1,247 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "fsl,ls1012a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+ <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
+ <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x2000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&dcfg>;
+ offset = <0xb0>;
+ mask = <0x02>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1012a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1012a-dcfg",
+ "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ big-endian;
+ };
+
+ clockgen: clocking at 1ee1000 {
+ compatible = "fsl,ls1012a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ i2c0: i2c at 2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ gpio0: gpio at 2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio at 2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wdog0: wdog at 2ad0000 {
+ compatible = "fsl,ls1012a-wdt",
+ "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ big-endian;
+ };
+
+ sai1: sai at 2b50000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b50000 0x0 0x10000>;
+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
+ <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 47>,
+ <&edma0 1 46>;
+ status = "disabled";
+ };
+
+ sai2: sai at 2b60000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b60000 0x0 0x10000>;
+ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
+ <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 45>,
+ <&edma0 1 44>;
+ status = "disabled";
+ };
+
+ edma0: edma at 2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
+ <0 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 3>,
+ <&clockgen 4 3>;
+ };
+
+ sata: sata at 3200000 {
+ compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH 1/2] ARM: hyp-stub: improve ABI
From: Christoffer Dall @ 2017-01-03 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161215185717.GM14217@n2100.armlinux.org.uk>
Hi Russell,
On Thu, Dec 15, 2016 at 06:57:18PM +0000, Russell King - ARM Linux wrote:
> On Thu, Dec 15, 2016 at 03:37:15PM +0000, Marc Zyngier wrote:
> > On 15/12/16 15:15, Russell King - ARM Linux wrote:
> > > On Thu, Dec 15, 2016 at 11:46:41AM +0000, Marc Zyngier wrote:
> > >> On 15/12/16 11:35, Russell King - ARM Linux wrote:
> > >>> On Thu, Dec 15, 2016 at 11:18:48AM +0000, Marc Zyngier wrote:
> > >>>> On 14/12/16 10:46, Russell King wrote:
> > >>>>> @@ -231,10 +244,14 @@ ENDPROC(__hyp_stub_do_trap)
> > >>>>> * initialisation entry point.
> > >>>>> */
> > >>>>> ENTRY(__hyp_get_vectors)
> > >>>>> - mov r0, #-1
> > >>>>> + mov r0, #HVC_GET_VECTORS
> > >>>>
> > >>>> This breaks the KVM implementation of __hyp_get_vectors, easily fixed
> > >>>> with the following patchlet:
> > >>>
> > >>> Right, so what Mark said is wrong:
> > >>>
> > >>> "The hyp-stub is part of the kernel image, and the API is private to
> > >>> that particular image, so we can change things -- there's no ABI to
> > >>> worry about."
> > >>
> > >> I think Mark is right. The API *is* private to the kernel, and KVM being
> > >> the only in-kernel hypervisor on ARM, this is not an ABI.
> > >
> > > Again, that's wrong.
> > >
> > > We have two hypervisors in the kernel. One is KVM, the other is the
> > > stub. Sure, the stub isn't a full implementation of a hypervisor, but
> > > it is nevertheless, for the purposes of _this_ discussion, a hypervisor
> > > of sorts.
> > >
> > > The reason that both are included is because they both appear to share
> > > a common interface (although that's totally not documented anywhere.)
> >
> > And this interface exists for the sole purpose of enabling KVM. Call it
> > a hypervisor if you wish, but its usefulness is doubtful on its own.
> >
> > >>> So no, I'm going with my original patch (which TI has tested) which is
> > >>> the minimal change, and if we _then_ want to rework the HYP mode
> > >>> interfaces, that's the time to do the other changes when more people
> > >>> (such as KVM folk) are paying attention and we can come to a cross-
> > >>> hypervisor agreement on what the interface should be.
> > >>
> > >> Given that there is a single in-kernel hypervisor, I can't really see
> > >> who we're going to agree anything with...
> > >
> > > As far as I can see, the hyp-stub falls under ARM arch maintanence.
> > > KVM falls under KVM people. Two different groups, we need agreement
> > > between them what a sane API for both "hypervisors" should be.
> >
> > Well, I though we had the right level of discussion by reviewing your
> > patches and coming up with improvements. If you're after something else,
> > please let me know.
>
> What I'm after is a meaningful discussion between ARM arch maintainers
> and KVM maintainers - so far all I see are people on the ARM side of
> things.
I think your patches look fine, and I agree with your suggestions on
improving the hyp ABI and documenting it.
Marc found a small problem for KVM with your patch and offered a simple
fix. I don't really see a bigger problem here?
>
> I've also yet to have any response on some of the KVM questions I raised
> earlier in this thread - again, silence from KVM people.
Sorry about my silence, I was really busy leading up to Christmas and
was offline for most of the Christmas and new years days.
I've gone back over the thread and haven't been able to spot anything
that wasn't already answered by Marc (who also maintains KVM so would be
one of the KVM people). Could you let me know which questions remain
unanswered and I can try to help?
>
> What's also coming clear is that there's very few people who understand
> all the interactions here, and the whole thing seems to be an undocumented
> mess.
I think the hyp stub has just served a very limited purpose so far, and
therefore is a somewhat immature implementation. Now we've discovered a
need to clean it up, and we're all for that. Again, I don't think the
problem is any larger than that, we just need to fix it, and it seems to
me everyone is willing to work on that. Marc even offered to work on
your suggestion to support the general hyp ABI commands in KVM.
[...]
>
> So, I want KVM further changes to come through my tree once this merge
> window is over
I think we should try to separate the discussion of fixing an immediate
problem with the hyp code, and that of how to maintain things. I think
we're already on the right track to fix the former.
Before we start changing up maintainerships (which I personally think
work fine as it is) I would encourage you to just comment on patches
touching arch/arm that you are unhappy with.
We have been cc'ing all our changes to lakml and we've tried to cc you
specifically on anything touching arch/arm, and we will listen to any
suggestions you may have.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH v2 1/4] pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433
From: Andi Shyti @ 2017-01-03 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230150932.q7kadv4ouhdrkqea@kozik-lap>
Hi Linus and Krzysztof,
> > > From: Chanwoo Choi <cw00.choi@samsung.com>
> > >
> > > This patch fixes the wrong width of PINCFG_TYPE_DRV bitfields for Exynos5433
> > > because PINCFG_TYPE_DRV of Exynos5433 has 4bit fields in the *_DRV
> > > registers. Usually, other Exynos have 2bit field for PINCFG_TYPE_DRV.
> > >
> > > Fixes: 3c5ecc9ed353 ("pinctrl: exynos: Add support for Exynos5433")
> > > Cc: stable at vger.kernel.org
> > > Cc: Tomasz Figa <tomasz.figa@gmail.com>
> > > Cc: Krzysztof Kozlowski <krzk@kernel.org>
> > > Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> > > Cc: Linus Walleij <linus.walleij@linaro.org>
> > > Cc: Kukjin Kim <kgene@kernel.org>
> > > Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> > > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> >
> > Nominally I think you should sign this off too Andi, as you are in the delivery
> > path.
> >
> > Patch applied for fixes.
>
> That has to be signed by Andi... otherwise the chain is broken (and
> there could be changes added inside).
yes, sorry about this. If Linus wants and it's not too late, he
can add my signed off at the bottom.
Thanks,
Andi
^ permalink raw reply
* [PATCH v6 05/14] ACPI: platform-msi: retrieve dev id from IORT
From: Tomasz Nowicki @ 2017-01-03 9:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <13cb0c87-e1c0-c4d6-4793-a3edd20944dc@semihalf.com>
On 03.01.2017 09:43, Tomasz Nowicki wrote:
> On 02.01.2017 14:31, Hanjun Guo wrote:
>> For devices connecting to ITS, it needs dev id to identify
>> itself, and this dev id is represented in the IORT table in
>> named componant node [1] for platform devices, so in this
>> patch we will scan the IORT to retrieve device's dev id.
>>
>> Introduce iort_pmsi_get_dev_id() with pointer dev passed
>> in for that purpose.
>>
>> [1]:
>> https://static.docs.arm.com/den0049/b/DEN0049B_IO_Remapping_Table.pdf
>>
>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>> Tested-by: Sinan Kaya <okaya@codeaurora.org>
>> Tested-by: Majun <majun258@huawei.com>
>> Tested-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Cc: Tomasz Nowicki <tn@semihalf.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> ---
>> drivers/acpi/arm64/iort.c | 26
>> ++++++++++++++++++++++++++
>> drivers/irqchip/irq-gic-v3-its-platform-msi.c | 4 +++-
>> include/linux/acpi_iort.h | 8 ++++++++
>> 3 files changed, 37 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index 174e983..ab7bae7 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -444,6 +444,32 @@ u32 iort_msi_map_rid(struct device *dev, u32 req_id)
>> }
>>
>> /**
>> + * iort_pmsi_get_dev_id() - Get the device id for a device
>> + * @dev: The device for which the mapping is to be done.
>> + * @dev_id: The device ID found.
>> + *
>> + * Returns: 0 for successful find a dev id, errors otherwise
>> + */
>> +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
>> +{
>> + struct acpi_iort_node *node;
>> +
>> + if (!iort_table)
>> + return -ENODEV;
>> +
>> + node = iort_find_dev_node(dev);
>> + if (!node) {
>> + dev_err(dev, "can't find related IORT node\n");
>> + return -ENODEV;
>> + }
>> +
>> + if(!iort_node_get_id(node, dev_id, IORT_MSI_TYPE, 0))
>> + return -ENODEV;
>> +
>> + return 0;
>> +}
>> +
>> +/**
> Giving that you are extending this to NC->
> SMMU->ITS case in later patch, we can use existing helpers from iort.c,
> like that:
>
> +/**
> + * iort_pmsi_get_dev_id() - Get the device id for a device
> + * @dev: The device for which the mapping is to be done.
> + * @dev_id: The device ID found.
> + *
> + * Returns: 0 for successful find a dev id, errors otherwise
> + */
> +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
> +{
> + struct acpi_iort_node *node;
> +
> + node = iort_find_dev_node(dev);
> + if (!node)
> + return -ENODEV;
> +
> + if (!iort_node_map_rid(node, 0, dev_id, IORT_MSI_TYPE))
> + return -ENODEV;
> +
> + return 0;
> +}
>
> Correct me if I am wrong.
>
"0" as rid_in for iort_node_map_rid() isn't good idea, sorry...
Tomasz
^ permalink raw reply
* [PATCH 15/20] ARM/hw_breakpoint: Convert to hotplug state machine
From: Mark Rutland @ 2017-01-03 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdaxAPSU-XPQrgVRoBecAD1ZpVVP4qPe59af-yy11WqBQw@mail.gmail.com>
Hi,
On Mon, Jan 02, 2017 at 09:15:29PM +0100, Linus Walleij wrote:
> On Mon, Jan 2, 2017 at 4:00 PM, Russell King - ARM Linux
> <linux@armlinux.org.uk> wrote:
> > On Mon, Jan 02, 2017 at 03:34:32PM +0100, Linus Walleij wrote:
> >> in the first line of arch_hw_breakpoint_init() in
> >> arch/arm/kernel/hw_breakpoint.c
> >>
> >> I suspect that is not an accepable solution ...
> >>
> >> It hangs at PC is at write_wb_reg+0x20c/0x330
> >> Which is c03101dc, and looks like this in objdump -d:
> >>
> >> c031020c: ee001eba mcr 14, 0, r1, cr0, cr10, {5}
> >> c0310210: eaffffb3 b c03100e4 <write_wb_reg+0x114>
> >
> > ... and this is several instructions after the address you mention above.
> > Presumably c03101dc is accessing a higher numbered register?
>
> Ah sorry. It looks like this:
>
> c03101dc: ee001ed0 mcr 14, 0, r1, cr0, cr0, {6}
> c03101e0: eaffffbf b c03100e4 <write_wb_reg+0x114>
> c03101e4: ee001ebf mcr 14, 0, r1, cr0, cr15, {5}
> c03101e8: eaffffbd b c03100e4 <write_wb_reg+0x114>
> c03101ec: ee001ebe mcr 14, 0, r1, cr0, cr14, {5}
> c03101f0: eaffffbb b c03100e4 <write_wb_reg+0x114>
> c03101f4: ee001ebd mcr 14, 0, r1, cr0, cr13, {5}
> c03101f8: eaffffb9 b c03100e4 <write_wb_reg+0x114>
FWIW, I was tracking an issue in this area before the holiday.
It looked like DBGPRSR.SPD is set unexpectedly over the default idle
path (i.e. WFI), causing the (otherwise valid) register accesses above
to be handled as undefined.
I haven't looked at the patch in detail, but I guess that it allows idle
to occur between reset_ctrl_regs() and arch_hw_breakpoint_init().
Reading DBGPRSR should clear SPD; but I'm not sure if other debug state
is affected.
Thanks,
Mark.
^ permalink raw reply
* [RFC PATCH] sched: Remove set_task_state()
From: Peter Zijlstra @ 2017-01-03 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483121873-21528-1-git-send-email-dave@stgolabs.net>
On Fri, Dec 30, 2016 at 10:17:53AM -0800, Davidlohr Bueso wrote:
> - set_task_state(current, TASK_RUNNING);
> + set_current_state(TASK_RUNNING);
Obviously good.
> - set_task_state(tsk, TASK_UNINTERRUPTIBLE);
> + set_current_state(TASK_UNINTERRUPTIBLE);
Not so much..
So while I fully support this move, should we not first clean up the
code and also remove all the local 'tsk = current' variables such that
all replacements end up being obvious?
In any case, would be good to hear from arm64 folks.
^ permalink raw reply
* [PATCH] ARM: dts: r8a7794: link DU to VSPD
From: Laurent Pinchart @ 2017-01-03 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1524349.7vYNCWaVjE@wasted.cogentembedded.com>
Hi Sergei,
On Thursday 29 Dec 2016 00:35:07 Sergei Shtylyov wrote:
> Add the "vsps" property to the DU device node in order to link this node to
> the (single) VSPD node.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
I'd like to first address the issues I've pointed out on the driver side of
this change.
> ---
> This patch is against the 'renesas-devel-20161220-v4.9' of Simon Horman's
> 'renesas.git' repo. It's only meaningful if the "Enable R8A7794 DU VSPD
> compositor" DU driver patches are applied...
>
> arch/arm/boot/dts/r8a7794.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> Index: renesas/arch/arm/boot/dts/r8a7794.dtsi
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7794.dtsi
> @@ -908,7 +908,7 @@
> power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
> };
>
> - vsp1 at fe930000 {
> + vspd0: vsp1 at fe930000 {
> compatible = "renesas,vsp1";
> reg = <0 0xfe930000 0 0x8000>;
> interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> @@ -925,6 +925,7 @@
> clocks = <&mstp7_clks R8A7794_CLK_DU0>,
> <&mstp7_clks R8A7794_CLK_DU0>;
> clock-names = "du.0", "du.1";
> + vsps = <&vspd0>;
> status = "disabled";
>
> ports {
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH] ARM: dts: r8a7791: link DU to VSPDs
From: Laurent Pinchart @ 2017-01-03 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1922293.x1RvWWSErN@wasted.cogentembedded.com>
Hi Sergei,
On Thursday 15 Dec 2016 01:07:52 Sergei Shtylyov wrote:
> Add the "vsps" property to the DU device node in order to link this node to
> the VSPD nodes.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
I'd like to first address the issues I've pointed out on the driver side of
this change.
> ---
> This patch is against the 'renesas-devel-20161212-v4.9' of Simon Horman's
> 'renesas.git' repo. It's only meaningful if the DU driver patch I've just
> posted is applied.
>
> arch/arm/boot/dts/r8a7791.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> Index: renesas/arch/arm/boot/dts/r8a7791.dtsi
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7791.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7791.dtsi
> @@ -989,7 +989,7 @@
> power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
> };
>
> - vsp1 at fe930000 {
> + vspd0: vsp1 at fe930000 {
> compatible = "renesas,vsp1";
> reg = <0 0xfe930000 0 0x8000>;
> interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> @@ -997,7 +997,7 @@
> power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
> };
>
> - vsp1 at fe938000 {
> + vspd1: vsp1 at fe938000 {
> compatible = "renesas,vsp1";
> reg = <0 0xfe938000 0 0x8000>;
> interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1016,6 +1016,7 @@
> <&mstp7_clks R8A7791_CLK_DU1>,
> <&mstp7_clks R8A7791_CLK_LVDS0>;
> clock-names = "du.0", "du.1", "lvds.0";
> + vsps = <&vspd0 &vspd1>;
> status = "disabled";
>
> ports {
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH] serial: mxs-auart: support CMSPAR termios cflag
From: Stefan Wahren @ 2017-01-03 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161212072101.9909-1-weo@reccoware.de>
Hi Wolfgang,
> If CMSPAR is set in the c_cflag of termios, "stick" parity is enabled.
you can have my
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
for this version 2 from 12.12.2016.
But in order to increase the chance that your patch get merged, please
resend your patch:
* with the correct version in your subject line
* not during the merge window
* with my Acked-by
* with a copy to linux-serial at vger.kernel.org
Thanks
Stefan
^ permalink raw reply
* [PATCH v6 6/8] IIO: add STM32 timer trigger driver
From: Benjamin Gaignard @ 2017-01-03 9:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c46e6e59-b5b6-39e6-d6f4-5ca4539f746c@kernel.org>
2017-01-02 19:22 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
> On 02/01/17 08:46, Benjamin Gaignard wrote:
>> 2016-12-30 22:12 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
>>> On 09/12/16 14:15, Benjamin Gaignard wrote:
>>>> Timers IPs can be used to generate triggers for other IPs like
>>>> DAC, ADC or other timers.
>>>> Each trigger may result of timer internals signals like counter enable,
>>>> reset or edge, this configuration could be done through "master_mode"
>>>> device attribute.
>>>>
>>>> A timer device could be triggered by other timers, we use the trigger
>>>> name and is_stm32_iio_timer_trigger() function to distinguish them
>>>> and configure IP input switch.
>>>>
>>>> Timer may also decide on which event (edge, level) they could
>>>> be activated by a trigger, this configuration is done by writing in
>>>> "slave_mode" device attribute.
>>>>
>>>> Since triggers could also be used by DAC or ADC their names are defined
>>>> in include/ nux/iio/timer/stm32-timer-trigger.h so those IPs will be able
>>>> to configure themselves in valid_trigger function
>>>>
>>>> Trigger have a "sampling_frequency" attribute which allow to configure
>>>> timer sampling frequency without using PWM interface
>>>>
>>>> version 5:
>>>> - simplify tables of triggers
>>>> - only create an IIO device when needed
>>>>
>>>> version 4:
>>>> - get triggers configuration from "reg" in DT
>>>> - add tables of triggers
>>>> - sampling frequency is enable/disable when writing in trigger
>>>> sampling_frequency attribute
>>>> - no more use of interruptions
>>>>
>>>> version 3:
>>>> - change compatible to "st,stm32-timer-trigger"
>>>> - fix attributes access right
>>>> - use string instead of int for master_mode and slave_mode
>>>> - document device attributes in sysfs-bus-iio-timer-stm32
>>>>
>>>> version 2:
>>>> - keep only one compatible
>>>> - use st,input-triggers-names and st,output-triggers-names
>>>> to know which triggers are accepted and/or create by the device
>>> Firstly, sorry it has taken me so long to get back to this.
>>>
>>> I'm still not keen on this use of iio_device elements just to act as
>>> glue between triggers. I think we need to work out a more light weight
>>> way to do this. As you are only using them for validation and to provide
>>> somewhere to hang the control attibutes off, there is nothing stopping us
>>> moving that over to the iio_trigger instead which would avoid the messy
>>> duality going on here.
>>
>> I have add an iio_device because each hardware can generate multiple
>> triggers (up to 5: trgo, ch 1...4) and slave_mode attribute will impact all the
>> triggers of a device. For me it was making sense to centralize that in an
>> iio_device rather than having an attribute "shared" (from hardware
>> point of view)
>> on multiple triggers.
>> Since master_mode attribute is only used by trgo and not impact ch1...4
>> triggers I will move it to trigger instead of the iio_device.
>>
>> I also wanted to be able to connect triggers on a iio_device as I
>> could do for an
>> ADC with a command like 'echo "tim1_trgo" > iio_deviceX/trigger/current_trigger'
> This is interesting, but with a bit of refactoring I would think it would
> be possible to share some of that code thus allowing non IIO devices to
> bind to triggers. Ultimately I want to be able to bind a trigger to
> a trigger - I appreciate here the topology is more limited than that
> so some complexity comes in.
>
> My gut feeling is that representing that topology explicitly is hard
> to do in a remotely general way, but lets try it and see.
> We run into this sort of interdependency issue between different bits of
> the hardware all the time. Setting a value somewhere effects the configuration
> elsewhere - often the best plan is to just let that happen and leave it up to
> userspace to check for changes if it cares.
okay
>> If I change that to parent_trigger attribute it change this behavior
>> and I will have to
>> duplicated what is done in iio_trigger_write_current() to find and
>> validate triggers.
> I get the reasoning, but we still end up with something represented
> by an IIO device that isn't providing any channels at all. It's simply
> using some of the infrastructure. To my mind it is 'something else'
> and should be represented as such. I have no problem at all with
> you registering additional elements in /sysfs/bus/iio/ to represent
> these shared elements - we already have drivers that do that to
> provide some centralized infrastructure (e.g. the sysfs-trigger)
My hardware block are timers maybe I can add a channel type "IIO_TIMER"
and declare a channel with info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ)
so I will be able to write/read sampling frequency on IIO device.
> I'm worried about the scope spread we get for an IIO device otherwise.
> They serve a well defined purpose at the moment, and that isn't what
> is happening here.
>
> So my gut feeling is we are better deliberately not representing the
> inter dependence and claiming all triggers we are creating are
> independent. That way we can have a nice generic infrastructure
> that will work in all cases (be it pushing the sanity checking to
> userspace).
>
> So each trigger has direct access to what controls it. Changing anything
> can effect other triggers in weird ways.
>
> I'm finding it hard to see anything else generalizing sufficiently
> as we'll always get cases where we can't represent the topology without
> diving into the complexity of something like the media controller
> framework.
>
> Jonathan
>>
>>> I might still be missing something though!
>>>
>>> You would only I think need 3 attributes
>>>
>>> parrent_trigger
>>> and something like your master_mode and slave_mode attributes.
>>>
>>> The parrent_trigger would need some validation etc, but if we keep it
>>> within this driver initially that won't be hard to do. Checking the device
>>> parent matches will do most of it.
>>>
>>> Jonathan
>>>>
>>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>> ---
>>>> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 55 +++
>>>> drivers/iio/Kconfig | 2 +-
>>>> drivers/iio/Makefile | 1 +
>>>> drivers/iio/timer/Kconfig | 13 +
>>>> drivers/iio/timer/Makefile | 1 +
>>>> drivers/iio/timer/stm32-timer-trigger.c | 466 +++++++++++++++++++++
>>>> drivers/iio/trigger/Kconfig | 1 -
>>>> include/linux/iio/timer/stm32-timer-trigger.h | 62 +++
>>>> 8 files changed, 599 insertions(+), 2 deletions(-)
>>>> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>> create mode 100644 drivers/iio/timer/Kconfig
>>>> create mode 100644 drivers/iio/timer/Makefile
>>>> create mode 100644 drivers/iio/timer/stm32-timer-trigger.c
>>>> create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
>>>>
>>>> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>> new file mode 100644
>>>> index 0000000..26583dd
>>>> --- /dev/null
>>>> +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>> @@ -0,0 +1,55 @@
>>>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode_available
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the list possible master modes which are:
>>>> + - "reset" : The UG bit from the TIMx_EGR register is used as trigger output (TRGO).
>>>> + - "enable" : The Counter Enable signal CNT_EN is used as trigger output.
>>>> + - "update" : The update event is selected as trigger output.
>>>> + For instance a master timer can then be used as a prescaler for a slave timer.
>>>> + - "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set.
>>>> + - "OC1REF" : OC1REF signal is used as trigger output.
>>>> + - "OC2REF" : OC2REF signal is used as trigger output.
>>>> + - "OC3REF" : OC3REF signal is used as trigger output.
>>>> + - "OC4REF" : OC4REF signal is used as trigger output.
>>>> +
>>>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the current master modes.
>>>> + Writing set the master mode
>>>> +
>>>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode_available
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the list possible slave modes which are:
>>>> + - "disabled" : The prescaler is clocked directly by the internal clock.
>>>> + - "encoder_1" : Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
>>>> + - "encoder_2" : Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
>>>> + - "encoder_3" : Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
>>>> + on the level of the other input.
>>>> + - "reset" : Rising edge of the selected trigger input reinitializes the counter
>>>> + and generates an update of the registers.
>>>> + - "gated" : The counter clock is enabled when the trigger input is high.
>>>> + The counter stops (but is not reset) as soon as the trigger becomes low.
>>>> + Both start and stop of the counter are controlled.
>>>> + - "trigger" : The counter starts at a rising edge of the trigger TRGI (but it is not
>>>> + reset). Only the start of the counter is controlled.
>>>> + - "external_clock": Rising edges of the selected trigger (TRGI) clock the counter.
>>>> +
>>>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the current slave mode.
>>>> + Writing set the slave mode
>>>> +
>>>> +What: /sys/bus/iio/devices/triggerX/sampling_frequency
>>>> +KernelVersion: 4.10
>>>> +Contact: benjamin.gaignard at st.com
>>>> +Description:
>>>> + Reading returns the current sampling frequency.
>>>> + Writing an value different of 0 set and start sampling.
>>>> + Writing 0 stop sampling.
>>>> diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
>>>> index 6743b18..2de2a80 100644
>>>> --- a/drivers/iio/Kconfig
>>>> +++ b/drivers/iio/Kconfig
>>>> @@ -90,5 +90,5 @@ source "drivers/iio/potentiometer/Kconfig"
>>>> source "drivers/iio/pressure/Kconfig"
>>>> source "drivers/iio/proximity/Kconfig"
>>>> source "drivers/iio/temperature/Kconfig"
>>>> -
>>>> +source "drivers/iio/timer/Kconfig"
>>>> endif # IIO
>>>> diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
>>>> index 87e4c43..b797c08 100644
>>>> --- a/drivers/iio/Makefile
>>>> +++ b/drivers/iio/Makefile
>>>> @@ -32,4 +32,5 @@ obj-y += potentiometer/
>>>> obj-y += pressure/
>>>> obj-y += proximity/
>>>> obj-y += temperature/
>>>> +obj-y += timer/
>>>> obj-y += trigger/
>>>> diff --git a/drivers/iio/timer/Kconfig b/drivers/iio/timer/Kconfig
>>>> new file mode 100644
>>>> index 0000000..e3c21f2
>>>> --- /dev/null
>>>> +++ b/drivers/iio/timer/Kconfig
>>>> @@ -0,0 +1,13 @@
>>>> +#
>>>> +# Timers drivers
>>>> +
>>>> +menu "Timers"
>>>> +
>>>> +config IIO_STM32_TIMER_TRIGGER
>>>> + tristate "STM32 Timer Trigger"
>>>> + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST
>>>> + select IIO_TRIGGERED_EVENT
>>>> + help
>>>> + Select this option to enable STM32 Timer Trigger
>>>> +
>>>> +endmenu
>>>> diff --git a/drivers/iio/timer/Makefile b/drivers/iio/timer/Makefile
>>>> new file mode 100644
>>>> index 0000000..4ad95ec9
>>>> --- /dev/null
>>>> +++ b/drivers/iio/timer/Makefile
>>>> @@ -0,0 +1 @@
>>>> +obj-$(CONFIG_IIO_STM32_TIMER_TRIGGER) += stm32-timer-trigger.o
>>>> diff --git a/drivers/iio/timer/stm32-timer-trigger.c b/drivers/iio/timer/stm32-timer-trigger.c
>>>> new file mode 100644
>>>> index 0000000..8d16e8f
>>>> --- /dev/null
>>>> +++ b/drivers/iio/timer/stm32-timer-trigger.c
>>>> @@ -0,0 +1,466 @@
>>>> +/*
>>>> + * Copyright (C) STMicroelectronics 2016
>>>> + *
>>>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>> + *
>>>> + * License terms: GNU General Public License (GPL), version 2
>>>> + */
>>>> +
>>>> +#include <linux/iio/iio.h>
>>>> +#include <linux/iio/sysfs.h>
>>>> +#include <linux/iio/timer/stm32-timer-trigger.h>
>>>> +#include <linux/iio/trigger.h>
>>>> +#include <linux/iio/triggered_event.h>
>>>> +#include <linux/interrupt.h>
>>>> +#include <linux/mfd/stm32-timers.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/platform_device.h>
>>>> +
>>>> +#define MAX_TRIGGERS 6
>>>> +#define MAX_VALIDS 5
>>>> +
>>>> +/* List the triggers created by each timer */
>>>> +static const void *triggers_table[][MAX_TRIGGERS] = {
>>>> + { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
>>>> + { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
>>>> + { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
>>>> + { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
>>>> + { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
>>>> + { TIM6_TRGO,},
>>>> + { TIM7_TRGO,},
>>>> + { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
>>>> + { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
>>>> + { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
>>>> +};
>>>> +
>>>> +/* List the triggers accepted by each timer */
>>>> +static const void *valids_table[][MAX_VALIDS] = {
>>>> + { TIM5_TRGO, TIM2_TRGO, TIM4_TRGO, TIM3_TRGO,},
>>>> + { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
>>>> + { TIM1_TRGO, TIM8_TRGO, TIM5_TRGO, TIM4_TRGO,},
>>>> + { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
>>>> + { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
>>>> + { }, /* timer 6 */
>>>> + { }, /* timer 7 */
>>>> + { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
>>>> + { TIM2_TRGO, TIM3_TRGO,},
>>>> + { TIM4_TRGO, TIM5_TRGO,},
>>>> +};
>>>> +
>>>> +struct stm32_timer_trigger {
>>>> + struct device *dev;
>>>> + struct regmap *regmap;
>>>> + struct clk *clk;
>>>> + u32 max_arr;
>>>> + const void *triggers;
>>>> + const void *valids;
>>>> +};
>>>> +
>>>> +static int stm32_timer_start(struct stm32_timer_trigger *priv,
>>>> + unsigned int frequency)
>>>> +{
>>>> + unsigned long long prd, div;
>>>> + int prescaler = 0;
>>>> + u32 ccer, cr1;
>>>> +
>>>> + /* Period and prescaler values depends of clock rate */
>>>> + div = (unsigned long long)clk_get_rate(priv->clk);
>>>> +
>>>> + do_div(div, frequency);
>>>> +
>>>> + prd = div;
>>>> +
>>>> + /*
>>>> + * Increase prescaler value until we get a result that fit
>>>> + * with auto reload register maximum value.
>>>> + */
>>>> + while (div > priv->max_arr) {
>>>> + prescaler++;
>>>> + div = prd;
>>>> + do_div(div, (prescaler + 1));
>>>> + }
>>>> + prd = div;
>>>> +
>>>> + if (prescaler > MAX_TIM_PSC) {
>>>> + dev_err(priv->dev, "prescaler exceeds the maximum value\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + /* Check if nobody else use the timer */
>>>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>>>> + if (ccer & TIM_CCER_CCXE)
>>>> + return -EBUSY;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>> + if (!(cr1 & TIM_CR1_CEN))
>>>> + clk_enable(priv->clk);
>>>> +
>>>> + regmap_write(priv->regmap, TIM_PSC, prescaler);
>>>> + regmap_write(priv->regmap, TIM_ARR, prd - 1);
>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
>>>> +
>>>> + /* Force master mode to update mode */
>>>> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
>>>> +
>>>> + /* Make sure that registers are updated */
>>>> + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
>>>> +
>>>> + /* Enable controller */
>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static void stm32_timer_stop(struct stm32_timer_trigger *priv)
>>>> +{
>>>> + u32 ccer, cr1;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>>>> + if (ccer & TIM_CCER_CCXE)
>>>> + return;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>> + if (cr1 & TIM_CR1_CEN)
>>>> + clk_disable(priv->clk);
>>>> +
>>>> + /* Stop timer */
>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
>>>> + regmap_write(priv->regmap, TIM_PSC, 0);
>>>> + regmap_write(priv->regmap, TIM_ARR, 0);
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_store_frequency(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + const char *buf, size_t len)
>>>> +{
>>>> + struct iio_trigger *trig = to_iio_trigger(dev);
>>>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>>>> + unsigned int freq;
>>>> + int ret;
>>>> +
>>>> + ret = kstrtouint(buf, 10, &freq);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + if (freq == 0) {
>>>> + stm32_timer_stop(priv);
>>>> + } else {
>>>> + ret = stm32_timer_start(priv, freq);
>>>> + if (ret)
>>>> + return ret;
>>>> + }
>>>> +
>>>> + return len;
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_read_frequency(struct device *dev,
>>>> + struct device_attribute *attr, char *buf)
>>>> +{
>>>> + struct iio_trigger *trig = to_iio_trigger(dev);
>>>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>>>> + u32 psc, arr, cr1;
>>>> + unsigned long long freq = 0;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>> + regmap_read(priv->regmap, TIM_PSC, &psc);
>>>> + regmap_read(priv->regmap, TIM_ARR, &arr);
>>>> +
>>>> + if (psc && arr && (cr1 & TIM_CR1_CEN)) {
>>>> + freq = (unsigned long long)clk_get_rate(priv->clk);
>>>> + do_div(freq, psc);
>>>> + do_div(freq, arr);
>>>> + }
>>>> +
>>>> + return sprintf(buf, "%d\n", (unsigned int)freq);
>>>> +}
>>>> +
>>>> +static IIO_DEV_ATTR_SAMP_FREQ(0660,
>>>> + stm32_tt_read_frequency,
>>>> + stm32_tt_store_frequency);
>>>> +
>>>> +static struct attribute *stm32_trigger_attrs[] = {
>>>> + &iio_dev_attr_sampling_frequency.dev_attr.attr,
>>>> + NULL,
>>>> +};
>>>> +
>>>> +static const struct attribute_group stm32_trigger_attr_group = {
>>>> + .attrs = stm32_trigger_attrs,
>>>> +};
>>>> +
>>>> +static const struct attribute_group *stm32_trigger_attr_groups[] = {
>>>> + &stm32_trigger_attr_group,
>>>> + NULL,
>>>> +};
>>>> +
>>>> +static char *master_mode_table[] = {
>>>> + "reset",
>>>> + "enable",
>>>> + "update",
>>>> + "compare_pulse",
>>>> + "OC1REF",
>>>> + "OC2REF",
>>>> + "OC3REF",
>>>> + "OC4REF"
>>>> +};
>>>> +
>>>> +static ssize_t stm32_tt_show_master_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + char *buf)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + u32 cr2;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_CR2, &cr2);
>>>> + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
>>>> +
>>>> + return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_store_master_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + const char *buf, size_t len)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + int i;
>>>> +
>>>> + for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
>>>> + if (!strncmp(master_mode_table[i], buf,
>>>> + strlen(master_mode_table[i]))) {
>>>> + regmap_update_bits(priv->regmap, TIM_CR2,
>>>> + TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
>>>> + return len;
>>>> + }
>>>> + }
>>>> +
>>>> + return -EINVAL;
>>>> +}
>>>> +
>>>> +static IIO_CONST_ATTR(master_mode_available,
>>>> + "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
>>>> +
>>>> +static IIO_DEVICE_ATTR(master_mode, 0660,
>>>> + stm32_tt_show_master_mode,
>>>> + stm32_tt_store_master_mode,
>>>> + 0);
>>>> +
>>>> +static char *slave_mode_table[] = {
>>>> + "disabled",
>>>> + "encoder_1",
>>>> + "encoder_2",
>>>> + "encoder_3",
>>>> + "reset",
>>>> + "gated",
>>>> + "trigger",
>>>> + "external_clock",
>>>> +};
>>>> +
>>>> +static ssize_t stm32_tt_show_slave_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + char *buf)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + u32 smcr;
>>>> +
>>>> + regmap_read(priv->regmap, TIM_SMCR, &smcr);
>>>> + smcr &= TIM_SMCR_SMS;
>>>> +
>>>> + return snprintf(buf, PAGE_SIZE, "%s\n", slave_mode_table[smcr]);
>>>> +}
>>>> +
>>>> +static ssize_t stm32_tt_store_slave_mode(struct device *dev,
>>>> + struct device_attribute *attr,
>>>> + const char *buf, size_t len)
>>>> +{
>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + int i;
>>>> +
>>>> + for (i = 0; i < ARRAY_SIZE(slave_mode_table); i++) {
>>>> + if (!strncmp(slave_mode_table[i], buf,
>>>> + strlen(slave_mode_table[i]))) {
>>>> + regmap_update_bits(priv->regmap,
>>>> + TIM_SMCR, TIM_SMCR_SMS, i);
>>>> + return len;
>>>> + }
>>>> + }
>>>> +
>>>> + return -EINVAL;
>>>> +}
>>>> +
>>>> +static IIO_CONST_ATTR(slave_mode_available,
>>>> +"disabled encoder_1 encoder_2 encoder_3 reset gated trigger external_clock");
>>>> +
>>>> +static IIO_DEVICE_ATTR(slave_mode, 0660,
>>>> + stm32_tt_show_slave_mode,
>>>> + stm32_tt_store_slave_mode,
>>>> + 0);
>>>> +
>>>> +static struct attribute *stm32_timer_attrs[] = {
>>>> + &iio_dev_attr_master_mode.dev_attr.attr,
>>>> + &iio_const_attr_master_mode_available.dev_attr.attr,
>>>> + &iio_dev_attr_slave_mode.dev_attr.attr,
>>>> + &iio_const_attr_slave_mode_available.dev_attr.attr,
>>>> + NULL,
>>>> +};
>>>> +
>>>> +static const struct attribute_group stm32_timer_attr_group = {
>>>> + .attrs = stm32_timer_attrs,
>>>> +};
>>>> +
>>>> +static const struct iio_trigger_ops timer_trigger_ops = {
>>>> + .owner = THIS_MODULE,
>>>> +};
>>>> +
>>>> +static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
>>>> +{
>>>> + int ret;
>>>> + const char * const *cur = priv->triggers;
>>>> +
>>>> + while (cur && *cur) {
>>>> + struct iio_trigger *trig;
>>>> +
>>>> + trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
>>>> + if (!trig)
>>>> + return -ENOMEM;
>>>> +
>>>> + trig->dev.parent = priv->dev->parent;
>>>> + trig->ops = &timer_trigger_ops;
>>>> + trig->dev.groups = stm32_trigger_attr_groups;
>>>> + iio_trigger_set_drvdata(trig, priv);
>>>> +
>>>> + ret = devm_iio_trigger_register(priv->dev, trig);
>>>> + if (ret)
>>>> + return ret;
>>>> + cur++;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +/**
>>>> + * is_stm32_timer_trigger
>>>> + * @trig: trigger to be checked
>>>> + *
>>>> + * return true if the trigger is a valid stm32 iio timer trigger
>>>> + * either return false
>>>> + */
>>>> +bool is_stm32_timer_trigger(struct iio_trigger *trig)
>>>> +{
>>>> + return (trig->ops == &timer_trigger_ops);
>>>> +}
>>>> +EXPORT_SYMBOL(is_stm32_timer_trigger);
>>>> +
>>>> +static int stm32_validate_trigger(struct iio_dev *indio_dev,
>>>> + struct iio_trigger *trig)
>>>> +{
>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>> + const char * const *cur = priv->valids;
>>>> + unsigned int i = 0;
>>>> +
>>>> + if (!is_stm32_timer_trigger(trig))
>>>> + return -EINVAL;
>>>> +
>>>> + while (cur && *cur) {
>>>> + if (!strncmp(trig->name, *cur, strlen(trig->name))) {
>>>> + regmap_update_bits(priv->regmap,
>>>> + TIM_SMCR, TIM_SMCR_TS,
>>>> + i << TIM_SMCR_TS_SHIFT);
>>>> + return 0;
>>>> + }
>>>> + cur++;
>>>> + i++;
>>>> + }
>>>> +
>>>> + return -EINVAL;
>>>> +}
>>>> +
>>>> +static const struct iio_info stm32_trigger_info = {
>>>> + .driver_module = THIS_MODULE,
>>>> + .validate_trigger = stm32_validate_trigger,
>>>> + .attrs = &stm32_timer_attr_group,
>>>> +};
>>>> +
>>>> +static struct stm32_timer_trigger *stm32_setup_iio_device(struct device *dev)
>>>> +{
>>>> + struct iio_dev *indio_dev;
>>>> + int ret;
>>>> +
>>>> + indio_dev = devm_iio_device_alloc(dev,
>>>> + sizeof(struct stm32_timer_trigger));
>>>> + if (!indio_dev)
>>>> + return NULL;
>>>> +
>>>> + indio_dev->name = dev_name(dev);
>>>> + indio_dev->dev.parent = dev;
>>>> + indio_dev->info = &stm32_trigger_info;
>>>> + indio_dev->modes = INDIO_EVENT_TRIGGERED;
>>>> + indio_dev->num_channels = 0;
>>>> + indio_dev->dev.of_node = dev->of_node;
>>>> +
>>>> + ret = devm_iio_device_register(dev, indio_dev);
>>>> + if (ret)
>>>> + return NULL;
>>>> +
>>>> + return iio_priv(indio_dev);
>>>> +}
>>>> +
>>>> +static int stm32_timer_trigger_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct device *dev = &pdev->dev;
>>>> + struct stm32_timer_trigger *priv;
>>>> + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
>>>> + unsigned int index;
>>>> + int ret;
>>>> +
>>>> + if (of_property_read_u32(dev->of_node, "reg", &index))
>>>> + return -EINVAL;
>>>> +
>>>> + if (index >= ARRAY_SIZE(triggers_table))
>>>> + return -EINVAL;
>>>> +
>>>> + /* Create an IIO device only if we have triggers to be validated */
>>>> + if (*valids_table[index])
>>>> + priv = stm32_setup_iio_device(dev);
>>>
>>> I still don't like this. Really feels like we shouldn't be creating an
>>> iio device with all the bagage that carries just to allow us to do the
>>> trigger trees. We ought to have a much more light weight solution for this
>>> functionality - we aren't typically even using the interrupt tree stuff
>>> that the triggers for devices are all really about.
>>>
>>> A simpler approach of allowing each trigger the option of a parent seems like
>>> it would be cleaner. Could be done entirely within this driver in the first
>>> instance. Basically it would just look like your master and slave attributes
>>> but have those under triggerX not iio:deviceX.
>>>
>>> We can work out how to make it more generic later - including perhaps the
>>> option to trigger from triggers outside this driver, using some parallel
>>> infrastructure to the device triggering.
>>>
>>>
>>>> + else
>>>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>>>> +
>>>> + if (!priv)
>>>> + return -ENOMEM;
>>>> +
>>>> + priv->dev = dev;
>>>> + priv->regmap = ddata->regmap;
>>>> + priv->clk = ddata->clk;
>>>> + priv->max_arr = ddata->max_arr;
>>>> + priv->triggers = triggers_table[index];
>>>> + priv->valids = valids_table[index];
>>>> +
>>>> + ret = stm32_setup_iio_triggers(priv);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + platform_set_drvdata(pdev, priv);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static const struct of_device_id stm32_trig_of_match[] = {
>>>> + { .compatible = "st,stm32-timer-trigger", },
>>>> + { /* end node */ },
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
>>>> +
>>>> +static struct platform_driver stm32_timer_trigger_driver = {
>>>> + .probe = stm32_timer_trigger_probe,
>>>> + .driver = {
>>>> + .name = "stm32-timer-trigger",
>>>> + .of_match_table = stm32_trig_of_match,
>>>> + },
>>>> +};
>>>> +module_platform_driver(stm32_timer_trigger_driver);
>>>> +
>>>> +MODULE_ALIAS("platform: stm32-timer-trigger");
>>>> +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
>>>> +MODULE_LICENSE("GPL v2");
>>>> diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig
>>>> index 809b2e7..f2af4fe 100644
>>>> --- a/drivers/iio/trigger/Kconfig
>>>> +++ b/drivers/iio/trigger/Kconfig
>>>> @@ -46,5 +46,4 @@ config IIO_SYSFS_TRIGGER
>>>>
>>>> To compile this driver as a module, choose M here: the
>>>> module will be called iio-trig-sysfs.
>>>> -
>>> Clean this up.
>>
>> ok
>>
>>>> endmenu
>>>> diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h
>>>> new file mode 100644
>>>> index 0000000..55535ae
>>>> --- /dev/null
>>>> +++ b/include/linux/iio/timer/stm32-timer-trigger.h
>>>> @@ -0,0 +1,62 @@
>>>> +/*
>>>> + * Copyright (C) STMicroelectronics 2016
>>>> + *
>>>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>> + *
>>>> + * License terms: GNU General Public License (GPL), version 2
>>>> + */
>>>> +
>>>> +#ifndef _STM32_TIMER_TRIGGER_H_
>>>> +#define _STM32_TIMER_TRIGGER_H_
>>>> +
>>>> +#define TIM1_TRGO "tim1_trgo"
>>>> +#define TIM1_CH1 "tim1_ch1"
>>>> +#define TIM1_CH2 "tim1_ch2"
>>>> +#define TIM1_CH3 "tim1_ch3"
>>>> +#define TIM1_CH4 "tim1_ch4"
>>>> +
>>>> +#define TIM2_TRGO "tim2_trgo"
>>>> +#define TIM2_CH1 "tim2_ch1"
>>>> +#define TIM2_CH2 "tim2_ch2"
>>>> +#define TIM2_CH3 "tim2_ch3"
>>>> +#define TIM2_CH4 "tim2_ch4"
>>>> +
>>>> +#define TIM3_TRGO "tim3_trgo"
>>>> +#define TIM3_CH1 "tim3_ch1"
>>>> +#define TIM3_CH2 "tim3_ch2"
>>>> +#define TIM3_CH3 "tim3_ch3"
>>>> +#define TIM3_CH4 "tim3_ch4"
>>>> +
>>>> +#define TIM4_TRGO "tim4_trgo"
>>>> +#define TIM4_CH1 "tim4_ch1"
>>>> +#define TIM4_CH2 "tim4_ch2"
>>>> +#define TIM4_CH3 "tim4_ch3"
>>>> +#define TIM4_CH4 "tim4_ch4"
>>>> +
>>>> +#define TIM5_TRGO "tim5_trgo"
>>>> +#define TIM5_CH1 "tim5_ch1"
>>>> +#define TIM5_CH2 "tim5_ch2"
>>>> +#define TIM5_CH3 "tim5_ch3"
>>>> +#define TIM5_CH4 "tim5_ch4"
>>>> +
>>>> +#define TIM6_TRGO "tim6_trgo"
>>>> +
>>>> +#define TIM7_TRGO "tim7_trgo"
>>>> +
>>>> +#define TIM8_TRGO "tim8_trgo"
>>>> +#define TIM8_CH1 "tim8_ch1"
>>>> +#define TIM8_CH2 "tim8_ch2"
>>>> +#define TIM8_CH3 "tim8_ch3"
>>>> +#define TIM8_CH4 "tim8_ch4"
>>>> +
>>>> +#define TIM9_TRGO "tim9_trgo"
>>>> +#define TIM9_CH1 "tim9_ch1"
>>>> +#define TIM9_CH2 "tim9_ch2"
>>>> +
>>>> +#define TIM12_TRGO "tim12_trgo"
>>>> +#define TIM12_CH1 "tim12_ch1"
>>>> +#define TIM12_CH2 "tim12_ch2"
>>>> +
>>>> +bool is_stm32_timer_trigger(struct iio_trigger *trig);
>>>> +
>>>> +#endif
>>>>
>>>
>>
>>
>>
>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH] drm/meson: Fix plane atomic check when no crtc for the plane
From: Neil Armstrong @ 2017-01-03 9:20 UTC (permalink / raw)
To: linux-arm-kernel
When no CRTC is associated with the plane, the meson_plane_atomic_check()
call breaks the kernel with an Oops.
Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index 4942ca0..7890e30 100644
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -51,6 +51,9 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
struct drm_crtc_state *crtc_state;
struct drm_rect clip = { 0, };
+ if (!state->crtc)
+ return 0;
+
crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
--
1.9.1
^ permalink raw reply related
* [PATCH] ARM: davinci_all_defconfig: enable dumb vga-dac drm bridge
From: Sekhar Nori @ 2017-01-03 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480065182-7095-1-git-send-email-bgolaszewski@baylibre.com>
On Friday 25 November 2016 02:43 PM, Bartosz Golaszewski wrote:
> This enables the dumb-vga-dac driver by default for davinci boards.
>
> The driver is needed for tilcdc support on da850-lcdk board.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> arch/arm/configs/davinci_all_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
> index b5e978f..ab1bf18 100644
> --- a/arch/arm/configs/davinci_all_defconfig
> +++ b/arch/arm/configs/davinci_all_defconfig
> @@ -127,6 +127,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_REGULATOR_TPS6507X=y
> CONFIG_DRM=m
> CONFIG_DRM_TILCDC=m
> +CONFIG_DRM_BRIDGE=y
DRM_BRIDGE is a 'def_bool y'. So no need to explicitly enable it. And
actually it will get dropped with the next savedefconfig refresh anyway.
Applying this patch with this line dropped.
Thanks,
Sekhar
^ permalink raw reply
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