* [arm-platforms:kvm-arm64/gicv4-wip 9/39] include/linux/irqchip/arm-gic-v3.h:245:32: warning: left shift count >= width of type
From: kbuild test robot @ 2017-01-03 11:02 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv4-wip
head: ff003d7a3416337cc037320bfd175aaee79f05ae
commit: c02d4af9238775c4d1cfed01cf2072bc60d8c1ed [9/39] irqchip/gic-v3-its: Add probing for VLPI properties
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout c02d4af9238775c4d1cfed01cf2072bc60d8c1ed
# save the attached .config to linux build tree
make.cross ARCH=arm
All warnings (new ones prefixed by >>):
In file included from drivers/irqchip/irq-gic-v3-its.c:38:0:
drivers/irqchip/irq-gic-v3-its.c: In function 'its_probe_one':
>> include/linux/irqchip/arm-gic-v3.h:245:32: warning: left shift count >= width of type [-Wshift-count-overflow]
#define GITS_TYPER_VMOVP (1UL << 37)
^
>> drivers/irqchip/irq-gic-v3-its.c:1706:30: note: in expansion of macro 'GITS_TYPER_VMOVP'
if (its->is_v4 && !(typer & GITS_TYPER_VMOVP)) {
^~~~~~~~~~~~~~~~
vim +245 include/linux/irqchip/arm-gic-v3.h
229 #define GITS_CIDR3 0xfffc
230
231 #define GITS_TRANSLATER 0x10040
232
233 #define GITS_CTLR_ENABLE (1U << 0)
234 #define GITS_CTLR_ITS_NUMBER_SHIFT 4
235 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
236 #define GITS_CTLR_QUIESCENT (1U << 31)
237
238 #define GITS_TYPER_PLPIS (1UL << 0)
239 #define GITS_TYPER_VLPIS (1UL << 1)
240 #define GITS_TYPER_IDBITS_SHIFT 8
241 #define GITS_TYPER_DEVBITS_SHIFT 13
242 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
243 #define GITS_TYPER_PTA (1UL << 19)
244 #define GITS_TYPER_HWCOLLCNT_SHIFT 24
> 245 #define GITS_TYPER_VMOVP (1UL << 37)
246
247 #define GITS_CBASER_VALID (1ULL << 63)
248 #define GITS_CBASER_SHAREABILITY_SHIFT (10)
249 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
250 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
251 #define GITS_CBASER_SHAREABILITY_MASK \
252 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
253 #define GITS_CBASER_INNER_CACHEABILITY_MASK \
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v4 2/3] soc: zte: pm_domains: Add support for zx296718 board
From: Shawn Guo @ 2017-01-03 11:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483426577-5470-2-git-send-email-baoyou.xie@linaro.org>
On Tue, Jan 03, 2017 at 02:56:16PM +0800, Baoyou Xie wrote:
> This patch introduces the power domain driver of zx296718
> which belongs to zte's zx2967 family.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
It seems that none of the review comments I put on v3 [1] gets addressed
in this version. You missed them?
Shawn
[1] http://www.spinics.net/lists/arm-kernel/msg547691.html
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Richard Cochran @ 2017-01-03 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <BN3PR07MB25168573DD82F1681CDC8437C96E0@BN3PR07MB2516.namprd07.prod.outlook.com>
On Tue, Jan 03, 2017 at 10:47:56AM +0000, Rafal Ozieblo wrote:
> We could use only descriptor approach but there are many Atmel's cores on the market which support only event registers.
As I said in my other reply in this thread, the Atmel cores cannot
possibly be made to work correctly.
Sad, but true.
Thanks,
Richard
^ permalink raw reply
* [PATCH 1/2] arm64: setup: introduce kaslr_offset()
From: Jon Hunter @ 2017-01-03 11:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4094c1ef-0a75-7076-58e0-52ece326188b@linux.com>
Hi Will, Catalin,
On 22/12/16 12:51, Alexander Popov wrote:
> On 22.12.2016 09:18, Yury Norov wrote:
>> On Sun, Dec 11, 2016 at 03:50:55AM +0300, Alexander Popov wrote:
>>> Introduce kaslr_offset() similarly to x86_64 for fixing kcov.
>
> [...]
>
>> Hi Alexander,
>>
>> I found today's linux-next master broken:
>
> [...]
>
>> It looks like you declare kaslr_offset() twice - in this patch, and in 7ede8665f
>> (arm64: setup: introduce kaslr_offset()).
>
> Hello Yury,
>
> There was a race during applying this patch. So currently linux-next has 2 versions of it.
>
> The first one is 1a339a14b1f2c7a0dfdd6db79eee1e55d3cec357, which is original.
> The second one is 7ede8665f27cde7da69e8b2fbeaa1ed0664879c5, updated by Will Deacon and
> applied to the mainline.
>
> I'm sorry for that. The first one should be definitely dropped.
Looks like this is still broken in today's -next.
Cheers
Jon
--
nvpublic
^ permalink raw reply
* [arm-platforms:kvm-arm64/gicv4-wip 26/39] drivers/irqchip/irq-gic-v3-its.c:2053:3: error: implicit declaration of function 'writeq_relaxed'
From: kbuild test robot @ 2017-01-03 11:20 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv4-wip
head: ff003d7a3416337cc037320bfd175aaee79f05ae
commit: 0c2bc9e2fd28b4be9bc1f4e7442e0926714994d3 [26/39] irqchip/gic-v3-its: Add VPE scheduling
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 0c2bc9e2fd28b4be9bc1f4e7442e0926714994d3
# save the attached .config to linux build tree
make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:10:0,
from include/linux/list.h:8,
from include/linux/resource_ext.h:17,
from include/linux/acpi.h:26,
from drivers/irqchip/irq-gic-v3-its.c:18:
drivers/irqchip/irq-gic-v3-its.c: In function 'its_vpe_set_vcpu_affinity':
>> include/linux/bitops.h:22:27: warning: right shift count is negative [-Wshift-count-negative]
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
^
>> drivers/irqchip/irq-gic-v3-its.c:2049:4: note: in expansion of macro 'GENMASK'
GENMASK(51, 12);
^~~~~~~
>> drivers/irqchip/irq-gic-v3-its.c:2053:3: error: implicit declaration of function 'writeq_relaxed' [-Werror=implicit-function-declaration]
writeq_relaxed(val, gic_data_rdist_vlpi_base() + GICR_VPROPBASER);
^~~~~~~~~~~~~~
In file included from include/linux/kernel.h:10:0,
from include/linux/list.h:8,
from include/linux/resource_ext.h:17,
from include/linux/acpi.h:26,
from drivers/irqchip/irq-gic-v3-its.c:18:
>> include/linux/bitops.h:22:27: warning: right shift count is negative [-Wshift-count-negative]
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
^
drivers/irqchip/irq-gic-v3-its.c:2055:54: note: in expansion of macro 'GENMASK'
val = virt_to_phys(page_address(vpe->vpt_page)) & GENMASK(51, 16);
^~~~~~~
>> drivers/irqchip/irq-gic-v3-its.c:2069:9: error: implicit declaration of function 'readq_relaxed' [-Werror=implicit-function-declaration]
val = readq_relaxed(gic_data_rdist_vlpi_base() + GICR_VPENDBASER);
^~~~~~~~~~~~~
In file included from drivers/irqchip/irq-gic-v3-its.c:38:0:
drivers/irqchip/irq-gic-v3-its.c: In function 'its_probe_one':
include/linux/irqchip/arm-gic-v3.h:308:32: warning: left shift count >= width of type [-Wshift-count-overflow]
#define GITS_TYPER_VMOVP (1UL << 37)
^
drivers/irqchip/irq-gic-v3-its.c:2416:30: note: in expansion of macro 'GITS_TYPER_VMOVP'
if (its->is_v4 && !(typer & GITS_TYPER_VMOVP)) {
^~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/writeq_relaxed +2053 drivers/irqchip/irq-gic-v3-its.c
2043
2044 switch (info->cmd_type) {
2045 case SCHEDULE_VPE:
2046 {
2047 /* Schedule the VPE */
2048 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
> 2049 GENMASK(51, 12);
2050 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2051 val |= GICR_VPROPBASER_RaWb;
2052 val |= GICR_VPROPBASER_InnerShareable;
> 2053 writeq_relaxed(val, gic_data_rdist_vlpi_base() + GICR_VPROPBASER);
2054
2055 val = virt_to_phys(page_address(vpe->vpt_page)) & GENMASK(51, 16);
2056 val |= GICR_VPENDBASER_WaWb;
2057 val |= GICR_VPENDBASER_NonShareable;
2058 val |= GICR_PENDBASER_PendingLast;
2059 val |= vpe->idai ? GICR_PENDBASER_IDAI : 0;
2060 val |= GICR_PENDBASER_Valid;
2061 writeq_relaxed(val, gic_data_rdist_vlpi_base() + GICR_VPENDBASER);
2062
2063 return 0;
2064 }
2065
2066 case DESCHEDULE_VPE:
2067 {
2068 /* We're being scheduled out */
> 2069 val = readq_relaxed(gic_data_rdist_vlpi_base() + GICR_VPENDBASER);
2070 val &= ~GICR_PENDBASER_Valid;
2071 writeq_relaxed(val, gic_data_rdist_vlpi_base() + GICR_VPENDBASER);
2072
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH] ARM: OMAP1: DMA: Correct the number of logical channels
From: Peter Ujfalusi @ 2017-01-03 11:22 UTC (permalink / raw)
To: linux-arm-kernel
OMAP1510, OMAP5910 and OMAP310 have only 9 logical channels.
OMAP1610, OMAP5912, OMAP1710, OMAP730, and OMAP850 have 16 logical channels
available.
The wired 17 for the lch_count must have been used to cover the 16 + 1
dedicated LCD channel, in reality we can only use 9 or 16 channels.
The d->chan_count is not used by the omap-dma stack, so we can skip the
setup. chan_count was configured to the number of logical channels and not
the actual number of physical channels anyways.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/mach-omap1/dma.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index f6ba589cd312..c821c1d5610e 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -32,7 +32,6 @@
#include "soc.h"
#define OMAP1_DMA_BASE (0xfffed800)
-#define OMAP1_LOGICAL_DMA_CH_COUNT 17
static u32 enable_1510_mode;
@@ -348,8 +347,6 @@ static int __init omap1_system_dma_init(void)
goto exit_iounmap;
}
- d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
-
/* Valid attributes for omap1 plus processors */
if (cpu_is_omap15xx())
d->dev_caps = ENABLE_1510_MODE;
@@ -366,13 +363,14 @@ static int __init omap1_system_dma_init(void)
d->dev_caps |= CLEAR_CSR_ON_READ;
d->dev_caps |= IS_WORD_16;
- if (cpu_is_omap15xx())
- d->chan_count = 9;
- else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
- if (!(d->dev_caps & ENABLE_1510_MODE))
- d->chan_count = 16;
+ /* available logical channels */
+ if (cpu_is_omap15xx()) {
+ d->lch_count = 9;
+ } else {
+ if (d->dev_caps & ENABLE_1510_MODE)
+ d->lch_count = 9;
else
- d->chan_count = 9;
+ d->lch_count = 16;
}
p = dma_plat_info;
--
2.11.0
^ permalink raw reply related
* [PATCH 0/2] ARM: dts: boundary: fix sgtl5000 pinctrl init
From: Gary Bisson @ 2017-01-03 11:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi Shawn, all,
While testing other features, I realized that the sound card wouldn't
probe on Nitrogen6_MAX. This is because the pinctrl node was under the
sound driver node whereas it should be under the codec one.
This caused GPIO_0 not to be set as CLKO1 and therefore the codec probing
was failing. The pinctrl node is just moved around to fix it.
Also making the same patch for our SOM2 although it was working, the
reason is that U-Boot is setting GPIO_0 in U-Boot for SOM2 and not MAX.
Regards,
Gary
Gary Bisson (2):
ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init
ARM: dts: imx6qdl-nitrogen6_som2: fix sgtl5000 pinctrl init
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
--
2.11.0
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init
From: Gary Bisson @ 2017-01-03 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103112247.4563-1-gary.bisson@boundarydevices.com>
This patch fixes the following error:
sgtl5000 0-000a: Error reading chip id -6
imx-sgtl5000 sound: ASoC: CODEC DAI sgtl5000 not registered
imx-sgtl5000 sound: snd_soc_register_card failed (-517)
The problem was that the pinctrl group was linked to the sound driver
instead of the codec node. Since the codec is probed first, the sys_mclk
was missing and it would therefore fail to initialize.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
---
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index 34887a10c5f1..47ba97229a48 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -319,8 +319,6 @@
compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-nitrogen6_max-sgtl5000";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sgtl5000>;
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
@@ -402,6 +400,8 @@
codec: sgtl5000 at 0a {
compatible = "fsl,sgtl5000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <®_2p5v>;
--
2.11.0
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: imx6qdl-nitrogen6_som2: fix sgtl5000 pinctrl init
From: Gary Bisson @ 2017-01-03 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103112247.4563-1-gary.bisson@boundarydevices.com>
Since the codec is probed first, the pinctrl node should be
under the codec node.
The codec init was working for this board since U-Boot was
already setting GPIO_0 as CLKO1 but better fix it anyway.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
---
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index d80f21abea62..31d4cc62dbc7 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -250,8 +250,6 @@
compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-nitrogen6_som2-sgtl5000";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sgtl5000>;
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
@@ -320,6 +318,8 @@
codec: sgtl5000 at 0a {
compatible = "fsl,sgtl5000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <®_2p5v>;
--
2.11.0
^ permalink raw reply related
* [PATCH v6 05/14] ACPI: platform-msi: retrieve dev id from IORT
From: Tomasz Nowicki @ 2017-01-03 11:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4ab6a7e3-7aa3-367d-a333-effb24399fd5@semihalf.com>
On 03.01.2017 10:37, Tomasz Nowicki wrote:
> On 03.01.2017 09:43, Tomasz Nowicki wrote:
>> On 02.01.2017 14:31, Hanjun Guo wrote:
>>> For devices connecting to ITS, it needs dev id to identify
>>> itself, and this dev id is represented in the IORT table in
>>> named componant node [1] for platform devices, so in this
>>> patch we will scan the IORT to retrieve device's dev id.
>>>
>>> Introduce iort_pmsi_get_dev_id() with pointer dev passed
>>> in for that purpose.
>>>
>>> [1]:
>>> https://static.docs.arm.com/den0049/b/DEN0049B_IO_Remapping_Table.pdf
>>>
>>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>>> Tested-by: Sinan Kaya <okaya@codeaurora.org>
>>> Tested-by: Majun <majun258@huawei.com>
>>> Tested-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>>> Cc: Tomasz Nowicki <tn@semihalf.com>
>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>> ---
>>> drivers/acpi/arm64/iort.c | 26
>>> ++++++++++++++++++++++++++
>>> drivers/irqchip/irq-gic-v3-its-platform-msi.c | 4 +++-
>>> include/linux/acpi_iort.h | 8 ++++++++
>>> 3 files changed, 37 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>>> index 174e983..ab7bae7 100644
>>> --- a/drivers/acpi/arm64/iort.c
>>> +++ b/drivers/acpi/arm64/iort.c
>>> @@ -444,6 +444,32 @@ u32 iort_msi_map_rid(struct device *dev, u32
>>> req_id)
>>> }
>>>
>>> /**
>>> + * iort_pmsi_get_dev_id() - Get the device id for a device
>>> + * @dev: The device for which the mapping is to be done.
>>> + * @dev_id: The device ID found.
>>> + *
>>> + * Returns: 0 for successful find a dev id, errors otherwise
>>> + */
>>> +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
>>> +{
>>> + struct acpi_iort_node *node;
>>> +
>>> + if (!iort_table)
>>> + return -ENODEV;
>>> +
>>> + node = iort_find_dev_node(dev);
>>> + if (!node) {
>>> + dev_err(dev, "can't find related IORT node\n");
>>> + return -ENODEV;
>>> + }
>>> +
>>> + if(!iort_node_get_id(node, dev_id, IORT_MSI_TYPE, 0))
>>> + return -ENODEV;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +/**
>> Giving that you are extending this to NC->
>> SMMU->ITS case in later patch, we can use existing helpers from iort.c,
>> like that:
>>
>> +/**
>> + * iort_pmsi_get_dev_id() - Get the device id for a device
>> + * @dev: The device for which the mapping is to be done.
>> + * @dev_id: The device ID found.
>> + *
>> + * Returns: 0 for successful find a dev id, errors otherwise
>> + */
>> +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
>> +{
>> + struct acpi_iort_node *node;
>> +
>> + node = iort_find_dev_node(dev);
>> + if (!node)
>> + return -ENODEV;
>> +
>> + if (!iort_node_map_rid(node, 0, dev_id, IORT_MSI_TYPE))
>> + return -ENODEV;
>> +
>> + return 0;
>> +}
>>
>> Correct me if I am wrong.
>>
>
> "0" as rid_in for iort_node_map_rid() isn't good idea, sorry...
>
I refactored iort_node_map_rid() and added new
iort_node_map_single_rid() which should works for you. Below patch bases
on v4.10-rc2:
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index e0d2e6e..2526b89 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -297,8 +297,17 @@ static acpi_status iort_match_node_callback(struct
acpi_iort_node *node,
}
static int iort_id_map(struct acpi_iort_id_mapping *map, u8 type, u32
rid_in,
- u32 *rid_out)
+ u32 *rid_out, bool single)
{
+ if (!single) {
+ if (rid_in < map->input_base ||
+ (rid_in >= map->input_base + map->id_count))
+ return -ENXIO;
+
+ *rid_out = map->output_base + (rid_in - map->input_base);
+ return 0;
+ }
+
/* Single mapping does not care for input id */
if (map->flags & ACPI_IORT_ID_SINGLE_MAPPING) {
if (type == ACPI_IORT_NODE_NAMED_COMPONENT ||
@@ -309,15 +318,9 @@ static int iort_id_map(struct acpi_iort_id_mapping
*map, u8 type, u32 rid_in,
pr_warn(FW_BUG "[map %p] SINGLE MAPPING flag not allowed for node
type %d, skipping ID map\n",
map, type);
- return -ENXIO;
}
- if (rid_in < map->input_base ||
- (rid_in >= map->input_base + map->id_count))
- return -ENXIO;
-
- *rid_out = map->output_base + (rid_in - map->input_base);
- return 0;
+ return -ENXIO;
}
static
@@ -359,6 +362,38 @@ struct acpi_iort_node *iort_node_get_id(struct
acpi_iort_node *node,
return NULL;
}
+static struct acpi_iort_node *iort_node_map_rid_one(struct
acpi_iort_node *node,
+ u32 *rid, bool single)
+{
+ struct acpi_iort_id_mapping *map;
+ struct acpi_iort_node *next;
+ int i;
+
+ if (!node->mapping_offset || !node->mapping_count)
+ return NULL;
+
+ map = ACPI_ADD_PTR(struct acpi_iort_id_mapping, node,
+ node->mapping_offset);
+
+ /* Firmware bug! */
+ if (!map->output_reference) {
+ pr_err(FW_BUG "[node %p type %d] ID map has NULL parent reference\n",
+ node, node->type);
+ return NULL;
+ }
+
+ next = ACPI_ADD_PTR(struct acpi_iort_node, iort_table,
+ map->output_reference);
+
+ /* Do the RID translation */
+ for (i = 0; i < node->mapping_count; i++, map++) {
+ if (!iort_id_map(map, node->type, *rid, rid, single))
+ return next;
+ }
+
+ return NULL;
+}
+
static struct acpi_iort_node *iort_node_map_rid(struct acpi_iort_node
*node,
u32 rid_in, u32 *rid_out,
u8 type_mask)
@@ -367,42 +402,15 @@ static struct acpi_iort_node
*iort_node_map_rid(struct acpi_iort_node *node,
/* Parse the ID mapping tree to find specified node type */
while (node) {
- struct acpi_iort_id_mapping *map;
- int i;
-
if (IORT_TYPE_MASK(node->type) & type_mask) {
if (rid_out)
*rid_out = rid;
return node;
}
- if (!node->mapping_offset || !node->mapping_count)
- goto fail_map;
-
- map = ACPI_ADD_PTR(struct acpi_iort_id_mapping, node,
- node->mapping_offset);
-
- /* Firmware bug! */
- if (!map->output_reference) {
- pr_err(FW_BUG "[node %p type %d] ID map has NULL parent reference\n",
- node, node->type);
- goto fail_map;
- }
-
- /* Do the RID translation */
- for (i = 0; i < node->mapping_count; i++, map++) {
- if (!iort_id_map(map, node->type, rid, &rid))
- break;
- }
-
- if (i == node->mapping_count)
- goto fail_map;
-
- node = ACPI_ADD_PTR(struct acpi_iort_node, iort_table,
- map->output_reference);
+ node = iort_node_map_rid_one(node, &rid, false);
}
-fail_map:
/* Map input RID to output RID unchanged on mapping failure*/
if (rid_out)
*rid_out = rid_in;
@@ -410,6 +418,20 @@ static struct acpi_iort_node
*iort_node_map_rid(struct acpi_iort_node *node,
return NULL;
}
+static struct acpi_iort_node *iort_node_map_single_rid(
+ struct acpi_iort_node *node,
+ u32 *rid_out, u8 type_mask)
+{
+ u32 rid;
+
+ /* Get the initial rid */
+ node = iort_node_map_rid_one(node, &rid, true);
+ if (!node)
+ return NULL;
+
+ return iort_node_map_rid(node, rid, rid_out, type_mask);
+}
+
static struct acpi_iort_node *iort_find_dev_node(struct device *dev)
{
struct pci_bus *pbus;
^ permalink raw reply related
* [PATCH v4 1/3] soc: zte: pm_domains: Prepare for supporting ARMv8 zx2967 family
From: Shawn Guo @ 2017-01-03 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483426577-5470-1-git-send-email-baoyou.xie@linaro.org>
On Tue, Jan 03, 2017 at 02:56:15PM +0800, Baoyou Xie wrote:
> The ARMv8 zx2967 family (296718, 296716 etc) uses different value
> for controlling the power domain on/off registers, Choose the
> value depending on the compatible.
>
> Multiple domains are prepared for the family, this patch prepares
> the common functions.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> ---
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/zte/Kconfig | 13 ++++
> drivers/soc/zte/Makefile | 4 ++
> drivers/soc/zte/zx2967_pm_domains.c | 138 ++++++++++++++++++++++++++++++++++++
> drivers/soc/zte/zx2967_pm_domains.h | 45 ++++++++++++
> 6 files changed, 202 insertions(+)
> create mode 100644 drivers/soc/zte/Kconfig
> create mode 100644 drivers/soc/zte/Makefile
> create mode 100644 drivers/soc/zte/zx2967_pm_domains.c
> create mode 100644 drivers/soc/zte/zx2967_pm_domains.h
>
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index f31bceb..f09023f 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -11,5 +11,6 @@ source "drivers/soc/tegra/Kconfig"
> source "drivers/soc/ti/Kconfig"
> source "drivers/soc/ux500/Kconfig"
> source "drivers/soc/versatile/Kconfig"
> +source "drivers/soc/zte/Kconfig"
>
> endmenu
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 50c23d0..05eae52 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -16,3 +16,4 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-$(CONFIG_SOC_TI) += ti/
> obj-$(CONFIG_ARCH_U8500) += ux500/
> obj-$(CONFIG_PLAT_VERSATILE) += versatile/
> +obj-$(CONFIG_ARCH_ZX) += zte/
> diff --git a/drivers/soc/zte/Kconfig b/drivers/soc/zte/Kconfig
> new file mode 100644
> index 0000000..20bde38
> --- /dev/null
> +++ b/drivers/soc/zte/Kconfig
> @@ -0,0 +1,13 @@
> +#
> +# ZTE SoC drivers
> +#
> +menuconfig SOC_ZTE
> + bool "ZTE SoC driver support"
> +
> +if SOC_ZTE
> +
> +config ZX2967_PM_DOMAINS
> + bool "ZX2967 PM domains"
> + depends on PM_GENERIC_DOMAINS
> +
> +endif
> diff --git a/drivers/soc/zte/Makefile b/drivers/soc/zte/Makefile
> new file mode 100644
> index 0000000..8a37f2f
> --- /dev/null
> +++ b/drivers/soc/zte/Makefile
> @@ -0,0 +1,4 @@
> +#
> +# ZTE SOC drivers
> +#
> +obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx2967_pm_domains.o
> diff --git a/drivers/soc/zte/zx2967_pm_domains.c b/drivers/soc/zte/zx2967_pm_domains.c
> new file mode 100644
> index 0000000..98b3b5f
> --- /dev/null
> +++ b/drivers/soc/zte/zx2967_pm_domains.c
> @@ -0,0 +1,138 @@
> +/*
> + * Copyright (C) 2015 ZTE Ltd.
What about year 2017?
> + *
> + * Author: Baoyou Xie <baoyou.xie@linaro.org>
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
Can we have a newline between system and local includes?
> +#include "zx2967_pm_domains.h"
> +
> +#define PCU_DM_CLKEN(zpd) ((zpd)->reg_offset[REG_CLKEN])
> +#define PCU_DM_ISOEN(zpd) ((zpd)->reg_offset[REG_ISOEN])
> +#define PCU_DM_RSTEN(zpd) ((zpd)->reg_offset[REG_RSTEN])
> +#define PCU_DM_PWREN(zpd) ((zpd)->reg_offset[REG_PWREN])
> +#define PCU_DM_PWRDN(zpd) ((zpd)->reg_offset[REG_PWRDN])
> +#define PCU_DM_ACK_SYNC(zpd) ((zpd)->reg_offset[REG_ACK_SYNC])
> +
> +static void __iomem *pcubase;
> +
> +int zx2967_power_on(struct generic_pm_domain *domain)
> +{
> + struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain;
> + unsigned long loop = 1000;
> + u32 val;
> +
> + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd));
> + if (zpd->polarity == PWREN)
> + val |= BIT(zpd->bit);
> + else
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_PWRDN(zpd));
Hmm, do you really want to read val from PCU_DM_PWREN and then write
back to PCU_DM_PWRDN? They are two different registers or same one? A
bit confused here.
> +
> + do {
> + udelay(1);
> + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd))
> + & BIT(zpd->bit);
> + } while (--loop && !val);
> +
> + if (!loop) {
> + pr_err("Error: %s %s fail\n", __func__, domain->name);
> + return -EIO;
> + }
> +
> + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd));
> + val |= BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd));
> + val |= BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd));
> + udelay(5);
> +
> + pr_debug("normal poweron %s\n", domain->name);
> +
> + return 0;
> +}
> +
> +int zx2967_power_off(struct generic_pm_domain *domain)
> +{
> + struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain;
> + unsigned long loop = 1000;
> + u32 val;
> +
> + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd));
> + val |= BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd));
> + if (zpd->polarity == PWREN)
> + val &= ~BIT(zpd->bit);
> + else
> + val |= BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_PWRDN(zpd));
Ditto
> +
> + do {
> + udelay(1);
> + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd))
> + & BIT(zpd->bit);
> + } while (--loop && val);
> +
> + if (!loop) {
> + pr_err("Error: %s %s fail\n", __func__, domain->name);
> + return -EIO;
> + }
> +
> + pr_debug("normal poweroff %s\n", domain->name);
> +
> + return 0;
> +}
> +
> +int zx2967_pd_probe(struct platform_device *pdev,
> + struct generic_pm_domain **zx_pm_domains,
> + int domain_num)
Please fix the indentation as below.
int zx2967_pd_probe(struct platform_device *pdev,
struct generic_pm_domain **zx_pm_domains,
int domain_num)
> +{
> + struct genpd_onecell_data *genpd_data;
> + struct resource *res;
> + int i;
> +
> + genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL);
> + if (!genpd_data)
> + return -ENOMEM;
> +
> + genpd_data->domains = zx_pm_domains;
> + genpd_data->num_domains = domain_num;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + pcubase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(pcubase)) {
> + dev_err(&pdev->dev, "ioremap fail.\n");
> + return PTR_ERR(pcubase);
> + }
> +
> + for (i = 0; i < domain_num; ++i)
> + pm_genpd_init(zx_pm_domains[i], NULL, false);
> +
> + of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data);
> + dev_info(&pdev->dev, "powerdomain init ok\n");
> + return 0;
> +}
> diff --git a/drivers/soc/zte/zx2967_pm_domains.h b/drivers/soc/zte/zx2967_pm_domains.h
> new file mode 100644
> index 0000000..35938c3
> --- /dev/null
> +++ b/drivers/soc/zte/zx2967_pm_domains.h
> @@ -0,0 +1,45 @@
> +/*
> + * Header for ZTE's Power Domain Driver support
> + *
> + * Copyright (C) 2015 ZTE Ltd.
> + *
> + * Author: Baoyou Xie <baoyou.xie@linaro.org>
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +
> +#ifndef __ZTE_ZX2967_PM_DOMAIN_H
> +#define __ZTE_ZX2967_PM_DOMAIN_H
> +
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +
> +enum {
> + REG_CLKEN,
> + REG_ISOEN,
> + REG_RSTEN,
> + REG_PWREN,
> + REG_PWRDN,
> + REG_ACK_SYNC,
> +
> + /* The size of the array - must be last */
> + REG_ARRAY_SIZE,
> +};
> +
> +enum zx2967_power_polarity {
> + PWREN,
> + PWRDN,
> +};
> +
> +struct zx2967_pm_domain {
> + struct generic_pm_domain dm;
> + const u16 bit;
> + const enum zx2967_power_polarity polarity;
> + const u16 *reg_offset;
> +};
> +
> +extern int zx2967_power_on(struct generic_pm_domain *domain);
> +extern int zx2967_power_off(struct generic_pm_domain *domain);
> +extern int zx2967_pd_probe(struct platform_device *pdev,
> + struct generic_pm_domain **zx_pm_domains,
> + int domain_num);
Have a newline here.
Shawn
> +#endif /* __ZTE_ZX2967_PM_DOMAIN_H */
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 1/2] arm64: setup: introduce kaslr_offset()
From: Will Deacon @ 2017-01-03 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <db9266fb-5c6e-5dfb-2aac-4165c6b2b337@nvidia.com>
On Tue, Jan 03, 2017 at 11:18:15AM +0000, Jon Hunter wrote:
> On 22/12/16 12:51, Alexander Popov wrote:
> > On 22.12.2016 09:18, Yury Norov wrote:
> >> On Sun, Dec 11, 2016 at 03:50:55AM +0300, Alexander Popov wrote:
> >>> Introduce kaslr_offset() similarly to x86_64 for fixing kcov.
> >
> > [...]
> >
> >> Hi Alexander,
> >>
> >> I found today's linux-next master broken:
> >
> > [...]
> >
> >> It looks like you declare kaslr_offset() twice - in this patch, and in 7ede8665f
> >> (arm64: setup: introduce kaslr_offset()).
> >
> > Hello Yury,
> >
> > There was a race during applying this patch. So currently linux-next has 2 versions of it.
> >
> > The first one is 1a339a14b1f2c7a0dfdd6db79eee1e55d3cec357, which is original.
> > The second one is 7ede8665f27cde7da69e8b2fbeaa1ed0664879c5, updated by Will Deacon and
> > applied to the mainline.
> >
> > I'm sorry for that. The first one should be definitely dropped.
>
> Looks like this is still broken in today's -next.
I think this is coming in via akpm's tree, so there's nothing we can do
about it from the arm64 side :/
Andrew -- please can you drop 1a339a14b1f2 ("arm64: setup: introduce
kaslr_offset()") from your -next branch? It's superceded by
7ede8665f27c ("arm64: setup: introduce kaslr_offset()"), which landed
in mainline for -rc1, so you'll need to pick that up if you want your
branch to build on its own.
Thanks,
Will
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init
From: Shawn Guo @ 2017-01-03 11:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103112247.4563-2-gary.bisson@boundarydevices.com>
On Tue, Jan 03, 2017 at 12:22:46PM +0100, Gary Bisson wrote:
> This patch fixes the following error:
> sgtl5000 0-000a: Error reading chip id -6
> imx-sgtl5000 sound: ASoC: CODEC DAI sgtl5000 not registered
> imx-sgtl5000 sound: snd_soc_register_card failed (-517)
>
> The problem was that the pinctrl group was linked to the sound driver
> instead of the codec node. Since the codec is probed first, the sys_mclk
> was missing and it would therefore fail to initialize.
>
> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Should we have it go as a fix for v4.10-rc cycles? In that case, please
add a Fixes: tag. Also, do we need to apply it for stable kernel?
Shawn
> ---
> arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
> index 34887a10c5f1..47ba97229a48 100644
> --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
> @@ -319,8 +319,6 @@
> compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
> "fsl,imx-audio-sgtl5000";
> model = "imx6q-nitrogen6_max-sgtl5000";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_sgtl5000>;
> ssi-controller = <&ssi1>;
> audio-codec = <&codec>;
> audio-routing =
> @@ -402,6 +400,8 @@
>
> codec: sgtl5000 at 0a {
> compatible = "fsl,sgtl5000";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sgtl5000>;
> reg = <0x0a>;
> clocks = <&clks IMX6QDL_CLK_CKO>;
> VDDA-supply = <®_2p5v>;
> --
> 2.11.0
>
^ permalink raw reply
* [PATCH v2 2/2] mtd: nand: Update dependency of IFC for LS1021A
From: Marek Vasut @ 2017-01-03 11:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483411266-45875-2-git-send-email-b18965@freescale.com>
On 01/03/2017 03:41 AM, Alison Wang wrote:
> As NAND support for Freescale/NXP IFC controller is available on
> LS1021A, the dependency for LS1021A is added.
Does LS stand for LayerScape ? Yes it does. So why does ARCH_LAYERSCAPE
not cover LS1021 ?
> Signed-off-by: Alison Wang <alison.wang@nxp.com>
> ---
> Changes in v2:
> - None
>
> drivers/mtd/nand/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 353a9dd..85e3860 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -441,7 +441,7 @@ config MTD_NAND_FSL_ELBC
>
> config MTD_NAND_FSL_IFC
> tristate "NAND support for Freescale IFC controller"
> - depends on FSL_SOC || ARCH_LAYERSCAPE
> + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
> select FSL_IFC
> select MEMORY
> help
>
--
Best regards,
Marek Vasut
^ permalink raw reply
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Chanwoo Choi @ 2017-01-03 11:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103102548.73jg6qddlcthe2mu@gangnam.samsung>
Dear all,
2017-01-03 19:25 GMT+09:00 Andi Shyti <andi.shyti@samsung.com>:
>> >> > Currently tm2e dts includes tm2 but there are some differences
>> >> > between the two boards and tm2 has some properties that tm2e
>> >> > doesn't have.
>> >> >
>> >> > That's why it's important to keep the two dts files independent
>> >> > and put all the commonalities in a tm2-common.dtsi file.
>> >> >
>> >> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>> >> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
>> >> > ---
>> >> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
>> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
>> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
>> >> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
>> >> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>> >>
>> >> I would like to see here the rename and diff from it. Not entire delta
>> >> (deletions and addons). It is not possible to compare it... I think
>> >> git supports it by default with similarity of 50%.
>> >
>> > I understand, it's indeed quite cryptic to understand. But all
>> > the diff algorithms (patience, minimal, histogram, myers) give
>> > the same result. I don't know how to make it better.
>> >
>> > I could split this patch, but this also means breaking tm2's
>> > functionality, which looks worse.
>> >
>> > Please tell me if you know a better way for generating the patch.
>>
>> git format-patch -M95%?
>
> Same thing with all M values.
>
> Because exynos5433-tm2.dts results modified, while
> exynos5433-tm2-common.dtsi is new. Even though I did:
>
> 1. mv exynos5433-tm2.dts exynos5433-tm2-common.dtsi
> 2. copied pieces from exynos5433-tm2-common.dtsi to a new
> exynos5433-tm2.dts
I think that exynos5433-tm2-common.dtsi is not necessary because there
is small difference between TM2 and TM2E.
I explain the detailed difference between TM2 and TM2E and then reply
how to support the TM2E board with existing exynos5433-tm2.dts file
without exynos5433-tm2-common.dtsi.
Difference and the way to support TM2E with existing
exynos5433-tm2.dts file as following:
- hsi2c_9 is either used or not. TM2 uses the hsi2c_9 node for
touchkey. but TM2E do not use the hsi2c_9.
: We can just disable the hsi2c_9 node on tm2e.dts as following:
&hsi2c_9 {
status = "disable";
};
- The difference name and voltage of regulators.
: Already modified on tm2e.dts.
- The size of touchscreen between tm2 and tm2e ('x-size', 'y-size')
: We can update the x/y size on tm2e.dts.
- The timing value of display-timing between tm2 and tm2e
('clock-frequency', 'hactive')
: We can update the 'clock-frequency' and 'hactive' on tm2e.dts.
--
Best Regards,
Chanwoo Choi
^ permalink raw reply
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-03 11:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGTfZH3ez4DPTE7-bDeayjhSGxJ_8Mj1MQz1M7O1qhwOGOnmMQ@mail.gmail.com>
Hi Chanwoo,
> >> >> > Currently tm2e dts includes tm2 but there are some differences
> >> >> > between the two boards and tm2 has some properties that tm2e
> >> >> > doesn't have.
> >> >> >
> >> >> > That's why it's important to keep the two dts files independent
> >> >> > and put all the commonalities in a tm2-common.dtsi file.
> >> >> >
> >> >> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> >> >> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> >> >> > ---
> >> >> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
> >> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
> >> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
> >> >> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
> >> >> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> >> >>
[...]
> > Because exynos5433-tm2.dts results modified, while
> > exynos5433-tm2-common.dtsi is new. Even though I did:
> >
> > 1. mv exynos5433-tm2.dts exynos5433-tm2-common.dtsi
> > 2. copied pieces from exynos5433-tm2-common.dtsi to a new
> > exynos5433-tm2.dts
>
> I think that exynos5433-tm2-common.dtsi is not necessary because there
> is small difference between TM2 and TM2E.
>
> I explain the detailed difference between TM2 and TM2E and then reply
> how to support the TM2E board with existing exynos5433-tm2.dts file
> without exynos5433-tm2-common.dtsi.
>
> Difference and the way to support TM2E with existing
> exynos5433-tm2.dts file as following:
> - hsi2c_9 is either used or not. TM2 uses the hsi2c_9 node for
> touchkey. but TM2E do not use the hsi2c_9.
> : We can just disable the hsi2c_9 node on tm2e.dts as following:
>
> &hsi2c_9 {
> status = "disable";
> };
I thought about this alternative too, it just looked cleaner to
me to have a tm2-common.dtsi file.
Anyway, as you guys wish. If for you and Krzysztof is better this
way, we can drop this patch and add the above lines in the current
Jaechul's patch 4/4.
Thanks,
Andi
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init
From: Gary Bisson @ 2017-01-03 11:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103114316.GC20956@dragon>
Hi Shawn,
On Tue, Jan 03, 2017 at 07:43:17PM +0800, Shawn Guo wrote:
> On Tue, Jan 03, 2017 at 12:22:46PM +0100, Gary Bisson wrote:
> > This patch fixes the following error:
> > sgtl5000 0-000a: Error reading chip id -6
> > imx-sgtl5000 sound: ASoC: CODEC DAI sgtl5000 not registered
> > imx-sgtl5000 sound: snd_soc_register_card failed (-517)
> >
> > The problem was that the pinctrl group was linked to the sound driver
> > instead of the codec node. Since the codec is probed first, the sys_mclk
> > was missing and it would therefore fail to initialize.
> >
> > Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
>
> Should we have it go as a fix for v4.10-rc cycles? In that case, please
> add a Fixes: tag. Also, do we need to apply it for stable kernel?
Sure it'd be great if it could be in v4.10.
Fixes: b32e700256bc ("ARM: dts: imx: add Boundary Devices Nitrogen6_Max board")
As for stable kernel, I guess it wouldn't hurt but it's not mandatory in
my opinion.
Do you want me to re-send with the Fixes line? What about the SOM2
patch, should it include a Fixes line although it works thanks to
U-Boot?
Thanks,
Gary
^ permalink raw reply
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Javier Martinez Canillas @ 2017-01-03 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103115530.zhjwn7bzmqmumy23@gangnam.samsung>
Hello Andi,
On 01/03/2017 08:55 AM, Andi Shyti wrote:
> Hi Chanwoo,
>
>>>>>>> Currently tm2e dts includes tm2 but there are some differences
>>>>>>> between the two boards and tm2 has some properties that tm2e
>>>>>>> doesn't have.
>>>>>>>
>>>>>>> That's why it's important to keep the two dts files independent
>>>>>>> and put all the commonalities in a tm2-common.dtsi file.
>>>>>>>
>>>>>>> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>>>>>>> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
>>>>>>> ---
>>>>>>> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
>>>>>>> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
>>>>>>> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
>>>>>>> 3 files changed, 1049 insertions(+), 1032 deletions(-)
>>>>>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>>>>>>
>
> [...]
>
>>> Because exynos5433-tm2.dts results modified, while
>>> exynos5433-tm2-common.dtsi is new. Even though I did:
>>>
>>> 1. mv exynos5433-tm2.dts exynos5433-tm2-common.dtsi
>>> 2. copied pieces from exynos5433-tm2-common.dtsi to a new
>>> exynos5433-tm2.dts
>>
>> I think that exynos5433-tm2-common.dtsi is not necessary because there
>> is small difference between TM2 and TM2E.
>>
>> I explain the detailed difference between TM2 and TM2E and then reply
>> how to support the TM2E board with existing exynos5433-tm2.dts file
>> without exynos5433-tm2-common.dtsi.
>>
>> Difference and the way to support TM2E with existing
>> exynos5433-tm2.dts file as following:
>> - hsi2c_9 is either used or not. TM2 uses the hsi2c_9 node for
>> touchkey. but TM2E do not use the hsi2c_9.
>> : We can just disable the hsi2c_9 node on tm2e.dts as following:
>>
>> &hsi2c_9 {
>> status = "disable";
>> };
>
> I thought about this alternative too, it just looked cleaner to
> me to have a tm2-common.dtsi file.
>
> Anyway, as you guys wish. If for you and Krzysztof is better this
> way, we can drop this patch and add the above lines in the current
> Jaechul's patch 4/4.
>
FWIW, I also agree with Chanwoo that the difference is too small to
need a common .dtsi file.
> Thanks,
> Andi
>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH v4 0/5] mfd: dt: Add bindings for the Aspeed MFDs
From: Lee Jones @ 2017-01-03 12:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4e69b379-299f-ebf3-3a61-9ac1bcaba7b3@acm.org>
On Thu, 22 Dec 2016, Corey Minyard wrote:
> It looks like this is ready. Should I take this in the IPMI tree, or is
> there a better tree for it?
Please refrain from top posting.
Judging by the diff, it looks like the MFD tree would be the most
appropriate place to merge these into.
> On 12/20/2016 01:15 AM, Andrew Jeffery wrote:
> > Hi Lee,
> >
> > Here's v4 of the Aspeed LPC MFD devicetree bindings series. v3 can be found at:
> >
> > https://lkml.org/lkml/2016/12/5/835
> >
> > Changes since v3:
> >
> > * Based on Arnd's argument[1], drop the addition of the mfd/syscon bindings
> > directory as well as the the last patch in v3, which moved a number of
> > existing bindings. Eventually the Aspeed display controller will have a
> > device-specific driver so it doesn't belong there either.
> >
> > * Add a compatible string for the AST2400 in the LPC Host Controller bindings
> > as requested by Joel and slightly tweak the reg description for Rob.
> >
> > [1] https://lkml.org/lkml/2016/12/13/202
> >
> > Andrew Jeffery (5):
> > mfd: dt: Fix "indicates" typo in mfd bindings document
> > mfd: dt: ranges, #address-cells and #size-cells as optional properties
> > mfd: dt: Add Aspeed Low Pin Count Controller bindings
> > mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
> > mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
> >
> > .../devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++
> > .../devicetree/bindings/mfd/aspeed-lpc.txt | 137 +++++++++++++++++++++
> > Documentation/devicetree/bindings/mfd/mfd.txt | 12 +-
> > 3 files changed, 165 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
> > create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> >
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 1/4] input: Add support for the tm2 touchkey device driver
From: Javier Martinez Canillas @ 2017-01-03 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483430237-26823-2-git-send-email-jcsing.lee@samsung.com>
Hello Jaechul,
On 01/03/2017 04:57 AM, Jaechul Lee wrote:
> This patch adds the binding description of the tm2 touchkey
> device driver.
>
> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> ---
Patch looks good to me.
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH v4 2/3] soc: zte: pm_domains: Add support for zx296718 board
From: kbuild test robot @ 2017-01-03 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483426577-5470-2-git-send-email-baoyou.xie@linaro.org>
Hi Baoyou,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.10-rc2 next-20161224]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Baoyou-Xie/soc-zte-pm_domains-Prepare-for-supporting-ARMv8-zx2967-family/20170103-181714
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
>> drivers/soc/zte/zx296718_pm_domains.c:7:47: fatal error: dt-bindings/soc/zx2967,pm_domains.h: No such file or directory
#include <dt-bindings/soc/zx2967,pm_domains.h>
^
compilation terminated.
vim +7 drivers/soc/zte/zx296718_pm_domains.c
1 /*
2 * Copyright (C) 2015 ZTE Ltd.
3 *
4 * Author: Baoyou Xie <baoyou.xie@linaro.org>
5 * License terms: GNU General Public License (GPL) version 2
6 */
> 7 #include <dt-bindings/soc/zx2967,pm_domains.h>
8 #include "zx2967_pm_domains.h"
9
10 static u16 zx296718_offsets[REG_ARRAY_SIZE] = {
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [RESEND PATCH 1/2] arm64: change from CONT_PMD_SHIFT to CONT_PTE_SHIFT
From: Catalin Marinas @ 2017-01-03 12:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481725151-20549-2-git-send-email-zhongjiang@huawei.com>
On Wed, Dec 14, 2016 at 10:19:10PM +0800, zhongjiang wrote:
> From: zhong jiang <zhongjiang@huawei.com>
>
> I think that CONT_PTE_SHIFT is more reasonable even if they are some
> value. and the patch is not any functional change.
>
> Signed-off-by: zhong jiang <zhongjiang@huawei.com>
> ---
> arch/arm64/mm/hugetlbpage.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
> index 2e49bd2..0a4c97b 100644
> --- a/arch/arm64/mm/hugetlbpage.c
> +++ b/arch/arm64/mm/hugetlbpage.c
> @@ -323,7 +323,7 @@ static __init int setup_hugepagesz(char *opt)
> static __init int add_default_hugepagesz(void)
> {
> if (size_to_hstate(CONT_PTES * PAGE_SIZE) == NULL)
> - hugetlb_add_hstate(CONT_PMD_SHIFT);
> + hugetlb_add_hstate(CONT_PTE_SHIFT);
> return 0;
> }
> arch_initcall(add_default_hugepagesz);
It looks like I fixed this already when I merged some other hugetlb
patches. See commit 6ed0038d5ecb ("arm64: Fix typo in
add_default_hugepagesz() for 64K pages").
--
Catalin
^ permalink raw reply
* [PATCH 1/2] drivers: psci: annotate timer on stack to silence odebug messages
From: Sudeep Holla @ 2017-01-03 12:32 UTC (permalink / raw)
To: linux-arm-kernel
When DEBUG_OBJECTS config is enabled, we get the below odebug warnings:
ODEBUG: object is on stack, but not annotated
WARNING: CPU: 3 PID: 1304 at kernel/lib/debugobjects.c:300 __debug_object_init+0x1f0/0x458
CPU: 3 PID: 1304 Comm: psci_suspend_te Tainted: G W 4.9.0-06564-gf80f3f199260 #284
task: ffffe9e1b55a1600 task.stack: ffffe9e1b51c0000
PC is at __debug_object_init+0x1f0/0x458
LR is at __debug_object_init+0x1ec/0x458
Call trace:
__debug_object_init+0x1f0/0x458
debug_object_activate+0x150/0x260
mod_timer+0xb4/0x4c0
suspend_test_thread+0x1cc/0x3c0
kthread+0x110/0x140
ret_from_fork+0x10/0x40
This patch annotates the timer on the stack using setup_timer_on_stack
function to remove the above warnings.
Cc: Kevin Brodsky <kevin.brodsky@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
drivers/firmware/psci_checker.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/psci_checker.c b/drivers/firmware/psci_checker.c
index 44bdb78f837b..29d58feaf675 100644
--- a/drivers/firmware/psci_checker.c
+++ b/drivers/firmware/psci_checker.c
@@ -270,8 +270,7 @@ static int suspend_test_thread(void *arg)
struct cpuidle_device *dev;
struct cpuidle_driver *drv;
/* No need for an actual callback, we just want to wake up the CPU. */
- struct timer_list wakeup_timer =
- TIMER_INITIALIZER(dummy_callback, 0, 0);
+ struct timer_list wakeup_timer;
/* Wait for the main thread to give the start signal. */
wait_for_completion(&suspend_threads_started);
@@ -287,6 +286,7 @@ static int suspend_test_thread(void *arg)
pr_info("CPU %d entering suspend cycles, states 1 through %d\n",
cpu, drv->state_count - 1);
+ setup_timer_on_stack(&wakeup_timer, dummy_callback, 0);
for (i = 0; i < NUM_SUSPEND_CYCLE; ++i) {
int index;
/*
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] MAINTAINERS: extend PSCI entry to cover the newly add PSCI checker code
From: Sudeep Holla @ 2017-01-03 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483446768-26973-1-git-send-email-sudeep.holla@arm.com>
This patch extends the file entry for PSCI so that the newly added
PSCI checker module code is also covered.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index cfff2c9e3d94..c7397bdef186 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9842,7 +9842,7 @@ M: Mark Rutland <mark.rutland@arm.com>
M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
L: linux-arm-kernel at lists.infradead.org
S: Maintained
-F: drivers/firmware/psci.c
+F: drivers/firmware/psci*.c
F: include/linux/psci.h
F: include/uapi/linux/psci.h
--
2.7.4
^ permalink raw reply related
* [PATCH v6 6/8] IIO: add STM32 timer trigger driver
From: Benjamin Gaignard @ 2017-01-03 12:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+M3ks6jshX-rEsi7Qfo-65awzWcHsEMVBjm-baYy979V9187Q@mail.gmail.com>
2017-01-03 10:23 GMT+01:00 Benjamin Gaignard <benjamin.gaignard@linaro.org>:
> 2017-01-02 19:22 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
>> On 02/01/17 08:46, Benjamin Gaignard wrote:
>>> 2016-12-30 22:12 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
>>>> On 09/12/16 14:15, Benjamin Gaignard wrote:
>>>>> Timers IPs can be used to generate triggers for other IPs like
>>>>> DAC, ADC or other timers.
>>>>> Each trigger may result of timer internals signals like counter enable,
>>>>> reset or edge, this configuration could be done through "master_mode"
>>>>> device attribute.
>>>>>
>>>>> A timer device could be triggered by other timers, we use the trigger
>>>>> name and is_stm32_iio_timer_trigger() function to distinguish them
>>>>> and configure IP input switch.
>>>>>
>>>>> Timer may also decide on which event (edge, level) they could
>>>>> be activated by a trigger, this configuration is done by writing in
>>>>> "slave_mode" device attribute.
>>>>>
>>>>> Since triggers could also be used by DAC or ADC their names are defined
>>>>> in include/ nux/iio/timer/stm32-timer-trigger.h so those IPs will be able
>>>>> to configure themselves in valid_trigger function
>>>>>
>>>>> Trigger have a "sampling_frequency" attribute which allow to configure
>>>>> timer sampling frequency without using PWM interface
>>>>>
>>>>> version 5:
>>>>> - simplify tables of triggers
>>>>> - only create an IIO device when needed
>>>>>
>>>>> version 4:
>>>>> - get triggers configuration from "reg" in DT
>>>>> - add tables of triggers
>>>>> - sampling frequency is enable/disable when writing in trigger
>>>>> sampling_frequency attribute
>>>>> - no more use of interruptions
>>>>>
>>>>> version 3:
>>>>> - change compatible to "st,stm32-timer-trigger"
>>>>> - fix attributes access right
>>>>> - use string instead of int for master_mode and slave_mode
>>>>> - document device attributes in sysfs-bus-iio-timer-stm32
>>>>>
>>>>> version 2:
>>>>> - keep only one compatible
>>>>> - use st,input-triggers-names and st,output-triggers-names
>>>>> to know which triggers are accepted and/or create by the device
>>>> Firstly, sorry it has taken me so long to get back to this.
>>>>
>>>> I'm still not keen on this use of iio_device elements just to act as
>>>> glue between triggers. I think we need to work out a more light weight
>>>> way to do this. As you are only using them for validation and to provide
>>>> somewhere to hang the control attibutes off, there is nothing stopping us
>>>> moving that over to the iio_trigger instead which would avoid the messy
>>>> duality going on here.
>>>
>>> I have add an iio_device because each hardware can generate multiple
>>> triggers (up to 5: trgo, ch 1...4) and slave_mode attribute will impact all the
>>> triggers of a device. For me it was making sense to centralize that in an
>>> iio_device rather than having an attribute "shared" (from hardware
>>> point of view)
>>> on multiple triggers.
>>> Since master_mode attribute is only used by trgo and not impact ch1...4
>>> triggers I will move it to trigger instead of the iio_device.
>>>
>>> I also wanted to be able to connect triggers on a iio_device as I
>>> could do for an
>>> ADC with a command like 'echo "tim1_trgo" > iio_deviceX/trigger/current_trigger'
>> This is interesting, but with a bit of refactoring I would think it would
>> be possible to share some of that code thus allowing non IIO devices to
>> bind to triggers. Ultimately I want to be able to bind a trigger to
>> a trigger - I appreciate here the topology is more limited than that
>> so some complexity comes in.
>>
>> My gut feeling is that representing that topology explicitly is hard
>> to do in a remotely general way, but lets try it and see.
>> We run into this sort of interdependency issue between different bits of
>> the hardware all the time. Setting a value somewhere effects the configuration
>> elsewhere - often the best plan is to just let that happen and leave it up to
>> userspace to check for changes if it cares.
>
> okay
>
>>> If I change that to parent_trigger attribute it change this behavior
>>> and I will have to
>>> duplicated what is done in iio_trigger_write_current() to find and
>>> validate triggers.
>> I get the reasoning, but we still end up with something represented
>> by an IIO device that isn't providing any channels at all. It's simply
>> using some of the infrastructure. To my mind it is 'something else'
>> and should be represented as such. I have no problem at all with
>> you registering additional elements in /sysfs/bus/iio/ to represent
>> these shared elements - we already have drivers that do that to
>> provide some centralized infrastructure (e.g. the sysfs-trigger)
>
> My hardware block are timers maybe I can add a channel type "IIO_TIMER"
> and declare a channel with info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ)
> so I will be able to write/read sampling frequency on IIO device.
>
If it isn't possible to implement IIO_TIMER I will simply drop device part of
my driver until we find a solution because I would like to upstream at
least what is
need to ADC/DAC.
>> I'm worried about the scope spread we get for an IIO device otherwise.
>> They serve a well defined purpose at the moment, and that isn't what
>> is happening here.
>>
>> So my gut feeling is we are better deliberately not representing the
>> inter dependence and claiming all triggers we are creating are
>> independent. That way we can have a nice generic infrastructure
>> that will work in all cases (be it pushing the sanity checking to
>> userspace).
>>
>> So each trigger has direct access to what controls it. Changing anything
>> can effect other triggers in weird ways.
>>
>> I'm finding it hard to see anything else generalizing sufficiently
>> as we'll always get cases where we can't represent the topology without
>> diving into the complexity of something like the media controller
>> framework.
>>
>> Jonathan
>>>
>>>> I might still be missing something though!
>>>>
>>>> You would only I think need 3 attributes
>>>>
>>>> parrent_trigger
>>>> and something like your master_mode and slave_mode attributes.
>>>>
>>>> The parrent_trigger would need some validation etc, but if we keep it
>>>> within this driver initially that won't be hard to do. Checking the device
>>>> parent matches will do most of it.
>>>>
>>>> Jonathan
>>>>>
>>>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>>> ---
>>>>> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 55 +++
>>>>> drivers/iio/Kconfig | 2 +-
>>>>> drivers/iio/Makefile | 1 +
>>>>> drivers/iio/timer/Kconfig | 13 +
>>>>> drivers/iio/timer/Makefile | 1 +
>>>>> drivers/iio/timer/stm32-timer-trigger.c | 466 +++++++++++++++++++++
>>>>> drivers/iio/trigger/Kconfig | 1 -
>>>>> include/linux/iio/timer/stm32-timer-trigger.h | 62 +++
>>>>> 8 files changed, 599 insertions(+), 2 deletions(-)
>>>>> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>>> create mode 100644 drivers/iio/timer/Kconfig
>>>>> create mode 100644 drivers/iio/timer/Makefile
>>>>> create mode 100644 drivers/iio/timer/stm32-timer-trigger.c
>>>>> create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
>>>>>
>>>>> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>>> new file mode 100644
>>>>> index 0000000..26583dd
>>>>> --- /dev/null
>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>>>>> @@ -0,0 +1,55 @@
>>>>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode_available
>>>>> +KernelVersion: 4.10
>>>>> +Contact: benjamin.gaignard at st.com
>>>>> +Description:
>>>>> + Reading returns the list possible master modes which are:
>>>>> + - "reset" : The UG bit from the TIMx_EGR register is used as trigger output (TRGO).
>>>>> + - "enable" : The Counter Enable signal CNT_EN is used as trigger output.
>>>>> + - "update" : The update event is selected as trigger output.
>>>>> + For instance a master timer can then be used as a prescaler for a slave timer.
>>>>> + - "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set.
>>>>> + - "OC1REF" : OC1REF signal is used as trigger output.
>>>>> + - "OC2REF" : OC2REF signal is used as trigger output.
>>>>> + - "OC3REF" : OC3REF signal is used as trigger output.
>>>>> + - "OC4REF" : OC4REF signal is used as trigger output.
>>>>> +
>>>>> +What: /sys/bus/iio/devices/iio:deviceX/master_mode
>>>>> +KernelVersion: 4.10
>>>>> +Contact: benjamin.gaignard at st.com
>>>>> +Description:
>>>>> + Reading returns the current master modes.
>>>>> + Writing set the master mode
>>>>> +
>>>>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode_available
>>>>> +KernelVersion: 4.10
>>>>> +Contact: benjamin.gaignard at st.com
>>>>> +Description:
>>>>> + Reading returns the list possible slave modes which are:
>>>>> + - "disabled" : The prescaler is clocked directly by the internal clock.
>>>>> + - "encoder_1" : Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
>>>>> + - "encoder_2" : Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
>>>>> + - "encoder_3" : Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
>>>>> + on the level of the other input.
>>>>> + - "reset" : Rising edge of the selected trigger input reinitializes the counter
>>>>> + and generates an update of the registers.
>>>>> + - "gated" : The counter clock is enabled when the trigger input is high.
>>>>> + The counter stops (but is not reset) as soon as the trigger becomes low.
>>>>> + Both start and stop of the counter are controlled.
>>>>> + - "trigger" : The counter starts at a rising edge of the trigger TRGI (but it is not
>>>>> + reset). Only the start of the counter is controlled.
>>>>> + - "external_clock": Rising edges of the selected trigger (TRGI) clock the counter.
>>>>> +
>>>>> +What: /sys/bus/iio/devices/iio:deviceX/slave_mode
>>>>> +KernelVersion: 4.10
>>>>> +Contact: benjamin.gaignard at st.com
>>>>> +Description:
>>>>> + Reading returns the current slave mode.
>>>>> + Writing set the slave mode
>>>>> +
>>>>> +What: /sys/bus/iio/devices/triggerX/sampling_frequency
>>>>> +KernelVersion: 4.10
>>>>> +Contact: benjamin.gaignard at st.com
>>>>> +Description:
>>>>> + Reading returns the current sampling frequency.
>>>>> + Writing an value different of 0 set and start sampling.
>>>>> + Writing 0 stop sampling.
>>>>> diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
>>>>> index 6743b18..2de2a80 100644
>>>>> --- a/drivers/iio/Kconfig
>>>>> +++ b/drivers/iio/Kconfig
>>>>> @@ -90,5 +90,5 @@ source "drivers/iio/potentiometer/Kconfig"
>>>>> source "drivers/iio/pressure/Kconfig"
>>>>> source "drivers/iio/proximity/Kconfig"
>>>>> source "drivers/iio/temperature/Kconfig"
>>>>> -
>>>>> +source "drivers/iio/timer/Kconfig"
>>>>> endif # IIO
>>>>> diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
>>>>> index 87e4c43..b797c08 100644
>>>>> --- a/drivers/iio/Makefile
>>>>> +++ b/drivers/iio/Makefile
>>>>> @@ -32,4 +32,5 @@ obj-y += potentiometer/
>>>>> obj-y += pressure/
>>>>> obj-y += proximity/
>>>>> obj-y += temperature/
>>>>> +obj-y += timer/
>>>>> obj-y += trigger/
>>>>> diff --git a/drivers/iio/timer/Kconfig b/drivers/iio/timer/Kconfig
>>>>> new file mode 100644
>>>>> index 0000000..e3c21f2
>>>>> --- /dev/null
>>>>> +++ b/drivers/iio/timer/Kconfig
>>>>> @@ -0,0 +1,13 @@
>>>>> +#
>>>>> +# Timers drivers
>>>>> +
>>>>> +menu "Timers"
>>>>> +
>>>>> +config IIO_STM32_TIMER_TRIGGER
>>>>> + tristate "STM32 Timer Trigger"
>>>>> + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST
>>>>> + select IIO_TRIGGERED_EVENT
>>>>> + help
>>>>> + Select this option to enable STM32 Timer Trigger
>>>>> +
>>>>> +endmenu
>>>>> diff --git a/drivers/iio/timer/Makefile b/drivers/iio/timer/Makefile
>>>>> new file mode 100644
>>>>> index 0000000..4ad95ec9
>>>>> --- /dev/null
>>>>> +++ b/drivers/iio/timer/Makefile
>>>>> @@ -0,0 +1 @@
>>>>> +obj-$(CONFIG_IIO_STM32_TIMER_TRIGGER) += stm32-timer-trigger.o
>>>>> diff --git a/drivers/iio/timer/stm32-timer-trigger.c b/drivers/iio/timer/stm32-timer-trigger.c
>>>>> new file mode 100644
>>>>> index 0000000..8d16e8f
>>>>> --- /dev/null
>>>>> +++ b/drivers/iio/timer/stm32-timer-trigger.c
>>>>> @@ -0,0 +1,466 @@
>>>>> +/*
>>>>> + * Copyright (C) STMicroelectronics 2016
>>>>> + *
>>>>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>>> + *
>>>>> + * License terms: GNU General Public License (GPL), version 2
>>>>> + */
>>>>> +
>>>>> +#include <linux/iio/iio.h>
>>>>> +#include <linux/iio/sysfs.h>
>>>>> +#include <linux/iio/timer/stm32-timer-trigger.h>
>>>>> +#include <linux/iio/trigger.h>
>>>>> +#include <linux/iio/triggered_event.h>
>>>>> +#include <linux/interrupt.h>
>>>>> +#include <linux/mfd/stm32-timers.h>
>>>>> +#include <linux/module.h>
>>>>> +#include <linux/platform_device.h>
>>>>> +
>>>>> +#define MAX_TRIGGERS 6
>>>>> +#define MAX_VALIDS 5
>>>>> +
>>>>> +/* List the triggers created by each timer */
>>>>> +static const void *triggers_table[][MAX_TRIGGERS] = {
>>>>> + { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
>>>>> + { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
>>>>> + { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
>>>>> + { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
>>>>> + { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
>>>>> + { TIM6_TRGO,},
>>>>> + { TIM7_TRGO,},
>>>>> + { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
>>>>> + { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
>>>>> + { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
>>>>> +};
>>>>> +
>>>>> +/* List the triggers accepted by each timer */
>>>>> +static const void *valids_table[][MAX_VALIDS] = {
>>>>> + { TIM5_TRGO, TIM2_TRGO, TIM4_TRGO, TIM3_TRGO,},
>>>>> + { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
>>>>> + { TIM1_TRGO, TIM8_TRGO, TIM5_TRGO, TIM4_TRGO,},
>>>>> + { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
>>>>> + { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
>>>>> + { }, /* timer 6 */
>>>>> + { }, /* timer 7 */
>>>>> + { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
>>>>> + { TIM2_TRGO, TIM3_TRGO,},
>>>>> + { TIM4_TRGO, TIM5_TRGO,},
>>>>> +};
>>>>> +
>>>>> +struct stm32_timer_trigger {
>>>>> + struct device *dev;
>>>>> + struct regmap *regmap;
>>>>> + struct clk *clk;
>>>>> + u32 max_arr;
>>>>> + const void *triggers;
>>>>> + const void *valids;
>>>>> +};
>>>>> +
>>>>> +static int stm32_timer_start(struct stm32_timer_trigger *priv,
>>>>> + unsigned int frequency)
>>>>> +{
>>>>> + unsigned long long prd, div;
>>>>> + int prescaler = 0;
>>>>> + u32 ccer, cr1;
>>>>> +
>>>>> + /* Period and prescaler values depends of clock rate */
>>>>> + div = (unsigned long long)clk_get_rate(priv->clk);
>>>>> +
>>>>> + do_div(div, frequency);
>>>>> +
>>>>> + prd = div;
>>>>> +
>>>>> + /*
>>>>> + * Increase prescaler value until we get a result that fit
>>>>> + * with auto reload register maximum value.
>>>>> + */
>>>>> + while (div > priv->max_arr) {
>>>>> + prescaler++;
>>>>> + div = prd;
>>>>> + do_div(div, (prescaler + 1));
>>>>> + }
>>>>> + prd = div;
>>>>> +
>>>>> + if (prescaler > MAX_TIM_PSC) {
>>>>> + dev_err(priv->dev, "prescaler exceeds the maximum value\n");
>>>>> + return -EINVAL;
>>>>> + }
>>>>> +
>>>>> + /* Check if nobody else use the timer */
>>>>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>>>>> + if (ccer & TIM_CCER_CCXE)
>>>>> + return -EBUSY;
>>>>> +
>>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>>> + if (!(cr1 & TIM_CR1_CEN))
>>>>> + clk_enable(priv->clk);
>>>>> +
>>>>> + regmap_write(priv->regmap, TIM_PSC, prescaler);
>>>>> + regmap_write(priv->regmap, TIM_ARR, prd - 1);
>>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
>>>>> +
>>>>> + /* Force master mode to update mode */
>>>>> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
>>>>> +
>>>>> + /* Make sure that registers are updated */
>>>>> + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
>>>>> +
>>>>> + /* Enable controller */
>>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static void stm32_timer_stop(struct stm32_timer_trigger *priv)
>>>>> +{
>>>>> + u32 ccer, cr1;
>>>>> +
>>>>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>>>>> + if (ccer & TIM_CCER_CCXE)
>>>>> + return;
>>>>> +
>>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>>> + if (cr1 & TIM_CR1_CEN)
>>>>> + clk_disable(priv->clk);
>>>>> +
>>>>> + /* Stop timer */
>>>>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
>>>>> + regmap_write(priv->regmap, TIM_PSC, 0);
>>>>> + regmap_write(priv->regmap, TIM_ARR, 0);
>>>>> +}
>>>>> +
>>>>> +static ssize_t stm32_tt_store_frequency(struct device *dev,
>>>>> + struct device_attribute *attr,
>>>>> + const char *buf, size_t len)
>>>>> +{
>>>>> + struct iio_trigger *trig = to_iio_trigger(dev);
>>>>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>>>>> + unsigned int freq;
>>>>> + int ret;
>>>>> +
>>>>> + ret = kstrtouint(buf, 10, &freq);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + if (freq == 0) {
>>>>> + stm32_timer_stop(priv);
>>>>> + } else {
>>>>> + ret = stm32_timer_start(priv, freq);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + return len;
>>>>> +}
>>>>> +
>>>>> +static ssize_t stm32_tt_read_frequency(struct device *dev,
>>>>> + struct device_attribute *attr, char *buf)
>>>>> +{
>>>>> + struct iio_trigger *trig = to_iio_trigger(dev);
>>>>> + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
>>>>> + u32 psc, arr, cr1;
>>>>> + unsigned long long freq = 0;
>>>>> +
>>>>> + regmap_read(priv->regmap, TIM_CR1, &cr1);
>>>>> + regmap_read(priv->regmap, TIM_PSC, &psc);
>>>>> + regmap_read(priv->regmap, TIM_ARR, &arr);
>>>>> +
>>>>> + if (psc && arr && (cr1 & TIM_CR1_CEN)) {
>>>>> + freq = (unsigned long long)clk_get_rate(priv->clk);
>>>>> + do_div(freq, psc);
>>>>> + do_div(freq, arr);
>>>>> + }
>>>>> +
>>>>> + return sprintf(buf, "%d\n", (unsigned int)freq);
>>>>> +}
>>>>> +
>>>>> +static IIO_DEV_ATTR_SAMP_FREQ(0660,
>>>>> + stm32_tt_read_frequency,
>>>>> + stm32_tt_store_frequency);
>>>>> +
>>>>> +static struct attribute *stm32_trigger_attrs[] = {
>>>>> + &iio_dev_attr_sampling_frequency.dev_attr.attr,
>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +static const struct attribute_group stm32_trigger_attr_group = {
>>>>> + .attrs = stm32_trigger_attrs,
>>>>> +};
>>>>> +
>>>>> +static const struct attribute_group *stm32_trigger_attr_groups[] = {
>>>>> + &stm32_trigger_attr_group,
>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +static char *master_mode_table[] = {
>>>>> + "reset",
>>>>> + "enable",
>>>>> + "update",
>>>>> + "compare_pulse",
>>>>> + "OC1REF",
>>>>> + "OC2REF",
>>>>> + "OC3REF",
>>>>> + "OC4REF"
>>>>> +};
>>>>> +
>>>>> +static ssize_t stm32_tt_show_master_mode(struct device *dev,
>>>>> + struct device_attribute *attr,
>>>>> + char *buf)
>>>>> +{
>>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>>> + u32 cr2;
>>>>> +
>>>>> + regmap_read(priv->regmap, TIM_CR2, &cr2);
>>>>> + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
>>>>> +
>>>>> + return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
>>>>> +}
>>>>> +
>>>>> +static ssize_t stm32_tt_store_master_mode(struct device *dev,
>>>>> + struct device_attribute *attr,
>>>>> + const char *buf, size_t len)
>>>>> +{
>>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>>> + int i;
>>>>> +
>>>>> + for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
>>>>> + if (!strncmp(master_mode_table[i], buf,
>>>>> + strlen(master_mode_table[i]))) {
>>>>> + regmap_update_bits(priv->regmap, TIM_CR2,
>>>>> + TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
>>>>> + return len;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + return -EINVAL;
>>>>> +}
>>>>> +
>>>>> +static IIO_CONST_ATTR(master_mode_available,
>>>>> + "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
>>>>> +
>>>>> +static IIO_DEVICE_ATTR(master_mode, 0660,
>>>>> + stm32_tt_show_master_mode,
>>>>> + stm32_tt_store_master_mode,
>>>>> + 0);
>>>>> +
>>>>> +static char *slave_mode_table[] = {
>>>>> + "disabled",
>>>>> + "encoder_1",
>>>>> + "encoder_2",
>>>>> + "encoder_3",
>>>>> + "reset",
>>>>> + "gated",
>>>>> + "trigger",
>>>>> + "external_clock",
>>>>> +};
>>>>> +
>>>>> +static ssize_t stm32_tt_show_slave_mode(struct device *dev,
>>>>> + struct device_attribute *attr,
>>>>> + char *buf)
>>>>> +{
>>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>>> + u32 smcr;
>>>>> +
>>>>> + regmap_read(priv->regmap, TIM_SMCR, &smcr);
>>>>> + smcr &= TIM_SMCR_SMS;
>>>>> +
>>>>> + return snprintf(buf, PAGE_SIZE, "%s\n", slave_mode_table[smcr]);
>>>>> +}
>>>>> +
>>>>> +static ssize_t stm32_tt_store_slave_mode(struct device *dev,
>>>>> + struct device_attribute *attr,
>>>>> + const char *buf, size_t len)
>>>>> +{
>>>>> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
>>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>>> + int i;
>>>>> +
>>>>> + for (i = 0; i < ARRAY_SIZE(slave_mode_table); i++) {
>>>>> + if (!strncmp(slave_mode_table[i], buf,
>>>>> + strlen(slave_mode_table[i]))) {
>>>>> + regmap_update_bits(priv->regmap,
>>>>> + TIM_SMCR, TIM_SMCR_SMS, i);
>>>>> + return len;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + return -EINVAL;
>>>>> +}
>>>>> +
>>>>> +static IIO_CONST_ATTR(slave_mode_available,
>>>>> +"disabled encoder_1 encoder_2 encoder_3 reset gated trigger external_clock");
>>>>> +
>>>>> +static IIO_DEVICE_ATTR(slave_mode, 0660,
>>>>> + stm32_tt_show_slave_mode,
>>>>> + stm32_tt_store_slave_mode,
>>>>> + 0);
>>>>> +
>>>>> +static struct attribute *stm32_timer_attrs[] = {
>>>>> + &iio_dev_attr_master_mode.dev_attr.attr,
>>>>> + &iio_const_attr_master_mode_available.dev_attr.attr,
>>>>> + &iio_dev_attr_slave_mode.dev_attr.attr,
>>>>> + &iio_const_attr_slave_mode_available.dev_attr.attr,
>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +static const struct attribute_group stm32_timer_attr_group = {
>>>>> + .attrs = stm32_timer_attrs,
>>>>> +};
>>>>> +
>>>>> +static const struct iio_trigger_ops timer_trigger_ops = {
>>>>> + .owner = THIS_MODULE,
>>>>> +};
>>>>> +
>>>>> +static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
>>>>> +{
>>>>> + int ret;
>>>>> + const char * const *cur = priv->triggers;
>>>>> +
>>>>> + while (cur && *cur) {
>>>>> + struct iio_trigger *trig;
>>>>> +
>>>>> + trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
>>>>> + if (!trig)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + trig->dev.parent = priv->dev->parent;
>>>>> + trig->ops = &timer_trigger_ops;
>>>>> + trig->dev.groups = stm32_trigger_attr_groups;
>>>>> + iio_trigger_set_drvdata(trig, priv);
>>>>> +
>>>>> + ret = devm_iio_trigger_register(priv->dev, trig);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + cur++;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +/**
>>>>> + * is_stm32_timer_trigger
>>>>> + * @trig: trigger to be checked
>>>>> + *
>>>>> + * return true if the trigger is a valid stm32 iio timer trigger
>>>>> + * either return false
>>>>> + */
>>>>> +bool is_stm32_timer_trigger(struct iio_trigger *trig)
>>>>> +{
>>>>> + return (trig->ops == &timer_trigger_ops);
>>>>> +}
>>>>> +EXPORT_SYMBOL(is_stm32_timer_trigger);
>>>>> +
>>>>> +static int stm32_validate_trigger(struct iio_dev *indio_dev,
>>>>> + struct iio_trigger *trig)
>>>>> +{
>>>>> + struct stm32_timer_trigger *priv = iio_priv(indio_dev);
>>>>> + const char * const *cur = priv->valids;
>>>>> + unsigned int i = 0;
>>>>> +
>>>>> + if (!is_stm32_timer_trigger(trig))
>>>>> + return -EINVAL;
>>>>> +
>>>>> + while (cur && *cur) {
>>>>> + if (!strncmp(trig->name, *cur, strlen(trig->name))) {
>>>>> + regmap_update_bits(priv->regmap,
>>>>> + TIM_SMCR, TIM_SMCR_TS,
>>>>> + i << TIM_SMCR_TS_SHIFT);
>>>>> + return 0;
>>>>> + }
>>>>> + cur++;
>>>>> + i++;
>>>>> + }
>>>>> +
>>>>> + return -EINVAL;
>>>>> +}
>>>>> +
>>>>> +static const struct iio_info stm32_trigger_info = {
>>>>> + .driver_module = THIS_MODULE,
>>>>> + .validate_trigger = stm32_validate_trigger,
>>>>> + .attrs = &stm32_timer_attr_group,
>>>>> +};
>>>>> +
>>>>> +static struct stm32_timer_trigger *stm32_setup_iio_device(struct device *dev)
>>>>> +{
>>>>> + struct iio_dev *indio_dev;
>>>>> + int ret;
>>>>> +
>>>>> + indio_dev = devm_iio_device_alloc(dev,
>>>>> + sizeof(struct stm32_timer_trigger));
>>>>> + if (!indio_dev)
>>>>> + return NULL;
>>>>> +
>>>>> + indio_dev->name = dev_name(dev);
>>>>> + indio_dev->dev.parent = dev;
>>>>> + indio_dev->info = &stm32_trigger_info;
>>>>> + indio_dev->modes = INDIO_EVENT_TRIGGERED;
>>>>> + indio_dev->num_channels = 0;
>>>>> + indio_dev->dev.of_node = dev->of_node;
>>>>> +
>>>>> + ret = devm_iio_device_register(dev, indio_dev);
>>>>> + if (ret)
>>>>> + return NULL;
>>>>> +
>>>>> + return iio_priv(indio_dev);
>>>>> +}
>>>>> +
>>>>> +static int stm32_timer_trigger_probe(struct platform_device *pdev)
>>>>> +{
>>>>> + struct device *dev = &pdev->dev;
>>>>> + struct stm32_timer_trigger *priv;
>>>>> + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
>>>>> + unsigned int index;
>>>>> + int ret;
>>>>> +
>>>>> + if (of_property_read_u32(dev->of_node, "reg", &index))
>>>>> + return -EINVAL;
>>>>> +
>>>>> + if (index >= ARRAY_SIZE(triggers_table))
>>>>> + return -EINVAL;
>>>>> +
>>>>> + /* Create an IIO device only if we have triggers to be validated */
>>>>> + if (*valids_table[index])
>>>>> + priv = stm32_setup_iio_device(dev);
>>>>
>>>> I still don't like this. Really feels like we shouldn't be creating an
>>>> iio device with all the bagage that carries just to allow us to do the
>>>> trigger trees. We ought to have a much more light weight solution for this
>>>> functionality - we aren't typically even using the interrupt tree stuff
>>>> that the triggers for devices are all really about.
>>>>
>>>> A simpler approach of allowing each trigger the option of a parent seems like
>>>> it would be cleaner. Could be done entirely within this driver in the first
>>>> instance. Basically it would just look like your master and slave attributes
>>>> but have those under triggerX not iio:deviceX.
>>>>
>>>> We can work out how to make it more generic later - including perhaps the
>>>> option to trigger from triggers outside this driver, using some parallel
>>>> infrastructure to the device triggering.
>>>>
>>>>
>>>>> + else
>>>>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>>>>> +
>>>>> + if (!priv)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + priv->dev = dev;
>>>>> + priv->regmap = ddata->regmap;
>>>>> + priv->clk = ddata->clk;
>>>>> + priv->max_arr = ddata->max_arr;
>>>>> + priv->triggers = triggers_table[index];
>>>>> + priv->valids = valids_table[index];
>>>>> +
>>>>> + ret = stm32_setup_iio_triggers(priv);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + platform_set_drvdata(pdev, priv);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static const struct of_device_id stm32_trig_of_match[] = {
>>>>> + { .compatible = "st,stm32-timer-trigger", },
>>>>> + { /* end node */ },
>>>>> +};
>>>>> +MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
>>>>> +
>>>>> +static struct platform_driver stm32_timer_trigger_driver = {
>>>>> + .probe = stm32_timer_trigger_probe,
>>>>> + .driver = {
>>>>> + .name = "stm32-timer-trigger",
>>>>> + .of_match_table = stm32_trig_of_match,
>>>>> + },
>>>>> +};
>>>>> +module_platform_driver(stm32_timer_trigger_driver);
>>>>> +
>>>>> +MODULE_ALIAS("platform: stm32-timer-trigger");
>>>>> +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
>>>>> +MODULE_LICENSE("GPL v2");
>>>>> diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig
>>>>> index 809b2e7..f2af4fe 100644
>>>>> --- a/drivers/iio/trigger/Kconfig
>>>>> +++ b/drivers/iio/trigger/Kconfig
>>>>> @@ -46,5 +46,4 @@ config IIO_SYSFS_TRIGGER
>>>>>
>>>>> To compile this driver as a module, choose M here: the
>>>>> module will be called iio-trig-sysfs.
>>>>> -
>>>> Clean this up.
>>>
>>> ok
>>>
>>>>> endmenu
>>>>> diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h
>>>>> new file mode 100644
>>>>> index 0000000..55535ae
>>>>> --- /dev/null
>>>>> +++ b/include/linux/iio/timer/stm32-timer-trigger.h
>>>>> @@ -0,0 +1,62 @@
>>>>> +/*
>>>>> + * Copyright (C) STMicroelectronics 2016
>>>>> + *
>>>>> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
>>>>> + *
>>>>> + * License terms: GNU General Public License (GPL), version 2
>>>>> + */
>>>>> +
>>>>> +#ifndef _STM32_TIMER_TRIGGER_H_
>>>>> +#define _STM32_TIMER_TRIGGER_H_
>>>>> +
>>>>> +#define TIM1_TRGO "tim1_trgo"
>>>>> +#define TIM1_CH1 "tim1_ch1"
>>>>> +#define TIM1_CH2 "tim1_ch2"
>>>>> +#define TIM1_CH3 "tim1_ch3"
>>>>> +#define TIM1_CH4 "tim1_ch4"
>>>>> +
>>>>> +#define TIM2_TRGO "tim2_trgo"
>>>>> +#define TIM2_CH1 "tim2_ch1"
>>>>> +#define TIM2_CH2 "tim2_ch2"
>>>>> +#define TIM2_CH3 "tim2_ch3"
>>>>> +#define TIM2_CH4 "tim2_ch4"
>>>>> +
>>>>> +#define TIM3_TRGO "tim3_trgo"
>>>>> +#define TIM3_CH1 "tim3_ch1"
>>>>> +#define TIM3_CH2 "tim3_ch2"
>>>>> +#define TIM3_CH3 "tim3_ch3"
>>>>> +#define TIM3_CH4 "tim3_ch4"
>>>>> +
>>>>> +#define TIM4_TRGO "tim4_trgo"
>>>>> +#define TIM4_CH1 "tim4_ch1"
>>>>> +#define TIM4_CH2 "tim4_ch2"
>>>>> +#define TIM4_CH3 "tim4_ch3"
>>>>> +#define TIM4_CH4 "tim4_ch4"
>>>>> +
>>>>> +#define TIM5_TRGO "tim5_trgo"
>>>>> +#define TIM5_CH1 "tim5_ch1"
>>>>> +#define TIM5_CH2 "tim5_ch2"
>>>>> +#define TIM5_CH3 "tim5_ch3"
>>>>> +#define TIM5_CH4 "tim5_ch4"
>>>>> +
>>>>> +#define TIM6_TRGO "tim6_trgo"
>>>>> +
>>>>> +#define TIM7_TRGO "tim7_trgo"
>>>>> +
>>>>> +#define TIM8_TRGO "tim8_trgo"
>>>>> +#define TIM8_CH1 "tim8_ch1"
>>>>> +#define TIM8_CH2 "tim8_ch2"
>>>>> +#define TIM8_CH3 "tim8_ch3"
>>>>> +#define TIM8_CH4 "tim8_ch4"
>>>>> +
>>>>> +#define TIM9_TRGO "tim9_trgo"
>>>>> +#define TIM9_CH1 "tim9_ch1"
>>>>> +#define TIM9_CH2 "tim9_ch2"
>>>>> +
>>>>> +#define TIM12_TRGO "tim12_trgo"
>>>>> +#define TIM12_CH1 "tim12_ch1"
>>>>> +#define TIM12_CH2 "tim12_ch2"
>>>>> +
>>>>> +bool is_stm32_timer_trigger(struct iio_trigger *trig);
>>>>> +
>>>>> +#endif
>>>>>
>>>>
>>>
>>>
>>>
>>
>
>
>
> --
> Benjamin Gaignard
>
> Graphic Study Group
>
> Linaro.org ? Open source software for ARM SoCs
>
> Follow Linaro: Facebook | Twitter | Blog
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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