* [GIT PULL] Amlogic fixes for v4.10-rc
From: Arnd Bergmann @ 2017-01-04 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7hk2abgzgb.fsf@baylibre.com>
On Tuesday, January 3, 2017 9:35:00 PM CET Kevin Hilman wrote:
> This pull has one real fix, as a couple non-critical ones. The DRM
> DT/defconfig patches are coming now because I didn't expect the new
> driver to make it for the v4.10 merge window, but since it did[1], the
> DT and defconfig should go into the same release.
>
Pulled into fixes, thanks!
Arnd
^ permalink raw reply
* [GIT PULL] DaVinci fixes for v4.10
From: Arnd Bergmann @ 2017-01-04 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104121354.8467-1-nsekhar@ti.com>
On Wednesday, January 4, 2017 5:43:54 PM CET Sekhar Nori wrote:
> This pull request contains fixes for the following issues
>
> 1) Fix two instances of infinite loop occurring in
> clock list for DA850. This fixes kernel hangs in some
> instances and so have been marked for stable kernel.
>
> 2) Fix for sleeping function called from atomic context
> with USB 2.0 clock management code introduced in v4.10
> merge window.
>
>
Pulled into fixes, thanks!
Arnd
^ permalink raw reply
* [PATCH 0/9] ARM: dts: armada388: Introduce Clearfog Base DT
From: Gregory CLEMENT @ 2017-01-04 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO43Q-0007yJ-ON@rmk-PC.armlinux.org.uk>
Hi Russell,
On lun., janv. 02 2017, Russell King <rmk+kernel@armlinux.org.uk> wrote:
> This patch series, based upon the previously submitted fix for the SPI
> flash, reworks the Clearfog DT files to add support for the SolidRun
> Clearfog Base platform.
>
> The conventional model is now known as the "Clearfog Pro" module, which
> has the DSA switch and two PCIe sockets. The base model is a smaller
> board without the DSA switch, replacing it with a second copper gigabit
> port, and only one PCIe socket.
>
> We retain the original DT file (named armada-388-clearfog.dtb) for
> compatibility with existing installations - not only the filename,
> but also the board name exposed in userspace.
All the series applied on mvebu/dt.
I amended the last two patches because the license text was mangled as
spotted by Alexandre Belloni, so I fixed it while applying the patches.
Thanks,
Gregory
>
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/armada-388-clearfog-base.dts | 94 ++++++
> arch/arm/boot/dts/armada-388-clearfog-pro.dts | 55 ++++
> arch/arm/boot/dts/armada-388-clearfog.dts | 364 ++++-----------------
> arch/arm/boot/dts/armada-388-clearfog.dtsi | 310 ++++++++++++++++++
> .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 21 ++
> 6 files changed, 548 insertions(+), 298 deletions(-)
> create mode 100644 arch/arm/boot/dts/armada-388-clearfog-base.dts
> create mode 100644 arch/arm/boot/dts/armada-388-clearfog-pro.dts
> create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dtsi
>
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH v5 2/4] ARM: Define KERNEL_START and KERNEL_END
From: Hartley Sweeten @ 2017-01-04 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104011417.1496-3-f.fainelli@gmail.com>
On Tuesday, January 03, 2017 6:14 PM, Florian Fainelli wrote:
>
> In preparation for adding CONFIG_DEBUG_VIRTUAL support, define a set of
> common constants: KERNEL_START and KERNEL_END which abstract
> CONFIG_XIP_KERNEL vs. !CONFIG_XIP_KERNEL. Update the code where
> relevant.
>
> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/include/asm/memory.h | 7 +++++++
> arch/arm/mm/init.c | 7 ++-----
> arch/arm/mm/mmu.c | 6 +-----
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 76cbd9c674df..bee7511c5098 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -111,6 +111,13 @@
>
> #endif /* !CONFIG_MMU */
>
> +#ifdef CONFIG_XIP_KERNEL
> +#define KERNEL_START _sdata
> +#else
> +#define KERNEL_START _stext
> +#endif
> +#define KERNEL_END _end
> +
> /*
> * We fix the TCM memories max 32 KiB ITCM resp DTCM at these
> * locations
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index 370581aeb871..c87d0d5b65f2 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -230,11 +230,8 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
> void __init arm_memblock_init(const struct machine_desc *mdesc)
> {
> /* Register the kernel text, kernel data and initrd with memblock. */
> -#ifdef CONFIG_XIP_KERNEL
> - memblock_reserve(__pa(_sdata), _end - _sdata);
> -#else
> - memblock_reserve(__pa(_stext), _end - _stext);
> -#endif
> + memblock_reserve(__pa(KERNEL_START), _end - KERNEL_START);
Shouldn't the '_end' above be 'KERNEL_END'?
Hartley
^ permalink raw reply
* [GIT PULL] omap fixes for v4.10-rc cycle
From: Tony Lindgren @ 2017-01-04 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3791843.yGbamM6pzm@wuerfel>
* Arnd Bergmann <arnd@arndb.de> [170104 07:18]:
> On Friday, December 30, 2016 1:10:43 PM CET Tony Lindgren wrote:
> > Fist set of fixes for omaps for v4.10-rc cycle, mostly
> > to deal with various regressions noticed during the merge
> > window and to fix various device tree configurations for
> > boards. Also included is removal of mach-omap2/gpio.c that
> > is now dead code with device tree based booting that should
> > be OK for the early -rc cycle:
> >
> > - A series of fixes to add empty chosen node to fix regressions
> > caused for bootloaders that don't create chosen node as the
> > decompressor needs the chosen node to merge command line and
> > ATAGs into it
> >
> > - Fix missing logicpd-som-lv-37xx-devkit.dtb entry in Makefile
> >
> > - Fix regression for am437x timers
> >
> > - Fix wrong strcat for non-NULL terminated string
> >
> > - A series of changes to fix tps65217 interrupts to not use
> > defines as we don't do that for interrupts
> >
> > - Two patches to fix USB VBUS detection on am57xx-idk and force it
> > to peripheral mode until dwc3 role detection is working
> >
> > - Add missing dra72-evm-tps65917 missing voltage supplies
> > accidentally left out of an earlier patch
> >
> > - Fix n900 eMMC detection when booted on qemu
> >
> > - Remove unwanted pr_err on failed memory allocation for
> > prm_common.c
> >
> > - Remove legacy mach-omap2/gpio.c that now is dead code
> > since we boot mach-omap2 in device tree only mode
> >
> > - Fix am572x-idk pcie1 by adding the missing gpio reset pin
>
> I think I would have preferred to see the gpio.c removal as
> a fixes-non-critical patch for 4.11 instead, but I don't feel
> like making you respin the pull request for that, since I
> really want to get the other fixes merged for -rc3.
Sorry yeah I had that queued for v4.11 but I forgot it and then
the holidays came.. Anyways it's been sitting in Linux next since
late November so should be safe to merge.
> Pulled everything into fixes now.
Thanks,
Tony
^ permalink raw reply
* [PATCH v5 13/17] irqdomain: irq_domain_check_msi_remap
From: Auger Eric @ 2017-01-04 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c9c4c159-60ea-8501-5dc2-17bbb24ddfab@arm.com>
Hi Marc,
On 04/01/2017 16:27, Marc Zyngier wrote:
> On 04/01/17 14:11, Auger Eric wrote:
>> Hi Marc,
>>
>> On 04/01/2017 14:46, Marc Zyngier wrote:
>>> Hi Eric,
>>>
>>> On 04/01/17 13:32, Eric Auger wrote:
>>>> This new function checks whether all platform and PCI
>>>> MSI domains implement IRQ remapping. This is useful to
>>>> understand whether VFIO passthrough is safe with respect
>>>> to interrupts.
>>>>
>>>> On ARM typically an MSI controller can sit downstream
>>>> to the IOMMU without preventing VFIO passthrough.
>>>> As such any assigned device can write into the MSI doorbell.
>>>> In case the MSI controller implements IRQ remapping, assigned
>>>> devices will not be able to trigger interrupts towards the
>>>> host. On the contrary, the assignment must be emphasized as
>>>> unsafe with respect to interrupts.
>>>>
>>>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>>>
>>>> ---
>>>>
>>>> v4 -> v5:
>>>> - Handle DOMAIN_BUS_FSL_MC_MSI domains
>>>> - Check parents
>>>> ---
>>>> include/linux/irqdomain.h | 1 +
>>>> kernel/irq/irqdomain.c | 41 +++++++++++++++++++++++++++++++++++++++++
>>>> 2 files changed, 42 insertions(+)
>>>>
>>>> diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
>>>> index ab017b2..281a40f 100644
>>>> --- a/include/linux/irqdomain.h
>>>> +++ b/include/linux/irqdomain.h
>>>> @@ -219,6 +219,7 @@ struct irq_domain *irq_domain_add_legacy(struct device_node *of_node,
>>>> void *host_data);
>>>> extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec,
>>>> enum irq_domain_bus_token bus_token);
>>>> +extern bool irq_domain_check_msi_remap(void);
>>>> extern void irq_set_default_host(struct irq_domain *host);
>>>> extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs,
>>>> irq_hw_number_t hwirq, int node,
>>>> diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
>>>> index 8c0a0ae..700caea 100644
>>>> --- a/kernel/irq/irqdomain.c
>>>> +++ b/kernel/irq/irqdomain.c
>>>> @@ -278,6 +278,47 @@ struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec,
>>>> EXPORT_SYMBOL_GPL(irq_find_matching_fwspec);
>>>>
>>>> /**
>>>> + * irq_domain_is_msi_remap - Check if @domain or any parent
>>>> + * has MSI remapping support
>>>> + * @domain: domain pointer
>>>> + */
>>>> +static bool irq_domain_is_msi_remap(struct irq_domain *domain)
>>>> +{
>>>> + struct irq_domain *h = domain;
>>>> +
>>>> + for (; h; h = h->parent) {
>>>> + if (h->flags & IRQ_DOMAIN_FLAG_MSI_REMAP)
>>>> + return true;
>>>> + }
>>>> + return false;
>>>> +}
>>>> +
>>>> +/**
>>>> + * irq_domain_check_msi_remap() - Checks whether all MSI
>>>> + * irq domains implement IRQ remapping
>>>> + */
>>>> +bool irq_domain_check_msi_remap(void)
>>>> +{
>>>> + struct irq_domain *h;
>>>> + bool ret = true;
>>>> +
>>>> + mutex_lock(&irq_domain_mutex);
>>>> + list_for_each_entry(h, &irq_domain_list, link) {
>>>> + if (((h->bus_token & DOMAIN_BUS_PCI_MSI) ||
>>>> + (h->bus_token & DOMAIN_BUS_PLATFORM_MSI) ||
>>>> + (h->bus_token & DOMAIN_BUS_FSL_MC_MSI)) &&
>>>> + !irq_domain_is_msi_remap(h)) {
>>>
>>> (h->bus_token & DOMAIN_BUS_PCI_MSI) and co looks quite wrong. bus_token
>>> is not a bitmap, and DOMAIN_BUS_* not a single bit value (see enum
>>> irq_domain_bus_token). Surely this should read
>>> (h->bus_token == DOMAIN_BUS_PCI_MSI).
>> Oh I did not notice that. Thanks.
>>
>> Any other comments on the irqdomain side? Do you think the current
>> approach consisting in looking at those bus tokens and their parents
>> looks good?
>
> To be completely honest, I don't like it much, as having to enumerate
> all the bus types can come up with could become quite a burden in the
> long run. I'd rather be able to identify MSI capable domains by
> construction. I came up with the following approach (fully untested):
>
> diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
> index 281a40f..7779796 100644
> --- a/include/linux/irqdomain.h
> +++ b/include/linux/irqdomain.h
> @@ -183,8 +183,11 @@ enum {
> /* Irq domain is an IPI domain with single virq */
> IRQ_DOMAIN_FLAG_IPI_SINGLE = (1 << 3),
>
> + /* Irq domain implements MSIs */
> + IRQ_DOMAIN_FLAG_MSI = (1 << 4),
> +
> /* Irq domain is MSI remapping capable */
> - IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 4),
> + IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 5),
>
> /*
> * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved
> @@ -450,6 +453,11 @@ static inline bool irq_domain_is_ipi_single(struct irq_domain *domain)
> {
> return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE;
> }
> +
> +static inline bool irq_domain_is_msi(struct irq_domain *domain)
> +{
> + return domain->flags & IRQ_DOMAIN_FLAG_MSI;
> +}
> #else /* CONFIG_IRQ_DOMAIN_HIERARCHY */
> static inline void irq_domain_activate_irq(struct irq_data *data) { }
> static inline void irq_domain_deactivate_irq(struct irq_data *data) { }
> @@ -481,6 +489,11 @@ static inline bool irq_domain_is_ipi_single(struct irq_domain *domain)
> {
> return false;
> }
> +
> +static inline bool irq_domain_is_msi(struct irq_domain *domain)
> +{
> + return false;
> +}
> #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
>
> #else /* CONFIG_IRQ_DOMAIN */
> diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
> index 700caea..33b6921 100644
> --- a/kernel/irq/irqdomain.c
> +++ b/kernel/irq/irqdomain.c
> @@ -304,10 +304,7 @@ bool irq_domain_check_msi_remap(void)
>
> mutex_lock(&irq_domain_mutex);
> list_for_each_entry(h, &irq_domain_list, link) {
> - if (((h->bus_token & DOMAIN_BUS_PCI_MSI) ||
> - (h->bus_token & DOMAIN_BUS_PLATFORM_MSI) ||
> - (h->bus_token & DOMAIN_BUS_FSL_MC_MSI)) &&
> - !irq_domain_is_msi_remap(h)) {
> + if (irq_domain_is_msi(h) && !irq_domain_is_msi_remap(h)) {
> ret = false;
> goto out;
> }
> diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c
> index ee23006..b637263 100644
> --- a/kernel/irq/msi.c
> +++ b/kernel/irq/msi.c
> @@ -270,7 +270,7 @@ struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
> if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
> msi_domain_update_chip_ops(info);
>
> - return irq_domain_create_hierarchy(parent, 0, 0, fwnode,
> + return irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0, fwnode,
> &msi_domain_ops, info);
> }
>
>
>
> Thoughts?
No objection from my side. I will respin and test.
Thanks
Eric
>
> M.
>
^ permalink raw reply
* imx: RS-485 problems during TX, maybe DMA related
From: Clemens Gruber @ 2017-01-04 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
I observed odd behavior of the current tty/serial/imx.c driver in RS-485
mode.
RX works fine, but TX does not: When sending data, it arrives multiple
times and with data from previous transmissions at the end, after a
delay.
# My setup
Hardware:
i.MX6Q board with UARTn_RX_DATA, _TX_DATA and _CTS_B connected to a
RS-485 half-duplex transceiver (Exar SP3082E), pins RXD, TXD and DE
respectively. (DE is active-high, _CTS_B is inverted on the board)
I am using an external USB-to-RS-485 converter connected to my PC to
conduct the tests.
Firmware:
I tried both the original ROM SDMA scripts and also the RAM scripts from
Freescale (placed in firmware/imx), but there was no difference, except
for a DMA transaction error message going away (appeared when writing too
much data too fast into a device configured with too low baud rate).
So I switched back to the pure mainline 4.9 kernel with SDMA using the
scripts from ROM.
Software:
Mainline Linux 4.9 with serial_rs485 flags: rs485 (SER_RS485_ENABLED),
-rs485rtsonsend (~SER_RS485_RTS_ON_SEND), rs485rtsaftersend and
rs485rxduringtx. I only enabled rs485rxduringtx, because otherwise it
would not work at all. But I am still unsure why it is needed for
half-duplex RS-485.
# The tests
1) On the board: echo A > /dev/ttymxc4
2) On my PC: A \n A \n appears immediately
(about 4s delay)
A \n
(about 4s delay)
A \n
Kernel log on the board:
[ 29.059983] imx-uart 21f4000.serial: TX: prepare to send 2 bytes by DMA.
[ 29.067166] imx-uart 21f4000.serial: we finish the TX DMA.
[ 29.073057] imx-uart 21f4000.serial: TX: prepare to send 4094 bytes by DMA.
[ 33.359405] imx-uart 21f4000.serial: we finish the TX DMA.
[ 33.365173] imx-uart 21f4000.serial: TX: prepare to send 4072 bytes by DMA.
[ 37.603551] imx-uart 21f4000.serial: we finish the TX DMA.
3) On the board: echo B > /dev/ttymxc4
4) On my PC: B \n B \n appears immediately
(about 4s delay)
A \n B \n
(about 4s delay)
A \n B \n
Kernel log:
[ 66.000296] imx-uart 21f4000.serial: TX: prepare to send 2 bytes by DMA.
[ 66.007110] imx-uart 21f4000.serial: we finish the TX DMA.
[ 66.012841] imx-uart 21f4000.serial: TX: prepare to send 4094 bytes by DMA.
[ 70.297051] imx-uart 21f4000.serial: we finish the TX DMA.
[ 70.302798] imx-uart 21f4000.serial: TX: prepare to send 4072 bytes by DMA.
[ 74.539094] imx-uart 21f4000.serial: we finish the TX DMA.
And so on..
( If I continue with a echo C > /dev/ttymxc4, the last characters are
A \n B \n C )
--
To illustrate the behavior, I recorded the signals on the transceiver
pins with a logic analyzer:
https://pqgruber.com/rs485_results.png
I triggered only on the raising and on the falling edge of DE, so I only
captured the first and the last characters for the first two tests and
not all three events per test.
I also enabled the DMA debug options in the kernel if that is helpful,
here is the full log during the two tests:
https://gist.github.com/clemensg/1ac5ee8a8ea32acc9145c5aa8407aea5
--
Do you have an idea, what's wrong here?
Also: If you are using RS-485 with the imx driver on a recent kernel,
please let me know if it is working for you and if you can reproduce the
behavior.
Thanks,
Clemens
--
PS:
Because I assumed that the error has something to do with DMA, I
commented out the call to imx_uart_dma_init.
Then, transmitting and receiving data over RS-485 works! Verified with
the logic analyzer and the RS-485-to-USB adapter.
However, if trying to send large amounts of data in a short time,
sometimes I get an "Unhandled fault: imprecise external abort (0x1406)".
But the back trace is not very helpful and probably not related
(it is different every time), the last time I tried, the PC was at
_raw_spin_unlock_irqrestore, called from hrtimer_start_range_ns.
^ permalink raw reply
* [PATCH] mailbox: sti: Fix mbox-names copy and paste error
From: Lee Jones @ 2017-01-04 16:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104145732.7yiqbi7rf7m6lem4@rob-hp-laptop>
On Wed, 04 Jan 2017, Rob Herring wrote:
> On Wed, Jan 04, 2017 at 12:05:27PM +0000, Lee Jones wrote:
> > Due to an over-sight, mbox-names has become mbox-name in some instances.
> >
> > Let's put it right.
> >
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > Documentation/devicetree/bindings/mailbox/sti-mailbox.txt | 4 ++--
> > arch/arm/boot/dts/stih407-family.dtsi | 8 ++++----
> > drivers/mailbox/mailbox-sti.c | 2 +-
> > 3 files changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > index 351f612..648d176 100644
> > --- a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > +++ b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > @@ -9,7 +9,7 @@ Controller
> > Required properties:
> > - compatible : Should be "st,stih407-mailbox"
> > - reg : Offset and length of the device's register set
> > -- mbox-name : Name of the mailbox
> > +- mbox-names : Name of the mailbox
>
> It's worse than this. mbox-names is for the mailbox client side.
Ah yes, of course. False alarm.
Let's just leave it as it is. ;)
I'll reply to the reporter directly.
> This should just be dropped. Plus, *-names is pointless when there
> is only 1 element.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* mbox-name vs. mbox-names (was: Re: [PATCH v4 1/5] mailbox: dt: Supply bindings for ST's Mailbox IP)
From: Lee Jones @ 2017-01-04 16:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024084107.GD14477@dell>
On Mon, 24 Oct 2016, Lee Jones wrote:
> On Fri, 21 Oct 2016, Geert Uytterhoeven wrote:
>
> > On Fri, Oct 16, 2015 at 9:21 AM, Lee Jones <lee.jones@linaro.org> wrote:
> > > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > > ---
> > > .../devicetree/bindings/mailbox/sti-mailbox.txt | 51 ++++++++++++++++++++++
> > > 1 file changed, 51 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > > new file mode 100644
> > > index 0000000..b61eec9
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > > @@ -0,0 +1,51 @@
> > > +ST Microelectronics Mailbox Driver
> > > +
> > > +Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages
> > > +are passed between Application and Remote processors using shared memory.
> > > +
> > > +Controller
> > > +----------
> > > +
> > > +Required properties:
> > > +- compatible : Should be "st,stih407-mailbox"
> > > +- reg : Offset and length of the device's register set
> > > +- mbox-name : Name of the mailbox
> >
> > All other mailbox drivers use "mbox-names". Oops, it's in v4.9-rc1...
> >
> > Can we still fix that?
>
> So long as all the fixes; changes to the driver and DT are merged in a
> single kernel release, we can change it.
Scrap that, change of plan. Actually current code is correct.
mbox-name does not have the same functionality as mbox-names.
mbox-names is a client-side property used to request channels, where
as mbox-name is used to provide a better user-readable name other than
mailbox{0..x}.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH] crypto: arm64/aes - add scalar implementation
From: Ard Biesheuvel @ 2017-01-04 16:19 UTC (permalink / raw)
To: linux-arm-kernel
This adds a scalar implementation of AES, based on the precomputed tables
that are exposed by the generic AES code. Since rotates are cheap on arm64,
this implementation only uses the 4 core tables (of 1 KB each), and avoids
the prerotated ones, reducing the D-cache footprint by 75%.
On Cortex-A57, this code manages 13.0 cycles per byte, which is ~34% faster
than the generic C code. (Note that this is still >13x slower than the code
that uses the optional ARMv8 Crypto Extensions, which manages <1 cycles per
byte.)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Raw performance data after the patch, which was generated on a 2 GHz
Cortex-A57 (AMD Seattle B1).
arch/arm64/crypto/Kconfig | 4 +
arch/arm64/crypto/Makefile | 3 +
arch/arm64/crypto/aes-cipher-core.S | 126 ++++++++++++++++++++
arch/arm64/crypto/aes-cipher-glue.c | 69 +++++++++++
4 files changed, 202 insertions(+)
diff --git a/arch/arm64/crypto/Kconfig b/arch/arm64/crypto/Kconfig
index 0bf0f531f539..0826f8e599a6 100644
--- a/arch/arm64/crypto/Kconfig
+++ b/arch/arm64/crypto/Kconfig
@@ -41,6 +41,10 @@ config CRYPTO_CRC32_ARM64_CE
depends on KERNEL_MODE_NEON && CRC32
select CRYPTO_HASH
+config CRYPTO_AES_ARM64
+ tristate "AES core cipher using scalar instructions"
+ select CRYPTO_AES
+
config CRYPTO_AES_ARM64_CE
tristate "AES core cipher using ARMv8 Crypto Extensions"
depends on ARM64 && KERNEL_MODE_NEON
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index 9d2826c5fccf..a893507629eb 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -44,6 +44,9 @@ sha512-arm64-y := sha512-glue.o sha512-core.o
obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha20-neon.o
chacha20-neon-y := chacha20-neon-core.o chacha20-neon-glue.o
+obj-$(CONFIG_CRYPTO_AES_ARM64) += aes-arm64.o
+aes-arm64-y := aes-cipher-core.o aes-cipher-glue.o
+
AFLAGS_aes-ce.o := -DINTERLEAVE=4
AFLAGS_aes-neon.o := -DINTERLEAVE=4
diff --git a/arch/arm64/crypto/aes-cipher-core.S b/arch/arm64/crypto/aes-cipher-core.S
new file mode 100644
index 000000000000..22d1bc46feba
--- /dev/null
+++ b/arch/arm64/crypto/aes-cipher-core.S
@@ -0,0 +1,126 @@
+/*
+ * Scalar AES core transform
+ *
+ * Copyright (C) 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ .text
+ .align 5
+
+ rk .req x0
+ out .req x1
+ in .req x2
+ rounds .req x3
+ tt .req x4
+ lt .req x2
+
+ .macro __hround, out0, out1, in0, in1, in2, in3, t0, t1, enc
+ ldp \out0, \out1, [rk], #8
+
+ ubfx w13, \in0, #0, #8
+ ubfx w14, \in1, #8, #8
+ ldr w13, [tt, w13, uxtw #2]
+ ldr w14, [tt, w14, uxtw #2]
+
+ ubfx w15, \in2, #16, #8
+ ubfx w16, \in3, #24, #8
+ ldr w15, [tt, w15, uxtw #2]
+ ldr w16, [tt, w16, uxtw #2]
+
+ .if \enc
+ ubfx w17, \in1, #0, #8
+ ubfx w18, \in2, #8, #8
+ .else
+ ubfx w17, \in3, #0, #8
+ ubfx w18, \in0, #8, #8
+ .endif
+ ldr w17, [tt, w17, uxtw #2]
+ ldr w18, [tt, w18, uxtw #2]
+
+ .if \enc
+ ubfx \t0, \in3, #16, #8
+ ubfx \t1, \in0, #24, #8
+ .else
+ ubfx \t0, \in1, #16, #8
+ ubfx \t1, \in2, #24, #8
+ .endif
+ ldr \t0, [tt, \t0, uxtw #2]
+ ldr \t1, [tt, \t1, uxtw #2]
+
+ eor \out0, \out0, w13
+ eor \out1, \out1, w17
+ eor \out0, \out0, w14, ror #24
+ eor \out1, \out1, w18, ror #24
+ eor \out0, \out0, w15, ror #16
+ eor \out1, \out1, \t0, ror #16
+ eor \out0, \out0, w16, ror #8
+ eor \out1, \out1, \t1, ror #8
+ .endm
+
+ .macro fround, out0, out1, out2, out3, in0, in1, in2, in3
+ __hround \out0, \out1, \in0, \in1, \in2, \in3, \out2, \out3, 1
+ __hround \out2, \out3, \in2, \in3, \in0, \in1, \in1, \in2, 1
+ .endm
+
+ .macro iround, out0, out1, out2, out3, in0, in1, in2, in3
+ __hround \out0, \out1, \in0, \in3, \in2, \in1, \out2, \out3, 0
+ __hround \out2, \out3, \in2, \in1, \in0, \in3, \in1, \in0, 0
+ .endm
+
+ .macro do_crypt, round, ttab, ltab
+ ldp w5, w6, [in]
+ ldp w7, w8, [in, #8]
+ ldp w9, w10, [rk], #16
+ ldp w11, w12, [rk, #-8]
+
+CPU_BE( rev w5, w5 )
+CPU_BE( rev w6, w6 )
+CPU_BE( rev w7, w7 )
+CPU_BE( rev w8, w8 )
+
+ eor w5, w5, w9
+ eor w6, w6, w10
+ eor w7, w7, w11
+ eor w8, w8, w12
+
+ ldr tt, =\ttab
+ ldr lt, =\ltab
+
+ tbnz rounds, #1, 1f
+
+0: \round w9, w10, w11, w12, w5, w6, w7, w8
+ \round w5, w6, w7, w8, w9, w10, w11, w12
+
+1: subs rounds, rounds, #4
+ \round w9, w10, w11, w12, w5, w6, w7, w8
+ csel tt, tt, lt, hi
+ \round w5, w6, w7, w8, w9, w10, w11, w12
+ b.hi 0b
+
+CPU_BE( rev w5, w5 )
+CPU_BE( rev w6, w6 )
+CPU_BE( rev w7, w7 )
+CPU_BE( rev w8, w8 )
+
+ stp w5, w6, [out]
+ stp w7, w8, [out, #8]
+ ret
+
+ .align 4
+ .ltorg
+ .endm
+
+ENTRY(__aes_arm64_encrypt)
+ do_crypt fround, crypto_ft_tab, crypto_fl_tab
+ENDPROC(__aes_arm64_encrypt)
+
+ENTRY(__aes_arm64_decrypt)
+ do_crypt iround, crypto_it_tab, crypto_il_tab
+ENDPROC(__aes_arm64_decrypt)
diff --git a/arch/arm64/crypto/aes-cipher-glue.c b/arch/arm64/crypto/aes-cipher-glue.c
new file mode 100644
index 000000000000..7288e7cbebff
--- /dev/null
+++ b/arch/arm64/crypto/aes-cipher-glue.c
@@ -0,0 +1,69 @@
+/*
+ * Scalar AES core transform
+ *
+ * Copyright (C) 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <crypto/aes.h>
+#include <linux/crypto.h>
+#include <linux/module.h>
+
+asmlinkage void __aes_arm64_encrypt(u32 *rk, u8 *out, const u8 *in, int rounds);
+EXPORT_SYMBOL(__aes_arm64_encrypt);
+
+asmlinkage void __aes_arm64_decrypt(u32 *rk, u8 *out, const u8 *in, int rounds);
+EXPORT_SYMBOL(__aes_arm64_decrypt);
+
+static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ int rounds = 6 + ctx->key_length / 4;
+
+ __aes_arm64_encrypt(ctx->key_enc, out, in, rounds);
+}
+
+static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ int rounds = 6 + ctx->key_length / 4;
+
+ __aes_arm64_decrypt(ctx->key_dec, out, in, rounds);
+}
+
+static struct crypto_alg aes_alg = {
+ .cra_name = "aes",
+ .cra_driver_name = "aes-arm64",
+ .cra_priority = 200,
+ .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct crypto_aes_ctx),
+ .cra_module = THIS_MODULE,
+
+ .cra_cipher.cia_min_keysize = AES_MIN_KEY_SIZE,
+ .cra_cipher.cia_max_keysize = AES_MAX_KEY_SIZE,
+ .cra_cipher.cia_setkey = crypto_aes_set_key,
+ .cra_cipher.cia_encrypt = aes_encrypt,
+ .cra_cipher.cia_decrypt = aes_decrypt
+};
+
+static int __init aes_init(void)
+{
+ return crypto_register_alg(&aes_alg);
+}
+
+static void __exit aes_fini(void)
+{
+ crypto_unregister_alg(&aes_alg);
+}
+
+module_init(aes_init);
+module_exit(aes_fini);
+
+MODULE_DESCRIPTION("Scalar AES cipher for arm64");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("aes");
--
2.7.4
testing speed of async ecb(aes) (ecb(aes-generic)) encryption
test 0 (128 bit key, 16 byte blocks): 4594689 operations in 1 seconds (73515024 bytes)
test 1 (128 bit key, 64 byte blocks): 1585137 operations in 1 seconds (101448768 bytes)
test 2 (128 bit key, 256 byte blocks): 435173 operations in 1 seconds (111404288 bytes)
test 3 (128 bit key, 1024 byte blocks): 111505 operations in 1 seconds (114181120 bytes)
test 4 (128 bit key, 8192 byte blocks): 14093 operations in 1 seconds (115449856 bytes)
test 5 (192 bit key, 16 byte blocks): 4078345 operations in 1 seconds (65253520 bytes)
test 6 (192 bit key, 64 byte blocks): 1349425 operations in 1 seconds (86363200 bytes)
test 7 (192 bit key, 256 byte blocks): 365631 operations in 1 seconds (93601536 bytes)
test 8 (192 bit key, 1024 byte blocks): 93362 operations in 1 seconds (95602688 bytes)
test 9 (192 bit key, 8192 byte blocks): 11729 operations in 1 seconds (96083968 bytes)
test 10 (256 bit key, 16 byte blocks): 3692945 operations in 1 seconds (59087120 bytes)
test 11 (256 bit key, 64 byte blocks): 1182522 operations in 1 seconds (75681408 bytes)
test 12 (256 bit key, 256 byte blocks): 317285 operations in 1 seconds (81224960 bytes)
test 13 (256 bit key, 1024 byte blocks): 80459 operations in 1 seconds (82390016 bytes)
test 14 (256 bit key, 8192 byte blocks): 10138 operations in 1 seconds (83050496 bytes)
testing speed of async ecb(aes) (ecb(aes-arm64)) encryption
test 0 (128 bit key, 16 byte blocks): 5455304 operations in 1 seconds (87284864 bytes)
test 1 (128 bit key, 64 byte blocks): 2000321 operations in 1 seconds (128020544 bytes)
test 2 (128 bit key, 256 byte blocks): 574174 operations in 1 seconds (146988544 bytes)
test 3 (128 bit key, 1024 byte blocks): 148497 operations in 1 seconds (152060928 bytes)
test 4 (128 bit key, 8192 byte blocks): 18836 operations in 1 seconds (154304512 bytes)
test 5 (192 bit key, 16 byte blocks): 4962478 operations in 1 seconds (79399648 bytes)
test 6 (192 bit key, 64 byte blocks): 1740157 operations in 1 seconds (111370048 bytes)
test 7 (192 bit key, 256 byte blocks): 490443 operations in 1 seconds (125553408 bytes)
test 8 (192 bit key, 1024 byte blocks): 126165 operations in 1 seconds (129192960 bytes)
test 9 (192 bit key, 8192 byte blocks): 15897 operations in 1 seconds (130228224 bytes)
test 10 (256 bit key, 16 byte blocks): 4527784 operations in 1 seconds (72444544 bytes)
test 11 (256 bit key, 64 byte blocks): 1527235 operations in 1 seconds (97743040 bytes)
test 12 (256 bit key, 256 byte blocks): 425302 operations in 1 seconds (108877312 bytes)
test 13 (256 bit key, 1024 byte blocks): 109013 operations in 1 seconds (111629312 bytes)
test 14 (256 bit key, 8192 byte blocks): 13778 operations in 1 seconds (112869376 bytes)
^ permalink raw reply related
* [PATCH 1/5] ARM: dts: armada388-clearfog: add phy reset gpio-hog
From: Gregory CLEMENT @ 2017-01-04 16:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO4Vz-00005t-8n@rmk-PC.armlinux.org.uk>
Hi Russell,
On lun., janv. 02 2017, Russell King <rmk+kernel@armlinux.org.uk> wrote:
It would be nice to have some word here about this patch. Especially why
we need it now. I guess it is for being less dependent on the
initialization done by the bootloader but maybe you have other reasons.
Thanks,
Gregory
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> ---
> arch/arm/boot/dts/armada-388-clearfog-base.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts
> index f86e1876fb38..da788ea40717 100644
> --- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
> +++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
> @@ -74,7 +74,17 @@
> phy = <&phy1>;
> };
>
> +&gpio0 {
> + phy1_reset {
> + gpio-hog;
> + gpios = <19 GPIO_ACTIVE_LOW>;
> + output-low;
> + line-name = "phy1-reset";
> + };
> +};
> +
> &mdio {
> + pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>;
> phy1: ethernet-phy at 1 {
> /*
> * Annoyingly, the marvell phy driver configures the LED
> @@ -87,6 +97,11 @@
> };
>
> &pinctrl {
> + /* phy1 reset */
> + clearfog_phy_pins: clearfog-phy-pins {
> + marvell,pins = "mpp19";
> + marvell,function = "gpio";
> + };
> rear_button_pins: rear-button-pins {
> marvell,pins = "mpp44";
> marvell,function = "gpio";
> --
> 2.7.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 0/5] ARM: dts: armada388: rework clearfog's .dtsi references
From: Gregory CLEMENT @ 2017-01-04 16:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cO4UH-0008SR-GW@rmk-PC.armlinux.org.uk>
Hi Russell,
On lun., janv. 02 2017, Russell King <rmk+kernel@armlinux.org.uk> wrote:
> This patch series, based upon the previous series adding Clearfog Base
> support, reworks the clearfog .dtsi file to reference nodes by label
> rather than by path.
>
> Not everything is moved - just those which had labels at the time the
> patches were created.
All the series is applied on mvebu/dt, however I would like to have a
commit log for the first patch before pushing it to arm-soc.
Thanks,
Gregory
>
> arch/arm/boot/dts/armada-388-clearfog-base.dts | 15 +
> arch/arm/boot/dts/armada-388-clearfog.dtsi | 353 ++++++++++-----------
> .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 113 ++++---
> 3 files changed, 245 insertions(+), 236 deletions(-)
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/5] ARM: wire up HWCAP2 feature bits to the CPU modalias
From: Ard Biesheuvel @ 2017-01-04 16:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102234013.GK14217@n2100.armlinux.org.uk>
On 2 January 2017 at 23:40, Russell King - ARM Linux
<linux@armlinux.org.uk> wrote:
> On Mon, Jan 02, 2017 at 09:06:04PM +0000, Ard Biesheuvel wrote:
>> On 31 October 2016 at 16:13, Russell King - ARM Linux
>> <linux@armlinux.org.uk> wrote:
>> > On Sat, Oct 29, 2016 at 11:08:36AM +0100, Ard Biesheuvel wrote:
>> >> On 18 October 2016 at 11:52, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>> >> > Wire up the generic support for exposing CPU feature bits via the
>> >> > modalias in /sys/device/system/cpu. This allows udev to automatically
>> >> > load modules for things like crypto algorithms that are implemented
>> >> > using optional instructions.
>> >> >
>> >> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> > ---
>> >> > arch/arm/Kconfig | 1 +
>> >> > arch/arm/include/asm/cpufeature.h | 32 ++++++++++++++++++++
>> >> > 2 files changed, 33 insertions(+)
>> >> >
>> >>
>> >> Russell,
>> >>
>> >> do you have any concerns regarding this patch? If not, I will drop it
>> >> into the patch system.
>> >
>> > It's still something I need to look at... I've been offline last week,
>> > and sort-of offline the previous week, so I'm catching up.
>> >
>>
>> Hi Russell,
>>
>> Any thoughts yet?
>
> None, and the patch is well buried now that it'll take me a while to
> find... back in mid-October? Yea, I'll have to drop everything and
> go digging through my mailboxes to find it... and I'm just catching
> up (again) after a week and a bit's time offline - yep, it's wonderful
> timing. Sorry, no time to look at it right now, you're not the only
> one wanting my attention at the moment.
>
No worries. It is not exactly urgent, but it is a useful enhancement
nonetheless.
> Please try again in about a week's time - don't leave it a few months,
> and please include the patch.
>
OK
^ permalink raw reply
* [PATCH v6 11/14] msi: platform: make platform_msi_create_device_domain() ACPI aware
From: Lorenzo Pieralisi @ 2017-01-04 16:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483363905-2806-12-git-send-email-hanjun.guo@linaro.org>
On Mon, Jan 02, 2017 at 09:31:42PM +0800, Hanjun Guo wrote:
> With the platform msi domain created for ITS, irqchip such as
> mbi-gen connecting ITS, which needs ctreate its own irqdomain.
This patch touches generic platform-msi code, there is nothing ITS
and mbi-gen specific that has to be known here.
> Fortunately with the platform msi support upstreamed by Marc,
> we just need to add minor code to make it run properly.
Do you really think that anyone reading this log can easily
make use of this statement ?
> platform_msi_create_device_domain() is almost ready for ACPI use
> except of_node_to_fwnode() is for dt only, make it ACPI aware then
> things will work in both DTS and ACPI.
This commit log is unreadable and the readable bits do not contain
information that can be used for the purpose a commit log is made
for.
Please rewrite it in a way that can be used in the future to understand
what this patch does and why you want it in the kernel, thanks.
Lorenzo
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> Tested-by: Majun <majun258@huawei.com>
> Tested-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Greg KH <gregkh@linuxfoundation.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> ---
> drivers/base/platform-msi.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/base/platform-msi.c b/drivers/base/platform-msi.c
> index be6a599..035ca3b 100644
> --- a/drivers/base/platform-msi.c
> +++ b/drivers/base/platform-msi.c
> @@ -345,8 +345,7 @@ struct irq_domain *
>
> data->host_data = host_data;
> domain = irq_domain_create_hierarchy(dev->msi_domain, 0, nvec,
> - of_node_to_fwnode(dev->of_node),
> - ops, data);
> + dev->fwnode, ops, data);
> if (!domain)
> goto free_priv;
>
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH 1/2] arm: Cleanup sanity_check_meminfo
From: Laura Abbott @ 2017-01-04 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.20.1701031958100.21662@knanqh.ubzr>
On 01/03/2017 05:12 PM, Nicolas Pitre wrote:
> On Tue, 3 Jan 2017, Laura Abbott wrote:
>
>>
>> The logic for sanity_check_meminfo has become difficult to
>> follow. Clean up the code so it's more obvious what the code
>> is actually trying to do.
>
> Absolutely. This function has a long history of subtle bugs ... and
> broken fixes.
>
>> + if (reg->base < vmalloc_limit) {
>> + if (block_end > arm_lowmem_limit)
>> + arm_lowmem_limit = min(
>> + (phys_addr_t)vmalloc_limit,
>> + block_end);
>
> Just to illustrate how subtle this can be, the above would reintroduce a
> bug that was fixed in commit b9a019899f.
>
>
> Nicolas
>
Yup, I saw that commit and thought "I need to keep the fix". And yet I
still managed to get it wrong. I'll fix in a v2.
Thanks,
Laura
^ permalink raw reply
* [PATCH v4 2/3] dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdma
From: Appana Durga Kedareswara Rao @ 2017-01-04 17:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104152613.hhdptwsyg73ev3dz@rob-hp-laptop>
Hi Rob,
Thanks for the review....
> On Wed, Jan 04, 2017 at 07:05:53PM +0530, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered the DMA using issue_pending API.
> > In the current driver flow we are submitting one frame at a time but
> > we should submit all the n number of frames at one time as the h/w Is
> > configured for n number of frames.
>
> Please fix run-on sentences, capitalization, and word wrapping.
Sure will fix in the next version....
[Snip]
-- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> > @@ -66,6 +66,8 @@ Optional child node properties:
> > Optional child node properties for VDMA:
> > - xlnx,genlock-mode: Tells Genlock synchronization is
> > enabled/disabled in hardware.
> > +- xlnx,fstore-config: Tells Whether Frame Store Configuration is
> > + enabled/disabled in hardware.
>
> What's the default (when not present)? That should be the most common case.
> Looks like the code treats this as bool, but that's not clear here. The name is not
> clear what it is doing. Enabling or disabling the feature?
Default value is zero...
When this property is present it tells hardware is configured for frame store configuration.
Will fix the explanation part in the next version like below.
xlnx,fstore-config: Tells hardware is configured for frame store configuration.
Is the above explanation clear???
Regards,
Kedar.
^ permalink raw reply
* [PATCH v5 3/4] ARM: Add support for CONFIG_DEBUG_VIRTUAL
From: Laura Abbott @ 2017-01-04 17:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104011417.1496-4-f.fainelli@gmail.com>
On 01/03/2017 05:14 PM, Florian Fainelli wrote:
> x86 has an option: CONFIG_DEBUG_VIRTUAL to do additional checks on
> virt_to_phys calls. The goal is to catch users who are calling
> virt_to_phys on non-linear addresses immediately. This includes caller
> using __virt_to_phys() on image addresses instead of __pa_symbol(). This
> is a generally useful debug feature to spot bad code (particulary in
> drivers).
>
> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This mostly looks good with a few comments below
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/include/asm/memory.h | 16 +++++++++++--
> arch/arm/mm/Makefile | 1 +
> arch/arm/mm/physaddr.c | 55 +++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 71 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/mm/physaddr.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5fab553fd03a..4700294f4e09 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -2,6 +2,7 @@ config ARM
> bool
> default y
> select ARCH_CLOCKSOURCE_DATA
> + select ARCH_HAS_DEBUG_VIRTUAL
> select ARCH_HAS_DEVMEM_IS_ALLOWED
> select ARCH_HAS_ELF_RANDOMIZE
> select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index bee7511c5098..d90300193adf 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -213,7 +213,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
> : "r" (x), "I" (__PV_BITS_31_24) \
> : "cc")
>
> -static inline phys_addr_t __virt_to_phys(unsigned long x)
> +static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x)
> {
> phys_addr_t t;
>
> @@ -245,7 +245,7 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
> #define PHYS_OFFSET PLAT_PHYS_OFFSET
> #define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
>
> -static inline phys_addr_t __virt_to_phys(unsigned long x)
> +static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x)
> {
> return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET;
> }
> @@ -261,6 +261,16 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
> ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \
> PHYS_PFN_OFFSET)
>
> +#define __pa_symbol_nodebug(x) __virt_to_phys_nodebug((x))
> +
> +#ifdef CONFIG_DEBUG_VIRTUAL
> +extern phys_addr_t __virt_to_phys(unsigned long x);
> +extern phys_addr_t __phys_addr_symbol(unsigned long x);
> +#else
> +#define __virt_to_phys(x) __virt_to_phys_nodebug(x)
> +#define __phys_addr_symbol(x) __pa_symbol_nodebug(x)
> +#endif
> +
> /*
> * These are *only* valid on the kernel direct mapped RAM memory.
> * Note: Drivers should NOT use these. They are the wrong
> @@ -283,9 +293,11 @@ static inline void *phys_to_virt(phys_addr_t x)
> * Drivers should NOT use these either.
> */
> #define __pa(x) __virt_to_phys((unsigned long)(x))
> +#define __pa_symbol(x) __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0))
> #define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
> #define pfn_to_kaddr(pfn) __va((phys_addr_t)(pfn) << PAGE_SHIFT)
>
> +
Extra blank here
> extern long long arch_phys_to_idmap_offset;
>
> /*
> diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
> index e8698241ece9..b3dea80715b4 100644
> --- a/arch/arm/mm/Makefile
> +++ b/arch/arm/mm/Makefile
> @@ -14,6 +14,7 @@ endif
>
> obj-$(CONFIG_ARM_PTDUMP) += dump.o
> obj-$(CONFIG_MODULES) += proc-syms.o
> +obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
>
> obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
> obj-$(CONFIG_HIGHMEM) += highmem.o
> diff --git a/arch/arm/mm/physaddr.c b/arch/arm/mm/physaddr.c
> new file mode 100644
> index 000000000000..f10bdcbcb155
> --- /dev/null
> +++ b/arch/arm/mm/physaddr.c
> @@ -0,0 +1,55 @@
> +#include <linux/bug.h>
> +#include <linux/export.h>
> +#include <linux/types.h>
> +#include <linux/mmdebug.h>
> +#include <linux/mm.h>
> +
> +#include <asm/sections.h>
> +#include <asm/memory.h>
> +#include <asm/fixmap.h>
> +#include <asm/dma.h>
> +
> +#include "mm.h"
> +
> +static inline bool __virt_addr_valid(unsigned long x)
> +{
> + /* high_memory does not get immediately defined, and there
> + * are early callers of __pa() against PAGE_OFFSET
> + */
Nit: All the comments in this file should have the text starting on
the next line after the /*
> + if (!high_memory && x >= PAGE_OFFSET)
> + return true;
> +
> + if (high_memory && x >= PAGE_OFFSET && x < (unsigned long)high_memory)
> + return true;
> +
> + /* ARM uses the default per-CPU allocation routing which forces us to
> + * have an explicit check here to avoid a false positive
> + */
This comment isn't fully descriptive, MAX_DMA_ADDRESS could be used in more
places than just per-CPU allocation. Suggestion:
/*
* MAX_DMA_ADDRESS is a virtual address that may not correspond to an actual
* physical address. Enough code relies on __pa(MAX_DMA_ADDRESS) that we just
* need to work around it and always return true.
*/
> + if (x == MAX_DMA_ADDRESS)
> + return true;
> +
> + return false;
> +}
> +
> +phys_addr_t __virt_to_phys(unsigned long x)
> +{
> + WARN(!__virt_addr_valid(x),
> + "virt_to_phys used for non-linear address: %pK (%pS)\n",
> + (void *)x,
> + (void *)x);
> +
> + return __virt_to_phys_nodebug(x);
> +}
> +EXPORT_SYMBOL(__virt_to_phys);
> +
> +phys_addr_t __phys_addr_symbol(unsigned long x)
> +{
> + /* This is bounds checking against the kernel image only.
> + * __pa_symbol should only be used on kernel symbol addresses.
> + */
> + VIRTUAL_BUG_ON(x < (unsigned long)KERNEL_START ||
> + x > (unsigned long)KERNEL_END);
> +
> + return __pa_symbol_nodebug(x);
> +}
> +EXPORT_SYMBOL(__phys_addr_symbol);
>
With those comments, you can add
Acked-by: Laura Abbott <labbott@redhat.com>
^ permalink raw reply
* [PATCH] coresight: etm4x: Fix timestamp configuration when working from perf
From: Mathieu Poirier @ 2017-01-04 17:22 UTC (permalink / raw)
To: linux-arm-kernel
When using the ETM4x tracers from the perf interface two trace options are
available: cycle accurate and timestamp.
Enabling the timestamp feature is done by setting TRCCONFIGR.TS (bit 11).
The position of the timestamp bit in that register coincidentally happens
to be the same as what was chosen to enable timestamping from the 'mode'
sysFS entry. The code does the right thing but the semantic is wrong.
This patch sets TRCCONFIGR.TS explicitly, as it is done from the sysFS
interface. That way timestamps are set the same way from both perf and
sysFS and there is no misunderstanding as to what is intended.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index f432febdda49..d1340fb4e457 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -222,7 +222,8 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
}
if (attr->config & BIT(ETM_OPT_TS))
- config->cfg |= ETMv4_MODE_TIMESTAMP;
+ /* bit[11], Global timestamp tracing bit */
+ config->cfg |= BIT(11);
out:
return ret;
--
2.7.4
^ permalink raw reply related
* [PATCH v2] coresight: etm4x: Fix enabling of cycle accurate tracing in perf.
From: Mathieu Poirier @ 2017-01-04 17:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483523231-23993-1-git-send-email-mike.leach@linaro.org>
On 4 January 2017 at 02:47, Mike Leach <mike.leach@linaro.org> wrote:
> Using perf record 'cyclacc' option in cs_etm event was not setting up cycle
> accurate trace correctly.
>
> Corrects bit set in TRCCONFIGR to enable cycle accurate trace.
> Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++--
> drivers/hwtracing/coresight/coresight-etm4x.h | 1 +
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 4db8d6a..c5a65d1 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
> goto out;
>
> /* Go from generic option to ETMv4 specifics */
> - if (attr->config & BIT(ETM_OPT_CYCACC))
> - config->cfg |= ETMv4_MODE_CYCACC;
> + if (attr->config & BIT(ETM_OPT_CYCACC)) {
> + config->cfg |= BIT(4);
> + /* TRM: Must program this for cycacc to work */
> + config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
> + }
> if (attr->config & BIT(ETM_OPT_TS))
> config->cfg |= ETMv4_MODE_TIMESTAMP;
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index ba8d3f8..b3b5ea7 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -146,6 +146,7 @@
> #define ETM_ARCH_V4 0x40
> #define ETMv4_SYNC_MASK 0x1F
> #define ETM_CYC_THRESHOLD_MASK 0xFFF
> +#define ETM_CYC_THRESHOLD_DEFAULT 0x100
> #define ETMv4_EVENT_MASK 0xFF
> #define ETM_CNTR_MAX_VAL 0xFFFF
> #define ETM_TRACEID_MASK 0x3f
> --
> 2.7.4
>
Applied - thanks.
^ permalink raw reply
* [PATCH 3/8] ARM: dts: armada-388-clearfog: Utilize new DSA binding
From: Gregory CLEMENT @ 2017-01-04 17:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170102022249.10657-4-f.fainelli@gmail.com>
Hi Florian,
On lun., janv. 02 2017, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net:
> dsa: Document new binding"). The legacy binding node is kept included, but is
> marked disabled.
>
I tested this patch on mvebu/dt (I needed to reduce the context to apply
the patch due to the changes made by Russell King on this file). I also
set the status of the old binding to "disable" (instead of "okay").
It seems to work with the limited test did:
ifconfig eth1 up
udhcpc -i lan1
iperf -c mylaptop
(same for lan4)
However is there a way to be sure that the new binding is used?
Gregory
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/boot/dts/armada-388-clearfog.dts | 65 +++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
> index 71ce201c903e..35207aa1f4ec 100644
> --- a/arch/arm/boot/dts/armada-388-clearfog.dts
> +++ b/arch/arm/boot/dts/armada-388-clearfog.dts
> @@ -351,6 +351,8 @@
> };
>
> dsa at 0 {
> + status = "okay";
> +
> compatible = "marvell,dsa";
> dsa,ethernet = <ð1>;
> dsa,mii-bus = <&mdio>;
> @@ -444,3 +446,66 @@
> status = "disabled";
> };
> };
> +
> +&mdio {
> + status = "okay";
> +
> + switch at 4 {
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
> + pinctrl-names = "default";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + label = "lan5";
> + };
> +
> + port at 1 {
> + reg = <1>;
> + label = "lan4";
> + };
> +
> + port at 2 {
> + reg = <2>;
> + label = "lan3";
> + };
> +
> + port at 3 {
> + reg = <3>;
> + label = "lan2";
> + };
> +
> + port at 4 {
> + reg = <4>;
> + label = "lan1";
> + };
> +
> + port at 5 {
> + reg = <5>;
> + label = "cpu";
> + ethernet = <ð1>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port at 6 {
> + /* 88E1512 external phy */
> + reg = <6>;
> + label = "lan6";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> + };
> + };
> +};
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 3/8] ARM: dts: armada-388-clearfog: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-04 17:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87shoyeo2j.fsf@free-electrons.com>
On 01/04/2017 09:23 AM, Gregory CLEMENT wrote:
> Hi Florian,
>
> On lun., janv. 02 2017, Florian Fainelli <f.fainelli@gmail.com> wrote:
>
>> Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net:
>> dsa: Document new binding"). The legacy binding node is kept included, but is
>> marked disabled.
>>
>
> I tested this patch on mvebu/dt (I needed to reduce the context to apply
> the patch due to the changes made by Russell King on this file). I also
> set the status of the old binding to "disable" (instead of "okay").
Yes, that needs fixing, thanks for mentioning that.
>
> It seems to work with the limited test did:
> ifconfig eth1 up
> udhcpc -i lan1
> iperf -c mylaptop
>
> (same for lan4)
>
> However is there a way to be sure that the new binding is used?
The best way is probably to make sure that your switch device appears
parented to the MDIO bus driver under /sys/class/mdio_bus/*mvmdio*.
Alternatively, if you see a message like:
DSA: switch 0 0 parsed
in your dmesg, that would also be indicative of using the new binding
and corresponding code.
Thanks a lot for trying that out!
--
Florian
^ permalink raw reply
* [PATCH 1/8] ARM: dts: armada-370-rd: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-04 17:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103163609.GE32450@lunn.ch>
On 01/03/2017 08:36 AM, Andrew Lunn wrote:
>> +
>> + switch: switch at 10 {
>> + compatible = "marvell,mv88e6085";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <16>;
>
> Hummm, a device tree question. switch at 10, reg = <16>. Is there an
> implicit understanding that the 10 is hex?
Most (if not all?) unit addresses are hexadecimal, which is why this was
chosen here, but I really don't mind changing that.
--
Florian
^ permalink raw reply
* [PATCH v5 4/4] ARM: treewide: Replace uses of virt_to_phys with __pa_symbol
From: Laura Abbott @ 2017-01-04 17:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104011417.1496-5-f.fainelli@gmail.com>
On 01/03/2017 05:14 PM, Florian Fainelli wrote:
> All low-level PM/SMP code using virt_to_phys() should actually use
> __pa_symbol() against kernel symbols. Update code where relevant to move
> away from virt_to_phys().
>
Reviewed-by: Laura Abbott <labbott@redhat.com>
> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/common/mcpm_entry.c | 12 ++++++------
> arch/arm/mach-alpine/platsmp.c | 2 +-
> arch/arm/mach-axxia/platsmp.c | 2 +-
> arch/arm/mach-bcm/bcm63xx_smp.c | 2 +-
> arch/arm/mach-bcm/platsmp-brcmstb.c | 2 +-
> arch/arm/mach-bcm/platsmp.c | 4 ++--
> arch/arm/mach-berlin/platsmp.c | 2 +-
> arch/arm/mach-exynos/firmware.c | 4 ++--
> arch/arm/mach-exynos/mcpm-exynos.c | 2 +-
> arch/arm/mach-exynos/platsmp.c | 4 ++--
> arch/arm/mach-exynos/pm.c | 6 +++---
> arch/arm/mach-exynos/suspend.c | 6 +++---
> arch/arm/mach-hisi/platmcpm.c | 2 +-
> arch/arm/mach-hisi/platsmp.c | 6 +++---
> arch/arm/mach-imx/platsmp.c | 2 +-
> arch/arm/mach-imx/pm-imx6.c | 2 +-
> arch/arm/mach-imx/src.c | 2 +-
> arch/arm/mach-mediatek/platsmp.c | 2 +-
> arch/arm/mach-mvebu/pm.c | 2 +-
> arch/arm/mach-mvebu/pmsu.c | 2 +-
> arch/arm/mach-mvebu/system-controller.c | 2 +-
> arch/arm/mach-omap2/control.c | 8 ++++----
> arch/arm/mach-omap2/omap-mpuss-lowpower.c | 12 ++++++------
> arch/arm/mach-omap2/omap-smp.c | 4 ++--
> arch/arm/mach-prima2/platsmp.c | 2 +-
> arch/arm/mach-prima2/pm.c | 2 +-
> arch/arm/mach-pxa/palmz72.c | 2 +-
> arch/arm/mach-pxa/pxa25x.c | 2 +-
> arch/arm/mach-pxa/pxa27x.c | 2 +-
> arch/arm/mach-pxa/pxa3xx.c | 2 +-
> arch/arm/mach-realview/platsmp-dt.c | 2 +-
> arch/arm/mach-rockchip/platsmp.c | 4 ++--
> arch/arm/mach-rockchip/pm.c | 2 +-
> arch/arm/mach-s3c24xx/mach-jive.c | 2 +-
> arch/arm/mach-s3c24xx/pm-s3c2410.c | 2 +-
> arch/arm/mach-s3c24xx/pm-s3c2416.c | 2 +-
> arch/arm/mach-s3c64xx/pm.c | 2 +-
> arch/arm/mach-s5pv210/pm.c | 2 +-
> arch/arm/mach-sa1100/pm.c | 2 +-
> arch/arm/mach-shmobile/platsmp-apmu.c | 6 +++---
> arch/arm/mach-shmobile/platsmp-scu.c | 4 ++--
> arch/arm/mach-socfpga/platsmp.c | 4 ++--
> arch/arm/mach-spear/platsmp.c | 2 +-
> arch/arm/mach-sti/platsmp.c | 2 +-
> arch/arm/mach-sunxi/platsmp.c | 4 ++--
> arch/arm/mach-tango/platsmp.c | 2 +-
> arch/arm/mach-tango/pm.c | 2 +-
> arch/arm/mach-tegra/reset.c | 4 ++--
> arch/arm/mach-ux500/platsmp.c | 2 +-
> arch/arm/mach-vexpress/dcscb.c | 2 +-
> arch/arm/mach-vexpress/platsmp.c | 2 +-
> arch/arm/mach-vexpress/tc2_pm.c | 4 ++--
> arch/arm/mach-zx/platsmp.c | 4 ++--
> arch/arm/mach-zynq/platsmp.c | 2 +-
> 54 files changed, 86 insertions(+), 86 deletions(-)
>
> diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
> index a923524d1040..cf062472e07b 100644
> --- a/arch/arm/common/mcpm_entry.c
> +++ b/arch/arm/common/mcpm_entry.c
> @@ -144,7 +144,7 @@ extern unsigned long mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
>
> void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr)
> {
> - unsigned long val = ptr ? virt_to_phys(ptr) : 0;
> + unsigned long val = ptr ? __pa_symbol(ptr) : 0;
> mcpm_entry_vectors[cluster][cpu] = val;
> sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
> }
> @@ -299,8 +299,8 @@ void mcpm_cpu_power_down(void)
> * the kernel as if the power_up method just had deasserted reset
> * on the CPU.
> */
> - phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
> - phys_reset(virt_to_phys(mcpm_entry_point));
> + phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
> + phys_reset(__pa_symbol(mcpm_entry_point));
>
> /* should never get here */
> BUG();
> @@ -388,8 +388,8 @@ static int __init nocache_trampoline(unsigned long _arg)
> __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
> __mcpm_cpu_down(cpu, cluster);
>
> - phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
> - phys_reset(virt_to_phys(mcpm_entry_point));
> + phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
> + phys_reset(__pa_symbol(mcpm_entry_point));
> BUG();
> }
>
> @@ -449,7 +449,7 @@ int __init mcpm_sync_init(
> sync_cache_w(&mcpm_sync);
>
> if (power_up_setup) {
> - mcpm_power_up_setup_phys = virt_to_phys(power_up_setup);
> + mcpm_power_up_setup_phys = __pa_symbol(power_up_setup);
> sync_cache_w(&mcpm_power_up_setup_phys);
> }
>
> diff --git a/arch/arm/mach-alpine/platsmp.c b/arch/arm/mach-alpine/platsmp.c
> index dd77ea25e7ca..6dc6d491f88a 100644
> --- a/arch/arm/mach-alpine/platsmp.c
> +++ b/arch/arm/mach-alpine/platsmp.c
> @@ -27,7 +27,7 @@ static int alpine_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> phys_addr_t addr;
>
> - addr = virt_to_phys(secondary_startup);
> + addr = __pa_symbol(secondary_startup);
>
> if (addr > (phys_addr_t)(uint32_t)(-1)) {
> pr_err("FAIL: resume address over 32bit (%pa)", &addr);
> diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
> index ffbd71d45008..502e3df69f69 100644
> --- a/arch/arm/mach-axxia/platsmp.c
> +++ b/arch/arm/mach-axxia/platsmp.c
> @@ -25,7 +25,7 @@
> static void write_release_addr(u32 release_phys)
> {
> u32 *virt = (u32 *) phys_to_virt(release_phys);
> - writel_relaxed(virt_to_phys(secondary_startup), virt);
> + writel_relaxed(__pa_symbol(secondary_startup), virt);
> /* Make sure this store is visible to other CPUs */
> smp_wmb();
> __cpuc_flush_dcache_area(virt, sizeof(u32));
> diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c
> index 9b6727ed68cd..f5fb10b4376f 100644
> --- a/arch/arm/mach-bcm/bcm63xx_smp.c
> +++ b/arch/arm/mach-bcm/bcm63xx_smp.c
> @@ -135,7 +135,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
> }
>
> /* Write the secondary init routine to the BootLUT reset vector */
> - val = virt_to_phys(secondary_startup);
> + val = __pa_symbol(secondary_startup);
> writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
>
> /* Power up the core, will jump straight to its reset vector when we
> diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
> index 40dc8448445e..12379960e982 100644
> --- a/arch/arm/mach-bcm/platsmp-brcmstb.c
> +++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
> @@ -151,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
> * Set the reset vector to point to the secondary_startup
> * routine
> */
> - cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
> + cpu_set_boot_addr(cpu, __pa_symbol(secondary_startup));
>
> /* Unhalt the cpu */
> cpu_rst_cfg_set(cpu, 0);
> diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
> index 3ac3a9bc663c..582886d0d02f 100644
> --- a/arch/arm/mach-bcm/platsmp.c
> +++ b/arch/arm/mach-bcm/platsmp.c
> @@ -116,7 +116,7 @@ static int nsp_write_lut(unsigned int cpu)
> return -ENOMEM;
> }
>
> - secondary_startup_phy = virt_to_phys(secondary_startup);
> + secondary_startup_phy = __pa_symbol(secondary_startup);
> BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
>
> writel_relaxed(secondary_startup_phy, sku_rom_lut);
> @@ -189,7 +189,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
> * Secondary cores will start in secondary_startup(),
> * defined in "arch/arm/kernel/head.S"
> */
> - boot_func = virt_to_phys(secondary_startup);
> + boot_func = __pa_symbol(secondary_startup);
> BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
> BUG_ON(boot_func > (phys_addr_t)U32_MAX);
>
> diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
> index 93f90688db18..1167b0ed92c8 100644
> --- a/arch/arm/mach-berlin/platsmp.c
> +++ b/arch/arm/mach-berlin/platsmp.c
> @@ -92,7 +92,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
> * Write the secondary startup address into the SW reset address
> * vector. This is used by boot_inst.
> */
> - writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
> + writel(__pa_symbol(secondary_startup), vectors_base + SW_RESET_ADDR);
>
> iounmap(vectors_base);
> unmap_scu:
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index fd6da5419b51..e81a78b125d9 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -41,7 +41,7 @@ static int exynos_do_idle(unsigned long mode)
> case FW_DO_IDLE_AFTR:
> if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
> exynos_save_cp15();
> - writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
> + writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
> sysram_ns_base_addr + 0x24);
> writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
> if (soc_is_exynos3250()) {
> @@ -135,7 +135,7 @@ static int exynos_suspend(void)
> exynos_save_cp15();
>
> writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
> - writel(virt_to_phys(exynos_cpu_resume_ns),
> + writel(__pa_symbol(exynos_cpu_resume_ns),
> sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
>
> return cpu_suspend(0, exynos_cpu_suspend);
> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
> index f086bf615b29..214a9cfa92e9 100644
> --- a/arch/arm/mach-exynos/mcpm-exynos.c
> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
> @@ -221,7 +221,7 @@ static void exynos_mcpm_setup_entry_point(void)
> */
> __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
> __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
> - __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
> + __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
> }
>
> static struct syscore_ops exynos_mcpm_syscore_ops = {
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index 98ffe1e62ad5..9f4949f7ed88 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -353,7 +353,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> smp_rmb();
>
> - boot_addr = virt_to_phys(exynos4_secondary_startup);
> + boot_addr = __pa_symbol(exynos4_secondary_startup);
>
> ret = exynos_set_boot_addr(core_id, boot_addr);
> if (ret)
> @@ -443,7 +443,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
>
> mpidr = cpu_logical_map(i);
> core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> - boot_addr = virt_to_phys(exynos4_secondary_startup);
> + boot_addr = __pa_symbol(exynos4_secondary_startup);
>
> ret = exynos_set_boot_addr(core_id, boot_addr);
> if (ret)
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index 487295f4a56b..1a7e5b5d08d8 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -132,7 +132,7 @@ static void exynos_set_wakeupmask(long mask)
>
> static void exynos_cpu_set_boot_vector(long flags)
> {
> - writel_relaxed(virt_to_phys(exynos_cpu_resume),
> + writel_relaxed(__pa_symbol(exynos_cpu_resume),
> exynos_boot_vector_addr());
> writel_relaxed(flags, exynos_boot_vector_flag());
> }
> @@ -238,7 +238,7 @@ static int exynos_cpu0_enter_aftr(void)
>
> abort:
> if (cpu_online(1)) {
> - unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
> + unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
>
> /*
> * Set the boot vector to something non-zero
> @@ -330,7 +330,7 @@ static int exynos_cpu1_powerdown(void)
>
> static void exynos_pre_enter_aftr(void)
> {
> - unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
> + unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
>
> (void)exynos_set_boot_addr(1, boot_addr);
> }
> diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
> index 06332f626565..97765be2cc12 100644
> --- a/arch/arm/mach-exynos/suspend.c
> +++ b/arch/arm/mach-exynos/suspend.c
> @@ -344,7 +344,7 @@ static void exynos_pm_prepare(void)
> exynos_pm_enter_sleep_mode();
>
> /* ensure at least INFORM0 has the resume address */
> - pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
> + pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
> }
>
> static void exynos3250_pm_prepare(void)
> @@ -361,7 +361,7 @@ static void exynos3250_pm_prepare(void)
> exynos_pm_enter_sleep_mode();
>
> /* ensure at least INFORM0 has the resume address */
> - pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
> + pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
> }
>
> static void exynos5420_pm_prepare(void)
> @@ -386,7 +386,7 @@ static void exynos5420_pm_prepare(void)
>
> /* ensure at least INFORM0 has the resume address */
> if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
> - pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
> + pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
>
> tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
> tmp &= ~EXYNOS5_USE_RETENTION;
> diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
> index 4b653a8cb75c..a6c117622d67 100644
> --- a/arch/arm/mach-hisi/platmcpm.c
> +++ b/arch/arm/mach-hisi/platmcpm.c
> @@ -327,7 +327,7 @@ static int __init hip04_smp_init(void)
> */
> writel_relaxed(hip04_boot_method[0], relocation);
> writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
> - writel_relaxed(virt_to_phys(secondary_startup), relocation + 8);
> + writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
> writel_relaxed(0, relocation + 12);
> iounmap(relocation);
>
> diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
> index e1d67648d5d0..91bb02dec20f 100644
> --- a/arch/arm/mach-hisi/platsmp.c
> +++ b/arch/arm/mach-hisi/platsmp.c
> @@ -28,7 +28,7 @@ void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
> cpu = cpu_logical_map(cpu);
> if (!cpu || !ctrl_base)
> return;
> - writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
> + writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
> }
>
> int hi3xxx_get_cpu_jump(int cpu)
> @@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> phys_addr_t jumpaddr;
>
> - jumpaddr = virt_to_phys(secondary_startup);
> + jumpaddr = __pa_symbol(secondary_startup);
> hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
> hix5hd2_set_cpu(cpu, true);
> arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> @@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
> struct device_node *node;
>
>
> - jumpaddr = virt_to_phys(secondary_startup);
> + jumpaddr = __pa_symbol(secondary_startup);
> hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
>
> node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
> diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
> index 711dbbd5badd..c2d1b329fba1 100644
> --- a/arch/arm/mach-imx/platsmp.c
> +++ b/arch/arm/mach-imx/platsmp.c
> @@ -117,7 +117,7 @@ static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
> dcfg_base = of_iomap(np, 0);
> BUG_ON(!dcfg_base);
>
> - paddr = virt_to_phys(secondary_startup);
> + paddr = __pa_symbol(secondary_startup);
> writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
>
> iounmap(dcfg_base);
> diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
> index 1515e498d348..e61b1d1027e1 100644
> --- a/arch/arm/mach-imx/pm-imx6.c
> +++ b/arch/arm/mach-imx/pm-imx6.c
> @@ -499,7 +499,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
> memset(suspend_ocram_base, 0, sizeof(*pm_info));
> pm_info = suspend_ocram_base;
> pm_info->pbase = ocram_pbase;
> - pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
> + pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
> pm_info->pm_info_size = sizeof(*pm_info);
>
> /*
> diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
> index 70b083fe934a..495d85d0fe7e 100644
> --- a/arch/arm/mach-imx/src.c
> +++ b/arch/arm/mach-imx/src.c
> @@ -99,7 +99,7 @@ void imx_enable_cpu(int cpu, bool enable)
> void imx_set_cpu_jump(int cpu, void *jump_addr)
> {
> cpu = cpu_logical_map(cpu);
> - writel_relaxed(virt_to_phys(jump_addr),
> + writel_relaxed(__pa_symbol(jump_addr),
> src_base + SRC_GPR1 + cpu * 8);
> }
>
> diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
> index b821e34474b6..726eb69bb655 100644
> --- a/arch/arm/mach-mediatek/platsmp.c
> +++ b/arch/arm/mach-mediatek/platsmp.c
> @@ -122,7 +122,7 @@ static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
> * write the address of slave startup address into the system-wide
> * jump register
> */
> - writel_relaxed(virt_to_phys(secondary_startup_arm),
> + writel_relaxed(__pa_symbol(secondary_startup_arm),
> mtk_smp_base + mtk_smp_info->jump_reg);
> }
>
> diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
> index 2990c5269b18..c487be61d6d8 100644
> --- a/arch/arm/mach-mvebu/pm.c
> +++ b/arch/arm/mach-mvebu/pm.c
> @@ -110,7 +110,7 @@ static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
> {
> phys_addr_t resume_pc;
>
> - resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
> + resume_pc = __pa_symbol(armada_370_xp_cpu_resume);
>
> /*
> * The bootloader expects the first two words to be a magic
> diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
> index f39bd51bce18..27a78c80e5b1 100644
> --- a/arch/arm/mach-mvebu/pmsu.c
> +++ b/arch/arm/mach-mvebu/pmsu.c
> @@ -112,7 +112,7 @@ static const struct of_device_id of_pmsu_table[] = {
>
> void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
> {
> - writel(virt_to_phys(boot_addr), pmsu_mp_base +
> + writel(__pa_symbol(boot_addr), pmsu_mp_base +
> PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
> }
>
> diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
> index 76cbc82a7407..04d9ebe6a90a 100644
> --- a/arch/arm/mach-mvebu/system-controller.c
> +++ b/arch/arm/mach-mvebu/system-controller.c
> @@ -153,7 +153,7 @@ void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
> if (of_machine_is_compatible("marvell,armada375"))
> mvebu_armada375_smp_wa_init();
>
> - writel(virt_to_phys(boot_addr), system_controller_base +
> + writel(__pa_symbol(boot_addr), system_controller_base +
> mvebu_sc->resume_boot_addr);
> }
> #endif
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 1662071bb2cc..bd8089ff929f 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -315,15 +315,15 @@ void omap3_save_scratchpad_contents(void)
> scratchpad_contents.boot_config_ptr = 0x0;
> if (cpu_is_omap3630())
> scratchpad_contents.public_restore_ptr =
> - virt_to_phys(omap3_restore_3630);
> + __pa_symbol(omap3_restore_3630);
> else if (omap_rev() != OMAP3430_REV_ES3_0 &&
> omap_rev() != OMAP3430_REV_ES3_1 &&
> omap_rev() != OMAP3430_REV_ES3_1_2)
> scratchpad_contents.public_restore_ptr =
> - virt_to_phys(omap3_restore);
> + __pa_symbol(omap3_restore);
> else
> scratchpad_contents.public_restore_ptr =
> - virt_to_phys(omap3_restore_es3);
> + __pa_symbol(omap3_restore_es3);
>
> if (omap_type() == OMAP2_DEVICE_TYPE_GP)
> scratchpad_contents.secure_ram_restore_ptr = 0x0;
> @@ -395,7 +395,7 @@ void omap3_save_scratchpad_contents(void)
> sdrc_block_contents.flags = 0x0;
> sdrc_block_contents.block_size = 0x0;
>
> - arm_context_addr = virt_to_phys(omap3_arm_context);
> + arm_context_addr = __pa_symbol(omap3_arm_context);
>
> /* Copy all the contents to the scratchpad location */
> scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
> diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
> index 7d62ad48c7c9..113ab2dd2ee9 100644
> --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
> +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
> @@ -273,7 +273,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
> cpu_clear_prev_logic_pwrst(cpu);
> pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
> pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
> - set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
> + set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
> omap_pm_ops.scu_prepare(cpu, power_state);
> l2x0_pwrst_prepare(cpu, save_state);
>
> @@ -325,7 +325,7 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
>
> pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
> pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
> - set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
> + set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
> omap_pm_ops.scu_prepare(cpu, power_state);
>
> /*
> @@ -467,13 +467,13 @@ void __init omap4_mpuss_early_init(void)
> sar_base = omap4_get_sar_ram_base();
>
> if (cpu_is_omap443x())
> - startup_pa = virt_to_phys(omap4_secondary_startup);
> + startup_pa = __pa_symbol(omap4_secondary_startup);
> else if (cpu_is_omap446x())
> - startup_pa = virt_to_phys(omap4460_secondary_startup);
> + startup_pa = __pa_symbol(omap4460_secondary_startup);
> else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
> - startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
> + startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
> else
> - startup_pa = virt_to_phys(omap5_secondary_startup);
> + startup_pa = __pa_symbol(omap5_secondary_startup);
>
> if (cpu_is_omap44xx())
> writel_relaxed(startup_pa, sar_base +
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index b4de3da6dffa..003353b0b794 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -316,9 +316,9 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
> * A barrier is added to ensure that write buffer is drained
> */
> if (omap_secure_apis_support())
> - omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
> + omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));
> else
> - writel_relaxed(virt_to_phys(cfg.startup_addr),
> + writel_relaxed(__pa_symbol(cfg.startup_addr),
> base + OMAP_AUX_CORE_BOOT_1);
> }
>
> diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
> index 0875b99add18..75ef5d4be554 100644
> --- a/arch/arm/mach-prima2/platsmp.c
> +++ b/arch/arm/mach-prima2/platsmp.c
> @@ -65,7 +65,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
> * waiting for. This would wake up the secondary core from WFE
> */
> #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
> - __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
> + __raw_writel(__pa_symbol(sirfsoc_secondary_startup),
> clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
>
> #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
> diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
> index 83e94c95e314..b0bcf1ff02dd 100644
> --- a/arch/arm/mach-prima2/pm.c
> +++ b/arch/arm/mach-prima2/pm.c
> @@ -54,7 +54,7 @@ static void sirfsoc_set_sleep_mode(u32 mode)
>
> static int sirfsoc_pre_suspend_power_off(void)
> {
> - u32 wakeup_entry = virt_to_phys(cpu_resume);
> + u32 wakeup_entry = __pa_symbol(cpu_resume);
>
> sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
> SIRFSOC_PWRC_SCRATCH_PAD1);
> diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
> index 9c308de158c6..29630061e700 100644
> --- a/arch/arm/mach-pxa/palmz72.c
> +++ b/arch/arm/mach-pxa/palmz72.c
> @@ -249,7 +249,7 @@ static int palmz72_pm_suspend(void)
> store_ptr = *PALMZ72_SAVE_DWORD;
>
> /* Setting PSPR to a proper value */
> - PSPR = virt_to_phys(&palmz72_resume_info);
> + PSPR = __pa_symbol(&palmz72_resume_info);
>
> return 0;
> }
> diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
> index c725baf119e1..ba431fad5c47 100644
> --- a/arch/arm/mach-pxa/pxa25x.c
> +++ b/arch/arm/mach-pxa/pxa25x.c
> @@ -85,7 +85,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
> static int pxa25x_cpu_pm_prepare(void)
> {
> /* set resume return address */
> - PSPR = virt_to_phys(cpu_resume);
> + PSPR = __pa_symbol(cpu_resume);
> return 0;
> }
>
> diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
> index c0185c5c5a08..9b69be4e9fe3 100644
> --- a/arch/arm/mach-pxa/pxa27x.c
> +++ b/arch/arm/mach-pxa/pxa27x.c
> @@ -168,7 +168,7 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state)
> static int pxa27x_cpu_pm_prepare(void)
> {
> /* set resume return address */
> - PSPR = virt_to_phys(cpu_resume);
> + PSPR = __pa_symbol(cpu_resume);
> return 0;
> }
>
> diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
> index 87acc96388c7..0cc9f124c9ac 100644
> --- a/arch/arm/mach-pxa/pxa3xx.c
> +++ b/arch/arm/mach-pxa/pxa3xx.c
> @@ -123,7 +123,7 @@ static void pxa3xx_cpu_pm_suspend(void)
> PSPR = 0x5c014000;
>
> /* overwrite with the resume address */
> - *p = virt_to_phys(cpu_resume);
> + *p = __pa_symbol(cpu_resume);
>
> cpu_suspend(0, pxa3xx_finish_suspend);
>
> diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-realview/platsmp-dt.c
> index 70ca99eb52c6..c242423bf8db 100644
> --- a/arch/arm/mach-realview/platsmp-dt.c
> +++ b/arch/arm/mach-realview/platsmp-dt.c
> @@ -76,7 +76,7 @@ static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
> }
> /* Put the boot address in this magic register */
> regmap_write(map, REALVIEW_SYS_FLAGSSET_OFFSET,
> - virt_to_phys(versatile_secondary_startup));
> + __pa_symbol(versatile_secondary_startup));
> }
>
> static const struct smp_operations realview_dt_smp_ops __initconst = {
> diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
> index 4d827a069d49..3abafdbdd7f4 100644
> --- a/arch/arm/mach-rockchip/platsmp.c
> +++ b/arch/arm/mach-rockchip/platsmp.c
> @@ -156,7 +156,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
> */
> mdelay(1); /* ensure the cpus other than cpu0 to startup */
>
> - writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
> + writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
> writel(0xDEADBEAF, sram_base_addr + 4);
> dsb_sev();
> }
> @@ -195,7 +195,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
> }
>
> /* set the boot function for the sram code */
> - rockchip_boot_fn = virt_to_phys(secondary_startup);
> + rockchip_boot_fn = __pa_symbol(secondary_startup);
>
> /* copy the trampoline to sram, that runs during startup of the core */
> memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
> diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
> index bee8c8051929..0592534e0b88 100644
> --- a/arch/arm/mach-rockchip/pm.c
> +++ b/arch/arm/mach-rockchip/pm.c
> @@ -62,7 +62,7 @@ static inline u32 rk3288_l2_config(void)
> static void rk3288_config_bootdata(void)
> {
> rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
> - rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
> + rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
>
> rkpm_bootdata_l2ctlr_f = 1;
> rkpm_bootdata_l2ctlr = rk3288_l2_config();
> diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
> index 895aca225952..f5b5c49b56ac 100644
> --- a/arch/arm/mach-s3c24xx/mach-jive.c
> +++ b/arch/arm/mach-s3c24xx/mach-jive.c
> @@ -484,7 +484,7 @@ static int jive_pm_suspend(void)
> * correct address to resume from. */
>
> __raw_writel(0x2BED, S3C2412_INFORM0);
> - __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
> + __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
>
> return 0;
> }
> diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
> index 20e481d8a33a..a4588daeddb0 100644
> --- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
> +++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
> @@ -45,7 +45,7 @@ static void s3c2410_pm_prepare(void)
> {
> /* ensure at least GSTATUS3 has the resume address */
>
> - __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
> + __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
>
> S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
> S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
> diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
> index c0e328e37bd6..b5bbf0d5985c 100644
> --- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
> +++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
> @@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
> * correct address to resume from.
> */
> __raw_writel(0x2BED, S3C2412_INFORM0);
> - __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
> + __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
> }
>
> static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
> diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
> index 59d91b83b03d..945a9d1e1a71 100644
> --- a/arch/arm/mach-s3c64xx/pm.c
> +++ b/arch/arm/mach-s3c64xx/pm.c
> @@ -304,7 +304,7 @@ static void s3c64xx_pm_prepare(void)
> wake_irqs, ARRAY_SIZE(wake_irqs));
>
> /* store address of resume. */
> - __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
> + __raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
>
> /* ensure previous wakeup state is cleared before sleeping */
> __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
> diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
> index 21b4b13c5ab7..2d5f08015e34 100644
> --- a/arch/arm/mach-s5pv210/pm.c
> +++ b/arch/arm/mach-s5pv210/pm.c
> @@ -69,7 +69,7 @@ static void s5pv210_pm_prepare(void)
> __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
>
> /* ensure at least INFORM0 has the resume address */
> - __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
> + __raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0);
>
> tmp = __raw_readl(S5P_SLEEP_CFG);
> tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
> diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
> index 34853d5dfda2..9a7079f565bd 100644
> --- a/arch/arm/mach-sa1100/pm.c
> +++ b/arch/arm/mach-sa1100/pm.c
> @@ -73,7 +73,7 @@ static int sa11x0_pm_enter(suspend_state_t state)
> RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
>
> /* set resume return address */
> - PSPR = virt_to_phys(cpu_resume);
> + PSPR = __pa_symbol(cpu_resume);
>
> /* go zzz */
> cpu_suspend(0, sa1100_finish_suspend);
> diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
> index 0c6bb458b7a4..71729b8d1900 100644
> --- a/arch/arm/mach-shmobile/platsmp-apmu.c
> +++ b/arch/arm/mach-shmobile/platsmp-apmu.c
> @@ -171,7 +171,7 @@ static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
> static void __init shmobile_smp_apmu_setup_boot(void)
> {
> /* install boot code shared by all CPUs */
> - shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
> + shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
> }
>
> void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
> @@ -185,7 +185,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
> int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> /* For this particular CPU register boot vector */
> - shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
> + shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
>
> return apmu_wrap(cpu, apmu_power_on);
> }
> @@ -301,7 +301,7 @@ int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
> #if defined(CONFIG_SUSPEND)
> static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
> {
> - shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0);
> + shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
> shmobile_smp_apmu_cpu_shutdown(cpu);
> cpu_do_idle(); /* WFI selects Core Standby */
> return 1;
> diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
> index d1ecaf37d142..f1a1efde4beb 100644
> --- a/arch/arm/mach-shmobile/platsmp-scu.c
> +++ b/arch/arm/mach-shmobile/platsmp-scu.c
> @@ -24,7 +24,7 @@ static void __iomem *shmobile_scu_base;
> static int shmobile_scu_cpu_prepare(unsigned int cpu)
> {
> /* For this particular CPU register SCU SMP boot vector */
> - shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
> + shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_scu),
> shmobile_scu_base_phys);
> return 0;
> }
> @@ -33,7 +33,7 @@ void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
> unsigned int max_cpus)
> {
> /* install boot code shared by all CPUs */
> - shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
> + shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
>
> /* enable SCU and cache coherency on booting CPU */
> shmobile_scu_base_phys = scu_base_phys;
> diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
> index 07945748b571..0ee76772b507 100644
> --- a/arch/arm/mach-socfpga/platsmp.c
> +++ b/arch/arm/mach-socfpga/platsmp.c
> @@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
>
> - writel(virt_to_phys(secondary_startup),
> + writel(__pa_symbol(secondary_startup),
> sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
>
> flush_cache_all();
> @@ -63,7 +63,7 @@ static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle
> SOCFPGA_A10_RSTMGR_MODMPURST);
> memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
>
> - writel(virt_to_phys(secondary_startup),
> + writel(__pa_symbol(secondary_startup),
> sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
>
> flush_cache_all();
> diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
> index 8d1e2d551786..39038a03836a 100644
> --- a/arch/arm/mach-spear/platsmp.c
> +++ b/arch/arm/mach-spear/platsmp.c
> @@ -117,7 +117,7 @@ static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
> * (presently it is in SRAM). The BootMonitor waits until it receives a
> * soft interrupt, and then the secondary CPU branches to this address.
> */
> - __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
> + __raw_writel(__pa_symbol(spear13xx_secondary_startup), SYS_LOCATION);
> }
>
> const struct smp_operations spear13xx_smp_ops __initconst = {
> diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
> index ea5a2277ee46..231f19e17436 100644
> --- a/arch/arm/mach-sti/platsmp.c
> +++ b/arch/arm/mach-sti/platsmp.c
> @@ -103,7 +103,7 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
> u32 __iomem *cpu_strt_ptr;
> u32 release_phys;
> int cpu;
> - unsigned long entry_pa = virt_to_phys(sti_secondary_startup);
> + unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
>
> np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
>
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> index 6642267812c9..8fb5088464db 100644
> --- a/arch/arm/mach-sunxi/platsmp.c
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -80,7 +80,7 @@ static int sun6i_smp_boot_secondary(unsigned int cpu,
> spin_lock(&cpu_lock);
>
> /* Set CPU boot address */
> - writel(virt_to_phys(secondary_startup),
> + writel(__pa_symbol(secondary_startup),
> cpucfg_membase + CPUCFG_PRIVATE0_REG);
>
> /* Assert the CPU core in reset */
> @@ -162,7 +162,7 @@ static int sun8i_smp_boot_secondary(unsigned int cpu,
> spin_lock(&cpu_lock);
>
> /* Set CPU boot address */
> - writel(virt_to_phys(secondary_startup),
> + writel(__pa_symbol(secondary_startup),
> cpucfg_membase + CPUCFG_PRIVATE0_REG);
>
> /* Assert the CPU core in reset */
> diff --git a/arch/arm/mach-tango/platsmp.c b/arch/arm/mach-tango/platsmp.c
> index 98c62a4a8623..2f0c6c050fed 100644
> --- a/arch/arm/mach-tango/platsmp.c
> +++ b/arch/arm/mach-tango/platsmp.c
> @@ -5,7 +5,7 @@
>
> static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> - tango_set_aux_boot_addr(virt_to_phys(secondary_startup));
> + tango_set_aux_boot_addr(__pa_symbol(secondary_startup));
> tango_start_aux_core(cpu);
> return 0;
> }
> diff --git a/arch/arm/mach-tango/pm.c b/arch/arm/mach-tango/pm.c
> index b05c6d6f99d0..406c0814eb6e 100644
> --- a/arch/arm/mach-tango/pm.c
> +++ b/arch/arm/mach-tango/pm.c
> @@ -5,7 +5,7 @@
>
> static int tango_pm_powerdown(unsigned long arg)
> {
> - tango_suspend(virt_to_phys(cpu_resume));
> + tango_suspend(__pa_symbol(cpu_resume));
>
> return -EIO; /* tango_suspend has failed */
> }
> diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
> index 6fd9db54887e..dc558892753c 100644
> --- a/arch/arm/mach-tegra/reset.c
> +++ b/arch/arm/mach-tegra/reset.c
> @@ -94,14 +94,14 @@ void __init tegra_cpu_reset_handler_init(void)
> __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
> *((u32 *)cpu_possible_mask);
> __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
> - virt_to_phys((void *)secondary_startup);
> + __pa_symbol((void *)secondary_startup);
> #endif
>
> #ifdef CONFIG_PM_SLEEP
> __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
> TEGRA_IRAM_LPx_RESUME_AREA;
> __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
> - virt_to_phys((void *)tegra_resume);
> + __pa_symbol((void *)tegra_resume);
> #endif
>
> tegra_cpu_reset_handler_enable();
> diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
> index 8f2f615ff958..8c8f26389067 100644
> --- a/arch/arm/mach-ux500/platsmp.c
> +++ b/arch/arm/mach-ux500/platsmp.c
> @@ -54,7 +54,7 @@ static void wakeup_secondary(void)
> * backup ram register at offset 0x1FF0, which is what boot rom code
> * is waiting for. This will wake up the secondary core from WFE.
> */
> - writel(virt_to_phys(secondary_startup),
> + writel(__pa_symbol(secondary_startup),
> backupram + UX500_CPU1_JUMPADDR_OFFSET);
> writel(0xA1FEED01,
> backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
> diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> index 5cedcf572104..ee2a0faafaa1 100644
> --- a/arch/arm/mach-vexpress/dcscb.c
> +++ b/arch/arm/mach-vexpress/dcscb.c
> @@ -166,7 +166,7 @@ static int __init dcscb_init(void)
> * Future entries into the kernel can now go
> * through the cluster entry vectors.
> */
> - vexpress_flags_set(virt_to_phys(mcpm_entry_point));
> + vexpress_flags_set(__pa_symbol(mcpm_entry_point));
>
> return 0;
> }
> diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
> index 98e29dee91e8..742499bac6d0 100644
> --- a/arch/arm/mach-vexpress/platsmp.c
> +++ b/arch/arm/mach-vexpress/platsmp.c
> @@ -79,7 +79,7 @@ static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus)
> * until it receives a soft interrupt, and then the
> * secondary CPU branches to this address.
> */
> - vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
> + vexpress_flags_set(__pa_symbol(versatile_secondary_startup));
> }
>
> const struct smp_operations vexpress_smp_dt_ops __initconst = {
> diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
> index 1aa4ccece69f..9b5f3c427086 100644
> --- a/arch/arm/mach-vexpress/tc2_pm.c
> +++ b/arch/arm/mach-vexpress/tc2_pm.c
> @@ -54,7 +54,7 @@ static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
> if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
> return -EINVAL;
> ve_spc_set_resume_addr(cluster, cpu,
> - virt_to_phys(mcpm_entry_point));
> + __pa_symbol(mcpm_entry_point));
> ve_spc_cpu_wakeup_irq(cluster, cpu, true);
> return 0;
> }
> @@ -159,7 +159,7 @@ static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
>
> static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
> {
> - ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
> + ve_spc_set_resume_addr(cluster, cpu, __pa_symbol(mcpm_entry_point));
> }
>
> static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
> diff --git a/arch/arm/mach-zx/platsmp.c b/arch/arm/mach-zx/platsmp.c
> index 0297f92084e0..afb9a82dedc3 100644
> --- a/arch/arm/mach-zx/platsmp.c
> +++ b/arch/arm/mach-zx/platsmp.c
> @@ -76,7 +76,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
> * until it receives a soft interrupt, and then the
> * secondary CPU branches to this address.
> */
> - __raw_writel(virt_to_phys(zx_secondary_startup),
> + __raw_writel(__pa_symbol(zx_secondary_startup),
> aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
>
> iounmap(aonsysctrl_base);
> @@ -94,7 +94,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
>
> /* Map the first 4 KB IRAM for suspend usage */
> sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
> - zx_secondary_startup_pa = virt_to_phys(zx_secondary_startup);
> + zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
> fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
> }
>
> diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
> index 7cd9865bdeb7..caa6d5fe9078 100644
> --- a/arch/arm/mach-zynq/platsmp.c
> +++ b/arch/arm/mach-zynq/platsmp.c
> @@ -89,7 +89,7 @@ EXPORT_SYMBOL(zynq_cpun_start);
>
> static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> - return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
> + return zynq_cpun_start(__pa_symbol(secondary_startup), cpu);
> }
>
> /*
>
^ permalink raw reply
* [PATCH 1/5] clk: mvebu: support for 98DX3236 SoC
From: Gregory CLEMENT @ 2017-01-04 17:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161222041328.3303-2-chris.packham@alliedtelesis.co.nz>
Hi Chris,
On jeu., d?c. 22 2016, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
>
> The clock gating options are a subset of those on the Armada XP.
>
> The core clock divider is different to the Armada XP also.
This patch looks good, however you should update the device tree binding
documentation too.
Thanks,
Gregory
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> drivers/clk/mvebu/Makefile | 2 +-
> drivers/clk/mvebu/armada-xp.c | 42 +++++++
> drivers/clk/mvebu/clk-cpu.c | 33 +++++-
> drivers/clk/mvebu/mv98dx3236-corediv.c | 207 +++++++++++++++++++++++++++++++++
> 4 files changed, 280 insertions(+), 4 deletions(-)
> create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c
>
> diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
> index d9ae97fb43c4..6a3681e3d6db 100644
> --- a/drivers/clk/mvebu/Makefile
> +++ b/drivers/clk/mvebu/Makefile
> @@ -9,7 +9,7 @@ obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o
> obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-xtal.o
> obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-tbg.o
> obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o
> -obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
> +obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236-corediv.o
> obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
> obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
> obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o
> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
> index b3094315a3c0..0413bf8284e0 100644
> --- a/drivers/clk/mvebu/armada-xp.c
> +++ b/drivers/clk/mvebu/armada-xp.c
> @@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
> return 250000000;
> }
>
> +/* MV98DX3236 TCLK frequency is fixed to 200MHz */
> +static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
> +{
> + return 200000000;
> +}
> +
> static const u32 axp_cpu_freqs[] __initconst = {
> 1000000000,
> 1066000000,
> @@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
> return cpu_freq;
> }
>
> +/* MV98DX3236 CLK frequency is fixed to 800MHz */
> +static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
> +{
> + return 800000000;
> +}
> +
> static const int axp_nbclk_ratios[32][2] __initconst = {
> {0, 1}, {1, 2}, {2, 2}, {2, 2},
> {1, 2}, {1, 2}, {1, 1}, {2, 3},
> @@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = {
> .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
> };
>
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
> + .get_clk_ratio = NULL,
> + .ratios = NULL,
> + .num_ratios = 0,
> +};
> +
> /*
> * Clock Gating Control
> */
> @@ -195,6 +215,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
> { }
> };
>
> +static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
> + { "ge1", NULL, 3, 0 },
> + { "ge0", NULL, 4, 0 },
> + { "pex00", NULL, 5, 0 },
> + { "sdio", NULL, 17, 0 },
> + { "xor0", NULL, 22, 0 },
> + { }
> +};
> +
> static void __init axp_clk_init(struct device_node *np)
> {
> struct device_node *cgnp =
> @@ -206,3 +235,16 @@ static void __init axp_clk_init(struct device_node *np)
> mvebu_clk_gating_setup(cgnp, axp_gating_desc);
> }
> CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
> +
> +static void __init mv98dx3236_clk_init(struct device_node *np)
> +{
> + struct device_node *cgnp =
> + of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
> +
> + mvebu_coreclk_setup(np, &mv98dx3236_coreclks);
> +
> + if (cgnp)
> + mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
> +}
> +CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock",
> + mv98dx3236_clk_init);
> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
> index 5837eb8a212f..29f295e7a36b 100644
> --- a/drivers/clk/mvebu/clk-cpu.c
> +++ b/drivers/clk/mvebu/clk-cpu.c
> @@ -165,7 +165,9 @@ static const struct clk_ops cpu_ops = {
> .set_rate = clk_cpu_set_rate,
> };
>
> -static void __init of_cpu_clk_setup(struct device_node *node)
> +/* Add parameter to allow this to support different clock operations. */
> +static void __init _of_cpu_clk_setup(struct device_node *node,
> + const struct clk_ops *cpu_clk_ops)
> {
> struct cpu_clk *cpuclk;
> void __iomem *clock_complex_base = of_iomap(node, 0);
> @@ -218,7 +220,7 @@ static void __init of_cpu_clk_setup(struct device_node *node)
> cpuclk[cpu].hw.init = &init;
>
> init.name = cpuclk[cpu].clk_name;
> - init.ops = &cpu_ops;
> + init.ops = cpu_clk_ops;
> init.flags = 0;
> init.parent_names = &cpuclk[cpu].parent_name;
> init.num_parents = 1;
> @@ -243,5 +245,30 @@ static void __init of_cpu_clk_setup(struct device_node *node)
> iounmap(clock_complex_base);
> }
>
> +/* Use this function to call the generic setup with the correct
> + * clock operation
> + */
> +static void __init of_cpu_clk_setup(struct device_node *node)
> +{
> + _of_cpu_clk_setup(node, &cpu_ops);
> +}
> +
> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
> - of_cpu_clk_setup);
> + of_cpu_clk_setup);
> +
> +/* Define the clock and operations for the mv98dx3236 - it cannot perform
> + * any operations.
> + */
> +static const struct clk_ops mv98dx3236_cpu_ops = {
> + .recalc_rate = NULL,
> + .round_rate = NULL,
> + .set_rate = NULL,
> +};
> +
> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
> +{
> + _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
> +}
> +
> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
> + of_mv98dx3236_cpu_clk_setup);
> diff --git a/drivers/clk/mvebu/mv98dx3236-corediv.c b/drivers/clk/mvebu/mv98dx3236-corediv.c
> new file mode 100644
> index 000000000000..3060764a8e5d
> --- /dev/null
> +++ b/drivers/clk/mvebu/mv98dx3236-corediv.c
> @@ -0,0 +1,207 @@
> +/*
> + * MV98DX3236 Core divider clock
> + *
> + * Copyright (C) 2015 Allied Telesis Labs
> + *
> + * Based on armada-xp-corediv.c
> + * Copyright (C) 2015 Marvell
> + *
> + * John Thompson <john.thompson@alliedtelesis.co.nz>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/kernel.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/delay.h>
> +#include "common.h"
> +
> +#define CORE_CLK_DIV_RATIO_MASK 0xff
> +
> +#define CLK_DIV_RATIO_NAND_MASK 0x0f
> +#define CLK_DIV_RATIO_NAND_OFFSET 6
> +#define CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT 26
> +
> +#define RATIO_RELOAD_BIT BIT(10)
> +#define RATIO_REG_OFFSET 0x08
> +
> +/*
> + * This structure represents one core divider clock for the clock
> + * framework, and is dynamically allocated for each core divider clock
> + * existing in the current SoC.
> + */
> +struct clk_corediv {
> + struct clk_hw hw;
> + void __iomem *reg;
> + spinlock_t lock;
> +};
> +
> +static struct clk_onecell_data clk_data;
> +
> +
> +#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
> +
> +static int mv98dx3236_corediv_is_enabled(struct clk_hw *hwclk)
> +{
> + /* Core divider is always active */
> + return 1;
> +}
> +
> +static int mv98dx3236_corediv_enable(struct clk_hw *hwclk)
> +{
> + /* always succeeds */
> + return 0;
> +}
> +
> +static void mv98dx3236_corediv_disable(struct clk_hw *hwclk)
> +{
> + /* can't be disabled so is left alone */
> +}
> +
> +static unsigned long mv98dx3236_corediv_recalc_rate(struct clk_hw *hwclk,
> + unsigned long parent_rate)
> +{
> + struct clk_corediv *corediv = to_corediv_clk(hwclk);
> + u32 reg, div;
> +
> + reg = readl(corediv->reg + RATIO_REG_OFFSET);
> + div = (reg >> CLK_DIV_RATIO_NAND_OFFSET) & CLK_DIV_RATIO_NAND_MASK;
> + return parent_rate / div;
> +}
> +
> +static long mv98dx3236_corediv_round_rate(struct clk_hw *hwclk,
> + unsigned long rate, unsigned long *parent_rate)
> +{
> + /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
> + u32 div;
> +
> + div = *parent_rate / rate;
> + if (div < 4)
> + div = 4;
> + else if (div > 6)
> + div = 8;
> +
> + return *parent_rate / div;
> +}
> +
> +static int mv98dx3236_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_corediv *corediv = to_corediv_clk(hwclk);
> + unsigned long flags = 0;
> + u32 reg, div;
> +
> + div = parent_rate / rate;
> +
> + spin_lock_irqsave(&corediv->lock, flags);
> +
> + /* Write new divider to the divider ratio register */
> + reg = readl(corediv->reg + RATIO_REG_OFFSET);
> + reg &= ~(CLK_DIV_RATIO_NAND_MASK << CLK_DIV_RATIO_NAND_OFFSET);
> + reg |= (div & CLK_DIV_RATIO_NAND_MASK) << CLK_DIV_RATIO_NAND_OFFSET;
> + writel(reg, corediv->reg + RATIO_REG_OFFSET);
> +
> + /* Set reload-force for this clock */
> + reg = readl(corediv->reg) | BIT(CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT);
> + writel(reg, corediv->reg);
> +
> + /* Now trigger the clock update */
> + reg = readl(corediv->reg + RATIO_REG_OFFSET) | RATIO_RELOAD_BIT;
> + writel(reg, corediv->reg + RATIO_REG_OFFSET);
> +
> + /*
> + * Wait for clocks to settle down, and then clear all the
> + * ratios request and the reload request.
> + */
> + udelay(1000);
> + reg &= ~(CORE_CLK_DIV_RATIO_MASK | RATIO_RELOAD_BIT);
> + writel(reg, corediv->reg + RATIO_REG_OFFSET);
> + udelay(1000);
> +
> + spin_unlock_irqrestore(&corediv->lock, flags);
> +
> + return 0;
> +}
> +
> +static const struct clk_ops ops = {
> + .enable = mv98dx3236_corediv_enable,
> + .disable = mv98dx3236_corediv_disable,
> + .is_enabled = mv98dx3236_corediv_is_enabled,
> + .recalc_rate = mv98dx3236_corediv_recalc_rate,
> + .round_rate = mv98dx3236_corediv_round_rate,
> + .set_rate = mv98dx3236_corediv_set_rate,
> +};
> +
> +static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
> +{
> + struct clk_init_data init;
> + struct clk_corediv *corediv;
> + struct clk **clks;
> + void __iomem *base;
> + const __be32 *off;
> + const char *parent_name;
> + const char *clk_name;
> + int len;
> + struct device_node *dfx_node;
> +
> + dfx_node = of_parse_phandle(node, "base", 0);
> + if (WARN_ON(!dfx_node))
> + return;
> +
> + off = of_get_property(node, "reg", &len);
> + if (WARN_ON(!off))
> + return;
> +
> + base = of_iomap(dfx_node, 0);
> + if (WARN_ON(!base))
> + return;
> +
> + of_node_put(dfx_node);
> +
> + parent_name = of_clk_get_parent_name(node, 0);
> +
> + clk_data.clk_num = 1;
> +
> + /* clks holds the clock array */
> + clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
> + GFP_KERNEL);
> + if (WARN_ON(!clks))
> + goto err_unmap;
> + /* corediv holds the clock specific array */
> + corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
> + GFP_KERNEL);
> + if (WARN_ON(!corediv))
> + goto err_free_clks;
> +
> + spin_lock_init(&corediv->lock);
> +
> + of_property_read_string_index(node, "clock-output-names",
> + 0, &clk_name);
> +
> + init.num_parents = 1;
> + init.parent_names = &parent_name;
> + init.name = clk_name;
> + init.ops = &ops;
> + init.flags = 0;
> +
> + corediv[0].reg = (void *)((int)base + be32_to_cpu(*off));
> + corediv[0].hw.init = &init;
> +
> + clks[0] = clk_register(NULL, &corediv[0].hw);
> + WARN_ON(IS_ERR(clks[0]));
> +
> + clk_data.clks = clks;
> + of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
> + return;
> +
> +err_free_clks:
> + kfree(clks);
> +err_unmap:
> + iounmap(base);
> +}
> +
> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
> + mv98dx3236_corediv_clk_init);
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH v2] mfd: mc13xxx: Set the irq type.
From: Magnus Lilja @ 2017-01-04 17:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104110959.GZ27589@dell>
Hi,
On 4 January 2017 at 12:09, Lee Jones <lee.jones@linaro.org> wrote:
> On Fri, 30 Dec 2016, Magnus Lilja wrote:
>
>> Commit 10f9edaeaa30 ("mfd: mc13xxx: Use regmap irq framework for
>> interrupts") removed the passing of the IRQF_TRIGGER_HIGH flag when
>> registering the interrupt.
>> This commit fixes that problem by setting the IRQF_TRIGGER_HIGH flag in
>> case no irq type is set via irqd framework (e.g. device tree). In the
>> latter case the irq flag from irqd is used.
>
> This looks like a hack.
>
> Why can't you set the trigger type in Device Tree instead?
The i.MX31 PDK board has not, like many (all?) i.MX31 boards, not been
converted to use device tree yet. I think there is work in progress in
this area. However, as the IRQF_TRIGGER problem also affects several
stable kernel series (since 3.18.x) I thought it was worthwhile to fix
this.
Regards, Magnus
>> Tested on i.MX31 PDK hardware.
>>
>> Fixes: 10f9edaeaa30 ("mfd: mc13xxx: Use regmap irq framework for interrupts")
>> Cc: <stable@vger.kernel.org> # 3.18.x
>> Cc: Lee Jones <lee.jones@linaro.org>
>> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
>> ---
>> Changes from v1 (which was part of a patch series):
>> - Now uses irqd_-functions to check if irq type is defined
>> - Added Fixes: and Cc: to stable kernel.
>>
>> drivers/mfd/mc13xxx-core.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
>> index d7f54e4..e1757ea 100644
>> --- a/drivers/mfd/mc13xxx-core.c
>> +++ b/drivers/mfd/mc13xxx-core.c
>> @@ -15,6 +15,7 @@
>> #include <linux/of_device.h>
>> #include <linux/platform_device.h>
>> #include <linux/mfd/core.h>
>> +#include <linux/irq.h>
>>
>> #include "mc13xxx.h"
>>
>> @@ -410,6 +411,7 @@ int mc13xxx_common_init(struct device *dev)
>> struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
>> u32 revision;
>> int i, ret;
>> + unsigned int flags;
>>
>> mc13xxx->dev = dev;
>>
>> @@ -440,7 +442,11 @@ int mc13xxx_common_init(struct device *dev)
>> mc13xxx->irq_chip.irqs = mc13xxx->irqs;
>> mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
>>
>> - ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
>> + flags = irqd_get_trigger_type(irq_get_irq_data(mc13xxx->irq));
>> + flags = (flags == IRQ_TYPE_NONE) ? IRQF_TRIGGER_HIGH : flags;
>> +
>> + ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq,
>> + IRQF_ONESHOT | flags,
>> 0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
>> if (ret)
>> return ret;
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox