* [PATCH v2, 3/9] arm64: dts: ls1043a: fix typo of MSI compatible string
From: Minghuan Lian @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483603837-4629-1-git-send-email-Minghuan.Lian@nxp.com>
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
v2-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index ec13a6e..692fc35 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -589,21 +589,21 @@
};
msi1: msi-controller1 at 1571000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>;
msi-controller;
interrupts = <0 116 0x4>;
};
msi2: msi-controller2 at 1572000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1572000 0x0 0x8>;
msi-controller;
interrupts = <0 126 0x4>;
};
msi3: msi-controller3 at 1573000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1573000 0x0 0x8>;
msi-controller;
interrupts = <0 160 0x4>;
--
1.9.1
^ permalink raw reply related
* [PATCH v2,4/9] arm: dts: ls1021a: share all MSIs
From: Minghuan Lian @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483603837-4629-1-git-send-email-Minghuan.Lian@nxp.com>
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
v2-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 6651938..1c82024 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -723,7 +723,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi1>;
+ msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -746,7 +746,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi2>;
+ msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
--
1.9.1
^ permalink raw reply related
* [PATCH v2,5/9] arm64: dts: ls1043a: share all MSIs
From: Minghuan Lian @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483603837-4629-1-git-send-email-Minghuan.Lian@nxp.com>
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
v2-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 692fc35..3947220 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -625,7 +625,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi1>;
+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
@@ -650,7 +650,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi2>;
+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
@@ -675,7 +675,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi3>;
+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
--
1.9.1
^ permalink raw reply related
* [PATCH v2,6/9] arm64: dts: ls1046a: add MSI dts node
From: Minghuan Lian @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483603837-4629-1-git-send-email-Minghuan.Lian@nxp.com>
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2-v1:
- change whitespace number
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 31 ++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 2755cd1..dde4552 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -6,6 +6,7 @@ Required properties:
Layerscape PCIe MSI controller block such as:
"fsl,ls1021a-msi"
"fsl,ls1043a-msi"
+ "fsl,ls1046a-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..49dbafc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -511,5 +511,36 @@
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
+
+ msi1: msi-controller at 1580000 {
+ compatible = "fsl,ls1046a-msi";
+ msi-controller;
+ reg = <0x0 0x1580000 0x0 0x10000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ msi2: msi-controller at 1590000 {
+ compatible = "fsl,ls1046a-msi";
+ msi-controller;
+ reg = <0x0 0x1590000 0x0 0x10000>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ msi3: msi-controller at 15a0000 {
+ compatible = "fsl,ls1046a-msi";
+ msi-controller;
+ reg = <0x0 0x15a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2,7/9] irqchip/ls-scfg-msi: add LS1046a MSI support
From: Minghuan Lian @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483603837-4629-1-git-send-email-Minghuan.Lian@nxp.com>
LS1046a includes 4 MSIRs, each MSIR is assigned a dedicate GIC
SPI interrupt and provides 32 MSI interrupts. Compared to previous
MSI, LS1046a's IBS(interrupt bit select) shift is changed to 2 and
total MSI interrupt number is changed to 128.
The patch adds structure 'ls_scfg_msir' to describe MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
v2-v1:
- MSI dts node change has been merged into the patch 6/9
drivers/irqchip/irq-ls-scfg-msi.c | 161 +++++++++++++++++++++++++++++---------
1 file changed, 126 insertions(+), 35 deletions(-)
diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index cef67cc..67547bd 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -17,13 +17,24 @@
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/spinlock.h>
-#define MSI_MAX_IRQS 32
-#define MSI_IBS_SHIFT 3
-#define MSIR 4
+#define MSI_IRQS_PER_MSIR 32
+#define MSI_MSIR_OFFSET 4
+
+struct ls_scfg_msi_cfg {
+ u32 ibs_shift; /* Shift of interrupt bit select */
+};
+
+struct ls_scfg_msir {
+ struct ls_scfg_msi *msi_data;
+ unsigned int index;
+ unsigned int gic_irq;
+ void __iomem *reg;
+};
struct ls_scfg_msi {
spinlock_t lock;
@@ -32,8 +43,11 @@ struct ls_scfg_msi {
struct irq_domain *msi_domain;
void __iomem *regs;
phys_addr_t msiir_addr;
- int irq;
- DECLARE_BITMAP(used, MSI_MAX_IRQS);
+ struct ls_scfg_msi_cfg *cfg;
+ u32 msir_num;
+ struct ls_scfg_msir *msir;
+ u32 irqs_num;
+ unsigned long *used;
};
static struct irq_chip ls_scfg_msi_irq_chip = {
@@ -55,7 +69,7 @@ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
msg->address_hi = upper_32_bits(msi_data->msiir_addr);
msg->address_lo = lower_32_bits(msi_data->msiir_addr);
- msg->data = data->hwirq << MSI_IBS_SHIFT;
+ msg->data = data->hwirq;
}
static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
@@ -81,8 +95,8 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
WARN_ON(nr_irqs != 1);
spin_lock(&msi_data->lock);
- pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
- if (pos < MSI_MAX_IRQS)
+ pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
+ if (pos < msi_data->irqs_num)
__set_bit(pos, msi_data->used);
else
err = -ENOSPC;
@@ -106,7 +120,7 @@ static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
int pos;
pos = d->hwirq;
- if (pos < 0 || pos >= MSI_MAX_IRQS) {
+ if (pos < 0 || pos >= msi_data->irqs_num) {
pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
return;
}
@@ -123,15 +137,17 @@ static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
{
- struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
+ struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
+ struct ls_scfg_msi *msi_data = msir->msi_data;
unsigned long val;
- int pos, virq;
+ int pos, virq, hwirq;
chained_irq_enter(irq_desc_get_chip(desc), desc);
- val = ioread32be(msi_data->regs + MSIR);
- for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
- virq = irq_find_mapping(msi_data->parent, (31 - pos));
+ val = ioread32be(msir->reg);
+ for_each_set_bit(pos, &val, MSI_IRQS_PER_MSIR) {
+ hwirq = ((31 - pos) << msi_data->cfg->ibs_shift) | msir->index;
+ virq = irq_find_mapping(msi_data->parent, hwirq);
if (virq)
generic_handle_irq(virq);
}
@@ -143,7 +159,7 @@ static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
{
/* Initialize MSI domain parent */
msi_data->parent = irq_domain_add_linear(NULL,
- MSI_MAX_IRQS,
+ msi_data->irqs_num,
&ls_scfg_msi_domain_ops,
msi_data);
if (!msi_data->parent) {
@@ -164,16 +180,83 @@ static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
return 0;
}
+static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
+{
+ struct ls_scfg_msir *msir;
+ int virq, i, hwirq;
+
+ virq = platform_get_irq(msi_data->pdev, index);
+ if (virq <= 0)
+ return -ENODEV;
+
+ msir = &msi_data->msir[index];
+ msir->index = index;
+ msir->msi_data = msi_data;
+ msir->gic_irq = virq;
+ msir->reg = msi_data->regs + MSI_MSIR_OFFSET + 4 * index;
+
+ irq_set_chained_handler_and_data(msir->gic_irq,
+ ls_scfg_msi_irq_handler,
+ msir);
+
+ /* Release the hwirqs corresponding to this MSIR */
+ for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
+ hwirq = i << msi_data->cfg->ibs_shift | msir->index;
+ bitmap_clear(msi_data->used, hwirq, 1);
+ }
+
+ return 0;
+}
+
+static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
+{
+ struct ls_scfg_msi *msi_data = msir->msi_data;
+ int i, hwirq;
+
+ if (msir->gic_irq > 0)
+ irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
+
+ for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
+ hwirq = i << msi_data->cfg->ibs_shift | msir->index;
+ bitmap_set(msi_data->used, hwirq, 1);
+ }
+
+ return 0;
+}
+
+static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
+ .ibs_shift = 3,
+};
+
+static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
+ .ibs_shift = 2,
+};
+
+static const struct of_device_id ls_scfg_msi_id[] = {
+ { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
+ { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
+ { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
+
static int ls_scfg_msi_probe(struct platform_device *pdev)
{
+ const struct of_device_id *match;
struct ls_scfg_msi *msi_data;
struct resource *res;
- int ret;
+ int i, ret;
+
+ match = of_match_device(ls_scfg_msi_id, &pdev->dev);
+ if (!match)
+ return -ENODEV;
msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
if (!msi_data)
return -ENOMEM;
+ msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(msi_data->regs)) {
@@ -182,23 +265,37 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
}
msi_data->msiir_addr = res->start;
- msi_data->irq = platform_get_irq(pdev, 0);
- if (msi_data->irq <= 0) {
- dev_err(&pdev->dev, "failed to get MSI irq\n");
- return -ENODEV;
- }
-
msi_data->pdev = pdev;
spin_lock_init(&msi_data->lock);
+ msi_data->irqs_num = MSI_IRQS_PER_MSIR *
+ (1 << msi_data->cfg->ibs_shift);
+ msi_data->used = devm_kcalloc(&pdev->dev,
+ BITS_TO_LONGS(msi_data->irqs_num),
+ sizeof(*msi_data->used),
+ GFP_KERNEL);
+ if (!msi_data->used)
+ return -ENOMEM;
+ /*
+ * Reserve all the hwirqs
+ * The available hwirqs will be released in ls1_msi_setup_hwirq()
+ */
+ bitmap_set(msi_data->used, 0, msi_data->irqs_num);
+
+ msi_data->msir_num = of_irq_count(pdev->dev.of_node);
+ msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
+ sizeof(*msi_data->msir),
+ GFP_KERNEL);
+ if (!msi_data->msir)
+ return -ENOMEM;
+
+ for (i = 0; i < msi_data->msir_num; i++)
+ ls_scfg_msi_setup_hwirq(msi_data, i);
+
ret = ls_scfg_msi_domains_init(msi_data);
if (ret)
return ret;
- irq_set_chained_handler_and_data(msi_data->irq,
- ls_scfg_msi_irq_handler,
- msi_data);
-
platform_set_drvdata(pdev, msi_data);
return 0;
@@ -207,8 +304,10 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
static int ls_scfg_msi_remove(struct platform_device *pdev)
{
struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
+ int i;
- irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
+ for (i = 0; i < msi_data->msir_num; i++)
+ ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
irq_domain_remove(msi_data->msi_domain);
irq_domain_remove(msi_data->parent);
@@ -218,14 +317,6 @@ static int ls_scfg_msi_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id ls_scfg_msi_id[] = {
- { .compatible = "fsl,1s1021a-msi", }, /* a typo */
- { .compatible = "fsl,1s1043a-msi", }, /* a typo */
- { .compatible = "fsl,ls1021a-msi", },
- { .compatible = "fsl,ls1043a-msi", },
- {},
-};
-
static struct platform_driver ls_scfg_msi_driver = {
.driver = {
.name = "ls-scfg-msi",
--
1.9.1
^ permalink raw reply related
* [PATCH 15/22] mfd: axp20x: add CHRG_CTRL1 to writeable regs for AXP20X/AXP22X
From: Quentin Schulz @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67KmaECfFO+QBxKbtKscD0O=KNVHO1TS4FspYEdaLWUCA@mail.gmail.com>
On 05/01/2017 07:10, Chen-Yu Tsai wrote:
> On Tue, Jan 3, 2017 at 12:37 AM, Quentin Schulz
> <quentin.schulz@free-electrons.com> wrote:
>> The CHR_CTRL1 register is made of 7 read-write bits with one being used
>> to set the target voltage for battery charging.
>
> The description is incorrect.
>
> All 8 bits are read-write:
>
> - The highest bit enables the charger module
> - Bits [6:5] set the target voltage
> - Bits [4:3] set when the charge cycle ends, based on percentage
> of charge current
> - Bits [2:0] set the charge current
>
> Feel free to use the above in the commit message.
>
Thanks for the correction.
>>
>> This adds the CHRG_CTRL1 register to the list of writeable registers for
>> AXP20X and AXP22X PMICs.
>
> You might want to add up to CHRG_CTRL3 for the AXP22x and CHRG_CTRL2
> for the AXP20x. These control additional aspects of the charger.
>
ACK.
> AXP20X_CHRG_BAK_CTRL controls the charger for the RTC battery. You
> could add this now, or let the person doing the RTC battery driver
> add it.
I'll let the person adding the RTC battery driver add it.
Thanks,
Quentin
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2,8/9] irqchip/ls-scfg-msi: add LS1043a v1.1 MSI support
From: Minghuan Lian @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483603837-4629-1-git-send-email-Minghuan.Lian@nxp.com>
A MSI controller of LS1043a v1.0 only includes one MSIR and
is assigned one GIC interrupt. In order to support affinity,
LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts.
But the MSIR has the different offset and only supports 8 MSIs.
The bits between variable bit_start and bit_end in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2-v1:
- None
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
drivers/irqchip/irq-ls-scfg-msi.c | 45 +++++++++++++++++++---
2 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index dde4552..49ccabb 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -7,6 +7,7 @@ Required properties:
"fsl,ls1021a-msi"
"fsl,ls1043a-msi"
"fsl,ls1046a-msi"
+ "fsl,ls1043a-v1.1-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index 67547bd..dc19569 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -25,14 +25,21 @@
#define MSI_IRQS_PER_MSIR 32
#define MSI_MSIR_OFFSET 4
+#define MSI_LS1043V1_1_IRQS_PER_MSIR 8
+#define MSI_LS1043V1_1_MSIR_OFFSET 0x10
+
struct ls_scfg_msi_cfg {
u32 ibs_shift; /* Shift of interrupt bit select */
+ u32 msir_irqs; /* The irq number per MSIR */
+ u32 msir_base; /* The base address of MSIR */
};
struct ls_scfg_msir {
struct ls_scfg_msi *msi_data;
unsigned int index;
unsigned int gic_irq;
+ unsigned int bit_start;
+ unsigned int bit_end;
void __iomem *reg;
};
@@ -140,13 +147,18 @@ static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
struct ls_scfg_msi *msi_data = msir->msi_data;
unsigned long val;
- int pos, virq, hwirq;
+ int pos, size, virq, hwirq;
chained_irq_enter(irq_desc_get_chip(desc), desc);
val = ioread32be(msir->reg);
- for_each_set_bit(pos, &val, MSI_IRQS_PER_MSIR) {
- hwirq = ((31 - pos) << msi_data->cfg->ibs_shift) | msir->index;
+
+ pos = msir->bit_start;
+ size = msir->bit_end + 1;
+
+ for_each_set_bit_from(pos, &val, size) {
+ hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
+ msir->index;
virq = irq_find_mapping(msi_data->parent, hwirq);
if (virq)
generic_handle_irq(virq);
@@ -193,14 +205,24 @@ static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
msir->index = index;
msir->msi_data = msi_data;
msir->gic_irq = virq;
- msir->reg = msi_data->regs + MSI_MSIR_OFFSET + 4 * index;
+ msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
+
+ if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
+ msir->bit_start = 32 - ((msir->index + 1) *
+ MSI_LS1043V1_1_IRQS_PER_MSIR);
+ msir->bit_end = msir->bit_start +
+ MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
+ } else {
+ msir->bit_start = 0;
+ msir->bit_end = msi_data->cfg->msir_irqs - 1;
+ }
irq_set_chained_handler_and_data(msir->gic_irq,
ls_scfg_msi_irq_handler,
msir);
/* Release the hwirqs corresponding to this MSIR */
- for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
+ for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
hwirq = i << msi_data->cfg->ibs_shift | msir->index;
bitmap_clear(msi_data->used, hwirq, 1);
}
@@ -216,7 +238,7 @@ static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
if (msir->gic_irq > 0)
irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
- for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
+ for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
hwirq = i << msi_data->cfg->ibs_shift | msir->index;
bitmap_set(msi_data->used, hwirq, 1);
}
@@ -226,15 +248,26 @@ static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
.ibs_shift = 3,
+ .msir_irqs = MSI_IRQS_PER_MSIR,
+ .msir_base = MSI_MSIR_OFFSET,
};
static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
.ibs_shift = 2,
+ .msir_irqs = MSI_IRQS_PER_MSIR,
+ .msir_base = MSI_MSIR_OFFSET,
+};
+
+static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
+ .ibs_shift = 2,
+ .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
+ .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
};
static const struct of_device_id ls_scfg_msi_id[] = {
{ .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
{ .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
+ { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
{ .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
{},
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2,9/9] irqchip/ls-scfg-msi: add MSI affinity support
From: Minghuan Lian @ 2017-01-05 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483603837-4629-1-git-send-email-Minghuan.Lian@nxp.com>
For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4
CPUs. A GIC SPI interrupt of MSIR can be associated with a CPU.
When changing MSI interrupt affinity, this MSI will be moved to the
corresponding MSIR and MSI message data will be changed according to
MSIR. when requesting a MSI, the bits of all 4 MSIR will be reserved.
The parameter 'msi_affinity_flag' is provide to change this mode.
"lsmsi=no-affinity" will disable affinity, all MSI can only be
associated with CPU 0.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
v2-v1:
- None
drivers/irqchip/irq-ls-scfg-msi.c | 75 ++++++++++++++++++++++++++++++++++++---
1 file changed, 70 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index dc19569..753fe39 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -40,6 +40,7 @@ struct ls_scfg_msir {
unsigned int gic_irq;
unsigned int bit_start;
unsigned int bit_end;
+ unsigned int srs; /* Shared interrupt register select */
void __iomem *reg;
};
@@ -70,6 +71,19 @@ struct ls_scfg_msi {
.chip = &ls_scfg_msi_irq_chip,
};
+static int msi_affinity_flag = 1;
+
+static int __init early_parse_ls_scfg_msi(char *p)
+{
+ if (p && strncmp(p, "no-affinity", 11) == 0)
+ msi_affinity_flag = 0;
+ else
+ msi_affinity_flag = 1;
+
+ return 0;
+}
+early_param("lsmsi", early_parse_ls_scfg_msi);
+
static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
@@ -77,12 +91,43 @@ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
msg->address_hi = upper_32_bits(msi_data->msiir_addr);
msg->address_lo = lower_32_bits(msi_data->msiir_addr);
msg->data = data->hwirq;
+
+ if (msi_affinity_flag) {
+ u32 msir_index;
+
+ msir_index = cpumask_first(data->common->affinity);
+ if (msir_index >= msi_data->msir_num)
+ msir_index = 0;
+
+ msg->data |= msir_index;
+ }
}
static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
const struct cpumask *mask, bool force)
{
- return -EINVAL;
+ struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
+ u32 cpu;
+
+ if (!msi_affinity_flag)
+ return -EINVAL;
+
+ if (!force)
+ cpu = cpumask_any_and(mask, cpu_online_mask);
+ else
+ cpu = cpumask_first(mask);
+
+ if (cpu >= msi_data->msir_num)
+ return -EINVAL;
+
+ if (msi_data->msir[cpu].gic_irq <= 0) {
+ pr_warn("cannot bind the irq to cpu%d\n", cpu);
+ return -EINVAL;
+ }
+
+ cpumask_copy(irq_data->common->affinity, mask);
+
+ return IRQ_SET_MASK_OK;
}
static struct irq_chip ls_scfg_msi_parent_chip = {
@@ -158,7 +203,7 @@ static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
for_each_set_bit_from(pos, &val, size) {
hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
- msir->index;
+ msir->srs;
virq = irq_find_mapping(msi_data->parent, hwirq);
if (virq)
generic_handle_irq(virq);
@@ -221,10 +266,19 @@ static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
ls_scfg_msi_irq_handler,
msir);
+ if (msi_affinity_flag) {
+ /* Associate MSIR interrupt to the cpu */
+ irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
+ msir->srs = 0; /* This value is determined by the CPU */
+ } else
+ msir->srs = index;
+
/* Release the hwirqs corresponding to this MSIR */
- for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
- hwirq = i << msi_data->cfg->ibs_shift | msir->index;
- bitmap_clear(msi_data->used, hwirq, 1);
+ if (!msi_affinity_flag || msir->index == 0) {
+ for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
+ hwirq = i << msi_data->cfg->ibs_shift | msir->index;
+ bitmap_clear(msi_data->used, hwirq, 1);
+ }
}
return 0;
@@ -316,6 +370,17 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
bitmap_set(msi_data->used, 0, msi_data->irqs_num);
msi_data->msir_num = of_irq_count(pdev->dev.of_node);
+
+ if (msi_affinity_flag) {
+ u32 cpu_num;
+
+ cpu_num = num_possible_cpus();
+ if (msi_data->msir_num >= cpu_num)
+ msi_data->msir_num = cpu_num;
+ else
+ msi_affinity_flag = 0;
+ }
+
msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
sizeof(*msi_data->msir),
GFP_KERNEL);
--
1.9.1
^ permalink raw reply related
* [PATCH 05/22] ARM: dtsi: axp209: add AXP209 ADC subnode
From: Chen-Yu Tsai @ 2017-01-05 8:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1ddf7012-3336-84c2-6392-353b01beea93@free-electrons.com>
On Thu, Jan 5, 2017 at 4:08 PM, Quentin Schulz
<quentin.schulz@free-electrons.com> wrote:
> On 05/01/2017 06:51, Chen-Yu Tsai wrote:
>> On Tue, Jan 3, 2017 at 12:37 AM, Quentin Schulz
>> <quentin.schulz@free-electrons.com> wrote:
>>> X-Powers AXP209 PMIC has multiple ADCs, each one exposing data from the
>>> different power supplies connected to the PMIC.
>>>
>>> This adds the ADC subnode for AXP20X PMIC.
>>>
>>> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
>>> ---
>>> arch/arm/boot/dts/axp209.dtsi | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
>>> index 675bb0f..2a4e8ee 100644
>>> --- a/arch/arm/boot/dts/axp209.dtsi
>>> +++ b/arch/arm/boot/dts/axp209.dtsi
>>> @@ -53,6 +53,11 @@
>>> interrupt-controller;
>>> #interrupt-cells = <1>;
>>>
>>> + axp209_adc: axp209_adc {
>>
>> Node name should be generic. Please change it to "adc".
>>
>
> OK, do I keep the label as is?
>
> axp209_adc: adc {
Yup. The label is for dereferencing and stuff, and exists in a global scope.
You wouldn't want 2 label names clashing.
ChenYu
>
> Thanks,
> Quentin
>
> --
> Quentin Schulz, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* [PATCH v6 08/14] ACPI: ARM64: IORT: rework iort_node_get_id()
From: Hanjun Guo @ 2017-01-05 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104175822.GD8604@red-moon>
Hi Lorenzo,
On 2017/1/5 1:58, Lorenzo Pieralisi wrote:
> On Mon, Jan 02, 2017 at 09:31:39PM +0800, Hanjun Guo wrote:
>> iort_node_get_id() has two output, one is the mapped ids,
>> the other is the referenced parent node which is returned
>> from the function.
>>
>> For now we need a API just return its parent node for
>> single mapping, so just update this function slightly then
>> reuse it later.
>
> I think we need to fix iort_node_get_id() first though, I am referring
> to the index usage in relation to acpi_iort_id_mapping.output_reference
> and related parent pointer retrieval as you reported to me, I am happy
> to send it upstream independently.
Sure, please.
>
> As for this patch it is ok even though we can create an API that
> just retrieve a node parent without fiddling about with passing
> a NULL pointer for the id_out to achieve the same.
Since you commented "[PATCH v6 05/14] ACPI: platform-msi: retrieve dev
id from IORT" which also refer to this API, I will reply in that
email.
Thanks
Hanjun
^ permalink raw reply
* [PATCH v2 2/4] serial: 8250: Add new port type for TI DA8xx/OMAPL13x/AM17xx/AM18xx/C66x
From: Sekhar Nori @ 2017-01-05 8:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483561814-21953-3-git-send-email-david@lechnology.com>
On Thursday 05 January 2017 02:00 AM, David Lechner wrote:
> This adds a new UART port type for TI DA8xx/OMAPL13x/AM17xx/AM18xx/C66x.
The Keystone2 processors do include the C66x DSP. But the SoCs being
targeted with this patch are the ARM + DSP variants. Using 66AK2x is
more appropriate.
http://www.ti.com/lsds/ti/processors/dsp/c6000_dsp-arm/66ak2x/overview.page
Also, DA8xx includes DA830 which is pin-compatible with AM17x. So you
can shorten the list of supported processors to DA8xx/66AK2x.
> These SoCs have standard 8250 registers plus some extra non-standard
> registers.
>
> The UART will not function unless the non-standard Power and Emulation
> Management Register (PWREMU_MGMT) is configured correctly. This is
> currently handled in arch/arm/mach-davinci/serial.c for non-device-tree
> boards. Making this part of the UART driver will allow UART to work on
> device-tree boards as well and the mach code can eventually be removed.
>
> Signed-off-by: David Lechner <david@lechnology.com>
Looks good to me, apart from the minor change above.
Acked-by: Sekhar Nori <nsekhar@ti.com>
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v3 2/2] dt-bindings: Add DT bindings info for FlexRM ring manager
From: Anup Patel @ 2017-01-05 8:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170104143752.bl47gdfczbnfy6b3@rob-hp-laptop>
On Wed, Jan 4, 2017 at 8:07 PM, Rob Herring <robh@kernel.org> wrote:
> On Wed, Jan 04, 2017 at 11:04:42AM +0530, Anup Patel wrote:
>> This patch adds device tree bindings document for the FlexRM
>> ring manager found on Broadcom iProc SoCs.
>>
>> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
>> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
>> Signed-off-by: Anup Patel <anup.patel@broadcom.com>
>> ---
>> .../bindings/mailbox/brcm,iproc-flexrm-mbox.txt | 60 ++++++++++++++++++++++
>> 1 file changed, 60 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt
>> new file mode 100644
>> index 0000000..ca51a39
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt
>> @@ -0,0 +1,60 @@
>> +Broadcom FlexRM Ring Manager
>> +============================
>> +The Broadcom FlexRM ring manager provides a set of rings which can be
>> +used to submit work to offload engines. An SoC may have multiple FlexRM
>> +hardware blocks. There is one device tree entry per FlexRM block. The
>> +FlexRM driver will create a mailbox-controller instance for given FlexRM
>> +hardware block where each mailbox channel is a separate FlexRM ring.
>> +
>> +Required properties:
>> +--------------------
>> +- compatible: Should be "brcm,iproc-flexrm-mbox"
>> +- reg: Specifies base physical address and size of the FlexRM
>> + ring registers
>> +- msi-parent: Phandles (and potential Device IDs) to MSI controllers
>> + The FlexRM engine will send MSIs (instead of wired
>> + interrupts) to CPU. There is one MSI for each FlexRM ring.
>> + Refer devicetree/bindings/interrupt-controller/msi.txt
>> +- #mbox-cells: Specifies the number of cells needed to encode a mailbox
>> + channel. This should be 3.
>> +
>> + The 1st cell is the mailbox channel number.
>> +
>> + The 2nd cell contains MSI completion threshold. This is the
>> + number of completion messages for which FlexRM will inject
>> + one MSI interrupt to CPU.
>> +
>> + The 3nd cell contains MSI timer value representing time for
>> + which FlexRM will wait to accumulate N completion messages
>> + where N is the value specified by 2nd cell above. If FlexRM
>> + does not get required number of completion messages in time
>> + specified by this cell then it will inject one MSI interrupt
>> + to CPU provided atleast one completion message is available.
>> +
>> +Optional properties:
>> +--------------------
>> +- dma-coherent: Present if DMA operations made by the FlexRM engine (such
>> + as DMA descriptor access, access to buffers pointed by DMA
>> + descriptors and read/write pointer updates to DDR) are
>> + cache coherent with the CPU.
>> +
>> +Example:
>> +--------
>> +crypto_mbox: mbox at 67000000 {
>> + compatible = "brcm,iproc-flexrm-mbox";
>> + reg = <0x67000000 0x200000>;
>> + msi-parent = <&gic_its 0x7f00>;
>> + #mbox-cells = <3>;
>> +};
>> +
>> +crypto_client {
>
> crypto@<addr>
>
>> + ...
>> + mboxes = <&crypto_mbox 0 0x1 0xffff>,
>> + <&crypto_mbox 1 0x1 0xffff>,
>> + <&crypto_mbox 16 0x1 0xffff>,
>> + <&crypto_mbox 17 0x1 0xffff>,
>> + <&crypto_mbox 30 0x1 0xffff>,
>> + <&crypto_mbox 31 0x1 0xffff>;
>> + };
>> + ...
>
> Please somewhat fully list the contents for node.
>
Sure, I will add more complete example DT node for
mailbox client.
Regards,
Anup
^ permalink raw reply
* [PATCH v2 0/4] Add touch key driver support for TM2
From: Jaechul Lee @ 2017-01-05 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CGME20170105082715epcas1p10e0820a792ba9d89cd165299d6602654@epcas1p1.samsung.com>
Hi,
This patchset adds support for the tm2 touchkey device.
The driver has been ported from Tizen Kernel, originally written
by Beomho. I ported it to the latest mainline Kernel.
The patchset applies on next-20170105.
Changes in v2:
- fixed reviews from Javier, Dmitry
- refactored power enable/disable functions.
- reordered signed-offs in patch 2, while patch 4 is left as it
was as Andi copy pasted the node to the new tm2.dts file
- added Jarvier's (patch 1,2,4) and Krzysztof's (patch 4) reviews
and Rob's Ack
- patch 3 diff has been generated with -B50%
Best Regards,
Jaechul
Andi Shyti (1):
arm64: dts: exynos: make tm2 and tm2e independent from each other
Jaechul Lee (3):
input: Add support for the tm2 touchkey device driver
input: tm2-touchkey: Add touchkey driver support for TM2
arm64: dts: exynos: Add tm2 touchkey node
.../bindings/input/samsung,tm2-touchkey.txt | 27 +
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1116 ++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1105 +------------------
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
drivers/input/keyboard/Kconfig | 11 +
drivers/input/keyboard/Makefile | 1 +
drivers/input/keyboard/tm2-touchkey.c | 280 +++++
7 files changed, 1445 insertions(+), 1097 deletions(-)
create mode 100644 Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
create mode 100644 drivers/input/keyboard/tm2-touchkey.c
--
2.7.4
^ permalink raw reply
* [PATCH v2 1/4] input: Add support for the tm2 touchkey device driver
From: Jaechul Lee @ 2017-01-05 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483604833-29746-1-git-send-email-jcsing.lee@samsung.com>
This patch adds the binding description of the tm2 touchkey
device driver.
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/input/samsung,tm2-touchkey.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
diff --git a/Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt b/Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
new file mode 100644
index 0000000..4de1af0
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
@@ -0,0 +1,27 @@
+Samsung tm2-touchkey
+
+Required properties:
+- compatible: must be "samsung,tm2-touchkey"
+- reg: I2C address of the chip.
+- interrupt-parent: a phandle for the interrupt controller (see interrupt
+ binding[0]).
+- interrupts: interrupt to which the chip is connected (see interrupt
+ binding[0]).
+- vcc-supply : internal regulator output. 1.8V
+- vdd-supply : power supply for IC 3.3V
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+Example:
+ &i2c0 {
+ /* ... */
+
+ touchkey at 20 {
+ compatible = "samsung,tm2-touchkey";
+ reg = <0x20>;
+ interrupt-parent = <&gpa3>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply=<&ldo32_reg>;
+ vdd-supply=<&ldo33_reg>;
+ };
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/4] input: tm2-touchkey: Add touchkey driver support for TM2
From: Jaechul Lee @ 2017-01-05 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483604833-29746-1-git-send-email-jcsing.lee@samsung.com>
This patch adds support for the TM2 touch key and led
functionality.
The driver interfaces with userspace through an input device and
reports KEY_PHONE and KEY_BACK event types. LED brightness can be
controlled by "/sys/class/leds/tm2-touchkey/brightness".
Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
---
drivers/input/keyboard/Kconfig | 11 ++
drivers/input/keyboard/Makefile | 1 +
drivers/input/keyboard/tm2-touchkey.c | 280 ++++++++++++++++++++++++++++++++++
3 files changed, 292 insertions(+)
create mode 100644 drivers/input/keyboard/tm2-touchkey.c
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index cbd75cf..e6e9858 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -666,6 +666,17 @@ config KEYBOARD_TC3589X
To compile this driver as a module, choose M here: the
module will be called tc3589x-keypad.
+config KEYBOARD_TM2_TOUCHKEY
+ tristate "tm2-touchkey support"
+ depends on I2C
+ depends on LEDS_CLASS
+ help
+ Say Y here to enable device driver for tm2-touchkey with
+ LED control for the Exynos5433 TM2 board.
+
+ To compile this driver as a module, choose M here.
+ module will be called tm2-touchkey.
+
config KEYBOARD_TWL4030
tristate "TI TWL4030/TWL5030/TPS659x0 keypad support"
depends on TWL4030_CORE
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index d9f4cfc..7d9acff 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_KEYBOARD_SUN4I_LRADC) += sun4i-lradc-keys.o
obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o
obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
+obj-$(CONFIG_KEYBOARD_TM2_TOUCHKEY) += tm2-touchkey.o
obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o
obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o
obj-$(CONFIG_KEYBOARD_W90P910) += w90p910_keypad.o
diff --git a/drivers/input/keyboard/tm2-touchkey.c b/drivers/input/keyboard/tm2-touchkey.c
new file mode 100644
index 0000000..92eacb6
--- /dev/null
+++ b/drivers/input/keyboard/tm2-touchkey.c
@@ -0,0 +1,280 @@
+/*
+ * TM2 touchkey device driver
+ *
+ * Copyright 2005 Phil Blundell
+ * Copyright 2016 Samsung Electronics Co., Ltd.
+ *
+ * Author: Beomho Seo <beomho.seo@samsung.com>
+ * Author: Jaechul Lee <jcsing.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/leds.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pm.h>
+#include <linux/regulator/consumer.h>
+
+#define TM2_TOUCHKEY_DEV_NAME "tm2-touchkey"
+#define TM2_TOUCHKEY_KEYCODE_REG 0x03
+#define TM2_TOUCHKEY_BASE_REG 0x00
+#define TM2_TOUCHKEY_CMD_LED_ON 0x10
+#define TM2_TOUCHKEY_CMD_LED_OFF 0x20
+#define TM2_TOUCHKEY_BIT_PRESS_EV BIT(3)
+#define TM2_TOUCHKEY_BIT_KEYCODE GENMASK(2, 0)
+#define TM2_TOUCHKEY_LED_VOLTAGE_MIN 2500000
+#define TM2_TOUCHKEY_LED_VOLTAGE_MAX 3300000
+
+enum {
+ TM2_TOUCHKEY_KEY_MENU = 0x1,
+ TM2_TOUCHKEY_KEY_BACK,
+};
+
+struct tm2_touchkey_data {
+ struct i2c_client *client;
+ struct input_dev *input_dev;
+ struct led_classdev led_dev;
+ struct regulator_bulk_data regulators[2];
+
+ u8 keycode_type;
+ u8 pressed;
+};
+
+static void tm2_touchkey_led_brightness_set(struct led_classdev *led_dev,
+ enum led_brightness brightness)
+{
+ struct tm2_touchkey_data *touchkey =
+ container_of(led_dev, struct tm2_touchkey_data, led_dev);
+ u32 volt;
+ u8 data;
+
+ if (brightness == LED_OFF) {
+ volt = TM2_TOUCHKEY_LED_VOLTAGE_MIN;
+ data = TM2_TOUCHKEY_CMD_LED_OFF;
+ } else {
+ volt = TM2_TOUCHKEY_LED_VOLTAGE_MAX;
+ data = TM2_TOUCHKEY_CMD_LED_ON;
+ }
+
+ regulator_set_voltage(touchkey->regulators[1].consumer, volt, volt);
+ i2c_smbus_write_byte_data(touchkey->client,
+ TM2_TOUCHKEY_BASE_REG, data);
+}
+
+static int tm2_touchkey_power_enable(struct tm2_touchkey_data *touchkey)
+{
+ int ret = 0;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(touchkey->regulators),
+ touchkey->regulators);
+ if (ret)
+ return ret;
+
+ /* waiting for device initialization, at least 150ms */
+ msleep(150);
+
+ return 0;
+}
+
+static void tm2_touchkey_power_disable(void *data)
+{
+ struct tm2_touchkey_data *touchkey = data;
+
+ regulator_bulk_disable(ARRAY_SIZE(touchkey->regulators),
+ touchkey->regulators);
+}
+
+static irqreturn_t tm2_touchkey_irq_handler(int irq, void *devid)
+{
+ struct tm2_touchkey_data *touchkey = devid;
+ u32 data;
+
+ data = i2c_smbus_read_byte_data(touchkey->client,
+ TM2_TOUCHKEY_KEYCODE_REG);
+
+ if (data < 0) {
+ dev_err(&touchkey->client->dev, "Failed to read i2c data\n");
+ return IRQ_HANDLED;
+ }
+
+ touchkey->keycode_type = data & TM2_TOUCHKEY_BIT_KEYCODE;
+ touchkey->pressed = !(data & TM2_TOUCHKEY_BIT_PRESS_EV);
+
+ if (touchkey->keycode_type != TM2_TOUCHKEY_KEY_MENU &&
+ touchkey->keycode_type != TM2_TOUCHKEY_KEY_BACK) {
+ dev_warn(&touchkey->client->dev, "Skip unhandled keycode(%d)\n",
+ touchkey->keycode_type);
+ return IRQ_HANDLED;
+ }
+
+ if (!touchkey->pressed) {
+ input_report_key(touchkey->input_dev, KEY_PHONE, 0);
+ input_report_key(touchkey->input_dev, KEY_BACK, 0);
+ } else {
+ if (touchkey->keycode_type == TM2_TOUCHKEY_KEY_MENU)
+ input_report_key(touchkey->input_dev,
+ KEY_PHONE, 1);
+ else
+ input_report_key(touchkey->input_dev,
+ KEY_BACK, 1);
+ }
+ input_sync(touchkey->input_dev);
+
+ return IRQ_HANDLED;
+}
+
+static int tm2_touchkey_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct tm2_touchkey_data *touchkey;
+ int ret;
+
+ ret = i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE |
+ I2C_FUNC_SMBUS_BYTE_DATA);
+ if (!ret) {
+ dev_err(&client->dev, "No I2C functionality found\n");
+ return -ENODEV;
+ }
+
+ touchkey = devm_kzalloc(&client->dev, sizeof(*touchkey), GFP_KERNEL);
+ if (!touchkey)
+ return -ENOMEM;
+
+ touchkey->client = client;
+ i2c_set_clientdata(client, touchkey);
+
+ /* regulators */
+ touchkey->regulators[0].supply = "vcc";
+ touchkey->regulators[1].supply = "vdd";
+ ret = devm_regulator_bulk_get(&client->dev,
+ ARRAY_SIZE(touchkey->regulators),
+ touchkey->regulators);
+ if (ret) {
+ dev_err(&client->dev, "Failed to get regulators\n");
+ return ret;
+ }
+
+ /* power */
+ ret = tm2_touchkey_power_enable(touchkey);
+ if (ret) {
+ dev_err(&client->dev, "Failed to enable power\n");
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(&client->dev,
+ tm2_touchkey_power_disable, touchkey);
+ if (ret)
+ return ret;
+
+ /* input device */
+ touchkey->input_dev = devm_input_allocate_device(&client->dev);
+ if (!touchkey->input_dev) {
+ dev_err(&client->dev, "Failed to alloc input device\n");
+ return -ENOMEM;
+ }
+ touchkey->input_dev->name = TM2_TOUCHKEY_DEV_NAME;
+ touchkey->input_dev->id.bustype = BUS_I2C;
+
+ set_bit(EV_KEY, touchkey->input_dev->evbit);
+ input_set_capability(touchkey->input_dev, EV_KEY, KEY_PHONE);
+ input_set_capability(touchkey->input_dev, EV_KEY, KEY_BACK);
+
+ input_set_drvdata(touchkey->input_dev, touchkey);
+
+ ret = input_register_device(touchkey->input_dev);
+ if (ret) {
+ dev_err(&client->dev, "Failed to register input device\n");
+ return ret;
+ }
+
+ /* irq */
+ ret = devm_request_threaded_irq(&client->dev,
+ client->irq, NULL,
+ tm2_touchkey_irq_handler,
+ IRQF_ONESHOT, TM2_TOUCHKEY_DEV_NAME,
+ touchkey);
+ if (ret) {
+ dev_err(&client->dev, "Failed to request threaded irq\n");
+ return ret;
+ }
+
+ /* led device */
+ touchkey->led_dev.name = TM2_TOUCHKEY_DEV_NAME;
+ touchkey->led_dev.brightness = LED_FULL;
+ touchkey->led_dev.max_brightness = LED_FULL;
+ touchkey->led_dev.brightness_set = tm2_touchkey_led_brightness_set;
+
+ ret = devm_led_classdev_register(&client->dev, &touchkey->led_dev);
+ if (ret < 0) {
+ dev_err(&client->dev, "Failed to register touchkey led\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __maybe_unused tm2_touchkey_suspend(struct device *dev)
+{
+ struct tm2_touchkey_data *touchkey = dev_get_drvdata(dev);
+
+ disable_irq(touchkey->client->irq);
+ tm2_touchkey_power_disable(touchkey);
+
+ return 0;
+}
+
+static int __maybe_unused tm2_touchkey_resume(struct device *dev)
+{
+ struct tm2_touchkey_data *touchkey = dev_get_drvdata(dev);
+ int ret;
+
+ enable_irq(touchkey->client->irq);
+ ret = tm2_touchkey_power_enable(touchkey);
+ if (ret)
+ dev_err(dev, "Failed to enable power\n");
+
+ return ret;
+}
+
+static SIMPLE_DEV_PM_OPS(tm2_touchkey_pm_ops, tm2_touchkey_suspend,
+ tm2_touchkey_resume);
+
+static const struct i2c_device_id tm2_touchkey_id_table[] = {
+ {TM2_TOUCHKEY_DEV_NAME, 0},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, tm2_touchkey_id_table);
+
+static const struct of_device_id tm2_touchkey_of_match[] = {
+ {.compatible = "samsung,tm2-touchkey",},
+ {},
+};
+MODULE_DEVICE_TABLE(of, tm2_touchkey_of_match);
+
+static struct i2c_driver tm2_touchkey_driver = {
+ .driver = {
+ .name = TM2_TOUCHKEY_DEV_NAME,
+ .pm = &tm2_touchkey_pm_ops,
+ .of_match_table = of_match_ptr(tm2_touchkey_of_match),
+ },
+ .probe = tm2_touchkey_probe,
+ .id_table = tm2_touchkey_id_table,
+};
+
+module_i2c_driver(tm2_touchkey_driver);
+
+MODULE_AUTHOR("Beomho Seo <beomho.seo@samsung.com>");
+MODULE_AUTHOR("Jaechul Lee <jcsing.lee@samsung.com>");
+MODULE_DESCRIPTION("Samsung touchkey driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [PATCH v2 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Jaechul Lee @ 2017-01-05 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483604833-29746-1-git-send-email-jcsing.lee@samsung.com>
From: Andi Shyti <andi.shyti@samsung.com>
Currently tm2e dts includes tm2 but there are some differences
between the two boards and tm2 has some properties that tm2e
doesn't have.
That's why it's important to keep the two dts files independent
and put all the commonalities in a tm2-common.dtsi file.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
---
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1116 +++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1138 +-------------------
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
3 files changed, 1136 insertions(+), 1120 deletions(-)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
rewrite arch/arm64/boot/dts/exynos/exynos5433-tm2.dts (98%)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
new file mode 100644
index 0000000..7ad0019
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -0,0 +1,1116 @@
+/*
+ * SAMSUNG Exynos5433 TM2 board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *
+ * Device tree source file for Samsung's TM2 board which is based on
+ * Samsung Exynos5433 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos5433.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ gsc0 = &gsc_0;
+ gsc1 = &gsc_1;
+ gsc2 = &gsc_2;
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_aud;
+ pinctrl2 = &pinctrl_cpif;
+ pinctrl3 = &pinctrl_ese;
+ pinctrl4 = &pinctrl_finger;
+ pinctrl5 = &pinctrl_fsys;
+ pinctrl6 = &pinctrl_imem;
+ pinctrl7 = &pinctrl_nfc;
+ pinctrl8 = &pinctrl_peric;
+ pinctrl9 = &pinctrl_touch;
+ serial0 = &serial_0;
+ serial1 = &serial_1;
+ serial2 = &serial_2;
+ serial3 = &serial_3;
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ spi3 = &spi_3;
+ spi4 = &spi_4;
+ mshc0 = &mshc_0;
+ mshc2 = &mshc_2;
+ };
+
+ chosen {
+ stdout-path = &serial_1;
+ };
+
+ memory at 20000000 {
+ device_type = "memory";
+ reg = <0x0 0x20000000 0x0 0xc0000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power-key {
+ gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ label = "power key";
+ debounce-interval = <10>;
+ };
+
+ volume-up-key {
+ gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ label = "volume-up key";
+ debounce-interval = <10>;
+ };
+
+ volume-down-key {
+ gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ label = "volume-down key";
+ debounce-interval = <10>;
+ };
+
+ homepage-key {
+ gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MENU>;
+ label = "homepage key";
+ debounce-interval = <10>;
+ };
+ };
+
+ i2c_max98504: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
+ &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ max98504: max98504 at 31 {
+ compatible = "maxim,max98504";
+ reg = <0x31>;
+ maxim,rx-path = <1>;
+ maxim,tx-path = <1>;
+ maxim,tx-channel-mask = <3>;
+ maxim,tx-channel-source = <2>;
+ };
+ };
+
+ sound {
+ compatible = "samsung,tm2-audio";
+ audio-codec = <&wm5110>;
+ i2s-controller = <&i2s0>;
+ audio-amplifier = <&max98504>;
+ mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
+ model = "wm5110";
+ samsung,audio-routing =
+ /* Headphone */
+ "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+
+ /* Speaker */
+ "SPK", "SPKOUT",
+ "SPKOUT", "HPOUT2L",
+ "SPKOUT", "HPOUT2R",
+
+ /* Receiver */
+ "RCV", "HPOUT3L",
+ "RCV", "HPOUT3R";
+ status = "okay";
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo3_reg>;
+ status = "okay";
+
+ thermistor-ap {
+ compatible = "murata,ncp03wf104";
+ pullup-uv = <1800000>;
+ pullup-ohm = <100000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 0>;
+ };
+
+ thermistor-battery {
+ compatible = "murata,ncp03wf104";
+ pullup-uv = <1800000>;
+ pullup-ohm = <100000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 1>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermistor-charger {
+ compatible = "murata,ncp03wf104";
+ pullup-uv = <1800000>;
+ pullup-ohm = <100000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 2>;
+ };
+};
+
+&bus_g2d_400 {
+ devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
+ vdd-supply = <&buck4_reg>;
+ exynos,saturation-ratio = <10>;
+ status = "okay";
+};
+
+&bus_g2d_266 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_gscl {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_hevc {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_jpeg {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_mscl {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_noc0 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_noc1 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_noc2 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&cmu_aud {
+ assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
+ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
+};
+
+&cmu_fsys {
+ assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
+ <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
+ <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
+ <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
+ <&cmu_top CLK_DIV_SCLK_USBDRD30>,
+ <&cmu_top CLK_DIV_SCLK_USBHOST30>;
+ assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>,
+ <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
+ <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
+ assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+ <66700000>, <66700000>;
+};
+
+&cmu_gscl {
+ assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
+ <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
+ assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
+ <&cmu_top CLK_ACLK_GSCL_333>;
+};
+
+&cmu_mfc {
+ assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
+ assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
+};
+
+&cmu_mscl {
+ assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
+ <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
+ <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
+ <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
+ assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
+ <&cmu_top CLK_SCLK_JPEG_MSCL>,
+ <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>;
+};
+
+&cpu0 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&decon {
+ status = "okay";
+
+ i80-if-timings {
+ };
+};
+
+&dsi {
+ status = "okay";
+ vddcore-supply = <&ldo6_reg>;
+ vddio-supply = <&ldo7_reg>;
+ samsung,pll-clock-frequency = <24000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&te_irq>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ reg = <1>;
+
+ dsi_out: endpoint {
+ samsung,burst-clock-frequency = <512000000>;
+ samsung,esc-clock-frequency = <16000000>;
+ };
+ };
+ };
+};
+
+&hsi2c_0 {
+ status = "okay";
+ clock-frequency = <2500000>;
+
+ s2mps13-pmic at 66 {
+ compatible = "samsung,s2mps13-pmic";
+ interrupt-parent = <&gpa0>;
+ interrupts = <7 IRQ_TYPE_NONE>;
+ reg = <0x66>;
+ samsung,s2mps11-wrstbi-ground;
+
+ s2mps13_osc: clocks {
+ compatible = "samsung,s2mps13-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps13_ap", "s2mps13_cp",
+ "s2mps13_bt";
+ };
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE_0.9V_AP";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_MMC2_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VDD1_E_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDD10_MIF_PLL_1.0V_AP";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDD10_DPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VDD10_MIPI2L_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VDD18_MIPI2L_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD18_LLI_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "VDD18_ABB_ETC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD33_USB30_3.0V_AP";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD_INT_M_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD_KFC_M_1.1V_AP";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDD_G3D_M_0.95V_AP";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDDQ_M1_LDO_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDDQ_M2_LDO_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDDQ_EFUSE";
+ regulator-min-microvolt = <1400000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "V_TFLASH_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-name = "V_CODEC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VDDA_1.8V_COMP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "CAM_IO_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "CAM_SEN_CORE_1.2V_AP";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VT_CAM_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "CAM_SEN_A2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "CAM_AF_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "VCC_3.0V_LCD_AP";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "VCC_1.8V_LCD_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo29_reg: LDO29 {
+ regulator-name = "VT_CAM_2.8V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo30_reg: LDO30 {
+ regulator-name = "TSP_AVDD_3.3V_AP";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo31_reg: LDO31 {
+ regulator-name = "TSP_VDD_1.85V_AP";
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ ldo32_reg: LDO32 {
+ regulator-name = "VTOUCH_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo33_reg: LDO33 {
+ regulator-name = "VTOUCH_LED_3.3V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ };
+
+ ldo34_reg: LDO34 {
+ regulator-name = "VCC_1.8V_MHL_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ ldo35_reg: LDO35 {
+ regulator-name = "OIS_VM_2.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo36_reg: LDO36 {
+ regulator-name = "VSIL_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo37_reg: LDO37 {
+ regulator-name = "VF_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo38_reg: LDO38 {
+ regulator-name = "VCC_3.0V_MOTOR_AP";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo39_reg: LDO39 {
+ regulator-name = "V_HRM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo40_reg: LDO40 {
+ regulator-name = "V_HRM_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "VDD_MIF_0.9V_AP";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "VDD_EGL_1.0V_AP";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "VDD_KFC_1.0V_AP";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "VDD_INT_0.95V_AP";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VDD_DISP_CAM0_0.9V_AP";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "VDD_G3D_0.9V_AP";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "VDD_MEM1_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "VDD_LLDO_1.35V_AP";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "VDD_MLDO_2.0V_AP";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ buck10_reg: BUCK10 {
+ regulator-name = "vdd_mem2";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&hsi2c_8 {
+ status = "okay";
+
+ max77843 at 66 {
+ compatible = "maxim,max77843";
+ interrupt-parent = <&gpa1>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0x66>;
+
+ muic: max77843-muic {
+ compatible = "maxim,max77843-muic";
+ };
+
+ regulators {
+ compatible = "maxim,max77843-regulator";
+ safeout1_reg: SAFEOUT1 {
+ regulator-name = "SAFEOUT1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <4950000>;
+ };
+
+ safeout2_reg: SAFEOUT2 {
+ regulator-name = "SAFEOUT2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <4950000>;
+ };
+
+ charger_reg: CHARGER {
+ regulator-name = "CHARGER";
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <3150000>;
+ };
+ };
+
+ haptic: max77843-haptic {
+ compatible = "maxim,max77843-haptic";
+ haptic-supply = <&ldo38_reg>;
+ pwms = <&pwm 0 33670 0>;
+ pwm-names = "haptic";
+ };
+ };
+};
+
+&i2s0 {
+ status = "okay";
+};
+
+&mshc_0 {
+ status = "okay";
+ num-slots = <1>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-highspeed;
+ non-removable;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ samsung,dw-mshc-hs400-timing = <0 3>;
+ samsung,read-strobe-delay = <90>;
+ fifo-depth = <0x80>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
+ &sd0_bus8 &sd0_rdqs>;
+ bus-width = <8>;
+ assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
+ assigned-clock-rates = <800000000>;
+};
+
+&mshc_2 {
+ status = "okay";
+ num-slots = <1>;
+ cap-sd-highspeed;
+ disable-wp;
+ cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ fifo-depth = <0x80>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+};
+
+&ppmu_d0_general {
+ status = "okay";
+ events {
+ ppmu_event0_d0_general: ppmu-event0-d0-general {
+ event-name = "ppmu-event0-d0-general";
+ };
+ };
+};
+
+&ppmu_d1_general {
+ status = "okay";
+ events {
+ ppmu_event0_d1_general: ppmu-event0-d1-general {
+ event-name = "ppmu-event0-d1-general";
+ };
+ };
+};
+
+&pinctrl_alive {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_alive>;
+
+ initial_alive: initial-state {
+ PIN(IN, gpa0-0, DOWN, LV1);
+ PIN(IN, gpa0-1, NONE, LV1);
+ PIN(IN, gpa0-2, DOWN, LV1);
+ PIN(IN, gpa0-3, NONE, LV1);
+ PIN(IN, gpa0-4, NONE, LV1);
+ PIN(IN, gpa0-5, DOWN, LV1);
+ PIN(IN, gpa0-6, NONE, LV1);
+ PIN(IN, gpa0-7, NONE, LV1);
+
+ PIN(IN, gpa1-0, UP, LV1);
+ PIN(IN, gpa1-1, NONE, LV1);
+ PIN(IN, gpa1-2, NONE, LV1);
+ PIN(IN, gpa1-3, DOWN, LV1);
+ PIN(IN, gpa1-4, DOWN, LV1);
+ PIN(IN, gpa1-5, NONE, LV1);
+ PIN(IN, gpa1-6, NONE, LV1);
+ PIN(IN, gpa1-7, NONE, LV1);
+
+ PIN(IN, gpa2-0, NONE, LV1);
+ PIN(IN, gpa2-1, NONE, LV1);
+ PIN(IN, gpa2-2, NONE, LV1);
+ PIN(IN, gpa2-3, DOWN, LV1);
+ PIN(IN, gpa2-4, NONE, LV1);
+ PIN(IN, gpa2-5, DOWN, LV1);
+ PIN(IN, gpa2-6, DOWN, LV1);
+ PIN(IN, gpa2-7, NONE, LV1);
+
+ PIN(IN, gpa3-0, DOWN, LV1);
+ PIN(IN, gpa3-1, DOWN, LV1);
+ PIN(IN, gpa3-2, NONE, LV1);
+ PIN(IN, gpa3-3, DOWN, LV1);
+ PIN(IN, gpa3-4, NONE, LV1);
+ PIN(IN, gpa3-5, DOWN, LV1);
+ PIN(IN, gpa3-6, DOWN, LV1);
+ PIN(IN, gpa3-7, DOWN, LV1);
+
+ PIN(IN, gpf1-0, NONE, LV1);
+ PIN(IN, gpf1-1, NONE, LV1);
+ PIN(IN, gpf1-2, DOWN, LV1);
+ PIN(IN, gpf1-4, UP, LV1);
+ PIN(OUT, gpf1-5, NONE, LV1);
+ PIN(IN, gpf1-6, DOWN, LV1);
+ PIN(IN, gpf1-7, DOWN, LV1);
+
+ PIN(IN, gpf2-0, DOWN, LV1);
+ PIN(IN, gpf2-1, DOWN, LV1);
+ PIN(IN, gpf2-2, DOWN, LV1);
+ PIN(IN, gpf2-3, DOWN, LV1);
+
+ PIN(IN, gpf3-0, DOWN, LV1);
+ PIN(IN, gpf3-1, DOWN, LV1);
+ PIN(IN, gpf3-2, NONE, LV1);
+ PIN(IN, gpf3-3, DOWN, LV1);
+
+ PIN(IN, gpf4-0, DOWN, LV1);
+ PIN(IN, gpf4-1, DOWN, LV1);
+ PIN(IN, gpf4-2, DOWN, LV1);
+ PIN(IN, gpf4-3, DOWN, LV1);
+ PIN(IN, gpf4-4, DOWN, LV1);
+ PIN(IN, gpf4-5, DOWN, LV1);
+ PIN(IN, gpf4-6, DOWN, LV1);
+ PIN(IN, gpf4-7, DOWN, LV1);
+
+ PIN(IN, gpf5-0, DOWN, LV1);
+ PIN(IN, gpf5-1, DOWN, LV1);
+ PIN(IN, gpf5-2, DOWN, LV1);
+ PIN(IN, gpf5-3, DOWN, LV1);
+ PIN(OUT, gpf5-4, NONE, LV1);
+ PIN(IN, gpf5-5, DOWN, LV1);
+ PIN(IN, gpf5-6, DOWN, LV1);
+ PIN(IN, gpf5-7, DOWN, LV1);
+ };
+
+ te_irq: te_irq {
+ samsung,pins = "gpf1-3";
+ samsung,pin-function = <0xf>;
+ };
+};
+
+&pinctrl_cpif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_cpif>;
+
+ initial_cpif: initial-state {
+ PIN(IN, gpv6-0, DOWN, LV1);
+ PIN(IN, gpv6-1, DOWN, LV1);
+ };
+};
+
+&pinctrl_ese {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_ese>;
+
+ initial_ese: initial-state {
+ PIN(IN, gpj2-0, DOWN, LV1);
+ PIN(IN, gpj2-1, DOWN, LV1);
+ PIN(IN, gpj2-2, DOWN, LV1);
+ };
+};
+
+&pinctrl_fsys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_fsys>;
+
+ initial_fsys: initial-state {
+ PIN(IN, gpr3-0, NONE, LV1);
+ PIN(IN, gpr3-1, DOWN, LV1);
+ PIN(IN, gpr3-2, DOWN, LV1);
+ PIN(IN, gpr3-3, DOWN, LV1);
+ PIN(IN, gpr3-7, NONE, LV1);
+ };
+};
+
+&pinctrl_imem {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_imem>;
+
+ initial_imem: initial-state {
+ PIN(IN, gpf0-0, UP, LV1);
+ PIN(IN, gpf0-1, UP, LV1);
+ PIN(IN, gpf0-2, DOWN, LV1);
+ PIN(IN, gpf0-3, UP, LV1);
+ PIN(IN, gpf0-4, DOWN, LV1);
+ PIN(IN, gpf0-5, NONE, LV1);
+ PIN(IN, gpf0-6, DOWN, LV1);
+ PIN(IN, gpf0-7, UP, LV1);
+ };
+};
+
+&pinctrl_nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_nfc>;
+
+ initial_nfc: initial-state {
+ PIN(IN, gpj0-2, DOWN, LV1);
+ };
+};
+
+&pinctrl_peric {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_peric>;
+
+ initial_peric: initial-state {
+ PIN(IN, gpv7-0, DOWN, LV1);
+ PIN(IN, gpv7-1, DOWN, LV1);
+ PIN(IN, gpv7-2, NONE, LV1);
+ PIN(IN, gpv7-3, DOWN, LV1);
+ PIN(IN, gpv7-4, DOWN, LV1);
+ PIN(IN, gpv7-5, DOWN, LV1);
+
+ PIN(IN, gpb0-4, DOWN, LV1);
+
+ PIN(IN, gpc0-2, DOWN, LV1);
+ PIN(IN, gpc0-5, DOWN, LV1);
+ PIN(IN, gpc0-7, DOWN, LV1);
+
+ PIN(IN, gpc1-1, DOWN, LV1);
+
+ PIN(IN, gpc3-4, NONE, LV1);
+ PIN(IN, gpc3-5, NONE, LV1);
+ PIN(IN, gpc3-6, NONE, LV1);
+ PIN(IN, gpc3-7, NONE, LV1);
+
+ PIN(OUT, gpg0-0, NONE, LV1);
+ PIN(FUNC1, gpg0-1, DOWN, LV1);
+
+ PIN(IN, gpd2-5, DOWN, LV1);
+
+ PIN(IN, gpd4-0, NONE, LV1);
+ PIN(IN, gpd4-1, DOWN, LV1);
+ PIN(IN, gpd4-2, DOWN, LV1);
+ PIN(IN, gpd4-3, DOWN, LV1);
+ PIN(IN, gpd4-4, DOWN, LV1);
+
+ PIN(IN, gpd6-3, DOWN, LV1);
+
+ PIN(IN, gpd8-1, UP, LV1);
+
+ PIN(IN, gpg1-0, DOWN, LV1);
+ PIN(IN, gpg1-1, DOWN, LV1);
+ PIN(IN, gpg1-2, DOWN, LV1);
+ PIN(IN, gpg1-3, DOWN, LV1);
+ PIN(IN, gpg1-4, DOWN, LV1);
+
+ PIN(IN, gpg2-0, DOWN, LV1);
+ PIN(IN, gpg2-1, DOWN, LV1);
+
+ PIN(IN, gpg3-0, DOWN, LV1);
+ PIN(IN, gpg3-1, DOWN, LV1);
+ PIN(IN, gpg3-5, DOWN, LV1);
+ PIN(IN, gpg3-7, DOWN, LV1);
+ };
+};
+
+&pinctrl_touch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&initial_touch>;
+
+ initial_touch: initial-state {
+ PIN(IN, gpj1-2, DOWN, LV1);
+ };
+};
+
+&pwm {
+ pinctrl-0 = <&pwm0_out>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mic {
+ status = "okay";
+
+ i80-if-timings {
+ };
+};
+
+&pmu_system_controller {
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&xxti>;
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&spi_1 {
+ cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ wm5110: wm5110-codec at 0 {
+ compatible = "wlf,wm5110";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ interrupt-parent = <&gpa0>;
+ interrupts = <4 IRQ_TYPE_NONE>;
+ clocks = <&pmu_system_controller 0>,
+ <&s2mps13_osc S2MPS11_CLK_BT>;
+ clock-names = "mclk1", "mclk2";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ wlf,micd-detect-debounce = <300>;
+ wlf,micd-bias-start-time = <0x1>;
+ wlf,micd-rate = <0x7>;
+ wlf,micd-dbtime = <0x1>;
+ wlf,micd-force-micbias;
+ wlf,micd-configs = <0x0 1 0>;
+ wlf,hpdet-channel = <1>;
+ wlf,gpsw = <0x1>;
+ wlf,inmode = <2 0 2 0>;
+
+ wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
+ wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
+
+ /* core supplies */
+ AVDD-supply = <&ldo18_reg>;
+ DBVDD1-supply = <&ldo18_reg>;
+ CPVDD-supply = <&ldo18_reg>;
+ DBVDD2-supply = <&ldo18_reg>;
+ DBVDD3-supply = <&ldo18_reg>;
+
+ controller-data {
+ samsung,spi-feedback-delay = <0>;
+ };
+ };
+};
+
+&timer {
+ clock-frequency = <24000000>;
+};
+
+&tmu_atlas0 {
+ vtmu-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&tmu_apollo {
+ vtmu-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&tmu_g3d {
+ vtmu-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&usbdrd30 {
+ vdd33-supply = <&ldo10_reg>;
+ vdd10-supply = <&ldo6_reg>;
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+};
+
+&usbdrd30_phy {
+ vbus-supply = <&safeout1_reg>;
+ status = "okay";
+};
+
+&xxti {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
dissimilarity index 98%
index 4e6619c..aa8584a 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -1,1119 +1,19 @@
-/*
- * SAMSUNG Exynos5433 TM2 board device tree source
- *
- * Copyright (c) 2016 Samsung Electronics Co., Ltd.
- *
- * Device tree source file for Samsung's TM2 board which is based on
- * Samsung Exynos5433 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/dts-v1/;
-#include "exynos5433.dtsi"
-#include <dt-bindings/clock/samsung,s2mps11.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "Samsung TM2 board";
- compatible = "samsung,tm2", "samsung,exynos5433";
-
- aliases {
- gsc0 = &gsc_0;
- gsc1 = &gsc_1;
- gsc2 = &gsc_2;
- pinctrl0 = &pinctrl_alive;
- pinctrl1 = &pinctrl_aud;
- pinctrl2 = &pinctrl_cpif;
- pinctrl3 = &pinctrl_ese;
- pinctrl4 = &pinctrl_finger;
- pinctrl5 = &pinctrl_fsys;
- pinctrl6 = &pinctrl_imem;
- pinctrl7 = &pinctrl_nfc;
- pinctrl8 = &pinctrl_peric;
- pinctrl9 = &pinctrl_touch;
- serial0 = &serial_0;
- serial1 = &serial_1;
- serial2 = &serial_2;
- serial3 = &serial_3;
- spi0 = &spi_0;
- spi1 = &spi_1;
- spi2 = &spi_2;
- spi3 = &spi_3;
- spi4 = &spi_4;
- mshc0 = &mshc_0;
- mshc2 = &mshc_2;
- };
-
- chosen {
- stdout-path = &serial_1;
- };
-
- memory at 20000000 {
- device_type = "memory";
- reg = <0x0 0x20000000 0x0 0xc0000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- power-key {
- gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- label = "power key";
- debounce-interval = <10>;
- };
-
- volume-up-key {
- gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- label = "volume-up key";
- debounce-interval = <10>;
- };
-
- volume-down-key {
- gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- label = "volume-down key";
- debounce-interval = <10>;
- };
-
- homepage-key {
- gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_MENU>;
- label = "homepage key";
- debounce-interval = <10>;
- };
- };
-
- i2c_max98504: i2c-gpio-0 {
- compatible = "i2c-gpio";
- gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
- &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- max98504: max98504 at 31 {
- compatible = "maxim,max98504";
- reg = <0x31>;
- maxim,rx-path = <1>;
- maxim,tx-path = <1>;
- maxim,tx-channel-mask = <3>;
- maxim,tx-channel-source = <2>;
- };
- };
-
- sound {
- compatible = "samsung,tm2-audio";
- audio-codec = <&wm5110>;
- i2s-controller = <&i2s0>;
- audio-amplifier = <&max98504>;
- mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
- model = "wm5110";
- samsung,audio-routing =
- /* Headphone */
- "HP", "HPOUT1L",
- "HP", "HPOUT1R",
-
- /* Speaker */
- "SPK", "SPKOUT",
- "SPKOUT", "HPOUT2L",
- "SPKOUT", "HPOUT2R",
-
- /* Receiver */
- "RCV", "HPOUT3L",
- "RCV", "HPOUT3R";
- status = "okay";
- };
-};
-
-&adc {
- vdd-supply = <&ldo3_reg>;
- status = "okay";
-
- thermistor-ap {
- compatible = "murata,ncp03wf104";
- pullup-uv = <1800000>;
- pullup-ohm = <100000>;
- pulldown-ohm = <0>;
- io-channels = <&adc 0>;
- };
-
- thermistor-battery {
- compatible = "murata,ncp03wf104";
- pullup-uv = <1800000>;
- pullup-ohm = <100000>;
- pulldown-ohm = <0>;
- io-channels = <&adc 1>;
- #thermal-sensor-cells = <0>;
- };
-
- thermistor-charger {
- compatible = "murata,ncp03wf104";
- pullup-uv = <1800000>;
- pullup-ohm = <100000>;
- pulldown-ohm = <0>;
- io-channels = <&adc 2>;
- };
-};
-
-&bus_g2d_400 {
- devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
- vdd-supply = <&buck4_reg>;
- exynos,saturation-ratio = <10>;
- status = "okay";
-};
-
-&bus_g2d_266 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_gscl {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_hevc {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_jpeg {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_mfc {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_mscl {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_noc0 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_noc1 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_noc2 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&cmu_aud {
- assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
- assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
-};
-
-&cmu_fsys {
- assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
- <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
- <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
- <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
- <&cmu_top CLK_DIV_SCLK_USBDRD30>,
- <&cmu_top CLK_DIV_SCLK_USBHOST30>;
- assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
- <&cmu_top CLK_MOUT_BUS_PLL_USER>,
- <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
- <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
- assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
- <66700000>, <66700000>;
-};
-
-&cmu_gscl {
- assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
- <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
- assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
- <&cmu_top CLK_ACLK_GSCL_333>;
-};
-
-&cmu_mfc {
- assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
- assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
-};
-
-&cmu_mscl {
- assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
- <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
- <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
- <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
- assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
- <&cmu_top CLK_SCLK_JPEG_MSCL>,
- <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
- <&cmu_top CLK_MOUT_BUS_PLL_USER>;
-};
-
-&cpu0 {
- cpu-supply = <&buck3_reg>;
-};
-
-&cpu4 {
- cpu-supply = <&buck2_reg>;
-};
-
-&decon {
- status = "okay";
-
- i80-if-timings {
- };
-};
-
-&dsi {
- status = "okay";
- vddcore-supply = <&ldo6_reg>;
- vddio-supply = <&ldo7_reg>;
- samsung,pll-clock-frequency = <24000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&te_irq>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port at 1 {
- reg = <1>;
-
- dsi_out: endpoint {
- samsung,burst-clock-frequency = <512000000>;
- samsung,esc-clock-frequency = <16000000>;
- };
- };
- };
-};
-
-&hsi2c_0 {
- status = "okay";
- clock-frequency = <2500000>;
-
- s2mps13-pmic at 66 {
- compatible = "samsung,s2mps13-pmic";
- interrupt-parent = <&gpa0>;
- interrupts = <7 IRQ_TYPE_NONE>;
- reg = <0x66>;
- samsung,s2mps11-wrstbi-ground;
-
- s2mps13_osc: clocks {
- compatible = "samsung,s2mps13-clk";
- #clock-cells = <1>;
- clock-output-names = "s2mps13_ap", "s2mps13_cp",
- "s2mps13_bt";
- };
-
- regulators {
- ldo1_reg: LDO1 {
- regulator-name = "VDD_ALIVE_0.9V_AP";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "VDDQ_MMC2_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "VDD1_E_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "VDD10_MIF_PLL_1.0V_AP";
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo5_reg: LDO5 {
- regulator-name = "VDD10_DPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "VDD10_MIPI2L_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "VDD18_MIPI2L_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "VDD18_LLI_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo9_reg: LDO9 {
- regulator-name = "VDD18_ABB_ETC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "VDD33_USB30_3.0V_AP";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo11_reg: LDO11 {
- regulator-name = "VDD_INT_M_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "VDD_KFC_M_1.1V_AP";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- };
-
- ldo13_reg: LDO13 {
- regulator-name = "VDD_G3D_M_0.95V_AP";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <950000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "VDDQ_M1_LDO_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "VDDQ_M2_LDO_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "VDDQ_EFUSE";
- regulator-min-microvolt = <1400000>;
- regulator-max-microvolt = <3400000>;
- regulator-always-on;
- };
-
- ldo17_reg: LDO17 {
- regulator-name = "V_TFLASH_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo18_reg: LDO18 {
- regulator-name = "V_CODEC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo19_reg: LDO19 {
- regulator-name = "VDDA_1.8V_COMP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo20_reg: LDO20 {
- regulator-name = "VCC_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- ldo21_reg: LDO21 {
- regulator-name = "VT_CAM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo22_reg: LDO22 {
- regulator-name = "CAM_IO_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo23_reg: LDO23 {
- regulator-name = "CAM_SEN_CORE_1.2V_AP";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo24_reg: LDO24 {
- regulator-name = "VT_CAM_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo25_reg: LDO25 {
- regulator-name = "CAM_SEN_A2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo26_reg: LDO26 {
- regulator-name = "CAM_AF_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo27_reg: LDO27 {
- regulator-name = "VCC_3.0V_LCD_AP";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo28_reg: LDO28 {
- regulator-name = "VCC_1.8V_LCD_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo29_reg: LDO29 {
- regulator-name = "VT_CAM_2.8V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo30_reg: LDO30 {
- regulator-name = "TSP_AVDD_3.3V_AP";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo31_reg: LDO31 {
- regulator-name = "TSP_VDD_1.85V_AP";
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <1850000>;
- };
-
- ldo32_reg: LDO32 {
- regulator-name = "VTOUCH_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo33_reg: LDO33 {
- regulator-name = "VTOUCH_LED_3.3V";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- };
-
- ldo34_reg: LDO34 {
- regulator-name = "VCC_1.8V_MHL_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <2100000>;
- };
-
- ldo35_reg: LDO35 {
- regulator-name = "OIS_VM_2.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo36_reg: LDO36 {
- regulator-name = "VSIL_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo37_reg: LDO37 {
- regulator-name = "VF_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo38_reg: LDO38 {
- regulator-name = "VCC_3.0V_MOTOR_AP";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo39_reg: LDO39 {
- regulator-name = "V_HRM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo40_reg: LDO40 {
- regulator-name = "V_HRM_3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "VDD_MIF_0.9V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "VDD_EGL_1.0V_AP";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "VDD_KFC_1.0V_AP";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "VDD_INT_0.95V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "VDD_DISP_CAM0_0.9V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "VDD_G3D_0.9V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck7_reg: BUCK7 {
- regulator-name = "VDD_MEM1_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- buck8_reg: BUCK8 {
- regulator-name = "VDD_LLDO_1.35V_AP";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- buck9_reg: BUCK9 {
- regulator-name = "VDD_MLDO_2.0V_AP";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- buck10_reg: BUCK10 {
- regulator-name = "vdd_mem2";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- };
- };
- };
-};
-
-&hsi2c_8 {
- status = "okay";
-
- max77843 at 66 {
- compatible = "maxim,max77843";
- interrupt-parent = <&gpa1>;
- interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
- reg = <0x66>;
-
- muic: max77843-muic {
- compatible = "maxim,max77843-muic";
- };
-
- regulators {
- compatible = "maxim,max77843-regulator";
- safeout1_reg: SAFEOUT1 {
- regulator-name = "SAFEOUT1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <4950000>;
- };
-
- safeout2_reg: SAFEOUT2 {
- regulator-name = "SAFEOUT2";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <4950000>;
- };
-
- charger_reg: CHARGER {
- regulator-name = "CHARGER";
- regulator-min-microamp = <100000>;
- regulator-max-microamp = <3150000>;
- };
- };
-
- haptic: max77843-haptic {
- compatible = "maxim,max77843-haptic";
- haptic-supply = <&ldo38_reg>;
- pwms = <&pwm 0 33670 0>;
- pwm-names = "haptic";
- };
- };
-};
-
-&i2s0 {
- status = "okay";
-};
-
-&mshc_0 {
- status = "okay";
- num-slots = <1>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- cap-mmc-highspeed;
- non-removable;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <0 4>;
- samsung,dw-mshc-ddr-timing = <0 2>;
- samsung,dw-mshc-hs400-timing = <0 3>;
- samsung,read-strobe-delay = <90>;
- fifo-depth = <0x80>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
- &sd0_bus8 &sd0_rdqs>;
- bus-width = <8>;
- assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
- assigned-clock-rates = <800000000>;
-};
-
-&mshc_2 {
- status = "okay";
- num-slots = <1>;
- cap-sd-highspeed;
- disable-wp;
- cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
- cd-inverted;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <0 4>;
- samsung,dw-mshc-ddr-timing = <0 2>;
- fifo-depth = <0x80>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
- bus-width = <4>;
-};
-
-&ppmu_d0_general {
- status = "okay";
- events {
- ppmu_event0_d0_general: ppmu-event0-d0-general {
- event-name = "ppmu-event0-d0-general";
- };
- };
-};
-
-&ppmu_d1_general {
- status = "okay";
- events {
- ppmu_event0_d1_general: ppmu-event0-d1-general {
- event-name = "ppmu-event0-d1-general";
- };
- };
-};
-
-&pinctrl_alive {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_alive>;
-
- initial_alive: initial-state {
- PIN(IN, gpa0-0, DOWN, LV1);
- PIN(IN, gpa0-1, NONE, LV1);
- PIN(IN, gpa0-2, DOWN, LV1);
- PIN(IN, gpa0-3, NONE, LV1);
- PIN(IN, gpa0-4, NONE, LV1);
- PIN(IN, gpa0-5, DOWN, LV1);
- PIN(IN, gpa0-6, NONE, LV1);
- PIN(IN, gpa0-7, NONE, LV1);
-
- PIN(IN, gpa1-0, UP, LV1);
- PIN(IN, gpa1-1, NONE, LV1);
- PIN(IN, gpa1-2, NONE, LV1);
- PIN(IN, gpa1-3, DOWN, LV1);
- PIN(IN, gpa1-4, DOWN, LV1);
- PIN(IN, gpa1-5, NONE, LV1);
- PIN(IN, gpa1-6, NONE, LV1);
- PIN(IN, gpa1-7, NONE, LV1);
-
- PIN(IN, gpa2-0, NONE, LV1);
- PIN(IN, gpa2-1, NONE, LV1);
- PIN(IN, gpa2-2, NONE, LV1);
- PIN(IN, gpa2-3, DOWN, LV1);
- PIN(IN, gpa2-4, NONE, LV1);
- PIN(IN, gpa2-5, DOWN, LV1);
- PIN(IN, gpa2-6, DOWN, LV1);
- PIN(IN, gpa2-7, NONE, LV1);
-
- PIN(IN, gpa3-0, DOWN, LV1);
- PIN(IN, gpa3-1, DOWN, LV1);
- PIN(IN, gpa3-2, NONE, LV1);
- PIN(IN, gpa3-3, DOWN, LV1);
- PIN(IN, gpa3-4, NONE, LV1);
- PIN(IN, gpa3-5, DOWN, LV1);
- PIN(IN, gpa3-6, DOWN, LV1);
- PIN(IN, gpa3-7, DOWN, LV1);
-
- PIN(IN, gpf1-0, NONE, LV1);
- PIN(IN, gpf1-1, NONE, LV1);
- PIN(IN, gpf1-2, DOWN, LV1);
- PIN(IN, gpf1-4, UP, LV1);
- PIN(OUT, gpf1-5, NONE, LV1);
- PIN(IN, gpf1-6, DOWN, LV1);
- PIN(IN, gpf1-7, DOWN, LV1);
-
- PIN(IN, gpf2-0, DOWN, LV1);
- PIN(IN, gpf2-1, DOWN, LV1);
- PIN(IN, gpf2-2, DOWN, LV1);
- PIN(IN, gpf2-3, DOWN, LV1);
-
- PIN(IN, gpf3-0, DOWN, LV1);
- PIN(IN, gpf3-1, DOWN, LV1);
- PIN(IN, gpf3-2, NONE, LV1);
- PIN(IN, gpf3-3, DOWN, LV1);
-
- PIN(IN, gpf4-0, DOWN, LV1);
- PIN(IN, gpf4-1, DOWN, LV1);
- PIN(IN, gpf4-2, DOWN, LV1);
- PIN(IN, gpf4-3, DOWN, LV1);
- PIN(IN, gpf4-4, DOWN, LV1);
- PIN(IN, gpf4-5, DOWN, LV1);
- PIN(IN, gpf4-6, DOWN, LV1);
- PIN(IN, gpf4-7, DOWN, LV1);
-
- PIN(IN, gpf5-0, DOWN, LV1);
- PIN(IN, gpf5-1, DOWN, LV1);
- PIN(IN, gpf5-2, DOWN, LV1);
- PIN(IN, gpf5-3, DOWN, LV1);
- PIN(OUT, gpf5-4, NONE, LV1);
- PIN(IN, gpf5-5, DOWN, LV1);
- PIN(IN, gpf5-6, DOWN, LV1);
- PIN(IN, gpf5-7, DOWN, LV1);
- };
-
- te_irq: te_irq {
- samsung,pins = "gpf1-3";
- samsung,pin-function = <0xf>;
- };
-};
-
-&pinctrl_cpif {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_cpif>;
-
- initial_cpif: initial-state {
- PIN(IN, gpv6-0, DOWN, LV1);
- PIN(IN, gpv6-1, DOWN, LV1);
- };
-};
-
-&pinctrl_ese {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_ese>;
-
- initial_ese: initial-state {
- PIN(IN, gpj2-0, DOWN, LV1);
- PIN(IN, gpj2-1, DOWN, LV1);
- PIN(IN, gpj2-2, DOWN, LV1);
- };
-};
-
-&pinctrl_fsys {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_fsys>;
-
- initial_fsys: initial-state {
- PIN(IN, gpr3-0, NONE, LV1);
- PIN(IN, gpr3-1, DOWN, LV1);
- PIN(IN, gpr3-2, DOWN, LV1);
- PIN(IN, gpr3-3, DOWN, LV1);
- PIN(IN, gpr3-7, NONE, LV1);
- };
-};
-
-&pinctrl_imem {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_imem>;
-
- initial_imem: initial-state {
- PIN(IN, gpf0-0, UP, LV1);
- PIN(IN, gpf0-1, UP, LV1);
- PIN(IN, gpf0-2, DOWN, LV1);
- PIN(IN, gpf0-3, UP, LV1);
- PIN(IN, gpf0-4, DOWN, LV1);
- PIN(IN, gpf0-5, NONE, LV1);
- PIN(IN, gpf0-6, DOWN, LV1);
- PIN(IN, gpf0-7, UP, LV1);
- };
-};
-
-&pinctrl_nfc {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_nfc>;
-
- initial_nfc: initial-state {
- PIN(IN, gpj0-2, DOWN, LV1);
- };
-};
-
-&pinctrl_peric {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_peric>;
-
- initial_peric: initial-state {
- PIN(IN, gpv7-0, DOWN, LV1);
- PIN(IN, gpv7-1, DOWN, LV1);
- PIN(IN, gpv7-2, NONE, LV1);
- PIN(IN, gpv7-3, DOWN, LV1);
- PIN(IN, gpv7-4, DOWN, LV1);
- PIN(IN, gpv7-5, DOWN, LV1);
-
- PIN(IN, gpb0-4, DOWN, LV1);
-
- PIN(IN, gpc0-2, DOWN, LV1);
- PIN(IN, gpc0-5, DOWN, LV1);
- PIN(IN, gpc0-7, DOWN, LV1);
-
- PIN(IN, gpc1-1, DOWN, LV1);
-
- PIN(IN, gpc3-4, NONE, LV1);
- PIN(IN, gpc3-5, NONE, LV1);
- PIN(IN, gpc3-6, NONE, LV1);
- PIN(IN, gpc3-7, NONE, LV1);
-
- PIN(OUT, gpg0-0, NONE, LV1);
- PIN(FUNC1, gpg0-1, DOWN, LV1);
-
- PIN(IN, gpd2-5, DOWN, LV1);
-
- PIN(IN, gpd4-0, NONE, LV1);
- PIN(IN, gpd4-1, DOWN, LV1);
- PIN(IN, gpd4-2, DOWN, LV1);
- PIN(IN, gpd4-3, DOWN, LV1);
- PIN(IN, gpd4-4, DOWN, LV1);
-
- PIN(IN, gpd6-3, DOWN, LV1);
-
- PIN(IN, gpd8-1, UP, LV1);
-
- PIN(IN, gpg1-0, DOWN, LV1);
- PIN(IN, gpg1-1, DOWN, LV1);
- PIN(IN, gpg1-2, DOWN, LV1);
- PIN(IN, gpg1-3, DOWN, LV1);
- PIN(IN, gpg1-4, DOWN, LV1);
-
- PIN(IN, gpg2-0, DOWN, LV1);
- PIN(IN, gpg2-1, DOWN, LV1);
-
- PIN(IN, gpg3-0, DOWN, LV1);
- PIN(IN, gpg3-1, DOWN, LV1);
- PIN(IN, gpg3-5, DOWN, LV1);
- PIN(IN, gpg3-7, DOWN, LV1);
- };
-};
-
-&pinctrl_touch {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_touch>;
-
- initial_touch: initial-state {
- PIN(IN, gpj1-2, DOWN, LV1);
- };
-};
-
-&pwm {
- pinctrl-0 = <&pwm0_out>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&mic {
- status = "okay";
-
- i80-if-timings {
- };
-};
-
-&pmu_system_controller {
- assigned-clocks = <&pmu_system_controller 0>;
- assigned-clock-parents = <&xxti>;
-};
-
-&serial_1 {
- status = "okay";
-};
-
-&spi_1 {
- cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- wm5110: wm5110-codec at 0 {
- compatible = "wlf,wm5110";
- reg = <0x0>;
- spi-max-frequency = <20000000>;
- interrupt-parent = <&gpa0>;
- interrupts = <4 IRQ_TYPE_NONE>;
- clocks = <&pmu_system_controller 0>,
- <&s2mps13_osc S2MPS11_CLK_BT>;
- clock-names = "mclk1", "mclk2";
-
- gpio-controller;
- #gpio-cells = <2>;
-
- wlf,micd-detect-debounce = <300>;
- wlf,micd-bias-start-time = <0x1>;
- wlf,micd-rate = <0x7>;
- wlf,micd-dbtime = <0x1>;
- wlf,micd-force-micbias;
- wlf,micd-configs = <0x0 1 0>;
- wlf,hpdet-channel = <1>;
- wlf,gpsw = <0x1>;
- wlf,inmode = <2 0 2 0>;
-
- wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
- wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
-
- /* core supplies */
- AVDD-supply = <&ldo18_reg>;
- DBVDD1-supply = <&ldo18_reg>;
- CPVDD-supply = <&ldo18_reg>;
- DBVDD2-supply = <&ldo18_reg>;
- DBVDD3-supply = <&ldo18_reg>;
-
- controller-data {
- samsung,spi-feedback-delay = <0>;
- };
- };
-};
-
-&timer {
- clock-frequency = <24000000>;
-};
-
-&tmu_atlas0 {
- vtmu-supply = <&ldo3_reg>;
- status = "okay";
-};
-
-&tmu_apollo {
- vtmu-supply = <&ldo3_reg>;
- status = "okay";
-};
-
-&tmu_g3d {
- vtmu-supply = <&ldo3_reg>;
- status = "okay";
-};
-
-&usbdrd30 {
- vdd33-supply = <&ldo10_reg>;
- vdd10-supply = <&ldo6_reg>;
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
-};
-
-&usbdrd30_phy {
- vbus-supply = <&safeout1_reg>;
- status = "okay";
-};
-
-&xxti {
- clock-frequency = <24000000>;
-};
+/*
+ * SAMSUNG Exynos5433 TM2 board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *
+ * Device tree source file for Samsung's TM2 board which is based on
+ * Samsung Exynos5433 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos5433-tm2-common.dtsi"
+
+/ {
+ model = "Samsung TM2 board";
+ compatible = "samsung,tm2", "samsung,exynos5433";
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 1db4e7f..81fdbef 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -11,7 +11,7 @@
* published by the Free Software Foundation.
*/
-#include "exynos5433-tm2.dts"
+#include "exynos5433-tm2-common.dtsi"
/ {
model = "Samsung TM2E board";
--
2.7.4
^ permalink raw reply related
* [PATCH v2 4/4] arm64: dts: exynos: Add tm2 touchkey node
From: Jaechul Lee @ 2017-01-05 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483604833-29746-1-git-send-email-jcsing.lee@samsung.com>
Add DT node support for TM2 touchkey device.
Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index aa8584a..dad6fb8 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -17,3 +17,16 @@
model = "Samsung TM2 board";
compatible = "samsung,tm2", "samsung,exynos5433";
};
+
+&hsi2c_9 {
+ status = "okay";
+
+ touchkey at 20 {
+ compatible = "samsung,tm2-touchkey";
+ reg = <0x20>;
+ interrupt-parent = <&gpa3>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply = <&ldo32_reg>;
+ vdd-supply = <&ldo33_reg>;
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH] cpufreq: Remove CONFIG_CPU_FREQ_STAT_DETAILS config option
From: Viresh Kumar @ 2017-01-05 8:27 UTC (permalink / raw)
To: linux-arm-kernel
This doesn't have any benefit apart from saving a small amount of memory
when it is disabled. The ifdef hackery in the code makes it dirty
unnecessarily.
Clean it up by removing the Kconfig option completely. Few defconfigs
are also updated and CONFIG_CPU_FREQ_STAT_DETAILS is replaced with
CONFIG_CPU_FREQ_STAT now in them, as users wanted stats to be enabled.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/configs/exynos_defconfig | 2 +-
arch/arm/configs/multi_v5_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
arch/arm/configs/mvebu_v5_defconfig | 2 +-
arch/arm/configs/pxa_defconfig | 2 +-
arch/arm/configs/shmobile_defconfig | 2 +-
arch/mips/configs/lemote2f_defconfig | 1 -
arch/powerpc/configs/ppc6xx_defconfig | 1 -
arch/sh/configs/sh7785lcr_32bit_defconfig | 2 +-
drivers/cpufreq/Kconfig | 8 --------
drivers/cpufreq/cpufreq_stats.c | 14 --------------
11 files changed, 7 insertions(+), 31 deletions(-)
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 79c415c33f69..809f0bf3042a 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -24,7 +24,7 @@ CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 361686a362f1..69a4bd13eea5 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -58,7 +58,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_KIRKWOOD_CPUIDLE=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index b01a43851294..2dcac90eba01 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -132,7 +132,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_KEXEC=y
CONFIG_EFI=y
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
index f7f6039419aa..4b598da0d086 100644
--- a/arch/arm/configs/mvebu_v5_defconfig
+++ b/arch/arm/configs/mvebu_v5_defconfig
@@ -44,7 +44,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_KIRKWOOD_CPUIDLE=y
diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig
index e4314b1227a3..271dc7e78e43 100644
--- a/arch/arm/configs/pxa_defconfig
+++ b/arch/arm/configs/pxa_defconfig
@@ -97,7 +97,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=/dev/ram0 ro"
CONFIG_KEXEC=y
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 1b0f8ae36fb3..adeaecd831a4 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -38,7 +38,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
index 5da76e0e120f..bed745596d86 100644
--- a/arch/mips/configs/lemote2f_defconfig
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -40,7 +40,6 @@ CONFIG_PM_STD_PARTITION="/dev/hda3"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEBUG=y
CONFIG_CPU_FREQ_STAT=m
-CONFIG_CPU_FREQ_STAT_DETAILS=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index 3ce91a3df27f..1d2d69dd6409 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -62,7 +62,6 @@ CONFIG_MPC8610_HPCD=y
CONFIG_GEF_SBC610=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=m
-CONFIG_CPU_FREQ_STAT_DETAILS=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
diff --git a/arch/sh/configs/sh7785lcr_32bit_defconfig b/arch/sh/configs/sh7785lcr_32bit_defconfig
index 9bdcf72ec06a..2fce54d9c388 100644
--- a/arch/sh/configs/sh7785lcr_32bit_defconfig
+++ b/arch/sh/configs/sh7785lcr_32bit_defconfig
@@ -25,7 +25,7 @@ CONFIG_SH_SH7785LCR=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_SH_CPU_FREQ=y
CONFIG_HEARTBEAT=y
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index d8b164a7c4e5..15adef473d42 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -37,14 +37,6 @@ config CPU_FREQ_STAT
If in doubt, say N.
-config CPU_FREQ_STAT_DETAILS
- bool "CPU frequency transition statistics details"
- depends on CPU_FREQ_STAT
- help
- Show detailed CPU frequency transition table in sysfs.
-
- If in doubt, say N.
-
choice
prompt "Default CPUFreq governor"
default CPU_FREQ_DEFAULT_GOV_USERSPACE if ARM_SA1100_CPUFREQ || ARM_SA1110_CPUFREQ
diff --git a/drivers/cpufreq/cpufreq_stats.c b/drivers/cpufreq/cpufreq_stats.c
index ac284e66839c..18abd454da43 100644
--- a/drivers/cpufreq/cpufreq_stats.c
+++ b/drivers/cpufreq/cpufreq_stats.c
@@ -25,9 +25,7 @@ struct cpufreq_stats {
unsigned int last_index;
u64 *time_in_state;
unsigned int *freq_table;
-#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
unsigned int *trans_table;
-#endif
};
static int cpufreq_stats_update(struct cpufreq_stats *stats)
@@ -46,9 +44,7 @@ static void cpufreq_stats_clear_table(struct cpufreq_stats *stats)
unsigned int count = stats->max_state;
memset(stats->time_in_state, 0, count * sizeof(u64));
-#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
memset(stats->trans_table, 0, count * count * sizeof(int));
-#endif
stats->last_time = get_jiffies_64();
stats->total_trans = 0;
}
@@ -84,7 +80,6 @@ static ssize_t store_reset(struct cpufreq_policy *policy, const char *buf,
return count;
}
-#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
static ssize_t show_trans_table(struct cpufreq_policy *policy, char *buf)
{
struct cpufreq_stats *stats = policy->stats;
@@ -129,7 +124,6 @@ static ssize_t show_trans_table(struct cpufreq_policy *policy, char *buf)
return len;
}
cpufreq_freq_attr_ro(trans_table);
-#endif
cpufreq_freq_attr_ro(total_trans);
cpufreq_freq_attr_ro(time_in_state);
@@ -139,9 +133,7 @@ static struct attribute *default_attrs[] = {
&total_trans.attr,
&time_in_state.attr,
&reset.attr,
-#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
&trans_table.attr,
-#endif
NULL
};
static struct attribute_group stats_attr_group = {
@@ -200,9 +192,7 @@ void cpufreq_stats_create_table(struct cpufreq_policy *policy)
alloc_size = count * sizeof(int) + count * sizeof(u64);
-#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
alloc_size += count * count * sizeof(int);
-#endif
/* Allocate memory for time_in_state/freq_table/trans_table in one go */
stats->time_in_state = kzalloc(alloc_size, GFP_KERNEL);
@@ -211,9 +201,7 @@ void cpufreq_stats_create_table(struct cpufreq_policy *policy)
stats->freq_table = (unsigned int *)(stats->time_in_state + count);
-#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
stats->trans_table = stats->freq_table + count;
-#endif
stats->max_state = count;
@@ -259,8 +247,6 @@ void cpufreq_stats_record_transition(struct cpufreq_policy *policy,
cpufreq_stats_update(stats);
stats->last_index = new_index;
-#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
stats->trans_table[old_index * stats->max_state + new_index]++;
-#endif
stats->total_trans++;
}
--
2.7.1.410.g6faf27b
^ permalink raw reply related
* [PATCH 03/22] iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs
From: Chen-Yu Tsai @ 2017-01-05 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9acfe5e0-dc56-bd63-02b4-7bf34d49d62c@free-electrons.com>
On Thu, Jan 5, 2017 at 4:06 PM, Quentin Schulz
<quentin.schulz@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On 05/01/2017 06:42, Chen-Yu Tsai wrote:
>> On Tue, Jan 3, 2017 at 12:37 AM, Quentin Schulz
>> <quentin.schulz@free-electrons.com> wrote:
> [...]
>>> +
>>> +#define AXP20X_ADC_RATE_MASK (3 << 6)
>>> +#define AXP20X_ADC_RATE_25HZ (0 << 6)
>>> +#define AXP20X_ADC_RATE_50HZ BIT(6)
>>
>> Please be consistent with the format.
>>
>>> +#define AXP20X_ADC_RATE_100HZ (2 << 6)
>>> +#define AXP20X_ADC_RATE_200HZ (3 << 6)
>>> +
>>> +#define AXP22X_ADC_RATE_100HZ (0 << 6)
>>> +#define AXP22X_ADC_RATE_200HZ BIT(6)
>>> +#define AXP22X_ADC_RATE_400HZ (2 << 6)
>>> +#define AXP22X_ADC_RATE_800HZ (3 << 6)
>>
>> These are power-of-2 multiples of some base rate. May I suggest
>> a formula macro instead. Either way, you seem to be using only
>> one value. Will this be made configurable in the future?
>>
>
> Yes, I could use a formula macro instead. No plan to make it
> configurable, should I make it configurable?
I don't see a use case for that atm.
>>> +
>>> +#define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \
>>> + { \
>>> + .type = _type, \
>>> + .indexed = 1, \
>>> + .channel = _channel, \
>>> + .address = _reg, \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>> + BIT(IIO_CHAN_INFO_SCALE), \
>>> + .datasheet_name = _name, \
>>> + }
>>> +
>>> +#define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \
>>> + { \
>>> + .type = _type, \
>>> + .indexed = 1, \
>>> + .channel = _channel, \
>>> + .address = _reg, \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>> + BIT(IIO_CHAN_INFO_SCALE) |\
>>> + BIT(IIO_CHAN_INFO_OFFSET),\
>>> + .datasheet_name = _name, \
>>> + }
>>> +
>>> +struct axp20x_adc_iio {
>>> + struct iio_dev *indio_dev;
>>> + struct regmap *regmap;
>>> +};
>>> +
>>> +enum axp20x_adc_channel {
>>> + AXP20X_ACIN_V = 0,
>>> + AXP20X_ACIN_I,
>>> + AXP20X_VBUS_V,
>>> + AXP20X_VBUS_I,
>>> + AXP20X_TEMP_ADC,
>>
>> PMIC_TEMP would be better. And please save a slot for TS input.
>>
>
> ACK.
>
> Hum.. I'm wondering what should be the IIO type of the TS input channel
> then? The TS Pin can be used in two modes: either to monitor the
> temperature of the battery or as an external ADC, at least that's what I
> understand from the datasheet.
AFAIK the battery charge/discharge high/low temperature threshold
registers take values in terms of voltage, not actual temperature.
And the temperature readout kind of depends on the thermoresistor
one is using. So I think "voltage" would be the proper type.
>
>>> + AXP20X_GPIO0_V,
>>> + AXP20X_GPIO1_V,
>>
>> Please skip a slot for "battery instantaneous power".
>>
>>> + AXP20X_BATT_V,
>>> + AXP20X_BATT_CHRG_I,
>>> + AXP20X_BATT_DISCHRG_I,
>>> + AXP20X_IPSOUT_V,
>>> +};
>>> +
>>> +enum axp22x_adc_channel {
>>> + AXP22X_TEMP_ADC = 0,
>>
>> Same comments as AXP20X_TEMP_ADC.
>>
>>> + AXP22X_BATT_V,
>>> + AXP22X_BATT_CHRG_I,
>>> + AXP22X_BATT_DISCHRG_I,
>>> +};
>>
>> Shouldn't these channel numbers be exported as part of the device tree
>> bindings? At the very least, they shouldn't be changed.
>>
>
> I don't understand what you mean by that. Do you mean you want a
> consistent numbering between the AXP20X and the AXP22X, so that
> AXP22X_BATT_V would have the same channel number than AXP20X_BATT_V?
>
> Could you explain a bit more your thoughts on the channel numbers being
> exported as part of the device tree bindings?
What I meant was that, since you are referencing the channels in the
device tree, the numbering scheme would be part of the device tree
binding, and should never be changed. So either these would be macros
in include/dt-bindings/, or a big warning should be put before it.
But see my reply on patch 7, about do we actually need to expose this
in the device tree.
>> Also please add a comment saying that the channels are numbered
>> in the order of their respective registers, and not the table
>> describing the ADCs in the datasheet (9.7 Signal Capture for AXP209
>> and 9.5 E-Gauge for AXP221).
>>
>
> Yes I can.
>
> What about Rob wanting channel numbers to start at zero for each
> different IIO type (i.e., today we have AXP22X_BATT_CHRG_I being
> exported as in_current1_raw whereas he wants in_current0_raw).
Hmm... I missed this. Are you talking about IIO or hwmon? IIRC
hwmon numbers things starting at 1.
> [...]
>>> +static int axp22x_adc_read_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *channel, int *val,
>>> + int *val2)
>>> +{
>>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
>>> + int size = 12, ret;
>>> +
>>> + switch (channel->channel) {
>>> + case AXP22X_BATT_DISCHRG_I:
>>> + size = 13;
>>> + case AXP22X_TEMP_ADC:
>>> + case AXP22X_BATT_V:
>>> + case AXP22X_BATT_CHRG_I:
>>
>> According to the datasheet, AXP22X_BATT_CHRG_I is also 13 bits wide.
>>
>
> Where did you get that?
>
> Also, the datasheet is inconsistent:
> - 9.5 E-Gauge Fuel Gauge system => the min value is at 0x0 and the max
> value at 0xfff for all channels, that's 12 bits.
> - 10.1.4 ADC Data => all channels except battery discharge current are
> on 12 bits (8 high, 4 low).
My datasheets (AXP221 v1.6, AXP221s v1.2, AXP223 v1.1, all Chinese) say
in 10.1.4:
- 7A: battery charge current high 5 bits
- 7B: battery charge current low 8 bits
- 7C: battery discharge current high 5 bits
- 7D: battery discharge current low 8 bits
>
> [...]
>>> +static int axp22x_read_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan, int *val,
>>> + int *val2, long mask)
>>> +{
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_OFFSET:
>>> + *val = -2667;
>>
>> Datasheet says -267.7 C, or -2677 here.
>>
>
> The formula in the datasheet is (in milli Celsius):
> processed = raw * 100 - 266700;
>
> while the IIO framework asks for a scale and an offset which are then
> applied as:
> processed = (raw + offset) * scale;
>
> Thus by factorizing, we get:
> processed = (raw - 2667) * 100;
What I meant was that your lower end value is off by one degree,
-266.7 in your code vs -267.7 in the datasheet.
>
> [...]
>>> +static int axp20x_remove(struct platform_device *pdev)
>>> +{
>>> + struct axp20x_adc_iio *info;
>>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>>> +
>>> + info = iio_priv(indio_dev);
>>
>> Nit: you could just reverse the 2 declarations above and join this
>> line after struct axp20x_adc_iio *info;
>>
>>> + regmap_write(info->regmap, AXP20X_ADC_EN1, 0);
>>> + regmap_write(info->regmap, AXP20X_ADC_EN2, 0);
>>
>> The existing VBUS power supply driver enables the VBUS ADC bits itself,
>> and does not check them later on. This means if one were to remove this
>> axp20x-adc module, the voltage/current readings in the VBUS power supply
>> would be invalid. Some sort of workaround would be needed here in this
>> driver of the VBUS driver.
>>
>
> That would be one reason to migrate the VBUS driver to use the IIO
> channels, wouldn't it?
It is, preferably without changing the device tree.
Regards
ChenYu
>
> But ACK, I'll think about something to work around this issue.
>
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static struct platform_driver axp20x_adc_driver = {
>>> + .driver = {
>>> + .name = "axp20x-adc",
>>> + .of_match_table = axp20x_adc_of_match,
>>> + },
>>> + .probe = axp20x_probe,
>>> + .remove = axp20x_remove,
>>> +};
>>> +
>>> +module_platform_driver(axp20x_adc_driver);
>>> +
>>> +MODULE_DESCRIPTION("ADC driver for AXP20X and AXP22X PMICs");
>>> +MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
>>> +MODULE_LICENSE("GPL");
>>> diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
>>> index a4860bc..650c6f6 100644
>>> --- a/include/linux/mfd/axp20x.h
>>> +++ b/include/linux/mfd/axp20x.h
>>> @@ -150,6 +150,10 @@ enum {
>>> #define AXP20X_VBUS_I_ADC_L 0x5d
>>> #define AXP20X_TEMP_ADC_H 0x5e
>>> #define AXP20X_TEMP_ADC_L 0x5f
>>> +
>>> +#define AXP22X_TEMP_ADC_H 0x56
>>> +#define AXP22X_TEMP_ADC_L 0x57
>>> +
>>
>> This is in the wrong patch. Also we already have
>>
>> /* AXP22X specific registers */
>> #define AXP22X_PMIC_ADC_H 0x56
>> #define AXP22X_PMIC_ADC_L 0x57
>> #define AXP22X_TS_ADC_H 0x58
>> #define AXP22X_TS_ADC_L 0x59
>>
>> If you want, you could just rename them to be consistent.
>>
>
> ACK.
>
> Thanks,
> Quentin
>
> --
> Quentin Schulz, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* [PATCH 02/10] iommu/of: Prepare for deferred IOMMU configuration
From: Sricharan @ 2017-01-05 8:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161201112917.GA9680@red-moon>
Hi Robin/Lorenzo,
>Hi Robin,Lorenzo,
>
>>On Wed, Nov 30, 2016 at 04:42:27PM +0000, Robin Murphy wrote:
>>> On 30/11/16 16:17, Lorenzo Pieralisi wrote:
>>> > Sricharan, Robin,
>>> >
>>> > I gave this series a go on ACPI and apart from an SMMU v3 fix-up
>>> > it seems to work, more thorough testing required though.
>>> >
>>> > A key question below.
>>> >
>>> > On Wed, Nov 30, 2016 at 05:52:16AM +0530, Sricharan R wrote:
>>> >> From: Robin Murphy <robin.murphy@arm.com>
>>> >>
>>> >> IOMMU configuration represents unchanging properties of the hardware,
>>> >> and as such should only need happen once in a device's lifetime, but
>>> >> the necessary interaction with the IOMMU device and driver complicates
>>> >> exactly when that point should be.
>>> >>
>>> >> Since the only reasonable tool available for handling the inter-device
>>> >> dependency is probe deferral, we need to prepare of_iommu_configure()
>>> >> to run later than it is currently called (i.e. at driver probe rather
>>> >> than device creation), to handle being retried, and to tell whether a
>>> >> not-yet present IOMMU should be waited for or skipped (by virtue of
>>> >> having declared a built-in driver or not).
>>> >>
>>> >> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>> >> ---
>>> >> drivers/iommu/of_iommu.c | 30 +++++++++++++++++++++++++++++-
>>> >> 1 file changed, 29 insertions(+), 1 deletion(-)
>>> >>
>>> >> diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
>>> >> index ee49081..349bd1d 100644
>>> >> --- a/drivers/iommu/of_iommu.c
>>> >> +++ b/drivers/iommu/of_iommu.c
>>> >> @@ -104,12 +104,20 @@ int of_get_dma_window(struct device_node *dn, const char *prefix, int index,
>>> >> int err;
>>> >>
>>> >> ops = iommu_get_instance(fwnode);
>>> >> - if (!ops || !ops->of_xlate)
>>> >> + if ((ops && !ops->of_xlate) ||
>>> >> + (!ops && !of_match_node(&__iommu_of_table, iommu_spec->np)))
>>> >
>>> > IIUC of_match_node() here is there to check there is a driver compiled
>>> > in for this device_node (aka compatible string in OF world), correct ?
>>>
>>> Yes - specifically, it's checking the magic table for a matching
>>> IOMMU_OF_DECLARE entry.
>>>
>>> > If that's the case (and I think that's what Sricharan was referring to
>>> > in his ACPI query) I need to cook-up something on the ACPI side to
>>> > emulate the OF linker table behaviour (or anyway to detect a driver is
>>> > actually in the kernel), it is not that difficult but it is key to know,
>>> > I will give it some thought to make it as clean as possible.
>>>
>>> I didn't think this would be a concern for ACPI, since IORT works much
>>> the same way the current of_iommu_init_fn/of_platform_device_create()
>>> bodges in drivers so for DT. If you can only discover SMMUs from IORT,
>>> then iort_init_platform_devices() will have already created every SMMU
>>> that's going to exist before discovering other devices from wherever
>>> they come from, thus you could never get into the situation of probing a
>>> device without its SMMU being ready (if it's ever going to be). Is that
>>> not right?
>>
>>It is right, my point and question is: we are probing a device and we
>>have to know whether it is worth deferring its IOMMU DMA setup. On DT,
>>through of_match_node(&__iommu_of_table, iommu_device_node) we check at
>>once that:
>>
>>1 - A device for the IOMMU exists
>>
>>AND
>>
>>2 - A driver for the IOMMU is compiled in the kernel
>>
>>Is this correct ? As you said (1) is not a concern on ACPI IORT (because
>>we create the IOMMU device before _any_ other device so either the IOMMU
>>device is there or it will never be by the time master devices are
>>probed), but for (2) I need to slightly change how the IORT linker entry
>>work to make sure we can detect a driver is actually compiled in the
>>kernel, it is easy, I was just asking if my understanding was correct
>>and I think that was what Sricharan was referring to in his query.
>>
>
>Yes right, this was what i was looking for in the ACPI case and putting this
>in the iort_iommu_xlate was needed to return EPROBE_DEFER when the
>driver is not yet been probed.
With the thinking of taking this series through, would it be fine if i cleanup
the pci configure hanging outside and push it in to of/acpi_iommu configure
respectively ? This time with all neeeded for ACPI added as well.
Also on the last post of V4, Lorenzo commented that it worked for him, although
still the of_match_node equivalent in ACPI has to be added. If i can get that,
then i will add that as well to make this complete.
Regards,
Sricharan
^ permalink raw reply
* [PATCH v3] mfd: axp20x: Fix AXP806 access errors on cold boot
From: Lee Jones @ 2017-01-05 8:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105040103.10303-1-wens@csie.org>
On Thu, 05 Jan 2017, Chen-Yu Tsai wrote:
> The AXP806 supports either master/standalone or slave mode.
> Slave mode allows sharing the serial bus, even with multiple
> AXP806 which all have the same hardware address.
>
> This is done with extra "serial interface address extension",
> or AXP806_BUS_ADDR_EXT, and "register address extension", or
> AXP806_REG_ADDR_EXT, registers. The former is read-only, with
> 1 bit customizable at the factory, and 1 bit depending on the
> state of an external pin. The latter is writable. Only when
> the these device addressing bits (in the upper 4 bits of the
> registers) match, will the device respond to operations on
> its other registers.
>
> The AXP806_REG_ADDR_EXT was previously configured by Allwinner's
> bootloader. Work on U-boot SPL support now allows us to switch
> to mainline U-boot, which doesn't do this for us. There might
> be other bare minimum bootloaders out there which don't to this
> either. It's best to handle this in the kernel.
>
> This patch sets AXP806_REG_ADDR_EXT to 0x10, which is what we
> know to be the proper value for a standard AXP806 in slave mode.
> Afterwards it will reinitialize the regmap cache, to purge any
> invalid stale values.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> Changes since v2:
>
> - Dropped regcache_sync_region() and regmap_reinit_cache() calls.
> The write immediately after getting the regmap from the caller
> of axp20x_device_probe() is enough.
>
> - Slightly rearranged a few sentences in the comment block.
> ---
> drivers/mfd/axp20x.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
Much better.
Applied, thanks.
> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> index ed918de84238..81b9ddd10e6c 100644
> --- a/drivers/mfd/axp20x.c
> +++ b/drivers/mfd/axp20x.c
> @@ -31,6 +31,8 @@
>
> #define AXP20X_OFF 0x80
>
> +#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
> +
> static const char * const axp20x_model_names[] = {
> "AXP152",
> "AXP202",
> @@ -830,6 +832,30 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
> {
> int ret;
>
> + /*
> + * The AXP806 supports either master/standalone or slave mode.
> + * Slave mode allows sharing the serial bus, even with multiple
> + * AXP806 which all have the same hardware address.
> + *
> + * This is done with extra "serial interface address extension",
> + * or AXP806_BUS_ADDR_EXT, and "register address extension", or
> + * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
> + * 1 bit customizable at the factory, and 1 bit depending on the
> + * state of an external pin. The latter is writable. The device
> + * will only respond to operations to its other registers when
> + * the these device addressing bits (in the upper 4 bits of the
> + * registers) match.
> + *
> + * Since we only support an AXP806 chained to an AXP809 in slave
> + * mode, and there isn't any existing hardware which uses AXP806
> + * in master mode, or has 2 AXP806s in the same system, we can
> + * just program the register address extension to the slave mode
> + * address.
> + */
> + if (axp20x->variant == AXP806_ID)
> + regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
> + AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
> +
> ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
> IRQF_ONESHOT | IRQF_SHARED, -1,
> axp20x->regmap_irq_chip,
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree for Arria10
From: Steffen Trumtrar @ 2017-01-05 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483575694-29599-9-git-send-email-dinguyen@kernel.org>
Hi!
Dinh Nguyen <dinguyen@kernel.org> writes:
> From: Graham Moore <grmoore@opensource.altera.com>
>
> Add socfpga_arria10_socdk_nand.dts board file for supporting NAND.
>
> Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 44 ++++++++++++++++++++++++
> 2 files changed, 45 insertions(+)
> create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
>
(...)
> +#include "socfpga_arria10_socdk.dtsi"
> +
> +/ {
> + soc {
> + nand: nand at ffb90000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + status = "okay";
> +
> + compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
> + reg = <0xffb90000 0x72000>, <0xffb80000 0x10000>;
> + reg-names = "nand_data", "denali_reg";
> + interrupts = <0 99 4>;
> + dma-mask = <0xffffffff>;
> + clocks = <&nand_clk>;
This belongs into the socfpga_arria10.dtsi.
Regards,
Steffen
--
Pengutronix e.K. | Steffen Trumtrar |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v2 4/4] ARM: dts: keystone: Add "ti, da830-uart" compatible string
From: Sekhar Nori @ 2017-01-05 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <93c4aed0-6faa-2c27-7931-454fc1f48e79@oracle.com>
Hi Santosh,
On Thursday 05 January 2017 03:30 AM, Santosh Shilimkar wrote:
> On 1/4/2017 12:30 PM, David Lechner wrote:
>> The TI Keystone SoCs have extra UART registers beyond the standard 8250
>> registers, so we need a new compatible string to indicate this. Also, at
>> least one of these registers uses the full 32 bits, so we need to specify
>> reg-io-width in addition to reg-shift.
>>
>> "ns16550a" is left in the compatible specification since it does work as
>> long as the bootloader configures the SoC UART power management
>> registers.
>>
> NAK!!
> We can't break the booting boards with existing boot loaders.
Sorry, but it not clear to me how this breaks booting with older
bootloaders? If older DTB is ROM'ed, it will continue to work because of
match with ns16550a.
I just verified boot on K2E with these patches applied and using 2016.05
based U-Boot from a TI release.
http://pastebin.ubuntu.com/23744719/
> I suggest you to first get the driver updated to take care of
> the UART PM register and then enable the support for it.
Isn't that what patch 2/4 is doing?
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v8 0/5] Add support for the STM32F4 I2C
From: M'boumba Cedric Madianga @ 2017-01-05 9:07 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds support for the I2C controller embedded in STM32F4xx SoC.
It enables I2C transfer in interrupt mode with Standard-mode and Fast-mode bus
speed.
Changes since v7:
- Remove unneeded parenthesis in some macro definitions (Uwe)
- Fix some typo (s/KhzkHZ, s/PEC/POC) (Uwe)
- Fix alignment issues in some structures declaration (Uwe)
- Clarify comments to argue i2c_timing values chosen (Uwe)
- Raise an error if parent clk rate is out of scope during I2C hw config (Uwe)
- Use dev_dbg instead of dev_err message when I2C bus is busy (Uwe)
- Add more comments about stuff done by stm32f4_i2c_handle_rx_btf() (Uwe)
- Simplify stm32f4_i2c_isr_error() routine implementation by removing possible
status checking (Uwe)
- Rework stm32f4_i2c_isr_error() routine by removing the loop to check which status occured (Uwe)
- Add open-drain property for SCL pins (Uwe)
- Rework unneeded mul_ccr field from i2c_timing structure
- Remove min_ccr field from i2c_timing structure as default scl_period is chosen
to have a correct minimal ccr value
- Execute hw_config once during probe
- Remove soft_reset after an I2C error as all errors are now handled and
hw_config is done once during probe
- Generate STOP by software when Acknowledge failure occurs
- Set the max speed mode for I2C pins
- Add bias-disable property for I2C pins
- Use intrinsic limitation of APB bus to set I2C max input clk
M'boumba Cedric Madianga (5):
dt-bindings: Document the STM32 I2C bindings
i2c: Add STM32F4 I2C driver
ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
ARM: dts: stm32: Add I2C1 support for STM32429 eval board
ARM: configs: stm32: Add I2C support for STM32 defconfig
.../devicetree/bindings/i2c/i2c-stm32.txt | 33 +
arch/arm/boot/dts/stm32429i-eval.dts | 6 +
arch/arm/boot/dts/stm32f429.dtsi | 23 +
arch/arm/configs/stm32_defconfig | 3 +
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-stm32f4.c | 866 +++++++++++++++++++++
7 files changed, 942 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-stm32.txt
create mode 100644 drivers/i2c/busses/i2c-stm32f4.c
--
1.9.1
^ permalink raw reply
* [PATCH v8 1/5] dt-bindings: Document the STM32 I2C bindings
From: M'boumba Cedric Madianga @ 2017-01-05 9:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483607246-14771-1-git-send-email-cedric.madianga@gmail.com>
This patch adds documentation of device tree bindings for the STM32 I2C
controller.
Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/i2c/i2c-stm32.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-stm32.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
new file mode 100644
index 0000000..78eaf7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
@@ -0,0 +1,33 @@
+* I2C controller embedded in STMicroelectronics STM32 I2C platform
+
+Required properties :
+- compatible : Must be "st,stm32f4-i2c"
+- reg : Offset and length of the register set for the device
+- interrupts : Must contain the interrupt id for I2C event and then the
+ interrupt id for I2C error.
+- resets: Must contain the phandle to the reset controller.
+- clocks: Must contain the input clock of the I2C instance.
+- A pinctrl state named "default" must be defined to set pins in mode of
+ operation for I2C transfer
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties :
+- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
+ the default 100 kHz frequency will be used. As only Normal and Fast modes
+ are supported, possible values are 100000 and 400000.
+
+Example :
+
+ i2c at 40005400 {
+ compatible = "st,stm32f4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc 277>;
+ clocks = <&rcc 0 149>;
+ pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
+ pinctrl-names = "default";
+ };
--
1.9.1
^ permalink raw reply related
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