* [PATCH v2 3/4] ARM64: dts: exynos5433: use macros for pinctrl configuration on Exynos5433
From: Krzysztof Kozlowski @ 2017-01-05 20:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbX_MuLSCerq08-1VZV6VJfynjkv1QOr7ssOCGvM5aB_Q@mail.gmail.com>
On Tue, Jan 03, 2017 at 09:24:34AM +0100, Linus Walleij wrote:
> On Fri, Dec 30, 2016 at 4:17 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > On Fri, Dec 30, 2016 at 02:32:39PM +0100, Linus Walleij wrote:
> >> On Fri, Dec 30, 2016 at 5:14 AM, Andi Shyti <andi.shyti@samsung.com> wrote:
> >>
> >> > Use the macros defined in include/dt-bindings/pinctrl/samsung.h
> >> > instead of hardcoded values.
> >> >
> >> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> >>
> >> These look fine, but that this and the other DTS patch through ARM SoC.
> >>
> >> If you also need the headerfile patch (patch 2) to go through ARM SoC
> >> that is fine,
> >> I can take it out of pinctrl if you want.
> >
> > Yes, I need the header. It would be much appreciated if you could
> > provide a tag or stable branch with it.
>
> Nah better just merge that patch into the ARM SoC tree only.
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> I'll remove it from the pinctrl tree.
Thanks, I see it being dropped.
Andi,
Please fix missing Signed-off-by and resend with Linus' tags for #1 and
#2 and with other accumulated tags.
Best regards,
Krzysztof
^ permalink raw reply
* [nomadik:lis3lv02 5/6] warning: (IIO_ST_ACCEL_3AXIS) selects IIO_ST_ACCEL_I2C_3AXIS which has unmet direct dependencies (IIO && ..)
From: kbuild test robot @ 2017-01-05 20:03 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git lis3lv02
head: e343deae8006a1fc109534497c943eab51a1c2a8
commit: 0a9710dd480b06b6fefefdedc732020f2297e247 [5/6] iio: accel: st_accel: handle deprecated bindings
config: x86_64-randconfig-x008-201701 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
git checkout 0a9710dd480b06b6fefefdedc732020f2297e247
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
warning: (IIO_ST_ACCEL_3AXIS) selects IIO_ST_ACCEL_I2C_3AXIS which has unmet direct dependencies (IIO && !SENSORS_LIS3_I2C && IIO_ST_ACCEL_3AXIS && IIO_ST_SENSORS_I2C)
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCHv2 0/5] Support for Marvell switches with integrated CPUs
From: Chris Packham @ 2017-01-05 20:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPv3WKcT8MxX+g12C1o81MmQJWRt7Rpd-hgBh8rTpLOS3vdtqA@mail.gmail.com>
On 06/01/17 03:09, Marcin Wojtas wrote:
> Hi Chris,
>
> Thanks a lot for your work and v2. Can you please add changelog
> between patchset versions in your cover letter?
Will do for v3. I did actually include a changelog in the individual
patches but I can collate that here.
clk: mvebu: support for 98DX3236 SoC
- Update devicetree binding documentation for new compatible string
arm: mvebu: support for SMP on 98DX3336 SoC
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
- include sdio support for the 98DX4251
arm: mvebu: Add device tree for 98DX3236 SoCs
- Update devicetree binding documentation to reflect that 98DX3336 and
984251 are supersets of 98DX3236.
- disable crypto block
- disable sdio for 98DX3236, enable for 98DX4251
arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
- None
Here's the interdiff
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index a1bcfeed5f24..3c2fd72d0bf9 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -202,6 +202,7 @@ nodes to be present and contain the properties
described below.
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
+ "marvell,98dx3236-smp"
"mediatek,mt6589-smp"
"mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
index e7dc9b2dd90b..64e8c73fc5ab 100644
--- a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
@@ -6,5 +6,18 @@ shall have the following property:
Required root node property:
-compatible: one of "marvell,armadaxp-98dx3236", "marvell,armadaxp-98dx3336"
- or "marvell,armadaxp-98dx4251"
+compatible: must contain "marvell,armadaxp-98dx3236"
+
+In addition, boards using the Marvell 98DX3336 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3336"
+
+In addition, boards using the Marvell 98DX4251 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx4251"
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index 99c214660bdc..7f28506eaee7 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU
platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+ "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
diff --git
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
index 34c1e380adaa..d4e6ecdfc853 100644
---
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
+++
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
@@ -4,7 +4,7 @@ Please refer to marvell,mvebu-pinctrl.txt in this
directory for common binding
part and usage
Required properties:
-- compatible: "marvell,98dx3236-pinctrl"
+- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
- reg: register specifier of MPP registers
This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
@@ -16,12 +16,12 @@ mpp1 1 gpio, spi0(miso), dev(ad9)
mpp2 2 gpio, spi0(sck), dev(ad10)
mpp3 3 gpio, spi0(cs0), dev(ad11)
mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
-mpp5 5 gpio, pex(rsto), dev(bootcs)
-mpp6 6 gpio, dev(a2)
-mpp7 7 gpio, dev(ale0)
-mpp8 8 gpio, dev(ale1)
-mpp9 9 gpio, dev(ready0)
-mpp10 10 gpio, dev(ad12)
+mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
+mpp6 6 gpio, sd0(clk), dev(a2)
+mpp7 7 gpio, sd0(d0), dev(ale0)
+mpp8 8 gpio, sd0(d1), dev(ale1)
+mpp9 9 gpio, sd0(d2), dev(ready0)
+mpp10 10 gpio, sd0(d3), dev(ad12)
mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
mpp13 13 gpio, intr(out), dev(ad15)
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index bac53f8b44af..61bd3acc5cfe 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -138,6 +138,10 @@
status = "disabled";
};
+ crypto at 90000 {
+ status = "disabled";
+ };
+
xor at f0900 {
status = "disabled";
};
@@ -229,3 +233,15 @@
marvell,function = "spi0";
};
};
+
+&sdio {
+ status = "disabled";
+};
+
+&crypto_sram0 {
+ status = "disabled";
+};
+
+&crypto_sram1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index 5d1da8513fae..5f7edc23d5ae 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -76,3 +76,17 @@
};
};
};
+
+&sdio {
+ status = "okay";
+};
+
+&pinctrl {
+ compatible = "marvell,98dx4251-pinctrl";
+
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp5", "mpp6", "mpp7",
+ "mpp8", "mpp9", "mpp10";
+ marvell,function = "sd0";
+ };
+};
diff --git a/arch/arm/mach-mvebu/pmsu-98dx3236.c
b/arch/arm/mach-mvebu/pmsu-98dx3236.c
index fadc81d0c051..87ca42ef40c7 100644
--- a/arch/arm/mach-mvebu/pmsu-98dx3236.c
+++ b/arch/arm/mach-mvebu/pmsu-98dx3236.c
@@ -1,5 +1,5 @@
/**
- * CPU resume support for 98DX4521 internal CPU (a.k.a. MSYS).
+ * CPU resume support for 98DX3236 internal CPU (a.k.a. MSYS).
*/
#define pr_fmt(fmt) "mv98dx3236-resume: " fmt
@@ -38,7 +38,7 @@ static int __init mv98dx3236_resume_init(void)
if (!np)
return 0;
- pr_info("Initializing 98DX4521 Resume\n");
+ pr_info("Initializing 98DX3236 Resume\n");
if (of_address_to_resource(np, 0, &res)) {
pr_err("unable to get resource\n");
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 2586903c59f0..554eeae8cd21 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -389,21 +389,27 @@ static struct mvebu_mpp_mode
mv98dx3236_mpp_modes[] = {
MPP_MODE(5,
MPP_VAR_FUNCTION(0x0, "gpio", NULL,
V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x1, "pex", "rsto",
V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "bootcs0",
V_98DX3236_PLUS)),
MPP_MODE(6,
MPP_VAR_FUNCTION(0x0, "gpo", NULL,
V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "a2",
V_98DX3236_PLUS)),
MPP_MODE(7,
MPP_VAR_FUNCTION(0x0, "gpio", NULL,
V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ale0",
V_98DX3236_PLUS)),
MPP_MODE(8,
MPP_VAR_FUNCTION(0x0, "gpio", NULL,
V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ale1",
V_98DX3236_PLUS)),
MPP_MODE(9,
MPP_VAR_FUNCTION(0x0, "gpio", NULL,
V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ready0",
V_98DX3236_PLUS)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0x0, "gpio", NULL,
V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ad12",
V_98DX3236_PLUS)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0x0, "gpio", NULL,
V_98DX3236_PLUS),
@@ -501,6 +507,10 @@ static const struct of_device_id
armada_xp_pinctrl_of_match[] = {
.compatible = "marvell,98dx3236-pinctrl",
.data = (void *) V_98DX3236,
},
+ {
+ .compatible = "marvell,98dx4251-pinctrl",
+ .data = (void *) V_98DX4251,
+ },
{ },
};
>
> Best regards,
> Marcin
>
> 2017-01-05 4:36 GMT+01:00 Chris Packham <chris.packham@alliedtelesis.co.nz>:
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>> integrated CPUs. They CPU block is common within these product lines and
>> (as far as I can tell/have been told) is based on the Armada XP. There
>> are a few differences due to the fact they have to squeeze the CPU into
>> the same package as the switch.
>>
>> Chris Packham (4):
>> clk: mvebu: support for 98DX3236 SoC
>> arm: mvebu: support for SMP on 98DX3336 SoC
>> arm: mvebu: Add device tree for 98DX3236 SoCs
>> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
>>
>> Kalyan Kinthada (1):
>> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
>>
>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 18 ++
>> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
>> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
>> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
>> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 247 +++++++++++++++++++++
>> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 78 +++++++
>> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 92 ++++++++
>> arch/arm/boot/dts/db-dxbc2.dts | 159 +++++++++++++
>> arch/arm/boot/dts/db-xc3-24g4xg.dts | 155 +++++++++++++
>> arch/arm/mach-mvebu/Makefile | 1 +
>> arch/arm/mach-mvebu/common.h | 1 +
>> arch/arm/mach-mvebu/platsmp.c | 43 ++++
>> arch/arm/mach-mvebu/pmsu-98dx3236.c | 69 ++++++
>> drivers/clk/mvebu/Makefile | 2 +-
>> drivers/clk/mvebu/armada-xp.c | 42 ++++
>> drivers/clk/mvebu/clk-cpu.c | 33 ++-
>> drivers/clk/mvebu/mv98dx3236-corediv.c | 207 +++++++++++++++++
>> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++
>> 19 files changed, 1369 insertions(+), 4 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
>> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>> create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c
>> create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c
>>
>> --
>> 2.11.0.24.ge6920cf
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply related
* next-20170105 build: 4 failures 3 warnings (next-20170105)
From: Mark Brown @ 2017-01-05 19:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1cP6p1-0007i0-IF@optimist>
On Thu, Jan 05, 2017 at 12:07:08PM +0000, Build bot for Mark Brown wrote:
Since sometime over the Christmas vacation all arm64 configs have been
failing to build due to:
> ../arch/arm64/include/asm/setup.h:14:29: error: redefinition of 'kaslr_offset'
(same error repeating a different number of times for each config).
This is an interaction between Andrew's -current tree and Linus' tree.
Andrew's tree has "arm64: setup: introduce kaslr_offset()"
(1a339a14b1f2c7 in current -next) and Linus' tree has a commit
7ede8665f27cde7d with the same title but a modified version that went to
Linus through Will. In the version in Andrew's tree kaslr_offset() is
defined in asm/setup.h while in the version in Linus' tree it is
instead defined in asm/memory.h so -next ends up with two definitions of
that function causing the build errors.
I guess the commit in Andrew's tree should be dropped now, reverting it
fixes the builds for me.
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^ permalink raw reply
* [PATCHv2 0/5] Support for Marvell switches with integrated CPUs
From: Florian Fainelli @ 2017-01-05 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <059c78eaa7dd40c9a46cb08616bae2eb@svr-chch-ex1.atlnz.lc>
On 01/05/2017 11:46 AM, Chris Packham wrote:
> On 06/01/17 02:10, Andrew Lunn wrote:
>>> I'd love to see a switchdev driver but it's a huge task (and no I'm not
>>> committing to writing it). As it stands Marvell ship a switch SDK
>>> largely executes in userspace with a small kernel module providing some
>>> linkage to the underlying hardware.
>>
>> Is there any similarity to the mv88e6xxx family?
>>
>> If it was similar registers, just a different access mechanising, we
>> could probably extend the mv88e6xxx to support MMIO as well as MDIO.
>
> No the prestera family of devices are considerably more powerful (and
> complex) than the linkstreet devices.
I see, we have a similar situation with some of the Broadcom SoCs, the
BCM534xx/BCM5334x have a completely different integrated switching
engine that is not roboswitch compatible.
Thanks for the information, this is still valuable to have this
supported upstream.
--
Florian
^ permalink raw reply
* [PATCH 2/2] arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA
From: Robert Richter @ 2017-01-05 19:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105122200.GV4930@rric.localdomain>
On 05.01.17 13:22:00, Robert Richter wrote:
> On 05.01.17 12:08:20, Will Deacon wrote:
> > I really can't see how the fix causes a crash, and I couldn't reproduce
> > it on any of my boards, nor could any of the Linaro folk afaik. Are you
> > definitely running mainline with just these two patches from Ard?
>
> Yes, just both patches applied. Various other solutions were working.
I have retested the same kernel (v4.9 based) as before and now it
boots fine including rtc-efi device registration (it was crashing
there):
rtc-efi rtc-efi: rtc core: registered rtc-efi as rtc0
There could be a difference in firmware and mem setup, though I also
downgraded the firmware to test it, but can't reproduce it anymore. I
could reliable trigger the crash the first time.
FTR the oops.
-Robert
Unable to handle kernel paging request at virtual address 20251000
pgd = ffff000009090000
[20251000] *pgd=0000010ffff90003
, *pud=0000010ffff90003
, *pmd=0000000fdc030003
, *pte=00e8832000250707
Internal error: Oops: 96000047 [#1] SMP
Modules linked in:
CPU: 49 PID: 1 Comm: swapper/0 Tainted: G W 4.9.0.0.vanilla10-00002-g429605e9ab0a #1
Hardware name: www.cavium.com ThunderX CRB-2S/ThunderX CRB-2S, BIOS 0.3 Sep 13 2016
task: ffff800feee6bc00 task.stack: ffff800fec050000
PC is at 0x201ff820
LR is at 0x201fdfc0
pc : [<00000000201ff820>] lr : [<00000000201fdfc0>] pstate: 20000045
sp : ffff800fec053b70
x29: ffff800fec053bc0 x28: 0000000000000000
x27: ffff000008ce3e08 x26: ffff000008c52568
x25: ffff000008bf045c x24: ffff000008bdb828
x23: 0000000000000000 x22: 0000000000000040
x21: ffff800fec053bb8 x20: 0000000020251000
x19: ffff800fec053c20 x18: 0000000000000000
x17: 0000000000000000 x16: 00000000bbb67a65
x15: ffffffffffffffff x14: ffff810016ea291c
x13: ffff810016ea2181 x12: 0000000000000030
x11: 0101010101010101 x10: 7f7f7f7f7f7f7f7f
x9 : feff716475687163 x8 : ffffffffffffffff
x7 : 83f0680000000000 x6 : 0000000000000000
x5 : ffff800fc187aab9 x4 : 0002000000000000
x3 : ffff800fec053bb8 x2 : 0000000000000000
x1 : 83f0680000000000 x0 : 0000000020251000
Process swapper/0 (pid: 1, stack limit = 0xffff800fec050020)
Stack: (0xffff800fec053b70 to 0xffff800fec054000)
3b60: ffff800fec053c20 ffff800fec053c20
3b80: ffff800fec053c10 00000000201fd500 ffff000008e660d0 ffff800fec053c20
3ba0: ffff0000086eb954 ffff0000086eb930 ffff800fec053bc0 ffff0000086eb934
3bc0: ffff800fec053bf0 ffff000008c3eef4 ffff000008e602a0 ffff000008e602b0
3be0: ffff000008e60740 ffff000008e60768 ffff800fec053c30 ffff000008586c88
3c00: 00000000ffffffed ffff00000858023c ffff800fec053c30 ffff000008586c68
3c20: 0000000000000000 ffff000008e602b0 ffff800fec053c60 ffff0000085845d4
3c40: ffff000008e602b0 ffff000009049000 0000000000000000 ffff000008e60768
3c60: ffff800fec053ca0 ffff0000085848ac ffff000008e602b0 ffff000008e60310
3c80: ffff000008e60768 0000000000000000 ffff000008e4d000 ffff000008bdb828
3ca0: ffff800fec053cd0 ffff000008581e08 0000000000000000 ffff000008e60768
3cc0: ffff000008584788 0000000000000000 ffff800fec053d10 ffff000008583c30
3ce0: ffff000008e60768 ffff810fed477c00 ffff000008e4deb0 0000000000000000
3d00: ffff800fe54554a8 ffff810fed478e68 ffff800fec053d30 ffff000008583668
3d20: ffff000008e60768 ffff810fed477c00 ffff800fec053d70 ffff000008585430
3d40: ffff000008e60768 0000000000000000 ffff000008c3eed0 ffff000008e60768
3d60: ffff000008ef0000 0000000000000000 ffff800fec053d90 ffff000008586e3c
3d80: ffff000008e60740 0000000000000000 ffff800fec053dc0 ffff000008c3eec8
3da0: ffff000008c3eea8 ffff800fec050000 0000000000000000 0000000000000006
3dc0: ffff800fec053dd0 ffff000008082d94 ffff800fec053e40 ffff000008bf0d0c
3de0: 00000000000000f3 ffff000008ef0000 ffff000008c52578 0000000000000006
3e00: ffff000008ce3600 0000000000000000 ffff000008da2428 ffff000008ab2fa8
3e20: 0000000000000000 0000000600000006 ffff000008bf045c ffff000008bdb828
3e40: ffff800fec053ea0 ffff00000885e7a0 ffff00000885e788 0000000000000000
3e60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3e80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3ea0: 0000000000000000 ffff000008082b30 ffff00000885e788 0000000000000000
3ec0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3ee0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3f00: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3f20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3f40: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3f60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3f80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3fa0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
3fc0: 0000000000000000 0000000000000005 0000000000000000 0000000000000000
3fe0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
Call trace:
Exception stack(0xffff800fec0539a0 to 0xffff800fec053ad0)
39a0: ffff800fec053c20 0001000000000000 ffff800fec053b70 00000000201ff820
39c0: 0000000000000000 ffff810000412890 ffff800fec0539f0 ffff000008405534
39e0: ffff810000412890 ffff810016e90e30 ffff800fec053a20 ffff00000840682c
3a00: 0000000000000000 ffff800fc168f880 0000000000000000 ffff00000840668c
3a20: ffff800fec053ac0 ffff0000084069f8 ffff00000903e7b0 0000000000000001
3a40: 0000000020251000 83f0680000000000 0000000000000000 ffff800fec053bb8
3a60: 0002000000000000 ffff800fc187aab9 0000000000000000 83f0680000000000
3a80: ffffffffffffffff feff716475687163 7f7f7f7f7f7f7f7f 0101010101010101
3aa0: 0000000000000030 ffff810016ea2181 ffff810016ea291c ffffffffffffffff
3ac0: 00000000bbb67a65 0000000000000000
[<00000000201ff820>] 0x201ff820
[<ffff000008c3eef4>] efi_rtc_probe+0x24/0x78
[<ffff000008586c88>] platform_drv_probe+0x60/0xc8
[<ffff0000085845d4>] driver_probe_device+0x26c/0x420
[<ffff0000085848ac>] __driver_attach+0x124/0x128
[<ffff000008581e08>] bus_for_each_dev+0x70/0xb0
[<ffff000008583c30>] driver_attach+0x30/0x40
[<ffff000008583668>] bus_add_driver+0x200/0x2b8
[<ffff000008585430>] driver_register+0x68/0x100
[<ffff000008586e3c>] __platform_driver_probe+0x84/0x128
[<ffff000008c3eec8>] efi_rtc_driver_init+0x20/0x28
[<ffff000008082d94>] do_one_initcall+0x44/0x138
[<ffff000008bf0d0c>] kernel_init_freeable+0x1ac/0x24c
[<ffff00000885e7a0>] kernel_init+0x18/0x110
[<ffff000008082b30>] ret_from_fork+0x10/0x20
Code: f9400000 d5033d9f d65f03c0 d5033e9f (f9000001)
---[ end trace e420ef9636e3c9b2 ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
^ permalink raw reply
* [PATCHv2 0/5] Support for Marvell switches with integrated CPUs
From: Chris Packham @ 2017-01-05 19:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105130945.GA18033@lunn.ch>
On 06/01/17 02:10, Andrew Lunn wrote:
>> I'd love to see a switchdev driver but it's a huge task (and no I'm not
>> committing to writing it). As it stands Marvell ship a switch SDK
>> largely executes in userspace with a small kernel module providing some
>> linkage to the underlying hardware.
>
> Is there any similarity to the mv88e6xxx family?
>
> If it was similar registers, just a different access mechanising, we
> could probably extend the mv88e6xxx to support MMIO as well as MDIO.
No the prestera family of devices are considerably more powerful (and
complex) than the linkstreet devices.
^ permalink raw reply
* [arm:clearfog 21/65] drivers/net/phy/micrel.c:969:2: warning: initialization from incompatible pointer type
From: kbuild test robot @ 2017-01-05 19:41 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git clearfog
head: a0b3b7ea35687eaa7b1836bcdbbe10daf034c621
commit: adb3f9b9239ac1d683db5f1e0ac9435966d02b3d [21/65] net: phy: convert micrel to new read_mmd/write_mmd driver methods
config: openrisc-or1ksim_defconfig (attached as .config)
compiler: or32-linux-gcc (GCC) 4.5.1-or32-1.0rc1
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout adb3f9b9239ac1d683db5f1e0ac9435966d02b3d
# save the attached .config to linux build tree
make.cross ARCH=openrisc
All warnings (new ones prefixed by >>):
>> drivers/net/phy/micrel.c:969:2: warning: initialization from incompatible pointer type
vim +969 drivers/net/phy/micrel.c
953 .phy_id_mask = 0x000ffffe,
954 .name = "Micrel KSZ9021 Gigabit PHY",
955 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
956 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
957 .driver_data = &ksz9021_type,
958 .config_init = ksz9021_config_init,
959 .config_aneg = genphy_config_aneg,
960 .read_status = genphy_read_status,
961 .ack_interrupt = kszphy_ack_interrupt,
962 .config_intr = kszphy_config_intr,
963 .get_sset_count = kszphy_get_sset_count,
964 .get_strings = kszphy_get_strings,
965 .get_stats = kszphy_get_stats,
966 .suspend = genphy_suspend,
967 .resume = genphy_resume,
968 .read_mmd = ksz9021_rd_mmd_phyreg,
> 969 .write_mmd = ksz9021_wr_mmd_phyreg,
970 }, {
971 .phy_id = PHY_ID_KSZ9031,
972 .phy_id_mask = MICREL_PHY_ID_MASK,
973 .name = "Micrel KSZ9031 Gigabit PHY",
974 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
975 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
976 .driver_data = &ksz9021_type,
977 .config_init = ksz9031_config_init,
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v2] ARM: dts: Add missing CPU frequencies for Exynos5422/5800
From: Krzysztof Kozlowski @ 2017-01-05 19:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2c85559a-dc12-610b-c842-c89d078e1c2a@osg.samsung.com>
On Wed, Jan 04, 2017 at 08:57:47PM -0300, Javier Martinez Canillas wrote:
> Hello Doug,
>
> On 01/04/2017 06:05 PM, Doug Anderson wrote:
> > Hi,
> >
> > On Thu, Dec 29, 2016 at 6:17 AM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >> On Thu, Dec 15, 2016 at 04:54:30PM -0800, Doug Anderson wrote:
> >>>> Index: b/arch/arm/boot/dts/exynos5800.dtsi
> >>>> ===================================================================
> >>>> --- a/arch/arm/boot/dts/exynos5800.dtsi 2016-12-15 12:43:54.365955950 +0100
> >>>> +++ b/arch/arm/boot/dts/exynos5800.dtsi 2016-12-15 12:43:54.361955949 +0100
> >>>> @@ -24,6 +24,16 @@
> >>>> };
> >>>>
> >>>> &cluster_a15_opp_table {
> >>>> + opp at 2000000000 {
> >>>> + opp-hz = /bits/ 64 <2000000000>;
> >>>> + opp-microvolt = <1250000>;
> >>>> + clock-latency-ns = <140000>;
> >>>> + };
> >>>> + opp at 1900000000 {
> >>>> + opp-hz = /bits/ 64 <1900000000>;
> >>>> + opp-microvolt = <1250000>;
> >>>> + clock-latency-ns = <140000>;
> >>>> + };
> >>>
> >>> I don't think the voltages you listed are high enough for all peach pi
> >>> boards for A15 at 1.9 GHz and 2.0 GHz, at least based on the research
> >>> I did. See my response to v1.
> >>
> >> I wanted to apply this but saw this remaining issue. Javier tested it
> >> on Peach Pi so is this concern still valid?
> >
> > I'm not sure. It's been years since I did anything with exynos, so I
> > won't stand in the way if everyone else agrees that this patch is
> > good, but I will point out that testing on a single Peach Pi board is
> > not really enough given the massive difference in voltage needed
> > between the highest ASV group and the lowest (a whopping 112.5 mV from
> > looking in the Chrome OS source tree).
> >
>
> I agree. That's why answered that I wasn't able to find regressions on the
> Peach Pi I've access to, but I couldn't provide a Reviewed-by tag since it
> wasn't clear to me that the values were safe for any Exynos5420/5422/5800.
The value of 1.250 V seems to be covering only half of ASV values for
2.0 GHz so indeed it might be insufficient for some of the chips.
Unfortunately...
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2 8/8] ARM: dts: kirkwood-rd88f6281: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net: dsa:
Document new binding"). The legacy binding node is kept included, but is marked
disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts | 11 ++++++++
arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 44 +++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
index 1a797381d3d4..6a4a65ec7944 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
@@ -33,3 +33,14 @@
ð1 {
status = "disabled";
};
+
+&switch {
+ reg = <0>;
+
+ ports {
+ port at 4 {
+ reg = <4>;
+ label = "wan";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
index d5aacf137e40..91f5da5dae5f 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -54,6 +54,8 @@
};
dsa {
+ status = "disabled";
+
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@@ -115,6 +117,48 @@
&mdio {
status = "okay";
+
+ switch: switch at 0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð0port>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ };
+ };
};
ð0 {
--
2.9.3
^ permalink raw reply related
* [PATCH v2 7/8] ARM: dts: kirkwood-mv88f6281gtw-ge: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net: dsa:
Document new binding"). The legacy binding node is kept included, but is marked
disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 49 ++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 172a38c0b8a9..327023a477b8 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -112,6 +112,8 @@
};
dsa {
+ status = "disabled";
+
compatible = "marvell,dsa";
#address-cells = <1>;
#size-cells = <0>;
@@ -159,6 +161,53 @@
&mdio {
status = "okay";
+
+ switch at 0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð0port>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
};
ð0 {
--
2.9.3
^ permalink raw reply related
* [PATCH v2 6/8] ARM: dts: kirkwood-linksys-viper: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net: dsa:
Document new binding"). The legacy binding node is kept included, but is marked
disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/kirkwood-linksys-viper.dts | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
index 345fcac48dc7..df7851820507 100644
--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts
+++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
@@ -70,6 +70,8 @@
};
dsa {
+ status = "disabled";
+
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@@ -207,6 +209,53 @@
&mdio {
status = "okay";
+
+ switch at 10 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <16>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "ethernet1";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "ethernet2";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "ethernet3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "ethernet4";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "internet";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð0port>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
};
&uart0 {
--
2.9.3
^ permalink raw reply related
* [PATCH v2 5/8] ARM: dts: kirkwood-dir665: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net: dsa:
Document new binding"). The legacy binding node is kept included, but is marked
disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/kirkwood-dir665.dts | 49 +++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
index 41acbb6dd6ab..4d2b15d6244a 100644
--- a/arch/arm/boot/dts/kirkwood-dir665.dts
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -194,6 +194,8 @@
};
dsa {
+ status = "disabled";
+
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@@ -241,6 +243,53 @@
&mdio {
status = "okay";
+
+ switch at 0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port at 6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <ð0port>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
};
/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
--
2.9.3
^ permalink raw reply related
* [PATCH v2 4/8] ARM: dts: armada-xp-linksys-mamba: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net: dsa:
Document new binding"). The legacy binding node is kept included, but is marked
disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 53 +++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 83ac884c0f8a..42ea8764814c 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -302,6 +302,8 @@
};
dsa {
+ status = "disabled";
+
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@@ -398,3 +400,54 @@
spi-max-frequency = <40000000>;
};
};
+
+&mdio {
+ status = "okay";
+
+ switch at 0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "internet";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/8] ARM: dts: armada-388-clearfog: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net:
dsa: Document new binding"). The legacy binding node is kept included, but is
marked disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 65 +++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 71ce201c903e..40ec6d768669 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -351,6 +351,8 @@
};
dsa at 0 {
+ status = "disabled";
+
compatible = "marvell,dsa";
dsa,ethernet = <ð1>;
dsa,mii-bus = <&mdio>;
@@ -444,3 +446,66 @@
status = "disabled";
};
};
+
+&mdio {
+ status = "okay";
+
+ switch at 4 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan5";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan4";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "lan1";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð1>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port at 6 {
+ /* 88E1512 external phy */
+ reg = <6>;
+ label = "lan6";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 2/8] ARM: dts: armada-385-linksys: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net: dsa:
Document new binding"). The legacy binding node is kept included, but is marked
disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/armada-385-linksys.dtsi | 52 ++++++++++++++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index 8f0e508f64ae..20d5e8b00f2d 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -103,8 +103,56 @@
};
};
- mdio {
+ mdio at 72004 {
status = "okay";
+
+ switch at 0 {
+ compatible = "marvell,mv88e6095";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð2>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
};
sata at a8000 {
@@ -261,6 +309,8 @@
};
dsa at 0 {
+ status = "disabled";
+
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
--
2.9.3
^ permalink raw reply related
* [PATCH v2 1/8] ARM: dts: armada-370-rd: Utilize new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105192957.14304-1-f.fainelli@gmail.com>
Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net: dsa:
Document new binding"). The legacy binding node is kept included, but is marked
disabled.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/armada-370-rd.dts | 44 +++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index c3fd6e49212f..ade956cbd41a 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -173,6 +173,8 @@
};
dsa {
+ status = "disabled";
+
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@@ -235,6 +237,48 @@
phy0: ethernet-phy at 0 {
reg = <0>;
};
+
+ switch: switch at 10 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð1>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 0/8] ARM: dts: Switch to new DSA binding
From: Florian Fainelli @ 2017-01-05 19:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series converts the in-tree users to utilize the new (relatively)
DSA binding that was introduced with commit 8c5ad1d6179d ("net: dsa: Document
new binding"). The legacy binding node is kept included, but is marked
disabled.
Changes in v2:
- patch 1: Use an hexadecimal reg property
- patch 2: fixed the subject
- patch 3: s/okay/disabled/ for the legacy DSA node
- patches 7/8: fixed a stray whitespace
In about 2-3 releases we may consider removing the old DSA binding entirely
from the kernel.
Thank you!
Florian Fainelli (8):
ARM: dts: armada-370-rd: Utilize new DSA binding
ARM: dts: armada-385-linksys: Utilize new DSA binding
ARM: dts: armada-388-clearfog: Utilize new DSA binding
ARM: dts: armada-xp-linksys-mamba: Utilize new DSA binding
ARM: dts: kirkwood-dir665: Utilize new DSA binding
ARM: dts: kirkwood-linksys-viper: Utilize new DSA binding
ARM: dts: kirkwood-mv88f6281gtw-ge: Utilize new DSA binding
ARM: dts: kirkwood-rd88f6281: Utilize new DSA binding
arch/arm/boot/dts/armada-370-rd.dts | 44 +++++++++++++++++
arch/arm/boot/dts/armada-385-linksys.dtsi | 52 ++++++++++++++++++++-
arch/arm/boot/dts/armada-388-clearfog.dts | 65 ++++++++++++++++++++++++++
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 53 +++++++++++++++++++++
arch/arm/boot/dts/kirkwood-dir665.dts | 49 +++++++++++++++++++
arch/arm/boot/dts/kirkwood-linksys-viper.dts | 49 +++++++++++++++++++
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 49 +++++++++++++++++++
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts | 11 +++++
arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 44 +++++++++++++++++
9 files changed, 415 insertions(+), 1 deletion(-)
--
2.9.3
^ permalink raw reply
* [PATCH v2 04/19] ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2017-01-05 19:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0a343705-1d38-9fe2-6419-56ab9bdfb0c2@mentor.com>
Hi Vladimir,
On 01/04/2017 04:25 AM, Vladimir Zapolskiy wrote:
> Hi Steve,
>
> On 01/03/2017 10:57 PM, Steve Longerbeam wrote:
>> Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
>> Both hang off the same i2c2 bus, so they require different (and non-
>> default) i2c slave addresses.
>>
>> The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
>>
>> The OV5640 connects to the input port on the MIPI CSI-2 receiver on
>> mipi_csi. It is set to transmit over MIPI virtual channel 1.
>>
>> Note there is a pin conflict with GPIO6. This pin functions as a power
>> input pin to the OV5642, but ENET uses it as the h/w workaround for
>> erratum ERR006687, to wake-up the ARM cores on normal RX and TX packet
>> done events (see 6261c4c8). So workaround 6261c4c8 is reverted here to
>> support the OV5642, and the "fsl,err006687-workaround-present" boolean
>> also must be removed. The result is that the CPUidle driver will no longer
>> allow entering the deep idle states on the sabrelite.
> For me it sounds like a candidate of its own separate change.
Yes, I split out the two partial reverts into a separate commit
("ARM: dts: imx6qdl-sabrelite: remove erratum ERR006687
workaround").
>
>
>
>> +
>> + mipi_camera: ov5640 at 40 {
> Please reorder device nodes by address value,
done.
> also according to ePAPR
> node names should be generic, labels can be specific:
>
> ov5640: camera at 40 {
> ...
> };
>
> ov5642: camera at 42 {
> ...
> };
fixed.
>
>> + pinctrl_ipu1_csi0: ipu1grp-csi0 {
> Please rename node name to ipu1csi0grp.
done.
>
>> +
>> + pinctrl_ov5640: ov5640grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
>> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
>> + >;
>> + };
>> +
> Indentation issues above, please use tabs instead of spaces.
fixed.
>
> Also please add new pin control groups preserving the alphanimerical order.
done.
Steve
^ permalink raw reply
* [PATCH 1/2] soc: ti: knav_dma: fix typos in trace message
From: Santosh Shilimkar @ 2017-01-05 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <586E99AA.7080409@ti.com>
On 1/5/2017 11:08 AM, Murali Karicheri wrote:
> On 12/20/2016 08:01 PM, Santosh Shilimkar wrote:
>> On 12/20/2016 2:24 PM, Murali Karicheri wrote:
>>> This patch fixes some typos in the trace message
>>>
>>> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
>>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>>> ---
>> Patch 1 and 2 looks fine. Will pick them for next
>> merge window. Thanks !!
>>
>> Regards,
>> Santosh
>>
> Santosh,
>
> Could you send this to linux-next please so that I can
> cherry-pick them for our internal release?
>
Am collecting few more patches Murali. Hopefully
I will be able to push that to linux-next next week.
Regards,
Santosh
^ permalink raw reply
* [PATCH 1/2] soc: ti: knav_dma: fix typos in trace message
From: Murali Karicheri @ 2017-01-05 19:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <06b11675-e66f-2a0f-134a-29ab789f7d99@oracle.com>
On 12/20/2016 08:01 PM, Santosh Shilimkar wrote:
> On 12/20/2016 2:24 PM, Murali Karicheri wrote:
>> This patch fixes some typos in the trace message
>>
>> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>> ---
> Patch 1 and 2 looks fine. Will pick them for next
> merge window. Thanks !!
>
> Regards,
> Santosh
>
Santosh,
Could you send this to linux-next please so that I can
cherry-pick them for our internal release?
--
Murali Karicheri
Linux Kernel, Keystone
^ permalink raw reply
* [PATCH] ARM: OMAP2+: Fix init for multiple quirks for the same SoC
From: Tony Lindgren @ 2017-01-05 19:08 UTC (permalink / raw)
To: linux-arm-kernel
It's possible that there are multiple quirks that need to be initialized
for the same SoC. Fix the issue by not returning on the first match.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/pdata-quirks.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -599,7 +599,6 @@ static void pdata_quirks_check(struct pdata_init *quirks)
if (of_machine_is_compatible(quirks->compatible)) {
if (quirks->fn)
quirks->fn();
- break;
}
quirks++;
}
--
2.11.0
^ permalink raw reply
* [PATCH v6 18/18] iommu/arm-smmu: Do not advertise IOMMU_CAP_INTR_REMAP anymore
From: Eric Auger @ 2017-01-05 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483643086-2883-1-git-send-email-eric.auger@redhat.com>
IOMMU_CAP_INTR_REMAP has been advertised in arm-smmu(-v3) although
on ARM this property is not attached to the IOMMU but rather is
implemented in the MSI controller (GICv3 ITS).
Now vfio_iommu_type1 checks MSI remapping capability at MSI controller
level, let's correct this.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
drivers/iommu/arm-smmu-v3.c | 2 --
drivers/iommu/arm-smmu.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 6c4111c..d9cf6cb 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -1375,8 +1375,6 @@ static bool arm_smmu_capable(enum iommu_cap cap)
switch (cap) {
case IOMMU_CAP_CACHE_COHERENCY:
return true;
- case IOMMU_CAP_INTR_REMAP:
- return true; /* MSIs are just memory writes */
case IOMMU_CAP_NOEXEC:
return true;
default:
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a354572..13d2600 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1374,8 +1374,6 @@ static bool arm_smmu_capable(enum iommu_cap cap)
* requests.
*/
return true;
- case IOMMU_CAP_INTR_REMAP:
- return true; /* MSIs are just memory writes */
case IOMMU_CAP_NOEXEC:
return true;
default:
--
1.9.1
^ permalink raw reply related
* [PATCH v6 17/18] vfio/type1: Check MSI remapping at irq domain level
From: Eric Auger @ 2017-01-05 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483643086-2883-1-git-send-email-eric.auger@redhat.com>
In case the IOMMU translates MSI transactions (typical case
on ARM), we check MSI remapping capability at IRQ domain
level. Otherwise it is checked at IOMMU level.
At this stage the arm-smmu-(v3) still advertise the
IOMMU_CAP_INTR_REMAP capability at IOMMU level. This will be
removed in subsequent patches.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v6: rewrite test
---
drivers/vfio/vfio_iommu_type1.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index b473ef80..fa0b5c4 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -40,6 +40,7 @@
#include <linux/mdev.h>
#include <linux/notifier.h>
#include <linux/dma-iommu.h>
+#include <linux/irqdomain.h>
#define DRIVER_VERSION "0.2"
#define DRIVER_AUTHOR "Alex Williamson <alex.williamson@redhat.com>"
@@ -1208,7 +1209,7 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
struct vfio_domain *domain, *d;
struct bus_type *bus = NULL, *mdev_bus;
int ret;
- bool resv_msi;
+ bool resv_msi, msi_remap;
phys_addr_t resv_msi_base;
mutex_lock(&iommu->lock);
@@ -1284,8 +1285,10 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
INIT_LIST_HEAD(&domain->group_list);
list_add(&group->next, &domain->group_list);
- if (!allow_unsafe_interrupts &&
- !iommu_capable(bus, IOMMU_CAP_INTR_REMAP)) {
+ msi_remap = resv_msi ? irq_domain_check_msi_remap() :
+ iommu_capable(bus, IOMMU_CAP_INTR_REMAP);
+
+ if (!allow_unsafe_interrupts && !msi_remap) {
pr_warn("%s: No interrupt remapping support. Use the module param \"allow_unsafe_interrupts\" to enable VFIO IOMMU support on this platform\n",
__func__);
ret = -EPERM;
--
1.9.1
^ permalink raw reply related
* [PATCH v6 16/18] vfio/type1: Allow transparent MSI IOVA allocation
From: Eric Auger @ 2017-01-05 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483643086-2883-1-git-send-email-eric.auger@redhat.com>
When attaching a group to the container, check the group's
reserved regions and test whether the IOMMU translates MSI
transactions. If yes, we initialize an IOVA allocator through
the iommu_get_msi_cookie API. This will allow the MSI IOVAs
to be transparently allocated on MSI controller's compose().
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v3 -> v4:
- test region's type: IOMMU_RESV_MSI
- restructure the code to prepare for safety assessment
- reword title
---
drivers/vfio/vfio_iommu_type1.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index f3726ba..b473ef80 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -39,6 +39,7 @@
#include <linux/pid_namespace.h>
#include <linux/mdev.h>
#include <linux/notifier.h>
+#include <linux/dma-iommu.h>
#define DRIVER_VERSION "0.2"
#define DRIVER_AUTHOR "Alex Williamson <alex.williamson@redhat.com>"
@@ -1177,6 +1178,28 @@ static struct vfio_group *find_iommu_group(struct vfio_domain *domain,
return NULL;
}
+static bool vfio_iommu_has_resv_msi(struct iommu_group *group,
+ phys_addr_t *base)
+{
+ struct list_head group_resv_regions;
+ struct iommu_resv_region *region, *next;
+ bool ret = false;
+
+ INIT_LIST_HEAD(&group_resv_regions);
+ iommu_get_group_resv_regions(group, &group_resv_regions);
+ list_for_each_entry(region, &group_resv_regions, list) {
+ if (region->type & IOMMU_RESV_MSI) {
+ *base = region->start;
+ ret = true;
+ goto out;
+ }
+ }
+out:
+ list_for_each_entry_safe(region, next, &group_resv_regions, list)
+ kfree(region);
+ return ret;
+}
+
static int vfio_iommu_type1_attach_group(void *iommu_data,
struct iommu_group *iommu_group)
{
@@ -1185,6 +1208,8 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
struct vfio_domain *domain, *d;
struct bus_type *bus = NULL, *mdev_bus;
int ret;
+ bool resv_msi;
+ phys_addr_t resv_msi_base;
mutex_lock(&iommu->lock);
@@ -1254,6 +1279,8 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
if (ret)
goto out_domain;
+ resv_msi = vfio_iommu_has_resv_msi(iommu_group, &resv_msi_base);
+
INIT_LIST_HEAD(&domain->group_list);
list_add(&group->next, &domain->group_list);
@@ -1300,6 +1327,9 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
if (ret)
goto out_detach;
+ if (resv_msi && iommu_get_msi_cookie(domain->domain, resv_msi_base))
+ goto out_detach;
+
list_add(&domain->next, &iommu->domain_list);
mutex_unlock(&iommu->lock);
--
1.9.1
^ permalink raw reply related
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