* [PATCH v2 4/4] ARM64: dts: TM2: comply to the samsung pinctrl naming convention
From: Krzysztof Kozlowski @ 2017-01-06 6:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230041421.24448-5-andi.shyti@samsung.com>
On Fri, Dec 30, 2016 at 01:14:21PM +0900, Andi Shyti wrote:
> Change the PIN() macro definition so that it can use the macros
> from pinctrl/samsung.h header file.
>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 25 +-
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 254 ++++++++++-----------
> 2 files changed, 133 insertions(+), 146 deletions(-)
>
Thanks, applied (here and in 3/4 with fixed subject).
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/3] ARM: at91: fix cpuidle crash on SAMA5D4 Xplained board
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: linux-arm-kernel
Fix cpuidle crash on SAMA5D4 Xplained board when enable
CONFIG_ARM_AT91_CPUIDLE. Because some SoCs have the L2 cache,
we should flush the L2 cache before entering the cpu idle.
Wenyou Yang (3):
ARM: at91: flush the L2 cache before entering cpu idle
doc: binding: add new compatible for SDRAM/DDR Controller
ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc
Documentation/devicetree/bindings/arm/atmel-at91.txt | 1 +
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++
drivers/memory/atmel-sdramc.c | 1 +
5 files changed, 23 insertions(+), 2 deletions(-)
--
2.11.0
^ permalink raw reply
* [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106065947.30631-1-wenyou.yang@atmel.com>
For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache,
flush the L2 cache first before entering the cpu idle.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++
drivers/memory/atmel-sdramc.c | 1 +
2 files changed, 20 insertions(+)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index b4332b727e9c..1a60dede1a01 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -289,6 +289,24 @@ static void at91_ddr_standby(void)
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}
+static void at91_ddr_cache_standby(void)
+{
+ u32 saved_lpr;
+
+ flush_cache_all();
+ outer_disable();
+
+ saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+ at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr &
+ (~AT91_DDRSDRC_LPCB)) | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+
+ cpu_do_idle();
+
+ at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr);
+
+ outer_resume();
+}
+
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember.
*/
@@ -324,6 +342,7 @@ static const struct of_device_id const ramc_ids[] __initconst = {
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
+ { .compatible = "atmel,sama5d4-ddramc", .data = at91_ddr_cache_standby },
{ /*sentinel*/ }
};
diff --git a/drivers/memory/atmel-sdramc.c b/drivers/memory/atmel-sdramc.c
index b418b39af180..7e5c5c6c1348 100644
--- a/drivers/memory/atmel-sdramc.c
+++ b/drivers/memory/atmel-sdramc.c
@@ -48,6 +48,7 @@ static const struct of_device_id atmel_ramc_of_match[] = {
{ .compatible = "atmel,at91sam9260-sdramc", .data = &at91rm9200_caps, },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &at91sam9g45_caps, },
{ .compatible = "atmel,sama5d3-ddramc", .data = &sama5d3_caps, },
+ { .compatible = "atmel,sama5d4-ddramc", .data = &sama5d3_caps, },
{},
};
--
2.11.0
^ permalink raw reply related
* [PATCH 2/3] doc: binding: add new compatible for SDRAM/DDR Controller
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106065947.30631-1-wenyou.yang@atmel.com>
Add the new compatible "atmel,sama5d4-ddramc" for the SDRAM/DDR
Controller.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
Documentation/devicetree/bindings/arm/atmel-at91.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 29737b9b616e..9b5de6397666 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -111,6 +111,7 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
+ "atmel,sama5d4-ddramc",
- reg: Should contain registers location and length
Examples:
--
2.11.0
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106065947.30631-1-wenyou.yang@atmel.com>
Use the new compatible "atmel,sama5d4-ddramc" for the ramc of
SAMA5D2 and SAMA5D4.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index ceb9783ff7e1..b5259d85737d 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -380,7 +380,7 @@
};
ramc0: ramc at f000c000 {
- compatible = "atmel,sama5d3-ddramc";
+ compatible = "atmel,sama5d4-ddramc";
reg = <0xf000c000 0x200>;
clocks = <&ddrck>, <&mpddr_clk>;
clock-names = "ddrck", "mpddr";
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 4f60c1b7b137..603ba986858c 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -370,7 +370,7 @@
};
ramc0: ramc at f0010000 {
- compatible = "atmel,sama5d3-ddramc";
+ compatible = "atmel,sama5d4-ddramc";
reg = <0xf0010000 0x200>;
clocks = <&ddrck>, <&mpddr_clk>;
clock-names = "ddrck", "mpddr";
--
2.11.0
^ permalink raw reply related
* [PATCH] arm64: dts: exynos: Remove unsupported regulator-always-off property from TM2E
From: Krzysztof Kozlowski @ 2017-01-06 7:02 UTC (permalink / raw)
To: linux-arm-kernel
The regulator property 'regulator-always-off' is not documented and not
supported.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 1db4e7f363a9..398f5e092b02 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -25,7 +25,6 @@
&ldo25_reg {
regulator-name = "UNUSED_LDO25";
- regulator-always-off;
};
&ldo31_reg {
--
2.9.3
^ permalink raw reply related
* [PATCH v3 1/5] arm64: dts: exynos5433: TM2/E: Fix wrong information of ldo23 and ldo25
From: Krzysztof Kozlowski @ 2017-01-06 7:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483675149-32598-2-git-send-email-jcsing.lee@samsung.com>
On Fri, Jan 06, 2017 at 12:59:05PM +0900, Jaechul Lee wrote:
> From: Chanwoo Choi <cw00.choi@samsung.com>
>
> This patch fixes the wrong information of ldo23 and ldo25 on both TM2 and TM2E.
Please describe what is exactly wrong and how it affects the
system/user. This is going to the fixes so it needs a good explanation.
>
> Fixes: 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 7 ++++---
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 10 ----------
> 2 files changed, 4 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index 3b5215c..e8971f4 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -504,9 +504,9 @@
> };
>
> ldo23_reg: LDO23 {
> - regulator-name = "CAM_SEN_CORE_1.2V_AP";
> + regulator-name = "CAM_SEN_CORE_1.05V_AP";
> regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1200000>;
> + regulator-max-microvolt = <1050000>;
> };
>
> ldo24_reg: LDO24 {
> @@ -516,9 +516,10 @@
> };
>
> ldo25_reg: LDO25 {
> - regulator-name = "CAM_SEN_A2.8V_AP";
> + regulator-name = "UNUSED_LDO25";
> regulator-min-microvolt = <2800000>;
> regulator-max-microvolt = <2800000>;
> + regulator-always-off;
Don't add it. See my other patch.
Best regards,
Krzysztof
> };
>
> ldo26_reg: LDO26 {
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> index 1db4e7f..854c583 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -18,16 +18,6 @@
> compatible = "samsung,tm2e", "samsung,exynos5433";
> };
>
> -&ldo23_reg {
> - regulator-name = "CAM_SEN_CORE_1.025V_AP";
> - regulator-max-microvolt = <1050000>;
> -};
> -
> -&ldo25_reg {
> - regulator-name = "UNUSED_LDO25";
> - regulator-always-off;
> -};
> -
> &ldo31_reg {
> regulator-name = "TSP_VDD_1.8V_AP";
> regulator-min-microvolt = <1800000>;
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-06 7:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483675149-32598-3-git-send-email-jcsing.lee@samsung.com>
On Fri, Jan 06, 2017 at 12:59:06PM +0900, Jaechul Lee wrote:
> From: Andi Shyti <andi.shyti@samsung.com>
>
> Currently tm2e dts includes tm2 but there are some differences
> between the two boards and tm2 has some properties that tm2e
> doesn't have.
>
> That's why it's important to keep the two dts files independent
> and put all the commonalities in a tm2-common.dtsi file.
>
> At the current status the only two differences between the two
> dts files (besides the board name) are ldo31 and ldo38.
>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1118 +++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1153 +-------------------
Like talking to a wall. Without any feedback. If my instructions were
wrong (and it is not possible to detect rename) then please say it (you
can add personal comments after separator ---).
As of now because it is third time without any explanation: NACK.
Best regards,
Krzysztof
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 22 +-
> 3 files changed, 1163 insertions(+), 1130 deletions(-)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> rewrite arch/arm64/boot/dts/exynos/exynos5433-tm2.dts (98%)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> new file mode 100644
> index 0000000..c43f9a3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -0,0 +1,1118 @@
> +/*
> + * SAMSUNG Exynos5433 TM2 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Common device tree source file for Samsung's TM2 and TM2E boards
> + * which are based on Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos5433.dtsi"
> +#include <dt-bindings/clock/samsung,s2mps11.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "Samsung TM2 board";
> + compatible = "samsung,tm2", "samsung,exynos5433";
> +
> + aliases {
> + gsc0 = &gsc_0;
> + gsc1 = &gsc_1;
> + gsc2 = &gsc_2;
> + pinctrl0 = &pinctrl_alive;
> + pinctrl1 = &pinctrl_aud;
> + pinctrl2 = &pinctrl_cpif;
> + pinctrl3 = &pinctrl_ese;
> + pinctrl4 = &pinctrl_finger;
> + pinctrl5 = &pinctrl_fsys;
> + pinctrl6 = &pinctrl_imem;
> + pinctrl7 = &pinctrl_nfc;
> + pinctrl8 = &pinctrl_peric;
> + pinctrl9 = &pinctrl_touch;
> + serial0 = &serial_0;
> + serial1 = &serial_1;
> + serial2 = &serial_2;
> + serial3 = &serial_3;
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + spi3 = &spi_3;
> + spi4 = &spi_4;
> + mshc0 = &mshc_0;
> + mshc2 = &mshc_2;
> + };
> +
> + chosen {
> + stdout-path = &serial_1;
> + };
> +
> + memory at 20000000 {
> + device_type = "memory";
> + reg = <0x0 0x20000000 0x0 0xc0000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + power-key {
> + gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + label = "power key";
> + debounce-interval = <10>;
> + };
> +
> + volume-up-key {
> + gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEUP>;
> + label = "volume-up key";
> + debounce-interval = <10>;
> + };
> +
> + volume-down-key {
> + gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEDOWN>;
> + label = "volume-down key";
> + debounce-interval = <10>;
> + };
> +
> + homepage-key {
> + gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_MENU>;
> + label = "homepage key";
> + debounce-interval = <10>;
> + };
> + };
> +
> + i2c_max98504: i2c-gpio-0 {
> + compatible = "i2c-gpio";
> + gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
> + &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + max98504: max98504 at 31 {
> + compatible = "maxim,max98504";
> + reg = <0x31>;
> + maxim,rx-path = <1>;
> + maxim,tx-path = <1>;
> + maxim,tx-channel-mask = <3>;
> + maxim,tx-channel-source = <2>;
> + };
> + };
> +
> + sound {
> + compatible = "samsung,tm2-audio";
> + audio-codec = <&wm5110>;
> + i2s-controller = <&i2s0>;
> + audio-amplifier = <&max98504>;
> + mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
> + model = "wm5110";
> + samsung,audio-routing =
> + /* Headphone */
> + "HP", "HPOUT1L",
> + "HP", "HPOUT1R",
> +
> + /* Speaker */
> + "SPK", "SPKOUT",
> + "SPKOUT", "HPOUT2L",
> + "SPKOUT", "HPOUT2R",
> +
> + /* Receiver */
> + "RCV", "HPOUT3L",
> + "RCV", "HPOUT3R";
> + status = "okay";
> + };
> +};
> +
> +&adc {
> + vdd-supply = <&ldo3_reg>;
> + status = "okay";
> +
> + thermistor-ap {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 0>;
> + };
> +
> + thermistor-battery {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 1>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + thermistor-charger {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 2>;
> + };
> +};
> +
> +&bus_g2d_400 {
> + devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
> + vdd-supply = <&buck4_reg>;
> + exynos,saturation-ratio = <10>;
> + status = "okay";
> +};
> +
> +&bus_g2d_266 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_gscl {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_hevc {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_jpeg {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_mfc {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_mscl {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_noc0 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_noc1 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_noc2 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&cmu_aud {
> + assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
> + assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> +};
> +
> +&cmu_fsys {
> + assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> + <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
> + <&cmu_top CLK_DIV_SCLK_USBDRD30>,
> + <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> + assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> + <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> + <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> + assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
> + <66700000>, <66700000>;
> +};
> +
> +&cmu_gscl {
> + assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
> + <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
> + assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
> + <&cmu_top CLK_ACLK_GSCL_333>;
> +};
> +
> +&cmu_mfc {
> + assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
> + assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
> +};
> +
> +&cmu_mscl {
> + assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
> + <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> + <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
> + <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
> + assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
> + <&cmu_top CLK_SCLK_JPEG_MSCL>,
> + <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> +};
> +
> +&cpu0 {
> + cpu-supply = <&buck3_reg>;
> +};
> +
> +&cpu4 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&decon {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&dsi {
> + status = "okay";
> + vddcore-supply = <&ldo6_reg>;
> + vddio-supply = <&ldo7_reg>;
> + samsung,pll-clock-frequency = <24000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&te_irq>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + reg = <1>;
> +
> + dsi_out: endpoint {
> + samsung,burst-clock-frequency = <512000000>;
> + samsung,esc-clock-frequency = <16000000>;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_0 {
> + status = "okay";
> + clock-frequency = <2500000>;
> +
> + s2mps13-pmic at 66 {
> + compatible = "samsung,s2mps13-pmic";
> + interrupt-parent = <&gpa0>;
> + interrupts = <7 IRQ_TYPE_NONE>;
> + reg = <0x66>;
> + samsung,s2mps11-wrstbi-ground;
> +
> + s2mps13_osc: clocks {
> + compatible = "samsung,s2mps13-clk";
> + #clock-cells = <1>;
> + clock-output-names = "s2mps13_ap", "s2mps13_cp",
> + "s2mps13_bt";
> + };
> +
> + regulators: regulators {
> + ldo1_reg: LDO1 {
> + regulator-name = "VDD_ALIVE_0.9V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + regulator-name = "VDDQ_MMC2_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "VDD1_E_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + regulator-name = "VDD10_MIF_PLL_1.0V_AP";
> + regulator-min-microvolt = <1300000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo5_reg: LDO5 {
> + regulator-name = "VDD10_DPLL_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo6_reg: LDO6 {
> + regulator-name = "VDD10_MIPI2L_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo7_reg: LDO7 {
> + regulator-name = "VDD18_MIPI2L_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo8_reg: LDO8 {
> + regulator-name = "VDD18_LLI_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo9_reg: LDO9 {
> + regulator-name = "VDD18_ABB_ETC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo10_reg: LDO10 {
> + regulator-name = "VDD33_USB30_3.0V_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo11_reg: LDO11 {
> + regulator-name = "VDD_INT_M_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo12_reg: LDO12 {
> + regulator-name = "VDD_KFC_M_1.1V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + };
> +
> + ldo13_reg: LDO13 {
> + regulator-name = "VDD_G3D_M_0.95V_AP";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <950000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo14_reg: LDO14 {
> + regulator-name = "VDDQ_M1_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo15_reg: LDO15 {
> + regulator-name = "VDDQ_M2_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo16_reg: LDO16 {
> + regulator-name = "VDDQ_EFUSE";
> + regulator-min-microvolt = <1400000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-always-on;
> + };
> +
> + ldo17_reg: LDO17 {
> + regulator-name = "V_TFLASH_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo18_reg: LDO18 {
> + regulator-name = "V_CODEC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo19_reg: LDO19 {
> + regulator-name = "VDDA_1.8V_COMP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo20_reg: LDO20 {
> + regulator-name = "VCC_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + ldo21_reg: LDO21 {
> + regulator-name = "VT_CAM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo22_reg: LDO22 {
> + regulator-name = "CAM_IO_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo23_reg: LDO23 {
> + regulator-name = "CAM_SEN_CORE_1.05V_AP";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + ldo24_reg: LDO24 {
> + regulator-name = "VT_CAM_1.2V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo25_reg: LDO25 {
> + regulator-name = "UNUSED_LDO25";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-off;
> + };
> +
> + ldo26_reg: LDO26 {
> + regulator-name = "CAM_AF_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo27_reg: LDO27 {
> + regulator-name = "VCC_3.0V_LCD_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo28_reg: LDO28 {
> + regulator-name = "VCC_1.8V_LCD_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo29_reg: LDO29 {
> + regulator-name = "VT_CAM_2.8V";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo30_reg: LDO30 {
> + regulator-name = "TSP_AVDD_3.3V_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + /*
> + * LDO31 differs from target to target,
> + * its definition is in the .dts
> + */
> +
> + ldo32_reg: LDO32 {
> + regulator-name = "VTOUCH_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo33_reg: LDO33 {
> + regulator-name = "VTOUCH_LED_3.3V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-ramp-delay = <12500>;
> + };
> +
> + ldo34_reg: LDO34 {
> + regulator-name = "VCC_1.8V_MHL_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <2100000>;
> + };
> +
> + ldo35_reg: LDO35 {
> + regulator-name = "OIS_VM_2.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo36_reg: LDO36 {
> + regulator-name = "VSIL_1.0V";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + };
> +
> + ldo37_reg: LDO37 {
> + regulator-name = "VF_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + /*
> + * LDO38 differs from target to target,
> + * its definition is in the .dts
> + */
> +
> + ldo39_reg: LDO39 {
> + regulator-name = "V_HRM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo40_reg: LDO40 {
> + regulator-name = "V_HRM_3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + buck1_reg: BUCK1 {
> + regulator-name = "VDD_MIF_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck2_reg: BUCK2 {
> + regulator-name = "VDD_EGL_1.0V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck3_reg: BUCK3 {
> + regulator-name = "VDD_KFC_1.0V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck4_reg: BUCK4 {
> + regulator-name = "VDD_INT_0.95V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck5_reg: BUCK5 {
> + regulator-name = "VDD_DISP_CAM0_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck6_reg: BUCK6 {
> + regulator-name = "VDD_G3D_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck7_reg: BUCK7 {
> + regulator-name = "VDD_MEM1_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + buck8_reg: BUCK8 {
> + regulator-name = "VDD_LLDO_1.35V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck9_reg: BUCK9 {
> + regulator-name = "VDD_MLDO_2.0V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck10_reg: BUCK10 {
> + regulator-name = "vdd_mem2";
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_8 {
> + status = "okay";
> +
> + max77843 at 66 {
> + compatible = "maxim,max77843";
> + interrupt-parent = <&gpa1>;
> + interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> + reg = <0x66>;
> +
> + muic: max77843-muic {
> + compatible = "maxim,max77843-muic";
> + };
> +
> + regulators {
> + compatible = "maxim,max77843-regulator";
> + safeout1_reg: SAFEOUT1 {
> + regulator-name = "SAFEOUT1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + safeout2_reg: SAFEOUT2 {
> + regulator-name = "SAFEOUT2";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + charger_reg: CHARGER {
> + regulator-name = "CHARGER";
> + regulator-min-microamp = <100000>;
> + regulator-max-microamp = <3150000>;
> + };
> + };
> +
> + haptic: max77843-haptic {
> + compatible = "maxim,max77843-haptic";
> + haptic-supply = <&ldo38_reg>;
> + pwms = <&pwm 0 33670 0>;
> + pwm-names = "haptic";
> + };
> + };
> +};
> +
> +&i2s0 {
> + status = "okay";
> +};
> +
> +&mshc_0 {
> + status = "okay";
> + num-slots = <1>;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + cap-mmc-highspeed;
> + non-removable;
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <0 4>;
> + samsung,dw-mshc-ddr-timing = <0 2>;
> + samsung,dw-mshc-hs400-timing = <0 3>;
> + samsung,read-strobe-delay = <90>;
> + fifo-depth = <0x80>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
> + &sd0_bus8 &sd0_rdqs>;
> + bus-width = <8>;
> + assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
> + assigned-clock-rates = <800000000>;
> +};
> +
> +&mshc_2 {
> + status = "okay";
> + num-slots = <1>;
> + cap-sd-highspeed;
> + disable-wp;
> + cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <0 4>;
> + samsung,dw-mshc-ddr-timing = <0 2>;
> + fifo-depth = <0x80>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
> + bus-width = <4>;
> +};
> +
> +&ppmu_d0_general {
> + status = "okay";
> + events {
> + ppmu_event0_d0_general: ppmu-event0-d0-general {
> + event-name = "ppmu-event0-d0-general";
> + };
> + };
> +};
> +
> +&ppmu_d1_general {
> + status = "okay";
> + events {
> + ppmu_event0_d1_general: ppmu-event0-d1-general {
> + event-name = "ppmu-event0-d1-general";
> + };
> + };
> +};
> +
> +&pinctrl_alive {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_alive>;
> +
> + initial_alive: initial-state {
> + PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpa0-1, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpa0-3, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-4, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpa0-6, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-7, NONE, FAST_SR1);
> +
> + PIN(INPUT, gpa1-0, UP, FAST_SR1);
> + PIN(INPUT, gpa1-1, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-2, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpa1-5, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-6, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-7, NONE, FAST_SR1);
> +
> + PIN(INPUT, gpa2-0, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-1, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-2, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpa2-4, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpa2-7, NONE, FAST_SR1);
> +
> + PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-2, NONE, FAST_SR1);
> + PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-4, NONE, FAST_SR1);
> + PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf1-0, NONE, FAST_SR1);
> + PIN(INPUT, gpf1-1, NONE, FAST_SR1);
> + PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf1-4, UP, FAST_SR1);
> + PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
> + PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf3-2, NONE, FAST_SR1);
> + PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
> + PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
> + PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
> + };
> +
> + te_irq: te_irq {
> + samsung,pins = "gpf1-3";
> + samsung,pin-function = <0xf>;
> + };
> +};
> +
> +&pinctrl_cpif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_cpif>;
> +
> + initial_cpif: initial-state {
> + PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_ese {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_ese>;
> +
> + initial_ese: initial-state {
> + PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_fsys {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_fsys>;
> +
> + initial_fsys: initial-state {
> + PIN(INPUT, gpr3-0, NONE, FAST_SR1);
> + PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpr3-7, NONE, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_imem {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_imem>;
> +
> + initial_imem: initial-state {
> + PIN(INPUT, gpf0-0, UP, FAST_SR1);
> + PIN(INPUT, gpf0-1, UP, FAST_SR1);
> + PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf0-3, UP, FAST_SR1);
> + PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpf0-5, NONE, FAST_SR1);
> + PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf0-7, UP, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_nfc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_nfc>;
> +
> + initial_nfc: initial-state {
> + PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_peric {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_peric>;
> +
> + initial_peric: initial-state {
> + PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-2, NONE, FAST_SR1);
> + PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpc3-4, NONE, FAST_SR1);
> + PIN(INPUT, gpc3-5, NONE, FAST_SR1);
> + PIN(INPUT, gpc3-6, NONE, FAST_SR1);
> + PIN(INPUT, gpc3-7, NONE, FAST_SR1);
> +
> + PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
> + PIN(2, gpg0-1, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd4-0, NONE, FAST_SR1);
> + PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd8-1, UP, FAST_SR1);
> +
> + PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_touch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_touch>;
> +
> + initial_touch: initial-state {
> + PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pwm {
> + pinctrl-0 = <&pwm0_out>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mic {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&pmu_system_controller {
> + assigned-clocks = <&pmu_system_controller 0>;
> + assigned-clock-parents = <&xxti>;
> +};
> +
> +&serial_1 {
> + status = "okay";
> +};
> +
> +&spi_1 {
> + cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + wm5110: wm5110-codec at 0 {
> + compatible = "wlf,wm5110";
> + reg = <0x0>;
> + spi-max-frequency = <20000000>;
> + interrupt-parent = <&gpa0>;
> + interrupts = <4 IRQ_TYPE_NONE>;
> + clocks = <&pmu_system_controller 0>,
> + <&s2mps13_osc S2MPS11_CLK_BT>;
> + clock-names = "mclk1", "mclk2";
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + wlf,micd-detect-debounce = <300>;
> + wlf,micd-bias-start-time = <0x1>;
> + wlf,micd-rate = <0x7>;
> + wlf,micd-dbtime = <0x1>;
> + wlf,micd-force-micbias;
> + wlf,micd-configs = <0x0 1 0>;
> + wlf,hpdet-channel = <1>;
> + wlf,gpsw = <0x1>;
> + wlf,inmode = <2 0 2 0>;
> +
> + wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
> + wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
> +
> + /* core supplies */
> + AVDD-supply = <&ldo18_reg>;
> + DBVDD1-supply = <&ldo18_reg>;
> + CPVDD-supply = <&ldo18_reg>;
> + DBVDD2-supply = <&ldo18_reg>;
> + DBVDD3-supply = <&ldo18_reg>;
> +
> + controller-data {
> + samsung,spi-feedback-delay = <0>;
> + };
> + };
> +};
> +
> +&timer {
> + clock-frequency = <24000000>;
> +};
> +
> +&tmu_atlas0 {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_apollo {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_g3d {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd30 {
> + vdd33-supply = <&ldo10_reg>;
> + vdd10-supply = <&ldo6_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd_dwc3_0 {
> + dr_mode = "otg";
> +};
> +
> +&usbdrd30_phy {
> + vbus-supply = <&safeout1_reg>;
> + status = "okay";
> +};
> +
> +&xxti {
> + clock-frequency = <24000000>;
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> dissimilarity index 98%
> index e8971f4..d30b45a 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -1,1120 +1,33 @@
> -/*
> - * SAMSUNG Exynos5433 TM2 board device tree source
> - *
> - * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> - *
> - * Device tree source file for Samsung's TM2 board which is based on
> - * Samsung Exynos5433 SoC.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -/dts-v1/;
> -#include "exynos5433.dtsi"
> -#include <dt-bindings/clock/samsung,s2mps11.h>
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/input/input.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> -
> -/ {
> - model = "Samsung TM2 board";
> - compatible = "samsung,tm2", "samsung,exynos5433";
> -
> - aliases {
> - gsc0 = &gsc_0;
> - gsc1 = &gsc_1;
> - gsc2 = &gsc_2;
> - pinctrl0 = &pinctrl_alive;
> - pinctrl1 = &pinctrl_aud;
> - pinctrl2 = &pinctrl_cpif;
> - pinctrl3 = &pinctrl_ese;
> - pinctrl4 = &pinctrl_finger;
> - pinctrl5 = &pinctrl_fsys;
> - pinctrl6 = &pinctrl_imem;
> - pinctrl7 = &pinctrl_nfc;
> - pinctrl8 = &pinctrl_peric;
> - pinctrl9 = &pinctrl_touch;
> - serial0 = &serial_0;
> - serial1 = &serial_1;
> - serial2 = &serial_2;
> - serial3 = &serial_3;
> - spi0 = &spi_0;
> - spi1 = &spi_1;
> - spi2 = &spi_2;
> - spi3 = &spi_3;
> - spi4 = &spi_4;
> - mshc0 = &mshc_0;
> - mshc2 = &mshc_2;
> - };
> -
> - chosen {
> - stdout-path = &serial_1;
> - };
> -
> - memory at 20000000 {
> - device_type = "memory";
> - reg = <0x0 0x20000000 0x0 0xc0000000>;
> - };
> -
> - gpio-keys {
> - compatible = "gpio-keys";
> -
> - power-key {
> - gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_POWER>;
> - label = "power key";
> - debounce-interval = <10>;
> - };
> -
> - volume-up-key {
> - gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEUP>;
> - label = "volume-up key";
> - debounce-interval = <10>;
> - };
> -
> - volume-down-key {
> - gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEDOWN>;
> - label = "volume-down key";
> - debounce-interval = <10>;
> - };
> -
> - homepage-key {
> - gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_MENU>;
> - label = "homepage key";
> - debounce-interval = <10>;
> - };
> - };
> -
> - i2c_max98504: i2c-gpio-0 {
> - compatible = "i2c-gpio";
> - gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
> - &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
> - i2c-gpio,delay-us = <2>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "okay";
> -
> - max98504: max98504 at 31 {
> - compatible = "maxim,max98504";
> - reg = <0x31>;
> - maxim,rx-path = <1>;
> - maxim,tx-path = <1>;
> - maxim,tx-channel-mask = <3>;
> - maxim,tx-channel-source = <2>;
> - };
> - };
> -
> - sound {
> - compatible = "samsung,tm2-audio";
> - audio-codec = <&wm5110>;
> - i2s-controller = <&i2s0>;
> - audio-amplifier = <&max98504>;
> - mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
> - model = "wm5110";
> - samsung,audio-routing =
> - /* Headphone */
> - "HP", "HPOUT1L",
> - "HP", "HPOUT1R",
> -
> - /* Speaker */
> - "SPK", "SPKOUT",
> - "SPKOUT", "HPOUT2L",
> - "SPKOUT", "HPOUT2R",
> -
> - /* Receiver */
> - "RCV", "HPOUT3L",
> - "RCV", "HPOUT3R";
> - status = "okay";
> - };
> -};
> -
> -&adc {
> - vdd-supply = <&ldo3_reg>;
> - status = "okay";
> -
> - thermistor-ap {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 0>;
> - };
> -
> - thermistor-battery {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 1>;
> - #thermal-sensor-cells = <0>;
> - };
> -
> - thermistor-charger {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 2>;
> - };
> -};
> -
> -&bus_g2d_400 {
> - devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
> - vdd-supply = <&buck4_reg>;
> - exynos,saturation-ratio = <10>;
> - status = "okay";
> -};
> -
> -&bus_g2d_266 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_gscl {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_hevc {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_jpeg {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_mfc {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_mscl {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc0 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc1 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc2 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&cmu_aud {
> - assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
> - assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> -};
> -
> -&cmu_fsys {
> - assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> - <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
> - <&cmu_top CLK_DIV_SCLK_USBDRD30>,
> - <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> - assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> - <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> - <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> - assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
> - <66700000>, <66700000>;
> -};
> -
> -&cmu_gscl {
> - assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
> - <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
> - <&cmu_top CLK_ACLK_GSCL_333>;
> -};
> -
> -&cmu_mfc {
> - assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
> -};
> -
> -&cmu_mscl {
> - assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
> - <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
> - <&cmu_top CLK_SCLK_JPEG_MSCL>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> -};
> -
> -&cpu0 {
> - cpu-supply = <&buck3_reg>;
> -};
> -
> -&cpu4 {
> - cpu-supply = <&buck2_reg>;
> -};
> -
> -&decon {
> - status = "okay";
> -
> - i80-if-timings {
> - };
> -};
> -
> -&dsi {
> - status = "okay";
> - vddcore-supply = <&ldo6_reg>;
> - vddio-supply = <&ldo7_reg>;
> - samsung,pll-clock-frequency = <24000000>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&te_irq>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port at 1 {
> - reg = <1>;
> -
> - dsi_out: endpoint {
> - samsung,burst-clock-frequency = <512000000>;
> - samsung,esc-clock-frequency = <16000000>;
> - };
> - };
> - };
> -};
> -
> -&hsi2c_0 {
> - status = "okay";
> - clock-frequency = <2500000>;
> -
> - s2mps13-pmic at 66 {
> - compatible = "samsung,s2mps13-pmic";
> - interrupt-parent = <&gpa0>;
> - interrupts = <7 IRQ_TYPE_NONE>;
> - reg = <0x66>;
> - samsung,s2mps11-wrstbi-ground;
> -
> - s2mps13_osc: clocks {
> - compatible = "samsung,s2mps13-clk";
> - #clock-cells = <1>;
> - clock-output-names = "s2mps13_ap", "s2mps13_cp",
> - "s2mps13_bt";
> - };
> -
> - regulators {
> - ldo1_reg: LDO1 {
> - regulator-name = "VDD_ALIVE_0.9V_AP";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <900000>;
> - regulator-always-on;
> - };
> -
> - ldo2_reg: LDO2 {
> - regulator-name = "VDDQ_MMC2_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo3_reg: LDO3 {
> - regulator-name = "VDD1_E_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo4_reg: LDO4 {
> - regulator-name = "VDD10_MIF_PLL_1.0V_AP";
> - regulator-min-microvolt = <1300000>;
> - regulator-max-microvolt = <1300000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo5_reg: LDO5 {
> - regulator-name = "VDD10_DPLL_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo6_reg: LDO6 {
> - regulator-name = "VDD10_MIPI2L_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo7_reg: LDO7 {
> - regulator-name = "VDD18_MIPI2L_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo8_reg: LDO8 {
> - regulator-name = "VDD18_LLI_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo9_reg: LDO9 {
> - regulator-name = "VDD18_ABB_ETC_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo10_reg: LDO10 {
> - regulator-name = "VDD33_USB30_3.0V_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo11_reg: LDO11 {
> - regulator-name = "VDD_INT_M_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo12_reg: LDO12 {
> - regulator-name = "VDD_KFC_M_1.1V_AP";
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1350000>;
> - regulator-always-on;
> - };
> -
> - ldo13_reg: LDO13 {
> - regulator-name = "VDD_G3D_M_0.95V_AP";
> - regulator-min-microvolt = <950000>;
> - regulator-max-microvolt = <950000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo14_reg: LDO14 {
> - regulator-name = "VDDQ_M1_LDO_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo15_reg: LDO15 {
> - regulator-name = "VDDQ_M2_LDO_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo16_reg: LDO16 {
> - regulator-name = "VDDQ_EFUSE";
> - regulator-min-microvolt = <1400000>;
> - regulator-max-microvolt = <3400000>;
> - regulator-always-on;
> - };
> -
> - ldo17_reg: LDO17 {
> - regulator-name = "V_TFLASH_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo18_reg: LDO18 {
> - regulator-name = "V_CODEC_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo19_reg: LDO19 {
> - regulator-name = "VDDA_1.8V_COMP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo20_reg: LDO20 {
> - regulator-name = "VCC_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - };
> -
> - ldo21_reg: LDO21 {
> - regulator-name = "VT_CAM_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo22_reg: LDO22 {
> - regulator-name = "CAM_IO_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo23_reg: LDO23 {
> - regulator-name = "CAM_SEN_CORE_1.05V_AP";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - };
> -
> - ldo24_reg: LDO24 {
> - regulator-name = "VT_CAM_1.2V";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo25_reg: LDO25 {
> - regulator-name = "UNUSED_LDO25";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-off;
> - };
> -
> - ldo26_reg: LDO26 {
> - regulator-name = "CAM_AF_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo27_reg: LDO27 {
> - regulator-name = "VCC_3.0V_LCD_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo28_reg: LDO28 {
> - regulator-name = "VCC_1.8V_LCD_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo29_reg: LDO29 {
> - regulator-name = "VT_CAM_2.8V";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo30_reg: LDO30 {
> - regulator-name = "TSP_AVDD_3.3V_AP";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - ldo31_reg: LDO31 {
> - regulator-name = "TSP_VDD_1.85V_AP";
> - regulator-min-microvolt = <1850000>;
> - regulator-max-microvolt = <1850000>;
> - };
> -
> - ldo32_reg: LDO32 {
> - regulator-name = "VTOUCH_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo33_reg: LDO33 {
> - regulator-name = "VTOUCH_LED_3.3V";
> - regulator-min-microvolt = <2500000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-ramp-delay = <12500>;
> - };
> -
> - ldo34_reg: LDO34 {
> - regulator-name = "VCC_1.8V_MHL_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <2100000>;
> - };
> -
> - ldo35_reg: LDO35 {
> - regulator-name = "OIS_VM_2.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo36_reg: LDO36 {
> - regulator-name = "VSIL_1.0V";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - };
> -
> - ldo37_reg: LDO37 {
> - regulator-name = "VF_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo38_reg: LDO38 {
> - regulator-name = "VCC_3.0V_MOTOR_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo39_reg: LDO39 {
> - regulator-name = "V_HRM_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo40_reg: LDO40 {
> - regulator-name = "V_HRM_3.3V";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - buck1_reg: BUCK1 {
> - regulator-name = "VDD_MIF_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck2_reg: BUCK2 {
> - regulator-name = "VDD_EGL_1.0V_AP";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <1300000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck3_reg: BUCK3 {
> - regulator-name = "VDD_KFC_1.0V_AP";
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck4_reg: BUCK4 {
> - regulator-name = "VDD_INT_0.95V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck5_reg: BUCK5 {
> - regulator-name = "VDD_DISP_CAM0_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck6_reg: BUCK6 {
> - regulator-name = "VDD_G3D_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck7_reg: BUCK7 {
> - regulator-name = "VDD_MEM1_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - buck8_reg: BUCK8 {
> - regulator-name = "VDD_LLDO_1.35V_AP";
> - regulator-min-microvolt = <1350000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - buck9_reg: BUCK9 {
> - regulator-name = "VDD_MLDO_2.0V_AP";
> - regulator-min-microvolt = <1350000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - buck10_reg: BUCK10 {
> - regulator-name = "vdd_mem2";
> - regulator-min-microvolt = <550000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - };
> - };
> - };
> -};
> -
> -&hsi2c_8 {
> - status = "okay";
> -
> - max77843 at 66 {
> - compatible = "maxim,max77843";
> - interrupt-parent = <&gpa1>;
> - interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> - reg = <0x66>;
> -
> - muic: max77843-muic {
> - compatible = "maxim,max77843-muic";
> - };
> -
> - regulators {
> - compatible = "maxim,max77843-regulator";
> - safeout1_reg: SAFEOUT1 {
> - regulator-name = "SAFEOUT1";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <4950000>;
> - };
> -
> - safeout2_reg: SAFEOUT2 {
> - regulator-name = "SAFEOUT2";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <4950000>;
> - };
> -
> - charger_reg: CHARGER {
> - regulator-name = "CHARGER";
> - regulator-min-microamp = <100000>;
> - regulator-max-microamp = <3150000>;
> - };
> - };
> -
> - haptic: max77843-haptic {
> - compatible = "maxim,max77843-haptic";
> - haptic-supply = <&ldo38_reg>;
> - pwms = <&pwm 0 33670 0>;
> - pwm-names = "haptic";
> - };
> - };
> -};
> -
> -&i2s0 {
> - status = "okay";
> -};
> -
> -&mshc_0 {
> - status = "okay";
> - num-slots = <1>;
> - mmc-hs200-1_8v;
> - mmc-hs400-1_8v;
> - cap-mmc-highspeed;
> - non-removable;
> - card-detect-delay = <200>;
> - samsung,dw-mshc-ciu-div = <3>;
> - samsung,dw-mshc-sdr-timing = <0 4>;
> - samsung,dw-mshc-ddr-timing = <0 2>;
> - samsung,dw-mshc-hs400-timing = <0 3>;
> - samsung,read-strobe-delay = <90>;
> - fifo-depth = <0x80>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
> - &sd0_bus8 &sd0_rdqs>;
> - bus-width = <8>;
> - assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
> - assigned-clock-rates = <800000000>;
> -};
> -
> -&mshc_2 {
> - status = "okay";
> - num-slots = <1>;
> - cap-sd-highspeed;
> - disable-wp;
> - cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
> - cd-inverted;
> - card-detect-delay = <200>;
> - samsung,dw-mshc-ciu-div = <3>;
> - samsung,dw-mshc-sdr-timing = <0 4>;
> - samsung,dw-mshc-ddr-timing = <0 2>;
> - fifo-depth = <0x80>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
> - bus-width = <4>;
> -};
> -
> -&ppmu_d0_general {
> - status = "okay";
> - events {
> - ppmu_event0_d0_general: ppmu-event0-d0-general {
> - event-name = "ppmu-event0-d0-general";
> - };
> - };
> -};
> -
> -&ppmu_d1_general {
> - status = "okay";
> - events {
> - ppmu_event0_d1_general: ppmu-event0-d1-general {
> - event-name = "ppmu-event0-d1-general";
> - };
> - };
> -};
> -
> -&pinctrl_alive {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_alive>;
> -
> - initial_alive: initial-state {
> - PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-3, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-6, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa1-0, UP, FAST_SR1);
> - PIN(INPUT, gpa1-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpa1-5, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-6, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa2-0, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf1-0, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-1, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf1-4, UP, FAST_SR1);
> - PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf3-2, NONE, FAST_SR1);
> - PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
> - PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
> - PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
> - };
> -
> - te_irq: te_irq {
> - samsung,pins = "gpf1-3";
> - samsung,pin-function = <0xf>;
> - };
> -};
> -
> -&pinctrl_cpif {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_cpif>;
> -
> - initial_cpif: initial-state {
> - PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_ese {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_ese>;
> -
> - initial_ese: initial-state {
> - PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_fsys {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_fsys>;
> -
> - initial_fsys: initial-state {
> - PIN(INPUT, gpr3-0, NONE, FAST_SR1);
> - PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-7, NONE, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_imem {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_imem>;
> -
> - initial_imem: initial-state {
> - PIN(INPUT, gpf0-0, UP, FAST_SR1);
> - PIN(INPUT, gpf0-1, UP, FAST_SR1);
> - PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-3, UP, FAST_SR1);
> - PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-5, NONE, FAST_SR1);
> - PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-7, UP, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_nfc {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_nfc>;
> -
> - initial_nfc: initial-state {
> - PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_peric {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_peric>;
> -
> - initial_peric: initial-state {
> - PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-2, NONE, FAST_SR1);
> - PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc3-4, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-5, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-6, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-7, NONE, FAST_SR1);
> -
> - PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
> - PIN(2, gpg0-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd4-0, NONE, FAST_SR1);
> - PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd8-1, UP, FAST_SR1);
> -
> - PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_touch {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_touch>;
> -
> - initial_touch: initial-state {
> - PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pwm {
> - pinctrl-0 = <&pwm0_out>;
> - pinctrl-names = "default";
> - status = "okay";
> -};
> -
> -&mic {
> - status = "okay";
> -
> - i80-if-timings {
> - };
> -};
> -
> -&pmu_system_controller {
> - assigned-clocks = <&pmu_system_controller 0>;
> - assigned-clock-parents = <&xxti>;
> -};
> -
> -&serial_1 {
> - status = "okay";
> -};
> -
> -&spi_1 {
> - cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> - status = "okay";
> -
> - wm5110: wm5110-codec at 0 {
> - compatible = "wlf,wm5110";
> - reg = <0x0>;
> - spi-max-frequency = <20000000>;
> - interrupt-parent = <&gpa0>;
> - interrupts = <4 IRQ_TYPE_NONE>;
> - clocks = <&pmu_system_controller 0>,
> - <&s2mps13_osc S2MPS11_CLK_BT>;
> - clock-names = "mclk1", "mclk2";
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - wlf,micd-detect-debounce = <300>;
> - wlf,micd-bias-start-time = <0x1>;
> - wlf,micd-rate = <0x7>;
> - wlf,micd-dbtime = <0x1>;
> - wlf,micd-force-micbias;
> - wlf,micd-configs = <0x0 1 0>;
> - wlf,hpdet-channel = <1>;
> - wlf,gpsw = <0x1>;
> - wlf,inmode = <2 0 2 0>;
> -
> - wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
> - wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
> -
> - /* core supplies */
> - AVDD-supply = <&ldo18_reg>;
> - DBVDD1-supply = <&ldo18_reg>;
> - CPVDD-supply = <&ldo18_reg>;
> - DBVDD2-supply = <&ldo18_reg>;
> - DBVDD3-supply = <&ldo18_reg>;
> -
> - controller-data {
> - samsung,spi-feedback-delay = <0>;
> - };
> - };
> -};
> -
> -&timer {
> - clock-frequency = <24000000>;
> -};
> -
> -&tmu_atlas0 {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&tmu_apollo {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&tmu_g3d {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&usbdrd30 {
> - vdd33-supply = <&ldo10_reg>;
> - vdd10-supply = <&ldo6_reg>;
> - status = "okay";
> -};
> -
> -&usbdrd_dwc3_0 {
> - dr_mode = "otg";
> -};
> -
> -&usbdrd30_phy {
> - vbus-supply = <&safeout1_reg>;
> - status = "okay";
> -};
> -
> -&xxti {
> - clock-frequency = <24000000>;
> -};
> +/*
> + * SAMSUNG Exynos5433 TM2 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung's TM2 board which is based on
> + * Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "exynos5433-tm2-common.dtsi"
> +
> +/ {
> + model = "Samsung TM2E board";
> + compatible = "samsung,tm2e", "samsung,exynos5433";
> +};
> +
> +®ulators {
> + ldo31_reg: LDO31 {
> + regulator-name = "TSP_VDD_1.85V_AP";
> + regulator-min-microvolt = <1850000>;
> + regulator-max-microvolt = <1850000>;
> + };
> +
> + ldo38_reg: LDO38 {
> + regulator-name = "VCC_3.0V_MOTOR_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> index 854c583..53e361f 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -11,21 +11,23 @@
> * published by the Free Software Foundation.
> */
>
> -#include "exynos5433-tm2.dts"
> +#include "exynos5433-tm2-common.dtsi"
>
> / {
> model = "Samsung TM2E board";
> compatible = "samsung,tm2e", "samsung,exynos5433";
> };
>
> -&ldo31_reg {
> - regulator-name = "TSP_VDD_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> -};
> +®ulators {
> + ldo31_reg: LDO31 {
> + regulator-name = "TSP_VDD_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
>
> -&ldo38_reg {
> - regulator-name = "VCC_3.3V_MOTOR_AP";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> + ldo38_reg: LDO38 {
> + regulator-name = "VCC_3.3V_MOTOR_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> };
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3 1/5] arm64: dts: exynos5433: TM2/E: Fix wrong information of ldo23 and ldo25
From: Chanwoo Choi @ 2017-01-06 7:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106070539.wd3kfhi77pa5ekcy@kozik-lap>
On 2017? 01? 06? 16:05, Krzysztof Kozlowski wrote:
> On Fri, Jan 06, 2017 at 12:59:05PM +0900, Jaechul Lee wrote:
>> From: Chanwoo Choi <cw00.choi@samsung.com>
>>
>> This patch fixes the wrong information of ldo23 and ldo25 on both TM2 and TM2E.
>
> Please describe what is exactly wrong and how it affects the
> system/user. This is going to the fixes so it needs a good explanation.
When I posted the patch[1], I refer to the old schematic document of both TM2 and TM2E.
[1] 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
After checking the highest version of schematic document of both TM2 and TM2E,
there is no difference of ldo23/ldo25 on both TM2 and TM2E.
- ldo23 is used on TM2/TM2E, but the name/max-microvolt are wrong.
- ldo25 isn't used on TM2/TM2E. (not connected)
Because ldo23 and lod25 are not used on other device in Exynos5433 and TM2 board.
this patch does not affect the operation to system/user.
>
>>
>> Fixes: 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
>> ---
>> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 7 ++++---
>> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 10 ----------
>> 2 files changed, 4 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> index 3b5215c..e8971f4 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> @@ -504,9 +504,9 @@
>> };
>>
>> ldo23_reg: LDO23 {
>> - regulator-name = "CAM_SEN_CORE_1.2V_AP";
>> + regulator-name = "CAM_SEN_CORE_1.05V_AP";
>> regulator-min-microvolt = <1050000>;
>> - regulator-max-microvolt = <1200000>;
>> + regulator-max-microvolt = <1050000>;
>> };
>>
>> ldo24_reg: LDO24 {
>> @@ -516,9 +516,10 @@
>> };
>>
>> ldo25_reg: LDO25 {
>> - regulator-name = "CAM_SEN_A2.8V_AP";
>> + regulator-name = "UNUSED_LDO25";
>> regulator-min-microvolt = <2800000>;
>> regulator-max-microvolt = <2800000>;
>> + regulator-always-off;
>
> Don't add it. See my other patch.
OK. After completing the kernel booting, the unused regulators will be off.
>
> Best regards,
> Krzysztof
>
>> };
>>
>> ldo26_reg: LDO26 {
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> index 1db4e7f..854c583 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> @@ -18,16 +18,6 @@
>> compatible = "samsung,tm2e", "samsung,exynos5433";
>> };
>>
>> -&ldo23_reg {
>> - regulator-name = "CAM_SEN_CORE_1.025V_AP";
>> - regulator-max-microvolt = <1050000>;
>> -};
>> -
>> -&ldo25_reg {
>> - regulator-name = "UNUSED_LDO25";
>> - regulator-always-off;
>> -};
>> -
>> &ldo31_reg {
>> regulator-name = "TSP_VDD_1.8V_AP";
>> regulator-min-microvolt = <1800000>;
>> --
>> 2.7.4
>>
>
>
>
--
Best Regards,
Chanwoo Choi
S/W Center, Samsung Electronics
^ permalink raw reply
* [PATCH 2/2] media: rc: add driver for IR remote receiver on MT7623 SoC
From: Sean Wang @ 2017-01-06 7:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105171240.GA9136@gofer.mess.org>
Hi Sean,
Thanks for your effort for code reviewing. I add comments inline.
On Thu, 2017-01-05 at 17:12 +0000, Sean Young wrote:
> Hi Sean,
>
> Some review comments.
>
> On Fri, Jan 06, 2017 at 12:06:24AM +0800, sean.wang at mediatek.com wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> >
> > This patch adds driver for IR controller on
> > Mediatek MT7623 SoC. Currently testing successfully
> > on NEC and SONY remote controller only but it should
> > work on others (lirc, rc-5 and rc-6).
> >
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > ---
> > drivers/media/rc/Kconfig | 10 ++
> > drivers/media/rc/Makefile | 1 +
> > drivers/media/rc/mtk-cir.c | 319 +++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 330 insertions(+)
> > create mode 100644 linux-4.8.rc1_p0/drivers/media/rc/mtk-cir.c
> >
> > diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
> > index 370e16e..626c500 100644
> > --- a/drivers/media/rc/Kconfig
> > +++ b/drivers/media/rc/Kconfig
> > @@ -389,4 +389,14 @@ config IR_SUNXI
> > To compile this driver as a module, choose M here: the module will
> > be called sunxi-ir.
> >
> > +config IR_MTK
> > + tristate "Mediatek IR remote control"
> > + depends on RC_CORE
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + ---help---
> > + Say Y if you want to use Mediatek internal IR Controller
> > +
> > + To compile this driver as a module, choose M here: the module will
> > + be called mtk-cir.
> > +
> > endif #RC_DEVICES
> > diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
> > index 379a5c0..505908d 100644
> > --- a/drivers/media/rc/Makefile
> > +++ b/drivers/media/rc/Makefile
> > @@ -37,3 +37,4 @@ obj-$(CONFIG_IR_TTUSBIR) += ttusbir.o
> > obj-$(CONFIG_RC_ST) += st_rc.o
> > obj-$(CONFIG_IR_SUNXI) += sunxi-cir.o
> > obj-$(CONFIG_IR_IMG) += img-ir/
> > +obj-$(CONFIG_IR_MTK) += mtk-cir.o
> > diff --git a/drivers/media/rc/mtk-cir.c b/drivers/media/rc/mtk-cir.c
> > new file mode 100644
> > index 0000000..4fa4cab
> > --- /dev/null
> > +++ b/drivers/media/rc/mtk-cir.c
> > @@ -0,0 +1,319 @@
> > +/*
> > + * Driver for Mediatek MT7623 IR Receiver Controller
> > + *
> > + * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/reset.h>
> > +#include <media/rc-core.h>
> > +
> > +#define MTK_IR_DEV "mtk-ir"
>
> KBUILD_MODNAME could be used instead. Currently the module is called
> mtk-cir but the rc device will have driver name mtk-ir.
okay. i will use this instead of this insistent coding.
> > +
> > +/* Register to enable PWM and IR */
> > +#define MTK_CONFIG_HIGH_REG 0x0c
> > +/* Enable IR pulse width detection */
> > +#define MTK_PWM_EN BIT(13)
> > +/* Enable IR hardware function */
> > +#define MTK_IR_EN BIT(0)
> > +
> > +/* Register to setting sample period */
> > +#define MTK_CONFIG_LOW_REG 0x10
> > +/* Field to set sample period */
> > +#define CHK_PERIOD 0xC00
> > +#define MTK_CHK_PERIOD (((CHK_PERIOD) << 8) & (GENMASK(20, 8)))
> > +#define MTK_CHK_PERIOD_MASK (GENMASK(20, 8))
> > +
> > +/* Register to clear state of state machine */
> > +#define MTK_IRCLR_REG 0x20
> > +/* Bit to restart IR receiving */
> > +#define MTK_IRCLR BIT(0)
> > +
> > +/* Register containing pulse width data */
> > +#define MTK_CHKDATA_REG(i) (0x88 + 4 * i)
> > +
> > +/* Register to enable IR interrupt */
> > +#define MTK_IRINT_EN_REG 0xcc
> > +/* Bit to enable interrupt */
> > +#define MTK_IRINT_EN BIT(0)
> > +
> > +/* Register to ack IR interrupt */
> > +#define MTK_IRINT_CLR_REG 0xd0
> > +/* Bit to clear interrupt status */
> > +#define MTK_IRINT_CLR BIT(0)
> > +
> > +/* Number of registers to record the pulse width */
> > +#define MTK_CHKDATA_SZ 17
> > +/* Required frequency */
> > +#define MTK_IR_BASE_CLK 273000000
> > +/* Frequency after IR internal divider */
> > +#define MTK_IR_CLK (MTK_IR_BASE_CLK / 4)
> > +/* Sample period in ns */
> > +#define MTK_IR_SAMPLE (((1000000000ul / MTK_IR_CLK) * CHK_PERIOD))
> > +/* Indicate the end of IR data*/
> > +#define MTK_IR_END(v) (v == 0xff)
> > +
> > +/* struct mtk_ir - This is the main datasructure for holding the state
> > + * of the driver
> > + * @dev: The device pointer
> > + * @ir_lock: Make sure that synchronization between remove and ISR
> > + * @rc: The rc instrance
> > + * @base: The mapped register i/o base
> > + * @irq: The IRQ that we are using
> > + * @clk: The clock that we are using
> > + * @map_name: The name for keymap lookup
> > + */
> > +struct mtk_ir {
> > + struct device *dev;
> > + /*Protect concurrency between driver removal and ISR*/
> > + spinlock_t ir_lock;
> > + struct rc_dev *rc;
> > + void __iomem *base;
> > + int irq;
> > + struct clk *clk;
> > + const char *map_name;
>
> irq and map_name don't need to be stored here, they're only used in
> mtk_ir_probe.
>
I will remove map_name , but keep irq for synchronize_irq call needs.
> > +};
> > +
> > +static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
> > +{
> > + u32 tmp;
> > +
> > + tmp = __raw_readl(ir->base + reg);
> > + tmp = (tmp & ~mask) | val;
> > + __raw_writel(tmp, ir->base + reg);
> > +}
> > +
> > +static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
> > +{
> > + __raw_writel(val, ir->base + reg);
> > +}
> > +
> > +static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
> > +{
> > + return __raw_readl(ir->base + reg);
> > +}
> > +
> > +static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
> > +{
> > + u32 val;
> > +
> > + val = mtk_r32(ir, MTK_IRINT_EN_REG);
> > + mtk_w32(ir, val & ~mask, MTK_IRINT_EN_REG);
> > +}
> > +
> > +static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
> > +{
> > + u32 val;
> > +
> > + val = mtk_r32(ir, MTK_IRINT_EN_REG);
> > + mtk_w32(ir, val | mask, MTK_IRINT_EN_REG);
> > +}
> > +
> > +static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
> > +{
> > + struct mtk_ir *ir = dev_id;
> > + u8 wid = 0;
> > + u32 i, j, val;
> > + DEFINE_IR_RAW_EVENT(rawir);
> > +
> > + spin_lock(&ir->ir_lock);
> > +
> > + mtk_irq_disable(ir, MTK_IRINT_EN);
> > +
> > + /* Reset decoder state machine */
> > + ir_raw_event_reset(ir->rc);
> > +
> > + /* First message must be pulse */
> > + rawir.pulse = false;
> > +
> > + /* Handle pulse and space until end of message */
> > + for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
> > + val = mtk_r32(ir, MTK_CHKDATA_REG(i));
> > + dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
> > +
> > + for (j = 0 ; j < 4 ; j++) {
> > + wid = (val & (0xff << j * 8)) >> j * 8;
> > + rawir.pulse = !rawir.pulse;
> > + rawir.duration = wid * (MTK_IR_SAMPLE + 1);
> > + ir_raw_event_store_with_filter(ir->rc, &rawir);
> > +
> > + if (MTK_IR_END(wid))
> > + goto end_msg;
> > + }
> > + }
>
> If I read this correctly, there is a maximum of 17 * 4 = 68 edges per
> IR message. The rc6 mce key 0 (scancode 0x800f0400) is 69 edges, so that
> won't work.
>
Uh, this is related to hardware limitation. Maximum number hardware
holds indeed is only 68 edges as you said :(
For the case, I will try change the logic into that the whole message
is dropped if no end of message is seen within 68 counts to avoid
wasting CPU for decoding.
> > +end_msg:
> > + /* Restart the next receive */
> > + mtk_w32_mask(ir, 0x1, MTK_IRCLR, MTK_IRCLR_REG);
> > +
> > + ir_raw_event_set_idle(ir->rc, true);
> > + ir_raw_event_handle(ir->rc);
> > +
> > + /* Clear interrupt status */
> > + mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, MTK_IRINT_CLR_REG);
> > +
> > + /* Enable interrupt */
> > + mtk_irq_enable(ir, MTK_IRINT_EN);
> > +
> > + spin_unlock(&ir->ir_lock);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int mtk_ir_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *dn = dev->of_node;
> > + struct resource *res;
> > + struct mtk_ir *ir;
> > + u32 val;
> > + int ret = 0;
> > +
> > + ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
> > + if (!ir)
> > + return -ENOMEM;
> > +
> > + spin_lock_init(&ir->ir_lock);
> > +
> > + ir->dev = dev;
> > +
> > + if (!of_device_is_compatible(dn, "mediatek,mt7623-ir"))
> > + return -ENODEV;
> > +
> > + ir->clk = devm_clk_get(dev, "clk");
> > + if (IS_ERR(ir->clk)) {
> > + dev_err(dev, "failed to get a ir clock.\n");
> > + return PTR_ERR(ir->clk);
> > + }
> > +
> > + if (clk_prepare_enable(ir->clk)) {
> > + dev_err(dev, "try to enable ir_clk failed\n");
> > + ret = -EINVAL;
> > + goto exit_clkdisable_clk;
> > + }
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + ir->base = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(ir->base)) {
> > + dev_err(dev, "failed to map registers\n");
> > + ret = PTR_ERR(ir->base);
> > + goto exit_clkdisable_clk;
> > + }
> > +
> > + ir->rc = rc_allocate_device();
> > + if (!ir->rc) {
> > + dev_err(dev, "failed to allocate device\n");
> > + ret = -ENOMEM;
> > + goto exit_clkdisable_clk;
> > + }
> > +
> > + ir->rc->priv = ir;
> > + ir->rc->input_name = MTK_IR_DEV;
> > + ir->rc->input_phys = "mtk-ir/input0";
> > + ir->rc->input_id.bustype = BUS_HOST;
> > + ir->rc->input_id.vendor = 0x0001;
> > + ir->rc->input_id.product = 0x0001;
> > + ir->rc->input_id.version = 0x0001;
> > + ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
> > + ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
> > + ir->rc->dev.parent = dev;
> > + ir->rc->driver_type = RC_DRIVER_IR_RAW;
> > + ir->rc->driver_name = MTK_IR_DEV;
> > + ir->rc->allowed_protocols = RC_BIT_ALL;
> > + ir->rc->rx_resolution = MTK_IR_SAMPLE;
> > +
> > + ret = rc_register_device(ir->rc);
> > + if (ret) {
> > + dev_err(dev, "failed to register rc device\n");
> > + goto exit_free_dev;
> > + }
> > +
> > + platform_set_drvdata(pdev, ir);
> > +
> > + ir->irq = platform_get_irq(pdev, 0);
> > + if (ir->irq < 0) {
> > + dev_err(dev, "no irq resource\n");
> > + ret = ir->irq;
>
> From here on onwards the errors paths should call rc_unregister_device(),
> and no longer call rc_free_device(). Note that current master has
> devm_rc_allocate_device() and devm_rc_register_device() which would
> simplify this code.
okay, i will use devm_rc_register_device to have simplified code.
> > + goto exit_free_dev;
> > + }
> > +
> > + ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
> > + if (ret) {
> > + dev_err(dev, "failed request irq\n");
> > + goto exit_free_dev;
> > + }
> > +
> > + mtk_irq_disable(ir, MTK_IRINT_EN);
> > +
> > + val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
> > + val |= MTK_PWM_EN | MTK_IR_EN;
> > + mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
> > +
> > + /* Setting sample period */
> > + mtk_w32_mask(ir, MTK_CHK_PERIOD, MTK_CHK_PERIOD_MASK,
> > + MTK_CONFIG_LOW_REG);
> > +
> > + mtk_irq_enable(ir, MTK_IRINT_EN);
> > +
> > + dev_info(dev, "initialized MT7623 IR driver\n");
> > + return 0;
> > +
> > +exit_free_dev:
> > + rc_free_device(ir->rc);
> > +exit_clkdisable_clk:
> > + clk_disable_unprepare(ir->clk);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ir_remove(struct platform_device *pdev)
> > +{
> > + unsigned long flags;
> > +
> > + struct mtk_ir *ir = platform_get_drvdata(pdev);
> > +
> > + spin_lock_irqsave(&ir->ir_lock, flags);
> > +
> > + mtk_irq_disable(ir, MTK_IRINT_EN);
> > +
> > + clk_disable_unprepare(ir->clk);
> > +
> > + spin_unlock_irqrestore(&ir->ir_lock, flags);
>
> I'm not convinced the ir_lock is helping to prevent any race condition. An
> irq might still already have occurred which will now try to use ir->rc
> which is freed. You can remove the spinlock completely and call
> sychronize_irq() after disabling the mtk interrupt. That way you're sure
> the remove is safe to complete.
Okay, it's great suggestion. I will use sychronize_irq instead of the my
bad one :)
> > +
> > + rc_unregister_device(ir->rc);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ir_match[] = {
> > + { .compatible = "mediatek,mt7623-ir" },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_ir_match);
> > +
> > +static struct platform_driver mtk_ir_driver = {
> > + .probe = mtk_ir_probe,
> > + .remove = mtk_ir_remove,
> > + .driver = {
> > + .name = MTK_IR_DEV,
> > + .of_match_table = mtk_ir_match,
> > + },
> > +};
> > +
> > +module_platform_driver(mtk_ir_driver);
> > +
> > +MODULE_DESCRIPTION("Mediatek MT7623 IR Receiver Controller Driver");
> > +MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
> > +MODULE_LICENSE("GPL");
> > --
> > 1.9.1
> >
^ permalink raw reply
* [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges
From: Dinh Nguyen @ 2017-01-06 7:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANk1AXRsrW1YHRPn4Rcv7Pu8jBUEcOmREOFYvvMV8D9eKLU-6g@mail.gmail.com>
On 01/05/2017 10:34 AM, Alan Tull wrote:
> On Thu, Jan 5, 2017 at 10:28 AM, Alan Tull <atull@kernel.org> wrote:
>> On Wed, Jan 4, 2017 at 6:21 PM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>>> From: Alan Tull <atull@opensource.altera.com>
>>>
>>> Add h2f and lwh2f bridges.
>>> Add base FPGA Region to support DT overlays for FPGA programming.
>>> Add l3regs.
>>>
>>> Signed-off-by: Alan Tull <atull@opensource.altera.com>
>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>> ---
>>> arch/arm/boot/dts/socfpga.dtsi | 31 +++++++++++++++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index de29172..dccc281 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>> @@ -93,6 +93,16 @@
>>> };
>>> };
>>>
>>> + base_fpga_region {
>>> + compatible = "fpga-region";
>>> + fpga-mgr = <&fpgamgr0>;
>>> + fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>;
>>
>> Hi Dinh,
>>
>> We want to get rid of the 'fpga-bridges' line.
>>
>>> +
>>> + #address-cells = <0x1>;
>>> + #size-cells = <0x1>;
>>> + ranges = <0 0xff200000 0x100000>;
>>
>> Should get rid of the ranges line here too. The 'fpga-bridges' and
>> 'ranges' line can be added in the overlay.
>>
>> Alan
>>
>>> + };
>>> +
>>> can0: can at ffc00000 {
>>> compatible = "bosch,d_can";
>>> reg = <0xffc00000 0x1000>;
>>> @@ -513,6 +523,22 @@
>>> };
>>> };
>>>
>>> + fpga_bridge0: fpga_bridge at ff400000 {
>>> + compatible = "altr,socfpga-lwhps2fpga-bridge";
>>> + reg = <0xff400000 0x100000>;
>>> + resets = <&rst LWHPS2FPGA_RESET>;
>>> + reset-names = "lwhps2fpga";
>
> The driver doesn't need 'reset-names' here or below for fpga_bridge1.
>
Ok, thanks for the review.
Dinh
^ permalink raw reply
* [PATCH 2/2] media: rc: add driver for IR remote receiver on MT7623 SoC
From: Sean Wang @ 2017-01-06 7:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106034346.7njhyhtsc4yado5c@gangnam.samsung>
Hi Andi,
Thank for your reminder. I will refine the code based on your work.
to have elegant code and easy error handling.
Sean
On Fri, 2017-01-06 at 12:43 +0900, Andi Shyti wrote:
> Hi Sean,
>
> > + ir->rc = rc_allocate_device();
>
> Yes, you should use devm_rc_allocate_device(...)
>
> Besides, standing to this patch which is not in yet:
>
> https://lkml.org/lkml/2016/12/18/39
>
> rc_allocate_device should provide the driver type during
> allocation, so it should be:
>
> ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
>
> and this line can be removed:
>
> > + ir->rc->driver_type = RC_DRIVER_IR_RAW;
>
> I don't know when Mauro will take the patch above.
>
> Andi
^ permalink raw reply
* [PATCHv2] ARM: dts: socfpga: add base fpga region and fpga bridges
From: Dinh Nguyen @ 2017-01-06 7:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Alan Tull <atull@opensource.altera.com>
Add h2f and lwh2f bridges.
Add base FPGA Region to support DT overlays for FPGA programming.
Add l3regs.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: removed fpga-bridges, ranges, and reset-names
---
arch/arm/boot/dts/socfpga.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index de29172..c984f53 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -93,6 +93,14 @@
};
};
+ base_fpga_region {
+ compatible = "fpga-region";
+ fpga-mgr = <&fpgamgr0>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
can0: can at ffc00000 {
compatible = "bosch,d_can";
reg = <0xffc00000 0x1000>;
@@ -513,6 +521,20 @@
};
};
+ fpga_bridge0: fpga_bridge at ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
+ fpga_bridge1: fpga_bridge at ff500000 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ reg = <0xff500000 0x10000>;
+ resets = <&rst HPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
fpgamgr0: fpgamgr at ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000
@@ -694,6 +716,11 @@
arm,prefetch-offset = <7>;
};
+ l3regs at 0xff800000 {
+ compatible = "altr,l3regs", "syscon";
+ reg = <0xff800000 0x1000>;
+ };
+
mmc: dwmmc0 at ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH v7 0/8] Add PWM and IIO timer drivers for STM32
From: Benjamin Gaignard @ 2017-01-06 7:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170105144953.GT24225@dell>
2017-01-05 15:49 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Thu, 05 Jan 2017, Benjamin Gaignard wrote:
>
>> version 7:
>> - rebase on v4.10-rc2
>> - remove iio_device code from driver and keep only the trigger part
>>
>> version 6:
>> - rename stm32-gptimer in stm32-timers.
>> - change "st,stm32-gptimer" compatible to "st,stm32-timers".
>> - modify "st,breakinput" parameter in pwm part.
>> - split DT patch in 2
>>
>> version 5:
>> - fix comments done on version 4
>> - rebased on kernel 4.9-rc8
>> - change nodes names and re-order then by addresses
>>
>> version 4:
>> - fix comments done on version 3
>> - don't use interrupts anymore in IIO timer
>> - detect hardware capabilities at probe time to simplify binding
>>
>> version 3:
>> - no change on mfd and pwm divers patches
>> - add cross reference between bindings
>> - change compatible to "st,stm32-timer-trigger"
>> - fix attributes access rights
>> - use string instead of int for master_mode and slave_mode
>> - document device attributes in sysfs-bus-iio-timer-stm32
>> - update DT with the new compatible
>>
>> version 2:
>> - keep only one compatible per driver
>> - use DT parameters to describe hardware block configuration:
>> - pwm channels, complementary output, counter size, break input
>> - triggers accepted and create by IIO timers
>> - change DT to limite use of reference to the node
>> - interrupt is now in IIO timer driver
>> - rename stm32-mfd-timer to stm32-timers (for general purpose timer)
>>
>> The following patches enable PWM and IIO Timer features for STM32 platforms.
>>
>> Those two features are mixed into the registers of the same hardware block
>> (named general purpose timer) which lead to introduce a multifunctions driver
>> on the top of them to be able to share the registers.
>>
>> In STM32f4 14 instances of timer hardware block exist, even if they all have
>> the same register mapping they could have a different number of pwm channels
>> and/or different triggers capabilities. We use various parameters in DT to
>> describe the differences between hardware blocks
>>
>> The MFD (stm32-timers.c) takes care of clock and register mapping
>> by using regmap. stm32_timers structure is provided to its sub-node to
>> share those information.
>>
>> PWM driver is implemented into pwm-stm32.c. Depending of the instance we may
>> have up to 4 channels, sometime with complementary outputs or 32 bits counter
>> instead of 16 bits. Some hardware blocks may also have a break input function
>> which allows to stop pwm depending of a level, defined in devicetree, on an
>> external pin.
>>
>> IIO timer driver (stm32-timer-trigger.c and stm32-timer-trigger.h) define a list
>> of hardware triggers usable by hardware blocks like ADC, DAC or other timers.
>>
>> The matrix of possible connections between blocks is quite complex so we use
>> trigger names and is_stm32_iio_timer_trigger() function to be sure that
>> triggers are valid and configure the IPs.
>>
>> At run time IIO timer hardware blocks can configure (through "master_mode"
>> IIO device attribute) which internal signal (counter enable, reset,
>> comparison block, etc...) is used to generate the trigger.
>>
>> Benjamin Gaignard (8):
>> MFD: add bindings for STM32 Timers driver
>> MFD: add STM32 Timers driver
>> PWM: add pwm-stm32 DT bindings
>> PWM: add PWM driver for STM32 plaftorm
>> IIO: add bindings for STM32 timer trigger driver
>> IIO: add STM32 timer trigger driver
>> ARM: dts: stm32: add Timers driver for stm32f429 MCU
>> ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
>
> Any reason why you've dropped all your Acks?
>
> I don't really want to review it again if little is different.
>
> How much MFD related code has changed since the last review?
All my apologies I forgot to add your Acks for MFD parts.
Sorry for that
>
>> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++
>> .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++
>> .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++
>> .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++
>> arch/arm/boot/dts/stm32f429.dtsi | 275 +++++++++++++
>> arch/arm/boot/dts/stm32f469-disco.dts | 28 ++
>> drivers/iio/Kconfig | 1 -
>> drivers/iio/trigger/Kconfig | 10 +
>> drivers/iio/trigger/Makefile | 1 +
>> drivers/iio/trigger/stm32-timer-trigger.c | 340 ++++++++++++++++
>> drivers/mfd/Kconfig | 11 +
>> drivers/mfd/Makefile | 2 +
>> drivers/mfd/stm32-timers.c | 80 ++++
>> drivers/pwm/Kconfig | 9 +
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-stm32.c | 434 +++++++++++++++++++++
>> include/linux/iio/timer/stm32-timer-trigger.h | 62 +++
>> include/linux/mfd/stm32-timers.h | 71 ++++
>> 18 files changed, 1455 insertions(+), 1 deletion(-)
>> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt
>> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>> create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c
>> create mode 100644 drivers/mfd/stm32-timers.c
>> create mode 100644 drivers/pwm/pwm-stm32.c
>> create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
>> create mode 100644 include/linux/mfd/stm32-timers.h
>>
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v3 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-06 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106070911.sj6qjd5akyxnazsl@kozik-lap>
Hi,
On Fri, Jan 06, 2017 at 09:09:11AM +0200, Krzysztof Kozlowski wrote:
> On Fri, Jan 06, 2017 at 12:59:06PM +0900, Jaechul Lee wrote:
> > From: Andi Shyti <andi.shyti@samsung.com>
> >
> > Currently tm2e dts includes tm2 but there are some differences
> > between the two boards and tm2 has some properties that tm2e
> > doesn't have.
> >
> > That's why it's important to keep the two dts files independent
> > and put all the commonalities in a tm2-common.dtsi file.
> >
> > At the current status the only two differences between the two
> > dts files (besides the board name) are ldo31 and ldo38.
> >
> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> > ---
> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1118 +++++++++++++++++++
> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1153 +-------------------
>
> Like talking to a wall. Without any feedback. If my instructions were
> wrong (and it is not possible to detect rename) then please say it (you
> can add personal comments after separator ---).
no Krzysztof, I'm sorry, but this patch has been formatted with
the diff algorithm *you* asked, -B50% both version 2 (where you
didn't comment) and version 3. If you still don't like it, please
don't blame me, blame the algorithm.
Now we can stay here at trying random diff algorithms (as they
give more or less the same result) or you tell me which exact
algorithm you want me to use. Besides, for me it's clear,
tm2-common is all new, while in tm2 you have on one side the '-'
(if it applies nothing has changed) on the bottom the '+'.
Andi
^ permalink raw reply
* [PATCH] ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS
From: Neil Armstrong @ 2017-01-06 8:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9f508097-f605-ebd8-20af-c3e798c6fdcc@poczta.onet.pl>
On 01/05/2017 08:04 PM, Micha? Zegan wrote:
> Hello.
>
> The patch causes cpufreq module (scpi-cpufreq) not to detect cpufreq, so
> it actually works, but...
> Loading the module causes few errors because of not found frequencies or
> something, then it is all okay. However after loading scpi-cpufreq you
> cannot actually power the cpu off and on. You will power it off
> successfully, but when trying to power it on, the cpufreq driver will
> error out, and then after it happens, the cpu that was trying to go
> online will be offline again, and that is a little... unfortunate. The
> question is, and I cannot really test that: will the module actually
> autoload after this change?
Hi Michal,
You are right, it breaks cpufreq and the cpu hotplug feature, I will send a v2 completely disabling cpufreq instead.
For the module autoloading, the arm_scpi.ko must be loaded before the other scpi modules.
Please ask Sudeep Holla <sudeep.holla@arm.com> if module autoloading for scpi is meant to work.
Neil
>
> W dniu 05.01.2017 o 16:02, Neil Armstrong pisze:
>> The current hardware is not able to run with all cores enabled at a
>> cluster frequency superior at 1536MHz.
>> But the currently shipped u-boot for the platform still reports an OPP
>> table with possible DVFS frequency up to 2GHz, and will not change since
>> the off-tree linux tree supports limiting the OPPs with a kernel parameter.
>> A recent u-boot change reports the boot-time DVFS around 100MHz and
>> the default performance cpufreq governor sets the maximum frequency.
>> Previous version of u-boot reported to be already at the max OPP and
>> left the OPP as is.
>> Nevertheless, other governors like ondemand could setup the max frequency
>> and make the system crash.
>>
>> This patch disables the DVFS clock and disables cpufreq.
>>
>> Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> index 238fbea..5e63e3b 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> @@ -137,6 +137,10 @@
>> };
>> };
>>
>> +&scpi_dvfs {
>> + status = "disabled";
>> +};
>> +
>> &uart_AO {
>> status = "okay";
>> pinctrl-0 = <&uart_ao_a_pins>;
>>
>
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^ permalink raw reply
* [PATCH v2] ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS
From: Neil Armstrong @ 2017-01-06 8:04 UTC (permalink / raw)
To: linux-arm-kernel
The current hardware is not able to run with all cores enabled at a
cluster frequency superior at 1536MHz.
But the currently shipped u-boot for the platform still reports an OPP
table with possible DVFS frequency up to 2GHz, and will not change since
the off-tree linux tree supports limiting the OPPs with a kernel parameter.
A recent u-boot change reports the boot-time DVFS around 100MHz and
the default performance cpufreq governor sets the maximum frequency.
Previous version of u-boot reported to be already at the max OPP and
left the OPP as is.
Nevertheless, other governors like ondemand could setup the max frequency
and make the system crash.
This patch disables the DVFS clock and disables cpufreq.
Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 4 ++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
Changes since v1 at [1] :
- Disable scpi_clocks instead of scpi_dvfs_clock
[1] http://lkml.kernel.org/r/1483628549-29486-1-git-send-email-narmstrong at baylibre.com
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 238fbea..5d28e1c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -137,6 +137,10 @@
};
};
+&scpi_clocks {
+ status = "disabled";
+};
+
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 51edd5b5..77caedd8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -55,7 +55,7 @@
mboxes = <&mailbox 1 &mailbox 2>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
- clocks {
+ scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks at 0 {
--
1.9.1
^ permalink raw reply related
* [PATCH v2,9/9] irqchip/ls-scfg-msi: add MSI affinity support
From: M.H. Lian @ 2017-01-06 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7888f3a1-ae4a-f2b6-f41b-fc414f7ca968@arm.com>
Hi Marc,
Thanks for your review.
Please see my comments inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Marc Zyngier [mailto:marc.zyngier at arm.com]
> Sent: Thursday, January 05, 2017 11:33 PM
> To: M.H. Lian <minghuan.lian@nxp.com>; linux-arm-
> kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> devicetree at vger.kernel.org
> Cc: Rob Herring <robh@kernel.org>; Jason Cooper
> <jason@lakedaemon.net>; Roy Zang <roy.zang@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; Stuart Yoder <stuart.yoder@nxp.com>; Leo Li
> <leoyang.li@nxp.com>; Scott Wood <scott.wood@nxp.com>
> Subject: Re: [PATCH v2,9/9] irqchip/ls-scfg-msi: add MSI affinity support
>
> On 05/01/17 08:10, Minghuan Lian wrote:
> > For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4
> > CPUs. A GIC SPI interrupt of MSIR can be associated with a CPU.
> > When changing MSI interrupt affinity, this MSI will be moved to the
> > corresponding MSIR and MSI message data will be changed according to
> > MSIR. when requesting a MSI, the bits of all 4 MSIR will be reserved.
> > The parameter 'msi_affinity_flag' is provide to change this mode.
> > "lsmsi=no-affinity" will disable affinity, all MSI can only be
> > associated with CPU 0.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > v2-v1:
> > - None
> >
> > drivers/irqchip/irq-ls-scfg-msi.c | 75
> > ++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 70 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-ls-scfg-msi.c
> > b/drivers/irqchip/irq-ls-scfg-msi.c
> > index dc19569..753fe39 100644
> > --- a/drivers/irqchip/irq-ls-scfg-msi.c
> > +++ b/drivers/irqchip/irq-ls-scfg-msi.c
> > @@ -40,6 +40,7 @@ struct ls_scfg_msir {
> > unsigned int gic_irq;
> > unsigned int bit_start;
> > unsigned int bit_end;
> > + unsigned int srs; /* Shared interrupt register select */
> > void __iomem *reg;
> > };
> >
> > @@ -70,6 +71,19 @@ struct ls_scfg_msi {
> > .chip = &ls_scfg_msi_irq_chip,
> > };
> >
> > +static int msi_affinity_flag = 1;
> > +
> > +static int __init early_parse_ls_scfg_msi(char *p) {
> > + if (p && strncmp(p, "no-affinity", 11) == 0)
> > + msi_affinity_flag = 0;
> > + else
> > + msi_affinity_flag = 1;
> > +
> > + return 0;
> > +}
> > +early_param("lsmsi", early_parse_ls_scfg_msi);
>
> What is the point of this option? If feels like an unnecessary complexity.
[Minghuan Lian] For LS1043a rev1.1, there are only 8 MSI interrupts for each MSI controller when enable affinity.
(32 MSI interrupts are evenly distributed to 4 cores). 3 MSI controllers can only provide 32 MSI interrupts.
When disable affinity, the MSI interrupts number of 3 controllers can up to 32*3= 96.
32 MSI interrupts may be not enough.
For example: an Ethernet card with 4 ports, each port needs 4 RX, 4TX and 1 error interrupts, totally need 4*(4+4+1)
36 MSI interrupts.
With the parameter "lsmsi=no-affinity" this Ethernet card can work well, although the performance is poor.
>
> > +
> > static void ls_scfg_msi_compose_msg(struct irq_data *data, struct
> > msi_msg *msg) {
> > struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
> @@
> > -77,12 +91,43 @@ static void ls_scfg_msi_compose_msg(struct irq_data
> *data, struct msi_msg *msg)
> > msg->address_hi = upper_32_bits(msi_data->msiir_addr);
> > msg->address_lo = lower_32_bits(msi_data->msiir_addr);
> > msg->data = data->hwirq;
> > +
> > + if (msi_affinity_flag) {
> > + u32 msir_index;
> > +
> > + msir_index = cpumask_first(data->common->affinity);
> > + if (msir_index >= msi_data->msir_num)
> > + msir_index = 0;
>
> How can this happen?
[Minghuan Lian] This will never happen. I will remove this "if" sentence.
>
> > +
> > + msg->data |= msir_index;
>
> How do you guarantee that the low bits were clear? Please document the
> way you encode your MSI payload.
[Minghuan Lian] the available message data is a bytes.
7 6 5 4 3 2 1 0
| - | ibs | srs |
SRS bit 0-1 is used to select MSIR register/CPU. A MSIR is associated with a CPU.
IBS bit2-6 of ls1046, bit2-4 for ls1043 is used to select bit of the MSIR.
When enable affinity, only bits of MSIR0(srs = 0 cpu0) is be freed for requesting MSI.
all bits of the MSIR1-3(cpu1-3) are reserved to be sure this MSI can be successfully associated with cpu 1-3.
So, When requesting a MSI interrupt, srs always is 0.
The hwirq always equals bits number of the MSIR0(SRS = 0).
First, MSI message data payload equals hwirq, and then plus the real SRS according to smp_affinity.
This MSI interrupt will be routed to the corresponding the MSIR/CPU.
>
> > + }
> > }
> >
> > static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
> > const struct cpumask *mask, bool force) {
> > - return -EINVAL;
> > + struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
> > + u32 cpu;
> > +
> > + if (!msi_affinity_flag)
> > + return -EINVAL;
> > +
> > + if (!force)
> > + cpu = cpumask_any_and(mask, cpu_online_mask);
> > + else
> > + cpu = cpumask_first(mask);
> > +
> > + if (cpu >= msi_data->msir_num)
> > + return -EINVAL;
> > +
> > + if (msi_data->msir[cpu].gic_irq <= 0) {
> > + pr_warn("cannot bind the irq to cpu%d\n", cpu);
>
> Please don't. Returning an error is enough. If you really want to have
> something, turn it into a proper debug message.
[Minghuan Lian] ok, I will change it.
>
> > + return -EINVAL;
> > + }
> > +
> > + cpumask_copy(irq_data->common->affinity, mask);
> > +
> > + return IRQ_SET_MASK_OK;
> > }
> >
> > static struct irq_chip ls_scfg_msi_parent_chip = { @@ -158,7 +203,7
> > @@ static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
> >
> > for_each_set_bit_from(pos, &val, size) {
> > hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
> > - msir->index;
> > + msir->srs;
> > virq = irq_find_mapping(msi_data->parent, hwirq);
> > if (virq)
> > generic_handle_irq(virq);
> > @@ -221,10 +266,19 @@ static int ls_scfg_msi_setup_hwirq(struct
> ls_scfg_msi *msi_data, int index)
> > ls_scfg_msi_irq_handler,
> > msir);
> >
> > + if (msi_affinity_flag) {
> > + /* Associate MSIR interrupt to the cpu */
> > + irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
> > + msir->srs = 0; /* This value is determined by the CPU */
> > + } else
> > + msir->srs = index;
> > +
> > /* Release the hwirqs corresponding to this MSIR */
> > - for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
> > - hwirq = i << msi_data->cfg->ibs_shift | msir->index;
> > - bitmap_clear(msi_data->used, hwirq, 1);
> > + if (!msi_affinity_flag || msir->index == 0) {
> > + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
> > + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
> > + bitmap_clear(msi_data->used, hwirq, 1);
> > + }
> > }
> >
> > return 0;
> > @@ -316,6 +370,17 @@ static int ls_scfg_msi_probe(struct
> platform_device *pdev)
> > bitmap_set(msi_data->used, 0, msi_data->irqs_num);
> >
> > msi_data->msir_num = of_irq_count(pdev->dev.of_node);
> > +
> > + if (msi_affinity_flag) {
> > + u32 cpu_num;
> > +
> > + cpu_num = num_possible_cpus();
> > + if (msi_data->msir_num >= cpu_num)
> > + msi_data->msir_num = cpu_num;
> > + else
> > + msi_affinity_flag = 0;
> > + }
> > +
> > msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
> > sizeof(*msi_data->msir),
> > GFP_KERNEL);
> >
>
> This is a very confusing patch. Please get rid of this useless option and
> document how you encode the routing in the hwirq.
[Minghuan Lian] Both LS1021a and LS1043av1.0 have only a MSIR, a gic interrupt.
MSI controllers cannot support affinity.
Then LS1046a/LS1043av1.1 extends MSIR number to 4 same to cpu number. So each MSIR with a GIC interrupt can be associated with a cpu.
To keep simple, the first patch for ls1046 and ls1043av1.1 keep the same way with ls1021 and ls1043av1.0 that does not support affinity and
all interrupts of MSIR0-3 are different and can be used for requesting MSI interrupts.
This patch is to enable affinity, that means, for ls1046a and ls1043av1.1, the same bit of MSIR0-3 will be looked as one interrupt using the same hwirq. And MSIRN only is used when the MSI interrupt is associated with the corresponding cpu.
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH 17/22] power: supply: add battery driver for AXP20X and AXP22X PMICs
From: Quentin Schulz @ 2017-01-06 8:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v66XnWOGcaLeRo+cb6NGqfm_cyJVoK+GURUo5iV4pdZzew@mail.gmail.com>
Hi,
On 06/01/2017 04:39, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, Jan 3, 2017 at 12:37 AM, Quentin Schulz
> <quentin.schulz@free-electrons.com> wrote:
[...]
>> + case POWER_SUPPLY_PROP_CURRENT_MAX:
>> + ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1, ®);
>> + if (ret)
>> + return ret;
>> +
>> + reg &= AXP20X_CHRG_CTRL1_TGT_CURR;
>> + val->intval = reg * 100000 + 300000;
>> + break;
>
>
> This controls the charge current. I believe the correct property to use
> is CONSTANT_CHARGE_CURRENT. And you should add CONSTANT_CHARGE_CURRENT_MAX
> which returns the highest possible setting.
>
ACK.
> Also letting the user control this might not always be a good idea.
> IIUC, LiPo batteries can only be charged at 1C, where C is the
> rated capacity (X mAh).
>
OK. Should I get the charge current from a DT property then?
Like "x-powers,charge-current = <300000>;"
It's close to what has been done in bq24257_charger for example.
[...]
>> +static enum power_supply_property axp20x_battery_props[] = {
>> + POWER_SUPPLY_PROP_PRESENT,
>> + POWER_SUPPLY_PROP_ONLINE,
>> + POWER_SUPPLY_PROP_STATUS,
>> + POWER_SUPPLY_PROP_VOLTAGE_NOW,
>> + POWER_SUPPLY_PROP_CURRENT_NOW,
>> + POWER_SUPPLY_PROP_CURRENT_MAX,
>> + POWER_SUPPLY_PROP_HEALTH,
>> + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
>> + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
>> + POWER_SUPPLY_PROP_CAPACITY,
>
> You can also add POWER_SUPPLY_PROP_TECHNOLOGY, which would return
> POWER_SUPPLY_TECHNOLOGY_LIPO.
>
Hum.. There are also POWER_SUPPLY_TECHNOLOGY_LION,
POWER_SUPPLY_TECHNOLOGY_LiFe and POWER_SUPPLY_TECHNOLOGY_LiMn which are
all Lithium-based batteries. From the datasheet, it can take a "single
cell Li-battery (Li-Ion/Polymer)". So I guess it's either
POWER_SUPPLY_TECHNOLOGY_LION or POWER_SUPPLY_TECHNOLOGY_LIPO.
> It is also possible to do POWER_SUPPLY_PROP_CHARGE_TYPE. According
> to the manual, if the battery is charging, it is in constant current
> mode (POWER_SUPPLY_CHARGE_TYPE_FAST) when V_battery < V_target.
> When V_battery == V_target, it is in constant voltage mode, though
> I don't think this is the same as POWER_SUPPLY_CHARGE_TYPE_TRICKLE.
> When it is not charging, you can return POWER_SUPPLY_CHARGE_TYPE_NONE.
>
ACK, I'll look into that.
Thanks,
Quentin
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v5 13/17] irqdomain: irq_domain_check_msi_remap
From: Auger Eric @ 2017-01-06 8:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM5PR0401MB2545B4A50ABE17B27C50B3099A630@AM5PR0401MB2545.eurprd04.prod.outlook.com>
Hi Bharat,
On 06/01/2017 05:27, Bharat Bhushan wrote:
> Hi Mark,
>
>> -----Original Message-----
>> From: Auger Eric [mailto:eric.auger at redhat.com]
>> Sent: Thursday, January 05, 2017 5:39 PM
>> To: Marc Zyngier <marc.zyngier@arm.com>; eric.auger.pro at gmail.com;
>> christoffer.dall at linaro.org; robin.murphy at arm.com;
>> alex.williamson at redhat.com; will.deacon at arm.com; joro at 8bytes.org;
>> tglx at linutronix.de; jason at lakedaemon.net; linux-arm-
>> kernel at lists.infradead.org
>> Cc: drjones at redhat.com; kvm at vger.kernel.org; punit.agrawal at arm.com;
>> linux-kernel at vger.kernel.org; geethasowjanya.akula at gmail.com; Diana
>> Madalina Craciun <diana.craciun@nxp.com>; iommu at lists.linux-
>> foundation.org; pranav.sawargaonkar at gmail.com; Bharat Bhushan
>> <bharat.bhushan@nxp.com>; shankerd at codeaurora.org;
>> gpkulkarni at gmail.com
>> Subject: Re: [PATCH v5 13/17] irqdomain: irq_domain_check_msi_remap
>>
>> Hi Marc,
>>
>> On 05/01/2017 12:57, Marc Zyngier wrote:
>>> On 05/01/17 11:29, Auger Eric wrote:
>>>> Hi Marc,
>>>>
>>>> On 05/01/2017 12:25, Marc Zyngier wrote:
>>>>> On 05/01/17 10:45, Auger Eric wrote:
>>>>>> Hi Marc,
>>>>>>
>>>>>> On 04/01/2017 16:27, Marc Zyngier wrote:
>>>>>>> On 04/01/17 14:11, Auger Eric wrote:
>>>>>>>> Hi Marc,
>>>>>>>>
>>>>>>>> On 04/01/2017 14:46, Marc Zyngier wrote:
>>>>>>>>> Hi Eric,
>>>>>>>>>
>>>>>>>>> On 04/01/17 13:32, Eric Auger wrote:
>>>>>>>>>> This new function checks whether all platform and PCI MSI
>>>>>>>>>> domains implement IRQ remapping. This is useful to understand
>>>>>>>>>> whether VFIO passthrough is safe with respect to interrupts.
>>>>>>>>>>
>>>>>>>>>> On ARM typically an MSI controller can sit downstream to the
>>>>>>>>>> IOMMU without preventing VFIO passthrough.
>>>>>>>>>> As such any assigned device can write into the MSI doorbell.
>>>>>>>>>> In case the MSI controller implements IRQ remapping, assigned
>>>>>>>>>> devices will not be able to trigger interrupts towards the
>>>>>>>>>> host. On the contrary, the assignment must be emphasized as
>>>>>>>>>> unsafe with respect to interrupts.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>>>>>>>>>
>>>>>>>>>> ---
>>>>>>>>>>
>>>>>>>>>> v4 -> v5:
>>>>>>>>>> - Handle DOMAIN_BUS_FSL_MC_MSI domains
>>>>>>>>>> - Check parents
>>>>>>>>>> ---
>>>>>>>>>> include/linux/irqdomain.h | 1 +
>>>>>>>>>> kernel/irq/irqdomain.c | 41
>> +++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>> 2 files changed, 42 insertions(+)
>>>>>>>>>>
>>>>>>>>>> diff --git a/include/linux/irqdomain.h
>>>>>>>>>> b/include/linux/irqdomain.h index ab017b2..281a40f 100644
>>>>>>>>>> --- a/include/linux/irqdomain.h
>>>>>>>>>> +++ b/include/linux/irqdomain.h
>>>>>>>>>> @@ -219,6 +219,7 @@ struct irq_domain
>> *irq_domain_add_legacy(struct device_node *of_node,
>>>>>>>>>> void *host_data);
>>>>>>>>>> extern struct irq_domain *irq_find_matching_fwspec(struct
>> irq_fwspec *fwspec,
>>>>>>>>>> enum
>> irq_domain_bus_token bus_token);
>>>>>>>>>> +extern bool irq_domain_check_msi_remap(void);
>>>>>>>>>> extern void irq_set_default_host(struct irq_domain *host);
>>>>>>>>>> extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs,
>>>>>>>>>> irq_hw_number_t hwirq, int node,
>> diff --git
>>>>>>>>>> a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index
>>>>>>>>>> 8c0a0ae..700caea 100644
>>>>>>>>>> --- a/kernel/irq/irqdomain.c
>>>>>>>>>> +++ b/kernel/irq/irqdomain.c
>>>>>>>>>> @@ -278,6 +278,47 @@ struct irq_domain
>>>>>>>>>> *irq_find_matching_fwspec(struct irq_fwspec *fwspec,
>>>>>>>>>> EXPORT_SYMBOL_GPL(irq_find_matching_fwspec);
>>>>>>>>>>
>>>>>>>>>> /**
>>>>>>>>>> + * irq_domain_is_msi_remap - Check if @domain or any parent
>>>>>>>>>> + * has MSI remapping support
>>>>>>>>>> + * @domain: domain pointer
>>>>>>>>>> + */
>>>>>>>>>> +static bool irq_domain_is_msi_remap(struct irq_domain
>> *domain)
>>>>>>>>>> +{
>>>>>>>>>> + struct irq_domain *h = domain;
>>>>>>>>>> +
>>>>>>>>>> + for (; h; h = h->parent) {
>>>>>>>>>> + if (h->flags & IRQ_DOMAIN_FLAG_MSI_REMAP)
>>>>>>>>>> + return true;
>>>>>>>>>> + }
>>>>>>>>>> + return false;
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +/**
>>>>>>>>>> + * irq_domain_check_msi_remap() - Checks whether all MSI
>>>>>>>>>> + * irq domains implement IRQ remapping */ bool
>>>>>>>>>> +irq_domain_check_msi_remap(void) {
>>>>>>>>>> + struct irq_domain *h;
>>>>>>>>>> + bool ret = true;
>>>>>>>>>> +
>>>>>>>>>> + mutex_lock(&irq_domain_mutex);
>>>>>>>>>> + list_for_each_entry(h, &irq_domain_list, link) {
>>>>>>>>>> + if (((h->bus_token & DOMAIN_BUS_PCI_MSI) ||
>>>>>>>>>> + (h->bus_token & DOMAIN_BUS_PLATFORM_MSI)
>> ||
>>>>>>>>>> + (h->bus_token & DOMAIN_BUS_FSL_MC_MSI))
>> &&
>>>>>>>>>> + !irq_domain_is_msi_remap(h)) {
>>>>>>>>>
>>>>>>>>> (h->bus_token & DOMAIN_BUS_PCI_MSI) and co looks quite
>> wrong.
>>>>>>>>> bus_token is not a bitmap, and DOMAIN_BUS_* not a single bit
>>>>>>>>> value (see enum irq_domain_bus_token). Surely this should read
>>>>>>>>> (h->bus_token == DOMAIN_BUS_PCI_MSI).
>>>>>>>> Oh I did not notice that. Thanks.
>>>>>>>>
>>>>>>>> Any other comments on the irqdomain side? Do you think the
>>>>>>>> current approach consisting in looking at those bus tokens and
>>>>>>>> their parents looks good?
>>>>>>>
>>>>>>> To be completely honest, I don't like it much, as having to
>>>>>>> enumerate all the bus types can come up with could become quite a
>>>>>>> burden in the long run. I'd rather be able to identify MSI capable
>>>>>>> domains by construction. I came up with the following approach (fully
>> untested):
>>>>>>>
>>>>>>> diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
>>>>>>> index 281a40f..7779796 100644
>>>>>>> --- a/include/linux/irqdomain.h
>>>>>>> +++ b/include/linux/irqdomain.h
>>>>>>> @@ -183,8 +183,11 @@ enum {
>>>>>>> /* Irq domain is an IPI domain with single virq */
>>>>>>> IRQ_DOMAIN_FLAG_IPI_SINGLE = (1 << 3),
>>>>>>>
>>>>>>> + /* Irq domain implements MSIs */
>>>>>>> + IRQ_DOMAIN_FLAG_MSI = (1 << 4),
>>>>>>> +
>>>>>>> /* Irq domain is MSI remapping capable */
>>>>>>> - IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 4),
>>>>>>> + IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 5),
>>>>>>>
>>>>>>> /*
>>>>>>> * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved
>> @@
>>>>>>> -450,6 +453,11 @@ static inline bool
>>>>>>> irq_domain_is_ipi_single(struct irq_domain *domain) {
>>>>>>> return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE; }
>>>>>>> +
>>>>>>> +static inline bool irq_domain_is_msi(struct irq_domain *domain) {
>>>>>>> + return domain->flags & IRQ_DOMAIN_FLAG_MSI; }
>>>>>>> #else /* CONFIG_IRQ_DOMAIN_HIERARCHY */
>>>>>>> static inline void irq_domain_activate_irq(struct irq_data *data)
>>>>>>> { } static inline void irq_domain_deactivate_irq(struct irq_data
>>>>>>> *data) { } @@ -481,6 +489,11 @@ static inline bool
>>>>>>> irq_domain_is_ipi_single(struct irq_domain *domain) {
>>>>>>> return false;
>>>>>>> }
>>>>>>> +
>>>>>>> +static inline bool irq_domain_is_msi(struct irq_domain *domain) {
>>>>>>> + return false;
>>>>>>> +}
>>>>>>> #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
>>>>>>>
>>>>>>> #else /* CONFIG_IRQ_DOMAIN */
>>>>>>> diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index
>>>>>>> 700caea..33b6921 100644
>>>>>>> --- a/kernel/irq/irqdomain.c
>>>>>>> +++ b/kernel/irq/irqdomain.c
>>>>>>> @@ -304,10 +304,7 @@ bool irq_domain_check_msi_remap(void)
>>>>>>>
>>>>>>> mutex_lock(&irq_domain_mutex);
>>>>>>> list_for_each_entry(h, &irq_domain_list, link) {
>>>>>>> - if (((h->bus_token & DOMAIN_BUS_PCI_MSI) ||
>>>>>>> - (h->bus_token & DOMAIN_BUS_PLATFORM_MSI)
>> ||
>>>>>>> - (h->bus_token & DOMAIN_BUS_FSL_MC_MSI))
>> &&
>>>>>>> - !irq_domain_is_msi_remap(h)) {
>>>>>>> + if (irq_domain_is_msi(h) &&
>> !irq_domain_is_msi_remap(h)) {
>>>>>>> ret = false;
>>>>>>> goto out;
>>>>>>> }
>>>>>>> diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index
>>>>>>> ee23006..b637263 100644
>>>>>>> --- a/kernel/irq/msi.c
>>>>>>> +++ b/kernel/irq/msi.c
>>>>>>> @@ -270,7 +270,7 @@ struct irq_domain
>> *msi_create_irq_domain(struct fwnode_handle *fwnode,
>>>>>>> if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
>>>>>>> msi_domain_update_chip_ops(info);
>>>>>>>
>>>>>>> - return irq_domain_create_hierarchy(parent, 0, 0, fwnode,
>>>>>>> + return irq_domain_create_hierarchy(parent,
>> IRQ_DOMAIN_FLAG_MSI,
>>>>>>> +0, fwnode,
>>>>>>> &msi_domain_ops, info);
>>>>>>> }
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> Thoughts?
>>>>>>
>>>>>> Don't we need to set the IRQ_DOMAIN_FLAG_MSI flag in
>>>>>> platform_msi_create_device_domain too (drivers/base/platform-
>> msi.c)?
>>>> was mentioning platform_msi_create_*device*_domain.
>>>> it calls irq_domain_create_hierarchy and looks to be MSI irq domain
>>>> related. But I don't have a full understanding of the whole irq
>>>> domain hierarchy.
>>>
>>> Ah, sorry - I blame the ARM coffee.
>>>
>>> This function builds a domain for a single device on top of the MSI
>>> domain that has been already created (see the dev->msi_domain passed
>>> to irq_domain_create_hierarchy). The structure looks like this:
>>>
>>> device-domain -> platform MSI domain -> HW MSI domain -> whatever
>>>
>>> So what we're *really* interested in is the platform MSI domain, which
>>> is going to carry the IRQ_DOMAIN_FLAG_MSI flag. The device-domain only
>>> describes a portion of it, and can safely be ignored.
>>>
>>> In the end, what matters for this patch is that we can prove that from
>>> any domain carrying the IRQ_DOMAIN_FLAG_MSI flag, we can find a
>> domain
>>> carrying the IRQ_DOMAIN_FLAG_MSI_REMAP flag. If that property holds,
>>> we're safe. Otherwise, we disable the Guest MSI feature.
>>>
>>> Does it make sense?
>> Yes it makes sense. Thank you for the explanation!
>
> If I understood correctly then the domain hierarchy is
>
> -> "gic-irq-domain"
> -> "gic-its-irq-domain"
> -> "platform-msi-domain"
> -> "pci-msi-domain"
> -> "fsl-mc-msi-domain"
>
> "gic-its-irq-domain" carries IRQ_DOMAIN_FLAG_MSI_REMAP
>
> So we need to look for the IRQ_DOMAIN_FLAG_MSI_REMAP flag in "gic-its-irq-domain" when doing safety check for "platform/pci/fsl-mc"-msi-irqdomain, is this what you mentioned?
>
> Can we can pass this flags from "gic-its-irq-domain" to "platform/pci/fsl-mc"-msi-irqdomain during domain creation?
fsl_mc_msi_create_irq_domain (drivers/staging/fsl-mc/bus/fsl-mc-msi.c)
calls msi_create_irq_domain. So the associated domain carries the
IRQ_DOMAIN_FLAG_MSI flag. The code will check whether any parent carries
the IRQ_DOMAIN_FLAG_MSI flag. This will be the case (gic-its-irq-domain).
Does it answer your question?
Thanks
Eric
>
> Thanks
> -Bharat
>
>>
>> Eric
>>>
>>> Thanks,
>>>
>>> M.
>>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH v3] arm64: mm: Fix NOMAP page initialization
From: Ard Biesheuvel @ 2017-01-06 8:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cbbf14fd-a1cc-2463-ba67-acd6d61e9db1@linaro.org>
On 6 January 2017 at 01:07, Hanjun Guo <hanjun.guo@linaro.org> wrote:
> On 2017/1/5 10:03, Hanjun Guo wrote:
>>
>> On 2017/1/4 21:56, Ard Biesheuvel wrote:
>>>
>>> On 16 December 2016 at 16:54, Robert Richter <rrichter@cavium.com> wrote:
>>>>
>>>> On ThunderX systems with certain memory configurations we see the
>>>> following BUG_ON():
>>>>
>>>> kernel BUG at mm/page_alloc.c:1848!
>>>>
>>>> This happens for some configs with 64k page size enabled. The BUG_ON()
>>>> checks if start and end page of a memmap range belongs to the same
>>>> zone.
>>>>
>>>> The BUG_ON() check fails if a memory zone contains NOMAP regions. In
>>>> this case the node information of those pages is not initialized. This
>>>> causes an inconsistency of the page links with wrong zone and node
>>>> information for that pages. NOMAP pages from node 1 still point to the
>>>> mem zone from node 0 and have the wrong nid assigned.
>>>>
>>>> The reason for the mis-configuration is a change in pfn_valid() which
>>>> reports pages marked NOMAP as invalid:
>>>>
>>>> 68709f45385a arm64: only consider memblocks with NOMAP cleared for
>>>> linear mapping
>>>>
>>>> This causes pages marked as nomap being no longer reassigned to the
>>>> new zone in memmap_init_zone() by calling __init_single_pfn().
>>>>
>>>> Fixing this by implementing an arm64 specific early_pfn_valid(). This
>>>> causes all pages of sections with memory including NOMAP ranges to be
>>>> initialized by __init_single_page() and ensures consistency of page
>>>> links to zone, node and section.
>>>>
>>>
>>> I like this solution a lot better than the first one, but I am still
>>> somewhat uneasy about having the kernel reason about attributes of
>>> pages it should not touch in the first place. But the fact that
>>> early_pfn_valid() is only used a single time in the whole kernel does
>>> give some confidence that we are not simply moving the problem
>>> elsewhere.
>>>
>>> Given that you are touching arch/arm/ as well as arch/arm64, could you
>>> explain why only arm64 needs this treatment? Is it simply because we
>>> don't have NUMA support there?
>>>
>>> Considering that Hisilicon D05 suffered from the same issue, I would
>>> like to get some coverage there as well. Hanjun, is this something you
>>> can arrange? Thanks
>>
>>
>> Sure, we will test this patch with LTP MM stress test (which triggers
>> the bug on D05), and give the feedback.
>
>
> a update here, tested on 4.9,
>
> - Applied Ard's two patches only
> - Applied Robert's patch only
>
> Both of them can work fine on D05 with NUMA enabled, which means
> boot ok and LTP MM stress test is passed.
>
Thanks a lot Hanjun.
Any comments on the performance impact (including boot time) ?
^ permalink raw reply
* [PATCH v3 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-06 8:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106075914.y5nuak3bz3zrvvex@gangnam.samsung>
On Fri, Jan 06, 2017 at 04:59:14PM +0900, Andi Shyti wrote:
> Hi,
>
> On Fri, Jan 06, 2017 at 09:09:11AM +0200, Krzysztof Kozlowski wrote:
> > On Fri, Jan 06, 2017 at 12:59:06PM +0900, Jaechul Lee wrote:
> > > From: Andi Shyti <andi.shyti@samsung.com>
> > >
> > > Currently tm2e dts includes tm2 but there are some differences
> > > between the two boards and tm2 has some properties that tm2e
> > > doesn't have.
> > >
> > > That's why it's important to keep the two dts files independent
> > > and put all the commonalities in a tm2-common.dtsi file.
> > >
> > > At the current status the only two differences between the two
> > > dts files (besides the board name) are ldo31 and ldo38.
> > >
> > > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> > > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> > > ---
> > > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1118 +++++++++++++++++++
> > > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1153 +-------------------
> >
> > Like talking to a wall. Without any feedback. If my instructions were
> > wrong (and it is not possible to detect rename) then please say it (you
> > can add personal comments after separator ---).
>
> no Krzysztof, I'm sorry, but this patch has been formatted with
> the diff algorithm *you* asked, -B50% both version 2 (where you
> didn't comment) and version 3. If you still don't like it, please
> don't blame me, blame the algorithm.
If you wrote it in cover letter or after '---' I wouldn't complain
because I would know that my feedback was ignored. But here it is like
black hole - I do not know whether I was ignored or it was not working.
>
> Now we can stay here at trying random diff algorithms (as they
> give more or less the same result) or you tell me which exact
> algorithm you want me to use. Besides, for me it's clear,
> tm2-common is all new, while in tm2 you have on one side the '-'
> (if it applies nothing has changed) on the bottom the '+'.
Maybe that depends on the git?
$ git --version
git version 2.9.3
$ git format-patch -2 -B50%
...
21 ...ynos5433-tm2.dts => exynos5433-tm2-common.dtsi} | 24 +-
22 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1153 +-------------------
23 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 22 +-
24 3 files changed, 56 insertions(+), 1143 deletions(-)
25 copy arch/arm64/boot/dts/exynos/{exynos5433-tm2.dts => exynos5433-tm2-common.dtsi} (98%)
26 rewrite arch/arm64/boot/dts/exynos/exynos5433-tm2.dts (98%)
Best regards,
Krzysztof
^ permalink raw reply
* [PATCHv3 2/5] arm: mvebu: support for SMP on 98DX3336 SoC
From: Chris Packham @ 2017-01-06 8:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106063602.GM17126@codeaurora.org>
On 06/01/17 19:44, Stephen Boyd wrote:
> On 01/06, Chris Packham wrote:
>> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
>> index 46c742d3bd41..3c9ab9a008ad 100644
>> --- a/arch/arm/mach-mvebu/platsmp.c
>> +++ b/arch/arm/mach-mvebu/platsmp.c
>> @@ -182,5 +182,48 @@ const struct smp_operations armada_xp_smp_ops __initconst = {
>> #endif
>> };
>>
>> +static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
>> +{
>> + int ret, hw_cpu;
>> +
>> + pr_info("Booting CPU %d\n", cpu);
>
> Doesn't the core already print something when bringing up CPUs?
> This message seems redundant.
>
Copied from armada_xp_boot_secondary but that's no reason to keep it.
Will remove in v4.
>> +
>> + hw_cpu = cpu_logical_map(cpu);
>> + set_secondary_cpu_clock(hw_cpu);
>> + mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
>> + armada_xp_secondary_startup);
>> +
>> + /*
>> + * This is needed to wake up CPUs in the offline state after
>> + * using CPU hotplug.
>> + */
>> + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
>> +
>> + /*
>> + * This is needed to take secondary CPUs out of reset on the
>> + * initial boot.
>> + */
>> + ret = mvebu_cpu_reset_deassert(hw_cpu);
>> + if (ret) {
>> + pr_warn("unable to boot CPU: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +struct smp_operations mv98dx3236_smp_ops __initdata = {
>
> static const __initconst?
>
Will do.
>> + .smp_init_cpus = armada_xp_smp_init_cpus,
>> + .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
>> + .smp_boot_secondary = mv98dx3236_boot_secondary,
>> + .smp_secondary_init = armada_xp_secondary_init,
>> +#ifdef CONFIG_HOTPLUG_CPU
>> + .cpu_die = armada_xp_cpu_die,
>> + .cpu_kill = armada_xp_cpu_kill,
>> +#endif
>> +};
>> +
>> CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
>> &armada_xp_smp_ops);
>> +CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
>> + &mv98dx3236_smp_ops);
>> diff --git a/arch/arm/mach-mvebu/pmsu-98dx3236.c b/arch/arm/mach-mvebu/pmsu-98dx3236.c
>> new file mode 100644
>> index 000000000000..1052674dd439
>> --- /dev/null
>> +++ b/arch/arm/mach-mvebu/pmsu-98dx3236.c
>> @@ -0,0 +1,52 @@
>> +/**
>> + * CPU resume support for 98DX3236 internal CPU (a.k.a. MSYS).
>> + */
>> +
>> +#define pr_fmt(fmt) "mv98dx3236-resume: " fmt
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/of_address.h>
>> +#include <linux/io.h>
>> +#include "common.h"
>> +
>> +static void __iomem *mv98dx3236_resume_base;
>> +#define MV98DX3236_CPU_RESUME_CTRL_OFFSET 0x08
>> +#define MV98DX3236_CPU_RESUME_ADDR_OFFSET 0x04
>> +
>> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
>> + {.compatible = "marvell,98dx3336-resume-ctrl",},
>> + { /* end of list */ },
>> +};
>> +
>> +void mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
>> +{
>> + WARN_ON(hw_cpu != 1);
>> +
>> + writel(0, mv98dx3236_resume_base + MV98DX3236_CPU_RESUME_CTRL_OFFSET);
>> + writel(virt_to_phys(boot_addr), mv98dx3236_resume_base +
>> + MV98DX3236_CPU_RESUME_ADDR_OFFSET);
>> +}
>> +
>> +static int __init mv98dx3236_resume_init(void)
>> +{
>> + struct device_node *np;
>> + void __iomem *base;
>> +
>> + np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
>> + if (!np)
>> + return 0;
>
> Is there any reason we can't just look for this node from the
> smp_ops and map it if it isn't mapped yet? Seems simpler than a
> whole new file and initcall.
>
That's at least 2 votes for rolling it into platsmp.c. The amount of
code has been significantly reduced so I think I will do it for v4.
>> +
>> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
>> + if (IS_ERR(base)) {
>> + pr_err("unable to map registers\n");
>
> Doesn't of_io_request_and_map() spit out an error on failure
> already?
>
Not that I can see. But as has been previously mentioned a CPU failing
to come online is reasonably obvious already.
>> + of_node_put(np);
>
> This could be done before the if statement and then the duplicate
> statement deleted.
>
Will do.
>> + return PTR_ERR(mv98dx3236_resume_base);
>
> Should be PTR_ERR(base)?
Yes. I decided to add the local variable at the last minute.
>
>> + }
>> +
>> + mv98dx3236_resume_base = base;
>> + of_node_put(np);
>> + return 0;
>> +}
>
^ permalink raw reply
* [PATCH v6 17/18] vfio/type1: Check MSI remapping at irq domain level
From: Bharat Bhushan @ 2017-01-06 8:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483643086-2883-18-git-send-email-eric.auger@redhat.com>
Hi Eric,
> -----Original Message-----
> From: Eric Auger [mailto:eric.auger at redhat.com]
> Sent: Friday, January 06, 2017 12:35 AM
> To: eric.auger at redhat.com; eric.auger.pro at gmail.com;
> christoffer.dall at linaro.org; marc.zyngier at arm.com;
> robin.murphy at arm.com; alex.williamson at redhat.com;
> will.deacon at arm.com; joro at 8bytes.org; tglx at linutronix.de;
> jason at lakedaemon.net; linux-arm-kernel at lists.infradead.org
> Cc: kvm at vger.kernel.org; drjones at redhat.com; linux-
> kernel at vger.kernel.org; pranav.sawargaonkar at gmail.com;
> iommu at lists.linux-foundation.org; punit.agrawal at arm.com; Diana Madalina
> Craciun <diana.craciun@nxp.com>; gpkulkarni at gmail.com;
> shankerd at codeaurora.org; Bharat Bhushan <bharat.bhushan@nxp.com>;
> geethasowjanya.akula at gmail.com
> Subject: [PATCH v6 17/18] vfio/type1: Check MSI remapping at irq domain
> level
>
> In case the IOMMU translates MSI transactions (typical case on ARM), we
> check MSI remapping capability at IRQ domain level. Otherwise it is checked
> at IOMMU level.
>
> At this stage the arm-smmu-(v3) still advertise the
> IOMMU_CAP_INTR_REMAP capability at IOMMU level. This will be removed
> in subsequent patches.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
>
> v6: rewrite test
> ---
> drivers/vfio/vfio_iommu_type1.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/vfio/vfio_iommu_type1.c
> b/drivers/vfio/vfio_iommu_type1.c index b473ef80..fa0b5c4 100644
> --- a/drivers/vfio/vfio_iommu_type1.c
> +++ b/drivers/vfio/vfio_iommu_type1.c
> @@ -40,6 +40,7 @@
> #include <linux/mdev.h>
> #include <linux/notifier.h>
> #include <linux/dma-iommu.h>
> +#include <linux/irqdomain.h>
>
> #define DRIVER_VERSION "0.2"
> #define DRIVER_AUTHOR "Alex Williamson
> <alex.williamson@redhat.com>"
> @@ -1208,7 +1209,7 @@ static int vfio_iommu_type1_attach_group(void
> *iommu_data,
> struct vfio_domain *domain, *d;
> struct bus_type *bus = NULL, *mdev_bus;
> int ret;
> - bool resv_msi;
> + bool resv_msi, msi_remap;
> phys_addr_t resv_msi_base;
>
> mutex_lock(&iommu->lock);
> @@ -1284,8 +1285,10 @@ static int vfio_iommu_type1_attach_group(void
> *iommu_data,
> INIT_LIST_HEAD(&domain->group_list);
> list_add(&group->next, &domain->group_list);
>
> - if (!allow_unsafe_interrupts &&
> - !iommu_capable(bus, IOMMU_CAP_INTR_REMAP)) {
> + msi_remap = resv_msi ? irq_domain_check_msi_remap() :
There can be multiple interrupt-controller, at-least theoretically it is possible and not sure practically it exists and supported, where not all may support IRQ_REMAP. If that is the case be then should we check for IRQ-REMAP for that device-bus irq-domain?
Thanks
-Bharat
> + iommu_capable(bus,
> IOMMU_CAP_INTR_REMAP);
> +
> + if (!allow_unsafe_interrupts && !msi_remap) {
> pr_warn("%s: No interrupt remapping support. Use the
> module param \"allow_unsafe_interrupts\" to enable VFIO IOMMU support
> on this platform\n",
> __func__);
> ret = -EPERM;
> --
> 1.9.1
^ permalink raw reply
* [PATCH v3 1/5] arm64: dts: exynos5433: TM2/E: Fix wrong information of ldo23 and ldo25
From: Krzysztof Kozlowski @ 2017-01-06 8:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <586F4554.6020206@samsung.com>
On Fri, Jan 06, 2017 at 04:20:52PM +0900, Chanwoo Choi wrote:
> On 2017? 01? 06? 16:05, Krzysztof Kozlowski wrote:
> > On Fri, Jan 06, 2017 at 12:59:05PM +0900, Jaechul Lee wrote:
> >> From: Chanwoo Choi <cw00.choi@samsung.com>
> >>
> >> This patch fixes the wrong information of ldo23 and ldo25 on both TM2 and TM2E.
> >
> > Please describe what is exactly wrong and how it affects the
> > system/user. This is going to the fixes so it needs a good explanation.
>
> When I posted the patch[1], I refer to the old schematic document of both TM2 and TM2E.
> [1] 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
>
> After checking the highest version of schematic document of both TM2 and TM2E,
> there is no difference of ldo23/ldo25 on both TM2 and TM2E.
> - ldo23 is used on TM2/TM2E, but the name/max-microvolt are wrong.
> - ldo25 isn't used on TM2/TM2E. (not connected)
>
> Because ldo23 and lod25 are not used on other device in Exynos5433 and TM2 board.
> this patch does not affect the operation to system/user.
If it does not affect anyone (including TM2/TM2E) then this do not have
to be a fix. Am I right?
Best regards,
Krzysztof
^ permalink raw reply
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