* [PATCH V9 7/9] dmaengine: pl330: Make sure microcode is privileged
From: Sricharan R @ 2017-01-06 13:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483709296-32761-1-git-send-email-sricharan@codeaurora.org>
From: Mitchel Humpherys <mitchelh@codeaurora.org>
The PL330 is hard-wired such that instruction fetches on both the
manager and channel threads go out onto the bus with the "privileged"
bit set. This can become troublesome once there is an IOMMU or other
form of memory protection downstream, since those will typically be
programmed by the DMA mapping subsystem in the expectation of normal
unprivileged transactions (such as the PL330 channel threads' own data
accesses as currently configured by this driver).
To avoid the case of, say, an IOMMU blocking an unexpected privileged
transaction with a permission fault, use the newly-introduced
DMA_ATTR_PRIVILEGED attribute for the mapping of our microcode buffer.
That way the DMA layer can do whatever it needs to do to make things
continue to work as expected on more complex systems.
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Vinod Koul <vinod.koul@intel.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
[rm: remove now-redundant local variable, clarify commit message]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/dma/pl330.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 87fd015..5a90d0c 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -1864,9 +1864,10 @@ static int dmac_alloc_resources(struct pl330_dmac *pl330)
* Alloc MicroCode buffer for 'chans' Channel threads.
* A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
*/
- pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
+ pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
chans * pl330->mcbufsz,
- &pl330->mcode_bus, GFP_KERNEL);
+ &pl330->mcode_bus, GFP_KERNEL,
+ DMA_ATTR_PRIVILEGED);
if (!pl330->mcode_cpu) {
dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
__func__, __LINE__);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V9 8/9] iommu/arm-smmu: Set privileged attribute to 'default' instead of 'unprivileged'
From: Sricharan R @ 2017-01-06 13:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483709296-32761-1-git-send-email-sricharan@codeaurora.org>
Currently the driver sets all the device transactions privileges
to UNPRIVILEGED, but there are cases where the iommu masters wants
to isolate privileged supervisor and unprivileged user.
So don't override the privileged setting to unprivileged, instead
set it to default as incoming and let it be controlled by the pagetable
settings.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/iommu/arm-smmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a60cded..73a0a25 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1214,7 +1214,7 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
continue;
s2cr[idx].type = type;
- s2cr[idx].privcfg = S2CR_PRIVCFG_UNPRIV;
+ s2cr[idx].privcfg = S2CR_PRIVCFG_DEFAULT;
s2cr[idx].cbndx = cbndx;
arm_smmu_write_s2cr(smmu, idx);
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V9 9/9] Revert "iommu/arm-smmu: Set PRIVCFG in stage 1 STEs"
From: Sricharan R @ 2017-01-06 13:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483709296-32761-1-git-send-email-sricharan@codeaurora.org>
From: Robin Murphy <robin.murphy@arm.com>
This reverts commit df5e1a0f2a2d779ad467a691203bcbc74d75690e.
Now that proper privileged mappings can be requested via IOMMU_PRIV,
unconditionally overriding the incoming PRIVCFG becomes the wrong thing
to do, so stop it.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/iommu/arm-smmu-v3.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 4d6ec44..7d45d8b 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -269,9 +269,6 @@
#define STRTAB_STE_1_SHCFG_INCOMING 1UL
#define STRTAB_STE_1_SHCFG_SHIFT 44
-#define STRTAB_STE_1_PRIVCFG_UNPRIV 2UL
-#define STRTAB_STE_1_PRIVCFG_SHIFT 48
-
#define STRTAB_STE_2_S2VMID_SHIFT 0
#define STRTAB_STE_2_S2VMID_MASK 0xffffUL
#define STRTAB_STE_2_VTCR_SHIFT 32
@@ -1073,9 +1070,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
#ifdef CONFIG_PCI_ATS
STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
#endif
- STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT |
- STRTAB_STE_1_PRIVCFG_UNPRIV <<
- STRTAB_STE_1_PRIVCFG_SHIFT);
+ STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
if (smmu->features & ARM_SMMU_FEAT_STALLS)
dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [GIT PULL] ARM: OXNAS SoC DT updates for 4.11
From: Neil Armstrong @ 2017-01-06 13:39 UTC (permalink / raw)
To: linux-arm-kernel
Dear arm-soc maintainers,
The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88:
Linux 4.10-rc2 (2017-01-01 14:31:53 -0800)
are available in the git repository at:
https://github.com/OXNAS/linux.git tags/oxnas-arm-soc-dt-for-4.11
for you to fetch changes up to 0c5987d3e3c5bf7fb861230ee6d2a0f17a1dcd3b:
ARM: dts: OX820: Update with dt-bindings includes (2017-01-04 10:31:34 +0100)
----------------------------------------------------------------
- Add dt-bindings includes for OX820 and OX810SE dtsi
- Replace reset and clock magic numbers for OX820 and OX810SE
----------------------------------------------------------------
Neil Armstrong (2):
ARM: dts: OX810: Update with dt-bindings includes
ARM: dts: OX820: Update with dt-bindings includes
arch/arm/boot/dts/ox810se.dtsi | 10 ++++++----
arch/arm/boot/dts/ox820.dtsi | 14 ++++++++------
2 files changed, 14 insertions(+), 10 deletions(-)
Thanks,
Neil
^ permalink raw reply
* [PATCH v5 0/5] Add touch key driver support for TM2
From: Andi Shyti @ 2017-01-06 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CGME20170106134355epcas1p171f1f3b3c20c6a92e7736c1639ea2dd8@epcas1p1.samsung.com>
Hi,
I'll send this patch on behalf of Jaechul Lee
<jcsing.lee@samsung.com> becasue I don't want to block
anyone who wants to make changes to the exynos5433-tm2*dts*
files.
This patches are based on Krzysztof's branch for-next [1] and
this was the original Jaechul's mail:
"This patchset adds support for the tm2 touchkey device.
The driver has been ported from Tizen Kernel,
originally written
by Beomho. I ported it to the latest mainline Kernel."
Thanks and hopefully I got it right :)
Andi
[1] https://git.kernel.org/cgit/linux/kernel/git/krzk/linux.git/log/?h=for-next
Changes in v5:
- patch 1: removed a spurious regulator-always-off inherited from
a different patch. Thanks Krzysztof.
- patch 2: fixed a slip on the model, thanks Javier (this patch
confuses me quite a lot, this was all right some patches ago
and re appeared on this one).
- patch 2: removed 'regulator' label and used the original ldo3x
labels. Krzysztof: it looks better indeed.
- added Javier's reviews and Krzysztof's acks on the related
patches.
Changes in v4:
- patch 1 has been rebased on top of 7c294e002641 (arm64: dts:
exynos: Remove unsupported regulator-always-off property from
TM2E)
- patch 2 has been generated with -B50% diff option using git
2.11
Changes in v3:
- Changed the commit ordering, the tm2-touchkey related patches
are the last 3.
- Added Chanwoo's patch which fixes the wrong voltage of ldo23
and ldo25.
- Andi (patch 3) moves the ldo31 and ldo38 in the tm2 and tm2e
files as they have different values.
Changes in v2:
- fixed reviews from Javier, Dmitry
- refactored power enable/disable functions.
- reordered signed-offs in patch 2, while patch 4 is left as it
was as Andi copy pasted the node to the new tm2.dts file
- added Jarvier's (patch 1,2,4) and Krzysztof's (patch 4)
reviews
and Rob's Ack
- patch 3 diff has been generated with -B50%
Andi Shyti (1):
arm64: dts: exynos: make tm2 and tm2e independent from each other
Andi Shyti (1):
arm64: dts: exynos: make tm2 and tm2e independent from each other
Chanwoo Choi (1):
arm64: dts: exynos5433: TM2/E: Fix wrong values for ldo23 and ldo25
Jaechul Lee (3):
input: Add support for the tm2 touchkey device driver
input: tm2-touchkey: Add touchkey driver support for TM2
arm64: dts: exynos: Add tm2 touchkey node
.../bindings/input/samsung,tm2-touchkey.txt | 27 +
...ynos5433-tm2.dts => exynos5433-tm2-common.dtsi} | 27 +-
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1163 +-------------------
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 11 +-
drivers/input/keyboard/Kconfig | 11 +
drivers/input/keyboard/Makefile | 1 +
drivers/input/keyboard/tm2-touchkey.c | 280 +++++
7 files changed, 377 insertions(+), 1143 deletions(-)
create mode 100644 Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
copy arch/arm64/boot/dts/exynos/{exynos5433-tm2.dts => exynos5433-tm2-common.dtsi} (97%)
rewrite arch/arm64/boot/dts/exynos/exynos5433-tm2.dts (97%)
create mode 100644 drivers/input/keyboard/tm2-touchkey.c
--
2.11.0
^ permalink raw reply
* [PATCH v5 1/5] arm64: dts: exynos5433: TM2/E: Fix wrong values for ldo23 and ldo25
From: Andi Shyti @ 2017-01-06 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134350.32428-1-andi.shyti@samsung.com>
From: Chanwoo Choi <cw00.choi@samsung.com>
This patch fixes wrong values assigned to ldo23 and ldo25 on both TM2 and TM2E.
Fixes: 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 6 +++---
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 9 ---------
2 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 3b5215c40fcd..640e4b9910ae 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -504,9 +504,9 @@
};
ldo23_reg: LDO23 {
- regulator-name = "CAM_SEN_CORE_1.2V_AP";
+ regulator-name = "CAM_SEN_CORE_1.05V_AP";
regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1050000>;
};
ldo24_reg: LDO24 {
@@ -516,7 +516,7 @@
};
ldo25_reg: LDO25 {
- regulator-name = "CAM_SEN_A2.8V_AP";
+ regulator-name = "UNUSED_LDO25";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 398f5e092b02..854c583092d5 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -18,15 +18,6 @@
compatible = "samsung,tm2e", "samsung,exynos5433";
};
-&ldo23_reg {
- regulator-name = "CAM_SEN_CORE_1.025V_AP";
- regulator-max-microvolt = <1050000>;
-};
-
-&ldo25_reg {
- regulator-name = "UNUSED_LDO25";
-};
-
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
--
2.11.0
^ permalink raw reply related
* [PATCH v5 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-06 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134350.32428-1-andi.shyti@samsung.com>
Currently tm2e dts includes tm2 but there are some differences
between the two boards and tm2 has some properties that tm2e
doesn't have.
That's why it's important to keep the two dts files independent
and put all the commonalities in a tm2-common.dtsi file.
At the current status the only two differences between the two
dts files (besides the board name) are ldo31 and ldo38.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
...ynos5433-tm2.dts => exynos5433-tm2-common.dtsi} | 21 +-
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1150 +-------------------
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
3 files changed, 42 insertions(+), 1131 deletions(-)
copy arch/arm64/boot/dts/exynos/{exynos5433-tm2.dts => exynos5433-tm2-common.dtsi} (98%)
rewrite arch/arm64/boot/dts/exynos/exynos5433-tm2.dts (98%)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
similarity index 98%
copy from arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
copy to arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 640e4b9910ae..cc6701b3bce4 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -3,8 +3,8 @@
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
*
- * Device tree source file for Samsung's TM2 board which is based on
- * Samsung Exynos5433 SoC.
+ * Common device tree source file for Samsung's TM2 and TM2E boards
+ * which are based on Samsung Exynos5433 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -19,9 +19,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
- model = "Samsung TM2 board";
- compatible = "samsung,tm2", "samsung,exynos5433";
-
aliases {
gsc0 = &gsc_0;
gsc1 = &gsc_1;
@@ -552,9 +549,10 @@
};
ldo31_reg: LDO31 {
- regulator-name = "TSP_VDD_1.85V_AP";
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <1850000>;
+ /*
+ * LDO31 differs from target to target,
+ * its definition is in the .dts
+ */
};
ldo32_reg: LDO32 {
@@ -595,9 +593,10 @@
};
ldo38_reg: LDO38 {
- regulator-name = "VCC_3.0V_MOTOR_AP";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ /*
+ * LDO38 differs from target to target,
+ * its definition is in the .dts
+ */
};
ldo39_reg: LDO39 {
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
dissimilarity index 98%
index 640e4b9910ae..2449266b268f 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -1,1119 +1,31 @@
-/*
- * SAMSUNG Exynos5433 TM2 board device tree source
- *
- * Copyright (c) 2016 Samsung Electronics Co., Ltd.
- *
- * Device tree source file for Samsung's TM2 board which is based on
- * Samsung Exynos5433 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/dts-v1/;
-#include "exynos5433.dtsi"
-#include <dt-bindings/clock/samsung,s2mps11.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "Samsung TM2 board";
- compatible = "samsung,tm2", "samsung,exynos5433";
-
- aliases {
- gsc0 = &gsc_0;
- gsc1 = &gsc_1;
- gsc2 = &gsc_2;
- pinctrl0 = &pinctrl_alive;
- pinctrl1 = &pinctrl_aud;
- pinctrl2 = &pinctrl_cpif;
- pinctrl3 = &pinctrl_ese;
- pinctrl4 = &pinctrl_finger;
- pinctrl5 = &pinctrl_fsys;
- pinctrl6 = &pinctrl_imem;
- pinctrl7 = &pinctrl_nfc;
- pinctrl8 = &pinctrl_peric;
- pinctrl9 = &pinctrl_touch;
- serial0 = &serial_0;
- serial1 = &serial_1;
- serial2 = &serial_2;
- serial3 = &serial_3;
- spi0 = &spi_0;
- spi1 = &spi_1;
- spi2 = &spi_2;
- spi3 = &spi_3;
- spi4 = &spi_4;
- mshc0 = &mshc_0;
- mshc2 = &mshc_2;
- };
-
- chosen {
- stdout-path = &serial_1;
- };
-
- memory at 20000000 {
- device_type = "memory";
- reg = <0x0 0x20000000 0x0 0xc0000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- power-key {
- gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- label = "power key";
- debounce-interval = <10>;
- };
-
- volume-up-key {
- gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- label = "volume-up key";
- debounce-interval = <10>;
- };
-
- volume-down-key {
- gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- label = "volume-down key";
- debounce-interval = <10>;
- };
-
- homepage-key {
- gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_MENU>;
- label = "homepage key";
- debounce-interval = <10>;
- };
- };
-
- i2c_max98504: i2c-gpio-0 {
- compatible = "i2c-gpio";
- gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
- &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- max98504: max98504 at 31 {
- compatible = "maxim,max98504";
- reg = <0x31>;
- maxim,rx-path = <1>;
- maxim,tx-path = <1>;
- maxim,tx-channel-mask = <3>;
- maxim,tx-channel-source = <2>;
- };
- };
-
- sound {
- compatible = "samsung,tm2-audio";
- audio-codec = <&wm5110>;
- i2s-controller = <&i2s0>;
- audio-amplifier = <&max98504>;
- mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
- model = "wm5110";
- samsung,audio-routing =
- /* Headphone */
- "HP", "HPOUT1L",
- "HP", "HPOUT1R",
-
- /* Speaker */
- "SPK", "SPKOUT",
- "SPKOUT", "HPOUT2L",
- "SPKOUT", "HPOUT2R",
-
- /* Receiver */
- "RCV", "HPOUT3L",
- "RCV", "HPOUT3R";
- status = "okay";
- };
-};
-
-&adc {
- vdd-supply = <&ldo3_reg>;
- status = "okay";
-
- thermistor-ap {
- compatible = "murata,ncp03wf104";
- pullup-uv = <1800000>;
- pullup-ohm = <100000>;
- pulldown-ohm = <0>;
- io-channels = <&adc 0>;
- };
-
- thermistor-battery {
- compatible = "murata,ncp03wf104";
- pullup-uv = <1800000>;
- pullup-ohm = <100000>;
- pulldown-ohm = <0>;
- io-channels = <&adc 1>;
- #thermal-sensor-cells = <0>;
- };
-
- thermistor-charger {
- compatible = "murata,ncp03wf104";
- pullup-uv = <1800000>;
- pullup-ohm = <100000>;
- pulldown-ohm = <0>;
- io-channels = <&adc 2>;
- };
-};
-
-&bus_g2d_400 {
- devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
- vdd-supply = <&buck4_reg>;
- exynos,saturation-ratio = <10>;
- status = "okay";
-};
-
-&bus_g2d_266 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_gscl {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_hevc {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_jpeg {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_mfc {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_mscl {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_noc0 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_noc1 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&bus_noc2 {
- devfreq = <&bus_g2d_400>;
- status = "okay";
-};
-
-&cmu_aud {
- assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
- assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
-};
-
-&cmu_fsys {
- assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
- <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
- <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
- <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
- <&cmu_top CLK_DIV_SCLK_USBDRD30>,
- <&cmu_top CLK_DIV_SCLK_USBHOST30>;
- assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
- <&cmu_top CLK_MOUT_BUS_PLL_USER>,
- <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
- <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
- assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
- <66700000>, <66700000>;
-};
-
-&cmu_gscl {
- assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
- <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
- assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
- <&cmu_top CLK_ACLK_GSCL_333>;
-};
-
-&cmu_mfc {
- assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
- assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
-};
-
-&cmu_mscl {
- assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
- <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
- <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
- <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
- assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
- <&cmu_top CLK_SCLK_JPEG_MSCL>,
- <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
- <&cmu_top CLK_MOUT_BUS_PLL_USER>;
-};
-
-&cpu0 {
- cpu-supply = <&buck3_reg>;
-};
-
-&cpu4 {
- cpu-supply = <&buck2_reg>;
-};
-
-&decon {
- status = "okay";
-
- i80-if-timings {
- };
-};
-
-&dsi {
- status = "okay";
- vddcore-supply = <&ldo6_reg>;
- vddio-supply = <&ldo7_reg>;
- samsung,pll-clock-frequency = <24000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&te_irq>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port at 1 {
- reg = <1>;
-
- dsi_out: endpoint {
- samsung,burst-clock-frequency = <512000000>;
- samsung,esc-clock-frequency = <16000000>;
- };
- };
- };
-};
-
-&hsi2c_0 {
- status = "okay";
- clock-frequency = <2500000>;
-
- s2mps13-pmic at 66 {
- compatible = "samsung,s2mps13-pmic";
- interrupt-parent = <&gpa0>;
- interrupts = <7 IRQ_TYPE_NONE>;
- reg = <0x66>;
- samsung,s2mps11-wrstbi-ground;
-
- s2mps13_osc: clocks {
- compatible = "samsung,s2mps13-clk";
- #clock-cells = <1>;
- clock-output-names = "s2mps13_ap", "s2mps13_cp",
- "s2mps13_bt";
- };
-
- regulators {
- ldo1_reg: LDO1 {
- regulator-name = "VDD_ALIVE_0.9V_AP";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "VDDQ_MMC2_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "VDD1_E_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "VDD10_MIF_PLL_1.0V_AP";
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo5_reg: LDO5 {
- regulator-name = "VDD10_DPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "VDD10_MIPI2L_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "VDD18_MIPI2L_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "VDD18_LLI_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo9_reg: LDO9 {
- regulator-name = "VDD18_ABB_ETC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "VDD33_USB30_3.0V_AP";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo11_reg: LDO11 {
- regulator-name = "VDD_INT_M_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "VDD_KFC_M_1.1V_AP";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- };
-
- ldo13_reg: LDO13 {
- regulator-name = "VDD_G3D_M_0.95V_AP";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <950000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "VDDQ_M1_LDO_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "VDDQ_M2_LDO_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "VDDQ_EFUSE";
- regulator-min-microvolt = <1400000>;
- regulator-max-microvolt = <3400000>;
- regulator-always-on;
- };
-
- ldo17_reg: LDO17 {
- regulator-name = "V_TFLASH_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo18_reg: LDO18 {
- regulator-name = "V_CODEC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo19_reg: LDO19 {
- regulator-name = "VDDA_1.8V_COMP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo20_reg: LDO20 {
- regulator-name = "VCC_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- ldo21_reg: LDO21 {
- regulator-name = "VT_CAM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo22_reg: LDO22 {
- regulator-name = "CAM_IO_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo23_reg: LDO23 {
- regulator-name = "CAM_SEN_CORE_1.05V_AP";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- ldo24_reg: LDO24 {
- regulator-name = "VT_CAM_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo25_reg: LDO25 {
- regulator-name = "UNUSED_LDO25";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo26_reg: LDO26 {
- regulator-name = "CAM_AF_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo27_reg: LDO27 {
- regulator-name = "VCC_3.0V_LCD_AP";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo28_reg: LDO28 {
- regulator-name = "VCC_1.8V_LCD_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo29_reg: LDO29 {
- regulator-name = "VT_CAM_2.8V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo30_reg: LDO30 {
- regulator-name = "TSP_AVDD_3.3V_AP";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo31_reg: LDO31 {
- regulator-name = "TSP_VDD_1.85V_AP";
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <1850000>;
- };
-
- ldo32_reg: LDO32 {
- regulator-name = "VTOUCH_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo33_reg: LDO33 {
- regulator-name = "VTOUCH_LED_3.3V";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- };
-
- ldo34_reg: LDO34 {
- regulator-name = "VCC_1.8V_MHL_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <2100000>;
- };
-
- ldo35_reg: LDO35 {
- regulator-name = "OIS_VM_2.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo36_reg: LDO36 {
- regulator-name = "VSIL_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo37_reg: LDO37 {
- regulator-name = "VF_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo38_reg: LDO38 {
- regulator-name = "VCC_3.0V_MOTOR_AP";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo39_reg: LDO39 {
- regulator-name = "V_HRM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo40_reg: LDO40 {
- regulator-name = "V_HRM_3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "VDD_MIF_0.9V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "VDD_EGL_1.0V_AP";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "VDD_KFC_1.0V_AP";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "VDD_INT_0.95V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "VDD_DISP_CAM0_0.9V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "VDD_G3D_0.9V_AP";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck7_reg: BUCK7 {
- regulator-name = "VDD_MEM1_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- buck8_reg: BUCK8 {
- regulator-name = "VDD_LLDO_1.35V_AP";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- buck9_reg: BUCK9 {
- regulator-name = "VDD_MLDO_2.0V_AP";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- buck10_reg: BUCK10 {
- regulator-name = "vdd_mem2";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- };
- };
- };
-};
-
-&hsi2c_8 {
- status = "okay";
-
- max77843 at 66 {
- compatible = "maxim,max77843";
- interrupt-parent = <&gpa1>;
- interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
- reg = <0x66>;
-
- muic: max77843-muic {
- compatible = "maxim,max77843-muic";
- };
-
- regulators {
- compatible = "maxim,max77843-regulator";
- safeout1_reg: SAFEOUT1 {
- regulator-name = "SAFEOUT1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <4950000>;
- };
-
- safeout2_reg: SAFEOUT2 {
- regulator-name = "SAFEOUT2";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <4950000>;
- };
-
- charger_reg: CHARGER {
- regulator-name = "CHARGER";
- regulator-min-microamp = <100000>;
- regulator-max-microamp = <3150000>;
- };
- };
-
- haptic: max77843-haptic {
- compatible = "maxim,max77843-haptic";
- haptic-supply = <&ldo38_reg>;
- pwms = <&pwm 0 33670 0>;
- pwm-names = "haptic";
- };
- };
-};
-
-&i2s0 {
- status = "okay";
-};
-
-&mshc_0 {
- status = "okay";
- num-slots = <1>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- cap-mmc-highspeed;
- non-removable;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <0 4>;
- samsung,dw-mshc-ddr-timing = <0 2>;
- samsung,dw-mshc-hs400-timing = <0 3>;
- samsung,read-strobe-delay = <90>;
- fifo-depth = <0x80>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
- &sd0_bus8 &sd0_rdqs>;
- bus-width = <8>;
- assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
- assigned-clock-rates = <800000000>;
-};
-
-&mshc_2 {
- status = "okay";
- num-slots = <1>;
- cap-sd-highspeed;
- disable-wp;
- cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
- cd-inverted;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <0 4>;
- samsung,dw-mshc-ddr-timing = <0 2>;
- fifo-depth = <0x80>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
- bus-width = <4>;
-};
-
-&ppmu_d0_general {
- status = "okay";
- events {
- ppmu_event0_d0_general: ppmu-event0-d0-general {
- event-name = "ppmu-event0-d0-general";
- };
- };
-};
-
-&ppmu_d1_general {
- status = "okay";
- events {
- ppmu_event0_d1_general: ppmu-event0-d1-general {
- event-name = "ppmu-event0-d1-general";
- };
- };
-};
-
-&pinctrl_alive {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_alive>;
-
- initial_alive: initial-state {
- PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
- PIN(INPUT, gpa0-1, NONE, FAST_SR1);
- PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
- PIN(INPUT, gpa0-3, NONE, FAST_SR1);
- PIN(INPUT, gpa0-4, NONE, FAST_SR1);
- PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
- PIN(INPUT, gpa0-6, NONE, FAST_SR1);
- PIN(INPUT, gpa0-7, NONE, FAST_SR1);
-
- PIN(INPUT, gpa1-0, UP, FAST_SR1);
- PIN(INPUT, gpa1-1, NONE, FAST_SR1);
- PIN(INPUT, gpa1-2, NONE, FAST_SR1);
- PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
- PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
- PIN(INPUT, gpa1-5, NONE, FAST_SR1);
- PIN(INPUT, gpa1-6, NONE, FAST_SR1);
- PIN(INPUT, gpa1-7, NONE, FAST_SR1);
-
- PIN(INPUT, gpa2-0, NONE, FAST_SR1);
- PIN(INPUT, gpa2-1, NONE, FAST_SR1);
- PIN(INPUT, gpa2-2, NONE, FAST_SR1);
- PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
- PIN(INPUT, gpa2-4, NONE, FAST_SR1);
- PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
- PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
- PIN(INPUT, gpa2-7, NONE, FAST_SR1);
-
- PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
- PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
- PIN(INPUT, gpa3-2, NONE, FAST_SR1);
- PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
- PIN(INPUT, gpa3-4, NONE, FAST_SR1);
- PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
- PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
- PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
-
- PIN(INPUT, gpf1-0, NONE, FAST_SR1);
- PIN(INPUT, gpf1-1, NONE, FAST_SR1);
- PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
- PIN(INPUT, gpf1-4, UP, FAST_SR1);
- PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
- PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
- PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
-
- PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
- PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
- PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
- PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
-
- PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
- PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
- PIN(INPUT, gpf3-2, NONE, FAST_SR1);
- PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
-
- PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
- PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
- PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
- PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
- PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
- PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
- PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
- PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
-
- PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
- PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
- PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
- PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
- PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
- PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
- PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
- PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
- };
-
- te_irq: te_irq {
- samsung,pins = "gpf1-3";
- samsung,pin-function = <0xf>;
- };
-};
-
-&pinctrl_cpif {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_cpif>;
-
- initial_cpif: initial-state {
- PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
- PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
- };
-};
-
-&pinctrl_ese {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_ese>;
-
- initial_ese: initial-state {
- PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
- PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
- PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
- };
-};
-
-&pinctrl_fsys {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_fsys>;
-
- initial_fsys: initial-state {
- PIN(INPUT, gpr3-0, NONE, FAST_SR1);
- PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
- PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
- PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
- PIN(INPUT, gpr3-7, NONE, FAST_SR1);
- };
-};
-
-&pinctrl_imem {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_imem>;
-
- initial_imem: initial-state {
- PIN(INPUT, gpf0-0, UP, FAST_SR1);
- PIN(INPUT, gpf0-1, UP, FAST_SR1);
- PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
- PIN(INPUT, gpf0-3, UP, FAST_SR1);
- PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
- PIN(INPUT, gpf0-5, NONE, FAST_SR1);
- PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
- PIN(INPUT, gpf0-7, UP, FAST_SR1);
- };
-};
-
-&pinctrl_nfc {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_nfc>;
-
- initial_nfc: initial-state {
- PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
- };
-};
-
-&pinctrl_peric {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_peric>;
-
- initial_peric: initial-state {
- PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
- PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
- PIN(INPUT, gpv7-2, NONE, FAST_SR1);
- PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
- PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
- PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
-
- PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
-
- PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
- PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
- PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
-
- PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
-
- PIN(INPUT, gpc3-4, NONE, FAST_SR1);
- PIN(INPUT, gpc3-5, NONE, FAST_SR1);
- PIN(INPUT, gpc3-6, NONE, FAST_SR1);
- PIN(INPUT, gpc3-7, NONE, FAST_SR1);
-
- PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
- PIN(2, gpg0-1, DOWN, FAST_SR1);
-
- PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
-
- PIN(INPUT, gpd4-0, NONE, FAST_SR1);
- PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
- PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
- PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
- PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
-
- PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
-
- PIN(INPUT, gpd8-1, UP, FAST_SR1);
-
- PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
- PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
- PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
- PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
- PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
-
- PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
- PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
-
- PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
- PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
- PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
- PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
- };
-};
-
-&pinctrl_touch {
- pinctrl-names = "default";
- pinctrl-0 = <&initial_touch>;
-
- initial_touch: initial-state {
- PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
- };
-};
-
-&pwm {
- pinctrl-0 = <&pwm0_out>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&mic {
- status = "okay";
-
- i80-if-timings {
- };
-};
-
-&pmu_system_controller {
- assigned-clocks = <&pmu_system_controller 0>;
- assigned-clock-parents = <&xxti>;
-};
-
-&serial_1 {
- status = "okay";
-};
-
-&spi_1 {
- cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- wm5110: wm5110-codec at 0 {
- compatible = "wlf,wm5110";
- reg = <0x0>;
- spi-max-frequency = <20000000>;
- interrupt-parent = <&gpa0>;
- interrupts = <4 IRQ_TYPE_NONE>;
- clocks = <&pmu_system_controller 0>,
- <&s2mps13_osc S2MPS11_CLK_BT>;
- clock-names = "mclk1", "mclk2";
-
- gpio-controller;
- #gpio-cells = <2>;
-
- wlf,micd-detect-debounce = <300>;
- wlf,micd-bias-start-time = <0x1>;
- wlf,micd-rate = <0x7>;
- wlf,micd-dbtime = <0x1>;
- wlf,micd-force-micbias;
- wlf,micd-configs = <0x0 1 0>;
- wlf,hpdet-channel = <1>;
- wlf,gpsw = <0x1>;
- wlf,inmode = <2 0 2 0>;
-
- wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
- wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
-
- /* core supplies */
- AVDD-supply = <&ldo18_reg>;
- DBVDD1-supply = <&ldo18_reg>;
- CPVDD-supply = <&ldo18_reg>;
- DBVDD2-supply = <&ldo18_reg>;
- DBVDD3-supply = <&ldo18_reg>;
-
- controller-data {
- samsung,spi-feedback-delay = <0>;
- };
- };
-};
-
-&timer {
- clock-frequency = <24000000>;
-};
-
-&tmu_atlas0 {
- vtmu-supply = <&ldo3_reg>;
- status = "okay";
-};
-
-&tmu_apollo {
- vtmu-supply = <&ldo3_reg>;
- status = "okay";
-};
-
-&tmu_g3d {
- vtmu-supply = <&ldo3_reg>;
- status = "okay";
-};
-
-&usbdrd30 {
- vdd33-supply = <&ldo10_reg>;
- vdd10-supply = <&ldo6_reg>;
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
-};
-
-&usbdrd30_phy {
- vbus-supply = <&safeout1_reg>;
- status = "okay";
-};
-
-&xxti {
- clock-frequency = <24000000>;
-};
+/*
+ * SAMSUNG Exynos5433 TM2 board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *
+ * Device tree source file for Samsung's TM2 board which is based on
+ * Samsung Exynos5433 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos5433-tm2-common.dtsi"
+
+/ {
+ model = "Samsung TM2 board";
+ compatible = "samsung,tm2", "samsung,exynos5433";
+};
+
+&ldo31_reg {
+ regulator-name = "TSP_VDD_1.85V_AP";
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+};
+
+&ldo38_reg {
+ regulator-name = "VCC_3.0V_MOTOR_AP";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 854c583092d5..2fbf3a860316 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -11,7 +11,7 @@
* published by the Free Software Foundation.
*/
-#include "exynos5433-tm2.dts"
+#include "exynos5433-tm2-common.dtsi"
/ {
model = "Samsung TM2E board";
--
2.11.0
^ permalink raw reply related
* [PATCH v5 3/5] input: Add support for the tm2 touchkey device driver
From: Andi Shyti @ 2017-01-06 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134350.32428-1-andi.shyti@samsung.com>
From: Jaechul Lee <jcsing.lee@samsung.com>
This patch adds the binding description of the tm2 touchkey
device driver.
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
---
.../bindings/input/samsung,tm2-touchkey.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
diff --git a/Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt b/Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
new file mode 100644
index 000000000000..4de1af0f0a37
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/samsung,tm2-touchkey.txt
@@ -0,0 +1,27 @@
+Samsung tm2-touchkey
+
+Required properties:
+- compatible: must be "samsung,tm2-touchkey"
+- reg: I2C address of the chip.
+- interrupt-parent: a phandle for the interrupt controller (see interrupt
+ binding[0]).
+- interrupts: interrupt to which the chip is connected (see interrupt
+ binding[0]).
+- vcc-supply : internal regulator output. 1.8V
+- vdd-supply : power supply for IC 3.3V
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+Example:
+ &i2c0 {
+ /* ... */
+
+ touchkey at 20 {
+ compatible = "samsung,tm2-touchkey";
+ reg = <0x20>;
+ interrupt-parent = <&gpa3>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply=<&ldo32_reg>;
+ vdd-supply=<&ldo33_reg>;
+ };
+ };
--
2.11.0
^ permalink raw reply related
* [PATCH v5 4/5] input: tm2-touchkey: Add touchkey driver support for TM2
From: Andi Shyti @ 2017-01-06 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134350.32428-1-andi.shyti@samsung.com>
From: Jaechul Lee <jcsing.lee@samsung.com>
This patch adds support for the TM2 touch key and led
functionality.
The driver interfaces with userspace through an input device and
reports KEY_PHONE and KEY_BACK event types. LED brightness can be
controlled by "/sys/class/leds/tm2-touchkey/brightness".
Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
---
drivers/input/keyboard/Kconfig | 11 ++
drivers/input/keyboard/Makefile | 1 +
drivers/input/keyboard/tm2-touchkey.c | 280 ++++++++++++++++++++++++++++++++++
3 files changed, 292 insertions(+)
create mode 100644 drivers/input/keyboard/tm2-touchkey.c
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index cbd75cf44739..e6e98585b4b0 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -666,6 +666,17 @@ config KEYBOARD_TC3589X
To compile this driver as a module, choose M here: the
module will be called tc3589x-keypad.
+config KEYBOARD_TM2_TOUCHKEY
+ tristate "tm2-touchkey support"
+ depends on I2C
+ depends on LEDS_CLASS
+ help
+ Say Y here to enable device driver for tm2-touchkey with
+ LED control for the Exynos5433 TM2 board.
+
+ To compile this driver as a module, choose M here.
+ module will be called tm2-touchkey.
+
config KEYBOARD_TWL4030
tristate "TI TWL4030/TWL5030/TPS659x0 keypad support"
depends on TWL4030_CORE
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index d9f4cfcf3410..7d9acff819a7 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_KEYBOARD_SUN4I_LRADC) += sun4i-lradc-keys.o
obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o
obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
+obj-$(CONFIG_KEYBOARD_TM2_TOUCHKEY) += tm2-touchkey.o
obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o
obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o
obj-$(CONFIG_KEYBOARD_W90P910) += w90p910_keypad.o
diff --git a/drivers/input/keyboard/tm2-touchkey.c b/drivers/input/keyboard/tm2-touchkey.c
new file mode 100644
index 000000000000..92eacb62f8e7
--- /dev/null
+++ b/drivers/input/keyboard/tm2-touchkey.c
@@ -0,0 +1,280 @@
+/*
+ * TM2 touchkey device driver
+ *
+ * Copyright 2005 Phil Blundell
+ * Copyright 2016 Samsung Electronics Co., Ltd.
+ *
+ * Author: Beomho Seo <beomho.seo@samsung.com>
+ * Author: Jaechul Lee <jcsing.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/leds.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pm.h>
+#include <linux/regulator/consumer.h>
+
+#define TM2_TOUCHKEY_DEV_NAME "tm2-touchkey"
+#define TM2_TOUCHKEY_KEYCODE_REG 0x03
+#define TM2_TOUCHKEY_BASE_REG 0x00
+#define TM2_TOUCHKEY_CMD_LED_ON 0x10
+#define TM2_TOUCHKEY_CMD_LED_OFF 0x20
+#define TM2_TOUCHKEY_BIT_PRESS_EV BIT(3)
+#define TM2_TOUCHKEY_BIT_KEYCODE GENMASK(2, 0)
+#define TM2_TOUCHKEY_LED_VOLTAGE_MIN 2500000
+#define TM2_TOUCHKEY_LED_VOLTAGE_MAX 3300000
+
+enum {
+ TM2_TOUCHKEY_KEY_MENU = 0x1,
+ TM2_TOUCHKEY_KEY_BACK,
+};
+
+struct tm2_touchkey_data {
+ struct i2c_client *client;
+ struct input_dev *input_dev;
+ struct led_classdev led_dev;
+ struct regulator_bulk_data regulators[2];
+
+ u8 keycode_type;
+ u8 pressed;
+};
+
+static void tm2_touchkey_led_brightness_set(struct led_classdev *led_dev,
+ enum led_brightness brightness)
+{
+ struct tm2_touchkey_data *touchkey =
+ container_of(led_dev, struct tm2_touchkey_data, led_dev);
+ u32 volt;
+ u8 data;
+
+ if (brightness == LED_OFF) {
+ volt = TM2_TOUCHKEY_LED_VOLTAGE_MIN;
+ data = TM2_TOUCHKEY_CMD_LED_OFF;
+ } else {
+ volt = TM2_TOUCHKEY_LED_VOLTAGE_MAX;
+ data = TM2_TOUCHKEY_CMD_LED_ON;
+ }
+
+ regulator_set_voltage(touchkey->regulators[1].consumer, volt, volt);
+ i2c_smbus_write_byte_data(touchkey->client,
+ TM2_TOUCHKEY_BASE_REG, data);
+}
+
+static int tm2_touchkey_power_enable(struct tm2_touchkey_data *touchkey)
+{
+ int ret = 0;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(touchkey->regulators),
+ touchkey->regulators);
+ if (ret)
+ return ret;
+
+ /* waiting for device initialization, at least 150ms */
+ msleep(150);
+
+ return 0;
+}
+
+static void tm2_touchkey_power_disable(void *data)
+{
+ struct tm2_touchkey_data *touchkey = data;
+
+ regulator_bulk_disable(ARRAY_SIZE(touchkey->regulators),
+ touchkey->regulators);
+}
+
+static irqreturn_t tm2_touchkey_irq_handler(int irq, void *devid)
+{
+ struct tm2_touchkey_data *touchkey = devid;
+ u32 data;
+
+ data = i2c_smbus_read_byte_data(touchkey->client,
+ TM2_TOUCHKEY_KEYCODE_REG);
+
+ if (data < 0) {
+ dev_err(&touchkey->client->dev, "Failed to read i2c data\n");
+ return IRQ_HANDLED;
+ }
+
+ touchkey->keycode_type = data & TM2_TOUCHKEY_BIT_KEYCODE;
+ touchkey->pressed = !(data & TM2_TOUCHKEY_BIT_PRESS_EV);
+
+ if (touchkey->keycode_type != TM2_TOUCHKEY_KEY_MENU &&
+ touchkey->keycode_type != TM2_TOUCHKEY_KEY_BACK) {
+ dev_warn(&touchkey->client->dev, "Skip unhandled keycode(%d)\n",
+ touchkey->keycode_type);
+ return IRQ_HANDLED;
+ }
+
+ if (!touchkey->pressed) {
+ input_report_key(touchkey->input_dev, KEY_PHONE, 0);
+ input_report_key(touchkey->input_dev, KEY_BACK, 0);
+ } else {
+ if (touchkey->keycode_type == TM2_TOUCHKEY_KEY_MENU)
+ input_report_key(touchkey->input_dev,
+ KEY_PHONE, 1);
+ else
+ input_report_key(touchkey->input_dev,
+ KEY_BACK, 1);
+ }
+ input_sync(touchkey->input_dev);
+
+ return IRQ_HANDLED;
+}
+
+static int tm2_touchkey_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct tm2_touchkey_data *touchkey;
+ int ret;
+
+ ret = i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE |
+ I2C_FUNC_SMBUS_BYTE_DATA);
+ if (!ret) {
+ dev_err(&client->dev, "No I2C functionality found\n");
+ return -ENODEV;
+ }
+
+ touchkey = devm_kzalloc(&client->dev, sizeof(*touchkey), GFP_KERNEL);
+ if (!touchkey)
+ return -ENOMEM;
+
+ touchkey->client = client;
+ i2c_set_clientdata(client, touchkey);
+
+ /* regulators */
+ touchkey->regulators[0].supply = "vcc";
+ touchkey->regulators[1].supply = "vdd";
+ ret = devm_regulator_bulk_get(&client->dev,
+ ARRAY_SIZE(touchkey->regulators),
+ touchkey->regulators);
+ if (ret) {
+ dev_err(&client->dev, "Failed to get regulators\n");
+ return ret;
+ }
+
+ /* power */
+ ret = tm2_touchkey_power_enable(touchkey);
+ if (ret) {
+ dev_err(&client->dev, "Failed to enable power\n");
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(&client->dev,
+ tm2_touchkey_power_disable, touchkey);
+ if (ret)
+ return ret;
+
+ /* input device */
+ touchkey->input_dev = devm_input_allocate_device(&client->dev);
+ if (!touchkey->input_dev) {
+ dev_err(&client->dev, "Failed to alloc input device\n");
+ return -ENOMEM;
+ }
+ touchkey->input_dev->name = TM2_TOUCHKEY_DEV_NAME;
+ touchkey->input_dev->id.bustype = BUS_I2C;
+
+ set_bit(EV_KEY, touchkey->input_dev->evbit);
+ input_set_capability(touchkey->input_dev, EV_KEY, KEY_PHONE);
+ input_set_capability(touchkey->input_dev, EV_KEY, KEY_BACK);
+
+ input_set_drvdata(touchkey->input_dev, touchkey);
+
+ ret = input_register_device(touchkey->input_dev);
+ if (ret) {
+ dev_err(&client->dev, "Failed to register input device\n");
+ return ret;
+ }
+
+ /* irq */
+ ret = devm_request_threaded_irq(&client->dev,
+ client->irq, NULL,
+ tm2_touchkey_irq_handler,
+ IRQF_ONESHOT, TM2_TOUCHKEY_DEV_NAME,
+ touchkey);
+ if (ret) {
+ dev_err(&client->dev, "Failed to request threaded irq\n");
+ return ret;
+ }
+
+ /* led device */
+ touchkey->led_dev.name = TM2_TOUCHKEY_DEV_NAME;
+ touchkey->led_dev.brightness = LED_FULL;
+ touchkey->led_dev.max_brightness = LED_FULL;
+ touchkey->led_dev.brightness_set = tm2_touchkey_led_brightness_set;
+
+ ret = devm_led_classdev_register(&client->dev, &touchkey->led_dev);
+ if (ret < 0) {
+ dev_err(&client->dev, "Failed to register touchkey led\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __maybe_unused tm2_touchkey_suspend(struct device *dev)
+{
+ struct tm2_touchkey_data *touchkey = dev_get_drvdata(dev);
+
+ disable_irq(touchkey->client->irq);
+ tm2_touchkey_power_disable(touchkey);
+
+ return 0;
+}
+
+static int __maybe_unused tm2_touchkey_resume(struct device *dev)
+{
+ struct tm2_touchkey_data *touchkey = dev_get_drvdata(dev);
+ int ret;
+
+ enable_irq(touchkey->client->irq);
+ ret = tm2_touchkey_power_enable(touchkey);
+ if (ret)
+ dev_err(dev, "Failed to enable power\n");
+
+ return ret;
+}
+
+static SIMPLE_DEV_PM_OPS(tm2_touchkey_pm_ops, tm2_touchkey_suspend,
+ tm2_touchkey_resume);
+
+static const struct i2c_device_id tm2_touchkey_id_table[] = {
+ {TM2_TOUCHKEY_DEV_NAME, 0},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, tm2_touchkey_id_table);
+
+static const struct of_device_id tm2_touchkey_of_match[] = {
+ {.compatible = "samsung,tm2-touchkey",},
+ {},
+};
+MODULE_DEVICE_TABLE(of, tm2_touchkey_of_match);
+
+static struct i2c_driver tm2_touchkey_driver = {
+ .driver = {
+ .name = TM2_TOUCHKEY_DEV_NAME,
+ .pm = &tm2_touchkey_pm_ops,
+ .of_match_table = of_match_ptr(tm2_touchkey_of_match),
+ },
+ .probe = tm2_touchkey_probe,
+ .id_table = tm2_touchkey_id_table,
+};
+
+module_i2c_driver(tm2_touchkey_driver);
+
+MODULE_AUTHOR("Beomho Seo <beomho.seo@samsung.com>");
+MODULE_AUTHOR("Jaechul Lee <jcsing.lee@samsung.com>");
+MODULE_DESCRIPTION("Samsung touchkey driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related
* [PATCH v5 5/5] arm64: dts: exynos: Add tm2 touchkey node
From: Andi Shyti @ 2017-01-06 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134350.32428-1-andi.shyti@samsung.com>
From: Jaechul Lee <jcsing.lee@samsung.com>
Add DT node support for TM2 touchkey device.
Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 2449266b268f..92fcc4ec8319 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -18,6 +18,19 @@
compatible = "samsung,tm2", "samsung,exynos5433";
};
+&hsi2c_9 {
+ status = "okay";
+
+ touchkey at 20 {
+ compatible = "samsung,tm2-touchkey";
+ reg = <0x20>;
+ interrupt-parent = <&gpa3>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply = <&ldo32_reg>;
+ vdd-supply = <&ldo33_reg>;
+ };
+};
+
&ldo31_reg {
regulator-name = "TSP_VDD_1.85V_AP";
regulator-min-microvolt = <1850000>;
--
2.11.0
^ permalink raw reply related
* [PATCH 1/2] arm64: dma_mapping: allow PCI host driver to limit DMA mask
From: Nikita Yushchenko @ 2017-01-06 13:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2723285.JORgusvJv4@wuerfel>
>>> Just a guess, but if the inbound translation windows in the host
>>> bridge are wider than 32-bit, the reason for setting up a single
>>> 32-bit window is probably because that is what the parent bus supports.
I've re-checked rcar-pcie hardware documentation.
It indeed mentions that AXI bus it sits on is 32-bit.
>> Well anyway applying patch similar to your's will fix pcie-rcar + nvme
>> case - thus I don't object :) But it can break other cases ...
>>
>> But why do you hook at set_dma_mask() and overwrite mask inside, instead
>> of hooking at dma_supported() and rejecting unsupported mask?
>>
>> I think later is better, because it lets drivers to handle unsupported
>> high-dma case, like documented in DMA-API_HOWTO.
>
> I think the behavior I put in there is required for swiotlb to make
> sense, otherwise you would rely on the driver to handle dma_set_mask()
> failure gracefully with its own bounce buffers (as network and
> scsi drivers do but others don't).
>
> Having swiotlb or iommu enabled should result in dma_set_mask() always
> succeeding unless the mask is too small to cover the swiotlb
> bounce buffer area or the iommu virtual address space. This behavior
> is particularly important in case the bus address space is narrower
> than 32-bit, as we have to guarantee that the fallback to 32-bit
> DMA always succeeds. There are also a lot of drivers that try to
> set a 64-bit mask but don't implement bounce buffers for streaming
> mappings if that fails, and swiotlb is what we use to make those
> drivers work.
>
> And yes, the API is a horrible mess.
With my patch applied and thus 32bit dma_mask set for NVMe device, I do
see high addresses passed to dma_map_*() routines and handled by
swiotlb. Thus your statement that behavior "succeed 64bit dma_set_mask()
operation but silently replace mask behind the scene" is required for
swiotlb to be used, does not match reality.
It can be interpreted as a breakage elsewhere, but it's hard to point
particular "root cause". The entire infrastructure to allocate and use
DMA memory is messy.
Still current code does not work, thus fix is needed.
Perhaps need to introduce some generic API to "allocate memory best
suited for DMA to particular device", and fix allocation points (in
drivers, filesystems, etc) to use it. Such an API could try to allocate
area that can be DMAed by hardware, and fallback to other memory that
can be used via swiotlb or other bounce buffer implementation.
But for now, have to stay with dma masks. Will follow-up with a patch
based on your but with coherent mask handling added.
Nikita
^ permalink raw reply
* [PATCH v5 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-06 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134350.32428-3-andi.shyti@samsung.com>
On Fri, Jan 06, 2017 at 10:43:47PM +0900, Andi Shyti wrote:
> Currently tm2e dts includes tm2 but there are some differences
> between the two boards and tm2 has some properties that tm2e
> doesn't have.
>
> That's why it's important to keep the two dts files independent
> and put all the commonalities in a tm2-common.dtsi file.
>
> At the current status the only two differences between the two
> dts files (besides the board name) are ldo31 and ldo38.
>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> ...ynos5433-tm2.dts => exynos5433-tm2-common.dtsi} | 21 +-
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1150 +-------------------
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
> 3 files changed, 42 insertions(+), 1131 deletions(-)
> copy arch/arm64/boot/dts/exynos/{exynos5433-tm2.dts => exynos5433-tm2-common.dtsi} (98%)
> rewrite arch/arm64/boot/dts/exynos/exynos5433-tm2.dts (98%)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> similarity index 98%
> copy from arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> copy to arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index 640e4b9910ae..cc6701b3bce4 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -3,8 +3,8 @@
> *
> * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> *
> - * Device tree source file for Samsung's TM2 board which is based on
> - * Samsung Exynos5433 SoC.
> + * Common device tree source file for Samsung's TM2 and TM2E boards
> + * which are based on Samsung Exynos5433 SoC.
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License version 2 as
> @@ -19,9 +19,6 @@
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> - model = "Samsung TM2 board";
> - compatible = "samsung,tm2", "samsung,exynos5433";
> -
> aliases {
> gsc0 = &gsc_0;
> gsc1 = &gsc_1;
> @@ -552,9 +549,10 @@
> };
>
> ldo31_reg: LDO31 {
> - regulator-name = "TSP_VDD_1.85V_AP";
> - regulator-min-microvolt = <1850000>;
> - regulator-max-microvolt = <1850000>;
> + /*
> + * LDO31 differs from target to target,
> + * its definition is in the .dts
> + */
> };
>
> ldo32_reg: LDO32 {
> @@ -595,9 +593,10 @@
> };
>
> ldo38_reg: LDO38 {
> - regulator-name = "VCC_3.0V_MOTOR_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> + /*
> + * LDO38 differs from target to target,
> + * its definition is in the .dts
> + */
> };
>
> ldo39_reg: LDO39 {
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> dissimilarity index 98%
> index 640e4b9910ae..2449266b268f 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -1,1119 +1,31 @@
> -/*
> - * SAMSUNG Exynos5433 TM2 board device tree source
> - *
> - * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> - *
> - * Device tree source file for Samsung's TM2 board which is based on
> - * Samsung Exynos5433 SoC.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -/dts-v1/;
> -#include "exynos5433.dtsi"
> -#include <dt-bindings/clock/samsung,s2mps11.h>
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/input/input.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> -
> -/ {
> - model = "Samsung TM2 board";
> - compatible = "samsung,tm2", "samsung,exynos5433";
> -
> - aliases {
> - gsc0 = &gsc_0;
> - gsc1 = &gsc_1;
> - gsc2 = &gsc_2;
> - pinctrl0 = &pinctrl_alive;
> - pinctrl1 = &pinctrl_aud;
> - pinctrl2 = &pinctrl_cpif;
> - pinctrl3 = &pinctrl_ese;
> - pinctrl4 = &pinctrl_finger;
> - pinctrl5 = &pinctrl_fsys;
> - pinctrl6 = &pinctrl_imem;
> - pinctrl7 = &pinctrl_nfc;
> - pinctrl8 = &pinctrl_peric;
> - pinctrl9 = &pinctrl_touch;
> - serial0 = &serial_0;
> - serial1 = &serial_1;
> - serial2 = &serial_2;
> - serial3 = &serial_3;
> - spi0 = &spi_0;
> - spi1 = &spi_1;
> - spi2 = &spi_2;
> - spi3 = &spi_3;
> - spi4 = &spi_4;
> - mshc0 = &mshc_0;
> - mshc2 = &mshc_2;
> - };
> -
> - chosen {
> - stdout-path = &serial_1;
> - };
> -
> - memory at 20000000 {
> - device_type = "memory";
> - reg = <0x0 0x20000000 0x0 0xc0000000>;
> - };
> -
> - gpio-keys {
> - compatible = "gpio-keys";
> -
> - power-key {
> - gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_POWER>;
> - label = "power key";
> - debounce-interval = <10>;
> - };
> -
> - volume-up-key {
> - gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEUP>;
> - label = "volume-up key";
> - debounce-interval = <10>;
> - };
> -
> - volume-down-key {
> - gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEDOWN>;
> - label = "volume-down key";
> - debounce-interval = <10>;
> - };
> -
> - homepage-key {
> - gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_MENU>;
> - label = "homepage key";
> - debounce-interval = <10>;
> - };
> - };
> -
> - i2c_max98504: i2c-gpio-0 {
> - compatible = "i2c-gpio";
> - gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
> - &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
> - i2c-gpio,delay-us = <2>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "okay";
> -
> - max98504: max98504 at 31 {
> - compatible = "maxim,max98504";
> - reg = <0x31>;
> - maxim,rx-path = <1>;
> - maxim,tx-path = <1>;
> - maxim,tx-channel-mask = <3>;
> - maxim,tx-channel-source = <2>;
> - };
> - };
> -
> - sound {
> - compatible = "samsung,tm2-audio";
> - audio-codec = <&wm5110>;
> - i2s-controller = <&i2s0>;
> - audio-amplifier = <&max98504>;
> - mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
> - model = "wm5110";
> - samsung,audio-routing =
> - /* Headphone */
> - "HP", "HPOUT1L",
> - "HP", "HPOUT1R",
> -
> - /* Speaker */
> - "SPK", "SPKOUT",
> - "SPKOUT", "HPOUT2L",
> - "SPKOUT", "HPOUT2R",
> -
> - /* Receiver */
> - "RCV", "HPOUT3L",
> - "RCV", "HPOUT3R";
> - status = "okay";
> - };
> -};
> -
> -&adc {
> - vdd-supply = <&ldo3_reg>;
> - status = "okay";
> -
> - thermistor-ap {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 0>;
> - };
> -
> - thermistor-battery {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 1>;
> - #thermal-sensor-cells = <0>;
> - };
> -
> - thermistor-charger {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 2>;
> - };
> -};
> -
> -&bus_g2d_400 {
> - devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
> - vdd-supply = <&buck4_reg>;
> - exynos,saturation-ratio = <10>;
> - status = "okay";
> -};
> -
> -&bus_g2d_266 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_gscl {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_hevc {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_jpeg {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_mfc {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_mscl {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc0 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc1 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc2 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&cmu_aud {
> - assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
> - assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> -};
> -
> -&cmu_fsys {
> - assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> - <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
> - <&cmu_top CLK_DIV_SCLK_USBDRD30>,
> - <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> - assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> - <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> - <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> - assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
> - <66700000>, <66700000>;
> -};
> -
> -&cmu_gscl {
> - assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
> - <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
> - <&cmu_top CLK_ACLK_GSCL_333>;
> -};
> -
> -&cmu_mfc {
> - assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
> -};
> -
> -&cmu_mscl {
> - assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
> - <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
> - <&cmu_top CLK_SCLK_JPEG_MSCL>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> -};
> -
> -&cpu0 {
> - cpu-supply = <&buck3_reg>;
> -};
> -
> -&cpu4 {
> - cpu-supply = <&buck2_reg>;
> -};
> -
> -&decon {
> - status = "okay";
> -
> - i80-if-timings {
> - };
> -};
> -
> -&dsi {
> - status = "okay";
> - vddcore-supply = <&ldo6_reg>;
> - vddio-supply = <&ldo7_reg>;
> - samsung,pll-clock-frequency = <24000000>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&te_irq>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port at 1 {
> - reg = <1>;
> -
> - dsi_out: endpoint {
> - samsung,burst-clock-frequency = <512000000>;
> - samsung,esc-clock-frequency = <16000000>;
> - };
> - };
> - };
> -};
> -
> -&hsi2c_0 {
> - status = "okay";
> - clock-frequency = <2500000>;
> -
> - s2mps13-pmic at 66 {
> - compatible = "samsung,s2mps13-pmic";
> - interrupt-parent = <&gpa0>;
> - interrupts = <7 IRQ_TYPE_NONE>;
> - reg = <0x66>;
> - samsung,s2mps11-wrstbi-ground;
> -
> - s2mps13_osc: clocks {
> - compatible = "samsung,s2mps13-clk";
> - #clock-cells = <1>;
> - clock-output-names = "s2mps13_ap", "s2mps13_cp",
> - "s2mps13_bt";
> - };
> -
> - regulators {
> - ldo1_reg: LDO1 {
> - regulator-name = "VDD_ALIVE_0.9V_AP";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <900000>;
> - regulator-always-on;
> - };
> -
> - ldo2_reg: LDO2 {
> - regulator-name = "VDDQ_MMC2_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo3_reg: LDO3 {
> - regulator-name = "VDD1_E_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo4_reg: LDO4 {
> - regulator-name = "VDD10_MIF_PLL_1.0V_AP";
> - regulator-min-microvolt = <1300000>;
> - regulator-max-microvolt = <1300000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo5_reg: LDO5 {
> - regulator-name = "VDD10_DPLL_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo6_reg: LDO6 {
> - regulator-name = "VDD10_MIPI2L_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo7_reg: LDO7 {
> - regulator-name = "VDD18_MIPI2L_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo8_reg: LDO8 {
> - regulator-name = "VDD18_LLI_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo9_reg: LDO9 {
> - regulator-name = "VDD18_ABB_ETC_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo10_reg: LDO10 {
> - regulator-name = "VDD33_USB30_3.0V_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo11_reg: LDO11 {
> - regulator-name = "VDD_INT_M_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo12_reg: LDO12 {
> - regulator-name = "VDD_KFC_M_1.1V_AP";
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1350000>;
> - regulator-always-on;
> - };
> -
> - ldo13_reg: LDO13 {
> - regulator-name = "VDD_G3D_M_0.95V_AP";
> - regulator-min-microvolt = <950000>;
> - regulator-max-microvolt = <950000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo14_reg: LDO14 {
> - regulator-name = "VDDQ_M1_LDO_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo15_reg: LDO15 {
> - regulator-name = "VDDQ_M2_LDO_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo16_reg: LDO16 {
> - regulator-name = "VDDQ_EFUSE";
> - regulator-min-microvolt = <1400000>;
> - regulator-max-microvolt = <3400000>;
> - regulator-always-on;
> - };
> -
> - ldo17_reg: LDO17 {
> - regulator-name = "V_TFLASH_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo18_reg: LDO18 {
> - regulator-name = "V_CODEC_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo19_reg: LDO19 {
> - regulator-name = "VDDA_1.8V_COMP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo20_reg: LDO20 {
> - regulator-name = "VCC_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - };
> -
> - ldo21_reg: LDO21 {
> - regulator-name = "VT_CAM_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo22_reg: LDO22 {
> - regulator-name = "CAM_IO_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo23_reg: LDO23 {
> - regulator-name = "CAM_SEN_CORE_1.05V_AP";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - };
> -
> - ldo24_reg: LDO24 {
> - regulator-name = "VT_CAM_1.2V";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo25_reg: LDO25 {
> - regulator-name = "UNUSED_LDO25";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo26_reg: LDO26 {
> - regulator-name = "CAM_AF_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo27_reg: LDO27 {
> - regulator-name = "VCC_3.0V_LCD_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo28_reg: LDO28 {
> - regulator-name = "VCC_1.8V_LCD_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo29_reg: LDO29 {
> - regulator-name = "VT_CAM_2.8V";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo30_reg: LDO30 {
> - regulator-name = "TSP_AVDD_3.3V_AP";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - ldo31_reg: LDO31 {
> - regulator-name = "TSP_VDD_1.85V_AP";
> - regulator-min-microvolt = <1850000>;
> - regulator-max-microvolt = <1850000>;
> - };
> -
> - ldo32_reg: LDO32 {
> - regulator-name = "VTOUCH_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo33_reg: LDO33 {
> - regulator-name = "VTOUCH_LED_3.3V";
> - regulator-min-microvolt = <2500000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-ramp-delay = <12500>;
> - };
> -
> - ldo34_reg: LDO34 {
> - regulator-name = "VCC_1.8V_MHL_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <2100000>;
> - };
> -
> - ldo35_reg: LDO35 {
> - regulator-name = "OIS_VM_2.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo36_reg: LDO36 {
> - regulator-name = "VSIL_1.0V";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - };
> -
> - ldo37_reg: LDO37 {
> - regulator-name = "VF_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo38_reg: LDO38 {
> - regulator-name = "VCC_3.0V_MOTOR_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo39_reg: LDO39 {
> - regulator-name = "V_HRM_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo40_reg: LDO40 {
> - regulator-name = "V_HRM_3.3V";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - buck1_reg: BUCK1 {
> - regulator-name = "VDD_MIF_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck2_reg: BUCK2 {
> - regulator-name = "VDD_EGL_1.0V_AP";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <1300000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck3_reg: BUCK3 {
> - regulator-name = "VDD_KFC_1.0V_AP";
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck4_reg: BUCK4 {
> - regulator-name = "VDD_INT_0.95V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck5_reg: BUCK5 {
> - regulator-name = "VDD_DISP_CAM0_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck6_reg: BUCK6 {
> - regulator-name = "VDD_G3D_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck7_reg: BUCK7 {
> - regulator-name = "VDD_MEM1_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - buck8_reg: BUCK8 {
> - regulator-name = "VDD_LLDO_1.35V_AP";
> - regulator-min-microvolt = <1350000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - buck9_reg: BUCK9 {
> - regulator-name = "VDD_MLDO_2.0V_AP";
> - regulator-min-microvolt = <1350000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - buck10_reg: BUCK10 {
> - regulator-name = "vdd_mem2";
> - regulator-min-microvolt = <550000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - };
> - };
> - };
> -};
> -
> -&hsi2c_8 {
> - status = "okay";
> -
> - max77843 at 66 {
> - compatible = "maxim,max77843";
> - interrupt-parent = <&gpa1>;
> - interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> - reg = <0x66>;
> -
> - muic: max77843-muic {
> - compatible = "maxim,max77843-muic";
> - };
> -
> - regulators {
> - compatible = "maxim,max77843-regulator";
> - safeout1_reg: SAFEOUT1 {
> - regulator-name = "SAFEOUT1";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <4950000>;
> - };
> -
> - safeout2_reg: SAFEOUT2 {
> - regulator-name = "SAFEOUT2";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <4950000>;
> - };
> -
> - charger_reg: CHARGER {
> - regulator-name = "CHARGER";
> - regulator-min-microamp = <100000>;
> - regulator-max-microamp = <3150000>;
> - };
> - };
> -
> - haptic: max77843-haptic {
> - compatible = "maxim,max77843-haptic";
> - haptic-supply = <&ldo38_reg>;
> - pwms = <&pwm 0 33670 0>;
> - pwm-names = "haptic";
> - };
> - };
> -};
> -
> -&i2s0 {
> - status = "okay";
> -};
> -
> -&mshc_0 {
> - status = "okay";
> - num-slots = <1>;
> - mmc-hs200-1_8v;
> - mmc-hs400-1_8v;
> - cap-mmc-highspeed;
> - non-removable;
> - card-detect-delay = <200>;
> - samsung,dw-mshc-ciu-div = <3>;
> - samsung,dw-mshc-sdr-timing = <0 4>;
> - samsung,dw-mshc-ddr-timing = <0 2>;
> - samsung,dw-mshc-hs400-timing = <0 3>;
> - samsung,read-strobe-delay = <90>;
> - fifo-depth = <0x80>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
> - &sd0_bus8 &sd0_rdqs>;
> - bus-width = <8>;
> - assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
> - assigned-clock-rates = <800000000>;
> -};
> -
> -&mshc_2 {
> - status = "okay";
> - num-slots = <1>;
> - cap-sd-highspeed;
> - disable-wp;
> - cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
> - cd-inverted;
> - card-detect-delay = <200>;
> - samsung,dw-mshc-ciu-div = <3>;
> - samsung,dw-mshc-sdr-timing = <0 4>;
> - samsung,dw-mshc-ddr-timing = <0 2>;
> - fifo-depth = <0x80>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
> - bus-width = <4>;
> -};
> -
> -&ppmu_d0_general {
> - status = "okay";
> - events {
> - ppmu_event0_d0_general: ppmu-event0-d0-general {
> - event-name = "ppmu-event0-d0-general";
> - };
> - };
> -};
> -
> -&ppmu_d1_general {
> - status = "okay";
> - events {
> - ppmu_event0_d1_general: ppmu-event0-d1-general {
> - event-name = "ppmu-event0-d1-general";
> - };
> - };
> -};
> -
> -&pinctrl_alive {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_alive>;
> -
> - initial_alive: initial-state {
> - PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-3, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-6, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa1-0, UP, FAST_SR1);
> - PIN(INPUT, gpa1-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpa1-5, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-6, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa2-0, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf1-0, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-1, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf1-4, UP, FAST_SR1);
> - PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf3-2, NONE, FAST_SR1);
> - PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
> - PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
> - PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
> - };
> -
> - te_irq: te_irq {
> - samsung,pins = "gpf1-3";
> - samsung,pin-function = <0xf>;
> - };
> -};
> -
> -&pinctrl_cpif {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_cpif>;
> -
> - initial_cpif: initial-state {
> - PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_ese {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_ese>;
> -
> - initial_ese: initial-state {
> - PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_fsys {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_fsys>;
> -
> - initial_fsys: initial-state {
> - PIN(INPUT, gpr3-0, NONE, FAST_SR1);
> - PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-7, NONE, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_imem {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_imem>;
> -
> - initial_imem: initial-state {
> - PIN(INPUT, gpf0-0, UP, FAST_SR1);
> - PIN(INPUT, gpf0-1, UP, FAST_SR1);
> - PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-3, UP, FAST_SR1);
> - PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-5, NONE, FAST_SR1);
> - PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-7, UP, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_nfc {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_nfc>;
> -
> - initial_nfc: initial-state {
> - PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_peric {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_peric>;
> -
> - initial_peric: initial-state {
> - PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-2, NONE, FAST_SR1);
> - PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc3-4, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-5, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-6, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-7, NONE, FAST_SR1);
> -
> - PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
> - PIN(2, gpg0-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd4-0, NONE, FAST_SR1);
> - PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd8-1, UP, FAST_SR1);
> -
> - PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_touch {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_touch>;
> -
> - initial_touch: initial-state {
> - PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pwm {
> - pinctrl-0 = <&pwm0_out>;
> - pinctrl-names = "default";
> - status = "okay";
> -};
> -
> -&mic {
> - status = "okay";
> -
> - i80-if-timings {
> - };
> -};
> -
> -&pmu_system_controller {
> - assigned-clocks = <&pmu_system_controller 0>;
> - assigned-clock-parents = <&xxti>;
> -};
> -
> -&serial_1 {
> - status = "okay";
> -};
> -
> -&spi_1 {
> - cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> - status = "okay";
> -
> - wm5110: wm5110-codec at 0 {
> - compatible = "wlf,wm5110";
> - reg = <0x0>;
> - spi-max-frequency = <20000000>;
> - interrupt-parent = <&gpa0>;
> - interrupts = <4 IRQ_TYPE_NONE>;
> - clocks = <&pmu_system_controller 0>,
> - <&s2mps13_osc S2MPS11_CLK_BT>;
> - clock-names = "mclk1", "mclk2";
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - wlf,micd-detect-debounce = <300>;
> - wlf,micd-bias-start-time = <0x1>;
> - wlf,micd-rate = <0x7>;
> - wlf,micd-dbtime = <0x1>;
> - wlf,micd-force-micbias;
> - wlf,micd-configs = <0x0 1 0>;
> - wlf,hpdet-channel = <1>;
> - wlf,gpsw = <0x1>;
> - wlf,inmode = <2 0 2 0>;
> -
> - wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
> - wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
> -
> - /* core supplies */
> - AVDD-supply = <&ldo18_reg>;
> - DBVDD1-supply = <&ldo18_reg>;
> - CPVDD-supply = <&ldo18_reg>;
> - DBVDD2-supply = <&ldo18_reg>;
> - DBVDD3-supply = <&ldo18_reg>;
> -
> - controller-data {
> - samsung,spi-feedback-delay = <0>;
> - };
> - };
> -};
> -
> -&timer {
> - clock-frequency = <24000000>;
> -};
> -
> -&tmu_atlas0 {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&tmu_apollo {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&tmu_g3d {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&usbdrd30 {
> - vdd33-supply = <&ldo10_reg>;
> - vdd10-supply = <&ldo6_reg>;
> - status = "okay";
> -};
> -
> -&usbdrd_dwc3_0 {
> - dr_mode = "otg";
> -};
> -
> -&usbdrd30_phy {
> - vbus-supply = <&safeout1_reg>;
> - status = "okay";
> -};
> -
> -&xxti {
> - clock-frequency = <24000000>;
> -};
> +/*
> + * SAMSUNG Exynos5433 TM2 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung's TM2 board which is based on
> + * Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "exynos5433-tm2-common.dtsi"
> +
> +/ {
> + model = "Samsung TM2 board";
> + compatible = "samsung,tm2", "samsung,exynos5433";
> +};
> +
> +&ldo31_reg {
> + regulator-name = "TSP_VDD_1.85V_AP";
> + regulator-min-microvolt = <1850000>;
> + regulator-max-microvolt = <1850000>;
> +};
> +
> +&ldo38_reg {
> + regulator-name = "VCC_3.0V_MOTOR_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> index 854c583092d5..2fbf3a860316 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -11,7 +11,7 @@
> * published by the Free Software Foundation.
> */
>
> -#include "exynos5433-tm2.dts"
> +#include "exynos5433-tm2-common.dtsi"
>
> / {
> model = "Samsung TM2E board";
Where are the regulators?
Beside that it is starting to look good. I didn't find anything else but
maybe Javier's eagle eye will catch something.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue
From: Jerome Brunet @ 2017-01-06 13:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106114226.GX14217@n2100.armlinux.org.uk>
On Fri, 2017-01-06 at 11:42 +0000, Russell King - ARM Linux wrote:
> On Fri, Jan 06, 2017 at 11:11:36AM +0100, Jerome Brunet wrote:
> >
> > The purpose of this patch is to provide a way to mark as broken a
> > particular eee mode. At first, it had nothing to do with "set_eee"
> > but,
> > as Florian rightly pointed out, users shouldn't be able to re-
> > enable a
> > broken mode.
>
> I think something else has been missed - I don't see much point to
> telling userspace that (eg) 1000baseT EEE is supported and then
> ignore attempts to advertise it.
>
> If it's broken, then arguably the hardware doesn't support the mode,
> so we should really be masking those bits from the EEE supported mask
> as well.
indeed.
>
> >
[...]
>
> >
> > >
> > > ?- maybe the problem here is that the PCS doesn't support support
> > > EEE in 1000baseT mode?
> >
> >
> > It does, and that's kind of the problem. EEE in ON for 100Tx and
> > 1000T
> > by default with this PHY. I have several platform with the same
> > MAC-PHY?
> > combination. Only the OdroidC2 shows this particular issue with
> > 1000T-
> > EEE
> >
> > As explained in other mails in this thread. The problem does not
> > come
> > from the MAC entering LPI. It actually comes from the link partner
> > entering LPI on the Rx path under significant Tx transfer. For some
> > reason, this completely mess up our PHY.
>
> For a 1000baseT link to enter low power, both ends have to enter LPI
> (see 802.3 78.1.3.3.1) - the Tx and Rx paths can't independently
> enter
> LPI.
>
> So, if you have a busy Tx link, the link itself can't be entering
> LPI.
> Your link partner may be sending a request to enter LPI due to its
> own
> Tx path being idle, which should then be forwarded to your MAC.
>
> It's pretty hard to see what could be messed up with that - I'd have
> expected the problems to occur when both ends were idle and the link
> had entered low power mode.
Well, maybe I'm not explaining the issue very well. Here the test done
which led me to this conclusion:
The?test?are?done?using?iperf. Receiving data works well, with the
expected performance. Sending data is the problem, and only under high
load:
Here are the lpi stats before starting the test:
? ? ?irq_tx_path_in_lpi_mode_n: 6
?????irq_tx_path_exit_lpi_mode_n: 5
?????irq_rx_path_in_lpi_mode_n: 76
?????irq_rx_path_exit_lpi_mode_n: 75
?????phy_eee_wakeup_error_n: 0
Sending data with iperf usually works for little while (between 0 and
10s)
# iperf3 -c 192.168.1.170 -p12345
Connecting to host 192.168.1.170, port 12345
local 192.168.1.30 port 54450 connected to 192.168.1.170 port 12345
Interval???????????Transfer?????Bandwidth???????Retr??Cwnd
0.00-1.00???sec???112 MBytes???938 Mbits/sec????0????409 KBytes???????
1.00-2.00???sec???112 MBytes???940 Mbits/sec????0????426 KBytes???????
2.00-3.00???sec???112 MBytes???939 Mbits/sec????0????426 KBytes???????
3.00-4.00???sec???112 MBytes???940 Mbits/sec????0????426 KBytes???????
4.00-5.00???sec???112 MBytes???940 Mbits/sec????0????426 KBytes???????
5.00-6.00???sec???112 MBytes???939 Mbits/sec????0????426 KBytes???????
6.00-7.00???sec??9.26 MBytes??77.6 Mbits/sec????2???1.41 KBytes <=Issue
? ?
7.00-8.00???sec??0.00 Bytes??0.00 bits/sec????1???1.41 KBytes???????
8.00-9.00???sec??0.00 Bytes??0.00 bits/sec????0???1.41 KBytes???????
^C10.00-13.58??sec??0.00 Bytes??0.00 bits/sec????1???1.41 KBytes???????
- - - - - - - - - - - - - - - - - - - - - - - - -
Interval???????????Transfer?????Bandwidth???????Retr
0.00-13.58??sec???681 MBytes???421 Mbits/sec????4?????????????sender
0.00-13.58??sec??0.00 Bytes??0.00 bits/sec??????????????????receiver
iperf3: interrupt - the client has terminated
iperf3 does not exit ant the link seems completely broken. We cannot
send or receive until the interface is brought down then up again.
Here are the LPI related stats after the test:
?????irq_tx_path_in_lpi_mode_n: 48
?????irq_tx_path_exit_lpi_mode_n: 48
?????irq_rx_path_in_lpi_mode_n: 325
?????irq_rx_path_exit_lpi_mode_n: 325
?????phy_eee_wakeup_error_n: 0
This happens with :
1) Default configuration: EEE enabled on the MAC, PHY with reset
settings (EEE advertised)
2) EEE disabled on the MAC, PHY still with reset settings (EEE
advertised). In such case there is no irq_tx_path_*_lpi_mode interrupts
at all but still a lot of irq_rx_path_*_lpi_mode interrupts. So even if
the mac does not drive anything EEE related, there is still something
happening between the PHY and the link partner regarding EEE.
3) Disabling EEE advertisement for 1000t: no irq_*_lpi_mode@all. The
feature is not negotiated and the Tx works well.
By the way, EEE work well for the 100tx on the same HW.
>
> >
> > >
> > > On the SolidRun boards, they're using AR8035, and have suffered
> > > this
> > > occasional link drop problem.??What has been found is that it
> > > seems
> > > to
> > > be to do with the timing parameters, and it seemed to only be
> > > 1000bT
> > > that was affected.??I don't remember off hand exactly which or
> > > what
> > > the change was they made to stabilise it though, but I can
> > > probabily
> > > find out tomorrow.
> > >
> >
> > Since the same combination of MAC-PHY works well on other designs,
> > it
> > is also my feeling that is has something to do with some timing
> > parameter, maybe related to this particular PCB.
>
> Maybe a different PHY interface???Meson seems to use RGMII, maybe
> others use SGMII - but then I'd expect 100base-Tx to also be broken.
> So not really sure.
Nope, same interface (RGMII), same SoC. Only the PCB layout and
external components might be different.
>
> I was talking to Florian about that last night, because the mis-named
> phy_init_eee() tests for various phy interface modes before
> proceeding,
> which seems to be fairly rubbish as the list of interface modes is
> gradually increasing since it was introduced (and I need to add SGMII
> to it.)??The conclusion I've come to there is that the test should
> never have been part of phylib, because if there are restrictions on
> which phy interface modes are allowable for EEE, they're likely to be
> either PHY or MAC specific.
>
> The other problem that having the test there causes is that if the
> existing users can't handle EEE over SGMII, then when I add SGMII to
> support my hardware, they end up breaking - far from desirable.
> There's no information on why the test is there, or even which PHYs
> or MACs it's applicable to, which makes this unnecessarily more
> difficult to now resolve.
>
> My feeling is that the integration of EEE into phylib is fairly poor
> at the moment, and we need to be a lot smarter about it.
You know a lot more than I do on this topic obviously. I'm just trying
to make GbE work (as cleanly as possible) on that board to be honest.
So I'm not sure I understand, are you against EEE integration in phylib
entirely, or specifically against the test I added in set_eee to filter
out broken modes ?
Since set_eee directly set the register, I don't see where else I could
have put this test to prevent EEE broken modes from being re-enabled.
>
> BTW, one of the problems (not caused by your patch) is that changing
> the EEE advertisment does not (on all PHY drivers) cause the link to
> be renegotiated - there's no call to phy_start_aneg() when the advert
> changes, and even if there was, there's no guarantee that
> phy_start_aneg() will even set the AN restart bit in the control
> register.
>
> However, given that you're hooking into the set_eee function, I'm not
> sure why you placed your EEE advertisment thing into config_aneg() -
> isn't it more an initialisation thing (so should be in
> config_init()?)
What I change is what the PHY advertise, so it seems logical to do it
where "genphy_config_advert" was called. Just taking the existing code
as an example
>
^ permalink raw reply
* [PATCH v5 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-06 13:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134929.mj7wqalp7lpkfm6b@kozik-lap>
Hi Krzysztof,
> > -#include "exynos5433-tm2.dts"
> > +#include "exynos5433-tm2-common.dtsi"
> >
> > / {
> > model = "Samsung TM2E board";
>
> Where are the regulators?
No need, they were already overwriting the original property, so
with your suggestion they didn't change in tm2e. That's why I like
your suggestion.
Originally I added the 'regulator' label to not have empty nodes.
Andi
^ permalink raw reply
* [PATCH 1/4] phy: sun4i-usb: add support for V3s USB PHY
From: Maxime Ripard @ 2017-01-06 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103152534.20118-2-icenowy@aosc.xyz>
On Tue, Jan 03, 2017 at 11:25:31PM +0800, Icenowy Zheng wrote:
> Allwinner V3s come with a USB PHY controller slightly different to other
> SoCs, with only one PHY.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 2/4] musb: sunxi: add support for the variant in H3/V3s SoC
From: Maxime Ripard @ 2017-01-06 13:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103152534.20118-3-icenowy@aosc.xyz>
On Tue, Jan 03, 2017 at 11:25:32PM +0800, Icenowy Zheng wrote:
> Allwinner H3/V3s features a variant of MUSB controller, which lacks one
> endpoint.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [RFC v2 PATCH 1/3] ARM: NOMMU: introduce dma operations for noMMU
From: Benjamin Gaignard @ 2017-01-06 13:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9c957673-64ba-67ca-46a0-2bde26c95d9c@arm.com>
2017-01-04 11:33 GMT+01:00 Vladimir Murzin <vladimir.murzin@arm.com>:
> Hello Benjamin,
>
> On 02/01/17 15:26, Benjamin Gaignard wrote:
>> Hello Vladimir,
>>
>> I have tested your patch on my setup (stm32f4: no MMU, no MPU) where
>> I'm writing display driver.
>> This driver use dma_alloc_wc() and dma_mmap_wc() for frame buffer
>> allocation and mmapping.
>>
>> In dma-mapping-nommu.c you haven't implement dma_map_ops.mmap so
>> obviously my driver
>> doesn't work with your code.
>> In current implementation it is buggy too but I submit a patch to fix
>> that problem:
>> http://www.armlinux.org.uk/developer/patches/viewpatch.php?id=8633/1
>>
>> Could it be possible for you to include mmap support in dma-mapping-nommu.c ?
>>
>
> IIRC, stm32f4 is Cortex-M4, so no cache support and it means that it uses
> dma_noop_ops. I offloaded mmap to common implementation, but completely forgot
> it has the same restriction as arm counterpart. Regardless, thanks for
> noticing that!
>
> It seems that I need to check that mapping is done from DMA coherent area (I'm
> moving to dma-coherent and here we have dma_mmap_from_coherent for that) and
> something like bellow for dma_noop_ops:
>
> diff --git a/lib/dma-noop.c b/lib/dma-noop.c
> index 3d766e7..d838b88 100644
> --- a/lib/dma-noop.c
> +++ b/lib/dma-noop.c
> @@ -64,6 +64,25 @@ static int dma_noop_supported(struct device *dev, u64 mask)
> return 1;
> }
>
> +static int dma_noop_mmap(struct device *dev, struct vm_area_struct *vma,
> + void *cpu_addr, dma_addr_t dma_addr, size_t size)
> +{
> + unsigned long user_count = vma_pages(vma);
> + unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
> + unsigned long pfn = page_to_pfn(virt_to_page(cpu_addr));
> + unsigned long off = vma->vm_pgoff;
> + int ret = -ENXIO;
> +
> + if (off < count && user_count <= (count - off)) {
> + ret = remap_pfn_range(vma, vma->vm_start,
> + pfn + off,
> + user_count << PAGE_SHIFT,
> + vma->vm_page_prot);
> + }
> +
> + return ret;
> +}
> +
> struct dma_map_ops dma_noop_ops = {
> .alloc = dma_noop_alloc,
> .free = dma_noop_free,
> @@ -71,6 +90,7 @@ struct dma_map_ops dma_noop_ops = {
> .map_sg = dma_noop_map_sg,
> .mapping_error = dma_noop_mapping_error,
> .dma_supported = dma_noop_supported,
> + .mmap = dma_noop_mmap,
> };
>
> EXPORT_SYMBOL(dma_noop_ops);
>
> I'd be glad to hear if it works for you.
With your patch mmap() does return an address unfortunately
framebuffer isn't displayed
anymore, I have a black screen instead of the usual pattern.
Without your patches my allocations dma_alloc_wc requests go to
dma-mapping so I guess
the problem is coming from dma noop implementation.
I have try to use dma-mapping-nommu ops but the status is the same.
>
> Cheers
> Vladimir
>
>> Regards,
>> Benjamin
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 0/4] Introduce STM32F7 Clocks
From: gabriel.fernandez at st.com @ 2017-01-06 13:59 UTC (permalink / raw)
To: linux-arm-kernel
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch-set introduces STM32F7 clocks.
F7 Clocks are very similar as F4.
We have some new clocks:
- hdmi-cec
- spdif-rx
- lptim1
- sai2
Uarts & I2cs can have different clock sources.
Gabriel Fernandez (4):
clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
clk: stm32f7: Introduce stm32f7 clocks for STM32F746 boards
ARM: dts: stm32: stm32f7: Enable clocks for STM32F746 boards
dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include
file
.../devicetree/bindings/clock/st,stm32-rcc.txt | 20 ++
arch/arm/boot/dts/stm32f746.dtsi | 80 ++++--
drivers/clk/clk-stm32f4.c | 277 ++++++++++++++++++++-
include/dt-bindings/clock/stm32fx-clock.h | 20 ++
include/dt-bindings/mfd/stm32f7-rcc.h | 112 +++++++++
5 files changed, 476 insertions(+), 33 deletions(-)
create mode 100644 include/dt-bindings/mfd/stm32f7-rcc.h
--
1.9.1
^ permalink raw reply
* [PATCH 1/4] clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
From: gabriel.fernandez at st.com @ 2017-01-06 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483711165-17149-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch introduces the stm32f7 clock DT bindings.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
.../devicetree/bindings/clock/st,stm32-rcc.txt | 20 ++++++++++++++++++++
include/dt-bindings/clock/stm32fx-clock.h | 20 ++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
index 8f19d87..b240121 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
@@ -10,6 +10,7 @@ Required properties:
- compatible: Should be:
"st,stm32f42xx-rcc"
"st,stm32f469-rcc"
+ "st,stm32f746-rcc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
@@ -84,6 +85,25 @@ The secondary index is bound with the following magic numbers:
12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
+ 14 CLK_HSI (Internal ocscillator clock)
+ 15 CLK_SYSCLK (System Clock)
+ 16 CLK_HDMI_CEC (HDMI-CEC clock)
+ 17 CLK_SPDIF (SPDIF-Rx clock)
+ 18 CLK_USART1 (U(s)arts clocks)
+ 19 CLK_USART2
+ 20 CLK_USART3
+ 21 CLK_UART4
+ 22 CLK_UART5
+ 23 CLK_USART6
+ 24 CLK_UART7
+ 25 CLK_UART8
+ 26 CLK_I2C1 (I2S clocks)
+ 27 CLK_I2C2
+ 28 CLK_I2C3
+ 29 CLK_I2C4
+ 30 CLK_LPTIMER (LPTimer1 clock)
+)
+
Example:
/* Misc clock, FCLK */
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 08bcab6..49bb3c2 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -36,4 +36,24 @@
#define END_PRIMARY_CLK 14
+#define CLK_HSI 14
+#define CLK_SYSCLK 15
+#define CLK_HDMI_CEC 16
+#define CLK_SPDIF 17
+#define CLK_USART1 18
+#define CLK_USART2 19
+#define CLK_USART3 20
+#define CLK_UART4 21
+#define CLK_UART5 22
+#define CLK_USART6 23
+#define CLK_UART7 24
+#define CLK_UART8 25
+#define CLK_I2C1 26
+#define CLK_I2C2 27
+#define CLK_I2C3 28
+#define CLK_I2C4 29
+#define CLK_LPTIMER 30
+
+#define END_PRIMARY_CLK_F7 31
+
#endif
--
1.9.1
^ permalink raw reply related
* [PATCH 2/4] clk: stm32f7: Introduce stm32f7 clocks for STM32F746 boards
From: gabriel.fernandez at st.com @ 2017-01-06 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483711165-17149-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch enables clocks for STM32F746 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 277 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 271 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 42f8534..344a411 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -48,6 +48,7 @@
#define STM32F4_RCC_PLLI2SCFGR 0x84
#define STM32F4_RCC_PLLSAICFGR 0x88
#define STM32F4_RCC_DCKCFGR 0x8c
+#define STM32F7_RCC_DCKCFGR2 0x90
#define NONE -1
#define NO_IDX NONE
@@ -224,6 +225,80 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
};
+static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
+ { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
+ { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
+
+ { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
+ { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
+ { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
+ { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
+ { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
+
+ { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
+ CLK_IGNORE_UNUSED },
+ { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
+ CLK_IGNORE_UNUSED },
+
+ { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
+ { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
+ { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
+
+ { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 11, "sdmmc", "sdmux" },
+ { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
+ { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
+};
+
/*
* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
* have gate bits associated with them. Its combined hweight is 71.
@@ -238,6 +313,10 @@ struct stm32f4_gate_data {
0x0000000000000003ull,
0x0c777f33f6fec9ffull };
+static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
+ 0x0000000000000003ull,
+ 0x04f77f033e01c9ffull };
+
static const u64 *stm32f4_gate_map;
static struct clk_hw **clks;
@@ -247,6 +326,8 @@ struct stm32f4_gate_data {
static struct regmap *pdrm;
+static int stm32fx_end_primary_clk;
+
/*
* "Multiplier" device for APBx clocks.
*
@@ -685,7 +766,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
u64 table[MAX_GATE_MAP];
if (primary == 1) {
- if (WARN_ON(secondary >= END_PRIMARY_CLK))
+ if (WARN_ON(secondary >= stm32fx_end_primary_clk))
return -EINVAL;
return secondary;
}
@@ -702,7 +783,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
table[BIT_ULL_WORD(secondary)] &=
GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
- return END_PRIMARY_CLK - 1 + hweight64(table[0]) +
+ return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
(BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
(BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
}
@@ -955,6 +1036,17 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
static const char *sdmux_parents[2] = { "pll48", "sys" };
+static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
+
+static const char *spdif_parent[1] = { "plli2s-p" };
+
+static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
+
+static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
+static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
+
+static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
+
struct stm32_aux_clk {
int idx;
const char *name;
@@ -975,6 +1067,7 @@ struct stm32f4_clk_data {
const struct stm32f4_pll_data *pll_data;
const struct stm32_aux_clk *aux_clk;
int aux_clk_num;
+ int end_primary;
};
static const struct stm32_aux_clk stm32f429_aux_clk[] = {
@@ -1043,7 +1136,154 @@ struct stm32f4_clk_data {
},
};
+static const struct stm32_aux_clk stm32f746_aux_clk[] = {
+ {
+ CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
+ NO_MUX, 0, 0,
+ STM32F4_RCC_APB2ENR, 26,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
+ STM32F4_RCC_CFGR, 23, 1,
+ NO_GATE, 0,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
+ STM32F4_RCC_DCKCFGR, 20, 3,
+ STM32F4_RCC_APB2ENR, 22,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
+ STM32F4_RCC_DCKCFGR, 22, 3,
+ STM32F4_RCC_APB2ENR, 23,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
+ STM32F7_RCC_DCKCFGR2, 27, 1,
+ NO_GATE, 0,
+ 0
+ },
+ {
+ NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
+ STM32F7_RCC_DCKCFGR2, 28, 1,
+ NO_GATE, 0,
+ 0
+ },
+ {
+ CLK_HDMI_CEC, "hdmi-cec",
+ hdmi_parents, ARRAY_SIZE(hdmi_parents),
+ STM32F7_RCC_DCKCFGR2, 26, 1,
+ NO_GATE, 0,
+ 0
+ },
+ {
+ CLK_SPDIF, "spdif-rx",
+ spdif_parent, ARRAY_SIZE(spdif_parent),
+ STM32F7_RCC_DCKCFGR2, 22, 3,
+ STM32F4_RCC_APB2ENR, 23,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ CLK_USART1, "usart1",
+ uart_parents1, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 0, 3,
+ STM32F4_RCC_APB2ENR, 4,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_USART2, "usart2",
+ uart_parents2, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 2, 3,
+ STM32F4_RCC_APB1ENR, 17,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_USART3, "usart3",
+ uart_parents2, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 4, 3,
+ STM32F4_RCC_APB1ENR, 18,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_UART4, "uart4",
+ uart_parents2, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 6, 3,
+ STM32F4_RCC_APB1ENR, 19,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_UART5, "uart5",
+ uart_parents2, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 8, 3,
+ STM32F4_RCC_APB1ENR, 20,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_USART6, "usart6",
+ uart_parents1, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 10, 3,
+ STM32F4_RCC_APB2ENR, 5,
+ CLK_SET_RATE_PARENT,
+ },
+
+ {
+ CLK_UART7, "uart7",
+ uart_parents2, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 12, 3,
+ STM32F4_RCC_APB1ENR, 30,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_UART8, "uart8",
+ uart_parents2, ARRAY_SIZE(uart_parents1),
+ STM32F7_RCC_DCKCFGR2, 14, 3,
+ STM32F4_RCC_APB1ENR, 31,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_I2C1, "i2c1",
+ i2c_parents, ARRAY_SIZE(i2c_parents),
+ STM32F7_RCC_DCKCFGR2, 16, 3,
+ STM32F4_RCC_APB1ENR, 21,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_I2C2, "i2c2",
+ i2c_parents, ARRAY_SIZE(i2c_parents),
+ STM32F7_RCC_DCKCFGR2, 18, 3,
+ STM32F4_RCC_APB1ENR, 22,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_I2C3, "i2c3",
+ i2c_parents, ARRAY_SIZE(i2c_parents),
+ STM32F7_RCC_DCKCFGR2, 20, 3,
+ STM32F4_RCC_APB1ENR, 23,
+ CLK_SET_RATE_PARENT,
+ },
+ {
+ CLK_I2C4, "i2c4",
+ i2c_parents, ARRAY_SIZE(i2c_parents),
+ STM32F7_RCC_DCKCFGR2, 22, 3,
+ STM32F4_RCC_APB1ENR, 24,
+ CLK_SET_RATE_PARENT,
+ },
+
+ {
+ CLK_LPTIMER, "lptim1",
+ lptim_parent, ARRAY_SIZE(lptim_parent),
+ STM32F7_RCC_DCKCFGR2, 24, 3,
+ STM32F4_RCC_APB1ENR, 9,
+ CLK_SET_RATE_PARENT
+ },
+};
+
static const struct stm32f4_clk_data stm32f429_clk_data = {
+ .end_primary = END_PRIMARY_CLK,
.gates_data = stm32f429_gates,
.gates_map = stm32f42xx_gate_map,
.gates_num = ARRAY_SIZE(stm32f429_gates),
@@ -1053,6 +1293,7 @@ struct stm32f4_clk_data {
};
static const struct stm32f4_clk_data stm32f469_clk_data = {
+ .end_primary = END_PRIMARY_CLK,
.gates_data = stm32f469_gates,
.gates_map = stm32f46xx_gate_map,
.gates_num = ARRAY_SIZE(stm32f469_gates),
@@ -1061,6 +1302,16 @@ struct stm32f4_clk_data {
.aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk),
};
+static const struct stm32f4_clk_data stm32f746_clk_data = {
+ .end_primary = END_PRIMARY_CLK_F7,
+ .gates_data = stm32f746_gates,
+ .gates_map = stm32f746_gate_map,
+ .gates_num = ARRAY_SIZE(stm32f746_gates),
+ .pll_data = stm32f469_pll,
+ .aux_clk = stm32f746_aux_clk,
+ .aux_clk_num = ARRAY_SIZE(stm32f746_aux_clk),
+};
+
static const struct of_device_id stm32f4_of_match[] = {
{
.compatible = "st,stm32f42xx-rcc",
@@ -1070,6 +1321,10 @@ struct stm32f4_clk_data {
.compatible = "st,stm32f469-rcc",
.data = &stm32f469_clk_data
},
+ {
+ .compatible = "st,stm32f746-rcc",
+ .data = &stm32f746_clk_data
+ },
{}
};
@@ -1161,7 +1416,9 @@ static void __init stm32f4_rcc_init(struct device_node *np)
data = match->data;
- clks = kmalloc_array(data->gates_num + END_PRIMARY_CLK,
+ stm32fx_end_primary_clk = data->end_primary;
+
+ clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
sizeof(*clks), GFP_KERNEL);
if (!clks)
goto fail;
@@ -1175,8 +1432,9 @@ static void __init stm32f4_rcc_init(struct device_node *np)
i2s_parents[1] = i2s_in_clk;
sai_parents[2] = i2s_in_clk;
- clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
- 16000000, 160000);
+ clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
+ NULL, 0, 16000000, 160000);
+
pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
pllm = pllcfgr & 0x3f;
@@ -1215,7 +1473,8 @@ static void __init stm32f4_rcc_init(struct device_node *np)
}
sys_parents[1] = hse_clk;
- clk_register_mux_table(
+
+ clks[CLK_SYSCLK] = clk_hw_register_mux_table(
NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
@@ -1319,6 +1578,11 @@ static void __init stm32f4_rcc_init(struct device_node *np)
clks[aux_clk->idx] = hw;
}
+ if (of_device_is_compatible(np, "st,stm32f746-rcc"))
+
+ clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
+ 1, 488);
+
of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
return;
fail:
@@ -1327,3 +1591,4 @@ static void __init stm32f4_rcc_init(struct device_node *np)
}
CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
+CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
--
1.9.1
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: stm32: stm32f7: Enable clocks for STM32F746 boards
From: gabriel.fernandez at st.com @ 2017-01-06 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483711165-17149-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch enables clocks for STM32F746 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index f321ffe..e05e131 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -43,6 +43,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+#include <dt-bindings/clock/stm32fx-clock.h>
/ {
clocks {
@@ -51,6 +52,24 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
+
+ clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_i2s_ckin: clk-i2s-ckin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ };
};
soc {
@@ -178,6 +197,11 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
};
+ pwrcfg: power-config at 40007000 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
@@ -291,9 +315,10 @@
rcc: rcc at 40023800 {
#clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
- clocks = <&clk_hse>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
+ st,syscfg = <&pwrcfg>;
};
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH 4/4] dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file
From: gabriel.fernandez at st.com @ 2017-01-06 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483711165-17149-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch lists STM32F7's RCC numeric constants.
It will be used by clock and reset drivers, and DT bindings.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 51 ++++++++--------
include/dt-bindings/mfd/stm32f7-rcc.h | 112 ++++++++++++++++++++++++++++++++++
2 files changed, 138 insertions(+), 25 deletions(-)
create mode 100644 include/dt-bindings/mfd/stm32f7-rcc.h
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index e05e131..09d6649 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -44,6 +44,7 @@
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
clocks {
@@ -77,7 +78,7 @@
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
- clocks = <&rcc 0 128>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
@@ -85,7 +86,7 @@
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
- clocks = <&rcc 0 129>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
};
@@ -93,7 +94,7 @@
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
- clocks = <&rcc 0 130>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
};
@@ -101,14 +102,14 @@
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
- clocks = <&rcc 0 131>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
timer6: timer at 40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
- clocks = <&rcc 0 132>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
@@ -116,7 +117,7 @@
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
- clocks = <&rcc 0 133>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
@@ -124,7 +125,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
- clocks = <&rcc 0 145>;
+ clocks = <&rcc 1 CLK_USART2>;
status = "disabled";
};
@@ -132,7 +133,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
- clocks = <&rcc 0 146>;
+ clocks = <&rcc 1 CLK_USART3>;
status = "disabled";
};
@@ -140,7 +141,7 @@
compatible = "st,stm32f7-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
- clocks = <&rcc 0 147>;
+ clocks = <&rcc 1 CLK_UART4>;
status = "disabled";
};
@@ -148,7 +149,7 @@
compatible = "st,stm32f7-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
- clocks = <&rcc 0 148>;
+ clocks = <&rcc 1 CLK_UART5>;
status = "disabled";
};
@@ -156,7 +157,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007800 0x400>;
interrupts = <82>;
- clocks = <&rcc 0 158>;
+ clocks = <&rcc 1 CLK_UART7>;
status = "disabled";
};
@@ -164,7 +165,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007c00 0x400>;
interrupts = <83>;
- clocks = <&rcc 0 159>;
+ clocks = <&rcc 1 CLK_UART8>;
status = "disabled";
};
@@ -172,7 +173,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
- clocks = <&rcc 0 164>;
+ clocks = <&rcc 1 CLK_USART1>;
status = "disabled";
};
@@ -180,7 +181,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011400 0x400>;
interrupts = <71>;
- clocks = <&rcc 0 165>;
+ clocks = <&rcc 1 CLK_USART6>;
status = "disabled";
};
@@ -215,7 +216,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
- clocks = <&rcc 0 256>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
@@ -223,7 +224,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x400 0x400>;
- clocks = <&rcc 0 257>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
@@ -231,7 +232,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x800 0x400>;
- clocks = <&rcc 0 258>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
@@ -239,7 +240,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0xc00 0x400>;
- clocks = <&rcc 0 259>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
@@ -247,7 +248,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1000 0x400>;
- clocks = <&rcc 0 260>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
@@ -255,7 +256,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1400 0x400>;
- clocks = <&rcc 0 261>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
@@ -263,7 +264,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1800 0x400>;
- clocks = <&rcc 0 262>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
@@ -271,7 +272,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1c00 0x400>;
- clocks = <&rcc 0 263>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
@@ -279,7 +280,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x2000 0x400>;
- clocks = <&rcc 0 264>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
@@ -287,7 +288,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x2400 0x400>;
- clocks = <&rcc 0 265>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
@@ -295,7 +296,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x2800 0x400>;
- clocks = <&rcc 0 266>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
new file mode 100644
index 0000000..e36cc69
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -0,0 +1,112 @@
+/*
+ * This header provides constants for the STM32F7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
+#define _DT_BINDINGS_MFD_STM32F7_RCC_H
+
+/* AHB1 */
+#define STM32F7_RCC_AHB1_GPIOA 0
+#define STM32F7_RCC_AHB1_GPIOB 1
+#define STM32F7_RCC_AHB1_GPIOC 2
+#define STM32F7_RCC_AHB1_GPIOD 3
+#define STM32F7_RCC_AHB1_GPIOE 4
+#define STM32F7_RCC_AHB1_GPIOF 5
+#define STM32F7_RCC_AHB1_GPIOG 6
+#define STM32F7_RCC_AHB1_GPIOH 7
+#define STM32F7_RCC_AHB1_GPIOI 8
+#define STM32F7_RCC_AHB1_GPIOJ 9
+#define STM32F7_RCC_AHB1_GPIOK 10
+#define STM32F7_RCC_AHB1_CRC 12
+#define STM32F7_RCC_AHB1_BKPSRAM 18
+#define STM32F7_RCC_AHB1_DTCMRAM 20
+#define STM32F7_RCC_AHB1_DMA1 21
+#define STM32F7_RCC_AHB1_DMA2 22
+#define STM32F7_RCC_AHB1_DMA2D 23
+#define STM32F7_RCC_AHB1_ETHMAC 25
+#define STM32F7_RCC_AHB1_ETHMACTX 26
+#define STM32F7_RCC_AHB1_ETHMACRX 27
+#define STM32FF_RCC_AHB1_ETHMACPTP 28
+#define STM32F7_RCC_AHB1_OTGHS 29
+#define STM32F7_RCC_AHB1_OTGHSULPI 30
+
+#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
+
+
+/* AHB2 */
+#define STM32F7_RCC_AHB2_DCMI 0
+#define STM32F7_RCC_AHB2_CRYP 4
+#define STM32F7_RCC_AHB2_HASH 5
+#define STM32F7_RCC_AHB2_RNG 6
+#define STM32F7_RCC_AHB2_OTGFS 7
+
+#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F7_RCC_AHB3_FMC 0
+#define STM32F7_RCC_AHB3_QSPI 1
+
+#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F7_RCC_APB1_TIM2 0
+#define STM32F7_RCC_APB1_TIM3 1
+#define STM32F7_RCC_APB1_TIM4 2
+#define STM32F7_RCC_APB1_TIM5 3
+#define STM32F7_RCC_APB1_TIM6 4
+#define STM32F7_RCC_APB1_TIM7 5
+#define STM32F7_RCC_APB1_TIM12 6
+#define STM32F7_RCC_APB1_TIM13 7
+#define STM32F7_RCC_APB1_TIM14 8
+#define STM32F7_RCC_APB1_LPTIM1 9
+#define STM32F7_RCC_APB1_WWDG 11
+#define STM32F7_RCC_APB1_SPI2 14
+#define STM32F7_RCC_APB1_SPI3 15
+#define STM32F7_RCC_APB1_SPDIFRX 16
+#define STM32F7_RCC_APB1_UART2 17
+#define STM32F7_RCC_APB1_UART3 18
+#define STM32F7_RCC_APB1_UART4 19
+#define STM32F7_RCC_APB1_UART5 20
+#define STM32F7_RCC_APB1_I2C1 21
+#define STM32F7_RCC_APB1_I2C2 22
+#define STM32F7_RCC_APB1_I2C3 23
+#define STM32F7_RCC_APB1_I2C4 24
+#define STM32F7_RCC_APB1_CAN1 25
+#define STM32F7_RCC_APB1_CAN2 26
+#define STM32F7_RCC_APB1_CEC 27
+#define STM32F7_RCC_APB1_PWR 28
+#define STM32F7_RCC_APB1_DAC 29
+#define STM32F7_RCC_APB1_UART7 30
+#define STM32F7_RCC_APB1_UART8 31
+
+#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F7_RCC_APB2_TIM1 0
+#define STM32F7_RCC_APB2_TIM8 1
+#define STM32F7_RCC_APB2_USART1 4
+#define STM32F7_RCC_APB2_USART6 5
+#define STM32F7_RCC_APB2_ADC1 8
+#define STM32F7_RCC_APB2_ADC2 9
+#define STM32F7_RCC_APB2_ADC3 10
+#define STM32F7_RCC_APB2_SDMMC1 11
+#define STM32F7_RCC_APB2_SPI1 12
+#define STM32F7_RCC_APB2_SPI4 13
+#define STM32F7_RCC_APB2_SYSCFG 14
+#define STM32F7_RCC_APB2_TIM9 16
+#define STM32F7_RCC_APB2_TIM10 17
+#define STM32F7_RCC_APB2_TIM11 18
+#define STM32F7_RCC_APB2_SPI5 20
+#define STM32F7_RCC_APB2_SPI6 21
+#define STM32F7_RCC_APB2_SAI1 22
+#define STM32F7_RCC_APB2_SAI2 23
+#define STM32F7_RCC_APB2_LTDC 26
+
+#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
--
1.9.1
^ permalink raw reply related
* [PATCH v5 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-06 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106135357.n4ugkcdcog4hzbhe@gangnam.samsung>
On Fri, Jan 6, 2017 at 3:53 PM, Andi Shyti <andi.shyti@samsung.com> wrote:
> Hi Krzysztof,
>
>> > -#include "exynos5433-tm2.dts"
>> > +#include "exynos5433-tm2-common.dtsi"
>> >
>> > / {
>> > model = "Samsung TM2E board";
>>
>> Where are the regulators?
>
> No need, they were already overwriting the original property, so
> with your suggestion they didn't change in tm2e. That's why I like
> your suggestion.
>
> Originally I added the 'regulator' label to not have empty nodes.
Yes, I understand, I spotted it right now. Everything looks good, thanks.
Applied.
BR,
Krzysztof
^ permalink raw reply
* [PATCH v5 1/5] arm64: dts: exynos5433: TM2/E: Fix wrong values for ldo23 and ldo25
From: Krzysztof Kozlowski @ 2017-01-06 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134350.32428-2-andi.shyti@samsung.com>
On Fri, Jan 06, 2017 at 10:43:46PM +0900, Andi Shyti wrote:
> From: Chanwoo Choi <cw00.choi@samsung.com>
>
> This patch fixes wrong values assigned to ldo23 and ldo25 on both TM2 and TM2E.
>
> Fixes: 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 6 +++---
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 9 ---------
> 2 files changed, 3 insertions(+), 12 deletions(-)
>
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v5 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Javier Martinez Canillas @ 2017-01-06 14:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170106134929.mj7wqalp7lpkfm6b@kozik-lap>
Hello Krzysztof,
On 01/06/2017 10:49 AM, Krzysztof Kozlowski wrote:
> On Fri, Jan 06, 2017 at 10:43:47PM +0900, Andi Shyti wrote:
>> Currently tm2e dts includes tm2 but there are some differences
>> between the two boards and tm2 has some properties that tm2e
>> doesn't have.
>>
>> That's why it's important to keep the two dts files independent
>> and put all the commonalities in a tm2-common.dtsi file.
>>
>> At the current status the only two differences between the two
>> dts files (besides the board name) are ldo31 and ldo38.
>>
>> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
>> ---
[snip]
> Beside that it is starting to look good. I didn't find anything else but
> maybe Javier's eagle eye will catch something.
>
I didn't find anything else, the patch looks good to me now.
>
> Best regards,
> Krzysztof
>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
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