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* [RFC PATCH 1/2] ARM: vfp - allow kernel mode NEON in softirq context
From: Ard Biesheuvel @ 2017-01-11 18:23 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111175649.GK14217@n2100.armlinux.org.uk>

On 11 January 2017 at 17:56, Russell King - ARM Linux
<linux@armlinux.org.uk> wrote:
> On Mon, Jan 09, 2017 at 07:57:28PM +0000, Ard Biesheuvel wrote:
>> This updates the kernel mode NEON handling to allow the NEON to be used
>> in softirq context as well as process context. This involves disabling
>> softirq processing when the NEON is used in kernel mode in process context,
>> and dealing with the situation where 'current' is not the owner of the
>> userland context that is present in the NEON register file when the NEON
>> is enabled in kernel mode.
>
> I really don't like this idea as-is.
>
> We have cases where kernel code accesses VFP to (eg) save or restore
> register state, such as during signal handling.  We assume that this
> will not be interrupted by another user, and that if we enable access
> to the VFP, it will stay enabled.  If it gets disabled beneath us, then
> things won't go well.
>
> For example, consider vfp_sync_hwstate():
>
> vfp_sync_hwstate()
>   vfp_state_in_hw() => true
>     fpexc read
>         softirq happens
>                 kernel_neon_begin()
>                 kernel_neon_end()
>     fpexc re-enabled
>     current register state saved out (corrupting what was there)
>     fpexc restored, possible in an enabled state
>
> Or we could have:
>
> vfp_sync_hwstate()
>   vfp_state_in_hw() => true
>         softirq happens
>                 kernel_neon_begin()
>                 kernel_neon_end()
>     fpexc read
>     fpexc re-enabled
>     current register state saved out (corrupting what was there)
>     fpexc disabled
>
> Or worse:
>
> vfp_sync_hwstate()
>   vfp_state_in_hw() => true
>     fpexc read
>     fpexc re-enabled
>         softirq happens
>                 kernel_neon_begin()
>                 kernel_neon_end()
>     current register state saved out, blowing up because VFP is
>      unexpectedly disabled
>
> So we would need to disable softirqs around every sensitive point in the
> VFP support code, and over all VFP instruction emulations for those VFPs
> which bounce "difficult" operations to the kernel support code.
>

Ah yes, I should have known it couldn't be that simple.

Thanks for the critique: i will look into the impact of making these changes.

>> The rationale for this change is that the NEON is shared with the ARMv8
>> Crypto Extensions (which are also defined for the AArch32 execution state),
>> which can give a huge performance boost (15x) to use cases like mac80211
>> CCMP processing, which executes in softirq context.
>
> I think, once the implementation is more correct, this would need to
> be re-evaluated, and I'd also like other more general performance
> measurements as well (eg, latency.)
>

Re latency, I thought about adding a kernel_neon_yield(), which does a
kernel_neon_end()/do_softirq()/kernel_neon_begin() sequence if any
softirqs are pending, to be invoked by kernel mode NEON users at times
when there are no live NEON registers. But in-kernel users of the
crypto API are naturally quantised into disk sectors, pages or network
packets, so I would not expect any noticeable starvation to occur. But
that does mean such algorithms should not be exposed to userland
(which sounds like a bad idea in any case, given that userland can
simply execute the same instructions)

^ permalink raw reply

* [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
From: Marc Zyngier @ 2017-01-11 18:22 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111180627.GG20288@e104818-lin.cambridge.arm.com>

On 11/01/17 18:06, Catalin Marinas wrote:
> Some minor comments below, nothing fundamental (as long as you say the
> new sequence doesn't have the speculative TLB load problem I mentioned
> on a previous version).
> 
> On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
>> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
>> index 405da11..7151aed 100644
>> --- a/Documentation/arm64/silicon-errata.txt
>> +++ b/Documentation/arm64/silicon-errata.txt
>> @@ -42,24 +42,25 @@ file acts as a registry of software workarounds in the Linux Kernel and
>>  will be updated when new workarounds are committed and backported to
>>  stable kernels.
>>  
>> -| Implementor    | Component       | Erratum ID      | Kconfig                 |
>> -+----------------+-----------------+-----------------+-------------------------+
>> -| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319    |
>> -| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319    |
>> -| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069    |
>> -| ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472    |
>> -| ARM            | Cortex-A53      | #845719         | ARM64_ERRATUM_845719    |
>> -| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419    |
>> -| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    |
>> -| ARM            | Cortex-A57      | #852523         | N/A                     |
>> -| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220    |
>> -| ARM            | Cortex-A72      | #853709         | N/A                     |
>> -| ARM            | MMU-500         | #841119,#826419 | N/A                     |
>> -|                |                 |                 |                         |
>> -| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
>> -| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144    |
>> -| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
>> -| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
>> -| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
>> -|                |                 |                 |                         |
>> -| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
>> +| Implementor   | Component       | Erratum ID      | Kconfig                  |
>> ++---------------+-----------------+-----------------+--------------------------+
>> +| ARM           | Cortex-A53      | #826319         | ARM64_ERRATUM_826319     |
>> +| ARM           | Cortex-A53      | #827319         | ARM64_ERRATUM_827319     |
>> +| ARM           | Cortex-A53      | #824069         | ARM64_ERRATUM_824069     |
>> +| ARM           | Cortex-A53      | #819472         | ARM64_ERRATUM_819472     |
>> +| ARM           | Cortex-A53      | #845719         | ARM64_ERRATUM_845719     |
>> +| ARM           | Cortex-A53      | #843419         | ARM64_ERRATUM_843419     |
>> +| ARM           | Cortex-A57      | #832075         | ARM64_ERRATUM_832075     |
>> +| ARM           | Cortex-A57      | #852523         | N/A                      |
>> +| ARM           | Cortex-A57      | #834220         | ARM64_ERRATUM_834220     |
>> +| ARM           | Cortex-A72      | #853709         | N/A                      |
>> +| ARM           | MMU-500         | #841119,#826419 | N/A                      |
>> +|               |                 |                 |                          |
>> +| Cavium        | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375     |
>> +| Cavium        | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144     |
>> +| Cavium        | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154     |
>> +| Cavium        | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456     |
>> +| Cavium        | ThunderX SMMUv2 | #27704          | N/A                      |
>> +|               |                 |                 |                          |
>> +| Freescale/NXP | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585      |
>> +| Qualcomm      | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003 |
> 
> Please don't change the "Implementor" column width, there is no point
> and it makes the patch harder to read (i.e. this hunk should only have
> one line).
> 
>> diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
>> index 4c63cb1..5a0a82a 100644
>> --- a/arch/arm64/mm/context.c
>> +++ b/arch/arm64/mm/context.c
>> @@ -87,6 +87,11 @@ static void flush_context(unsigned int cpu)
>>  	/* Update the list of reserved ASIDs and the ASID bitmap. */
>>  	bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
>>  
>> +	/* Reserve ASID for Falkor erratum 1003 */
>> +	if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) &&
>> +	    cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003))
>> +		__set_bit(FALKOR_RESERVED_ASID, asid_map);
>> +
>>  	/*
>>  	 * Ensure the generation bump is observed before we xchg the
>>  	 * active_asids.
>> @@ -244,6 +249,11 @@ static int asids_init(void)
>>  		panic("Failed to allocate bitmap for %lu ASIDs\n",
>>  		      NUM_USER_ASIDS);
>>  
>> +	/* Reserve ASID for Falkor erratum 1003 */
>> +	if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) &&
>> +	    cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003))
>> +		__set_bit(FALKOR_RESERVED_ASID, asid_map);
>> +
>>  	pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
>>  	return 0;
>>  }
> 
> You could as well write a small static function in this file and call it
> twice.
> 
>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
>> index 32682be..9ee46df 100644
>> --- a/arch/arm64/mm/proc.S
>> +++ b/arch/arm64/mm/proc.S
>> @@ -23,6 +23,7 @@
>>  #include <asm/assembler.h>
>>  #include <asm/asm-offsets.h>
>>  #include <asm/hwcap.h>
>> +#include <asm/mmu_context.h>
>>  #include <asm/pgtable.h>
>>  #include <asm/pgtable-hwdef.h>
>>  #include <asm/cpufeature.h>
>> @@ -140,6 +141,18 @@ ENDPROC(cpu_do_resume)
>>  ENTRY(cpu_do_switch_mm)
>>  	mmid	x1, x1				// get mm->context.id
>>  	bfi	x0, x1, #48, #16		// set the ASID
>> +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
>> +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
>> +	mrs     x2, ttbr0_el1
>> +	mov     x3, #FALKOR_RESERVED_ASID
>> +	bfi     x2, x3, #48, #16                // reserved ASID + old BADDR
>> +	msr     ttbr0_el1, x2
>> +	isb
>> +	bfi     x2, x0, #0, #48                 // reserved ASID + new BADDR
>> +	msr     ttbr0_el1, x2
>> +	isb
>> +alternative_else_nop_endif
>> +#endif
>>  	msr	ttbr0_el1, x0			// set TTBR0
>>  	isb
>>  	post_ttbr0_update_workaround
> 
> Please move the above hunk to a pre_ttbr0_update_workaround macro for
> consistency with post_ttbr0_update_workaround.

In which case (and also for consistency), should we add that pre_ttbr0
macro to entry.S, just before __uaccess_ttbr0_enable? It may not be
needed in the SW pan case, but it is probably worth entertaining the
idea that there may be something to do there...

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply

* [PATCH] PCI:MSI Return -ENOSPC when requested vectors is not enough
From: Bjorn Helgaas @ 2017-01-11 18:18 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1480558504-18691-1-git-send-email-dennis.chen@arm.com>

On Thu, Dec 01, 2016 at 10:15:04AM +0800, Dennis Chen wrote:
> The __pci_enable_msi_range() should return -ENOSPC instead of -EINVAL
> when the device doesn't have enough vectors as required, just as the 
> MSI-X vector allocator does in __pci_enable_msix_range(). Otherwise, 
> some drivers depending on that return value will probably fallback to
> the legacy interrupt directly, for example, in commit 17a51f12cfbd2814
> ("ahci: only try to use multi-MSI mode if there is more than 1 port"), the
> ahci driver will fallback to single MSI mode only when the return value
> is -ENOSPC in case of required vectors is not enough, else the driver will
> use legacy interrupt which has been observed on a x86 box with 6-port SATA
> controller.

Unless Christoph objects, I'll apply this, but I don't understand the
situation with 17a51f12cfbd.  That commit doesn't check for EINVAL or
ENOSPC so I don't know what the connection with this patch is.

I know Christoph said he changed something in ahci to treat all errors
the same, but I don't know where that is, either.

If there's a revision of Linus' tree that is broken, please give the
details so I can at least describe which versions are broken, when it
got fixed by Christoph, and figure out whether we need stable
backports or anything.

Bjorn

> With this patch, when a MSI-capable device doesn't have enough MSI
> vectors as requested, it will fallback to single MSI mode while not
> legacy interrupt.
> 
> Signed-off-by: Dennis Chen <dennis.chen@arm.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Christoph Hellwig <hch@lst.de>
> Cc: Tom Long Nguyen <tom.l.nguyen@intel.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Steve Capper <steve.capper@arm.com>
> Cc: linux-ide at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> ---
>  drivers/pci/msi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> index ad70507..da37113 100644
> --- a/drivers/pci/msi.c
> +++ b/drivers/pci/msi.c
> @@ -1084,7 +1084,7 @@ static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
>  	if (nvec < 0)
>  		return nvec;
>  	if (nvec < minvec)
> -		return -EINVAL;
> +		return -ENOSPC;
>  
>  	if (nvec > maxvec)
>  		nvec = maxvec;
> -- 
> 2.7.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* [Linux-c6x-dev] [PATCH v2 7/7] uapi: export all headers under uapi directories
From: Mark Salter @ 2017-01-11 18:14 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1483695839-18660-8-git-send-email-nicolas.dichtel@6wind.com>

On Fri, 2017-01-06 at 10:43 +0100, Nicolas Dichtel wrote:
> Regularly, when a new header is created in include/uapi/, the developer
> forgets to add it in the corresponding Kbuild file. This error is usually
> detected after the release is out.
> 
> In fact, all headers under uapi directories should be exported, thus it's
> useless to have an exhaustive list.
> 
> After this patch, the following files, which were not exported, are now
> exported (with make headers_install_all):
> asm-unicore32/shmparam.h
> asm-unicore32/ucontext.h
> asm-hexagon/shmparam.h
> asm-mips/ucontext.h
> asm-mips/hwcap.h
> asm-mips/reg.h
> drm/vgem_drm.h
> drm/armada_drm.h
> drm/omap_drm.h
> drm/etnaviv_drm.h
> asm-tile/shmparam.h
> asm-blackfin/shmparam.h
> asm-blackfin/ucontext.h
> asm-powerpc/perf_regs.h
> rdma/qedr-abi.h
> asm-parisc/kvm_para.h
> asm-openrisc/shmparam.h
> asm-nios2/kvm_para.h
> asm-nios2/ucontext.h
> asm-sh/kvm_para.h
> asm-sh/ucontext.h
> asm-xtensa/kvm_para.h
> asm-avr32/kvm_para.h
> asm-m32r/kvm_para.h
> asm-h8300/shmparam.h
> asm-h8300/ucontext.h
> asm-metag/kvm_para.h
> asm-metag/shmparam.h
> asm-metag/ucontext.h
> asm-m68k/kvm_para.h
> asm-m68k/shmparam.h
> linux/bcache.h
> linux/kvm.h
> linux/kvm_para.h
> linux/kfd_ioctl.h
> linux/cryptouser.h
> linux/kcm.h
> linux/kcov.h
> linux/seg6_iptunnel.h
> linux/stm.h
> linux/genwqe
> linux/genwqe/.install
> linux/genwqe/genwqe_card.h
> linux/genwqe/..install.cmd
> linux/seg6.h
> linux/cifs
> linux/cifs/.install
> linux/cifs/cifs_mount.h
> linux/cifs/..install.cmd
> linux/auto_dev-ioctl.h
> 
> Thanks to Julien Floret <julien.floret@6wind.com> for the tip to get all
> subdirs with a pure makefile command.
> 
> Signed-off-by: Nicolas Dichtel <nicolas.dichtel@6wind.com>
> ---
> ?Documentation/kbuild/makefiles.txt??????????|??41 ++-
> ?arch/alpha/include/uapi/asm/Kbuild??????????|??41 ---
> ?arch/arc/include/uapi/asm/Kbuild????????????|???3 -
> ?arch/arm/include/uapi/asm/Kbuild????????????|??17 -
> ?arch/arm64/include/uapi/asm/Kbuild??????????|??18 --
> ?arch/avr32/include/uapi/asm/Kbuild??????????|??20 --
> ?arch/blackfin/include/uapi/asm/Kbuild???????|??17 -
> ?arch/c6x/include/uapi/asm/Kbuild????????????|???8 -
> ?arch/cris/include/uapi/arch-v10/arch/Kbuild |???5 -
> ?arch/cris/include/uapi/arch-v32/arch/Kbuild |???3 -
> ?arch/cris/include/uapi/asm/Kbuild???????????|??43 +--
> ?arch/frv/include/uapi/asm/Kbuild????????????|??33 --
> ?arch/h8300/include/uapi/asm/Kbuild??????????|??28 --
> ?arch/hexagon/include/asm/Kbuild?????????????|???3 -
> ?arch/hexagon/include/uapi/asm/Kbuild????????|??13 -
> ?arch/ia64/include/uapi/asm/Kbuild???????????|??45 ---
> ?arch/m32r/include/uapi/asm/Kbuild???????????|??31 --
> ?arch/m68k/include/uapi/asm/Kbuild???????????|??24 --
> ?arch/metag/include/uapi/asm/Kbuild??????????|???8 -
> ?arch/microblaze/include/uapi/asm/Kbuild?????|??32 --
> ?arch/mips/include/uapi/asm/Kbuild???????????|??37 ---
> ?arch/mn10300/include/uapi/asm/Kbuild????????|??32 --
> ?arch/nios2/include/uapi/asm/Kbuild??????????|???4 +-
> ?arch/openrisc/include/asm/Kbuild????????????|???3 -
> ?arch/openrisc/include/uapi/asm/Kbuild???????|???8 -
> ?arch/parisc/include/uapi/asm/Kbuild?????????|??28 --
> ?arch/powerpc/include/uapi/asm/Kbuild????????|??45 ---
> ?arch/s390/include/uapi/asm/Kbuild???????????|??52 ---
> ?arch/score/include/asm/Kbuild???????????????|???4 -
> ?arch/score/include/uapi/asm/Kbuild??????????|??32 --
> ?arch/sh/include/uapi/asm/Kbuild?????????????|??23 --
> ?arch/sparc/include/uapi/asm/Kbuild??????????|??48 ---
> ?arch/tile/include/asm/Kbuild????????????????|???3 -
> ?arch/tile/include/uapi/arch/Kbuild??????????|??17 -
> ?arch/tile/include/uapi/asm/Kbuild???????????|??19 +-
> ?arch/unicore32/include/uapi/asm/Kbuild??????|???6 -
> ?arch/x86/include/uapi/asm/Kbuild????????????|??59 ----
> ?arch/xtensa/include/uapi/asm/Kbuild?????????|??23 --
> ?include/Kbuild??????????????????????????????|???2 -
> ?include/asm-generic/Kbuild.asm??????????????|???1 -
> ?include/scsi/fc/Kbuild??????????????????????|???0
> ?include/uapi/Kbuild?????????????????????????|??15 -
> ?include/uapi/asm-generic/Kbuild?????????????|??36 ---
> ?include/uapi/asm-generic/Kbuild.asm?????????|??62 ++--
> ?include/uapi/drm/Kbuild?????????????????????|??22 --
> ?include/uapi/linux/Kbuild???????????????????| 482 ----------------------------
> ?include/uapi/linux/android/Kbuild???????????|???2 -
> ?include/uapi/linux/byteorder/Kbuild?????????|???3 -
> ?include/uapi/linux/caif/Kbuild??????????????|???3 -
> ?include/uapi/linux/can/Kbuild???????????????|???6 -
> ?include/uapi/linux/dvb/Kbuild???????????????|???9 -
> ?include/uapi/linux/hdlc/Kbuild??????????????|???2 -
> ?include/uapi/linux/hsi/Kbuild???????????????|???2 -
> ?include/uapi/linux/iio/Kbuild???????????????|???3 -
> ?include/uapi/linux/isdn/Kbuild??????????????|???2 -
> ?include/uapi/linux/mmc/Kbuild???????????????|???2 -
> ?include/uapi/linux/netfilter/Kbuild?????????|??89 -----
> ?include/uapi/linux/netfilter/ipset/Kbuild???|???5 -
> ?include/uapi/linux/netfilter_arp/Kbuild?????|???3 -
> ?include/uapi/linux/netfilter_bridge/Kbuild??|??18 --
> ?include/uapi/linux/netfilter_ipv4/Kbuild????|??10 -
> ?include/uapi/linux/netfilter_ipv6/Kbuild????|??13 -
> ?include/uapi/linux/nfsd/Kbuild??????????????|???6 -
> ?include/uapi/linux/raid/Kbuild??????????????|???3 -
> ?include/uapi/linux/spi/Kbuild???????????????|???2 -
> ?include/uapi/linux/sunrpc/Kbuild????????????|???2 -
> ?include/uapi/linux/tc_act/Kbuild????????????|??15 -
> ?include/uapi/linux/tc_ematch/Kbuild?????????|???5 -
> ?include/uapi/linux/usb/Kbuild???????????????|??12 -
> ?include/uapi/linux/wimax/Kbuild?????????????|???2 -
> ?include/uapi/misc/Kbuild????????????????????|???2 -
> ?include/uapi/mtd/Kbuild?????????????????????|???6 -
> ?include/uapi/rdma/Kbuild????????????????????|??18 --
> ?include/uapi/rdma/hfi/Kbuild????????????????|???2 -
> ?include/uapi/scsi/Kbuild????????????????????|???6 -
> ?include/uapi/scsi/fc/Kbuild?????????????????|???5 -
> ?include/uapi/sound/Kbuild???????????????????|??16 -
> ?include/uapi/video/Kbuild???????????????????|???4 -
> ?include/uapi/xen/Kbuild?????????????????????|???5 -
> ?include/video/Kbuild????????????????????????|???0
> ?scripts/Makefile.headersinst????????????????|??39 +--
> ?81 files changed, 73 insertions(+), 1745 deletions(-)
> ?delete mode 100644 arch/cris/include/uapi/arch-v10/arch/Kbuild
> ?delete mode 100644 arch/cris/include/uapi/arch-v32/arch/Kbuild
> ?delete mode 100644 arch/tile/include/uapi/arch/Kbuild
> ?delete mode 100644 include/Kbuild
> ?delete mode 100644 include/asm-generic/Kbuild.asm
> ?delete mode 100644 include/scsi/fc/Kbuild
> ?delete mode 100644 include/uapi/Kbuild
> ?delete mode 100644 include/uapi/asm-generic/Kbuild
> ?delete mode 100644 include/uapi/drm/Kbuild
> ?delete mode 100644 include/uapi/linux/Kbuild
> ?delete mode 100644 include/uapi/linux/android/Kbuild
> ?delete mode 100644 include/uapi/linux/byteorder/Kbuild
> ?delete mode 100644 include/uapi/linux/caif/Kbuild
> ?delete mode 100644 include/uapi/linux/can/Kbuild
> ?delete mode 100644 include/uapi/linux/dvb/Kbuild
> ?delete mode 100644 include/uapi/linux/hdlc/Kbuild
> ?delete mode 100644 include/uapi/linux/hsi/Kbuild
> ?delete mode 100644 include/uapi/linux/iio/Kbuild
> ?delete mode 100644 include/uapi/linux/isdn/Kbuild
> ?delete mode 100644 include/uapi/linux/mmc/Kbuild
> ?delete mode 100644 include/uapi/linux/netfilter/Kbuild
> ?delete mode 100644 include/uapi/linux/netfilter/ipset/Kbuild
> ?delete mode 100644 include/uapi/linux/netfilter_arp/Kbuild
> ?delete mode 100644 include/uapi/linux/netfilter_bridge/Kbuild
> ?delete mode 100644 include/uapi/linux/netfilter_ipv4/Kbuild
> ?delete mode 100644 include/uapi/linux/netfilter_ipv6/Kbuild
> ?delete mode 100644 include/uapi/linux/nfsd/Kbuild
> ?delete mode 100644 include/uapi/linux/raid/Kbuild
> ?delete mode 100644 include/uapi/linux/spi/Kbuild
> ?delete mode 100644 include/uapi/linux/sunrpc/Kbuild
> ?delete mode 100644 include/uapi/linux/tc_act/Kbuild
> ?delete mode 100644 include/uapi/linux/tc_ematch/Kbuild
> ?delete mode 100644 include/uapi/linux/usb/Kbuild
> ?delete mode 100644 include/uapi/linux/wimax/Kbuild
> ?delete mode 100644 include/uapi/misc/Kbuild
> ?delete mode 100644 include/uapi/mtd/Kbuild
> ?delete mode 100644 include/uapi/rdma/Kbuild
> ?delete mode 100644 include/uapi/rdma/hfi/Kbuild
> ?delete mode 100644 include/uapi/scsi/Kbuild
> ?delete mode 100644 include/uapi/scsi/fc/Kbuild
> ?delete mode 100644 include/uapi/sound/Kbuild
> ?delete mode 100644 include/uapi/video/Kbuild
> ?delete mode 100644 include/uapi/xen/Kbuild
> ?delete mode 100644 include/video/Kbuild
> 
> diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt
> index 37b525d329ae..53e31061ff18 100644
> --- a/Documentation/kbuild/makefiles.txt
> +++ b/Documentation/kbuild/makefiles.txt
> @@ -44,7 +44,7 @@ This document describes the Linux kernel Makefiles.
> ?	???--- 6.11 Post-link pass
> ?
> ?	=== 7 Kbuild syntax for exported headers
> -		--- 7.1 header-y
> +		--- 7.1 subdir-y
> ?		--- 7.2 genhdr-y
> ?		--- 7.3 generic-y
> ?		--- 7.4 generated-y
> @@ -1235,7 +1235,7 @@ When kbuild executes, the following steps are followed (roughly):
> ?	that may be shared between individual architectures.
> ?	The recommended approach how to use a generic header file is
> ?	to list the file in the Kbuild file.
> -	See "7.4 generic-y" for further info on syntax etc.
> +	See "7.3 generic-y" for further info on syntax etc.
> ?
> ?--- 6.11 Post-link pass
> ?
> @@ -1262,37 +1262,36 @@ The pre-processing does:
> ?- drop include of compiler.h
> ?- drop all sections that are kernel internal (guarded by ifdef __KERNEL__)
> ?
> -Each relevant directory contains a file name "Kbuild" which specifies the
> -headers to be exported.
> +All headers under include/uapi/, include/generated/uapi/,
> +arch/<arch>/include/uapi/asm/ and arch/<arch>/include/generated/uapi/asm/
> +are exported.
> +
> +A Kbuild file may be defined under arch/<arch>/include/uapi/asm/ and
> +arch/<arch>/include/asm/ to list asm files coming from asm-generic.
> ?See subsequent chapter for the syntax of the Kbuild file.
> ?
> -	--- 7.1 header-y
> +	--- 7.1 subdir-y
> ?
> -	header-y specifies header files to be exported.
> +	subdir-y may be used to specify a subdirectory to be exported.
> ?
> ?		Example:
> -			#include/linux/Kbuild
> -			header-y += usb/
> -			header-y += aio_abi.h
> +			#arch/cris/include/uapi/asm/Kbuild
> +			subdir-y += ../arch-v10/arch/
> +			subdir-y += ../arch-v32/arch/
> ?
> -	The convention is to list one file per line and
> +	The convention is to list one subdir per line and
> ?	preferably in alphabetic order.
> ?
> -	header-y also specifies which subdirectories to visit.
> -	A subdirectory is identified by a trailing '/' which
> -	can be seen in the example above for the usb subdirectory.
> -
> -	Subdirectories are visited before their parent directories.
> -
> ?	--- 7.2 genhdr-y
> ?
> -	genhdr-y specifies generated files to be exported.
> -	Generated files are special as they need to be looked
> -	up in another directory when doing 'make O=...' builds.
> +	genhdr-y specifies asm files to be generated.
> ?
> ?		Example:
> -			#include/linux/Kbuild
> -			genhdr-y += version.h
> +			#arch/x86/include/uapi/asm/Kbuild
> +			genhdr-y += unistd_32.h
> +			genhdr-y += unistd_64.h
> +			genhdr-y += unistd_x32.h
> +
> ?
> ?	--- 7.3 generic-y
> ?
> diff --git a/arch/alpha/include/uapi/asm/Kbuild b/arch/alpha/include/uapi/asm/Kbuild
> index d96f2ef5b639..b15bf6bc0e94 100644
> --- a/arch/alpha/include/uapi/asm/Kbuild
> +++ b/arch/alpha/include/uapi/asm/Kbuild
> @@ -1,43 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += a.out.h
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += compiler.h
> -header-y += console.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += fpu.h
> -header-y += gentrap.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += pal.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += reg.h
> -header-y += regdef.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += sysinfo.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/arc/include/uapi/asm/Kbuild b/arch/arc/include/uapi/asm/Kbuild
> index f50d02df78d5..b15bf6bc0e94 100644
> --- a/arch/arc/include/uapi/asm/Kbuild
> +++ b/arch/arc/include/uapi/asm/Kbuild
> @@ -1,5 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -header-y += elf.h
> -header-y += page.h
> -header-y += cachectl.h
> diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild
> index 46a76cd6acb6..607f702c2d62 100644
> --- a/arch/arm/include/uapi/asm/Kbuild
> +++ b/arch/arm/include/uapi/asm/Kbuild
> @@ -1,23 +1,6 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> -header-y += auxvec.h
> -header-y += byteorder.h
> -header-y += fcntl.h
> -header-y += hwcap.h
> -header-y += ioctls.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += perf_regs.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += setup.h
> -header-y += sigcontext.h
> -header-y += signal.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += unistd.h
> ?genhdr-y += unistd-common.h
> ?genhdr-y += unistd-oabi.h
> ?genhdr-y += unistd-eabi.h
> diff --git a/arch/arm64/include/uapi/asm/Kbuild b/arch/arm64/include/uapi/asm/Kbuild
> index 825b0fe51c2b..13a97aa2285f 100644
> --- a/arch/arm64/include/uapi/asm/Kbuild
> +++ b/arch/arm64/include/uapi/asm/Kbuild
> @@ -2,21 +2,3 @@
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> ?generic-y += kvm_para.h
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += fcntl.h
> -header-y += hwcap.h
> -header-y += kvm_para.h
> -header-y += perf_regs.h
> -header-y += param.h
> -header-y += ptrace.h
> -header-y += setup.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += ucontext.h
> -header-y += unistd.h
> diff --git a/arch/avr32/include/uapi/asm/Kbuild b/arch/avr32/include/uapi/asm/Kbuild
> index 08d8a3d76ea8..610395083364 100644
> --- a/arch/avr32/include/uapi/asm/Kbuild
> +++ b/arch/avr32/include/uapi/asm/Kbuild
> @@ -1,26 +1,6 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> -header-y += auxvec.h
> -header-y += byteorder.h
> -header-y += cachectl.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> ?generic-y += bitsperlong.h
> ?generic-y += errno.h
> ?generic-y += fcntl.h
> diff --git a/arch/blackfin/include/uapi/asm/Kbuild b/arch/blackfin/include/uapi/asm/Kbuild
> index 0bd28f77abc3..b15bf6bc0e94 100644
> --- a/arch/blackfin/include/uapi/asm/Kbuild
> +++ b/arch/blackfin/include/uapi/asm/Kbuild
> @@ -1,19 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += bfin_sport.h
> -header-y += byteorder.h
> -header-y += cachectl.h
> -header-y += fcntl.h
> -header-y += fixed_code.h
> -header-y += ioctls.h
> -header-y += kvm_para.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += stat.h
> -header-y += swab.h
> -header-y += unistd.h
> diff --git a/arch/c6x/include/uapi/asm/Kbuild b/arch/c6x/include/uapi/asm/Kbuild
> index e9bc2b2b8147..13a97aa2285f 100644
> --- a/arch/c6x/include/uapi/asm/Kbuild
> +++ b/arch/c6x/include/uapi/asm/Kbuild
> @@ -2,11 +2,3 @@
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> ?generic-y += kvm_para.h
> -
> -header-y += byteorder.h
> -header-y += kvm_para.h
> -header-y += ptrace.h
> -header-y += setup.h
> -header-y += sigcontext.h
> -header-y += swab.h
> -header-y += unistd.h

Acked-by: Mark Salter <msalter@redhat.com>

> diff --git a/arch/cris/include/uapi/arch-v10/arch/Kbuild b/arch/cris/include/uapi/arch-v10/arch/Kbuild
> deleted file mode 100644
> index 9048c87a782b..000000000000
> --- a/arch/cris/include/uapi/arch-v10/arch/Kbuild
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -# UAPI Header export list
> -header-y += sv_addr.agh
> -header-y += sv_addr_ag.h
> -header-y += svinto.h
> -header-y += user.h
> diff --git a/arch/cris/include/uapi/arch-v32/arch/Kbuild b/arch/cris/include/uapi/arch-v32/arch/Kbuild
> deleted file mode 100644
> index 59efffd16b61..000000000000
> --- a/arch/cris/include/uapi/arch-v32/arch/Kbuild
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -# UAPI Header export list
> -header-y += cryptocop.h
> -header-y += user.h
> diff --git a/arch/cris/include/uapi/asm/Kbuild b/arch/cris/include/uapi/asm/Kbuild
> index d5564a0ae66a..d0c5471856e0 100644
> --- a/arch/cris/include/uapi/asm/Kbuild
> +++ b/arch/cris/include/uapi/asm/Kbuild
> @@ -1,44 +1,5 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> -header-y += ../arch-v10/arch/
> -header-y += ../arch-v32/arch/
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += elf.h
> -header-y += elf_v10.h
> -header-y += elf_v32.h
> -header-y += errno.h
> -header-y += ethernet.h
> -header-y += etraxgpio.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += ptrace_v10.h
> -header-y += ptrace_v32.h
> -header-y += resource.h
> -header-y += rs485.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += sync_serial.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> +subdir-y += ../arch-v10/arch/
> +subdir-y += ../arch-v32/arch/
> diff --git a/arch/frv/include/uapi/asm/Kbuild b/arch/frv/include/uapi/asm/Kbuild
> index 42a2b33461c0..b15bf6bc0e94 100644
> --- a/arch/frv/include/uapi/asm/Kbuild
> +++ b/arch/frv/include/uapi/asm/Kbuild
> @@ -1,35 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += registers.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/h8300/include/uapi/asm/Kbuild b/arch/h8300/include/uapi/asm/Kbuild
> index fb6101a5d4f1..b15bf6bc0e94 100644
> --- a/arch/h8300/include/uapi/asm/Kbuild
> +++ b/arch/h8300/include/uapi/asm/Kbuild
> @@ -1,30 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += siginfo.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/hexagon/include/asm/Kbuild b/arch/hexagon/include/asm/Kbuild
> index db8ddabc6bd2..f3b1ceb5c1e4 100644
> --- a/arch/hexagon/include/asm/Kbuild
> +++ b/arch/hexagon/include/asm/Kbuild
> @@ -1,6 +1,3 @@
> -
> -header-y += ucontext.h
> -
> ?generic-y += auxvec.h
> ?generic-y += barrier.h
> ?generic-y += bug.h
> diff --git a/arch/hexagon/include/uapi/asm/Kbuild b/arch/hexagon/include/uapi/asm/Kbuild
> index c31706c38631..b15bf6bc0e94 100644
> --- a/arch/hexagon/include/uapi/asm/Kbuild
> +++ b/arch/hexagon/include/uapi/asm/Kbuild
> @@ -1,15 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += kvm_para.h
> -header-y += param.h
> -header-y += ptrace.h
> -header-y += registers.h
> -header-y += setup.h
> -header-y += sigcontext.h
> -header-y += signal.h
> -header-y += swab.h
> -header-y += unistd.h
> -header-y += user.h
> diff --git a/arch/ia64/include/uapi/asm/Kbuild b/arch/ia64/include/uapi/asm/Kbuild
> index 891002bbb995..13a97aa2285f 100644
> --- a/arch/ia64/include/uapi/asm/Kbuild
> +++ b/arch/ia64/include/uapi/asm/Kbuild
> @@ -2,48 +2,3 @@
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> ?generic-y += kvm_para.h
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += break.h
> -header-y += byteorder.h
> -header-y += cmpxchg.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += fpu.h
> -header-y += gcc_intrin.h
> -header-y += ia64regs.h
> -header-y += intel_intrin.h
> -header-y += intrinsics.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += perfmon.h
> -header-y += perfmon_default_smpl.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += ptrace_offsets.h
> -header-y += resource.h
> -header-y += rse.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += ucontext.h
> -header-y += unistd.h
> -header-y += ustack.h
> diff --git a/arch/m32r/include/uapi/asm/Kbuild b/arch/m32r/include/uapi/asm/Kbuild
> index 43937a61d6cf..b15bf6bc0e94 100644
> --- a/arch/m32r/include/uapi/asm/Kbuild
> +++ b/arch/m32r/include/uapi/asm/Kbuild
> @@ -1,33 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/m68k/include/uapi/asm/Kbuild b/arch/m68k/include/uapi/asm/Kbuild
> index 6a2d257bdfb2..64368077235a 100644
> --- a/arch/m68k/include/uapi/asm/Kbuild
> +++ b/arch/m68k/include/uapi/asm/Kbuild
> @@ -9,27 +9,3 @@ generic-y += socket.h
> ?generic-y += sockios.h
> ?generic-y += termbits.h
> ?generic-y += termios.h
> -
> -header-y += a.out.h
> -header-y += bootinfo.h
> -header-y += bootinfo-amiga.h
> -header-y += bootinfo-apollo.h
> -header-y += bootinfo-atari.h
> -header-y += bootinfo-hp300.h
> -header-y += bootinfo-mac.h
> -header-y += bootinfo-q40.h
> -header-y += bootinfo-vme.h
> -header-y += byteorder.h
> -header-y += cachectl.h
> -header-y += fcntl.h
> -header-y += ioctls.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += setup.h
> -header-y += sigcontext.h
> -header-y += signal.h
> -header-y += stat.h
> -header-y += swab.h
> -header-y += unistd.h
> diff --git a/arch/metag/include/uapi/asm/Kbuild b/arch/metag/include/uapi/asm/Kbuild
> index ab78be2b6eb0..b29731ebd7a9 100644
> --- a/arch/metag/include/uapi/asm/Kbuild
> +++ b/arch/metag/include/uapi/asm/Kbuild
> @@ -1,14 +1,6 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> -header-y += byteorder.h
> -header-y += ech.h
> -header-y += ptrace.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += swab.h
> -header-y += unistd.h
> -
> ?generic-y += mman.h
> ?generic-y += resource.h
> ?generic-y += setup.h
> diff --git a/arch/microblaze/include/uapi/asm/Kbuild b/arch/microblaze/include/uapi/asm/Kbuild
> index 1aac99f87df1..2178c78c7c1a 100644
> --- a/arch/microblaze/include/uapi/asm/Kbuild
> +++ b/arch/microblaze/include/uapi/asm/Kbuild
> @@ -2,35 +2,3 @@
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> ?generic-y += types.h
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += elf.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += unistd.h
> diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild
> index f2cf41461146..a0266feba9e6 100644
> --- a/arch/mips/include/uapi/asm/Kbuild
> +++ b/arch/mips/include/uapi/asm/Kbuild
> @@ -2,40 +2,3 @@
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> ?generic-y += ipcbuf.h
> -
> -header-y += auxvec.h
> -header-y += bitfield.h
> -header-y += bitsperlong.h
> -header-y += break.h
> -header-y += byteorder.h
> -header-y += cachectl.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += inst.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += sgidefs.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += sysmips.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/mn10300/include/uapi/asm/Kbuild b/arch/mn10300/include/uapi/asm/Kbuild
> index 040178cdb3eb..b15bf6bc0e94 100644
> --- a/arch/mn10300/include/uapi/asm/Kbuild
> +++ b/arch/mn10300/include/uapi/asm/Kbuild
> @@ -1,34 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/nios2/include/uapi/asm/Kbuild b/arch/nios2/include/uapi/asm/Kbuild
> index e0bb972a50d7..766455d0d291 100644
> --- a/arch/nios2/include/uapi/asm/Kbuild
> +++ b/arch/nios2/include/uapi/asm/Kbuild
> @@ -1,5 +1,3 @@
> +# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += elf.h
> -
> ?generic-y += ucontext.h
> diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
> index 2832f031fb11..561915716fd9 100644
> --- a/arch/openrisc/include/asm/Kbuild
> +++ b/arch/openrisc/include/asm/Kbuild
> @@ -1,6 +1,3 @@
> -
> -header-y += ucontext.h
> -
> ?generic-y += atomic.h
> ?generic-y += auxvec.h
> ?generic-y += barrier.h
> diff --git a/arch/openrisc/include/uapi/asm/Kbuild b/arch/openrisc/include/uapi/asm/Kbuild
> index 80761eb82b5f..b15bf6bc0e94 100644
> --- a/arch/openrisc/include/uapi/asm/Kbuild
> +++ b/arch/openrisc/include/uapi/asm/Kbuild
> @@ -1,10 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += byteorder.h
> -header-y += elf.h
> -header-y += kvm_para.h
> -header-y += param.h
> -header-y += ptrace.h
> -header-y += sigcontext.h
> -header-y += unistd.h
> diff --git a/arch/parisc/include/uapi/asm/Kbuild b/arch/parisc/include/uapi/asm/Kbuild
> index 348356c99514..3971c60a7e7f 100644
> --- a/arch/parisc/include/uapi/asm/Kbuild
> +++ b/arch/parisc/include/uapi/asm/Kbuild
> @@ -2,31 +2,3 @@
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> ?generic-y += resource.h
> -
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += pdc.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/powerpc/include/uapi/asm/Kbuild b/arch/powerpc/include/uapi/asm/Kbuild
> index dab3717e3ea0..b15bf6bc0e94 100644
> --- a/arch/powerpc/include/uapi/asm/Kbuild
> +++ b/arch/powerpc/include/uapi/asm/Kbuild
> @@ -1,47 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += bootx.h
> -header-y += byteorder.h
> -header-y += cputable.h
> -header-y += eeh.h
> -header-y += elf.h
> -header-y += epapr_hcalls.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += nvram.h
> -header-y += opal-prd.h
> -header-y += param.h
> -header-y += perf_event.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ps3fb.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += spu_info.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += tm.h
> -header-y += types.h
> -header-y += ucontext.h
> -header-y += unistd.h
> diff --git a/arch/s390/include/uapi/asm/Kbuild b/arch/s390/include/uapi/asm/Kbuild
> index bf736e764cb4..b15bf6bc0e94 100644
> --- a/arch/s390/include/uapi/asm/Kbuild
> +++ b/arch/s390/include/uapi/asm/Kbuild
> @@ -1,54 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += chpid.h
> -header-y += chsc.h
> -header-y += clp.h
> -header-y += cmb.h
> -header-y += dasd.h
> -header-y += debug.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += hypfs.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm.h
> -header-y += kvm_para.h
> -header-y += kvm_perf.h
> -header-y += kvm_virtio.h
> -header-y += mman.h
> -header-y += monwriter.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += qeth.h
> -header-y += resource.h
> -header-y += schid.h
> -header-y += sclp_ctl.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sie.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += tape390.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += ucontext.h
> -header-y += unistd.h
> -header-y += virtio-ccw.h
> -header-y += vtoc.h
> -header-y += zcrypt.h
> diff --git a/arch/score/include/asm/Kbuild b/arch/score/include/asm/Kbuild
> index a05218ff3fe4..128ca7ec0220 100644
> --- a/arch/score/include/asm/Kbuild
> +++ b/arch/score/include/asm/Kbuild
> @@ -1,7 +1,3 @@
> -
> -header-y +=
> -
> -
> ?generic-y += barrier.h
> ?generic-y += clkdev.h
> ?generic-y += cputime.h
> diff --git a/arch/score/include/uapi/asm/Kbuild b/arch/score/include/uapi/asm/Kbuild
> index 040178cdb3eb..b15bf6bc0e94 100644
> --- a/arch/score/include/uapi/asm/Kbuild
> +++ b/arch/score/include/uapi/asm/Kbuild
> @@ -1,34 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/arch/sh/include/uapi/asm/Kbuild b/arch/sh/include/uapi/asm/Kbuild
> index 60613ae78513..b15bf6bc0e94 100644
> --- a/arch/sh/include/uapi/asm/Kbuild
> +++ b/arch/sh/include/uapi/asm/Kbuild
> @@ -1,25 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += byteorder.h
> -header-y += cachectl.h
> -header-y += cpu-features.h
> -header-y += hw_breakpoint.h
> -header-y += ioctls.h
> -header-y += posix_types.h
> -header-y += posix_types_32.h
> -header-y += posix_types_64.h
> -header-y += ptrace.h
> -header-y += ptrace_32.h
> -header-y += ptrace_64.h
> -header-y += setup.h
> -header-y += sigcontext.h
> -header-y += signal.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += swab.h
> -header-y += types.h
> -header-y += unistd.h
> -header-y += unistd_32.h
> -header-y += unistd_64.h
> diff --git a/arch/sparc/include/uapi/asm/Kbuild b/arch/sparc/include/uapi/asm/Kbuild
> index b5843ee09fb5..b15bf6bc0e94 100644
> --- a/arch/sparc/include/uapi/asm/Kbuild
> +++ b/arch/sparc/include/uapi/asm/Kbuild
> @@ -1,50 +1,2 @@
> ?# UAPI Header export list
> -# User exported sparc header files
> -
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += apc.h
> -header-y += asi.h
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += display7seg.h
> -header-y += envctrl.h
> -header-y += errno.h
> -header-y += fbio.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += jsflash.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += openpromio.h
> -header-y += param.h
> -header-y += perfctr.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += psr.h
> -header-y += psrcompat.h
> -header-y += pstate.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += traps.h
> -header-y += uctx.h
> -header-y += unistd.h
> -header-y += utrap.h
> -header-y += watchdog.h
> diff --git a/arch/tile/include/asm/Kbuild b/arch/tile/include/asm/Kbuild
> index 2d1f5638974c..057eaa533877 100644
> --- a/arch/tile/include/asm/Kbuild
> +++ b/arch/tile/include/asm/Kbuild
> @@ -1,6 +1,3 @@
> -
> -header-y += ../arch/
> -
> ?generic-y += bug.h
> ?generic-y += bugs.h
> ?generic-y += clkdev.h
> diff --git a/arch/tile/include/uapi/arch/Kbuild b/arch/tile/include/uapi/arch/Kbuild
> deleted file mode 100644
> index 97dfbecec6b6..000000000000
> --- a/arch/tile/include/uapi/arch/Kbuild
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -# UAPI Header export list
> -header-y += abi.h
> -header-y += chip.h
> -header-y += chip_tilegx.h
> -header-y += chip_tilepro.h
> -header-y += icache.h
> -header-y += interrupts.h
> -header-y += interrupts_32.h
> -header-y += interrupts_64.h
> -header-y += opcode.h
> -header-y += opcode_tilegx.h
> -header-y += opcode_tilepro.h
> -header-y += sim.h
> -header-y += sim_def.h
> -header-y += spr_def.h
> -header-y += spr_def_32.h
> -header-y += spr_def_64.h
> diff --git a/arch/tile/include/uapi/asm/Kbuild b/arch/tile/include/uapi/asm/Kbuild
> index c20db8e428bf..e0a50111e07f 100644
> --- a/arch/tile/include/uapi/asm/Kbuild
> +++ b/arch/tile/include/uapi/asm/Kbuild
> @@ -1,21 +1,6 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += cachectl.h
> -header-y += hardwall.h
> -header-y += kvm_para.h
> -header-y += mman.h
> -header-y += ptrace.h
> -header-y += setup.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += stat.h
> -header-y += swab.h
> -header-y += ucontext.h
> -header-y += unistd.h
> -
> ?generic-y += ucontext.h
> +
> +subdir-y += ../arch
> diff --git a/arch/unicore32/include/uapi/asm/Kbuild b/arch/unicore32/include/uapi/asm/Kbuild
> index 0514d7ad6855..13a97aa2285f 100644
> --- a/arch/unicore32/include/uapi/asm/Kbuild
> +++ b/arch/unicore32/include/uapi/asm/Kbuild
> @@ -1,10 +1,4 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> ?
> -header-y += byteorder.h
> -header-y += kvm_para.h
> -header-y += ptrace.h
> -header-y += sigcontext.h
> -header-y += unistd.h
> -
> ?generic-y += kvm_para.h
> diff --git a/arch/x86/include/uapi/asm/Kbuild b/arch/x86/include/uapi/asm/Kbuild
> index 3dec769cadf7..83b6e9a0dce4 100644
> --- a/arch/x86/include/uapi/asm/Kbuild
> +++ b/arch/x86/include/uapi/asm/Kbuild
> @@ -4,62 +4,3 @@ include include/uapi/asm-generic/Kbuild.asm
> ?genhdr-y += unistd_32.h
> ?genhdr-y += unistd_64.h
> ?genhdr-y += unistd_x32.h
> -header-y += a.out.h
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += boot.h
> -header-y += bootparam.h
> -header-y += byteorder.h
> -header-y += debugreg.h
> -header-y += e820.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += hw_breakpoint.h
> -header-y += hyperv.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += ist.h
> -header-y += kvm.h
> -header-y += kvm_para.h
> -header-y += kvm_perf.h
> -header-y += ldt.h
> -header-y += mce.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += msr-index.h
> -header-y += msr.h
> -header-y += mtrr.h
> -header-y += param.h
> -header-y += perf_regs.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += posix_types_32.h
> -header-y += posix_types_64.h
> -header-y += posix_types_x32.h
> -header-y += prctl.h
> -header-y += processor-flags.h
> -header-y += ptrace-abi.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += sigcontext32.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += svm.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += ucontext.h
> -header-y += unistd.h
> -header-y += vm86.h
> -header-y += vmx.h
> -header-y += vsyscall.h
> diff --git a/arch/xtensa/include/uapi/asm/Kbuild b/arch/xtensa/include/uapi/asm/Kbuild
> index 56aad54e7fb7..b15bf6bc0e94 100644
> --- a/arch/xtensa/include/uapi/asm/Kbuild
> +++ b/arch/xtensa/include/uapi/asm/Kbuild
> @@ -1,25 +1,2 @@
> ?# UAPI Header export list
> ?include include/uapi/asm-generic/Kbuild.asm
> -
> -header-y += auxvec.h
> -header-y += byteorder.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += types.h
> -header-y += unistd.h
> diff --git a/include/Kbuild b/include/Kbuild
> deleted file mode 100644
> index bab1145bc7a7..000000000000
> --- a/include/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# Top-level Makefile calls into asm-$(ARCH)
> -# List only non-arch directories below
> diff --git a/include/asm-generic/Kbuild.asm b/include/asm-generic/Kbuild.asm
> deleted file mode 100644
> index d2ee86b4c091..000000000000
> --- a/include/asm-generic/Kbuild.asm
> +++ /dev/null
> @@ -1 +0,0 @@
> -include include/uapi/asm-generic/Kbuild.asm
> diff --git a/include/scsi/fc/Kbuild b/include/scsi/fc/Kbuild
> deleted file mode 100644
> index e69de29bb2d1..000000000000
> diff --git a/include/uapi/Kbuild b/include/uapi/Kbuild
> deleted file mode 100644
> index 245aa6e05e6a..000000000000
> --- a/include/uapi/Kbuild
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -# UAPI Header export list
> -# Top-level Makefile calls into asm-$(ARCH)
> -# List only non-arch directories below
> -
> -
> -header-y += asm-generic/
> -header-y += linux/
> -header-y += sound/
> -header-y += mtd/
> -header-y += rdma/
> -header-y += video/
> -header-y += drm/
> -header-y += xen/
> -header-y += scsi/
> -header-y += misc/
> diff --git a/include/uapi/asm-generic/Kbuild b/include/uapi/asm-generic/Kbuild
> deleted file mode 100644
> index b73de7bb7a62..000000000000
> --- a/include/uapi/asm-generic/Kbuild
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -# UAPI Header export list
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += errno-base.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += int-l64.h
> -header-y += int-ll64.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += kvm_para.h
> -header-y += mman-common.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += shmparam.h
> -header-y += siginfo.h
> -header-y += signal-defs.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += ucontext.h
> -header-y += unistd.h
> diff --git a/include/uapi/asm-generic/Kbuild.asm b/include/uapi/asm-generic/Kbuild.asm
> index fcd50b759217..c13805d5a2a0 100644
> --- a/include/uapi/asm-generic/Kbuild.asm
> +++ b/include/uapi/asm-generic/Kbuild.asm
> @@ -8,38 +8,38 @@ opt-header += a.out.h
> ?#
> ?# Headers that are mandatory in usr/include/asm/
> ?#
> -header-y += auxvec.h
> -header-y += bitsperlong.h
> -header-y += byteorder.h
> -header-y += errno.h
> -header-y += fcntl.h
> -header-y += ioctl.h
> -header-y += ioctls.h
> -header-y += ipcbuf.h
> -header-y += mman.h
> -header-y += msgbuf.h
> -header-y += param.h
> -header-y += poll.h
> -header-y += posix_types.h
> -header-y += ptrace.h
> -header-y += resource.h
> -header-y += sembuf.h
> -header-y += setup.h
> -header-y += shmbuf.h
> -header-y += sigcontext.h
> -header-y += siginfo.h
> -header-y += signal.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += stat.h
> -header-y += statfs.h
> -header-y += swab.h
> -header-y += termbits.h
> -header-y += termios.h
> -header-y += types.h
> -header-y += unistd.h
> +generic-y += auxvec.h
> +generic-y += bitsperlong.h
> +generic-y += byteorder.h
> +generic-y += errno.h
> +generic-y += fcntl.h
> +generic-y += ioctl.h
> +generic-y += ioctls.h
> +generic-y += ipcbuf.h
> +generic-y += mman.h
> +generic-y += msgbuf.h
> +generic-y += param.h
> +generic-y += poll.h
> +generic-y += posix_types.h
> +generic-y += ptrace.h
> +generic-y += resource.h
> +generic-y += sembuf.h
> +generic-y += setup.h
> +generic-y += shmbuf.h
> +generic-y += sigcontext.h
> +generic-y += siginfo.h
> +generic-y += signal.h
> +generic-y += socket.h
> +generic-y += sockios.h
> +generic-y += stat.h
> +generic-y += statfs.h
> +generic-y += swab.h
> +generic-y += termbits.h
> +generic-y += termios.h
> +generic-y += types.h
> +generic-y += unistd.h
> ?
> -header-y += $(foreach hdr,$(opt-header), \
> +generic-y += $(foreach hdr,$(opt-header), \
> ?	??????$(if \
> ?		$(wildcard \
> ?			$(srctree)/arch/$(SRCARCH)/include/uapi/asm/$(hdr) \
> diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild
> deleted file mode 100644
> index 9355dd8eff3b..000000000000
> --- a/include/uapi/drm/Kbuild
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -# UAPI Header export list
> -header-y += drm.h
> -header-y += drm_fourcc.h
> -header-y += drm_mode.h
> -header-y += drm_sarea.h
> -header-y += amdgpu_drm.h
> -header-y += exynos_drm.h
> -header-y += i810_drm.h
> -header-y += i915_drm.h
> -header-y += mga_drm.h
> -header-y += nouveau_drm.h
> -header-y += qxl_drm.h
> -header-y += r128_drm.h
> -header-y += radeon_drm.h
> -header-y += savage_drm.h
> -header-y += sis_drm.h
> -header-y += tegra_drm.h
> -header-y += via_drm.h
> -header-y += vmwgfx_drm.h
> -header-y += msm_drm.h
> -header-y += vc4_drm.h
> -header-y += virtgpu_drm.h
> diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
> deleted file mode 100644
> index a8b93e685239..000000000000
> --- a/include/uapi/linux/Kbuild
> +++ /dev/null
> @@ -1,482 +0,0 @@
> -# UAPI Header export list
> -header-y += android/
> -header-y += byteorder/
> -header-y += can/
> -header-y += caif/
> -header-y += dvb/
> -header-y += hdlc/
> -header-y += hsi/
> -header-y += iio/
> -header-y += isdn/
> -header-y += mmc/
> -header-y += nfsd/
> -header-y += raid/
> -header-y += spi/
> -header-y += sunrpc/
> -header-y += tc_act/
> -header-y += tc_ematch/
> -header-y += netfilter/
> -header-y += netfilter_arp/
> -header-y += netfilter_bridge/
> -header-y += netfilter_ipv4/
> -header-y += netfilter_ipv6/
> -header-y += usb/
> -header-y += wimax/
> -
> -genhdr-y += version.h
> -
> -ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/a.out.h \
> -		??$(srctree)/arch/$(SRCARCH)/include/asm/a.out.h),)
> -header-y += a.out.h
> -endif
> -
> -header-y += acct.h
> -header-y += adb.h
> -header-y += adfs_fs.h
> -header-y += affs_hardblocks.h
> -header-y += agpgart.h
> -header-y += aio_abi.h
> -header-y += am437x-vpfe.h
> -header-y += apm_bios.h
> -header-y += arcfb.h
> -header-y += atalk.h
> -header-y += atmapi.h
> -header-y += atmarp.h
> -header-y += atmbr2684.h
> -header-y += atmclip.h
> -header-y += atmdev.h
> -header-y += atm_eni.h
> -header-y += atm.h
> -header-y += atm_he.h
> -header-y += atm_idt77105.h
> -header-y += atmioc.h
> -header-y += atmlec.h
> -header-y += atmmpc.h
> -header-y += atm_nicstar.h
> -header-y += atmppp.h
> -header-y += atmsap.h
> -header-y += atmsvc.h
> -header-y += atm_tcp.h
> -header-y += atm_zatm.h
> -header-y += audit.h
> -header-y += auto_fs4.h
> -header-y += auto_fs.h
> -header-y += auxvec.h
> -header-y += ax25.h
> -header-y += b1lli.h
> -header-y += baycom.h
> -header-y += bcm933xx_hcs.h
> -header-y += bfs_fs.h
> -header-y += binfmts.h
> -header-y += blkpg.h
> -header-y += blktrace_api.h
> -header-y += blkzoned.h
> -header-y += bpf_common.h
> -header-y += bpf_perf_event.h
> -header-y += bpf.h
> -header-y += bpqether.h
> -header-y += bsg.h
> -header-y += bt-bmc.h
> -header-y += btrfs.h
> -header-y += can.h
> -header-y += capability.h
> -header-y += capi.h
> -header-y += cciss_defs.h
> -header-y += cciss_ioctl.h
> -header-y += cdrom.h
> -header-y += cec.h
> -header-y += cec-funcs.h
> -header-y += cgroupstats.h
> -header-y += chio.h
> -header-y += cm4000_cs.h
> -header-y += cn_proc.h
> -header-y += coda.h
> -header-y += coda_psdev.h
> -header-y += coff.h
> -header-y += connector.h
> -header-y += const.h
> -header-y += cramfs_fs.h
> -header-y += cuda.h
> -header-y += cyclades.h
> -header-y += cycx_cfm.h
> -header-y += dcbnl.h
> -header-y += dccp.h
> -header-y += devlink.h
> -header-y += dlmconstants.h
> -header-y += dlm_device.h
> -header-y += dlm.h
> -header-y += dlm_netlink.h
> -header-y += dlm_plock.h
> -header-y += dm-ioctl.h
> -header-y += dm-log-userspace.h
> -header-y += dn.h
> -header-y += dqblk_xfs.h
> -header-y += edd.h
> -header-y += efs_fs_sb.h
> -header-y += elfcore.h
> -header-y += elf-em.h
> -header-y += elf-fdpic.h
> -header-y += elf.h
> -header-y += errno.h
> -header-y += errqueue.h
> -header-y += ethtool.h
> -header-y += eventpoll.h
> -header-y += fadvise.h
> -header-y += falloc.h
> -header-y += fanotify.h
> -header-y += fb.h
> -header-y += fcntl.h
> -header-y += fd.h
> -header-y += fdreg.h
> -header-y += fib_rules.h
> -header-y += fiemap.h
> -header-y += filter.h
> -header-y += firewire-cdev.h
> -header-y += firewire-constants.h
> -header-y += flat.h
> -header-y += fou.h
> -header-y += fs.h
> -header-y += fsl_hypervisor.h
> -header-y += fuse.h
> -header-y += futex.h
> -header-y += gameport.h
> -header-y += genetlink.h
> -header-y += gen_stats.h
> -header-y += gfs2_ondisk.h
> -header-y += gigaset_dev.h
> -header-y += gpio.h
> -header-y += gsmmux.h
> -header-y += gtp.h
> -header-y += hdlcdrv.h
> -header-y += hdlc.h
> -header-y += hdreg.h
> -header-y += hiddev.h
> -header-y += hid.h
> -header-y += hidraw.h
> -header-y += hpet.h
> -header-y += hsr_netlink.h
> -header-y += hyperv.h
> -header-y += hysdn_if.h
> -header-y += i2c-dev.h
> -header-y += i2c.h
> -header-y += i2o-dev.h
> -header-y += i8k.h
> -header-y += icmp.h
> -header-y += icmpv6.h
> -header-y += if_addr.h
> -header-y += if_addrlabel.h
> -header-y += if_alg.h
> -header-y += if_arcnet.h
> -header-y += if_arp.h
> -header-y += if_bonding.h
> -header-y += if_bridge.h
> -header-y += if_cablemodem.h
> -header-y += if_eql.h
> -header-y += if_ether.h
> -header-y += if_fc.h
> -header-y += if_fddi.h
> -header-y += if_frad.h
> -header-y += if.h
> -header-y += if_hippi.h
> -header-y += if_infiniband.h
> -header-y += if_link.h
> -header-y += if_ltalk.h
> -header-y += if_macsec.h
> -header-y += if_packet.h
> -header-y += if_phonet.h
> -header-y += if_plip.h
> -header-y += if_ppp.h
> -header-y += if_pppol2tp.h
> -header-y += if_pppox.h
> -header-y += if_slip.h
> -header-y += if_team.h
> -header-y += if_tun.h
> -header-y += if_tunnel.h
> -header-y += if_vlan.h
> -header-y += if_x25.h
> -header-y += igmp.h
> -header-y += ila.h
> -header-y += in6.h
> -header-y += inet_diag.h
> -header-y += in.h
> -header-y += inotify.h
> -header-y += input.h
> -header-y += input-event-codes.h
> -header-y += in_route.h
> -header-y += ioctl.h
> -header-y += ip6_tunnel.h
> -header-y += ipc.h
> -header-y += ip.h
> -header-y += ipmi.h
> -header-y += ipmi_msgdefs.h
> -header-y += ipsec.h
> -header-y += ipv6.h
> -header-y += ipv6_route.h
> -header-y += ip_vs.h
> -header-y += ipx.h
> -header-y += irda.h
> -header-y += irqnr.h
> -header-y += isdn_divertif.h
> -header-y += isdn.h
> -header-y += isdnif.h
> -header-y += isdn_ppp.h
> -header-y += iso_fs.h
> -header-y += ivtvfb.h
> -header-y += ivtv.h
> -header-y += ixjuser.h
> -header-y += jffs2.h
> -header-y += joystick.h
> -header-y += kcmp.h
> -header-y += kdev_t.h
> -header-y += kd.h
> -header-y += kernelcapi.h
> -header-y += kernel.h
> -header-y += kernel-page-flags.h
> -header-y += kexec.h
> -header-y += keyboard.h
> -header-y += keyctl.h
> -
> -ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/kvm.h \
> -		??$(srctree)/arch/$(SRCARCH)/include/asm/kvm.h),)
> -header-y += kvm.h
> -endif
> -
> -
> -ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/kvm_para.h \
> -		??$(srctree)/arch/$(SRCARCH)/include/asm/kvm_para.h),)
> -header-y += kvm_para.h
> -endif
> -
> -header-y += hw_breakpoint.h
> -header-y += l2tp.h
> -header-y += libc-compat.h
> -header-y += lirc.h
> -header-y += limits.h
> -header-y += llc.h
> -header-y += loop.h
> -header-y += lp.h
> -header-y += lwtunnel.h
> -header-y += magic.h
> -header-y += major.h
> -header-y += map_to_7segment.h
> -header-y += matroxfb.h
> -header-y += mdio.h
> -header-y += media.h
> -header-y += media-bus-format.h
> -header-y += mei.h
> -header-y += membarrier.h
> -header-y += memfd.h
> -header-y += mempolicy.h
> -header-y += meye.h
> -header-y += mic_common.h
> -header-y += mic_ioctl.h
> -header-y += mii.h
> -header-y += minix_fs.h
> -header-y += mman.h
> -header-y += mmtimer.h
> -header-y += mpls.h
> -header-y += mpls_iptunnel.h
> -header-y += mqueue.h
> -header-y += mroute6.h
> -header-y += mroute.h
> -header-y += msdos_fs.h
> -header-y += msg.h
> -header-y += mtio.h
> -header-y += nbd.h
> -header-y += ncp_fs.h
> -header-y += ncp.h
> -header-y += ncp_mount.h
> -header-y += ncp_no.h
> -header-y += ndctl.h
> -header-y += neighbour.h
> -header-y += netconf.h
> -header-y += netdevice.h
> -header-y += net_dropmon.h
> -header-y += netfilter_arp.h
> -header-y += netfilter_bridge.h
> -header-y += netfilter_decnet.h
> -header-y += netfilter.h
> -header-y += netfilter_ipv4.h
> -header-y += netfilter_ipv6.h
> -header-y += net.h
> -header-y += netlink_diag.h
> -header-y += netlink.h
> -header-y += netrom.h
> -header-y += net_namespace.h
> -header-y += net_tstamp.h
> -header-y += nfc.h
> -header-y += nfs2.h
> -header-y += nfs3.h
> -header-y += nfs4.h
> -header-y += nfs4_mount.h
> -header-y += nfsacl.h
> -header-y += nfs_fs.h
> -header-y += nfs.h
> -header-y += nfs_idmap.h
> -header-y += nfs_mount.h
> -header-y += nl80211.h
> -header-y += n_r3964.h
> -header-y += nubus.h
> -header-y += nvme_ioctl.h
> -header-y += nvram.h
> -header-y += omap3isp.h
> -header-y += omapfb.h
> -header-y += oom.h
> -header-y += openvswitch.h
> -header-y += packet_diag.h
> -header-y += param.h
> -header-y += parport.h
> -header-y += patchkey.h
> -header-y += pci.h
> -header-y += pci_regs.h
> -header-y += perf_event.h
> -header-y += personality.h
> -header-y += pfkeyv2.h
> -header-y += pg.h
> -header-y += phantom.h
> -header-y += phonet.h
> -header-y += pktcdvd.h
> -header-y += pkt_cls.h
> -header-y += pkt_sched.h
> -header-y += pmu.h
> -header-y += poll.h
> -header-y += posix_acl.h
> -header-y += posix_acl_xattr.h
> -header-y += posix_types.h
> -header-y += ppdev.h
> -header-y += ppp-comp.h
> -header-y += ppp_defs.h
> -header-y += ppp-ioctl.h
> -header-y += pps.h
> -header-y += prctl.h
> -header-y += psci.h
> -header-y += ptp_clock.h
> -header-y += ptrace.h
> -header-y += qnx4_fs.h
> -header-y += qnxtypes.h
> -header-y += quota.h
> -header-y += radeonfb.h
> -header-y += random.h
> -header-y += raw.h
> -header-y += rds.h
> -header-y += reboot.h
> -header-y += reiserfs_fs.h
> -header-y += reiserfs_xattr.h
> -header-y += resource.h
> -header-y += rfkill.h
> -header-y += rio_cm_cdev.h
> -header-y += rio_mport_cdev.h
> -header-y += romfs_fs.h
> -header-y += rose.h
> -header-y += route.h
> -header-y += rtc.h
> -header-y += rtnetlink.h
> -header-y += scc.h
> -header-y += sched.h
> -header-y += scif_ioctl.h
> -header-y += screen_info.h
> -header-y += sctp.h
> -header-y += sdla.h
> -header-y += seccomp.h
> -header-y += securebits.h
> -header-y += selinux_netlink.h
> -header-y += sem.h
> -header-y += serial_core.h
> -header-y += serial.h
> -header-y += serial_reg.h
> -header-y += serio.h
> -header-y += shm.h
> -header-y += signalfd.h
> -header-y += signal.h
> -header-y += smiapp.h
> -header-y += snmp.h
> -header-y += sock_diag.h
> -header-y += socket.h
> -header-y += sockios.h
> -header-y += sonet.h
> -header-y += sonypi.h
> -header-y += soundcard.h
> -header-y += sound.h
> -header-y += stat.h
> -header-y += stddef.h
> -header-y += string.h
> -header-y += suspend_ioctls.h
> -header-y += swab.h
> -header-y += synclink.h
> -header-y += sync_file.h
> -header-y += sysctl.h
> -header-y += sysinfo.h
> -header-y += target_core_user.h
> -header-y += taskstats.h
> -header-y += tcp.h
> -header-y += tcp_metrics.h
> -header-y += telephony.h
> -header-y += termios.h
> -header-y += thermal.h
> -header-y += time.h
> -header-y += times.h
> -header-y += timex.h
> -header-y += tiocl.h
> -header-y += tipc_config.h
> -header-y += tipc_netlink.h
> -header-y += tipc.h
> -header-y += toshiba.h
> -header-y += tty_flags.h
> -header-y += tty.h
> -header-y += types.h
> -header-y += udf_fs_i.h
> -header-y += udp.h
> -header-y += uhid.h
> -header-y += uinput.h
> -header-y += uio.h
> -header-y += uleds.h
> -header-y += ultrasound.h
> -header-y += un.h
> -header-y += unistd.h
> -header-y += unix_diag.h
> -header-y += usbdevice_fs.h
> -header-y += usbip.h
> -header-y += utime.h
> -header-y += utsname.h
> -header-y += uuid.h
> -header-y += uvcvideo.h
> -header-y += v4l2-common.h
> -header-y += v4l2-controls.h
> -header-y += v4l2-dv-timings.h
> -header-y += v4l2-mediabus.h
> -header-y += v4l2-subdev.h
> -header-y += veth.h
> -header-y += vfio.h
> -header-y += vhost.h
> -header-y += videodev2.h
> -header-y += virtio_9p.h
> -header-y += virtio_balloon.h
> -header-y += virtio_blk.h
> -header-y += virtio_config.h
> -header-y += virtio_console.h
> -header-y += virtio_gpu.h
> -header-y += virtio_ids.h
> -header-y += virtio_input.h
> -header-y += virtio_net.h
> -header-y += virtio_pci.h
> -header-y += virtio_ring.h
> -header-y += virtio_rng.h
> -header-y += virtio_scsi.h
> -header-y += virtio_types.h
> -header-y += virtio_vsock.h
> -header-y += virtio_crypto.h
> -header-y += vm_sockets.h
> -header-y += vt.h
> -header-y += vtpm_proxy.h
> -header-y += wait.h
> -header-y += wanrouter.h
> -header-y += watchdog.h
> -header-y += wimax.h
> -header-y += wireless.h
> -header-y += x25.h
> -header-y += xattr.h
> -header-y += xfrm.h
> -header-y += xilinx-v4l2-controls.h
> -header-y += zorro.h
> -header-y += zorro_ids.h
> -header-y += userfaultfd.h
> diff --git a/include/uapi/linux/android/Kbuild b/include/uapi/linux/android/Kbuild
> deleted file mode 100644
> index ca011eec252a..000000000000
> --- a/include/uapi/linux/android/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += binder.h
> diff --git a/include/uapi/linux/byteorder/Kbuild b/include/uapi/linux/byteorder/Kbuild
> deleted file mode 100644
> index 619225b9ff2e..000000000000
> --- a/include/uapi/linux/byteorder/Kbuild
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -# UAPI Header export list
> -header-y += big_endian.h
> -header-y += little_endian.h
> diff --git a/include/uapi/linux/caif/Kbuild b/include/uapi/linux/caif/Kbuild
> deleted file mode 100644
> index 43396612d3a3..000000000000
> --- a/include/uapi/linux/caif/Kbuild
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -# UAPI Header export list
> -header-y += caif_socket.h
> -header-y += if_caif.h
> diff --git a/include/uapi/linux/can/Kbuild b/include/uapi/linux/can/Kbuild
> deleted file mode 100644
> index 21c91bf25a29..000000000000
> --- a/include/uapi/linux/can/Kbuild
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# UAPI Header export list
> -header-y += bcm.h
> -header-y += error.h
> -header-y += gw.h
> -header-y += netlink.h
> -header-y += raw.h
> diff --git a/include/uapi/linux/dvb/Kbuild b/include/uapi/linux/dvb/Kbuild
> deleted file mode 100644
> index d40942cfc627..000000000000
> --- a/include/uapi/linux/dvb/Kbuild
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -# UAPI Header export list
> -header-y += audio.h
> -header-y += ca.h
> -header-y += dmx.h
> -header-y += frontend.h
> -header-y += net.h
> -header-y += osd.h
> -header-y += version.h
> -header-y += video.h
> diff --git a/include/uapi/linux/hdlc/Kbuild b/include/uapi/linux/hdlc/Kbuild
> deleted file mode 100644
> index 8c1d2cb75e33..000000000000
> --- a/include/uapi/linux/hdlc/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += ioctl.h
> diff --git a/include/uapi/linux/hsi/Kbuild b/include/uapi/linux/hsi/Kbuild
> deleted file mode 100644
> index a16a00544258..000000000000
> --- a/include/uapi/linux/hsi/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += hsi_char.h cs-protocol.h
> diff --git a/include/uapi/linux/iio/Kbuild b/include/uapi/linux/iio/Kbuild
> deleted file mode 100644
> index 86f76d84c44f..000000000000
> --- a/include/uapi/linux/iio/Kbuild
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -# UAPI Header export list
> -header-y += events.h
> -header-y += types.h
> diff --git a/include/uapi/linux/isdn/Kbuild b/include/uapi/linux/isdn/Kbuild
> deleted file mode 100644
> index 89e52850bf29..000000000000
> --- a/include/uapi/linux/isdn/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += capicmd.h
> diff --git a/include/uapi/linux/mmc/Kbuild b/include/uapi/linux/mmc/Kbuild
> deleted file mode 100644
> index 8c1d2cb75e33..000000000000
> --- a/include/uapi/linux/mmc/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += ioctl.h
> diff --git a/include/uapi/linux/netfilter/Kbuild b/include/uapi/linux/netfilter/Kbuild
> deleted file mode 100644
> index 03f194aeadc5..000000000000
> --- a/include/uapi/linux/netfilter/Kbuild
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -# UAPI Header export list
> -header-y += ipset/
> -header-y += nf_conntrack_common.h
> -header-y += nf_conntrack_ftp.h
> -header-y += nf_conntrack_sctp.h
> -header-y += nf_conntrack_tcp.h
> -header-y += nf_conntrack_tuple_common.h
> -header-y += nf_log.h
> -header-y += nf_tables.h
> -header-y += nf_tables_compat.h
> -header-y += nf_nat.h
> -header-y += nfnetlink.h
> -header-y += nfnetlink_acct.h
> -header-y += nfnetlink_compat.h
> -header-y += nfnetlink_conntrack.h
> -header-y += nfnetlink_cthelper.h
> -header-y += nfnetlink_cttimeout.h
> -header-y += nfnetlink_log.h
> -header-y += nfnetlink_queue.h
> -header-y += x_tables.h
> -header-y += xt_AUDIT.h
> -header-y += xt_CHECKSUM.h
> -header-y += xt_CLASSIFY.h
> -header-y += xt_CONNMARK.h
> -header-y += xt_CONNSECMARK.h
> -header-y += xt_CT.h
> -header-y += xt_DSCP.h
> -header-y += xt_HMARK.h
> -header-y += xt_IDLETIMER.h
> -header-y += xt_LED.h
> -header-y += xt_LOG.h
> -header-y += xt_MARK.h
> -header-y += xt_NFLOG.h
> -header-y += xt_NFQUEUE.h
> -header-y += xt_RATEEST.h
> -header-y += xt_SECMARK.h
> -header-y += xt_SYNPROXY.h
> -header-y += xt_TCPMSS.h
> -header-y += xt_TCPOPTSTRIP.h
> -header-y += xt_TEE.h
> -header-y += xt_TPROXY.h
> -header-y += xt_addrtype.h
> -header-y += xt_bpf.h
> -header-y += xt_cgroup.h
> -header-y += xt_cluster.h
> -header-y += xt_comment.h
> -header-y += xt_connbytes.h
> -header-y += xt_connlabel.h
> -header-y += xt_connlimit.h
> -header-y += xt_connmark.h
> -header-y += xt_conntrack.h
> -header-y += xt_cpu.h
> -header-y += xt_dccp.h
> -header-y += xt_devgroup.h
> -header-y += xt_dscp.h
> -header-y += xt_ecn.h
> -header-y += xt_esp.h
> -header-y += xt_hashlimit.h
> -header-y += xt_helper.h
> -header-y += xt_ipcomp.h
> -header-y += xt_iprange.h
> -header-y += xt_ipvs.h
> -header-y += xt_l2tp.h
> -header-y += xt_length.h
> -header-y += xt_limit.h
> -header-y += xt_mac.h
> -header-y += xt_mark.h
> -header-y += xt_multiport.h
> -header-y += xt_nfacct.h
> -header-y += xt_osf.h
> -header-y += xt_owner.h
> -header-y += xt_physdev.h
> -header-y += xt_pkttype.h
> -header-y += xt_policy.h
> -header-y += xt_quota.h
> -header-y += xt_rateest.h
> -header-y += xt_realm.h
> -header-y += xt_recent.h
> -header-y += xt_rpfilter.h
> -header-y += xt_sctp.h
> -header-y += xt_set.h
> -header-y += xt_socket.h
> -header-y += xt_state.h
> -header-y += xt_statistic.h
> -header-y += xt_string.h
> -header-y += xt_tcpmss.h
> -header-y += xt_tcpudp.h
> -header-y += xt_time.h
> -header-y += xt_u32.h
> diff --git a/include/uapi/linux/netfilter/ipset/Kbuild b/include/uapi/linux/netfilter/ipset/Kbuild
> deleted file mode 100644
> index d2680423d9ab..000000000000
> --- a/include/uapi/linux/netfilter/ipset/Kbuild
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -# UAPI Header export list
> -header-y += ip_set.h
> -header-y += ip_set_bitmap.h
> -header-y += ip_set_hash.h
> -header-y += ip_set_list.h
> diff --git a/include/uapi/linux/netfilter_arp/Kbuild b/include/uapi/linux/netfilter_arp/Kbuild
> deleted file mode 100644
> index 62d5637cc0ac..000000000000
> --- a/include/uapi/linux/netfilter_arp/Kbuild
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -# UAPI Header export list
> -header-y += arp_tables.h
> -header-y += arpt_mangle.h
> diff --git a/include/uapi/linux/netfilter_bridge/Kbuild b/include/uapi/linux/netfilter_bridge/Kbuild
> deleted file mode 100644
> index 0fbad8ef96de..000000000000
> --- a/include/uapi/linux/netfilter_bridge/Kbuild
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -# UAPI Header export list
> -header-y += ebt_802_3.h
> -header-y += ebt_among.h
> -header-y += ebt_arp.h
> -header-y += ebt_arpreply.h
> -header-y += ebt_ip.h
> -header-y += ebt_ip6.h
> -header-y += ebt_limit.h
> -header-y += ebt_log.h
> -header-y += ebt_mark_m.h
> -header-y += ebt_mark_t.h
> -header-y += ebt_nat.h
> -header-y += ebt_nflog.h
> -header-y += ebt_pkttype.h
> -header-y += ebt_redirect.h
> -header-y += ebt_stp.h
> -header-y += ebt_vlan.h
> -header-y += ebtables.h
> diff --git a/include/uapi/linux/netfilter_ipv4/Kbuild b/include/uapi/linux/netfilter_ipv4/Kbuild
> deleted file mode 100644
> index ecb291df390e..000000000000
> --- a/include/uapi/linux/netfilter_ipv4/Kbuild
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -# UAPI Header export list
> -header-y += ip_tables.h
> -header-y += ipt_CLUSTERIP.h
> -header-y += ipt_ECN.h
> -header-y += ipt_LOG.h
> -header-y += ipt_REJECT.h
> -header-y += ipt_TTL.h
> -header-y += ipt_ah.h
> -header-y += ipt_ecn.h
> -header-y += ipt_ttl.h
> diff --git a/include/uapi/linux/netfilter_ipv6/Kbuild b/include/uapi/linux/netfilter_ipv6/Kbuild
> deleted file mode 100644
> index 75a668ca2353..000000000000
> --- a/include/uapi/linux/netfilter_ipv6/Kbuild
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -# UAPI Header export list
> -header-y += ip6_tables.h
> -header-y += ip6t_HL.h
> -header-y += ip6t_LOG.h
> -header-y += ip6t_NPT.h
> -header-y += ip6t_REJECT.h
> -header-y += ip6t_ah.h
> -header-y += ip6t_frag.h
> -header-y += ip6t_hl.h
> -header-y += ip6t_ipv6header.h
> -header-y += ip6t_mh.h
> -header-y += ip6t_opts.h
> -header-y += ip6t_rt.h
> diff --git a/include/uapi/linux/nfsd/Kbuild b/include/uapi/linux/nfsd/Kbuild
> deleted file mode 100644
> index c11bc404053c..000000000000
> --- a/include/uapi/linux/nfsd/Kbuild
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# UAPI Header export list
> -header-y += cld.h
> -header-y += debug.h
> -header-y += export.h
> -header-y += nfsfh.h
> -header-y += stats.h
> diff --git a/include/uapi/linux/raid/Kbuild b/include/uapi/linux/raid/Kbuild
> deleted file mode 100644
> index e2c3d25405d7..000000000000
> --- a/include/uapi/linux/raid/Kbuild
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -# UAPI Header export list
> -header-y += md_p.h
> -header-y += md_u.h
> diff --git a/include/uapi/linux/spi/Kbuild b/include/uapi/linux/spi/Kbuild
> deleted file mode 100644
> index 0cc747eff165..000000000000
> --- a/include/uapi/linux/spi/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += spidev.h
> diff --git a/include/uapi/linux/sunrpc/Kbuild b/include/uapi/linux/sunrpc/Kbuild
> deleted file mode 100644
> index 8e02e47c20fb..000000000000
> --- a/include/uapi/linux/sunrpc/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += debug.h
> diff --git a/include/uapi/linux/tc_act/Kbuild b/include/uapi/linux/tc_act/Kbuild
> deleted file mode 100644
> index e3db7403296f..000000000000
> --- a/include/uapi/linux/tc_act/Kbuild
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -# UAPI Header export list
> -header-y += tc_csum.h
> -header-y += tc_defact.h
> -header-y += tc_gact.h
> -header-y += tc_ipt.h
> -header-y += tc_mirred.h
> -header-y += tc_nat.h
> -header-y += tc_pedit.h
> -header-y += tc_skbedit.h
> -header-y += tc_vlan.h
> -header-y += tc_bpf.h
> -header-y += tc_connmark.h
> -header-y += tc_ife.h
> -header-y += tc_tunnel_key.h
> -header-y += tc_skbmod.h
> diff --git a/include/uapi/linux/tc_ematch/Kbuild b/include/uapi/linux/tc_ematch/Kbuild
> deleted file mode 100644
> index 53fca3925535..000000000000
> --- a/include/uapi/linux/tc_ematch/Kbuild
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -# UAPI Header export list
> -header-y += tc_em_cmp.h
> -header-y += tc_em_meta.h
> -header-y += tc_em_nbyte.h
> -header-y += tc_em_text.h
> diff --git a/include/uapi/linux/usb/Kbuild b/include/uapi/linux/usb/Kbuild
> deleted file mode 100644
> index 4cc4d6e7e523..000000000000
> --- a/include/uapi/linux/usb/Kbuild
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -# UAPI Header export list
> -header-y += audio.h
> -header-y += cdc.h
> -header-y += cdc-wdm.h
> -header-y += ch11.h
> -header-y += ch9.h
> -header-y += functionfs.h
> -header-y += g_printer.h
> -header-y += gadgetfs.h
> -header-y += midi.h
> -header-y += tmc.h
> -header-y += video.h
> diff --git a/include/uapi/linux/wimax/Kbuild b/include/uapi/linux/wimax/Kbuild
> deleted file mode 100644
> index 1c97be49971f..000000000000
> --- a/include/uapi/linux/wimax/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += i2400m.h
> diff --git a/include/uapi/misc/Kbuild b/include/uapi/misc/Kbuild
> deleted file mode 100644
> index e96cae7d58c9..000000000000
> --- a/include/uapi/misc/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# misc Header export list
> -header-y += cxl.h
> diff --git a/include/uapi/mtd/Kbuild b/include/uapi/mtd/Kbuild
> deleted file mode 100644
> index 5a691e10cd0e..000000000000
> --- a/include/uapi/mtd/Kbuild
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# UAPI Header export list
> -header-y += inftl-user.h
> -header-y += mtd-abi.h
> -header-y += mtd-user.h
> -header-y += nftl-user.h
> -header-y += ubi-user.h
> diff --git a/include/uapi/rdma/Kbuild b/include/uapi/rdma/Kbuild
> deleted file mode 100644
> index 82bdf5626859..000000000000
> --- a/include/uapi/rdma/Kbuild
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -# UAPI Header export list
> -header-y += ib_user_cm.h
> -header-y += ib_user_mad.h
> -header-y += ib_user_sa.h
> -header-y += ib_user_verbs.h
> -header-y += rdma_netlink.h
> -header-y += rdma_user_cm.h
> -header-y += hfi/
> -header-y += rdma_user_rxe.h
> -header-y += cxgb3-abi.h
> -header-y += cxgb4-abi.h
> -header-y += mlx4-abi.h
> -header-y += mlx5-abi.h
> -header-y += mthca-abi.h
> -header-y += nes-abi.h
> -header-y += ocrdma-abi.h
> -header-y += hns-abi.h
> -header-y += vmw_pvrdma-abi.h
> diff --git a/include/uapi/rdma/hfi/Kbuild b/include/uapi/rdma/hfi/Kbuild
> deleted file mode 100644
> index ef23c294fc71..000000000000
> --- a/include/uapi/rdma/hfi/Kbuild
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# UAPI Header export list
> -header-y += hfi1_user.h
> diff --git a/include/uapi/scsi/Kbuild b/include/uapi/scsi/Kbuild
> deleted file mode 100644
> index d791e0ad509d..000000000000
> --- a/include/uapi/scsi/Kbuild
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# UAPI Header export list
> -header-y += fc/
> -header-y += scsi_bsg_fc.h
> -header-y += scsi_netlink.h
> -header-y += scsi_netlink_fc.h
> -header-y += cxlflash_ioctl.h
> diff --git a/include/uapi/scsi/fc/Kbuild b/include/uapi/scsi/fc/Kbuild
> deleted file mode 100644
> index 5ead9fac265c..000000000000
> --- a/include/uapi/scsi/fc/Kbuild
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -# UAPI Header export list
> -header-y += fc_els.h
> -header-y += fc_fs.h
> -header-y += fc_gs.h
> -header-y += fc_ns.h
> diff --git a/include/uapi/sound/Kbuild b/include/uapi/sound/Kbuild
> deleted file mode 100644
> index 9578d8bdbf31..000000000000
> --- a/include/uapi/sound/Kbuild
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -# UAPI Header export list
> -header-y += asequencer.h
> -header-y += asoc.h
> -header-y += asound.h
> -header-y += asound_fm.h
> -header-y += compress_offload.h
> -header-y += compress_params.h
> -header-y += emu10k1.h
> -header-y += firewire.h
> -header-y += hdsp.h
> -header-y += hdspm.h
> -header-y += sb16_csp.h
> -header-y += sfnt_info.h
> -header-y += tlv.h
> -header-y += usb_stream.h
> -header-y += snd_sst_tokens.h
> diff --git a/include/uapi/video/Kbuild b/include/uapi/video/Kbuild
> deleted file mode 100644
> index ac7203bb32cc..000000000000
> --- a/include/uapi/video/Kbuild
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -# UAPI Header export list
> -header-y += edid.h
> -header-y += sisfb.h
> -header-y += uvesafb.h
> diff --git a/include/uapi/xen/Kbuild b/include/uapi/xen/Kbuild
> deleted file mode 100644
> index 5c459628e8c7..000000000000
> --- a/include/uapi/xen/Kbuild
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -# UAPI Header export list
> -header-y += evtchn.h
> -header-y += gntalloc.h
> -header-y += gntdev.h
> -header-y += privcmd.h
> diff --git a/include/video/Kbuild b/include/video/Kbuild
> deleted file mode 100644
> index e69de29bb2d1..000000000000
> diff --git a/scripts/Makefile.headersinst b/scripts/Makefile.headersinst
> index 876b42cfede4..bb93f8466a35 100644
> --- a/scripts/Makefile.headersinst
> +++ b/scripts/Makefile.headersinst
> @@ -1,17 +1,18 @@
> ?# ==========================================================================
> ?# Installing headers
> ?#
> -# header-y??- list files to be installed. They are preprocessed
> -#?????????????to remove __KERNEL__ section of the file
> -# genhdr-y??- Same as header-y but in a generated/ directory
> +# All headers under include/uapi, include/generated/uapi,
> +# arch/<arch>/include/uapi/asm and /include/generated/uapi/asm are exported.
> +# They are preprocessed to remove __KERNEL__ section of the file.
> ?#
> ?# ==========================================================================
> ?
> ?# generated header directory
> ?gen := $(if $(gen),$(gen),$(subst include/,include/generated/,$(obj)))
> ?
> +# Kbuild file is optional
> ?kbuild-file := $(srctree)/$(obj)/Kbuild
> -include $(kbuild-file)
> +-include $(kbuild-file)
> ?
> ?# called may set destination dir (when installing to asm/)
> ?_dst := $(if $(dst),$(dst),$(obj))
> @@ -25,9 +26,12 @@ include scripts/Kbuild.include
> ?
> ?installdir????:= $(INSTALL_HDR_PATH)/$(subst uapi/,,$(_dst))
> ?
> -header-y??????:= $(sort $(header-y))
> -subdirs???????:= $(patsubst %/,%,$(filter %/, $(header-y)))
> -header-y??????:= $(filter-out %/, $(header-y))
> +subdirs???????:= $(patsubst $(srctree)/$(obj)/%/.,%,$(wildcard $(srctree)/$(obj)/*/.))
> +subdirs???????+= $(subdir-y)
> +header-files??:= $(notdir $(wildcard $(srctree)/$(obj)/*.h))
> +header-files??+= $(notdir $(wildcard $(srctree)/$(obj)/*.agh))
> +genhdr-files??:= $(notdir $(wildcard $(srctree)/$(gen)/*.h))
> +genhdr-files??:= $(filter-out $(header-files), $(genhdr-files))
> ?
> ?# files used to track state of install/check
> ?install-file??:= $(installdir)/.install
> @@ -35,26 +39,17 @@ check-file????:= $(installdir)/.check
> ?
> ?# generic-y list all files an architecture uses from asm-generic
> ?# Use this to build a list of headers which require a wrapper
> -wrapper-files := $(filter $(header-y), $(generic-y))
> +generic-files := $(notdir $(wildcard $(srctree)/include/uapi/asm-generic/*.h))
> +wrapper-files := $(filter $(generic-files), $(generic-y))
> +wrapper-files := $(filter-out $(header-files), $(wrapper-files))
> ?
> ?srcdir????????:= $(srctree)/$(obj)
> ?gendir????????:= $(objtree)/$(gen)
> ?
> ?# all headers files for this dir
> -header-y??????:= $(filter-out $(generic-y), $(header-y))
> -all-files?????:= $(header-y) $(genhdr-y) $(wrapper-files)
> +all-files?????:= $(header-files) $(genhdr-files) $(wrapper-files)
> ?output-files??:= $(addprefix $(installdir)/, $(all-files))
> ?
> -# Check that all expected files exist
> -$(foreach hdr, $(header-y), \
> -??$(if $(wildcard $(srcdir)/$(hdr)),, \
> -???????$(error Missing UAPI file $(srcdir)/$(hdr)) \
> -???))
> -$(foreach hdr, $(genhdr-y), \
> -??$(if	$(wildcard $(gendir)/$(hdr)),, \
> -???????$(error Missing generated UAPI file $(gendir)/$(hdr)) \
> -??))
> -
> ?# Work out what needs to be removed
> ?oldheaders????:= $(patsubst $(installdir)/%,%,$(wildcard $(installdir)/*.h))
> ?unwanted??????:= $(filter-out $(all-files),$(oldheaders))
> @@ -67,8 +62,8 @@ printdir = $(patsubst $(INSTALL_HDR_PATH)/%/,%,$(dir $@))
> ?quiet_cmd_install = INSTALL $(printdir) ($(words $(all-files))\
> ?????????????????????????????file$(if $(word 2, $(all-files)),s))
> ???????cmd_install = \
> -????????$(CONFIG_SHELL) $< $(installdir) $(srcdir) $(header-y); \
> -????????$(CONFIG_SHELL) $< $(installdir) $(gendir) $(genhdr-y); \
> +????????$(CONFIG_SHELL) $< $(installdir) $(srcdir) $(header-files); \
> +????????$(CONFIG_SHELL) $< $(installdir) $(gendir) $(genhdr-files); \
> ?????????for F in $(wrapper-files); do???????????????????????????????????\
> ?????????????????echo "\#include <asm-generic/$$F>" > $(installdir)/$$F;????\
> ?????????done;???????????????????????????????????????????????????????????\

^ permalink raw reply

* [PATCH v2 2/2] vring: Force use of DMA API for ARM-based systems
From: Andy Lutomirski @ 2017-01-11 18:12 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111100139.GC12388@arm.com>

On Wed, Jan 11, 2017 at 2:01 AM, Will Deacon <will.deacon@arm.com> wrote:
> On Wed, Jan 11, 2017 at 01:33:31AM +0200, Michael S. Tsirkin wrote:
>> On Tue, Jan 10, 2017 at 05:51:18PM +0000, Robin Murphy wrote:
>> > From: Will Deacon <will.deacon@arm.com>
>> >
>> > Booting Linux on an ARM fastmodel containing an SMMU emulation results
>> > in an unexpected I/O page fault from the legacy virtio-blk PCI device:
>> >
>> > [    1.211721] arm-smmu-v3 2b400000.smmu: event 0x10 received:
>> > [    1.211800] arm-smmu-v3 2b400000.smmu:   0x00000000fffff010
>> > [    1.211880] arm-smmu-v3 2b400000.smmu:   0x0000020800000000
>> > [    1.211959] arm-smmu-v3 2b400000.smmu:   0x00000008fa081002
>> > [    1.212075] arm-smmu-v3 2b400000.smmu:   0x0000000000000000
>> > [    1.212155] arm-smmu-v3 2b400000.smmu: event 0x10 received:
>> > [    1.212234] arm-smmu-v3 2b400000.smmu:   0x00000000fffff010
>> > [    1.212314] arm-smmu-v3 2b400000.smmu:   0x0000020800000000
>> > [    1.212394] arm-smmu-v3 2b400000.smmu:   0x00000008fa081000
>> > [    1.212471] arm-smmu-v3 2b400000.smmu:   0x0000000000000000
>> >
>> > <system hangs failing to read partition table>
>> >
>> > This is because the virtio-blk is behind an SMMU, so we have consequently
>> > swizzled its DMA ops and configured the SMMU to translate accesses. This
>> > then requires the vring code to use the DMA API to establish translations,
>> > otherwise all transactions will result in fatal faults and termination.
>> >
>> > Given that ARM-based systems only see an SMMU if one is really present
>> > (the topology is all described by firmware tables such as device-tree or
>> > IORT), then we can safely use the DMA API for all virtio devices.
>> >
>> > Cc: Andy Lutomirski <luto@kernel.org>
>> > Cc: Michael S. Tsirkin <mst@redhat.com>
>> > Signed-off-by: Will Deacon <will.deacon@arm.com>
>>
>> I'd like to better understand then need for this one.
>> Can't the device in question just set VIRTIO_F_IOMMU_PLATFORM ?
>>
>> I'd rather we avoided need for more hacks and just
>> have everyone switch to that.
>
> There are a couple of problems with VIRTIO_F_IOMMU_PLATFORM:
>
> 1. It doesn't exist for legacy devices, which are all we have on the
>    platform in question.
>
> 2. It's not documented in the virtio sp^H^HSTOP PRESS. I see you applied
>    my patch ;). Thanks.
>
> In which case, for non-legacy devices we should definitely be using
> VIRTIO_F_IOMMU_PLATFORM, but since this platform hasn't yet moved to the
> world of flying cars, could we unconditionally set the DMA ops on ARM
> for legacy devices? The alternative is disabling the SMMU altogether,
> but that's less than ideal because there are non-virtio devices on the
> same PCI bus.

Also, on ARM, using the DMA API appears to *always* be the correct
approach.  Why not do it all the time, then?  The non-DMA-API path is
a legacy thing that is needed because a few platforms incorrectly
enumerate their IOMMUs.  ARM gets it right, so I don't see why ARM
should be subject to the legacy mess.

Even on x86, it should be possible to get the code into a state where
using DMA ops is always correct.

--Andy

^ permalink raw reply

* [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
From: Catalin Marinas @ 2017-01-11 18:06 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111144118.17062-2-cov@codeaurora.org>

Some minor comments below, nothing fundamental (as long as you say the
new sequence doesn't have the speculative TLB load problem I mentioned
on a previous version).

On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 405da11..7151aed 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -42,24 +42,25 @@ file acts as a registry of software workarounds in the Linux Kernel and
>  will be updated when new workarounds are committed and backported to
>  stable kernels.
>  
> -| Implementor    | Component       | Erratum ID      | Kconfig                 |
> -+----------------+-----------------+-----------------+-------------------------+
> -| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319    |
> -| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319    |
> -| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069    |
> -| ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472    |
> -| ARM            | Cortex-A53      | #845719         | ARM64_ERRATUM_845719    |
> -| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419    |
> -| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    |
> -| ARM            | Cortex-A57      | #852523         | N/A                     |
> -| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220    |
> -| ARM            | Cortex-A72      | #853709         | N/A                     |
> -| ARM            | MMU-500         | #841119,#826419 | N/A                     |
> -|                |                 |                 |                         |
> -| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
> -| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144    |
> -| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
> -| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
> -| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
> -|                |                 |                 |                         |
> -| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
> +| Implementor   | Component       | Erratum ID      | Kconfig                  |
> ++---------------+-----------------+-----------------+--------------------------+
> +| ARM           | Cortex-A53      | #826319         | ARM64_ERRATUM_826319     |
> +| ARM           | Cortex-A53      | #827319         | ARM64_ERRATUM_827319     |
> +| ARM           | Cortex-A53      | #824069         | ARM64_ERRATUM_824069     |
> +| ARM           | Cortex-A53      | #819472         | ARM64_ERRATUM_819472     |
> +| ARM           | Cortex-A53      | #845719         | ARM64_ERRATUM_845719     |
> +| ARM           | Cortex-A53      | #843419         | ARM64_ERRATUM_843419     |
> +| ARM           | Cortex-A57      | #832075         | ARM64_ERRATUM_832075     |
> +| ARM           | Cortex-A57      | #852523         | N/A                      |
> +| ARM           | Cortex-A57      | #834220         | ARM64_ERRATUM_834220     |
> +| ARM           | Cortex-A72      | #853709         | N/A                      |
> +| ARM           | MMU-500         | #841119,#826419 | N/A                      |
> +|               |                 |                 |                          |
> +| Cavium        | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375     |
> +| Cavium        | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144     |
> +| Cavium        | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154     |
> +| Cavium        | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456     |
> +| Cavium        | ThunderX SMMUv2 | #27704          | N/A                      |
> +|               |                 |                 |                          |
> +| Freescale/NXP | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585      |
> +| Qualcomm      | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003 |

Please don't change the "Implementor" column width, there is no point
and it makes the patch harder to read (i.e. this hunk should only have
one line).

> diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
> index 4c63cb1..5a0a82a 100644
> --- a/arch/arm64/mm/context.c
> +++ b/arch/arm64/mm/context.c
> @@ -87,6 +87,11 @@ static void flush_context(unsigned int cpu)
>  	/* Update the list of reserved ASIDs and the ASID bitmap. */
>  	bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
>  
> +	/* Reserve ASID for Falkor erratum 1003 */
> +	if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) &&
> +	    cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003))
> +		__set_bit(FALKOR_RESERVED_ASID, asid_map);
> +
>  	/*
>  	 * Ensure the generation bump is observed before we xchg the
>  	 * active_asids.
> @@ -244,6 +249,11 @@ static int asids_init(void)
>  		panic("Failed to allocate bitmap for %lu ASIDs\n",
>  		      NUM_USER_ASIDS);
>  
> +	/* Reserve ASID for Falkor erratum 1003 */
> +	if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) &&
> +	    cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003))
> +		__set_bit(FALKOR_RESERVED_ASID, asid_map);
> +
>  	pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
>  	return 0;
>  }

You could as well write a small static function in this file and call it
twice.

> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 32682be..9ee46df 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -23,6 +23,7 @@
>  #include <asm/assembler.h>
>  #include <asm/asm-offsets.h>
>  #include <asm/hwcap.h>
> +#include <asm/mmu_context.h>
>  #include <asm/pgtable.h>
>  #include <asm/pgtable-hwdef.h>
>  #include <asm/cpufeature.h>
> @@ -140,6 +141,18 @@ ENDPROC(cpu_do_resume)
>  ENTRY(cpu_do_switch_mm)
>  	mmid	x1, x1				// get mm->context.id
>  	bfi	x0, x1, #48, #16		// set the ASID
> +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
> +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
> +	mrs     x2, ttbr0_el1
> +	mov     x3, #FALKOR_RESERVED_ASID
> +	bfi     x2, x3, #48, #16                // reserved ASID + old BADDR
> +	msr     ttbr0_el1, x2
> +	isb
> +	bfi     x2, x0, #0, #48                 // reserved ASID + new BADDR
> +	msr     ttbr0_el1, x2
> +	isb
> +alternative_else_nop_endif
> +#endif
>  	msr	ttbr0_el1, x0			// set TTBR0
>  	isb
>  	post_ttbr0_update_workaround

Please move the above hunk to a pre_ttbr0_update_workaround macro for
consistency with post_ttbr0_update_workaround.

-- 
Catalin

^ permalink raw reply

* [RFC PATCH 1/2] ARM: vfp - allow kernel mode NEON in softirq context
From: Russell King - ARM Linux @ 2017-01-11 17:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1483991849-32448-2-git-send-email-ard.biesheuvel@linaro.org>

On Mon, Jan 09, 2017 at 07:57:28PM +0000, Ard Biesheuvel wrote:
> This updates the kernel mode NEON handling to allow the NEON to be used
> in softirq context as well as process context. This involves disabling
> softirq processing when the NEON is used in kernel mode in process context,
> and dealing with the situation where 'current' is not the owner of the
> userland context that is present in the NEON register file when the NEON
> is enabled in kernel mode.

I really don't like this idea as-is.

We have cases where kernel code accesses VFP to (eg) save or restore
register state, such as during signal handling.  We assume that this
will not be interrupted by another user, and that if we enable access
to the VFP, it will stay enabled.  If it gets disabled beneath us, then
things won't go well.

For example, consider vfp_sync_hwstate():

vfp_sync_hwstate()
  vfp_state_in_hw() => true
    fpexc read
	softirq happens
		kernel_neon_begin()
		kernel_neon_end()
    fpexc re-enabled
    current register state saved out (corrupting what was there)
    fpexc restored, possible in an enabled state

Or we could have:

vfp_sync_hwstate()
  vfp_state_in_hw() => true
	softirq happens
		kernel_neon_begin()
		kernel_neon_end()
    fpexc read
    fpexc re-enabled
    current register state saved out (corrupting what was there)
    fpexc disabled

Or worse:

vfp_sync_hwstate()
  vfp_state_in_hw() => true
    fpexc read
    fpexc re-enabled
	softirq happens
		kernel_neon_begin()
		kernel_neon_end()
    current register state saved out, blowing up because VFP is
     unexpectedly disabled

So we would need to disable softirqs around every sensitive point in the
VFP support code, and over all VFP instruction emulations for those VFPs
which bounce "difficult" operations to the kernel support code.

> The rationale for this change is that the NEON is shared with the ARMv8
> Crypto Extensions (which are also defined for the AArch32 execution state),
> which can give a huge performance boost (15x) to use cases like mac80211
> CCMP processing, which executes in softirq context.

I think, once the implementation is more correct, this would need to
be re-evaluated, and I'd also like other more general performance
measurements as well (eg, latency.)

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply

* [PATCH 56/62] watchdog: tangox_wdt: Convert to use device managed functions
From: Guenter Roeck @ 2017-01-11 17:51 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <f7d9227c-4912-5c52-5ba7-ae7fa3b89857@sigmadesigns.com>

On Wed, Jan 11, 2017 at 04:28:12PM +0100, Marc Gonzalez wrote:
> On 11/01/2017 15:25, Guenter Roeck wrote:
> > On 01/11/2017 04:31 AM, Marc Gonzalez wrote:
> >> On 11/01/2017 11:52, Guenter Roeck wrote:
> >>
> >>> On 01/11/2017 01:07 AM, Marc Gonzalez wrote:
> >>>
> >>>>> @@ -134,12 +134,15 @@ static int tangox_wdt_probe(struct platform_device *pdev)
> >>>>>  	err = clk_prepare_enable(dev->clk);
> >>>>>  	if (err)
> >>>>>  		return err;
> >>>>> +	err = devm_add_action_or_reset(&pdev->dev,
> >>>>> +				       (void(*)(void *))clk_disable_unprepare,
> >>>>> +				       dev->clk);
> >>>>> +	if (err)
> >>>>> +		return err;
> >>>>
> >>>> Hello Guenter,
> >>>>
> >>>> I would rather avoid the function pointer cast.
> >>>> How about defining an auxiliary function for the cleanup action?
> >>>>
> >>>> clk_disable_unprepare() is static inline, so gcc will have to
> >>>> define an auxiliary function either way. What do you think?
> >>>
> >>> Not really. It would just make it more complicated to replace the
> >>> call with devm_clk_prepare_enable(), should it ever find its way
> >>> into the light of day.
> >>
> >> More complicated, because the cleanup function will have to be deleted later?
> >> The compiler will warn if someone forgets to do that.
> >>
> >> In my opinion, it's not a good idea to rely on the fact that casting
> >> void(*)(struct clk *clk) to void(*)(void *) is likely to work as expected
> >> on most platforms. (It has undefined behavior, strictly speaking.)
> >
> > I do hear that you object to this code.
> > 
> > However, I must admit that you completely lost me here. It is a cast from
> > one function pointer to another,
> 
> Perhaps you are used to work at the assembly level, where pointers are
> just addresses, and all pointers are interchangeable.
> 
> At a slightly higher level (C abstract machine), it is not so.
> 
> > passed as argument to another function,
> > with a secondary cast of its argument from a typed pointer to a void pointer.
> > I don't think C permits for "undefined behavior, strictly speaking".
> 
> The C standard leaves quite a lot of behavior undefined, e.g.
> 
> char *foo = "hello";
> foo[1] = 'a'; // UB
> 
> char buf[4];
> *(int *)&buf = 0xdeadbeef; // UB
> 
> 1 << 64; // UB
> 
Ah, yes, I stand corrected.

However, some other unrelated undefined behavior does not mean that this
specific behavior is undefined.

So far we have a claim that a cast to a void * may somehow be different
to a cast to a different pointer, if used as function argument, and that
the behavior with such a cast may be undefined. In other words, you claim
that a function implemented as, say,

   void func(int *var) {}

might result in undefined behavior if some header file declares it as

    void func(void *);

and it is called as

    int var;

    func(&var);

That seems really far fetched to me.

I do get the message that you do not like this kind of cast. But that doesn't
mean it is not correct.

> > Besides, that same mechanism is already used elsewhere, which is how I
> > got the idea. Are you claiming that there are situations where it won't
> > work ?
> 
> If this technique is already used elsewhere in the kernel, then I'll
> crawl back under my rock (and weep).
> 

git grep "(void(\*)(void \*))"

and variants thereof:

git grep "(void(\*)"

> I can see two issues with the code you propose.
> 
> First is the same for all casts: silencing potential warnings,
> e.g. if the prototype of clk_disable_unprepare ever changed.
> (Though casts are required for vararg function arguments.)
> 
Understood. However, one should really hope that anyone changing
an API has a look at all its callers and does not just pray that
there are no problems.

> Second is just theory and not a real-world concern.
> 
> >> Do you really dislike the portable solution I suggested? :-(
> >
> > It is not more portable than the above. It is more expensive and adds more
> > code.
> 
> Maybe I am mistaken. Can you tell me why adding an auxiliary function
> is more expensive? (In CPU cycles?)
> 
In terms of code required. The idea here is to simplify the code, not
to make it more complex. The auxiliary function needs to be declared
and maintained in each affected file. I do find it easier and better
(and safer, for that matter) to let the C compiler handle it.

Guenter

^ permalink raw reply

* [PATCH 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111174334.24343-1-martin.blumenstingl@googlemail.com>

Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi   |  8 ++++++++
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi  | 10 ++++++++++
 3 files changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index cddad8c795ec..ed3bf29eb76a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -237,6 +237,14 @@
 				status = "disabled";
 			};
 
+			saradc: adc at 8680 {
+				compatible = "amlogic,meson-saradc";
+				#io-channel-cells = <1>;
+				status = "disabled";
+				reg = <0x0 0x8680 0x0 0x34>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>;
+			};
+
 			pwm_ef: pwm at 86c0 {
 				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
 				reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 5d686334f692..114d7e1c9fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -429,6 +429,16 @@
 	clocks = <&clkc CLKID_I2C>;
 };
 
+&saradc {
+	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+	clocks = <&xtal>,
+		 <&clkc CLKID_SAR_ADC>,
+		 <&clkc CLKID_SANA>,
+		 <&clkc CLKID_SAR_ADC_CLK>,
+		 <&clkc CLKID_SAR_ADC_SEL>;
+	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A>,
 		 <&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bb2842f8a08f..6b63296b6c60 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -273,6 +273,16 @@
 	clocks = <&clkc CLKID_I2C>;
 };
 
+&saradc {
+	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+	clocks = <&xtal>,
+		 <&clkc CLKID_SAR_ADC>,
+		 <&clkc CLKID_SANA>,
+		 <&clkc CLKID_SAR_ADC_CLK>,
+		 <&clkc CLKID_SAR_ADC_SEL>;
+	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A>,
 		 <&xtal>,
-- 
2.11.0

^ permalink raw reply related

* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111174334.24343-1-martin.blumenstingl@googlemail.com>

This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.

The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.

Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.

Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
  accuracy of the results - in my tests the results were less than 3%
  off without calibration compared to the vendor driver). Adding support
  for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
  Adding support for this is probably not so easy since (based on the
  u-boot sources) most SoC versions are using different registers and
  algorithms for the conversion from "ADC value" to temperature.

Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
  buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
  individually because otherwise the ADC would be drawing power
  constantly)
- interrupt support (similar to the vendor driver this new driver is
  polling the results. It is unclear if the IRQ-mode is supported on
  older (Meson6 or Meson8) hardware as well or if there are any errata)

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/iio/adc/Kconfig        |  12 +
 drivers/iio/adc/Makefile       |   1 +
 drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 873 insertions(+)
 create mode 100644 drivers/iio/adc/meson_saradc.c

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
 	  This driver can also be built as a module. If so, the module will be
 	  called men_z188_adc.
 
+config MESON_SARADC
+	tristate "Amlogic Meson SAR ADC driver"
+	default ARCH_MESON
+	depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+	select REGMAP_MMIO
+	help
+	  Say yes here to build support for the SAR ADC found in Amlogic Meson
+	  SoCs.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called meson_saradc.
+
 config MXS_LRADC
         tristate "Freescale i.MX23/i.MX28 LRADC"
         depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
 obj-$(CONFIG_MCP3422) += mcp3422.o
 obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
 obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
 obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
 obj-$(CONFIG_NAU7802) += nau7802.o
 obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..06e8ac620385
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,860 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0						0x00
+	#define SAR_ADC_REG0_PANEL_DETECT			BIT(31)
+	#define SAR_ADC_REG0_BUSY_MASK				GENMASK(30, 28)
+	#define SAR_ADC_REG0_DELTA_BUSY				BIT(30)
+	#define SAR_ADC_REG0_AVG_BUSY				BIT(29)
+	#define SAR_ADC_REG0_SAMPLE_BUSY			BIT(28)
+	#define SAR_ADC_REG0_FIFO_FULL				BIT(27)
+	#define SAR_ADC_REG0_FIFO_EMPTY				BIT(26)
+	#define SAR_ADC_REG0_FIFO_COUNT_MASK			GENMASK(25, 21)
+	#define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK			GENMASK(20, 19)
+	#define SAR_ADC_REG0_CURR_CHAN_ID_MASK			GENMASK(18, 16)
+	#define SAR_ADC_REG0_ADC_TEMP_SEN_SEL			BIT(15)
+	#define SAR_ADC_REG0_SAMPLING_STOP			BIT(14)
+	#define SAR_ADC_REG0_CHAN_DELTA_EN_MASK			GENMASK(13, 12)
+	#define SAR_ADC_REG0_DETECT_IRQ_POL			BIT(10)
+	#define SAR_ADC_REG0_DETECT_IRQ_EN			BIT(9)
+	#define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK			GENMASK(8, 4)
+	#define SAR_ADC_REG0_FIFO_IRQ_EN			BIT(3)
+	#define SAR_ADC_REG0_SAMPLING_START			BIT(2)
+	#define SAR_ADC_REG0_CONTINUOUS_EN			BIT(1)
+	#define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE		BIT(0)
+
+#define SAR_ADC_CHAN_LIST					0x04
+	#define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK		GENMASK(26, 24)
+	#define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan)		\
+					(GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL					0x08
+	#define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan)		\
+					(16 + (_chan * 2))
+	#define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan)		\
+					(GENMASK(17, 16) << (_chan * 2))
+	#define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan)	\
+					(0 + (_chan * 2))
+	#define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan)	\
+					(GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3						0x0c
+	#define SAR_ADC_REG3_CNTL_USE_SC_DLY			BIT(31)
+	#define SAR_ADC_REG3_CLK_EN				BIT(30)
+	#define SAR_ADC_REG3_BL30_INITIALIZED			BIT(28)
+	#define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN		BIT(27)
+	#define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE		BIT(26)
+	#define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK		GENMASK(25, 23)
+	#define SAR_ADC_REG3_DETECT_EN				BIT(22)
+	#define SAR_ADC_REG3_ADC_EN				BIT(21)
+	#define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK		GENMASK(20, 18)
+	#define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK	GENMASK(17, 16)
+	#define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT			10
+	#define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH			5
+	#define SAR_ADC_REG3_ADC_CLK_DIV_MASK			GENMASK(15, 10)
+	#define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK			GENMASK(9, 8)
+	#define SAR_ADC_REG3_BLOCK_DLY_MASK			GENMASK(7, 0)
+
+#define SAR_ADC_DELAY						0x10
+	#define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK		GENMASK(25, 24)
+	#define SAR_ADC_DELAY_BL30_BUSY				BIT(15)
+	#define SAR_ADC_DELAY_KERNEL_BUSY			BIT(14)
+	#define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK		GENMASK(23, 16)
+	#define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK		GENMASK(9, 8)
+	#define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK		GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD						0x14
+	#define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK		GENMASK(23, 16)
+	#define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK		GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD						0x18
+	#define SAR_ADC_FIFO_RD_CHAN_ID_MASK			GENMASK(14, 12)
+	#define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK		GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW						0x1c
+	#define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan)		\
+					(GENMASK(10, 8) << ((_chan - 2) * 2))
+	#define SAR_ADC_AUX_SW_VREF_P_MUX			BIT(6)
+	#define SAR_ADC_AUX_SW_VREF_N_MUX			BIT(5)
+	#define SAR_ADC_AUX_SW_MODE_SEL				BIT(4)
+	#define SAR_ADC_AUX_SW_YP_DRIVE_SW			BIT(3)
+	#define SAR_ADC_AUX_SW_XP_DRIVE_SW			BIT(2)
+	#define SAR_ADC_AUX_SW_YM_DRIVE_SW			BIT(1)
+	#define SAR_ADC_AUX_SW_XM_DRIVE_SW			BIT(0)
+
+#define SAR_ADC_CHAN_10_SW					0x20
+	#define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK		GENMASK(25, 23)
+	#define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX		BIT(22)
+	#define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX		BIT(21)
+	#define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL		BIT(20)
+	#define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW		BIT(19)
+	#define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW		BIT(18)
+	#define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW		BIT(17)
+	#define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW		BIT(16)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK		GENMASK(9, 7)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX		BIT(6)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX		BIT(5)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL		BIT(4)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW		BIT(3)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW		BIT(2)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW		BIT(1)
+	#define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW		BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW					0x24
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN		BIT(26)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK	GENMASK(25, 23)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX	BIT(22)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX	BIT(21)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL		BIT(20)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW	BIT(19)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW	BIT(18)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW	BIT(17)
+	#define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW	BIT(16)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK	GENMASK(9, 7)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX	BIT(6)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX	BIT(5)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL		BIT(4)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW	BIT(3)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW	BIT(2)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW	BIT(1)
+	#define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW	BIT(0)
+
+#define SAR_ADC_DELTA_10					0x28
+	#define SAR_ADC_DELTA_10_TEMP_SEL			BIT(27)
+	#define SAR_ADC_DELTA_10_TS_REVE1			BIT(26)
+	#define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT	16
+	#define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK		GENMASK(25, 16)
+	#define SAR_ADC_DELTA_10_TS_REVE0			BIT(15)
+	#define SAR_ADC_DELTA_10_TS_C_SHIFT			11
+	#define SAR_ADC_DELTA_10_TS_C_MASK			GENMASK(14, 11)
+	#define SAR_ADC_DELTA_10_TS_VBG_EN			BIT(10)
+	#define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT	0
+	#define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK		GENMASK(9, 0)
+
+/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11						0x2c
+	#define SAR_ADC_REG11_BANDGAP_EN			BIT(13)
+
+#define SAR_ADC_REG13						0x34
+	#define SAR_ADC_REG13_12BIT_CALIBRATION_MASK		GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE		32
+#define SAR_ADC_NUM_CHANNELS		ARRAY_SIZE(meson_saradc_iio_channels)
+#define SAR_ADC_VALUE_MASK(_priv)	(BIT(_priv->resolution) - 1)
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) {				\
+	.type = _type,							\
+	.indexed = true,						\
+	.channel = _chan,						\
+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
+				BIT(IIO_CHAN_INFO_AVERAGE_RAW),		\
+	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
+	.datasheet_name = "SAR_ADC_CH"#_chan,				\
+}
+
+/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+	MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+	MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+	MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+	MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+	MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+	MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+	MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+	MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+	IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+	NO_AVERAGING = 0x0,
+	MEAN_AVERAGING = 0x1,
+	MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+	ONE_SAMPLE = 0x0,
+	TWO_SAMPLES = 0x1,
+	FOUR_SAMPLES = 0x2,
+	EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+	CHAN7_MUX_VSS = 0x0,
+	CHAN7_MUX_VDD_DIV4 = 0x1,
+	CHAN7_MUX_VDD_DIV2 = 0x2,
+	CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+	CHAN7_MUX_VDD = 0x4,
+	CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_priv {
+	struct regmap			*regmap;
+	struct clk			*clkin;
+	struct clk			*core_clk;
+	struct clk			*sana_clk;
+	struct clk			*adc_sel_clk;
+	struct clk			*adc_clk;
+	struct clk_gate			clk_gate;
+	struct clk			*adc_div_clk;
+	struct clk_divider		clk_div;
+	struct regulator		*vref;
+	struct completion		completion;
+	u8				resolution;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	u32 regval;
+
+	regmap_read(priv->regmap, SAR_ADC_REG0, &regval);
+
+	return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	int regval, timeout = 10000;
+
+	do {
+		udelay(1);
+		regmap_read(priv->regmap, SAR_ADC_REG0, &regval);
+	} while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+	if (timeout < 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+					const struct iio_chan_spec *chan,
+					int *val)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+	ret = meson_saradc_wait_busy_clear(indio_dev);
+	if (ret)
+		return ret;
+
+	regmap_read(priv->regmap, SAR_ADC_REG0, &regval);
+
+	while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+	       count < SAR_ADC_MAX_FIFO_SIZE) {
+		regmap_read(priv->regmap, SAR_ADC_FIFO_RD, &regval);
+
+		fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+		if (fifo_chan == chan->channel) {
+			fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+					     regval) & SAR_ADC_VALUE_MASK(priv);
+			sum += fifo_val;
+			count++;
+		}
+	}
+
+	if (!count)
+		return -ENOENT;
+
+	*val = sum / count;
+
+	return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+				       const struct iio_chan_spec *chan,
+				       enum meson_saradc_avg_mode mode,
+				       enum meson_saradc_num_samples samples)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	u32 val;
+
+	val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+	regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+			   SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+			   val);
+
+	val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+	regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+			   SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+					const struct iio_chan_spec *chan)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	u32 regval;
+
+	/* the SAR ADC engine allows sampling multiple channels at the same
+	 * time. to keep it simple we're only working with one *internal*
+	 * channel, which starts counting at index 0 (which means: count = 1).
+	 */
+	regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+	regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+			   SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+	/* map channel index 0 to the channel which we want to read */
+	regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+	regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+			   SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+	regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+			    chan->channel);
+	regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+			   SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+			   regval);
+
+	regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+			    chan->channel);
+	regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+			   SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+			   regval);
+
+	if (chan->channel == 6)
+		regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+				   SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+					  enum meson_saradc_chan7_mux_sel sel)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	u32 regval;
+
+	regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+	regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+			   SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+	usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+	regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+			   SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+			   SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+	regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+			   SAR_ADC_REG0_SAMPLING_START,
+			   SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+	regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+			   SAR_ADC_REG0_SAMPLING_STOP,
+			   SAR_ADC_REG0_SAMPLING_STOP);
+
+	/* wait until all modules are stopped */
+	meson_saradc_wait_busy_clear(indio_dev);
+
+	regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+			   SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	int val;
+
+	mutex_lock(&indio_dev->mlock);
+
+	/* prevent BL30 from using the SAR ADC while we are using it */
+	regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+			   SAR_ADC_DELAY_KERNEL_BUSY,
+			   SAR_ADC_DELAY_KERNEL_BUSY);
+
+	/* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+	do {
+		udelay(1);
+		regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+	} while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+	/* allow BL30 to use the SAR ADC again */
+	regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+			   SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+	mutex_unlock(&indio_dev->mlock);
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+				   const struct iio_chan_spec *chan,
+				   enum meson_saradc_avg_mode avg_mode,
+				   enum meson_saradc_num_samples avg_samples,
+				   int *val)
+{
+	int ret, tmp;
+
+	meson_saradc_lock(indio_dev);
+
+	/* clear old values from the FIFO buffer, ignoring errors */
+	meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
+
+	meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+	meson_saradc_enable_channel(indio_dev, chan);
+
+	meson_saradc_start_sample_engine(indio_dev);
+	ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+	meson_saradc_stop_sample_engine(indio_dev);
+
+	meson_saradc_unlock(indio_dev);
+
+	if (ret) {
+		dev_warn(&indio_dev->dev,
+			 "failed to read sample for channel %d: %d\n",
+			 chan->channel, ret);
+		return ret;
+	}
+
+	return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+					  const struct iio_chan_spec *chan,
+					  int *val, int *val2, long mask)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	int ret;
+
+	switch (mask) {
+	case IIO_CHAN_INFO_RAW:
+		return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+					       ONE_SAMPLE, val);
+		break;
+
+	case IIO_CHAN_INFO_AVERAGE_RAW:
+		return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+					       EIGHT_SAMPLES, val);
+		break;
+
+	case IIO_CHAN_INFO_SCALE:
+		ret = regulator_get_voltage(priv->vref);
+		if (ret < 0) {
+			dev_err(&indio_dev->dev,
+				"failed to get vref voltage: %d\n", ret);
+			return ret;
+		}
+
+		*val = ret / 1000;
+		*val2 = priv->resolution;
+		return IIO_VAL_FRACTIONAL_LOG2;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	struct clk_init_data init;
+	char clk_name[32];
+	const char *clk_parents[1];
+
+	snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
+		 of_node_full_name(indio_dev->dev.of_node));
+	init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+	init.flags = 0;
+	init.ops = &clk_divider_ops;
+	clk_parents[0] = __clk_get_name(priv->clkin);
+	init.parent_names = clk_parents;
+	init.num_parents = 1;
+
+	priv->clk_div.reg = base + SAR_ADC_REG3;
+	priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+	priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+	priv->clk_div.hw.init = &init;
+	priv->clk_div.flags = 0;
+
+	priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+					      &priv->clk_div.hw);
+	if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+		return PTR_ERR(priv->adc_div_clk);
+
+	snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
+		 of_node_full_name(indio_dev->dev.of_node));
+	init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+	init.flags = CLK_SET_RATE_PARENT;
+	init.ops = &clk_gate_ops;
+	clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+	init.parent_names = clk_parents;
+	init.num_parents = 1;
+
+	priv->clk_gate.reg = base + SAR_ADC_REG3;
+	priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+	priv->clk_gate.hw.init = &init;
+
+	priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+	if (WARN_ON(IS_ERR(priv->adc_clk)))
+		return PTR_ERR(priv->adc_clk);
+
+	return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	int regval, ret;
+
+	/* make sure we start at CH7 input */
+	meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+	regmap_read(priv->regmap, SAR_ADC_REG3, &regval);
+	if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
+		dev_info(&indio_dev->dev, "already initialized by BL30\n");
+		return 0;
+	}
+
+	dev_info(&indio_dev->dev, "initializing SAR ADC\n");
+
+	meson_saradc_stop_sample_engine(indio_dev);
+
+	/* update the channel 6 MUX to select the temperature sensor */
+	regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+			SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+			SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+	/* disable all channels by default */
+	regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+	regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+			   SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+	regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+			   SAR_ADC_REG3_CNTL_USE_SC_DLY,
+			   SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+	/* delay between two samples = (10+1) * 1uS */
+	regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+			   SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+			   FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+	regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+			   SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+			   FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+	/* delay between two samples = (10+1) * 1uS */
+	regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+			   SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+			   FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+	regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+			   SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+			   FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+	if (ret) {
+		dev_err(&indio_dev->dev,
+			"failed to set adc parent to clkin\n");
+		return ret;
+	}
+
+	ret = clk_set_rate(priv->adc_clk, 1200000);
+	if (ret) {
+		dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+	int ret;
+
+	meson_saradc_lock(indio_dev);
+
+	ret = regulator_enable(priv->vref);
+	if (ret < 0) {
+		dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
+		goto err_vref;
+	}
+
+	ret = clk_prepare_enable(priv->core_clk);
+	if (ret) {
+		dev_err(&indio_dev->dev, "failed to enable core clk\n");
+		goto err_core_clk;
+	}
+
+	ret = clk_prepare_enable(priv->sana_clk);
+	if (ret) {
+		dev_err(&indio_dev->dev, "failed to enable sana clk\n");
+		goto err_sana_clk;
+	}
+
+	regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+			   SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+	regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+			   SAR_ADC_REG3_ADC_EN);
+
+	udelay(5);
+
+	ret = clk_prepare_enable(priv->adc_clk);
+	if (ret) {
+		dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
+		goto err_adc_clk;
+	}
+
+	meson_saradc_unlock(indio_dev);
+
+	return 0;
+
+err_adc_clk:
+	clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+	clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+	regulator_disable(priv->vref);
+err_vref:
+	meson_saradc_unlock(indio_dev);
+	return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+	struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+	meson_saradc_lock(indio_dev);
+
+	clk_disable_unprepare(priv->adc_clk);
+
+	regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+	regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+			   SAR_ADC_REG11_BANDGAP_EN, 0);
+
+	clk_disable_unprepare(priv->sana_clk);
+	clk_disable_unprepare(priv->core_clk);
+
+	regulator_disable(priv->vref);
+
+	meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+	.read_raw = meson_saradc_iio_info_read_raw,
+	.driver_module = THIS_MODULE,
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+	{
+		.compatible = "amlogic,meson-gxbb-saradc",
+		.data = (void *)10,
+	}, {
+		.compatible = "amlogic,meson-gxl-saradc",
+		.data = (void *)12,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+	struct meson_saradc_priv *priv;
+	struct iio_dev *indio_dev;
+	struct resource *res;
+	void __iomem *base;
+	const struct of_device_id *match;
+	int ret;
+
+	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+	if (!indio_dev) {
+		dev_err(&pdev->dev, "failed allocating iio device\n");
+		return -ENOMEM;
+	}
+
+	priv = iio_priv(indio_dev);
+
+	match = of_match_device(meson_saradc_of_match, &pdev->dev);
+	priv->resolution = (unsigned long)match->data;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+					     &meson_saradc_regmap_config);
+	if (IS_ERR(priv->regmap))
+		return PTR_ERR(priv->regmap);
+
+	init_completion(&priv->completion);
+
+	priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+	if (IS_ERR(priv->clkin)) {
+		dev_err(&pdev->dev, "failed to get clkin\n");
+		return PTR_ERR(priv->clkin);
+	}
+
+	priv->core_clk = devm_clk_get(&pdev->dev, "core");
+	if (IS_ERR(priv->core_clk)) {
+		dev_err(&pdev->dev, "failed to get core clk\n");
+		return PTR_ERR(priv->core_clk);
+	}
+
+	priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+	if (IS_ERR(priv->sana_clk)) {
+		if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+			priv->sana_clk = NULL;
+		} else {
+			dev_err(&pdev->dev, "failed to get sana clk\n");
+			return PTR_ERR(priv->sana_clk);
+		}
+	}
+
+	priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+	if (IS_ERR(priv->adc_clk)) {
+		if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+			priv->adc_clk = NULL;
+		} else {
+			dev_err(&pdev->dev, "failed to get adc clk\n");
+			return PTR_ERR(priv->adc_clk);
+		}
+	}
+
+	priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+	if (IS_ERR(priv->adc_sel_clk)) {
+		if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+			priv->adc_sel_clk = NULL;
+		} else {
+			dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+			return PTR_ERR(priv->adc_sel_clk);
+		}
+	}
+
+	/* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+	if (!priv->adc_clk) {
+		ret = meson_saradc_clk_init(indio_dev, base);
+		if (ret)
+			return ret;
+	}
+
+	priv->vref = devm_regulator_get(&pdev->dev, "vref");
+	if (IS_ERR(priv->vref)) {
+		dev_err(&pdev->dev, "failed to get vref regulator\n");
+		return PTR_ERR(priv->vref);
+	}
+
+	ret = meson_saradc_init(indio_dev);
+	if (ret)
+		goto err;
+
+	ret = meson_saradc_hw_enable(indio_dev);
+	if (ret)
+		goto err;
+
+	platform_set_drvdata(pdev, indio_dev);
+
+	indio_dev->name = dev_name(&pdev->dev);
+	indio_dev->dev.parent = &pdev->dev;
+	indio_dev->dev.of_node = pdev->dev.of_node;
+	indio_dev->modes = INDIO_DIRECT_MODE;
+	indio_dev->info = &meson_saradc_iio_info;
+
+	indio_dev->channels = meson_saradc_iio_channels;
+	indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
+
+	ret = iio_device_register(indio_dev);
+	if (ret)
+		goto err_hw;
+
+	return 0;
+
+err_hw:
+	meson_saradc_hw_disable(indio_dev);
+err:
+	return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+	meson_saradc_hw_disable(indio_dev);
+	iio_device_unregister(indio_dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+	meson_saradc_hw_disable(indio_dev);
+
+	return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+	return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+			 meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+	.probe		= meson_saradc_probe,
+	.remove		= meson_saradc_remove,
+	.driver		= {
+		.name	= "meson-saradc",
+		.of_match_table = meson_saradc_of_match,
+		.pm = &meson_saradc_pm_ops,
+	},
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
-- 
2.11.0

^ permalink raw reply related

* [PATCH 2/4] clk: gxbb: add the SAR ADC clocks and expose them
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111174334.24343-1-martin.blumenstingl@googlemail.com>

The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
  2-bit wide, but the datasheet only lists the parents for the first
  bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock

Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/gxbb.c              | 48 +++++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h              |  9 ++++---
 include/dt-bindings/clock/gxbb-clkc.h |  4 +++
 3 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
 	},
 };
 
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+	.reg = (void *)HHI_SAR_CLK_CNTL,
+	.mask = 0x3,
+	.shift = 9,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "sar_adc_clk_sel",
+		.ops = &clk_mux_ops,
+		/* NOTE: The datasheet doesn't list the parents for bit 10 */
+		.parent_names = (const char *[]){ "xtal", "clk81", },
+		.num_parents = 2,
+	},
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+	.reg = (void *)HHI_SAR_CLK_CNTL,
+	.shift = 0,
+	.width = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "sar_adc_clk_div",
+		.ops = &clk_divider_ops,
+		.parent_names = (const char *[]){ "sar_adc_clk_sel" },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+	.reg = (void *)HHI_SAR_CLK_CNTL,
+	.bit_idx = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "sar_adc_clk",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "sar_adc_clk_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_SD_EMMC_A]	    = &gxbb_emmc_a.hw,
 		[CLKID_SD_EMMC_B]	    = &gxbb_emmc_b.hw,
 		[CLKID_SD_EMMC_C]	    = &gxbb_emmc_c.hw,
+		[CLKID_SAR_ADC_CLK]	    = &gxbb_sar_adc_clk.hw,
+		[CLKID_SAR_ADC_SEL]	    = &gxbb_sar_adc_clk_sel.hw,
+		[CLKID_SAR_ADC_DIV]	    = &gxbb_sar_adc_clk_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
 	&gxbb_emmc_a,
 	&gxbb_emmc_b,
 	&gxbb_emmc_c,
+	&gxbb_sar_adc_clk,
 };
 
 static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
 	gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
 	gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
 
+	/* Populate the base address for the SAR ADC clks */
+	gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+	gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
 	/* Populate base address for gates */
 	for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
 		gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
 #define CLKID_PERIPHS		  20
 #define CLKID_SPICC		  21
 /* CLKID_I2C */
-#define CLKID_SAR_ADC		  23
+/* #define CLKID_SAR_ADC */
 #define CLKID_SMART_CARD	  24
 #define CLKID_RNG0		  25
 #define CLKID_UART0		  26
@@ -237,7 +237,7 @@
 #define CLKID_MMC_PCLK		  66
 #define CLKID_DVIN		  67
 #define CLKID_UART2		  68
-#define CLKID_SANA		  69
+/* #define CLKID_SANA */
 #define CLKID_VPU_INTR		  70
 #define CLKID_SEC_AHB_AHB3_BRIDGE 71
 #define CLKID_CLK81_A53		  72
@@ -265,8 +265,11 @@
 /* CLKID_SD_EMMC_A */
 /* CLKID_SD_EMMC_B */
 /* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV	  99
 
-#define NR_CLKS			  97
+#define NR_CLKS			  100
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
 #define CLKID_MPLL2		15
 #define CLKID_SPI		34
 #define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
 #define CLKID_ETH		36
 #define CLKID_USB0		50
 #define CLKID_USB1		51
 #define CLKID_USB		55
 #define CLKID_USB1_DDR_BRIDGE	64
 #define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_SANA		69
 #define CLKID_AO_I2C		93
 #define CLKID_SD_EMMC_A		94
 #define CLKID_SD_EMMC_B		95
 #define CLKID_SD_EMMC_C		96
+#define CLKID_SAR_ADC_CLK	97
+#define CLKID_SAR_ADC_SEL	98
 
 #endif /* __GXBB_CLKC_H */
-- 
2.11.0

^ permalink raw reply related

* [PATCH 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111174334.24343-1-martin.blumenstingl@googlemail.com>

This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 .../bindings/iio/adc/amlogic,meson-saradc.txt      | 31 ++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt

diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible:	depending on the SoC this should be one of:
+			- "amlogic,meson-gxbb-saradc" for GXBB
+			- "amlogic,meson-gxl-saradc" for GXL and GXM
+		along with the generic "amlogic,meson-saradc"
+- reg:		the physical base address and length of the registers
+- clocks:	phandle and clock identifier (see clock-names)
+- clock-names:	mandatory clocks:
+			- "clkin" for the reference clock (typically XTAL)
+			- "core" for the SAR ADC core clock
+		optional clocks:
+			- "sana" for the analog clock
+			- "adc_clk" for the ADC (sampling) clock
+			- "adc_sel" for the ADC (sampling) clock mux
+- vref-supply:	the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+	saradc: adc at 8680 {
+		compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+		#io-channel-cells = <1>;
+		reg = <0x0 0x8680 0x0 0x34>;
+		clocks = <&xtal>,
+			 <&clkc CLKID_SAR_ADC>,
+			 <&clkc CLKID_SANA>,
+			 <&clkc CLKID_SAR_ADC_CLK>,
+			 <&clkc CLKID_SAR_ADC_SEL>;
+		clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+	};
-- 
2.11.0

^ permalink raw reply related

* [PATCH 0/4] Amlogic Meson SAR ADC support
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
  To: linux-arm-kernel

This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).

A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.

The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.

The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.

Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
  the system firmware does this already and provides the values via the
  SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
  the board-revision)
- and of course typical ADC measurements


Martin Blumenstingl (4):
  Documentation: dt-bindings: add the Amlogic Meson SAR ADC
    documentation
  clk: gxbb: add the SAR ADC clocks and expose them
  iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
  ARM64: dts: meson: meson-gx: add the SAR ADC

 .../bindings/iio/adc/amlogic,meson-saradc.txt      |  31 +
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi          |   8 +
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi        |  10 +
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi         |  10 +
 drivers/clk/meson/gxbb.c                           |  48 ++
 drivers/clk/meson/gxbb.h                           |   9 +-
 drivers/iio/adc/Kconfig                            |  12 +
 drivers/iio/adc/Makefile                           |   1 +
 drivers/iio/adc/meson_saradc.c                     | 860 +++++++++++++++++++++
 include/dt-bindings/clock/gxbb-clkc.h              |   4 +
 10 files changed, 990 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
 create mode 100644 drivers/iio/adc/meson_saradc.c

-- 
2.11.0

^ permalink raw reply

* [RFC PATCH 1/2] ARM: vfp - allow kernel mode NEON in softirq context
From: Ard Biesheuvel @ 2017-01-11 17:40 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1483991849-32448-2-git-send-email-ard.biesheuvel@linaro.org>

On 9 January 2017 at 19:57, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> This updates the kernel mode NEON handling to allow the NEON to be used
> in softirq context as well as process context. This involves disabling
> softirq processing when the NEON is used in kernel mode in process context,
> and dealing with the situation where 'current' is not the owner of the
> userland context that is present in the NEON register file when the NEON
> is enabled in kernel mode.
>
> The rationale for this change is that the NEON is shared with the ARMv8
> Crypto Extensions (which are also defined for the AArch32 execution state),
> which can give a huge performance boost (15x) to use cases like mac80211
> CCMP processing, which executes in softirq context.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  arch/arm/vfp/vfpmodule.c | 22 ++++++++++++++------
>  1 file changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
> index 569d5a650a4a..814752811537 100644
> --- a/arch/arm/vfp/vfpmodule.c
> +++ b/arch/arm/vfp/vfpmodule.c
> @@ -690,26 +690,33 @@ void kernel_neon_begin(void)
>         u32 fpexc;
>
>         /*
> -        * Kernel mode NEON is only allowed outside of interrupt context
> +        * Kernel mode NEON is only allowed outside of hardirq context
>          * with preemption disabled. This will make sure that the kernel
>          * mode NEON register contents never need to be preserved.
>          */
> -       BUG_ON(in_interrupt());
> +       BUG_ON(in_irq());
>         cpu = get_cpu();
>
> +       /*
> +        * Disable softirq processing while the NEON is used by the kernel in
> +        * process context. This ensures that only a single kernel mode NEON
> +        * state is live at any given time.
> +        */
> +       if (!in_serving_softirq())
> +               local_bh_disable();
> +
>         fpexc = fmrx(FPEXC) | FPEXC_EN;
>         fmxr(FPEXC, fpexc);
>
>         /*
> -        * Save the userland NEON/VFP state. Under UP,
> -        * the owner could be a task other than 'current'
> +        * Save the userland NEON/VFP state. Under UP, or when executing in
> +        * softirq context, the owner could be a task other than 'current'
>          */
>         if (vfp_state_in_hw(cpu, thread))
>                 vfp_save_state(&thread->vfpstate, fpexc);
> -#ifndef CONFIG_SMP
>         else if (vfp_current_hw_state[cpu] != NULL)
>                 vfp_save_state(vfp_current_hw_state[cpu], fpexc);
> -#endif
> +

Actually, I think this should not be necessary (and the change to the
comment is incorrect). Whether we're in process or softirq context
makes no difference here, and the comment is slightly confusing: under
SMP, the owner could also be a task other than 'current', but due to
the eager preserve, the latest userland NEON state will already have
been recorded, and there is no need doing it again.

>         vfp_current_hw_state[cpu] = NULL;
>  }
>  EXPORT_SYMBOL(kernel_neon_begin);
> @@ -718,7 +725,10 @@ void kernel_neon_end(void)
>  {
>         /* Disable the NEON/VFP unit. */
>         fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
> +       if (!in_serving_softirq())
> +               local_bh_enable();
>         put_cpu();
> +
>  }
>  EXPORT_SYMBOL(kernel_neon_end);
>
> --
> 2.7.4
>

^ permalink raw reply

* [PATCH 56/62] watchdog: tangox_wdt: Convert to use device managed functions
From: Guenter Roeck @ 2017-01-11 17:28 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170111143917.hedhyfu6m5dopag7@pengutronix.de>

On Wed, Jan 11, 2017 at 03:39:17PM +0100, Uwe Kleine-K?nig wrote:
> On Wed, Jan 11, 2017 at 01:31:47PM +0100, Marc Gonzalez wrote:
> > On 11/01/2017 11:52, Guenter Roeck wrote:
> > 
> > > On 01/11/2017 01:07 AM, Marc Gonzalez wrote:
> > > 
> > >>> @@ -134,12 +134,15 @@ static int tangox_wdt_probe(struct platform_device *pdev)
> > >>>  	err = clk_prepare_enable(dev->clk);
> > >>>  	if (err)
> > >>>  		return err;
> > >>> +	err = devm_add_action_or_reset(&pdev->dev,
> > >>> +				       (void(*)(void *))clk_disable_unprepare,
> > >>> +				       dev->clk);
> > >>> +	if (err)
> > >>> +		return err;
> 
> This looks wrong. There is no clk_unprepare_disable when
> devm_add_action_or_reset fails.
> 
That is what the _or_reset part of devm_add_action_or_reset() is for.

> > >>
> > >> Hello Guenter,
> > >>
> > >> I would rather avoid the function pointer cast.
> > >> How about defining an auxiliary function for the cleanup action?
> > >>
> > >> clk_disable_unprepare() is static inline, so gcc will have to
> > >> define an auxiliary function either way. What do you think?
> > > 
> > > Not really. It would just make it more complicated to replace the
> > > call with devm_clk_prepare_enable(), should it ever find its way
> > > into the light of day.
> > 
> > More complicated, because the cleanup function will have to be deleted later?
> > The compiler will warn if someone forgets to do that.
> > 
> > In my opinion, it's not a good idea to rely on the fact that casting
> > void(*)(struct clk *clk) to void(*)(void *) is likely to work as expected
> > on most platforms. (It has undefined behavior, strictly speaking.)
> 
> I would expect it to work on all (Linux) platforms. Anyhow, I wonder if
> there couldn't be found a better solution.
> 
> If in the end it looks like the following that would be good I think:
> 
> 	clk = devm_clk_get(...);
> 	if (IS_ERR(clk))
> 		...
> 
> 	ret = devm_clk_prepare_enable(clk)
> 	if (ret)
> 		return ret;
> 
Yes, Dmitry tried to introduce devm_clk_prepare_enable() some 5 years ago,
but the effort stalled.

My take is that it will be easy to write another coccinelle script to convert
to devm_clk_prepare_enable() once that is available, but I didn't see the point
of waiting for that, especially since it may never happen.

Guenter

^ permalink raw reply

* [PATCH v5 12/12] arm64: configs: enable SDHCI driver for Xenon
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 869dded0f09f..341fc631f598 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -390,6 +390,7 @@ CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_K3=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SUNXI=y
+CONFIG_MMC_SDHCI_XENON=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

Also enable it on the Armada 7040 DB board

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts       | 14 +++++++++++++-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 10 +++++++++-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 11 ++++++++++-
 3 files changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 070b589680c5..6adbfcd26369 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -146,3 +146,17 @@
 &cpm_usb3_1 {
 	status = "okay";
 };
+
+&ap_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
+
+&cpm_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 5019c8f4acd0..0b49cbda8539 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -229,6 +229,16 @@
 
 			};
 
+			ap_sdhci0: sdhci at 6e0000 {
+				compatible = "marvell,armada-8k-sdhci";
+				reg = <0x6e0000 0x300>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "core";
+				clocks = <&ap_syscon 4>;
+				dma-coherent;
+				status = "disabled";
+			};
+
 			ap_syscon: system-controller at 6f4000 {
 				compatible = "marvell,ap806-system-controller",
 					     "syscon";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 05222f749a45..421e91049cf7 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -172,6 +172,17 @@
 				clocks = <&cpm_syscon0 1 25>;
 				status = "okay";
 			};
+
+			cpm_sdhci0: sdhci at 780000 {
+				compatible = "marvell,armada-8k-sdhci";
+				reg = <0x780000 0x300>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "core";
+				clocks = <&cpm_syscon0 1 4>;
+				dma-coherent;
+				status = "disabled";
+			};
+
 		};
 
 		cpm_pcie0: pcie at f2600000 {
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 10/12] arm64: dts: marvell: add eMMC support for Armada 37xx
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-3720-db.dts | 16 ++++++++++++++++
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 11 +++++++++++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 89de0a751093..118796b325e5 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -72,6 +72,22 @@
 	status = "okay";
 };
 
+&sdhci0 {
+	non-removable;
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	marvell,pad-type = "fixed-1-8v";
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard at 0 {
+		compatible = "mmc-card";
+		reg = <0>;
+	};
+};
+
 /* CON31 */
 &usb3 {
 	status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index bab5c6ff5745..966b6f030bfa 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -184,6 +184,17 @@
 				};
 			};
 
+			sdhci0: sdhci at d8000 {
+				compatible = "marvell,armada-3700-sdhci",
+				"marvell,sdhci-xenon";
+				reg = <0xd8000 0x300
+				       0x17808 0x4>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&nb_periph_clk 0>;
+				clock-names = "core";
+				status = "disabled";
+			};
+
 			sata: sata at e0000 {
 				compatible = "marvell,armada-3700-ahci";
 				reg = <0xe0000 0x2000>;
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 09/12] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

From: Hu Ziji <huziji@marvell.com>

Add maintainer entry for Marvell Xenon eMMC/SD/SDIO
Host Controller drivers.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cfff2c9e3d94..f4fea77165d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7757,6 +7757,13 @@ M:	Nicolas Pitre <nico@fluxnic.net>
 S:	Odd Fixes
 F:	drivers/mmc/host/mvsdio.*
 
+MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
+M:	Ziji Hu <huziji@marvell.com>
+L:	linux-mmc at vger.kernel.org
+S:	Supported
+F:	drivers/mmc/host/sdhci-xenon*
+F:	Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
+
 MATROX FRAMEBUFFER DRIVER
 L:	linux-fbdev at vger.kernel.org
 S:	Orphan
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 08/12] mmc: sdhci-xenon: Add SoC PHY PAD voltage control
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

From: Hu Ziji <huziji@marvell.com>

Some SoCs have PHY PAD outside Xenon IP.
PHY PAD voltage should match signalling voltage in use.

Add generic SoC PHY PAD voltage control interface.
Implement Aramda-3700 SoC PHY PAD voltage control.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci-xenon-phy.c | 116 +++++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci-xenon.c     |   2 +-
 drivers/mmc/host/sdhci-xenon.h     |   2 +-
 3 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
index f410712d24ea..1221754b7a3d 100644
--- a/drivers/mmc/host/sdhci-xenon-phy.c
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -143,6 +143,27 @@ enum phy_type_enum {
 	NR_PHY_TYPES
 };
 
+enum soc_pad_ctrl_type {
+	SOC_PAD_SD,
+	SOC_PAD_FIXED_1_8V,
+};
+
+struct soc_pad_ctrl_table {
+	const char *soc;
+	void (*set_soc_pad)(struct sdhci_host *host,
+			    unsigned char signal_voltage);
+};
+
+struct soc_pad_ctrl {
+	/* Register address of SOC PHY PAD ctrl */
+	void __iomem	*reg;
+	/* SOC PHY PAD ctrl type */
+	enum soc_pad_ctrl_type pad_type;
+	/* SOC specific operation to set SOC PHY PAD */
+	void (*set_soc_pad)(struct sdhci_host *host,
+			    unsigned char signal_voltage);
+};
+
 static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
 	.timing_adj	= XENON_EMMC_5_0_PHY_TIMING_ADJUST,
 	.func_ctrl	= XENON_EMMC_5_0_PHY_FUNC_CONTROL,
@@ -176,6 +197,8 @@ struct emmc_phy_params {
 	u8	nr_tun_times;
 	/* Divider for calculating Tuning Step */
 	u8	tun_step_divider;
+
+	struct soc_pad_ctrl pad_ctrl;
 };
 
 static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
@@ -252,6 +275,45 @@ static int emmc_phy_init(struct sdhci_host *host)
 	return 0;
 }
 
+#define ARMADA_3700_SOC_PAD_1_8V	0x1
+#define ARMADA_3700_SOC_PAD_3_3V	0x0
+
+static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
+					    unsigned char signal_voltage)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+
+	if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {
+		writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+	} else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {
+		if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+			writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+		else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+			writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
+	}
+}
+
+/*
+ * Set SOC PHY voltage PAD control register,
+ * according to the operation voltage on PAD.
+ * The detailed operation depends on SOC implementaion.
+ */
+static void emmc_phy_set_soc_pad(struct sdhci_host *host,
+				 unsigned char signal_voltage)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+
+	if (!params->pad_ctrl.reg)
+		return;
+
+	if (params->pad_ctrl.set_soc_pad)
+		params->pad_ctrl.set_soc_pad(host, signal_voltage);
+}
+
 /*
  * Enable eMMC PHY HW DLL
  * DLL should be enabled and stable before HS200/SDR104 tuning,
@@ -621,6 +683,51 @@ static void emmc_phy_set(struct sdhci_host *host,
 	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
 }
 
+static int get_dt_pad_ctrl_data(struct sdhci_host *host,
+				struct device_node *np,
+				struct emmc_phy_params *params)
+{
+	int ret = 0;
+	const char *name;
+	struct resource iomem;
+
+	if (of_device_is_compatible(np, "marvell,armada-3700-sdhci"))
+		params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;
+	else
+		return 0;
+
+	if (of_address_to_resource(np, 1, &iomem)) {
+		dev_err(mmc_dev(host->mmc), "Unable to find SOC PAD ctrl register address for %s\n",
+			np->name);
+		return -EINVAL;
+	}
+
+	params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
+						     &iomem);
+	if (IS_ERR(params->pad_ctrl.reg)) {
+		dev_err(mmc_dev(host->mmc), "Unable to get SOC PHY PAD ctrl regiser for %s\n",
+			np->name);
+		return PTR_ERR(params->pad_ctrl.reg);
+	}
+
+	ret = of_property_read_string(np, "marvell,pad-type", &name);
+	if (ret) {
+		dev_err(mmc_dev(host->mmc), "Unable to determine SOC PHY PAD ctrl type\n");
+		return ret;
+	}
+	if (!strcmp(name, "sd")) {
+		params->pad_ctrl.pad_type = SOC_PAD_SD;
+	} else if (!strcmp(name, "fixed-1-8v")) {
+		params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V;
+	} else {
+		dev_err(mmc_dev(host->mmc), "Unsupported SOC PHY PAD ctrl type %s\n",
+			name);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
 static int emmc_phy_parse_param_dt(struct sdhci_host *host,
 				   struct device_node *np,
 				   struct emmc_phy_params *params)
@@ -654,7 +761,14 @@ static int emmc_phy_parse_param_dt(struct sdhci_host *host,
 	else
 		params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
 
-	return 0;
+	return get_dt_pad_ctrl_data(host, np, params);
+}
+
+/* Set SOC PHY Voltage PAD */
+void xenon_soc_pad_ctrl(struct sdhci_host *host,
+			unsigned char signal_voltage)
+{
+	emmc_phy_set_soc_pad(host, signal_voltage);
 }
 
 /*
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index e51079b2d01c..be93af56c348 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -335,6 +335,8 @@ static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
 	 */
 	enable_xenon_internal_clk(host);
 
+	xenon_soc_pad_ctrl(host, ios->signal_voltage);
+
 	if (priv->init_card_type == MMC_TYPE_MMC)
 		return xenon_emmc_signal_voltage_switch(mmc, ios);
 
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index e87639774bca..57e7cb463413 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -104,4 +104,6 @@ struct sdhci_xenon_priv {
 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
 int xenon_phy_parse_dt(struct device_node *np,
 		       struct sdhci_host *host);
+void xenon_soc_pad_ctrl(struct sdhci_host *host,
+			unsigned char signal_voltage);
 #endif
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 07/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC.
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

From: Hu Ziji <huziji@marvell.com>

Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Multiple types of PHYs are supported.

Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.

Xenon PHY cannot fit in kernel common PHY framework.
Xenon SDHC PHY register is a part of Xenon SDHC register set.
Besides, MMC initialization has to call several PHY functions to
complete timing setting.
Those PHY setting functions have to access SDHC registers and know
current MMC setting, such as bus width, clock frequency and
speed mode.
As a result, implement Xenon PHY in MMC host directory.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/Makefile          |   2 +-
 drivers/mmc/host/sdhci-xenon-phy.c | 790 ++++++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci-xenon.c     |   3 +-
 drivers/mmc/host/sdhci-xenon.h     |  37 +-
 4 files changed, 830 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c

diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index b0a2ab4b256e..893b48db5513 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -84,4 +84,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
 endif
 
 obj-$(CONFIG_MMC_SDHCI_XENON)	+= sdhci-xenon-driver.o
-sdhci-xenon-driver-y		+= sdhci-xenon.o
+sdhci-xenon-driver-y		+= sdhci-xenon.o sdhci-xenon-phy.o
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
new file mode 100644
index 000000000000..f410712d24ea
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -0,0 +1,790 @@
+/*
+ * PHY support for Xenon SDHC
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author:	Hu Ziji <huziji@marvell.com>
+ * Date:	2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+/* Register base for eMMC PHY 5.0 Version */
+#define XENON_EMMC_5_0_PHY_REG_BASE		0x0160
+/* Register base for eMMC PHY 5.1 Version */
+#define XENON_EMMC_PHY_REG_BASE			0x0170
+
+#define XENON_EMMC_PHY_TIMING_ADJUST		XENON_EMMC_PHY_REG_BASE
+#define XENON_EMMC_5_0_PHY_TIMING_ADJUST	XENON_EMMC_5_0_PHY_REG_BASE
+#define XENON_TIMING_ADJUST_SLOW_MODE		BIT(29)
+#define XENON_TIMING_ADJUST_SDIO_MODE		BIT(28)
+#define XENON_OUTPUT_QSN_PHASE_SELECT		BIT(17)
+#define XENON_SAMPL_INV_QSP_PHASE_SELECT	BIT(18)
+#define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT	18
+#define XENON_PHY_INITIALIZAION			BIT(31)
+#define XENON_WAIT_CYCLE_BEFORE_USING_MASK	0xF
+#define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT	12
+#define XENON_FC_SYNC_EN_DURATION_MASK		0xF
+#define XENON_FC_SYNC_EN_DURATION_SHIFT		8
+#define XENON_FC_SYNC_RST_EN_DURATION_MASK	0xF
+#define XENON_FC_SYNC_RST_EN_DURATION_SHIFT	4
+#define XENON_FC_SYNC_RST_DURATION_MASK		0xF
+#define XENON_FC_SYNC_RST_DURATION_SHIFT	0
+
+#define XENON_EMMC_PHY_FUNC_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x4)
+#define XENON_EMMC_5_0_PHY_FUNC_CONTROL		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x4)
+#define XENON_ASYNC_DDRMODE_MASK		BIT(23)
+#define XENON_ASYNC_DDRMODE_SHIFT		23
+#define XENON_CMD_DDR_MODE			BIT(16)
+#define XENON_DQ_DDR_MODE_SHIFT			8
+#define XENON_DQ_DDR_MODE_MASK			0xFF
+#define XENON_DQ_ASYNC_MODE			BIT(4)
+
+#define XENON_EMMC_PHY_PAD_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x8)
+#define XENON_EMMC_5_0_PHY_PAD_CONTROL		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x8)
+#define XENON_REC_EN_SHIFT			24
+#define XENON_REC_EN_MASK			0xF
+#define XENON_FC_DQ_RECEN			BIT(24)
+#define XENON_FC_CMD_RECEN			BIT(25)
+#define XENON_FC_QSP_RECEN			BIT(26)
+#define XENON_FC_QSN_RECEN			BIT(27)
+#define XENON_OEN_QSN				BIT(28)
+#define XENON_AUTO_RECEN_CTRL			BIT(30)
+#define XENON_FC_ALL_CMOS_RECEIVER		0xF000
+
+#define XENON_EMMC5_FC_QSP_PD			BIT(18)
+#define XENON_EMMC5_FC_QSP_PU			BIT(22)
+#define XENON_EMMC5_FC_CMD_PD			BIT(17)
+#define XENON_EMMC5_FC_CMD_PU			BIT(21)
+#define XENON_EMMC5_FC_DQ_PD			BIT(16)
+#define XENON_EMMC5_FC_DQ_PU			BIT(20)
+
+#define XENON_EMMC_PHY_PAD_CONTROL1		(XENON_EMMC_PHY_REG_BASE + 0xC)
+#define XENON_EMMC5_1_FC_QSP_PD			BIT(9)
+#define XENON_EMMC5_1_FC_QSP_PU			BIT(25)
+#define XENON_EMMC5_1_FC_CMD_PD			BIT(8)
+#define XENON_EMMC5_1_FC_CMD_PU			BIT(24)
+#define XENON_EMMC5_1_FC_DQ_PD			0xFF
+#define XENON_EMMC5_1_FC_DQ_PU			(0xFF << 16)
+
+#define XENON_EMMC_PHY_PAD_CONTROL2		(XENON_EMMC_PHY_REG_BASE + 0x10)
+#define XENON_EMMC_5_0_PHY_PAD_CONTROL2		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0xC)
+#define XENON_ZNR_MASK				0x1F
+#define XENON_ZNR_SHIFT				8
+#define XENON_ZPR_MASK				0x1F
+/* Perferred ZNR and ZPR value vary between different boards.
+ * The specific ZNR and ZPR value should be defined here
+ * according to board actual timing.
+ */
+#define XENON_ZNR_DEF_VALUE			0xF
+#define XENON_ZPR_DEF_VALUE			0xF
+
+#define XENON_EMMC_PHY_DLL_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_5_0_PHY_DLL_CONTROL		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x10)
+#define XENON_DLL_ENABLE			BIT(31)
+#define XENON_DLL_UPDATE_STROBE_5_0		BIT(30)
+#define XENON_DLL_REFCLK_SEL			BIT(30)
+#define XENON_DLL_UPDATE			BIT(23)
+#define XENON_DLL_PHSEL1_SHIFT			24
+#define XENON_DLL_PHSEL0_SHIFT			16
+#define XENON_DLL_PHASE_MASK			0x3F
+#define XENON_DLL_PHASE_90_DEGREE		0x1F
+#define XENON_DLL_FAST_LOCK			BIT(5)
+#define XENON_DLL_GAIN2X			BIT(3)
+#define XENON_DLL_BYPASS_EN			BIT(0)
+
+#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST	\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST	(XENON_EMMC_PHY_REG_BASE + 0x18)
+#define XENON_LOGIC_TIMING_VALUE		0x00AA8977
+
+/*
+ * List offset of PHY registers and some special register values
+ * in eMMC PHY 5.0 or eMMC PHY 5.1
+ */
+struct xenon_emmc_phy_regs {
+	/* Offset of Timing Adjust register */
+	u16 timing_adj;
+	/* Offset of Func Control register */
+	u16 func_ctrl;
+	/* Offset of Pad Control register */
+	u16 pad_ctrl;
+	/* Offset of Pad Control register 2 */
+	u16 pad_ctrl2;
+	/* Offset of DLL Control register */
+	u16 dll_ctrl;
+	/* Offset of Logic Timing Adjust register */
+	u16 logic_timing_adj;
+	/* DLL Update Enable bit */
+	u32 dll_update;
+};
+
+static const char * const phy_types[] = {
+	"emmc 5.0 phy",
+	"emmc 5.1 phy"
+};
+
+enum phy_type_enum {
+	EMMC_5_0_PHY,
+	EMMC_5_1_PHY,
+	NR_PHY_TYPES
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
+	.timing_adj	= XENON_EMMC_5_0_PHY_TIMING_ADJUST,
+	.func_ctrl	= XENON_EMMC_5_0_PHY_FUNC_CONTROL,
+	.pad_ctrl	= XENON_EMMC_5_0_PHY_PAD_CONTROL,
+	.pad_ctrl2	= XENON_EMMC_5_0_PHY_PAD_CONTROL2,
+	.dll_ctrl	= XENON_EMMC_5_0_PHY_DLL_CONTROL,
+	.logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
+	.dll_update	= XENON_DLL_UPDATE_STROBE_5_0,
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
+	.timing_adj	= XENON_EMMC_PHY_TIMING_ADJUST,
+	.func_ctrl	= XENON_EMMC_PHY_FUNC_CONTROL,
+	.pad_ctrl	= XENON_EMMC_PHY_PAD_CONTROL,
+	.pad_ctrl2	= XENON_EMMC_PHY_PAD_CONTROL2,
+	.dll_ctrl	= XENON_EMMC_PHY_DLL_CONTROL,
+	.logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
+	.dll_update	= XENON_DLL_UPDATE,
+};
+
+/*
+ * eMMC PHY configuration and operations
+ */
+struct emmc_phy_params {
+	bool	slow_mode;
+
+	u8	znr;
+	u8	zpr;
+
+	/* Nr of consecutive Sampling Points of a Valid Sampling Window */
+	u8	nr_tun_times;
+	/* Divider for calculating Tuning Step */
+	u8	tun_step_divider;
+};
+
+static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
+{
+	struct emmc_phy_params *params;
+
+	params = kzalloc(sizeof(*params), GFP_KERNEL);
+	if (!params)
+		return -ENOMEM;
+
+	priv->phy_params = params;
+	if (priv->phy_type == EMMC_5_0_PHY)
+		priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;
+	else
+		priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;
+
+	return 0;
+}
+
+/*
+ * eMMC 5.0/5.1 PHY init/re-init.
+ * eMMC PHY init should be executed after:
+ * 1. SDCLK frequecny changes.
+ * 2. SDCLK is stopped and re-enabled.
+ * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
+ * are changed
+ */
+static int emmc_phy_init(struct sdhci_host *host)
+{
+	u32 reg;
+	u32 wait, clock;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	reg |= XENON_PHY_INITIALIZAION;
+	sdhci_writel(host, reg, phy_regs->timing_adj);
+
+	/* Add duration of FC_SYNC_RST */
+	wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) &
+			XENON_FC_SYNC_RST_DURATION_MASK);
+	/* Add interval between FC_SYNC_EN and FC_SYNC_RST */
+	wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) &
+			XENON_FC_SYNC_RST_EN_DURATION_MASK);
+	/* Add duration of asserting FC_SYNC_EN */
+	wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) &
+			XENON_FC_SYNC_EN_DURATION_MASK);
+	/* Add duration of waiting for PHY */
+	wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) &
+			XENON_WAIT_CYCLE_BEFORE_USING_MASK);
+	/* 4 addtional bus clock and 4 AXI bus clock are required */
+	wait += 8;
+	wait <<= 20;
+
+	clock = host->clock;
+	if (!clock)
+		/* Use the possibly slowest bus frequency value */
+		clock = XENON_LOWEST_SDCLK_FREQ;
+	/* get the wait time */
+	wait /= clock;
+	wait++;
+	/* wait for host eMMC PHY init completes */
+	udelay(wait);
+
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	reg &= XENON_PHY_INITIALIZAION;
+	if (reg) {
+		dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
+			wait);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+/*
+ * Enable eMMC PHY HW DLL
+ * DLL should be enabled and stable before HS200/SDR104 tuning,
+ * and before HS400 data strobe setting.
+ */
+static int emmc_phy_enable_dll(struct sdhci_host *host)
+{
+	u32 reg;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+	u8 timeout;
+
+	if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
+		return -EINVAL;
+
+	reg = sdhci_readl(host, phy_regs->dll_ctrl);
+	if (reg & XENON_DLL_ENABLE)
+		return 0;
+
+	/* Enable DLL */
+	reg = sdhci_readl(host, phy_regs->dll_ctrl);
+	reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK);
+
+	/*
+	 * Set Phase as 90 degree, which is most common value.
+	 * Might set another value if necessary.
+	 * The granularity is 1 degree.
+	 */
+	reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) |
+		 (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT));
+	reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) |
+		(XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT));
+
+	reg &= ~XENON_DLL_BYPASS_EN;
+	reg |= phy_regs->dll_update;
+	if (priv->phy_type == EMMC_5_1_PHY)
+		reg &= ~XENON_DLL_REFCLK_SEL;
+	sdhci_writel(host, reg, phy_regs->dll_ctrl);
+
+	/* Wait max 32 ms */
+	timeout = 32;
+	while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
+		XENON_DLL_LOCK_STATE)) {
+		if (!timeout) {
+			dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
+			return -ETIMEDOUT;
+		}
+		timeout--;
+		mdelay(1);
+	}
+	return 0;
+}
+
+/*
+ * Config to eMMC PHY to prepare for tuning.
+ * Enable HW DLL and set the TUNING_STEP
+ */
+static int emmc_phy_config_tuning(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+	u32 reg, tuning_step;
+	int ret;
+	unsigned long flags;
+
+	if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
+		return -EINVAL;
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	ret = emmc_phy_enable_dll(host);
+	if (ret) {
+		spin_unlock_irqrestore(&host->lock, flags);
+		return ret;
+	}
+
+	/* Achieve TUNGING_STEP with HW DLL help */
+	reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
+	tuning_step = reg / params->tun_step_divider;
+	if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) {
+		dev_warn(mmc_dev(host->mmc),
+			 "HS200 TUNING_STEP %d is larger than MAX value\n",
+			 tuning_step);
+		tuning_step = XENON_TUNING_STEP_MASK;
+	}
+
+	/* Set TUNING_STEP for later tuning */
+	reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
+	reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK <<
+		 XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
+	reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
+	reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT);
+	reg |= (tuning_step << XENON_TUNING_STEP_SHIFT);
+	sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
+
+	spin_unlock_irqrestore(&host->lock, flags);
+	return 0;
+}
+
+static void __emmc_phy_disable_data_strobe(struct sdhci_host *host)
+{
+	u32 reg;
+
+	/* Disable SDHC Data Strobe */
+	reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+	reg &= ~XENON_ENABLE_DATA_STROBE;
+	sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
+}
+
+/* Set HS400 Data Strobe */
+static void emmc_phy_strobe_delay_adj(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	unsigned long flags;
+	u32 reg;
+
+	if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
+		return;
+
+	if (host->clock <= MMC_HIGH_52_MAX_DTR)
+		return;
+
+	dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	emmc_phy_enable_dll(host);
+
+	/* Enable SDHC Data Strobe */
+	reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+	reg |= XENON_ENABLE_DATA_STROBE;
+	sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
+
+	/* Set Data Strobe Pull down */
+	if (priv->phy_type == EMMC_5_0_PHY) {
+		reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+		reg |= XENON_EMMC5_FC_QSP_PD;
+		reg &= ~XENON_EMMC5_FC_QSP_PU;
+		sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+	} else {
+		reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
+		reg |= XENON_EMMC5_1_FC_QSP_PD;
+		reg &= ~XENON_EMMC5_1_FC_QSP_PU;
+		sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static inline bool temp_stage_hs200_to_hs400(struct sdhci_host *host,
+					     struct sdhci_xenon_priv *priv)
+{
+	/*
+	 * Tmep stages from HS200 to HS400
+	 * from HS200 to HS in 200MHz
+	 * from 200MHz to 52MHz
+	 */
+	if (((priv->timing == MMC_TIMING_MMC_HS200) &&
+	     (host->timing == MMC_TIMING_MMC_HS)) ||
+	    ((host->timing == MMC_TIMING_MMC_HS) &&
+	     (priv->clock > host->clock)))
+		return true;
+
+	return false;
+}
+
+static inline bool temp_stage_hs400_to_h200(struct sdhci_host *host,
+					    struct sdhci_xenon_priv *priv)
+{
+	/*
+	 * Temp stages from HS400 t0 HS200:
+	 * from 200MHz to 52MHz in HS400
+	 * from HS400 to HS DDR in 52MHz
+	 * from HS DDR to HS in 52MHz
+	 * from HS to HS200 in 52MHz
+	 */
+	if (((priv->timing == MMC_TIMING_MMC_HS400) &&
+	     ((host->clock == MMC_HIGH_52_MAX_DTR) ||
+	      (host->timing == MMC_TIMING_MMC_DDR52))) ||
+	    ((priv->timing == MMC_TIMING_MMC_DDR52) &&
+	     (host->timing == MMC_TIMING_MMC_HS)) ||
+	    ((host->timing == MMC_TIMING_MMC_HS200) &&
+	     (host->clock == MMC_HIGH_52_MAX_DTR)))
+		return true;
+
+	return false;
+}
+
+/*
+ * If eMMC PHY Slow Mode is required in lower speed mode in SDR mode
+ * (SDLCK < 55MHz), enable Slow Mode to bypass eMMC PHY.
+ * SDIO slower SDR mode also requires Slow Mode.
+ *
+ * If Slow Mode is enabled, return true.
+ * Otherwise, return false.
+ */
+static bool emmc_phy_slow_mode(struct sdhci_host *host,
+			       unsigned char timing)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+	u32 reg;
+
+	/* Skip temp stages from HS200 to HS400 */
+	if (temp_stage_hs200_to_hs400(host, priv))
+		return false;
+
+	/* Skip temp stages from HS400 t0 HS200 */
+	if (temp_stage_hs400_to_h200(host, priv))
+		return false;
+
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	/* Enable Slow Mode for SDIO in slower SDR mode */
+	if ((priv->init_card_type == MMC_TYPE_SDIO) &&
+	    ((timing == MMC_TIMING_UHS_SDR25) ||
+	     (timing == MMC_TIMING_UHS_SDR12) ||
+	     (timing == MMC_TIMING_SD_HS) ||
+	     (timing == MMC_TIMING_LEGACY))) {
+		reg |= XENON_TIMING_ADJUST_SLOW_MODE;
+		sdhci_writel(host, reg, phy_regs->timing_adj);
+		return true;
+	}
+
+	/* Check if Slow Mode is required in lower speed mode in SDR mode */
+	if (((timing == MMC_TIMING_UHS_SDR50) ||
+	     (timing == MMC_TIMING_UHS_SDR25) ||
+	     (timing == MMC_TIMING_UHS_SDR12) ||
+	     (timing == MMC_TIMING_SD_HS) ||
+	     (timing == MMC_TIMING_MMC_HS) ||
+	     (timing == MMC_TIMING_LEGACY)) && params->slow_mode) {
+		reg |= XENON_TIMING_ADJUST_SLOW_MODE;
+		sdhci_writel(host, reg, phy_regs->timing_adj);
+		return true;
+	}
+
+	reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
+	sdhci_writel(host, reg, phy_regs->timing_adj);
+	return false;
+}
+
+/*
+ * Set-up eMMC 5.0/5.1 PHY.
+ * Specific onfiguration depends on the current speed mode in use.
+ */
+static void emmc_phy_set(struct sdhci_host *host,
+			 unsigned char timing)
+{
+	u32 reg;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+	unsigned long flags;
+
+	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	/* Setup pad, set bit[28] and bits[26:24] */
+	reg = sdhci_readl(host, phy_regs->pad_ctrl);
+	reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
+		XENON_FC_QSP_RECEN | XENON_OEN_QSN);
+	/* All FC_XX_RECEIVCE should be set as CMOS Type */
+	reg |= XENON_FC_ALL_CMOS_RECEIVER;
+	sdhci_writel(host, reg, phy_regs->pad_ctrl);
+
+	/* Set CMD and DQ Pull Up */
+	if (priv->phy_type == EMMC_5_0_PHY) {
+		reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+		reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);
+		reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);
+		sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+	} else {
+		reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
+		reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);
+		reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);
+		sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
+	}
+
+	if (timing == MMC_TIMING_LEGACY)
+		goto phy_init;
+
+	/*
+	 * FIXME: should depends on the specific board timing.
+	 */
+	if ((timing == MMC_TIMING_MMC_HS400) ||
+	    (timing == MMC_TIMING_MMC_HS200) ||
+	    (timing == MMC_TIMING_UHS_SDR50) ||
+	    (timing == MMC_TIMING_UHS_SDR104) ||
+	    (timing == MMC_TIMING_UHS_DDR50) ||
+	    (timing == MMC_TIMING_UHS_SDR25) ||
+	    (timing == MMC_TIMING_MMC_DDR52)) {
+		reg = sdhci_readl(host, phy_regs->timing_adj);
+		reg &= ~XENON_OUTPUT_QSN_PHASE_SELECT;
+		sdhci_writel(host, reg, phy_regs->timing_adj);
+	}
+
+	/*
+	 * If SDIO card, set SDIO Mode
+	 * Otherwise, clear SDIO Mode
+	 */
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	if (priv->init_card_type == MMC_TYPE_SDIO)
+		reg |= XENON_TIMING_ADJUST_SDIO_MODE;
+	else
+		reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
+	sdhci_writel(host, reg, phy_regs->timing_adj);
+
+	if (emmc_phy_slow_mode(host, timing))
+		goto phy_init;
+
+	/*
+	 * Set preferred ZNR and ZPR value
+	 * The ZNR and ZPR value vary between different boards.
+	 * Define them both in sdhci-xenon-emmc-phy.h.
+	 */
+	reg = sdhci_readl(host, phy_regs->pad_ctrl2);
+	reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
+	reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);
+	sdhci_writel(host, reg, phy_regs->pad_ctrl2);
+
+	/*
+	 * When setting EMMC_PHY_FUNC_CONTROL register,
+	 * SD clock should be disabled
+	 */
+	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+	reg &= ~SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+	reg = sdhci_readl(host, phy_regs->func_ctrl);
+	if ((timing == MMC_TIMING_UHS_DDR50) ||
+	    (timing == MMC_TIMING_MMC_HS400) ||
+	    (timing == MMC_TIMING_MMC_DDR52))
+		reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
+		       XENON_CMD_DDR_MODE;
+	else
+		reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
+			 XENON_CMD_DDR_MODE);
+
+	if (timing == MMC_TIMING_MMC_HS400)
+		reg &= ~XENON_DQ_ASYNC_MODE;
+	else
+		reg |= XENON_DQ_ASYNC_MODE;
+	sdhci_writel(host, reg, phy_regs->func_ctrl);
+
+	/* Enable bus clock */
+	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+	reg |= SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+	if (timing == MMC_TIMING_MMC_HS400)
+		/* Hardware team recommend a value for HS400 */
+		sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
+			     phy_regs->logic_timing_adj);
+	else
+		__emmc_phy_disable_data_strobe(host);
+
+phy_init:
+	emmc_phy_init(host);
+
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
+}
+
+static int emmc_phy_parse_param_dt(struct sdhci_host *host,
+				   struct device_node *np,
+				   struct emmc_phy_params *params)
+{
+	u32 value;
+
+	if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
+		params->slow_mode = true;
+	else
+		params->slow_mode = false;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
+		params->znr = value & XENON_ZNR_MASK;
+	else
+		params->znr = XENON_ZNR_DEF_VALUE;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
+		params->zpr = value & XENON_ZPR_MASK;
+	else
+		params->zpr = XENON_ZPR_DEF_VALUE;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
+				  &value))
+		params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
+	else
+		params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
+				  &value))
+		params->tun_step_divider = value & 0xFF;
+	else
+		params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
+
+	return 0;
+}
+
+/*
+ * Setting PHY when card is working in High Speed Mode.
+ * HS400 set data strobe line.
+ * HS200/SDR104 set tuning config to prepare for tuning.
+ */
+static int xenon_hs_delay_adj(struct sdhci_host *host)
+{
+	int ret = 0;
+
+	if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
+		return -EINVAL;
+
+	if (host->timing == MMC_TIMING_MMC_HS400) {
+		emmc_phy_strobe_delay_adj(host);
+		return 0;
+	}
+
+	if ((host->timing == MMC_TIMING_MMC_HS200) ||
+	    (host->timing == MMC_TIMING_UHS_SDR104)) {
+		ret = emmc_phy_config_tuning(host);
+		if (!ret)
+			return 0;
+	}
+
+	/*
+	 * DDR Mode requires driver to scan Sampling Fixed Delay Line,
+	 * to find out a perfect operation sampling point.
+	 * It is hard to implement such a scan in host driver since initiating
+	 * commands by host driver is not safe.
+	 * Thus so far just keep PHY Sampling Fixed Delay in default value
+	 * in DDR mode.
+	 *
+	 * If any timing issue occrus in DDR mode on Marvell products,
+	 * please contact maintainer to ask for internal support in Marvell.
+	 */
+	if ((host->timing == MMC_TIMING_MMC_DDR52) ||
+	    (host->timing == MMC_TIMING_UHS_DDR50))
+		dev_warn(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
+	return ret;
+}
+
+/*
+ * Adjust PHY setting.
+ * PHY setting should be adjusted when SDCLK frequency, Bus Width
+ * or Speed Mode is changed.
+ * Addtional config are required when card is working in High Speed mode,
+ * after leaving Legacy Mode.
+ */
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	int ret = 0;
+
+	if (!host->clock) {
+		priv->clock = 0;
+		return 0;
+	}
+
+	/*
+	 * The timing, frequency or bus width is changed,
+	 * better to set eMMC PHY based on current setting
+	 * and adjust Xenon SDHC delay.
+	 */
+	if ((host->clock == priv->clock) &&
+	    (ios->bus_width == priv->bus_width) &&
+	    (ios->timing == priv->timing))
+		return 0;
+
+	emmc_phy_set(host, ios->timing);
+
+	/* Update the record */
+	priv->bus_width = ios->bus_width;
+
+	/* Skip temp stages from HS200 to HS400 */
+	if (temp_stage_hs200_to_hs400(host, priv))
+		return 0;
+
+	/* Skip temp stages from HS400 t0 HS200 */
+	if (temp_stage_hs400_to_h200(host, priv))
+		return 0;
+
+	priv->timing = ios->timing;
+	priv->clock = host->clock;
+
+	/* Legacy mode is a special case */
+	if (ios->timing == MMC_TIMING_LEGACY)
+		return 0;
+
+	if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
+		ret = xenon_hs_delay_adj(host);
+	return ret;
+}
+
+static int add_xenon_phy(struct device_node *np, struct sdhci_host *host,
+			 const char *phy_name)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	int i, ret;
+
+	for (i = 0; i < NR_PHY_TYPES; i++) {
+		if (!strcmp(phy_name, phy_types[i])) {
+			priv->phy_type = i;
+			break;
+		}
+	}
+	if (i == NR_PHY_TYPES) {
+		dev_err(mmc_dev(host->mmc),
+			"Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
+			phy_name);
+		priv->phy_type = EMMC_5_1_PHY;
+	}
+
+	ret = alloc_emmc_phy(priv);
+	if (ret)
+		return ret;
+
+	return emmc_phy_parse_param_dt(host, np, priv->phy_params);
+}
+
+int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
+{
+	const char *phy_type = NULL;
+
+	if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
+		return add_xenon_phy(np, host, phy_type);
+
+	dev_info(mmc_dev(host->mmc), "Fail to get Xenon PHY type. Use default eMMC 5.1 PHY\n");
+	return add_xenon_phy(np, host, "emmc 5.1 phy");
+}
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index 0e0c60892f72..e51079b2d01c 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -257,6 +257,7 @@ static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	spin_unlock_irqrestore(&host->lock, flags);
 
 	sdhci_set_ios(mmc, ios);
+	xenon_phy_adj(host, ios);
 
 	if (host->clock > XENON_DEFAULT_SDCLK_FREQ) {
 		spin_lock_irqsave(&host->lock, flags);
@@ -502,7 +503,7 @@ static int xenon_probe_dt(struct platform_device *pdev)
 	}
 	priv->tuning_count = tuning_count;
 
-	return err;
+	return xenon_phy_parse_dt(np, host);
 }
 
 static int xenon_sdhc_probe(struct sdhci_host *host)
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index 69de711db9eb..e87639774bca 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -24,7 +24,17 @@
 #define XENON_SYS_EXT_OP_CTRL			0x010C
 #define XENON_MASK_CMD_CONFLICT_ERR		BIT(8)
 
+#define XENON_SLOT_OP_STATUS_CTRL		0x0128
+
+#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT	16
+#define XENON_TUN_CONSECUTIVE_TIMES_MASK	0x7
+#define XENON_TUN_CONSECUTIVE_TIMES		0x4
+#define XENON_TUNING_STEP_SHIFT			12
+#define XENON_TUNING_STEP_MASK			0xF
+#define XENON_TUNING_STEP_DIVIDER		BIT(6)
+
 #define XENON_SLOT_EMMC_CTRL			0x0130
+#define XENON_ENABLE_DATA_STROBE		BIT(24)
 #define XENON_EMMC_VCCQ_MASK			0x3
 #define XENON_EMMC_VCCQ_1_8V			0x1
 #define XENON_EMMC_VCCQ_3_3V			0x3
@@ -33,11 +43,17 @@
 /* retuning compatible */
 #define XENON_RETUNING_COMPATIBLE		0x1
 
+#define XENON_SLOT_EXT_PRESENT_STATE		0x014C
+#define XENON_DLL_LOCK_STATE			0x1
+
+#define XENON_SLOT_DLL_CUR_DLY_VAL		0x0150
+
 /* Tuning Parameter */
 #define XENON_TMR_RETUN_NO_PRESENT		0xF
 #define XENON_DEF_TUNING_COUNT			0x9
 
 #define XENON_DEFAULT_SDCLK_FREQ		400000
+#define XENON_LOWEST_SDCLK_FREQ			100000
 
 /* Xenon specific Mode Select value */
 #define XENON_CTRL_HS200			0x5
@@ -65,6 +81,27 @@ struct sdhci_xenon_priv {
 	 * initialization completes.
 	 */
 	unsigned int	init_card_type;
+
+	/*
+	 * The bus_width, timing, and clock fields in below
+	 * record the current ios setting of Xenon SDHC.
+	 * Driver will adjust PHY setting if any change to
+	 * ios affects PHY timing.
+	 */
+	unsigned char	bus_width;
+	unsigned char	timing;
+	unsigned int	clock;
+
+	int		phy_type;
+	/*
+	 * Contains board-specific PHY parameters
+	 * passed from device tree.
+	 */
+	void		*phy_params;
+	struct xenon_emmc_phy_regs *emmc_phy_regs;
 };
 
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
+int xenon_phy_parse_dt(struct device_node *np,
+		       struct sdhci_host *host);
 #endif
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 06/12] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

From: Hu Ziji <huziji@marvell.com>

Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific intialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.

Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.

Marvell Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/Kconfig       |   9 +-
 drivers/mmc/host/Makefile      |   3 +-
 drivers/mmc/host/sdhci-xenon.c | 631 ++++++++++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci-xenon.h |  70 ++++-
 4 files changed, 713 insertions(+)
 create mode 100644 drivers/mmc/host/sdhci-xenon.c
 create mode 100644 drivers/mmc/host/sdhci-xenon.h

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 2eb97014dc3f..8d2d08de14a0 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -819,3 +819,12 @@ config MMC_SDHCI_BRCMSTB
 	  Broadcom STB SoCs.
 
 	  If unsure, say Y.
+
+config MMC_SDHCI_XENON
+	tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
+	depends on MMC_SDHCI && MMC_SDHCI_PLTFM
+	help
+	  This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+	  If you have a machine with integrated Marvell Xenon SDHC IP,
+	  say Y or M here.
+	  If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index ccc9c4cba154..b0a2ab4b256e 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -82,3 +82,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB)		+= sdhci-brcmstb.o
 ifeq ($(CONFIG_CB710_DEBUG),y)
 	CFLAGS-cb710-mmc	+= -DDEBUG
 endif
+
+obj-$(CONFIG_MMC_SDHCI_XENON)	+= sdhci-xenon-driver.o
+sdhci-xenon-driver-y		+= sdhci-xenon.o
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
new file mode 100644
index 000000000000..0e0c60892f72
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -0,0 +1,631 @@
+/*
+ * Driver for Marvell Xenon SDHC as a platform device
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author:	Hu Ziji <huziji@marvell.com>
+ * Date:	2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * Inspired by Jisheng Zhang <jszhang@marvell.com>
+ * Special thanks to Video BG4 project team.
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+static int enable_xenon_internal_clk(struct sdhci_host *host)
+{
+	u32 reg;
+	u8 timeout;
+
+	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+	reg |= SDHCI_CLOCK_INT_EN;
+	sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
+	/* Wait max 20 ms */
+	timeout = 20;
+	while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+			& SDHCI_CLOCK_INT_STABLE)) {
+		if (timeout == 0) {
+			pr_err("%s: Internal clock never stabilised.\n",
+			       mmc_hostname(host->mmc));
+			return -ETIMEDOUT;
+		}
+		timeout--;
+		mdelay(1);
+	}
+
+	return 0;
+}
+
+/* Set SDCLK-off-while-idle */
+static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
+				     unsigned char sdhc_id, bool enable)
+{
+	u32 reg;
+	u32 mask;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	/* Get the bit shift basing on the SDHC index */
+	mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
+	if (enable)
+		reg |= mask;
+	else
+		reg &= ~mask;
+
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable/Disable the Auto Clock Gating function */
+static void xenon_set_acg(struct sdhci_host *host, bool enable)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	if (enable)
+		reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
+	else
+		reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable this SDHC */
+static void xenon_enable_sdhc(struct sdhci_host *host,
+			      unsigned char sdhc_id)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+
+	/*
+	 * Manually set the flag which all the card types require,
+	 * including SD, eMMC, SDIO
+	 */
+	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+}
+
+/* Disable this SDHC */
+static void xenon_disable_sdhc(struct sdhci_host *host,
+			       unsigned char sdhc_id)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable Parallel Transfer Mode */
+static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
+					    unsigned char sdhc_id)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
+	reg |= BIT(sdhc_id);
+	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
+}
+
+/* Mask command conflict error */
+static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
+{
+	u32  reg;
+
+	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
+	reg |= XENON_MASK_CMD_CONFLICT_ERR;
+	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
+}
+
+static void xenon_sdhc_retune_setup(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg;
+
+	/* Disable the Re-Tuning Request functionality */
+	reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
+	reg &= ~XENON_RETUNING_COMPATIBLE;
+	sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
+
+	/* Disable the Re-tuning Interrupt */
+	reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
+	reg &= ~SDHCI_INT_RETUNE;
+	sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
+	reg = sdhci_readl(host, SDHCI_INT_ENABLE);
+	reg &= ~SDHCI_INT_RETUNE;
+	sdhci_writel(host, reg, SDHCI_INT_ENABLE);
+
+	/* Force to use Tuning Mode 1 */
+	host->tuning_mode = SDHCI_TUNING_MODE_1;
+	/* Set re-tuning period */
+	host->tuning_count = 1 << (priv->tuning_count - 1);
+}
+
+/*
+ * Operations inside struct sdhci_ops
+ */
+/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
+static void sdhci_xenon_reset_exit(struct sdhci_host *host,
+				   unsigned char sdhc_id, u8 mask)
+{
+	/* Only SOFTWARE RESET ALL will clear the register setting */
+	if (!(mask & SDHCI_RESET_ALL))
+		return;
+
+	/* Disable tuning request and auto-retuning again */
+	xenon_sdhc_retune_setup(host);
+
+	xenon_set_acg(host, true);
+
+	xenon_set_sdclk_off_idle(host, sdhc_id, false);
+}
+
+static void sdhci_xenon_reset(struct sdhci_host *host, u8 mask)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	sdhci_reset(host, mask);
+	sdhci_xenon_reset_exit(host, priv->sdhc_id, mask);
+}
+
+/*
+ * Xenon defines different values for HS200 and HS400
+ * in Host_Control_2
+ */
+static void xenon_set_uhs_signaling(struct sdhci_host *host,
+				    unsigned int timing)
+{
+	u16 ctrl_2;
+
+	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	/* Select Bus Speed Mode for host */
+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	if (timing == MMC_TIMING_MMC_HS200)
+		ctrl_2 |= XENON_CTRL_HS200;
+	else if (timing == MMC_TIMING_UHS_SDR104)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+	else if (timing == MMC_TIMING_UHS_SDR12)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+	else if (timing == MMC_TIMING_UHS_SDR25)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+	else if (timing == MMC_TIMING_UHS_SDR50)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+	else if ((timing == MMC_TIMING_UHS_DDR50) ||
+		 (timing == MMC_TIMING_MMC_DDR52))
+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+	else if (timing == MMC_TIMING_MMC_HS400)
+		ctrl_2 |= XENON_CTRL_HS400;
+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
+
+static const struct sdhci_ops sdhci_xenon_ops = {
+	.set_clock		= sdhci_set_clock,
+	.set_bus_width		= sdhci_set_bus_width,
+	.reset			= sdhci_xenon_reset,
+	.set_uhs_signaling	= xenon_set_uhs_signaling,
+	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
+};
+
+static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
+	.ops = &sdhci_xenon_ops,
+	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+		  SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
+		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+/*
+ * Xenon Specific Operations in mmc_host_ops
+ */
+static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	unsigned long flags;
+	u32 reg;
+
+	/*
+	 * HS400/HS200/eMMC HS doesn't have Preset Value register.
+	 * However, sdhci_set_ios will read HS400/HS200 Preset register.
+	 * Disable Preset Value register for HS400/HS200.
+	 * eMMC HS with preset_enabled set will trigger a bug in
+	 * get_preset_value().
+	 */
+	spin_lock_irqsave(&host->lock, flags);
+	if ((ios->timing == MMC_TIMING_MMC_HS400) ||
+	    (ios->timing == MMC_TIMING_MMC_HS200) ||
+	    (ios->timing == MMC_TIMING_MMC_HS)) {
+		host->preset_enabled = false;
+		host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+
+		reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+		reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+		sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+	} else {
+		host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	sdhci_set_ios(mmc, ios);
+
+	if (host->clock > XENON_DEFAULT_SDCLK_FREQ) {
+		spin_lock_irqsave(&host->lock, flags);
+		xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
+		spin_unlock_irqrestore(&host->lock, flags);
+	}
+}
+
+static int xenon_emmc_signal_voltage_switch(struct mmc_host *mmc,
+					    struct mmc_ios *ios)
+{
+	unsigned char voltage = ios->signal_voltage;
+	struct sdhci_host *host = mmc_priv(mmc);
+	unsigned char voltage_code;
+	u32 ctrl;
+
+	if ((voltage == MMC_SIGNAL_VOLTAGE_330) ||
+	    (voltage == MMC_SIGNAL_VOLTAGE_180)) {
+		if (voltage == MMC_SIGNAL_VOLTAGE_330)
+			voltage_code = XENON_EMMC_VCCQ_3_3V;
+		else if (voltage == MMC_SIGNAL_VOLTAGE_180)
+			voltage_code = XENON_EMMC_VCCQ_1_8V;
+
+		/*
+		 * This host is for eMMC, XENON self-defined
+		 * eMMC control register should be accessed
+		 * instead of Host Control 2
+		 */
+		ctrl = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+		ctrl &= ~XENON_EMMC_VCCQ_MASK;
+		ctrl |= voltage_code;
+		sdhci_writel(host, ctrl, XENON_SLOT_EMMC_CTRL);
+
+		/* There is no standard to determine this waiting period */
+		usleep_range(1000, 2000);
+
+		/* Check whether io voltage switch is done */
+		ctrl = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+		ctrl &= XENON_EMMC_VCCQ_MASK;
+		/*
+		 * This bit is set only when regulator feeds back
+		 * the voltage switch results to Xenon SDHC.
+		 * However, in actaul implementation, regulator might not
+		 * provide this feedback.
+		 * Thus we shall not rely on this bit to determine
+		 * if switch failed.
+		 * If the bit is not set, just throw a message.
+		 * Besides, error code should not be returned.
+		 */
+		if (ctrl != voltage_code)
+			dev_info(mmc_dev(mmc), "fail to detect eMMC signal voltage stable\n");
+		return 0;
+	}
+
+	dev_err(mmc_dev(mmc), "Unsupported signal voltage: %d\n", voltage);
+	return -EINVAL;
+}
+
+static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
+					     struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	/*
+	 * Before SD/SDIO set signal voltage, SD bus clock should be
+	 * disabled. However, sdhci_set_clock will also disable the Internal
+	 * clock in mmc_set_signal_voltage().
+	 * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
+	 * Thus here manually enable internal clock.
+	 *
+	 * After switch completes, it is unnecessary to disable internal clock,
+	 * since keeping internal clock active obeys SD spec.
+	 */
+	enable_xenon_internal_clk(host);
+
+	if (priv->init_card_type == MMC_TYPE_MMC)
+		return xenon_emmc_signal_voltage_switch(mmc, ios);
+
+	return sdhci_start_signal_voltage_switch(mmc, ios);
+}
+
+/*
+ * Update card type.
+ * priv->init_card_type will be used in PHY timing adjustment.
+ */
+static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	/* Update card type*/
+	priv->init_card_type = card->type;
+}
+
+static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+
+	if (host->timing == MMC_TIMING_UHS_DDR50)
+		return 0;
+
+	/*
+	 * Currently force Xenon driver back to support mode 1 only,
+	 * even though Xenon might claim to support mode 2 or mode 3.
+	 * It requires more time to test mode 2/mode 3 on more platforms.
+	 */
+	if (host->tuning_mode != SDHCI_TUNING_MODE_1)
+		xenon_sdhc_retune_setup(host);
+
+	return sdhci_execute_tuning(mmc, opcode);
+}
+
+static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg;
+	u8 sdhc_id = priv->sdhc_id;
+
+	sdhci_enable_sdio_irq(mmc, enable);
+
+	if (enable) {
+		/*
+		 * Set SDIO Card Inserted indication
+		 * to enable detecting SDIO async irq.
+		 */
+		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
+		reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
+		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
+	} else {
+		/* Clear SDIO Card Inserted indication */
+		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
+		reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
+		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
+	}
+}
+
+static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
+{
+	host->mmc_host_ops.set_ios = xenon_set_ios;
+	host->mmc_host_ops.start_signal_voltage_switch =
+			xenon_start_signal_voltage_switch;
+	host->mmc_host_ops.init_card = xenon_init_card;
+	host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
+	host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
+}
+
+/*
+ * Parse child node in Xenon DT.
+ * Search for the following item(s):
+ * - eMMC card type
+ */
+static int xenon_child_node_of_parse(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct mmc_host *mmc = host->mmc;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct device_node *child;
+	int nr_child;
+
+	priv->init_card_type = XENON_CARD_TYPE_UNKNOWN;
+
+	nr_child = of_get_child_count(np);
+	if (!nr_child)
+		return 0;
+
+	for_each_child_of_node(np, child) {
+		if (of_device_is_compatible(child, "mmc-card"))	{
+			priv->init_card_type = MMC_TYPE_MMC;
+			mmc->caps |= MMC_CAP_NONREMOVABLE;
+
+			/*
+			 * Force to clear BUS_TEST to
+			 * skip bus_test_pre and bus_test_post
+			 */
+			mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
+			mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ |
+				      MMC_CAP2_PACKED_CMD |
+				      MMC_CAP2_NO_SD |
+				      MMC_CAP2_NO_SDIO;
+		}
+	}
+
+	return 0;
+}
+
+static int xenon_probe_dt(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct mmc_host *mmc = host->mmc;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	int err;
+	u32 sdhc_id, nr_sdhc;
+	u32 tuning_count;
+
+	/* Standard MMC property */
+	err = mmc_of_parse(mmc);
+	if (err)
+		return err;
+
+	/* Standard SDHCI property */
+	sdhci_get_of_property(pdev);
+
+	/*
+	 * Xenon Specific property:
+	 * init_card_type: check whether this SDHC is for eMMC
+	 * sdhc-id: the index of current SDHC.
+	 *	    Refer to XENON_SYS_CFG_INFO register
+	 * tun-count: the interval between re-tuning
+	 */
+	/* Parse child node, including checking emmc type */
+	err = xenon_child_node_of_parse(pdev);
+	if (err)
+		return err;
+
+	priv->sdhc_id = 0x0;
+	if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
+		nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
+		nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
+		if (unlikely(sdhc_id > nr_sdhc)) {
+			dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
+				sdhc_id, nr_sdhc);
+			return -EINVAL;
+		}
+	}
+
+	tuning_count = XENON_DEF_TUNING_COUNT;
+	if (!of_property_read_u32(np, "marvell,xenon-tun-count",
+				  &tuning_count)) {
+		if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
+			dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
+				XENON_DEF_TUNING_COUNT);
+			tuning_count = XENON_DEF_TUNING_COUNT;
+		}
+	}
+	priv->tuning_count = tuning_count;
+
+	return err;
+}
+
+static int xenon_sdhc_probe(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u8 sdhc_id = priv->sdhc_id;
+
+	/* Enable SDHC */
+	xenon_enable_sdhc(host, sdhc_id);
+
+	/* Enable ACG */
+	xenon_set_acg(host, true);
+
+	/* Enable Parallel Transfer Mode */
+	xenon_enable_sdhc_parallel_tran(host, sdhc_id);
+
+	xenon_mask_cmd_conflict_err(host);
+
+	return 0;
+}
+
+static void xenon_sdhc_remove(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u8 sdhc_id = priv->sdhc_id;
+
+	/* disable SDHC */
+	xenon_disable_sdhc(host, sdhc_id);
+}
+
+static int sdhci_xenon_probe(struct platform_device *pdev)
+{
+	struct sdhci_pltfm_host *pltfm_host;
+	struct sdhci_host *host;
+	struct sdhci_xenon_priv *priv;
+	int err;
+
+	host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
+				sizeof(struct sdhci_xenon_priv));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	pltfm_host = sdhci_priv(host);
+	priv = sdhci_pltfm_priv(pltfm_host);
+
+	xenon_set_acg(host, false);
+
+	/*
+	 * Link Xenon specific mmc_host_ops function,
+	 * to replace standard ones in sdhci_ops.
+	 */
+	xenon_replace_mmc_host_ops(host);
+
+	pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
+	if (IS_ERR(pltfm_host->clk)) {
+		err = PTR_ERR(pltfm_host->clk);
+		dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
+		goto free_pltfm;
+	}
+	err = clk_prepare_enable(pltfm_host->clk);
+	if (err)
+		goto free_pltfm;
+
+	err = xenon_probe_dt(pdev);
+	if (err)
+		goto err_clk;
+
+	err = xenon_sdhc_probe(host);
+	if (err)
+		goto err_clk;
+
+	err = sdhci_add_host(host);
+	if (err)
+		goto remove_sdhc;
+
+	return 0;
+
+remove_sdhc:
+	xenon_sdhc_remove(host);
+err_clk:
+	clk_disable_unprepare(pltfm_host->clk);
+free_pltfm:
+	sdhci_pltfm_free(pdev);
+	return err;
+}
+
+static int sdhci_xenon_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+	xenon_sdhc_remove(host);
+
+	sdhci_remove_host(host, 0);
+
+	clk_disable_unprepare(pltfm_host->clk);
+
+	sdhci_pltfm_free(pdev);
+
+	return 0;
+}
+
+static const struct of_device_id sdhci_xenon_dt_ids[] = {
+	{ .compatible = "marvell,armada-8k-sdhci",},
+	{ .compatible = "marvell,armada-3700-sdhci",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
+
+static struct platform_driver sdhci_xenon_driver = {
+	.driver	= {
+		.name	= "xenon-sdhci",
+		.of_match_table = sdhci_xenon_dt_ids,
+		.pm = &sdhci_pltfm_pmops,
+	},
+	.probe	= sdhci_xenon_probe,
+	.remove	= sdhci_xenon_remove,
+};
+
+module_platform_driver(sdhci_xenon_driver);
+
+MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
+MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
new file mode 100644
index 000000000000..69de711db9eb
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author:	Hu Ziji <huziji@marvell.com>
+ * Date:	2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+#ifndef SDHCI_XENON_H_
+#define SDHCI_XENON_H_
+
+/* Register Offset of Xenon SDHC self-defined register */
+#define XENON_SYS_CFG_INFO			0x0104
+#define XENON_SLOT_TYPE_SDIO_SHIFT		24
+#define XENON_NR_SUPPORTED_SLOT_MASK		0x7
+
+#define XENON_SYS_OP_CTRL			0x0108
+#define XENON_AUTO_CLKGATE_DISABLE_MASK		BIT(20)
+#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT	8
+#define XENON_SLOT_ENABLE_SHIFT			0
+
+#define XENON_SYS_EXT_OP_CTRL			0x010C
+#define XENON_MASK_CMD_CONFLICT_ERR		BIT(8)
+
+#define XENON_SLOT_EMMC_CTRL			0x0130
+#define XENON_EMMC_VCCQ_MASK			0x3
+#define XENON_EMMC_VCCQ_1_8V			0x1
+#define XENON_EMMC_VCCQ_3_3V			0x3
+
+#define XENON_SLOT_RETUNING_REQ_CTRL		0x0144
+/* retuning compatible */
+#define XENON_RETUNING_COMPATIBLE		0x1
+
+/* Tuning Parameter */
+#define XENON_TMR_RETUN_NO_PRESENT		0xF
+#define XENON_DEF_TUNING_COUNT			0x9
+
+#define XENON_DEFAULT_SDCLK_FREQ		400000
+
+/* Xenon specific Mode Select value */
+#define XENON_CTRL_HS200			0x5
+#define XENON_CTRL_HS400			0x6
+
+/* Indicate Card Type is not clear yet */
+#define XENON_CARD_TYPE_UNKNOWN			0xF
+
+struct sdhci_xenon_priv {
+	unsigned char	tuning_count;
+	/* idx of SDHC */
+	u8		sdhc_id;
+
+	/*
+	 * eMMC/SD/SDIO require different PHY settings or
+	 * voltage control. It's necessary for Xenon driver to
+	 * recognize card type during, or even before initialization.
+	 * However, mmc_host->card is not available yet at that time.
+	 * This field records the card type during init.
+	 * For eMMC, it is updated in dt parse. For SD/SDIO, it is
+	 * updated in xenon_init_card().
+	 *
+	 * It is only valid during initialization after it is updated.
+	 * Do not access this variable in normal transfers after
+	 * initialization completes.
+	 */
+	unsigned int	init_card_type;
+};
+
+#endif
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 05/12] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

From: Hu Ziji <huziji@marvell.com>

Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 197 +++++++-
 1 file changed, 197 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt

diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
new file mode 100644
index 000000000000..a3876d2cc616
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
@@ -0,0 +1,197 @@
+Marvell Xenon SDHCI Controller device tree bindings
+This file documents differences between the core mmc properties
+described by mmc.txt and the properties used by the Xenon implementation.
+
+Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
+Each SDHC is independent and owns independent resources, such as register sets,
+clock and PHY.
+Each SDHC should have an independent device tree node.
+
+Required Properties:
+- compatible: should be one of the following
+  - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
+  Must provide a second register area and marvell,pad-type.
+  - "marvell,armada-8k-sdhci": For controllers on Armada 7K/8K SoC
+
+- clocks:
+  Array of clocks required for SDHC.
+  Require at least input clock for Xenon IP core.
+
+- clock-names:
+  Array of names corresponding to clocks property.
+  The input clock for Xenon IP core should be named as "core".
+
+- reg:
+  * For "marvell,armada-3700-sdhci", two register areas.
+    The first one for Xenon IP register. The second one for the Armada 3700 SoC
+    PHY PAD Voltage Control register.
+    Please follow the examples with compatible "marvell,armada-3700-sdhci"
+    in below.
+    Please also check property marvell,pad-type in below.
+
+  * For other compatible strings, one register area for Xenon IP.
+
+Optional Properties:
+- mmccard:
+  mmccard child node must be provided when current SDHC is for eMMC.
+  Xenon SDHC often can support both SD and eMMC. This child node indicates that
+  current SDHC is for eMMC card. Thus Xenon eMMC specific configuration and
+  operations can be enabled prior to eMMC init sequence.
+  Please refer to Documentation/devicetree/bindings/mmc/mmc-card.txt.
+  This child node should not be set if current Xenon SDHC is for SD/SDIO.
+
+- bus-width:
+  When 8-bit data bus width is in use for eMMC, this property should be
+  explicitly provided and set as 8.
+  It is optional when data bus width is 4-bit or 1-bit.
+
+- mmc-ddr-1_8v:
+  Select this property when eMMC HS DDR is supported on SDHC side.
+
+- mmc-hs400-1_8v:
+  Select this property when eMMC HS400 is supported on SDHC side.
+
+- no-1-8-v:
+  Select this property when 1.8V signaling voltage supply is unavailable.
+  When this property is enabled, both mmc-ddr-1_8v and mmc-hs400-1_8v should be
+  cleared.
+
+- marvell,xenon-sdhc-id:
+  Indicate the corresponding bit index of current SDHC in
+  SDHC System Operation Control Register Bit[7:0].
+  Set/clear the corresponding bit to enable/disable current SDHC.
+  If Xenon IP contains only one SDHC, this property is optional.
+
+- marvell,xenon-phy-type:
+  Xenon support mutilple types of PHYs.
+  To select eMMC 5.1 PHY, set:
+  marvell,xenon-phy-type = "emmc 5.1 phy"
+  eMMC 5.1 PHY is the default choice if this property is not provided.
+  To select eMMC 5.0 PHY, set:
+  marvell,xenon-phy-type = "emmc 5.0 phy"
+
+  All those types of PHYs can support eMMC, SD and SDIO.
+  Please note that this property only presents the type of PHY.
+  It doesn't stand for the entire SDHC type or property.
+  For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only supports
+  eMMC 5.1.
+
+- marvell,xenon-phy-znr:
+  Set PHY ZNR value.
+  Only available for eMMC PHY 5.1 and eMMC PHY 5.0.
+  Valid range = [0:0x1F].
+  ZNR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-zpr:
+  Set PHY ZPR value.
+  Only available for eMMC PHY 5.1 and eMMC PHY 5.0.
+  Valid range = [0:0x1F].
+  ZPR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-nr-success-tun:
+  Set the number of required consecutive successful sampling points used to
+  identify a valid sampling window, in tuning process.
+  Valid range = [1:7].
+  Set as 0x4 by default if this property is not provided.
+
+- marvell,xenon-phy-tun-step-divider:
+  Set the divider for calculating TUN_STEP.
+  Set as 64 by default if this property is not provided.
+
+- marvell,xenon-phy-slow-mode:
+  If this property is selected, transfers will bypass PHY.
+  Only available when bus frequency lower than 55MHz in SDR mde.
+  Disabled by default. Please only try this property if timing issues always
+  occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, SD SDR50 mode.
+
+- marvell,xenon-tun-count:
+  Xenon SDHC SoC usually doesn't provide re-tuning counter in
+  Capabilities Register 3 Bit[11:8].
+  This property provides the re-tuning counter.
+  If this property is not set, default re-tuning counter will
+  be set as 0x9 in driver.
+
+- marvell,pad-type:
+  Type of Armada 3700 SoC PHY PAD Voltage Controller register.
+  Only valid when "marvell,armada-3700-sdhci" is selected.
+  Two types: "sd" and "fixed-1-8v".
+  If "sd" is slected, SoC PHY PAD is set as 3.3V at the beginning and is
+  switched to 1.8V when SD in UHS-I.
+  If "fixed-1-8v" is slected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
+  Please follow the examples with compatible "marvell,armada-3700-sdhci"
+  in below.
+
+Example:
+- For eMMC:
+
+	sdhci at aa0000 {
+		compatible = "marvell,armada-8k-sdhci";
+		reg = <0xaa0000 0x1000>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+		clocks = <&emmc_clk>;
+		clock-names = "core";
+		bus-width = <8>;
+		mmc-ddr-1_8v;
+		mmc-hs400-1_8v;
+		marvell,xenon-sdhc-id = <0>;
+		marvell,xenon-phy-type = "emmc 5.1 phy";
+		marvell,xenon-tun-count = <11>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mmccard: mmccard at 0 {
+			compatible = "mmc-card";
+			reg = <0>;
+		};
+	};
+
+- For SD/SDIO:
+
+	sdhci at ab0000 {
+		compatible = "marvell,armada-8k-sdhci";
+		reg = <0xab0000 0x1000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+		vqmmc-supply = <&sd_regulator>;
+		clocks = <&sdclk>;
+		clock-names = "core";
+		bus-width = <4>;
+		marvell,xenon-tun-count = <9>;
+	};
+
+- For eMMC with compatible "marvell,armada-3700-sdhci":
+
+	sdhci at aa0000 {
+		compatible = "marvell,armada-3700-sdhci";
+		reg = <0xaa0000 0x1000>,
+		      <phy_addr 0x4>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+		clocks = <&emmcclk>;
+		clock-names = "core";
+		bus-width = <8>;
+		mmc-ddr-1_8v;
+		mmc-hs400-1_8v;
+
+		marvell,pad-type = "fixed-1-8v";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mmccard: mmccard at 0 {
+			compatible = "mmc-card";
+			reg = <0>;
+		};
+	};
+
+- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
+
+	sdhci at ab0000 {
+		compatible = "marvell,armada-3700-sdhci";
+		reg = <0xab0000 0x1000>,
+		      <phy_addr 0x4>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+		vqmmc-supply = <&sd_regulator>;
+		clocks = <&sdclk>;
+		clock-names = "core";
+		bus-width = <4>;
+
+		marvell,pad-type = "sd";
+	};
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 04/12] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

From: Hu Ziji <huziji@marvell.com>

Export sdhci_enable_sdio_irq() from sdhci.c.
Thus vendor SDHC driver can implement its specific SDIO irq
control.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci.c | 3 ++-
 drivers/mmc/host/sdhci.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d2338dc362f4..9a4fda81ff81 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1824,7 +1824,7 @@ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
 	}
 }
 
-static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 {
 	struct sdhci_host *host = mmc_priv(mmc);
 	unsigned long flags;
@@ -1838,6 +1838,7 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 	sdhci_enable_sdio_irq_nolock(host, enable);
 	spin_unlock_irqrestore(&host->lock, flags);
 }
+EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
 
 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
 				      struct mmc_ios *ios)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index e4a07543a12b..609783364941 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -694,6 +694,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
 				      struct mmc_ios *ios);
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
 
 #ifdef CONFIG_PM
 extern int sdhci_suspend_host(struct sdhci_host *host);
-- 
git-series 0.9.1

^ permalink raw reply related

* [PATCH v5 03/12] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
From: Gregory CLEMENT @ 2017-01-11 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.8527229dae6c124f24c5e637430c2cdc86f80392.1484154449.git-series.gregory.clement@free-electrons.com>

From: Hu Ziji <huziji@marvell.com>

Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci.c | 5 +++--
 drivers/mmc/host/sdhci.h | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0e9ed0fadff9..d2338dc362f4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1839,8 +1839,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
-					     struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+				      struct mmc_ios *ios)
 {
 	struct sdhci_host *host = mmc_priv(mmc);
 	u16 ctrl;
@@ -1932,6 +1932,7 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
 		return 0;
 	}
 }
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
 
 static int sdhci_card_busy(struct mmc_host *mmc)
 {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 3563c0c384ca..e4a07543a12b 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -692,6 +692,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask);
 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+				      struct mmc_ios *ios);
 
 #ifdef CONFIG_PM
 extern int sdhci_suspend_host(struct sdhci_host *host);
-- 
git-series 0.9.1

^ permalink raw reply related


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